1141 files changed, 29270 insertions, 13151 deletions

diff --git a/arch/alpha/include/asm/Kbuild b/arch/alpha/include/asm/Kbuild
index e858aa0ad8af..25b49725df07 100644
--- a/arch/alpha/include/asm/Kbuild
+++ b/arch/alpha/include/asm/Kbuild
@@ -4,7 +4,9 @@ generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += exec.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
 generic-y += scatterlist.h
+generic-y += sections.h
 generic-y += trace_clock.h
diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h
index 5ebab5895edb..f05bdb4b1cb9 100644
--- a/arch/alpha/include/asm/io.h
+++ b/arch/alpha/include/asm/io.h
@@ -500,10 +500,14 @@ extern inline void writeq(u64 b, volatile void __iomem *addr)
 #define outb_p          outb
 #define outw_p          outw
 #define outl_p          outl
-#define readb_relaxed(addr) __raw_readb(addr)
-#define readw_relaxed(addr) __raw_readw(addr)
-#define readl_relaxed(addr) __raw_readl(addr)
-#define readq_relaxed(addr) __raw_readq(addr)
+#define readb_relaxed(addr)     __raw_readb(addr)
+#define readw_relaxed(addr)     __raw_readw(addr)
+#define readl_relaxed(addr)     __raw_readl(addr)
+#define readq_relaxed(addr)     __raw_readq(addr)
+#define writeb_relaxed(b, addr) __raw_writeb(b, addr)
+#define writew_relaxed(b, addr) __raw_writew(b, addr)
+#define writel_relaxed(b, addr) __raw_writel(b, addr)
+#define writeq_relaxed(b, addr) __raw_writeq(b, addr)
 
 #define mmiowb()
 
diff --git a/arch/alpha/include/asm/sections.h b/arch/alpha/include/asm/sections.h
deleted file mode 100644
index 43b40edd6e44..000000000000
--- a/arch/alpha/include/asm/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _ALPHA_SECTIONS_H
-#define _ALPHA_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h
index f2c94402e2c8..c509d306db45 100644
--- a/arch/alpha/include/asm/unistd.h
+++ b/arch/alpha/include/asm/unistd.h
@@ -3,7 +3,7 @@
 
 #include <uapi/asm/unistd.h>
 
-#define NR_SYSCALLS                     508
+#define NR_SYSCALLS                     511
 
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_STAT64
diff --git a/arch/alpha/include/uapi/asm/ioctls.h b/arch/alpha/include/uapi/asm/ioctls.h
index 92c557be49fc..f30c94ae1bdb 100644
--- a/arch/alpha/include/uapi/asm/ioctls.h
+++ b/arch/alpha/include/uapi/asm/ioctls.h
@@ -90,6 +90,8 @@
 #define TIOCSBRK        0x5427  /* BSD compatibility */
 #define TIOCCBRK        0x5428  /* BSD compatibility */
 #define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TIOCGRS485      _IOR('T', 0x2E, struct serial_rs485)
+#define TIOCSRS485      _IOWR('T', 0x2F, struct serial_rs485)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
 #define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
diff --git a/arch/alpha/include/uapi/asm/unistd.h b/arch/alpha/include/uapi/asm/unistd.h
index 53ae7bb1bfd1..d214a0358100 100644
--- a/arch/alpha/include/uapi/asm/unistd.h
+++ b/arch/alpha/include/uapi/asm/unistd.h
@@ -469,5 +469,8 @@
 #define __NR_process_vm_writev          505
 #define __NR_kcmp                       506
 #define __NR_finit_module               507
+#define __NR_sched_setattr              508
+#define __NR_sched_getattr              509
+#define __NR_renameat2                  510
 
 #endif /* _UAPI_ALPHA_UNISTD_H */
diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S
index dca9b3fb0071..24789713f1ea 100644
--- a/arch/alpha/kernel/systbls.S
+++ b/arch/alpha/kernel/systbls.S
@@ -526,6 +526,9 @@ sys_call_table:
         .quad sys_process_vm_writev             /* 505 */
         .quad sys_kcmp
         .quad sys_finit_module
+        .quad sys_sched_setattr
+        .quad sys_sched_getattr
+        .quad sys_renameat2                     /* 510 */
 
         .size sys_call_table, . - sys_call_table
         .type sys_call_table, @object
diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
index e76fd79f32b0..b8fffc1a2ac2 100644
--- a/arch/arc/include/asm/Kbuild
+++ b/arch/arc/include/asm/Kbuild
@@ -18,6 +18,7 @@ generic-y += ioctl.h
 generic-y += ioctls.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kmap_types.h
 generic-y += kvm_para.h
 generic-y += local.h
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 4670afc3b971..9e1142729fd1 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -427,7 +427,7 @@ struct ic_inv_args {
 
 static void __ic_line_inv_vaddr_helper(void *info)
 {
-        struct ic_inv *ic_inv_args = (struct ic_inv_args *) info;
+        struct ic_inv_args *ic_inv = info;
 
         __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz);
 }
@@ -581,6 +581,7 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
                 tot_sz -= sz;
         }
 }
+EXPORT_SYMBOL(flush_icache_range);
 
 /*
  * General purpose helper to make I and D cache lines consistent.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c49a775937db..18f392f8b744 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -14,6 +14,7 @@ config ARM
         select CLONE_BACKWARDS
         select CPU_PM if (SUSPEND || CPU_IDLE)
         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
+        select GENERIC_ALLOCATOR
         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
         select GENERIC_IDLE_POLL_SETUP
@@ -24,6 +25,7 @@ config ARM
         select GENERIC_SMP_IDLE_THREAD
         select GENERIC_STRNCPY_FROM_USER
         select GENERIC_STRNLEN_USER
+        select HANDLE_DOMAIN_IRQ
         select HARDIRQS_SW_RESEND
         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
@@ -60,6 +62,7 @@ config ARM
         select HAVE_PERF_EVENTS
         select HAVE_PERF_REGS
         select HAVE_PERF_USER_STACK_DUMP
+        select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
         select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_SYSCALL_TRACEPOINTS
         select HAVE_UID16
@@ -387,6 +390,7 @@ config ARCH_CLPS711X
         select CPU_ARM720T
         select GENERIC_CLOCKEVENTS
         select MFD_SYSCON
+        select SOC_BUS
         help
           Support for Cirrus Logic 711x/721x/731x based boards.
 
@@ -650,6 +654,7 @@ config ARCH_SHMOBILE_LEGACY
         select ARCH_SHMOBILE
         select ARM_PATCH_PHYS_VIRT if MMU
         select CLKDEV_LOOKUP
+        select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
@@ -660,6 +665,7 @@ config ARCH_SHMOBILE_LEGACY
         select NO_IOPORT_MAP
         select PINCTRL
         select PM_GENERIC_DOMAINS if PM
+        select SH_CLK_CPG
         select SPARSE_IRQ
         help
           Support for Renesas ARM SoC platforms using a non-multiplatform
@@ -888,6 +894,8 @@ source "arch/arm/mach-keystone/Kconfig"
 
 source "arch/arm/mach-ks8695/Kconfig"
 
+source "arch/arm/mach-meson/Kconfig"
+
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-moxart/Kconfig"
@@ -1405,6 +1413,15 @@ config MCPM
           for (multi-)cluster based systems, such as big.LITTLE based
           systems.
 
+config MCPM_QUAD_CLUSTER
+        bool
+        depends on MCPM
+        help
+          To avoid wasting resources unnecessarily, MCPM only supports up
+          to 2 clusters by default.
+          Platforms with 3 or 4 clusters that use MCPM must select this
+          option to allow the additional clusters to be managed.
+
 config BIG_LITTLE
         bool "big.LITTLE support (Experimental)"
         depends on CPU_V7 && SMP
@@ -1644,6 +1661,10 @@ config ARCH_SELECT_MEMORY_MODEL
 config HAVE_ARCH_PFN_VALID
         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 
+config HAVE_GENERIC_RCU_GUP
+        def_bool y
+        depends on ARM_LPAE
+
 config HIGHMEM
         bool "High Memory Support"
         depends on MMU
@@ -1983,8 +2004,6 @@ config XIP_PHYS_ADDR
 config KEXEC
         bool "Kexec system call (EXPERIMENTAL)"
         depends on (!SMP || PM_SLEEP_SMP)
-        select CRYPTO
-        select CRYPTO_SHA256
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b11ad54f8d17..03dc4c1a8736 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -101,6 +101,10 @@ choice
                 bool "Kernel low-level debugging on 9263 and 9g45"
                 depends on HAVE_AT91_DBGU1
 
+        config AT91_DEBUG_LL_DBGU2
+                bool "Kernel low-level debugging on sama5d4"
+                depends on HAVE_AT91_DBGU2
+
         config DEBUG_BCM2835
                 bool "Kernel low-level debugging on BCM2835 PL011 UART"
                 depends on ARCH_BCM2835
@@ -122,6 +126,11 @@ choice
                   mobile SoCs in the Kona family of chips (e.g. bcm28155,
                   bcm11351, etc...)
 
+        config DEBUG_BCM63XX
+                bool "Kernel low-level debugging on BCM63XX UART"
+                depends on ARCH_BCM_63XX
+                select DEBUG_UART_BCM63XX
+
         config DEBUG_BERLIN_UART
                 bool "Marvell Berlin SoC Debug UART"
                 depends on ARCH_BERLIN
@@ -147,7 +156,7 @@ choice
         config DEBUG_CNS3XXX
                 bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
                 depends on ARCH_CNS3XXX
-                select DEBUG_UART_PL01X
+                select DEBUG_UART_8250
                 help
                   Say Y here if you want the debug print routines to direct
                   their output to the CNS3xxx UART0.
@@ -223,14 +232,6 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on HI3716 UART.
 
-        config DEBUG_HIX5HD2_UART
-                bool "Hisilicon Hix5hd2 Debug UART"
-                depends on ARCH_HIX5HD2
-                select DEBUG_UART_PL01X
-                help
-                  Say Y here if you want kernel low-level debugging support
-                  on Hix5hd2 UART.
-
         config DEBUG_HIGHBANK_UART
                 bool "Kernel low-level debugging messages via Highbank UART"
                 depends on ARCH_HIGHBANK
@@ -239,6 +240,22 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the UART on Highbank based devices.
 
+        config DEBUG_HIP04_UART
+                bool "Hisilicon HiP04 Debug UART"
+                depends on ARCH_HIP04
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on HIP04 UART.
+
+        config DEBUG_HIX5HD2_UART
+                bool "Hisilicon Hix5hd2 Debug UART"
+                depends on ARCH_HIX5HD2
+                select DEBUG_UART_PL01X
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Hix5hd2 UART.
+
         config DEBUG_IMX1_UART
                 bool "i.MX1 Debug UART"
                 depends on SOC_IMX1
@@ -348,6 +365,13 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to UART1 serial port on KEYSTONE2 devices.
 
+        config DEBUG_MESON_UARTAO
+                bool "Kernel low-level debugging via Meson6 UARTAO"
+                depends on ARCH_MESON
+                help
+                  Say Y here if you want kernel low-lever debugging support
+                  on Amlogic Meson6 based platforms on the UARTAO.
+
         config DEBUG_MMP_UART2
                 bool "Kernel low-level debugging message via MMP UART2"
                 depends on ARCH_MMP
@@ -834,6 +858,14 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on Ux500 based platforms.
 
+        config DEBUG_MT6589_UART0
+                bool "Mediatek mt6589 UART0"
+                depends on ARCH_MEDIATEK
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  for Mediatek mt6589 based platforms on UART0.
+
         config DEBUG_VEXPRESS_UART0_DETECT
                 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                 depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -1011,6 +1043,7 @@ config DEBUG_LL_INCLUDE
         string
         default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
         default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
+        default "debug/meson.S" if DEBUG_MESON_UARTAO
         default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
         default "debug/exynos.S" if DEBUG_EXYNOS_UART
         default "debug/efm32.S" if DEBUG_LL_UART_EFM32
@@ -1038,6 +1071,7 @@ config DEBUG_LL_INCLUDE
         default "debug/vf.S" if DEBUG_VF_UART
         default "debug/vt8500.S" if DEBUG_VT8500_UART0
         default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
+        default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX
         default "mach/debug-macro.S"
 
 # Compatibility options for PL01x
@@ -1057,6 +1091,10 @@ config DEBUG_UART_8250
                 ARCH_IOP33X || ARCH_IXP4XX || \
                 ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC
 
+# Compatibility options for BCM63xx
+config DEBUG_UART_BCM63XX
+        def_bool ARCH_BCM_63XX
+
 config DEBUG_UART_PHYS
         hex "Physical base address of debug UART"
         default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
@@ -1068,13 +1106,14 @@ config DEBUG_UART_PHYS
         default 0x02530c00 if DEBUG_KEYSTONE_UART0
         default 0x02531000 if DEBUG_KEYSTONE_UART1
         default 0x03010fe0 if ARCH_RPC
-        default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \
+        default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
                                 DEBUG_VEXPRESS_UART0_CA9
         default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
         default 0x10124000 if DEBUG_RK3X_UART0
         default 0x10126000 if DEBUG_RK3X_UART1
         default 0x101f1000 if ARCH_VERSATILE
         default 0x101fb000 if DEBUG_NOMADIK_UART
+        default 0x11006000 if DEBUG_MT6589_UART0
         default 0x16000000 if ARCH_INTEGRATOR
         default 0x18000300 if DEBUG_BCM_5301X
         default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
@@ -1093,7 +1132,9 @@ config DEBUG_UART_PHYS
                                 DEBUG_S3C2410_UART1)
         default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
                                 DEBUG_S3C2410_UART2)
+        default 0x78000000 if DEBUG_CNS3XXX
         default 0x7c0003f8 if FOOTBRIDGE
+        default 0x78000000 if DEBUG_CNS3XXX
         default 0x80070000 if DEBUG_IMX23_UART
         default 0x80074000 if DEBUG_IMX28_UART
         default 0x80230000 if DEBUG_PICOXCELL_UART
@@ -1106,9 +1147,11 @@ config DEBUG_UART_PHYS
         default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
         default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
         default 0xd0012000 if DEBUG_MVEBU_UART
+        default 0xc81004c0 if DEBUG_MESON_UARTAO
         default 0xd4017000 if DEBUG_MMP_UART2
         default 0xd4018000 if DEBUG_MMP_UART3
         default 0xe0000000 if ARCH_SPEAR13XX
+        default 0xe4007000 if DEBUG_HIP04_UART
         default 0xf0000be0 if ARCH_EBSA110
         default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
         default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
@@ -1122,21 +1165,23 @@ config DEBUG_UART_PHYS
         default 0xffc02000 if DEBUG_SOCFPGA_UART
         default 0xffd82340 if ARCH_IOP13XX
         default 0xfff36000 if DEBUG_HIGHBANK_UART
+        default 0xfffe8600 if DEBUG_UART_BCM63XX
         default 0xfffff700 if ARCH_IOP33X
         depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                 DEBUG_LL_UART_EFM32 || \
-                DEBUG_UART_8250 || DEBUG_UART_PL01X || \
-                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
+                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
+                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
+                DEBUG_UART_BCM63XX
 
 config DEBUG_UART_VIRT
         hex "Virtual base address of debug UART"
         default 0xe0010fe0 if ARCH_RPC
         default 0xe1000000 if DEBUG_MSM_UART
         default 0xf0000be0 if ARCH_EBSA110
-        default 0xf0009000 if DEBUG_CNS3XXX
         default 0xf01fb000 if DEBUG_NOMADIK_UART
         default 0xf0201000 if DEBUG_BCM2835
         default 0xf1000300 if DEBUG_BCM_5301X
+        default 0xf1006000 if DEBUG_MT6589_UART0
         default 0xf11f1000 if ARCH_VERSATILE
         default 0xf1600000 if ARCH_INTEGRATOR
         default 0xf1c28000 if DEBUG_SUNXI_UART0
@@ -1152,16 +1197,20 @@ config DEBUG_UART_VIRT
         default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
                                 DEBUG_S3C2410_UART2)
         default 0xf7fc9000 if DEBUG_BERLIN_UART
+        default 0xf8007000 if DEBUG_HIP04_UART
         default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
         default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
         default 0xfa71e000 if DEBUG_QCOM_UARTDM
+        default 0xfb002000 if DEBUG_CNS3XXX
         default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
         default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
+        default 0xfcfe8600 if DEBUG_UART_BCM63XX
         default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
         default 0xfd000000 if ARCH_SPEAR13XX
         default 0xfd012000 if ARCH_MV78XX0
         default 0xfde12000 if ARCH_DOVE
         default 0xfe012000 if ARCH_ORION5X
+        default 0xf31004c0 if DEBUG_MESON_UARTAO
         default 0xfe017000 if DEBUG_MMP_UART2
         default 0xfe018000 if DEBUG_MMP_UART3
         default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
@@ -1193,8 +1242,9 @@ config DEBUG_UART_VIRT
         default 0xff003000 if DEBUG_U300_UART
         default DEBUG_UART_PHYS if !MMU
         depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
-                DEBUG_UART_8250 || DEBUG_UART_PL01X || \
-                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
+                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
+                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
+                DEBUG_UART_BCM63XX
 
 config DEBUG_UART_8250_SHIFT
         int "Register offset shift for the 8250 debug UART"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0ce9d0f71f2a..dceb0441b1a6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_EBSA110)		+= ebsa110
 machine-$(CONFIG_ARCH_EFM32)            += efm32
 machine-$(CONFIG_ARCH_EP93XX)           += ep93xx
 machine-$(CONFIG_ARCH_EXYNOS)           += exynos
+machine-$(CONFIG_ARCH_FOOTBRIDGE)       += footbridge
 machine-$(CONFIG_ARCH_GEMINI)           += gemini
 machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
 machine-$(CONFIG_ARCH_HISI)             += hisi
@@ -168,6 +169,7 @@ machine-$(CONFIG_ARCH_IXP4XX)		+= ixp4xx
 machine-$(CONFIG_ARCH_KEYSTONE)         += keystone
 machine-$(CONFIG_ARCH_KS8695)           += ks8695
 machine-$(CONFIG_ARCH_LPC32XX)          += lpc32xx
+machine-$(CONFIG_ARCH_MESON)            += meson
 machine-$(CONFIG_ARCH_MMP)              += mmp
 machine-$(CONFIG_ARCH_MOXART)           += moxart
 machine-$(CONFIG_ARCH_MSM)              += msm
@@ -205,7 +207,6 @@ machine-$(CONFIG_ARCH_VEXPRESS)		+= vexpress
 machine-$(CONFIG_ARCH_VT8500)           += vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
-machine-$(CONFIG_FOOTBRIDGE)            += footbridge
 machine-$(CONFIG_PLAT_SPEAR)            += spear
 
 # Platform directory name.  This list is sorted alphanumerically
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index c394e305447c..5761f0039133 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -5,6 +5,8 @@
 # architecture-specific flags and dependencies.
 #
 
+GCOV_PROFILE    := n
+
 LDFLAGS_bootp   :=-p --no-undefined -X \
                  --defsym initrd_phys=$(INITRD_PHYS) \
                  --defsym params_phys=$(PARAMS_PHYS) -T
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 76a50ecae1c3..3ea230aa94b7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -37,6 +37,8 @@ ifeq ($(CONFIG_ARM_VIRT_EXT),y)
 OBJS            += hyp-stub.o
 endif
 
+GCOV_PROFILE            := n
+
 #
 # Architecture dependencies
 #
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3ddeb9..7c80af906897 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,11 +48,14 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d33ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
+# sama5d4
+dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
 
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
+dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
         bcm21664-garnet.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
@@ -90,6 +93,7 @@ dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
 dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
         ecx-2000.dtb
+dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
         integratorcp.dtb
 dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
@@ -144,8 +148,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
         kirkwood-openrd-client.dtb \
         kirkwood-openrd-ultimate.dtb \
         kirkwood-rd88f6192.dtb \
-        kirkwood-rd88f6281-a0.dtb \
-        kirkwood-rd88f6281-a1.dtb \
+        kirkwood-rd88f6281-z0.dtb \
+        kirkwood-rd88f6281-a.dtb \
         kirkwood-rs212.dtb \
         kirkwood-rs409.dtb \
         kirkwood-rs411.dtb \
@@ -159,8 +163,11 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
         kirkwood-ts419-6282.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
+dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
+        imx1-ads.dtb \
+        imx1-apf9328.dtb \
         imx25-eukrea-mbimxsd25-baseboard.dtb \
         imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
         imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
@@ -199,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6dl-gw52xx.dtb \
         imx6dl-gw53xx.dtb \
         imx6dl-gw54xx.dtb \
+        imx6dl-gw552x.dtb \
         imx6dl-hummingboard.dtb \
         imx6dl-nitrogen6x.dtb \
         imx6dl-phytec-pbab01.dtb \
@@ -223,6 +231,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6q-gw53xx.dtb \
         imx6q-gw5400-a.dtb \
         imx6q-gw54xx.dtb \
+        imx6q-gw552x.dtb \
+        imx6q-hummingboard.dtb \
         imx6q-nitrogen6x.dtb \
         imx6q-phytec-pbab01.dtb \
         imx6q-rex-pro.dtb \
@@ -240,7 +250,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6q-tx6q-1110.dtb \
         imx6sl-evk.dtb \
         imx6sx-sdb.dtb \
-        vf610-colibri.dtb \
+        vf610-colibri-eval-v3.dtb \
         vf610-cosmic.dtb \
         vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
@@ -286,7 +296,11 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
         omap3-devkit8000.dtb \
         omap3-evm.dtb \
         omap3-evm-37xx.dtb \
-        omap3-gta04.dtb \
+        omap3-gta04a3.dtb \
+        omap3-gta04a4.dtb \
+        omap3-gta04a5.dtb \
+        omap3-ha.dtb \
+        omap3-ha-lcd.dtb \
         omap3-igep0020.dtb \
         omap3-igep0030.dtb \
         omap3-ldp.dtb \
@@ -309,6 +323,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
         omap3-sbc-t3517.dtb \
         omap3-sbc-t3530.dtb \
         omap3-sbc-t3730.dtb \
+        omap3-thunder.dtb \
         omap3-zoom3.dtb
 dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
         am335x-bone.dtb \
@@ -341,7 +356,9 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_QCOM) += \
         qcom-apq8064-ifc6410.dtb \
         qcom-apq8074-dragonboard.dtb \
+        qcom-apq8084-ifc6540.dtb \
         qcom-apq8084-mtp.dtb \
+        qcom-ipq8064-ap148.dtb \
         qcom-msm8660-surf.dtb \
         qcom-msm8960-cdp.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
@@ -361,7 +378,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
         r8a7740-armadillo800eva.dtb \
         r8a7778-bockw.dtb \
         r8a7778-bockw-reference.dtb \
-        r8a7740-armadillo800eva-reference.dtb \
         r8a7779-marzen.dtb \
         r8a7791-koelsch.dtb \
         r8a7790-lager.dtb \
@@ -372,10 +388,12 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
         sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
         r7s72100-genmai.dtb \
+        r8a7740-armadillo800eva.dtb \
         r8a7791-henninger.dtb \
         r8a7791-koelsch.dtb \
         r8a7790-lager.dtb \
-        r8a7779-marzen.dtb
+        r8a7779-marzen.dtb \
+        r8a7794-alt.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
         socfpga_cyclone5_socdk.dtb \
         socfpga_cyclone5_sockit.dtb \
@@ -406,6 +424,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
 dtb-$(CONFIG_MACH_SUN5I) += \
         sun5i-a10s-olinuxino-micro.dtb \
         sun5i-a10s-r7-tv-dongle.dtb \
+        sun5i-a13-hsg-h702.dtb \
         sun5i-a13-olinuxino.dtb \
         sun5i-a13-olinuxino-micro.dtb
 dtb-$(CONFIG_MACH_SUN6I) += \
@@ -416,7 +435,9 @@ dtb-$(CONFIG_MACH_SUN6I) += \
 dtb-$(CONFIG_MACH_SUN7I) += \
         sun7i-a20-cubieboard2.dtb \
         sun7i-a20-cubietruck.dtb \
+        sun7i-a20-hummingbird.dtb \
         sun7i-a20-i12-tvbox.dtb \
+        sun7i-a20-olinuxino-lime.dtb \
         sun7i-a20-olinuxino-micro.dtb \
         sun7i-a20-pcduino3.dtb
 dtb-$(CONFIG_MACH_SUN8I) += \
@@ -440,6 +461,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra114-roth.dtb \
         tegra114-tn7.dtb \
         tegra124-jetson-tk1.dtb \
+        tegra124-nyan-big.dtb \
         tegra124-venice2.dtb
 dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
@@ -491,6 +513,7 @@ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
         dove-d2plug.dtb \
         dove-d3plug.dtb \
         dove-dove-db.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb
 
 targets += dtbs dtbs_install
 targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index bde1777b62be..6cc25ed912ee 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -7,9 +7,6 @@
  */
 
 / {
-        model = "TI AM335x BeagleBone";
-        compatible = "ti,am335x-bone", "ti,am33xx";
-
         cpus {
                 cpu@0 {
                         cpu0-supply = <&dcdc2_reg>;
@@ -227,6 +224,7 @@
 &tps {
         regulators {
                 dcdc1_reg: regulator@0 {
+                        regulator-name = "vdds_dpr";
                         regulator-always-on;
                 };
 
@@ -249,18 +247,22 @@
                 };
 
                 ldo1_reg: regulator@3 {
+                        regulator-name = "vio,vrtc,vdds";
                         regulator-always-on;
                 };
 
                 ldo2_reg: regulator@4 {
+                        regulator-name = "vdd_3v3aux";
                         regulator-always-on;
                 };
 
                 ldo3_reg: regulator@5 {
+                        regulator-name = "vdd_1v8";
                         regulator-always-on;
                 };
 
                 ldo4_reg: regulator@6 {
+                        regulator-name = "vdd_3v3a";
                         regulator-always-on;
                 };
         };
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 94ee427a6db1..83d40f7655e5 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -10,6 +10,11 @@
 #include "am33xx.dtsi"
 #include "am335x-bone-common.dtsi"
 
+/ {
+        model = "TI AM335x BeagleBone";
+        compatible = "ti,am335x-bone", "ti,am33xx";
+};
+
 &ldo3_reg {
         regulator-min-microvolt = <1800000>;
         regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 305975d3f531..901739fcb85a 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -10,6 +10,11 @@
 #include "am33xx.dtsi"
 #include "am335x-bone-common.dtsi"
 
+/ {
+        model = "TI AM335x BeagleBone Black";
+        compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+};
+
 &ldo3_reg {
         regulator-min-microvolt = <1800000>;
         regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 3a0a161342ba..831810583823 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -132,11 +132,15 @@
                         };
                 };
 
+                cm: syscon@44e10000 {
+                        compatible = "ti,am33xx-controlmodule", "syscon";
+                        reg = <0x44e10000 0x800>;
+                };
+
                 intc: interrupt-controller@48200000 {
-                        compatible = "ti,omap2-intc";
+                        compatible = "ti,am33xx-intc";
                         interrupt-controller;
                         #interrupt-cells = <1>;
-                        ti,intc-size = <128>;
                         reg = <0x48200000 0x1000>;
                 };
 
@@ -354,6 +358,10 @@
                         ti,hwmods = "mailbox";
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <8>;
+                        mbox_wkupm3: wkup_m3 {
+                                ti,mbox-tx = <0 0 0>;
+                                ti,mbox-rx = <0 0 3>;
+                        };
                 };
 
                 timer1: timer@44e31000 {
@@ -696,6 +704,7 @@
                          */
                         interrupts = <40 41 42 43>;
                         ranges;
+                        syscon = <&cm>;
                         status = "disabled";
 
                         davinci_mdio: mdio@4a101000 {
@@ -726,9 +735,8 @@
                 };
 
                 ocmcram: ocmcram@40300000 {
-                        compatible = "ti,am3352-ocmcram";
-                        reg = <0x40300000 0x10000>;
-                        ti,hwmods = "ocmcram";
+                        compatible = "mmio-sram";
+                        reg = <0x40300000 0x10000>; /* 64k */
                 };
 
                 wkup_m3: wkup_m3@44d00000 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 9b3d2ba82f13..46660ffd2b65 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -58,10 +58,12 @@
         };
 
         am43xx_pinmux: pinmux@44e10800 {
-                compatible = "pinctrl-single";
+                compatible = "ti,am437-padconf", "pinctrl-single";
                 reg = <0x44e10800 0x31c>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
                 pinctrl-single,register-width = <32>;
                 pinctrl-single,function-mask = <0xffffffff>;
         };
@@ -168,6 +170,10 @@
                         ti,hwmods = "mailbox";
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <8>;
+                        mbox_wkupm3: wkup_m3 {
+                                ti,mbox-tx = <0 0 0>;
+                                ti,mbox-rx = <0 0 3>;
+                        };
                 };
 
                 timer1: timer@44e31000 {
@@ -804,7 +810,7 @@
 
                         usb1: usb@48390000 {
                                 compatible = "synopsys,dwc3";
-                                reg = <0x48390000 0x17000>;
+                                reg = <0x48390000 0x10000>;
                                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
                                 phys = <&usb2_phy1>;
                                 phy-names = "usb2-phy";
@@ -826,7 +832,7 @@
 
                         usb2: usb@483d0000 {
                                 compatible = "synopsys,dwc3";
-                                reg = <0x483d0000 0x17000>;
+                                reg = <0x483d0000 0x10000>;
                                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                                 phys = <&usb2_phy2>;
                                 phy-names = "usb2-phy";
@@ -885,6 +891,11 @@
                                 clock-names = "fck";
                         };
                 };
+
+                ocmcram: ocmcram@40300000 {
+                        compatible = "mmio-sram";
+                        reg = <0x40300000 0x40000>; /* 256k */
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 646a6eade788..e7ac47fa6615 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -260,7 +260,7 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&i2c0_pins>;
-        clock-frequency = <400000>;
+        clock-frequency = <100000>;
 
         tps65218: tps65218@24 {
                 reg = <0x24>;
@@ -424,7 +424,7 @@
         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
         nand@0,0 {
                 reg = <0 0 4>;          /* device IO registers */
-                ti,nand-ecc-opt = "bch8";
+                ti,nand-ecc-opt = "bch16";
                 ti,elm-id = <&elm>;
                 nand-bus-width = <8>;
                 gpmc,device-width = <1>;
@@ -443,8 +443,6 @@
                 gpmc,rd-cycle-ns = <40>;
                 gpmc,wr-cycle-ns = <40>;
                 gpmc,wait-pin = <0>;
-                gpmc,wait-on-read;
-                gpmc,wait-on-write;
                 gpmc,bus-turnaround-ns = <0>;
                 gpmc,cycle2cycle-delay-ns = <0>;
                 gpmc,clk-activation-ns = <0>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index ed7dd2395915..ac3e4859935f 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -435,13 +435,13 @@
 };
 
 &gpmc {
-        status = "okay";
+        status = "okay";        /* Disable QSPI when enabling GPMC (NAND) */
         pinctrl-names = "default";
         pinctrl-0 = <&nand_flash_x8>;
         ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
         nand@0,0 {
                 reg = <0 0 0>; /* CS0, offset 0 */
-                ti,nand-ecc-opt = "bch8";
+                ti,nand-ecc-opt = "bch16";
                 ti,elm-id = <&elm>;
                 nand-bus-width = <8>;
                 gpmc,device-width = <1>;
@@ -459,8 +459,7 @@
                 gpmc,access-ns = <30>; /* tCEA + 4*/
                 gpmc,rd-cycle-ns = <40>;
                 gpmc,wr-cycle-ns = <40>;
-                gpmc,wait-on-read = "true";
-                gpmc,wait-on-write = "true";
+                gpmc,wait-pin = <0>;
                 gpmc,bus-turnaround-ns = <0>;
                 gpmc,cycle2cycle-delay-ns = <0>;
                 gpmc,clk-activation-ns = <0>;
@@ -557,7 +556,7 @@
 };
 
 &qspi {
-        status = "okay";
+        status = "disabled";    /* Disable GPMC (NAND) when enabling QSPI */
         pinctrl-names = "default";
         pinctrl-0 = <&qspi1_default>;
 
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 416f4e5a69c1..a495e5821ab8 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -43,6 +43,8 @@
                         };
 
                         mdio {
+                                pinctrl-0 = <&mdio_pins>;
+                                pinctrl-names = "default";
                                 phy0: ethernet-phy@0 {
                                         reg = <0>;
                                 };
@@ -53,11 +55,15 @@
                         };
 
                         ethernet@70000 {
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy0>;
                                 phy-mode = "rgmii-id";
                         };
                         ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy1>;
                                 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 097df7d8f0f6..2b6d24e0d1e8 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -91,6 +91,8 @@
                         };
 
                         mdio {
+                                pinctrl-0 = <&mdio_pins>;
+                                pinctrl-names = "default";
                                 phy0: ethernet-phy@0 {
                                         reg = <0>;
                                 };
@@ -100,11 +102,15 @@
                                 };
                         };
                         ethernet@70000 {
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy0>;
                                 phy-mode = "rgmii-id";
                         };
                         ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy1>;
                                 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index d6d572e5af32..3aebd93cc33c 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -101,12 +101,16 @@
                         };
 
                         mdio {
+                                pinctrl-0 = <&mdio_pins>;
+                                pinctrl-names = "default";
                                 phy0: ethernet-phy@0 { /* Marvell 88E1318 */
                                         reg = <0>;
                                 };
                         };
 
                         ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy0>;
                                 phy-mode = "rgmii-id";
@@ -122,7 +126,7 @@
                                 status = "okay";
 
                                 isl12057: isl12057@68 {
-                                        compatible = "isl,isl12057";
+                                        compatible = "isil,isl12057";
                                         reg = <0x68>;
                                 };
 
@@ -143,6 +147,10 @@
                                 marvell,nand-enable-arbiter;
                                 nand-on-flash-bbt;
 
+                                /* Use Hardware BCH ECC */
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
+
                                 partition@0 {
                                         label = "u-boot";
                                         reg = <0x0000000 0x180000>;  /* 1.5MB */
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index c5fe8b5dcdc7..c2f414bb9aba 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -86,6 +86,8 @@
                         };
 
                         mdio {
+                                pinctrl-0 = <&mdio_pins>;
+                                pinctrl-names = "default";
                                 phy0: ethernet-phy@0 { /* Marvell 88E1318 */
                                         reg = <0>;
                                 };
@@ -96,12 +98,16 @@
                         };
 
                         ethernet@70000 {
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy0>;
                                 phy-mode = "rgmii-id";
                         };
 
                         ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy1>;
                                 phy-mode = "rgmii-id";
@@ -117,7 +123,7 @@
                                 status = "okay";
 
                                 isl12057: isl12057@68 {
-                                        compatible = "isl,isl12057";
+                                        compatible = "isil,isl12057";
                                         reg = <0x68>;
                                 };
 
@@ -145,6 +151,10 @@
                                 marvell,nand-enable-arbiter;
                                 nand-on-flash-bbt;
 
+                                /* Use Hardware BCH ECC */
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
+
                                 partition@0 {
                                         label = "u-boot";
                                         reg = <0x0000000 0x180000>;  /* 1.5MB */
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 4169f4096ea3..f57a8f841498 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -9,6 +9,15 @@
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
  */
 
 /dts-v1/;
@@ -30,7 +39,7 @@
         };
 
         soc {
-                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
                           MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
 
                 pcie-controller {
@@ -50,6 +59,18 @@
                 };
 
                 internal-regs {
+                        pinctrl {
+                                fan_pins: fan-pins {
+                                        marvell,pins = "mpp8";
+                                        marvell,function = "gpio";
+                                };
+
+                                led_pins: led-pins {
+                                        marvell,pins = "mpp32";
+                                        marvell,function = "gpio";
+                                };
+                        };
+
                         serial@12000 {
                                 status = "okay";
                         };
@@ -59,6 +80,8 @@
                         };
 
                         mdio {
+                                pinctrl-0 = <&mdio_pins>;
+                                pinctrl-names = "default";
                                 phy0: ethernet-phy@0 {
                                         reg = <0>;
                                 };
@@ -74,6 +97,8 @@
                                 phy-mode = "sgmii";
                         };
                         ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy1>;
                                 phy-mode = "rgmii-id";
@@ -106,6 +131,26 @@
                                 };
                         };
 
+                        gpio-fan {
+                                compatible = "gpio-fan";
+                                gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+                                gpio-fan,speed-map = <0 0 3000 1>;
+                                pinctrl-0 = <&fan_pins>;
+                                pinctrl-names = "default";
+                        };
+
+                        gpio_leds {
+                                compatible = "gpio-leds";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&led_pins>;
+
+                                sw_led {
+                                        label = "370rd:green:sw";
+                                        gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+                                        default-state = "keep";
+                                };
+                        };
+
                         nand@d0000 {
                                 status = "okay";
                                 num-cs = <1>;
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 23227e0027ec..83286ec9702c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -110,7 +110,7 @@
                         };
 
                         spi0: spi@10600 {
-                                compatible = "marvell,orion-spi";
+                                compatible = "marvell,armada-370-spi", "marvell,orion-spi";
                                 reg = <0x10600 0x28>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -121,7 +121,7 @@
                         };
 
                         spi1: spi@10680 {
-                                compatible = "marvell,orion-spi";
+                                compatible = "marvell,armada-370-spi", "marvell,orion-spi";
                                 reg = <0x10680 0x28>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 21b588b6f6bd..6b3c23b1e138 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -151,6 +151,25 @@
                                                        "mpp62", "mpp60", "mpp58";
                                         marvell,function = "audio";
                                 };
+
+                                mdio_pins: mdio-pins {
+                                        marvell,pins = "mpp17", "mpp18";
+                                        marvell,function = "ge";
+                                };
+
+                                ge0_rgmii_pins: ge0-rgmii-pins {
+                                        marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
+                                                       "mpp9", "mpp10", "mpp11", "mpp12",
+                                                       "mpp13", "mpp14", "mpp15", "mpp16";
+                                        marvell,function = "ge0";
+                                };
+
+                                ge1_rgmii_pins: ge1-rgmii-pins {
+                                        marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
+                                                       "mpp23", "mpp24", "mpp25", "mpp26",
+                                                       "mpp27", "mpp28", "mpp29", "mpp30";
+                                        marvell,function = "ge1";
+                                };
                         };
 
                         gpio0: gpio@18100 {
@@ -206,6 +225,10 @@
                                 status = "okay";
                         };
 
+                        sscg@18330 {
+                                reg = <0x18330 0x4>;
+                        };
+
                         interrupt-controller@20000 {
                                 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
                         };
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index c1e49e7bf0fa..de6571445cef 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -185,6 +185,12 @@
                                 };
                         };
 
+                        rtc@10300 {
+                                compatible = "marvell,orion-rtc";
+                                reg = <0x10300 0x20>;
+                                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
                         spi0: spi@10600 {
                                 compatible = "marvell,orion-spi";
                                 reg = <0x10600 0x50>;
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 0cf999abc4ed..7d8f32873e82 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -174,7 +174,7 @@
                                 status = "okay";
 
                                 isl12057: isl12057@68 {
-                                        compatible = "isl,isl12057";
+                                        compatible = "isil,isl12057";
                                         reg = <0x68>;
                                 };
 
@@ -223,6 +223,10 @@
                                 marvell,nand-enable-arbiter;
                                 nand-on-flash-bbt;
 
+                                /* Use Hardware BCH ECC */
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
+
                                 partition@0 {
                                         label = "u-boot";
                                         reg = <0x0000000 0x180000>;  /* 1.5MB */
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index 000000000000..b5b84006469e
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,260 @@
+/*
+ * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ *  Copyright (C) 2014 Atmel,
+ *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+        model = "Atmel SAMA5D4-EK";
+        compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
+        };
+
+        memory {
+                reg = <0x20000000 0x20000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+
+                slow_xtal {
+                        clock-frequency = <32768>;
+                };
+
+                main_xtal {
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        lcd_bus@f0000000 {
+                                status = "okay";
+
+                                lcd@f0000000 {
+                                        status = "okay";
+                                };
+
+                                lcdovl1@f0000140 {
+                                        status = "okay";
+                                };
+
+                                lcdovl2@f0000240 {
+                                        status = "okay";
+                                };
+
+                                lcdheo1@f0000340 {
+                                        status = "okay";
+                                };
+                        };
+
+                        adc0: adc@fc034000 {
+                                /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
+                                atmel,adc-vref = <3300>;
+                                /*atmel,adc-ts-wires = <4>;*/   /* Set up ADC touch screen */
+                                status = "okay";                /* Enable ADC IIO support */
+                        };
+
+                        mmc0: mmc@f8000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioE 5 0>;
+                                };
+                        };
+
+                        spi0: spi@f8010000 {
+                                cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
+                                status = "okay";
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
+
+                        i2c0: i2c@f8014000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f8020000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        mmc1: mmc@fc000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioE 6 0>;
+                                };
+                        };
+
+                        usart2: serial@fc008000 {
+                                status = "okay";
+                        };
+
+                        usart3: serial@fc00c000 {
+                                status = "okay";
+                        };
+
+                        usart4: serial@fc010000 {
+                                status = "okay";
+                        };
+
+                        watchdog@fc068640 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fc06a000 {
+                                board {
+                                        pinctrl_mmc0_cd: mmc0_cd {
+                                                atmel,pins =
+                                                        <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                        pinctrl_mmc1_cd: mmc1_cd {
+                                                atmel,pins =
+                                                        <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                        pinctrl_usba_vbus: usba_vbus {
+                                                atmel,pins =
+                                                        <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+                                        };
+                                        pinctrl_key_gpio: key_gpio_0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
+                                        };
+                                };
+                        };
+                };
+
+                usb0: gadget@00400000 {
+                        atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usba_vbus>;
+                        status = "okay";
+                };
+
+                usb1: ohci@00500000 {
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
+                                           &pioE 11 GPIO_ACTIVE_LOW
+                                           &pioE 12 GPIO_ACTIVE_LOW
+                                          >;
+                        status = "okay";
+                };
+
+                usb2: ehci@00600000 {
+                        status = "okay";
+                };
+
+                nand0: nand@80000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        nand-on-flash-bbt;
+                        atmel,has-pmecc;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_key_gpio>;
+
+                pb_user1 {
+                        label = "pb_user1";
+                        gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 65ccf564b9a5..6c97d4af61ee 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -149,7 +149,7 @@
                                 usb: usbck {
                                         compatible = "atmel,at91rm9200-clk-usb";
                                         #clock-cells = <0>;
-                                        atmel,clk-divisors = <1 2>;
+                                        atmel,clk-divisors = <1 2 0 0>;
                                         clocks = <&pllb>;
                                 };
 
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index bb23c2d33cf8..d68b3c4862bc 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -345,10 +345,14 @@
                                 };
                         };
 
-                        ramc: ramc@ffffe200 {
+                        ramc0: ramc@ffffe200 {
                                 compatible = "atmel,at91sam9260-sdramc";
-                                reg = <0xffffe200 0x200
-                                       0xffffe800 0x200>;
+                                reg = <0xffffe200 0x200>;
+                        };
+
+                        ramc1: ramc@ffffe800 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffe800 0x200>;
                         };
 
                         pit: timer@fffffd30 {
@@ -834,6 +838,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff80000 0x600>;
                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 clocks = <&mci0_clk>;
@@ -845,6 +850,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff84000 0x600>;
                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 clocks = <&mci1_clk>;
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 31f7652612fc..a50ee587a7af 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -22,6 +22,10 @@
                                 compatible = "atmel,at91sam9g20-i2c";
                         };
 
+                        ssc0: ssc@fffbc000 {
+                                compatible = "atmel,at91sam9rl-ssc";
+                        };
+
                         adc0: adc@fffe0000 {
                                 atmel,adc-startup-time = <40>;
                         };
@@ -40,6 +44,7 @@
                                 };
 
                                 pllb: pllbck {
+                                        compatible = "atmel,at91sam9g20-clk-pllb";
                                         atmel,clk-input-range = <2000000 32000000>;
                                         atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
                                 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 932a669156af..d3f65130a1f8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -96,8 +96,14 @@
 
                         ramc0: ramc@ffffe400 {
                                 compatible = "atmel,at91sam9g45-ddramc";
-                                reg = <0xffffe400 0x200
-                                       0xffffe600 0x200>;
+                                reg = <0xffffe400 0x200>;
+                                clocks = <&ddrck>;
+                                clock-names = "ddrck";
+                        };
+
+                        ramc1: ramc@ffffe600 {
+                                compatible = "atmel,at91sam9g45-ddramc";
+                                reg = <0xffffe600 0x200>;
                                 clocks = <&ddrck>;
                                 clock-names = "ddrck";
                         };
@@ -159,7 +165,7 @@
                                         compatible = "atmel,at91rm9200-clk-master";
                                         #clock-cells = <0>;
                                         interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
-                                        clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
                                         atmel,clk-output-range = <0 133333333>;
                                         atmel,clk-divisors = <1 2 4 3>;
                                 };
@@ -175,7 +181,7 @@
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         interrupt-parent = <&pmc>;
-                                        clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 
                                         prog0: prog0 {
                                                 #clock-cells = <0>;
@@ -1159,6 +1165,39 @@
                                         atmel,can-isoc;
                                 };
                         };
+
+                        sckc@fffffd50 {
+                                compatible = "atmel,at91sam9x5-sckc";
+                                reg = <0xfffffd50 0x4>;
+
+                                slow_osc: slow_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                        #clock-cells = <0>;
+                                        atmel,startup-time-usec = <1200000>;
+                                        clocks = <&slow_xtal>;
+                                };
+
+                                slow_rc_osc: slow_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                        #clock-cells = <0>;
+                                        atmel,startup-time-usec = <75>;
+                                        clock-frequency = <32768>;
+                                        clock-accuracy = <50000000>;
+                                };
+
+                                clk32k: slck {
+                                        compatible = "atmel,at91sam9x5-clk-slow";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_rc_osc &slow_osc>;
+                                };
+                        };
+
+                        rtc@fffffdb0 {
+                                compatible = "atmel,at91rm9200-rtc";
+                                reg = <0xfffffdb0 0x30>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                status = "disabled";
+                        };
                 };
 
                 fb0: fb@0x00500000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 96ccc7de4f0a..d8dd22651090 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -160,6 +160,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_pwm_leds>;
                         };
+
+                        rtc@fffffdb0 {
+                                status = "okay";
+                        };
                 };
 
                 fb0: fb@0x00500000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 2bfac310dbec..68eb9aded164 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -87,6 +87,8 @@
                         ramc0: ramc@ffffe800 {
                                 compatible = "atmel,at91sam9g45-ddramc";
                                 reg = <0xffffe800 0x200>;
+                                clocks = <&ddrck>;
+                                clock-names = "ddrck";
                         };
 
                         pmc: pmc@fffffc00 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 83d723711ae1..13bb24ea971a 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -136,6 +136,8 @@
                 };
 
                 usb0: ohci@00500000 {
+                        num-ports = <1>;
+                        atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index ab56c8b81dfa..f0b4352650ed 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -204,7 +204,7 @@
                         };
 
                         ssc0: ssc@fffc0000 {
-                                compatible = "atmel,at91rm9200-ssc";
+                                compatible = "atmel,at91sam9rl-ssc";
                                 reg = <0xfffc0000 0x4000>;
                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
@@ -213,7 +213,7 @@
                         };
 
                         ssc1: ssc@fffc4000 {
-                                compatible = "atmel,at91rm9200-ssc";
+                                compatible = "atmel,at91sam9rl-ssc";
                                 reg = <0xfffc4000 0x4000>;
                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e1a5c70b885c..726274f7959b 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -95,6 +95,8 @@
                         ramc0: ramc@ffffe800 {
                                 compatible = "atmel,at91sam9g45-ddramc";
                                 reg = <0xffffe800 0x200>;
+                                clocks = <&ddrck>;
+                                clock-names = "ddrck";
                         };
 
                         pmc: pmc@fffffc00 {
@@ -966,7 +968,7 @@
                         adc0: adc@f804c000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                compatible = "atmel,at91sam9260-adc";
+                                compatible = "atmel,at91sam9x5-adc";
                                 reg = <0xf804c000 0x100>;
                                 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
                                 clocks = <&adc_clk>,
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 2a3b1c1313a0..58a0d60b95f1 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -23,7 +23,7 @@
 
 &gpio {
         pinctrl-names = "default";
-        pinctrl-0 = <&gpioout &alt0 &alt3>;
+        pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
 
         gpioout: gpioout {
                 brcm,pins = <6>;
@@ -39,6 +39,12 @@
                 brcm,pins = <48 49 50 51 52 53>;
                 brcm,function = <7>; /* alt3 */
         };
+
+        /* I2S interface */
+        alt2: alt2 {
+                brcm,pins = <28 29 30 31>;
+                brcm,function = <6>; /* alt2 */
+        };
 };
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index b8473c43e888..3342cb1407bc 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -99,6 +99,7 @@
                         dmas = <&dma 2>,
                                <&dma 3>;
                         dma-names = "tx", "rx";
+                        status = "disabled";
                 };
 
                 spi: spi@7e204000 {
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
new file mode 100644
index 000000000000..f3bb2dd6269e
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Broadcom BCM63138 DSL SoCs Device Tree
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+        compatible = "brcm,bcm63138";
+        model = "Broadcom BCM63138 DSL SoC";
+        interrupt-parent = <&gic>;
+
+        aliases {
+                uart0 = &serial0;
+                uart1 = &serial1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                arm_timer_clk: arm_timer_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <500000000>;
+                };
+
+                periph_clk: periph_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <50000000>;
+                        clock-output-names = "periph";
+                };
+        };
+
+        /* ARM bus */
+        axi@80000000 {
+                compatible = "simple-bus";
+                ranges = <0 0x80000000 0x784000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                L2: cache-controller@1d000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x1d000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                        cache-sets = <16>;
+                        cache-size = <0x80000>;
+                        interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                scu: scu@1e000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0x1e000 0x100>;
+                };
+
+                gic: interrupt-controller@1e100 {
+                        compatible = "arm,cortex-a9-gic";
+                        reg = <0x1f000 0x1000
+                                0x1e100 0x100>;
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                };
+
+                global_timer: timer@1e200 {
+                        compatible = "arm,cortex-a9-global-timer";
+                        reg = <0x1e200 0x20>;
+                        interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&arm_timer_clk>;
+                };
+
+                local_timer: local-timer@1e600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x1e600 0x20>;
+                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&arm_timer_clk>;
+                };
+
+                twd_watchdog: watchdog@1e620 {
+                        compatible = "arm,cortex-a9-twd-wdt";
+                        reg = <0x1e620 0x20>;
+                        interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                };
+        };
+
+        /* Legacy UBUS base */
+        ubus@fffe8000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0xfffe8000 0x8100>;
+
+                serial0: serial@600 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x600 0x1b>;
+                        interrupts = <GIC_SPI 32 0>;
+                        clocks = <&periph_clk>;
+                        clock-names = "periph";
+                        status = "disabled";
+                };
+
+                serial1: serial@620 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x620 0x1b>;
+                        interrupts = <GIC_SPI 33 0>;
+                        clocks = <&periph_clk>;
+                        clock-names = "periph";
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
new file mode 100644
index 000000000000..69c93395ecd2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -0,0 +1,30 @@
+/*
+ * Broadcom BCM63138 Reference Board DTS
+ */
+
+/dts-v1/;
+
+#include "bcm63138.dtsi"
+
+/ {
+        compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
+        model = "Broadcom BCM963138DVT";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &serial0;
+        };
+
+        memory {
+                reg = <0x0 0x08000000>;
+        };
+
+};
+
+&serial0 {
+        status = "okay";
+};
+
+&serial1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index a357ce02a64e..ea1f99b8eed6 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -45,3 +45,7 @@
 &uart0 {
         status = "okay";
 };
+
+&eth0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 400c40fceccc..891d56b03922 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -114,6 +114,23 @@
                         #interrupt-cells = <3>;
                 };
 
+                eth0: ethernet@b90000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xb90000 0x10000>;
+                        clocks = <&chip CLKID_GETH0>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-handle = <&ethphy0>;
+                        status = "disabled";
+
+                        ethphy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+
                 cpu-ctrl@dd0000 {
                         compatible = "marvell,berlin-cpu-ctrl";
                         reg = <0xdd0000 0x10000>;
diff --git a/arch/arm/boot/dts/cros-adc-thermistors.dtsi b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
new file mode 100644
index 000000000000..acd4fe1833f2
--- /dev/null
+++ b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Thermistor dts fragment for devices that use Thermistors as
+ * children of the IIO based ADC.
+ *
+ * Currently, used by Exynos5420 based Peach PIT and
+ * Exynos5800 based Peach PI.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&adc {
+        ncp15wb473@3 {
+                compatible = "murata,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <47000>;
+                pulldown-ohm = <0>;
+                io-channels = <&adc 3>;
+        };
+        ncp15wb473@4 {
+                compatible = "murata,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <47000>;
+                pulldown-ohm = <0>;
+                io-channels = <&adc 4>;
+        };
+        ncp15wb473@5 {
+                compatible = "murata,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <47000>;
+                pulldown-ohm = <0>;
+                io-channels = <&adc 5>;
+        };
+        ncp15wb473@6 {
+                compatible = "murata,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <47000>;
+                pulldown-ohm = <0>;
+                io-channels = <&adc 6>;
+        };
+};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 1e11e5a5f723..4f935ad9f27b 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -17,6 +17,18 @@
         soc {
                 pmx_core: pinmux@1c14120 {
                         status = "okay";
+
+                        mcasp0_pins: pinmux_mcasp0_pins {
+                                pinctrl-single,bits = <
+                                        /*
+                                         * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
+                                         * AFSR, AMUTE
+                                         */
+                                        0x00 0x11111111 0xffffffff
+                                        /* AXR11, AXR12 */
+                                        0x04 0x00011000 0x000ff000
+                                >;
+                        };
                 };
                 serial0: serial@1c42000 {
                         status = "okay";
@@ -39,6 +51,20 @@
                         tps: tps@48 {
                                 reg = <0x48>;
                         };
+                        tlv320aic3106: tlv320aic3106@18 {
+                                #sound-dai-cells = <0>;
+                                compatible = "ti,tlv320aic3106";
+                                reg = <0x18>;
+                                status = "okay";
+
+                                /* Regulators */
+                                IOVDD-supply = <&vdcdc2_reg>;
+                                /* Derived from VBAT: Baseboard 3.3V / 1.8V */
+                                AVDD-supply = <&vbat>;
+                                DRVDD-supply = <&vbat>;
+                                DVDD-supply = <&vbat>;
+                        };
+
                 };
                 wdt: wdt@1c21000 {
                         status = "okay";
@@ -117,6 +143,33 @@
                 regulator-max-microvolt = <5000000>;
                 regulator-boot-on;
         };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "DA850/OMAP-L138 EVM";
+                simple-audio-card,widgets =
+                        "Line", "Line In",
+                        "Line", "Line Out";
+                simple-audio-card,routing =
+                        "LINE1L", "Line In",
+                        "LINE1R", "Line In",
+                        "Line Out", "LLOUT",
+                        "Line Out", "RLOUT";
+                simple-audio-card,format = "dsp_b";
+                simple-audio-card,bitclock-master = <&link0_codec>;
+                simple-audio-card,frame-master = <&link0_codec>;
+                simple-audio-card,bitclock-inversion;
+
+                simple-audio-card,cpu {
+                        sound-dai = <&mcasp0>;
+                        system-clock-frequency = <24576000>;
+                };
+
+                link0_codec: simple-audio-card,codec {
+                        sound-dai = <&tlv320aic3106>;
+                        system-clock-frequency = <24576000>;
+                };
+        };
 };
 
 /include/ "tps6507x.dtsi"
@@ -170,3 +223,22 @@
                 };
         };
 };
+
+&mcasp0 {
+        #sound-dai-cells = <0>;
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcasp0_pins>;
+
+        op-mode = <0>;          /* MCASP_IIS_MODE */
+        tdm-slots = <2>;
+        /* 4 serializer */
+        serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+                0 0 0 0
+                0 0 0 0
+                0 0 0 1
+                2 0 0 0
+        >;
+        tx-num-evt = <32>;
+        rx-num-evt = <32>;
+};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index b695548dbb4e..0bd98cd00816 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -150,6 +150,12 @@
                         };
 
                 };
+                edma0: edma@01c00000 {
+                        compatible = "ti,edma3";
+                        reg =   <0x0 0x10000>;
+                        interrupts = <11 13 12>;
+                        #dma-cells = <1>;
+                };
                 serial0: serial@1c42000 {
                         compatible = "ns16550a";
                         reg = <0x42000 0x100>;
@@ -270,6 +276,19 @@
                         ti,davinci-gpio-unbanked = <0>;
                         status = "disabled";
                 };
+
+                mcasp0: mcasp@01d00000 {
+                        compatible = "ti,da830-mcasp-audio";
+                        reg = <0x100000 0x2000>,
+                              <0x102000 0x400000>;
+                        reg-names = "mpu", "dat";
+                        interrupts = <54>;
+                        interrupt-names = "common";
+                        status = "disabled";
+                        dmas = <&edma0 1>,
+                                <&edma0 0>;
+                        dma-names = "tx", "rx";
+                };
         };
         nand_cs3@62000000 {
                 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022905a1..c6ce6258434f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "TI DRA742";
@@ -24,9 +25,29 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
         };
+
+        vtt_fixed: fixedregulator-vtt {
+                compatible = "regulator-fixed";
+                regulator-name = "vtt_fixed";
+                regulator-min-microvolt = <1350000>;
+                regulator-max-microvolt = <1350000>;
+                regulator-always-on;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+        };
 };
 
 &dra7_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <&vtt_pin>;
+
+        vtt_pin: pinmux_vtt_pin {
+                pinctrl-single,pins = <
+                        0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
+                >;
+        };
+
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
@@ -43,20 +64,19 @@
 
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
-                        0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
-                        0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
+                        0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
+                        0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
                 >;
         };
 
         mcspi1_pins: pinmux_mcspi1_pins {
                 pinctrl-single,pins = <
-                        0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
-                        0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
-                        0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
-                        0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
-                        0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
-                        0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
-                        0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
+                        0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
+                        0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
+                        0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
+                        0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
+                        0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
+                        0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
                 >;
         };
 
@@ -284,7 +304,7 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&i2c3_pins>;
-        clock-frequency = <3400000>;
+        clock-frequency = <400000>;
 };
 
 &mcspi1 {
@@ -303,6 +323,8 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&uart1_pins>;
+        interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+                              <&dra7_pmx_core 0x3e0>;
 };
 
 &uart2 {
@@ -427,22 +449,19 @@
                 gpmc,device-width = <2>;
                 gpmc,sync-clk-ps = <0>;
                 gpmc,cs-on-ns = <0>;
-                gpmc,cs-rd-off-ns = <40>;
-                gpmc,cs-wr-off-ns = <40>;
+                gpmc,cs-rd-off-ns = <80>;
+                gpmc,cs-wr-off-ns = <80>;
                 gpmc,adv-on-ns = <0>;
-                gpmc,adv-rd-off-ns = <30>;
-                gpmc,adv-wr-off-ns = <30>;
-                gpmc,we-on-ns = <5>;
-                gpmc,we-off-ns = <25>;
-                gpmc,oe-on-ns = <2>;
-                gpmc,oe-off-ns = <20>;
-                gpmc,access-ns = <20>;
-                gpmc,wr-access-ns = <40>;
-                gpmc,rd-cycle-ns = <40>;
-                gpmc,wr-cycle-ns = <40>;
-                gpmc,wait-pin = <0>;
-                gpmc,wait-on-read;
-                gpmc,wait-on-write;
+                gpmc,adv-rd-off-ns = <60>;
+                gpmc,adv-wr-off-ns = <60>;
+                gpmc,we-on-ns = <10>;
+                gpmc,we-off-ns = <50>;
+                gpmc,oe-on-ns = <4>;
+                gpmc,oe-off-ns = <40>;
+                gpmc,access-ns = <40>;
+                gpmc,wr-access-ns = <80>;
+                gpmc,rd-cycle-ns = <80>;
+                gpmc,wr-cycle-ns = <80>;
                 gpmc,bus-turnaround-ns = <0>;
                 gpmc,cycle2cycle-delay-ns = <0>;
                 gpmc,clk-activation-ns = <0>;
@@ -483,7 +502,7 @@
                         reg = <0x001c0000 0x00020000>;
                 };
                 partition@7 {
-                        label = "NAND.u-boot-env";
+                        label = "NAND.u-boot-env.backup1";
                         reg = <0x001e0000 0x00020000>;
                 };
                 partition@8 {
@@ -504,3 +523,8 @@
 &usb2_phy2 {
         phy-supply = <&ldousb_reg>;
 };
+
+&gpio7 {
+        ti,no-reset-on-init;
+        ti,no-idle-on-init;
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 97f603c4483d..9cc98436a982 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -89,6 +89,7 @@
                 prm: prm@4ae06000 {
                         compatible = "ti,dra7-prm";
                         reg = <0x4ae06000 0x3000>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 
                         prm_clocks: clocks {
                                 #address-cells = <1>;
@@ -217,10 +218,12 @@
                 };
 
                 dra7_pmx_core: pinmux@4a003400 {
-                        compatible = "pinctrl-single";
+                        compatible = "ti,dra7-padconf", "pinctrl-single";
                         reg = <0x4a003400 0x0464>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
                         pinctrl-single,register-width = <32>;
                         pinctrl-single,function-mask = <0x3fffffff>;
                 };
@@ -245,7 +248,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 gpio2: gpio@48055000 {
@@ -256,7 +259,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 gpio3: gpio@48057000 {
@@ -267,7 +270,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 gpio4: gpio@48059000 {
@@ -278,7 +281,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 gpio5: gpio@4805b000 {
@@ -289,7 +292,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 gpio6: gpio@4805d000 {
@@ -300,7 +303,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 gpio7: gpio@48051000 {
@@ -311,7 +314,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 gpio8: gpio@48053000 {
@@ -322,13 +325,13 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <2>;
                 };
 
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -337,7 +340,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -346,7 +349,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -355,7 +358,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -364,7 +367,7 @@
                 uart5: serial@48066000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48066000 0x100>;
-                        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -373,7 +376,7 @@
                 uart6: serial@48068000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48068000 0x100>;
-                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -382,7 +385,7 @@
                 uart7: serial@48420000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48420000 0x100>;
-                        interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart7";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -391,7 +394,7 @@
                 uart8: serial@48422000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48422000 0x100>;
-                        interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart8";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -400,7 +403,7 @@
                 uart9: serial@48424000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48424000 0x100>;
-                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart9";
                         clock-frequency = <48000000>;
                         status = "disabled";
@@ -409,7 +412,7 @@
                 uart10: serial@4ae2b000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4ae2b000 0x100>;
-                        interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart10";
                         clock-frequency = <48000000>;
                         status = "disabled";
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 514702348818..41074288adfa 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -19,6 +19,126 @@
         };
 };
 
+&dra7_pmx_core {
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+                        0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+                >;
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        clock-frequency = <400000>;
+
+        tps65917: tps65917@58 {
+                compatible = "ti,tps65917";
+                reg = <0x58>;
+
+                interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
+                interrupt-parent = <&gic>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
+                ti,system-power-controller;
+
+                tps65917_pmic {
+                        compatible = "ti,tps65917-pmic";
+
+                        regulators {
+                                smps1_reg: smps1 {
+                                        /* VDD_MPU */
+                                        regulator-name = "smps1";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1250000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps2_reg: smps2 {
+                                        /* VDD_CORE */
+                                        regulator-name = "smps2";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1030000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                smps3_reg: smps3 {
+                                        /* VDD_GPU IVA DSPEVE */
+                                        regulator-name = "smps3";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1250000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                smps4_reg: smps4 {
+                                        /* VDDS1V8 */
+                                        regulator-name = "smps4";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps5_reg: smps5 {
+                                        /* VDD_DDR */
+                                        regulator-name = "smps5";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo1_reg: ldo1 {
+                                        /* LDO1_OUT --> SDIO  */
+                                        regulator-name = "ldo1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                };
+
+                                ldo2_reg: ldo2 {
+                                        /* LDO2_OUT --> TP1017 (UNUSED)  */
+                                        regulator-name = "ldo2";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo3_reg: ldo3 {
+                                        /* VDDA_1V8_PHY */
+                                        regulator-name = "ldo3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo5_reg: ldo5 {
+                                        /* VDDA_1V8_PLL */
+                                        regulator-name = "ldo5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo4_reg: ldo4 {
+                                        /* VDDA_3V_USB: VDDA_USBHS33 */
+                                        regulator-name = "ldo4";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index f1ec22f6ebf4..e5a3d23a3df1 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -22,4 +22,9 @@
                         reg = <0>;
                 };
         };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
+        };
 };
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index a4e8bb9f95c0..3be544c4891f 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -38,4 +38,10 @@
                         reg = <1>;
                 };
         };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 6d6d23c83d30..c697ff01ae8d 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -54,17 +54,13 @@
                 status = "okay";
 
                 num-slots = <1>;
-                supports-highspeed;
                 broken-cd;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
+                bus-width = <8>;
+                cap-mmc-highspeed;
         };
 
         watchdog@10060000 {
@@ -134,6 +130,8 @@
         i2c@13860000 {
                 pinctrl-0 = <&i2c0_bus>;
                 pinctrl-names = "default";
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <400000>;
                 status = "okay";
 
                 usb3503: usb3503@08 {
@@ -148,6 +146,10 @@
 
                 max77686: pmic@09 {
                         compatible = "maxim,max77686";
+                        interrupt-parent = <&gpx3>;
+                        interrupts = <2 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&max77686_irq>;
                         reg = <0x09>;
                         #clock-cells = <1>;
 
@@ -368,4 +370,11 @@
                 samsung,pins = "gpx1-3";
                 samsung,pin-pud = <0>;
         };
+
+        max77686_irq: max77686-irq {
+                samsung,pins = "gpx3-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9fbfb07..de15114fd07c 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
                 status = "okay";
 
                 num-slots = <1>;
-                supports-highspeed;
                 broken-cd;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
+                bus-width = <8>;
+                cap-mmc-highspeed;
         };
 
         codec@13400000 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4561e0..5e066cd87f66 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
 
         mmc@12550000 {
                 num-slots = <1>;
-                supports-highspeed;
                 broken-cd;
                 non-removable;
                 card-detect-delay = <200>;
@@ -532,11 +531,8 @@
                 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                 pinctrl-names = "default";
                 status = "okay";
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
+                bus-width = <8>;
+                cap-mmc-highspeed;
         };
 
         serial@13800000 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f50d15b..3acd97eb6630 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
         mmc_0: mmc@12200000 {
                 status = "okay";
                 num-slots = <1>;
-                supports-highspeed;
                 broken-cd;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
@@ -410,17 +409,13 @@
                 vmmc-supply = <&mmc_reg>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
+                bus-width = <8>;
+                cap-mmc-highspeed;
         };
 
         mmc_2: mmc@12220000 {
                 status = "okay";
                 num-slots = <1>;
-                supports-highspeed;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -428,12 +423,9 @@
                 vmmc-supply = <&mmc_reg>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <4>;
-                        disable-wp;
-                };
+                bus-width = <4>;
+                disable-wp;
+                cap-sd-highspeed;
         };
 
         i2s0: i2s@03830000 {
@@ -570,8 +562,4 @@
                         connect-gpios = <&gpd1 7 1>;
                 };
         };
-
-        usb@12110000 {
-                usb-phy = <&usb2_phy>;
-        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
deleted file mode 100644
index e603e9c70142..000000000000
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Common device tree include for all Exynos 5250 boards based off of Daisy.
- *
- * Copyright (c) 2012 Google, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/ {
-        aliases {
-        };
-
-        memory {
-                reg = <0x40000000 0x80000000>;
-        };
-
-        chosen {
-        };
-
-        pinctrl@11400000 {
-                /*
-                 * Disabled pullups since external part has its own pullups and
-                 * double-pulling gets us out of spec in some cases.
-                 */
-                i2c2_bus: i2c2-bus {
-                        samsung,pin-pud = <0>;
-                };
-        };
-
-        i2c@12C60000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <378000>;
-        };
-
-        i2c@12C70000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <378000>;
-        };
-
-        i2c@12C80000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-
-                hdmiddc@50 {
-                        compatible = "samsung,exynos4210-hdmiddc";
-                        reg = <0x50>;
-                };
-        };
-
-        i2c@12C90000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-        };
-
-        i2c@12CA0000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-        };
-
-        i2c@12CB0000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-        };
-
-        i2c@12CD0000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-        };
-
-        i2c@12CE0000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <378000>;
-
-                hdmiphy: hdmiphy@38 {
-                        compatible = "samsung,exynos4212-hdmiphy";
-                        reg = <0x38>;
-                };
-        };
-
-        mmc@12200000 {
-                num-slots = <1>;
-                supports-highspeed;
-                broken-cd;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
-        };
-
-        mmc@12220000 {
-                num-slots = <1>;
-                supports-highspeed;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <4>;
-                        wp-gpios = <&gpc2 1 0>;
-                };
-        };
-
-        mmc@12230000 {
-                num-slots = <1>;
-                supports-highspeed;
-                broken-cd;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                /* See board-specific dts files for pin setup */
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <4>;
-                };
-        };
-
-        spi_1: spi@12d30000 {
-                status = "okay";
-                samsung,spi-src-clk = <0>;
-                num-cs = <1>;
-        };
-
-        hdmi {
-                hpd-gpio = <&gpx3 7 0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&hdmi_hpd_irq>;
-                phy = <&hdmiphy>;
-                ddc = <&i2c_2>;
-        };
-
-        gpio-keys {
-                compatible = "gpio-keys";
-
-                power {
-                        label = "Power";
-                        gpios = <&gpx1 3 1>;
-                        linux,code = <116>; /* KEY_POWER */
-                        gpio-key,wakeup;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35adae565..6a0f4c0ff763 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -284,7 +284,6 @@
         mmc@12200000 {
                 status = "okay";
                 num-slots = <1>;
-                supports-highspeed;
                 broken-cd;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
@@ -292,29 +291,22 @@
                 samsung,dw-mshc-ddr-timing = <1 2>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
+                bus-width = <8>;
+                cap-mmc-highspeed;
         };
 
         mmc@12220000 {
                 status = "okay";
                 num-slots = <1>;
-                supports-highspeed;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <4>;
-                        disable-wp;
-                };
+                bus-width = <4>;
+                disable-wp;
+                cap-sd-highspeed;
         };
 
         spi_1: spi@12d30000 {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c4116541..e51fcef884a4 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
 */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "exynos5250.dtsi"
-#include "exynos5250-cros-common.dtsi"
 
 / {
         model = "Google Snow";
@@ -20,6 +20,13 @@
                 i2c104 = &i2c_104;
         };
 
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+        };
+
         rtc@101E0000 {
                 status = "okay";
         };
@@ -93,6 +100,13 @@
         gpio-keys {
                 compatible = "gpio-keys";
 
+                power {
+                        label = "Power";
+                        gpios = <&gpx1 3 1>;
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+
                 lid-switch {
                         label = "Lid";
                         gpios = <&gpx3 5 1>;
@@ -181,7 +195,7 @@
                                         dcdc3 {
                                                 ti,enable-ext-control;
                                         };
-                                        fet1 {
+                                        fet1: fet1 {
                                                 regulator-name = "vcd_led";
                                                 ti,overcurrent-wait = <3>;
                                         };
@@ -204,7 +218,7 @@
                                                 regulator-always-on;
                                                 ti,overcurrent-wait = <3>;
                                         };
-                                        fet6 {
+                                        fet6: fet6 {
                                                 regulator-name = "lcd_vdd";
                                                 ti,overcurrent-wait = <3>;
                                         };
@@ -226,26 +240,6 @@
                 };
         };
 
-        mmc@12200000 {
-                status = "okay";
-        };
-
-        mmc@12220000 {
-                status = "okay";
-        };
-
-        /*
-         * On Snow we've got SIP WiFi and so can keep drive strengths low to
-         * reduce EMI.
-         */
-        mmc@12230000 {
-                status = "okay";
-                slot@0 {
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
-                };
-        };
-
         i2c@12CD0000 {
                 max98095: codec@11 {
                         compatible = "maxim,max98095";
@@ -253,6 +247,15 @@
                         pinctrl-0 = <&max98095_en>;
                         pinctrl-names = "default";
                 };
+
+                ptn3460: lvds-bridge@20 {
+                        compatible = "nxp,ptn3460";
+                        reg = <0x20>;
+                        powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
+                        reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
+                        edid-emulation = <5>;
+                        panel = <&panel>;
+                };
         };
 
         i2s0: i2s@03830000 {
@@ -294,17 +297,24 @@
         };
 
         hdmi {
+                hpd-gpio = <&gpx3 7 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&hdmi_hpd_irq>;
+                phy = <&hdmiphy>;
+                ddc = <&i2c_2>;
                 hdmi-en-supply = <&tps65090_fet7>;
                 vdd-supply = <&ldo8_reg>;
                 vdd_osc-supply = <&ldo10_reg>;
                 vdd_pll-supply = <&ldo8_reg>;
         };
 
-        backlight {
+        backlight: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm 0 1000000 0>;
                 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
                 default-brightness-level = <7>;
+                enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
+                power-supply = <&fet1>;
                 pinctrl-0 = <&pwm0_out>;
                 pinctrl-names = "default";
         };
@@ -314,6 +324,12 @@
                 samsung,invert-vclk;
         };
 
+        panel: panel {
+                compatible = "auo,b116xw03";
+                power-supply = <&fet6>;
+                backlight = <&backlight>;
+        };
+
         dp-controller@145B0000 {
                 status = "okay";
                 pinctrl-names = "default";
@@ -325,26 +341,15 @@
                 samsung,link-rate = <0x0a>;
                 samsung,lane-count = <2>;
                 samsung,hpd-gpio = <&gpx0 7 0>;
-
-                display-timings {
-                        native-mode = <&timing1>;
-
-                        timing1: timing@1 {
-                                clock-frequency = <70589280>;
-                                hactive = <1366>;
-                                vactive = <768>;
-                                hfront-porch = <40>;
-                                hback-porch = <40>;
-                                hsync-len = <32>;
-                                vback-porch = <10>;
-                                vfront-porch = <12>;
-                                vsync-len = <6>;
-                        };
-                };
+                bridge = <&ptn3460>;
         };
 };
 
 &i2c_0 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+
         max77686@09 {
                 compatible = "maxim,max77686";
                 interrupt-parent = <&gpx3>;
@@ -491,6 +496,10 @@
 };
 
 &i2c_1 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+
         trackpad {
                 reg = <0x67>;
                 compatible = "cypress,cyapa";
@@ -500,6 +509,106 @@
         };
 };
 
+/*
+ * Disabled pullups since external part has its own pullups and
+ * double-pulling gets us out of spec in some cases.
+ */
+&i2c2_bus {
+        samsung,pin-pud = <0>;
+};
+
+&i2c_2 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+
+        hdmiddc@50 {
+                compatible = "samsung,exynos4210-hdmiddc";
+                reg = <0x50>;
+        };
+};
+
+&i2c_3 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_4 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_5 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_7 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_8 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+
+        hdmiphy: hdmiphy@38 {
+                compatible = "samsung,exynos4212-hdmiphy";
+                reg = <0x38>;
+        };
+};
+
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+};
+
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        bus-width = <4>;
+        wp-gpios = <&gpc2 1 0>;
+        cap-sd-highspeed;
+};
+
+/*
+ * On Snow we've got SIP WiFi and so can keep drive strengths low to
+ * reduce EMI.
+ */
+&mmc_3 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
+        bus-width = <4>;
+        cap-sd-highspeed;
+};
+
 &pinctrl_0 {
         max77686_irq: max77686-irq {
                 samsung,pins = "gpx3-2";
@@ -509,4 +618,10 @@
         };
 };
 
+&spi_1 {
+        status = "okay";
+        samsung,spi-src-clk = <0>;
+        num-cs = <1>;
+};
+
 #include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1eff37bd..f21b9aa00fbb 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -603,21 +603,6 @@
                 };
         };
 
-        usb2_phy: usbphy@12130000 {
-                compatible = "samsung,exynos5250-usb2phy";
-                reg = <0x12130000 0x100>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
-                clock-names = "ext_xtal", "usbhost";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                usbphy-sys {
-                        reg = <0x10040704 0x8>,
-                              <0x10050230 0x4>;
-                };
-        };
-
         usb2_phy_gen: phy@12130000 {
                 compatible = "samsung,exynos5250-usb2-phy";
                 reg = <0x12130000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 8c84ab27c19b..a803b605051b 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -69,7 +69,7 @@
         num-slots = <1>;
         broken-cd;
         bypass-smu;
-        supports-highspeed;
+        cap-mmc-highspeed;
         supports-hs200-mode; /* 200 Mhz */
         card-detect-delay = <200>;
         samsung,dw-mshc-ciu-div = <3>;
@@ -77,27 +77,19 @@
         samsung,dw-mshc-ddr-timing = <0 2>;
         pinctrl-names = "default";
         pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <8>;
-        };
+        bus-width = <8>;
 };
 
 &mmc_2 {
         status = "okay";
         num-slots = <1>;
-        supports-highspeed;
+        cap-sd-highspeed;
         card-detect-delay = <200>;
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <2 3>;
         samsung,dw-mshc-ddr-timing = <1 2>;
         pinctrl-names = "default";
         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-                disable-wp;
-        };
+        bus-width = <4>;
+        disable-wp;
 };
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 7275bbd6fc4b..be3e02530b42 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -40,33 +40,25 @@
 &mmc_0 {
         status = "okay";
         num-slots = <1>;
-        supports-highspeed;
+        cap-mmc-highspeed;
         broken-cd;
         card-detect-delay = <200>;
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <2 3>;
         samsung,dw-mshc-ddr-timing = <1 2>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <8>;
-        };
+        bus-width = <8>;
 };
 
 &mmc_2 {
         status = "okay";
         num-slots = <1>;
-        supports-highspeed;
+        cap-sd-highspeed;
         card-detect-delay = <200>;
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <2 3>;
         samsung,dw-mshc-ddr-timing = <1 2>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-                disable-wp;
-        };
+        bus-width = <4>;
+        disable-wp;
 };
 
 &uart0 {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 434fd9d3e09d..70a559cf1a3d 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -50,7 +50,6 @@
         mmc@12200000 {
                 status = "okay";
                 broken-cd;
-                supports-highspeed;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <0 4>;
@@ -58,16 +57,12 @@
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
                 vmmc-supply = <&ldo10_reg>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
+                bus-width = <8>;
+                cap-mmc-highspeed;
         };
 
         mmc@12220000 {
                 status = "okay";
-                supports-highspeed;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -75,11 +70,8 @@
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
                 vmmc-supply = <&ldo10_reg>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <4>;
-                };
+                bus-width = <4>;
+                cap-sd-highspeed;
         };
 
         hsi2c_4: i2c@12CA0000 {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 228a6b1e0aa1..9a233828539c 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "exynos5420.dtsi"
 
 / {
@@ -30,11 +31,12 @@
                 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
         };
 
-        backlight {
+        backlight: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm 0 1000000 0>;
                 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
                 default-brightness-level = <7>;
+                power-supply = <&tps65090_fet1>;
                 pinctrl-0 = <&pwm0_out>;
                 pinctrl-names = "default";
         };
@@ -100,6 +102,17 @@
                 regulator-boot-on;
                 regulator-always-on;
         };
+
+        panel: panel {
+                compatible = "auo,b116xw03";
+                power-supply = <&tps65090_fet6>;
+                backlight = <&backlight>;
+        };
+};
+
+&adc {
+        status = "okay";
+        vdd-supply = <&ldo9_reg>;
 };
 
 &dp {
@@ -113,22 +126,7 @@
         samsung,link-rate = <0x06>;
         samsung,lane-count = <2>;
         samsung,hpd-gpio = <&gpx2 6 0>;
-
-        display-timings {
-                native-mode = <&timing1>;
-
-                timing1: timing@1 {
-                        clock-frequency = <70589280>;
-                        hactive = <1366>;
-                        vactive = <768>;
-                        hfront-porch = <40>;
-                        hback-porch = <40>;
-                        hsync-len = <32>;
-                        vback-porch = <10>;
-                        vfront-porch = <12>;
-                        vsync-len = <6>;
-                };
-        };
+        bridge = <&ps8625>;
 };
 
 &fimd {
@@ -142,10 +140,348 @@
         pinctrl-names = "default";
         pinctrl-0 = <&hdmi_hpd_irq>;
         ddc = <&i2c_2>;
+
+        hdmi-en-supply = <&tps65090_fet7>;
+        vdd-supply = <&ldo8_reg>;
+        vdd_osc-supply = <&ldo10_reg>;
+        vdd_pll-supply = <&ldo8_reg>;
+};
+
+&hsi2c_4 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        max77802-pmic@9 {
+                compatible = "maxim,max77802";
+                interrupt-parent = <&gpx3>;
+                interrupts = <1 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
+                            <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
+                wakeup-source;
+                reg = <0x9>;
+                #clock-cells = <1>;
+
+                inb1-supply = <&tps65090_dcdc2>;
+                inb2-supply = <&tps65090_dcdc1>;
+                inb3-supply = <&tps65090_dcdc2>;
+                inb4-supply = <&tps65090_dcdc2>;
+                inb5-supply = <&tps65090_dcdc1>;
+                inb6-supply = <&tps65090_dcdc2>;
+                inb7-supply = <&tps65090_dcdc1>;
+                inb8-supply = <&tps65090_dcdc1>;
+                inb9-supply = <&tps65090_dcdc1>;
+                inb10-supply = <&tps65090_dcdc1>;
+
+                inl1-supply = <&buck5_reg>;
+                inl2-supply = <&buck7_reg>;
+                inl3-supply = <&buck9_reg>;
+                inl4-supply = <&buck9_reg>;
+                inl5-supply = <&buck9_reg>;
+                inl6-supply = <&tps65090_dcdc2>;
+                inl7-supply = <&buck9_reg>;
+                inl9-supply = <&tps65090_dcdc2>;
+                inl10-supply = <&buck7_reg>;
+
+                regulators {
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <700000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "vdd_1v2";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck6_reg: BUCK6 {
+                                regulator-name = "vdd_kfc";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck7_reg: BUCK7 {
+                                regulator-name = "vdd_1v35";
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck8_reg: BUCK8 {
+                                regulator-name = "vdd_emmc";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck9_reg: BUCK9 {
+                                regulator-name = "vdd_2v";
+                                regulator-min-microvolt = <2000000>;
+                                regulator-max-microvolt = <2000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck10_reg: BUCK10 {
+                                regulator-name = "vdd_1v8";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        ldo1_reg: LDO1 {
+                                regulator-name = "vdd_1v0";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo2_reg: LDO2 {
+                                regulator-name = "vdd_1v2_2";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo3_reg: LDO3 {
+                                regulator-name = "vdd_1v8_3";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        vqmmc_sdcard: ldo4_reg: LDO4 {
+                                regulator-name = "vdd_sd";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "vdd_1v8_5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "vdd_1v8_6";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo7_reg: LDO7 {
+                                regulator-name = "vdd_1v8_7";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "vdd_ldo8";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo9_reg: LDO9 {
+                                regulator-name = "vdd_ldo9";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "vdd_ldo10";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "vdd_ldo11";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "vdd_ldo12";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "vdd_ldo13";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "vdd_ldo14";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "vdd_ldo15";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "vdd_g3ds";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                        };
+
+                        ldo18_reg: LDO18 {
+                                regulator-name = "ldo_18";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo19_reg: LDO19 {
+                                regulator-name = "ldo_19";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo20_reg: LDO20 {
+                                regulator-name = "ldo_20";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo21_reg: LDO21 {
+                                regulator-name = "ldo_21";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "ldo_23";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        ldo24_reg: LDO24 {
+                                regulator-name = "ldo_24";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "ldo_25";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        ldo26_reg: LDO26 {
+                                regulator-name = "ldo_26";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo27_reg: LDO27 {
+                                regulator-name = "ldo_27";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo28_reg: LDO28 {
+                                regulator-name = "ldo_28";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo29_reg: LDO29 {
+                                regulator-name = "ldo_29";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo30_reg: LDO30 {
+                                regulator-name = "vdd_mifs";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo32_reg: LDO32 {
+                                regulator-name = "ldo_32";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+
+                        ldo33_reg: LDO33 {
+                                regulator-name = "ldo_33";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        ldo34_reg: LDO34 {
+                                regulator-name = "ldo_34";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+
+                        ldo35_reg: LDO35 {
+                                regulator-name = "ldo_35";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+                };
+        };
 };
 
 &hsi2c_7 {
         status = "okay";
+        clock-frequency = <400000>;
 
         max98090: codec@10 {
                 compatible = "maxim,max98090";
@@ -155,6 +491,44 @@
                 pinctrl-names = "default";
                 pinctrl-0 = <&max98090_irq>;
         };
+
+        light-sensor@44 {
+                compatible = "isil,isl29018";
+                reg = <0x44>;
+                vcc-supply = <&tps65090_fet5>;
+        };
+
+        ps8625: lvds-bridge@48 {
+                compatible = "parade,ps8625";
+                reg = <0x48>;
+                sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+                reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
+                lane-count = <2>;
+                panel = <&panel>;
+                use-external-pwm;
+        };
+};
+
+&hsi2c_8 {
+        status = "okay";
+        clock-frequency = <333000>;
+
+        /* Atmel mXT336S */
+        trackpad@4b {
+                compatible = "atmel,maxtouch";
+                reg = <0x4b>;
+                interrupt-parent = <&gpx1>;
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                wakeup-source;
+                pinctrl-names = "default";
+                pinctrl-0 = <&trackpad_irq>;
+                linux,gpio-keymap = <KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED       /* GPIO0 */
+                                     KEY_RESERVED       /* GPIO1 */
+                                     KEY_RESERVED       /* GPIO2 */
+                                     BTN_LEFT>;         /* GPIO3 */
+        };
 };
 
 &hsi2c_9 {
@@ -187,7 +561,7 @@
         num-slots = <1>;
         broken-cd;
         caps2-mmc-hs200-1_8v;
-        supports-highspeed;
+        cap-mmc-highspeed;
         non-removable;
         card-detect-delay = <200>;
         clock-frequency = <400000000>;
@@ -196,17 +570,13 @@
         samsung,dw-mshc-ddr-timing = <0 2>;
         pinctrl-names = "default";
         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <8>;
-        };
+        bus-width = <8>;
 };
 
 &mmc_2 {
         status = "okay";
         num-slots = <1>;
-        supports-highspeed;
+        cap-sd-highspeed;
         card-detect-delay = <200>;
         clock-frequency = <400000000>;
         samsung,dw-mshc-ciu-div = <3>;
@@ -214,11 +584,7 @@
         samsung,dw-mshc-ddr-timing = <1 2>;
         pinctrl-names = "default";
         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-        };
+        bus-width = <4>;
 };
 
 
@@ -249,6 +615,13 @@
                 samsung,pin-drv = <0>;
         };
 
+        trackpad_irq: trackpad-irq {
+                samsung,pins = "gpx1-1";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         power_key_irq: power-key-irq {
                 samsung,pins = "gpx1-2";
                 samsung,pin-function = <0>;
@@ -277,12 +650,42 @@
                 samsung,pin-drv = <0>;
         };
 
+        max77802_irq: max77802-irq {
+                samsung,pins = "gpx3-1";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         hdmi_hpd_irq: hdmi-hpd-irq {
                 samsung,pins = "gpx3-7";
                 samsung,pin-function = <0>;
                 samsung,pin-pud = <1>;
                 samsung,pin-drv = <0>;
         };
+
+        pmic_dvs_1: pmic-dvs-1 {
+                samsung,pins = "gpy7-6";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&pinctrl_2 {
+        pmic_dvs_2: pmic-dvs-2 {
+                samsung,pins = "gpj4-2";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pmic_dvs_3: pmic-dvs-3 {
+                samsung,pins = "gpj4-3";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
 };
 
 &pinctrl_3 {
@@ -312,6 +715,14 @@
                 samsung,pin-pud = <0>;
                 samsung,pin-drv = <0>;
         };
+
+        pmic_selb: pmic-selb {
+                samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
+                               "gph0-6";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
 };
 
 &rtc {
@@ -365,12 +776,12 @@
                                 vsys2-supply = <&vbat>;
                                 vsys3-supply = <&vbat>;
                                 infet1-supply = <&vbat>;
-                                infet2-supply = <&vbat>;
-                                infet3-supply = <&vbat>;
-                                infet4-supply = <&vbat>;
-                                infet5-supply = <&vbat>;
-                                infet6-supply = <&vbat>;
-                                infet7-supply = <&vbat>;
+                                infet2-supply = <&tps65090_dcdc1>;
+                                infet3-supply = <&tps65090_dcdc2>;
+                                infet4-supply = <&tps65090_dcdc2>;
+                                infet5-supply = <&tps65090_dcdc2>;
+                                infet6-supply = <&tps65090_dcdc2>;
+                                infet7-supply = <&tps65090_dcdc1>;
                                 vsys-l1-supply = <&vbat>;
                                 vsys-l2-supply = <&vbat>;
 
@@ -445,3 +856,4 @@
 };
 
 #include "cros-ec-keyboard.dtsi"
+#include "cros-adc-thermistors.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6052aa9c5659..8be3d7b489ff 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -76,34 +76,26 @@
         mmc@12200000 {
                 status = "okay";
                 broken-cd;
-                supports-highspeed;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <0 4>;
                 samsung,dw-mshc-ddr-timing = <0 2>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <8>;
-                };
+                bus-width = <8>;
+                cap-mmc-highspeed;
         };
 
         mmc@12220000 {
                 status = "okay";
-                supports-highspeed;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
-                slot@0 {
-                        reg = <0>;
-                        bus-width = <4>;
-                };
+                bus-width = <4>;
+                cap-sd-highspeed;
         };
 
         dp-controller@145B0000 {
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3ee48bbe05f..1d31c8132558 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "exynos5800.dtsi"
 
 / {
@@ -28,11 +29,13 @@
                 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
         };
 
-        backlight {
+        backlight: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm 0 1000000 0>;
                 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
                 default-brightness-level = <7>;
+                enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
+                power-supply = <&tps65090_fet1>;
                 pinctrl-0 = <&pwm0_out>;
                 pinctrl-names = "default";
         };
@@ -98,6 +101,17 @@
                 regulator-boot-on;
                 regulator-always-on;
         };
+
+        panel: panel {
+                compatible = "auo,b133htn01";
+                power-supply = <&tps65090_fet6>;
+                backlight = <&backlight>;
+        };
+};
+
+&adc {
+        status = "okay";
+        vdd-supply = <&ldo9_reg>;
 };
 
 &dp {
@@ -111,22 +125,7 @@
         samsung,link-rate = <0x0a>;
         samsung,lane-count = <2>;
         samsung,hpd-gpio = <&gpx2 6 0>;
-
-        display-timings {
-                native-mode = <&timing1>;
-
-                timing1: timing@1 {
-                        clock-frequency = <150660000>;
-                        hactive = <1920>;
-                        vactive = <1080>;
-                        hfront-porch = <60>;
-                        hback-porch = <172>;
-                        hsync-len = <80>;
-                        vback-porch = <25>;
-                        vfront-porch = <10>;
-                        vsync-len = <10>;
-                };
-        };
+        panel = <&panel>;
 };
 
 &fimd {
@@ -140,10 +139,348 @@
         pinctrl-names = "default";
         pinctrl-0 = <&hdmi_hpd_irq>;
         ddc = <&i2c_2>;
+
+        hdmi-en-supply = <&tps65090_fet7>;
+        vdd-supply = <&ldo8_reg>;
+        vdd_osc-supply = <&ldo10_reg>;
+        vdd_pll-supply = <&ldo8_reg>;
+};
+
+&hsi2c_4 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        max77802-pmic@9 {
+                compatible = "maxim,max77802";
+                interrupt-parent = <&gpx3>;
+                interrupts = <1 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
+                            <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
+                wakeup-source;
+                reg = <0x9>;
+                #clock-cells = <1>;
+
+                inb1-supply = <&tps65090_dcdc2>;
+                inb2-supply = <&tps65090_dcdc1>;
+                inb3-supply = <&tps65090_dcdc2>;
+                inb4-supply = <&tps65090_dcdc2>;
+                inb5-supply = <&tps65090_dcdc1>;
+                inb6-supply = <&tps65090_dcdc2>;
+                inb7-supply = <&tps65090_dcdc1>;
+                inb8-supply = <&tps65090_dcdc1>;
+                inb9-supply = <&tps65090_dcdc1>;
+                inb10-supply = <&tps65090_dcdc1>;
+
+                inl1-supply = <&buck5_reg>;
+                inl2-supply = <&buck7_reg>;
+                inl3-supply = <&buck9_reg>;
+                inl4-supply = <&buck9_reg>;
+                inl5-supply = <&buck9_reg>;
+                inl6-supply = <&tps65090_dcdc2>;
+                inl7-supply = <&buck9_reg>;
+                inl9-supply = <&tps65090_dcdc2>;
+                inl10-supply = <&buck7_reg>;
+
+                regulators {
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <700000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "vdd_1v2";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck6_reg: BUCK6 {
+                                regulator-name = "vdd_kfc";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <12500>;
+                        };
+
+                        buck7_reg: BUCK7 {
+                                regulator-name = "vdd_1v35";
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck8_reg: BUCK8 {
+                                regulator-name = "vdd_emmc";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck9_reg: BUCK9 {
+                                regulator-name = "vdd_2v";
+                                regulator-min-microvolt = <2000000>;
+                                regulator-max-microvolt = <2000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck10_reg: BUCK10 {
+                                regulator-name = "vdd_1v8";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        ldo1_reg: LDO1 {
+                                regulator-name = "vdd_1v0";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo2_reg: LDO2 {
+                                regulator-name = "vdd_1v2_2";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo3_reg: LDO3 {
+                                regulator-name = "vdd_1v8_3";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        vqmmc_sdcard: ldo4_reg: LDO4 {
+                                regulator-name = "vdd_sd";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "vdd_1v8_5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "vdd_1v8_6";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo7_reg: LDO7 {
+                                regulator-name = "vdd_1v8_7";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "vdd_ldo8";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo9_reg: LDO9 {
+                                regulator-name = "vdd_ldo9";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "vdd_ldo10";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "vdd_ldo11";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "vdd_ldo12";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "vdd_ldo13";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "vdd_ldo14";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "vdd_ldo15";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "vdd_g3ds";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                        };
+
+                        ldo18_reg: LDO18 {
+                                regulator-name = "ldo_18";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo19_reg: LDO19 {
+                                regulator-name = "ldo_19";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo20_reg: LDO20 {
+                                regulator-name = "ldo_20";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo21_reg: LDO21 {
+                                regulator-name = "ldo_21";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "ldo_23";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        ldo24_reg: LDO24 {
+                                regulator-name = "ldo_24";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "ldo_25";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        ldo26_reg: LDO26 {
+                                regulator-name = "ldo_26";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo27_reg: LDO27 {
+                                regulator-name = "ldo_27";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo28_reg: LDO28 {
+                                regulator-name = "ldo_28";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo29_reg: LDO29 {
+                                regulator-name = "ldo_29";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo30_reg: LDO30 {
+                                regulator-name = "vdd_mifs";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo32_reg: LDO32 {
+                                regulator-name = "ldo_32";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+
+                        ldo33_reg: LDO33 {
+                                regulator-name = "ldo_33";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        ldo34_reg: LDO34 {
+                                regulator-name = "ldo_34";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+
+                        ldo35_reg: LDO35 {
+                                regulator-name = "ldo_35";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+                };
+        };
 };
 
 &hsi2c_7 {
         status = "okay";
+        clock-frequency = <400000>;
 
         max98091: codec@10 {
                 compatible = "maxim,max98091";
@@ -153,6 +490,33 @@
                 pinctrl-names = "default";
                 pinctrl-0 = <&max98091_irq>;
         };
+
+        light-sensor@44 {
+                compatible = "isil,isl29018";
+                reg = <0x44>;
+                vcc-supply = <&tps65090_fet5>;
+        };
+};
+
+&hsi2c_8 {
+        status = "okay";
+        clock-frequency = <333000>;
+        /* Atmel mXT540S */
+        trackpad@4b {
+                compatible = "atmel,maxtouch";
+                reg = <0x4b>;
+                interrupt-parent = <&gpx1>;
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                wakeup-source;
+                pinctrl-names = "default";
+                pinctrl-0 = <&trackpad_irq>;
+                linux,gpio-keymap = <KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED       /* GPIO 0 */
+                                     KEY_RESERVED       /* GPIO 1 */
+                                     BTN_LEFT           /* GPIO 2 */
+                                     KEY_RESERVED>;     /* GPIO 3 */
+        };
 };
 
 &hsi2c_9 {
@@ -185,7 +549,7 @@
         num-slots = <1>;
         broken-cd;
         caps2-mmc-hs200-1_8v;
-        supports-highspeed;
+        cap-mmc-highspeed;
         non-removable;
         card-detect-delay = <200>;
         clock-frequency = <400000000>;
@@ -194,17 +558,13 @@
         samsung,dw-mshc-ddr-timing = <0 2>;
         pinctrl-names = "default";
         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <8>;
-        };
+        bus-width = <8>;
 };
 
 &mmc_2 {
         status = "okay";
         num-slots = <1>;
-        supports-highspeed;
+        cap-sd-highspeed;
         card-detect-delay = <200>;
         clock-frequency = <400000000>;
         samsung,dw-mshc-ciu-div = <3>;
@@ -212,11 +572,7 @@
         samsung,dw-mshc-ddr-timing = <1 2>;
         pinctrl-names = "default";
         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-        };
+        bus-width = <4>;
 };
 
 
@@ -247,6 +603,13 @@
                 samsung,pin-drv = <0>;
         };
 
+        trackpad_irq: trackpad-irq {
+                samsung,pins = "gpx1-1";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         power_key_irq: power-key-irq {
                 samsung,pins = "gpx1-2";
                 samsung,pin-function = <0>;
@@ -275,12 +638,42 @@
                 samsung,pin-drv = <0>;
         };
 
+        max77802_irq: max77802-irq {
+                samsung,pins = "gpx3-1";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         hdmi_hpd_irq: hdmi-hpd-irq {
                 samsung,pins = "gpx3-7";
                 samsung,pin-function = <0>;
                 samsung,pin-pud = <1>;
                 samsung,pin-drv = <0>;
         };
+
+        pmic_dvs_1: pmic-dvs-1 {
+                samsung,pins = "gpy7-6";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&pinctrl_2 {
+        pmic_dvs_2: pmic-dvs-2 {
+                samsung,pins = "gpj4-2";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pmic_dvs_3: pmic-dvs-3 {
+                samsung,pins = "gpj4-3";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
 };
 
 &pinctrl_3 {
@@ -310,6 +703,14 @@
                 samsung,pin-pud = <0>;
                 samsung,pin-drv = <0>;
         };
+
+        pmic_selb: pmic-selb {
+                samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
+                               "gph0-6";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
 };
 
 &rtc {
@@ -363,12 +764,12 @@
                                 vsys2-supply = <&vbat>;
                                 vsys3-supply = <&vbat>;
                                 infet1-supply = <&vbat>;
-                                infet2-supply = <&vbat>;
-                                infet3-supply = <&vbat>;
-                                infet4-supply = <&vbat>;
-                                infet5-supply = <&vbat>;
-                                infet6-supply = <&vbat>;
-                                infet7-supply = <&vbat>;
+                                infet2-supply = <&tps65090_dcdc1>;
+                                infet3-supply = <&tps65090_dcdc2>;
+                                infet4-supply = <&tps65090_dcdc2>;
+                                infet5-supply = <&tps65090_dcdc2>;
+                                infet6-supply = <&tps65090_dcdc2>;
+                                infet7-supply = <&tps65090_dcdc1>;
                                 vsys-l1-supply = <&vbat>;
                                 vsys-l2-supply = <&vbat>;
 
@@ -443,3 +844,4 @@
 };
 
 #include "cros-ec-keyboard.dtsi"
+#include "cros-adc-thermistors.dtsi"
diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
new file mode 100644
index 000000000000..40a9e33c2654
--- /dev/null
+++ b/arch/arm/boot/dts/hip04-d01.dts
@@ -0,0 +1,32 @@
+/*
+ *  Copyright (C) 2013-2014 Linaro Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "hip04.dtsi"
+
+/ {
+        /* memory bus is 64-bit */
+        #address-cells = <2>;
+        #size-cells = <2>;
+        model = "Hisilicon D01 Development Board";
+        compatible = "hisilicon,hip04-d01";
+
+        memory@00000000,10000000 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
+                      <0x00000004 0xc0000000 0x00000003 0x40000000>;
+        };
+
+        soc {
+                uart0: uart@4007000 {
+                        status = "ok";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
new file mode 100644
index 000000000000..93b6c909e991
--- /dev/null
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -0,0 +1,267 @@
+/*
+ * Hisilicon Ltd. HiP04 SoC
+ *
+ * Copyright (C) 2013-2014 Hisilicon Ltd.
+ * Copyright (C) 2013-2014 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+        /* memory bus is 64-bit */
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        bootwrapper {
+                compatible = "hisilicon,hip04-bootwrapper";
+                boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu-map {
+                        cluster0 {
+                                core0 {
+                                        cpu = <&CPU0>;
+                                };
+                                core1 {
+                                        cpu = <&CPU1>;
+                                };
+                                core2 {
+                                        cpu = <&CPU2>;
+                                };
+                                core3 {
+                                        cpu = <&CPU3>;
+                                };
+                        };
+                        cluster1 {
+                                core0 {
+                                        cpu = <&CPU4>;
+                                };
+                                core1 {
+                                        cpu = <&CPU5>;
+                                };
+                                core2 {
+                                        cpu = <&CPU6>;
+                                };
+                                core3 {
+                                        cpu = <&CPU7>;
+                                };
+                        };
+                        cluster2 {
+                                core0 {
+                                        cpu = <&CPU8>;
+                                };
+                                core1 {
+                                        cpu = <&CPU9>;
+                                };
+                                core2 {
+                                        cpu = <&CPU10>;
+                                };
+                                core3 {
+                                        cpu = <&CPU11>;
+                                };
+                        };
+                        cluster3 {
+                                core0 {
+                                        cpu = <&CPU12>;
+                                };
+                                core1 {
+                                        cpu = <&CPU13>;
+                                };
+                                core2 {
+                                        cpu = <&CPU14>;
+                                };
+                                core3 {
+                                        cpu = <&CPU15>;
+                                };
+                        };
+                };
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
+                CPU2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <2>;
+                };
+                CPU3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <3>;
+                };
+                CPU4: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x100>;
+                };
+                CPU5: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x101>;
+                };
+                CPU6: cpu@102 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x102>;
+                };
+                CPU7: cpu@103 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x103>;
+                };
+                CPU8: cpu@200 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x200>;
+                };
+                CPU9: cpu@201 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x201>;
+                };
+                CPU10: cpu@202 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x202>;
+                };
+                CPU11: cpu@203 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x203>;
+                };
+                CPU12: cpu@300 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x300>;
+                };
+                CPU13: cpu@301 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x301>;
+                };
+                CPU14: cpu@302 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x302>;
+                };
+                CPU15: cpu@303 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x303>;
+                };
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupt-parent = <&gic>;
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+
+        clk_50m: clk_50m {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <50000000>;
+        };
+
+        clk_168m: clk_168m {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <168000000>;
+        };
+
+        soc {
+                /* It's a 32-bit SoC. */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges = <0 0 0xe0000000 0x10000000>;
+
+                gic: interrupt-controller@c01000 {
+                        compatible = "hisilicon,hip04-intc";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        interrupts = <1 9 0xf04>;
+
+                        reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
+                              <0xc04000 0x2000>, <0xc06000 0x2000>;
+                };
+
+                sysctrl: sysctrl {
+                        compatible = "hisilicon,sysctrl";
+                        reg = <0x3e00000 0x00100000>;
+                };
+
+                fabric: fabric {
+                        compatible = "hisilicon,hip04-fabric";
+                        reg = <0x302a000 0x1000>;
+                };
+
+                dual_timer0: dual_timer@3000000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x3000000 0x1000>;
+                        interrupts = <0 224 4>;
+                        clocks = <&clk_50m>, <&clk_50m>;
+                        clock-names = "apb_pclk";
+                };
+
+                arm-pmu {
+                        compatible = "arm,cortex-a15-pmu";
+                        interrupts = <0 64 4>,
+                                     <0 65 4>,
+                                     <0 66 4>,
+                                     <0 67 4>,
+                                     <0 68 4>,
+                                     <0 69 4>,
+                                     <0 70 4>,
+                                     <0 71 4>,
+                                     <0 72 4>,
+                                     <0 73 4>,
+                                     <0 74 4>,
+                                     <0 75 4>,
+                                     <0 76 4>,
+                                     <0 77 4>,
+                                     <0 78 4>,
+                                     <0 79 4>;
+                };
+
+                uart0: uart@4007000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x4007000 0x1000>;
+                        interrupts = <0 381 4>;
+                        clocks = <&clk_168m>;
+                        clock-names = "uartclk";
+                        reg-shift = <2>;
+                        status = "disabled";
+                };
+
+                sata0: sata@a000000 {
+                        compatible = "hisilicon,hisi-ahci";
+                        reg = <0xa000000 0x1000000>;
+                        interrupts = <0 372 4>;
+                };
+
+        };
+};
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
new file mode 100644
index 000000000000..af4eee5794aa
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx1.dtsi"
+
+/ {
+        model = "Freescale MX1 ADS";
+        compatible = "fsl,imx1ads", "fsl,imx1";
+
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory {
+                reg = <0x08000000 0x04000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32 {
+                        compatible = "fsl,imx-clk32", "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32000>;
+                };
+        };
+};
+
+&cspi1 {
+        pinctrl-0 = <&pinctrl_cspi1>;
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&i2c {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c>;
+        status = "okay";
+
+        extgpio0: pcf8575@22 {
+                compatible = "nxp,pcf8575";
+                reg = <0x22>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        extgpio1: pcf8575@24 {
+                compatible = "nxp,pcf8575";
+                reg = <0x24>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim>;
+        status = "okay";
+
+        nor: nor@0,0 {
+                compatible = "cfi-flash";
+                reg = <0 0x00000000 0x02000000>;
+                bank-width = <4>;
+                fsl,weim-cs-timing = <0x00003e00 0x00000801>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+
+&iomuxc {
+        imx1-ads {
+                pinctrl_cspi1: cspi1grp {
+                        fsl,pins = <
+                                MX1_PAD_SPI1_MISO__SPI1_MISO    0x0
+                                MX1_PAD_SPI1_MOSI__SPI1_MOSI    0x0
+                                MX1_PAD_SPI1_RDY__SPI1_RDY      0x0
+                                MX1_PAD_SPI1_SCLK__SPI1_SCLK    0x0
+                                MX1_PAD_SPI1_SS__GPIO3_15       0x0
+                        >;
+                };
+
+                pinctrl_i2c: i2cgrp {
+                        fsl,pins = <
+                                MX1_PAD_I2C_SCL__I2C_SCL        0x0
+                                MX1_PAD_I2C_SDA__I2C_SDA        0x0
+                        >;
+                };
+
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX1_PAD_UART1_TXD__UART1_TXD    0x0
+                                MX1_PAD_UART1_RXD__UART1_RXD    0x0
+                                MX1_PAD_UART1_CTS__UART1_CTS    0x0
+                                MX1_PAD_UART1_RTS__UART1_RTS    0x0
+                        >;
+                };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX1_PAD_UART2_TXD__UART2_TXD    0x0
+                                MX1_PAD_UART2_RXD__UART2_RXD    0x0
+                                MX1_PAD_UART2_CTS__UART2_CTS    0x0
+                                MX1_PAD_UART2_RTS__UART2_RTS    0x0
+                        >;
+                };
+
+                pinctrl_weim: weimgrp {
+                        fsl,pins = <
+                                MX1_PAD_A0__A0                  0x0
+                                MX1_PAD_A16__A16                0x0
+                                MX1_PAD_A17__A17                0x0
+                                MX1_PAD_A18__A18                0x0
+                                MX1_PAD_A19__A19                0x0
+                                MX1_PAD_A20__A20                0x0
+                                MX1_PAD_A21__A21                0x0
+                                MX1_PAD_A22__A22                0x0
+                                MX1_PAD_A23__A23                0x0
+                                MX1_PAD_A24__A24                0x0
+                                MX1_PAD_BCLK__BCLK              0x0
+                                MX1_PAD_CS4__CS4                0x0
+                                MX1_PAD_DTACK__DTACK            0x0
+                                MX1_PAD_ECB__ECB                0x0
+                                MX1_PAD_LBA__LBA                0x0
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
new file mode 100644
index 000000000000..07d92fb40e6f
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx1.dtsi"
+
+/ {
+        model = "Armadeus APF9328";
+        compatible = "armadeus,imx1-apf9328", "fsl,imx1";
+
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory {
+                reg = <0x08000000 0x00800000>;
+        };
+};
+
+&i2c {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim>;
+        status = "okay";
+
+        nor: nor@0,0 {
+                compatible = "cfi-flash";
+                reg = <0 0x00000000 0x02000000>;
+                bank-width = <2>;
+                fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+
+        eth: eth@4,c00000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_eth>;
+                compatible = "davicom,dm9000";
+                reg = <
+                        4 0x00c00000 0x2
+                        4 0x00c00002 0x2
+                >;
+                interrupt-parent = <&gpio2>;
+                interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+                fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
+        };
+};
+
+&iomuxc {
+        imx1-apf9328 {
+                pinctrl_eth: ethgrp {
+                        fsl,pins = <
+                                MX1_PAD_SIM_SVEN__GPIO2_14      0x0
+                        >;
+                };
+
+                pinctrl_i2c: i2cgrp {
+                        fsl,pins = <
+                                MX1_PAD_I2C_SCL__I2C_SCL        0x0
+                                MX1_PAD_I2C_SDA__I2C_SDA        0x0
+                        >;
+                };
+
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX1_PAD_UART1_TXD__UART1_TXD    0x0
+                                MX1_PAD_UART1_RXD__UART1_RXD    0x0
+                                MX1_PAD_UART1_CTS__UART1_CTS    0x0
+                                MX1_PAD_UART1_RTS__UART1_RTS    0x0
+                        >;
+                };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX1_PAD_UART2_TXD__UART2_TXD    0x0
+                                MX1_PAD_UART2_RXD__UART2_RXD    0x0
+                                MX1_PAD_UART2_CTS__UART2_CTS    0x0
+                                MX1_PAD_UART2_RTS__UART2_RTS    0x0
+                        >;
+                };
+
+                pinctrl_weim: weimgrp {
+                        fsl,pins = <
+                                MX1_PAD_A0__A0                  0x0
+                                MX1_PAD_A16__A16                0x0
+                                MX1_PAD_A17__A17                0x0
+                                MX1_PAD_A18__A18                0x0
+                                MX1_PAD_A19__A19                0x0
+                                MX1_PAD_A20__A20                0x0
+                                MX1_PAD_A21__A21                0x0
+                                MX1_PAD_A22__A22                0x0
+                                MX1_PAD_A23__A23                0x0
+                                MX1_PAD_A24__A24                0x0
+                                MX1_PAD_BCLK__BCLK              0x0
+                                MX1_PAD_CS4__CS4                0x0
+                                MX1_PAD_DTACK__DTACK            0x0
+                                MX1_PAD_ECB__ECB                0x0
+                                MX1_PAD_LBA__LBA                0x0
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h
new file mode 100644
index 000000000000..22bec8b87680
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-pinfunc.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DTS_IMX1_PINFUNC_H
+#define __DTS_IMX1_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function:      0 - Primary function
+ *                1 - Alternate function
+ *                2 - GPIO
+ * direction:     0 - Input
+ *                1 - Output
+ * gpio_oconf:    0 - A_IN
+ *                1 - B_IN
+ *                2 - A_OUT
+ *                3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ *                1 - Interrupt Status Register
+ *                2 - 0
+ *                3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX1_PAD_A24__A24                        0x00 0x004
+#define MX1_PAD_A24__GPIO1_0                    0x00 0x032
+#define MX1_PAD_A24__SPI2_CLK                   0x00 0x006
+#define MX1_PAD_TIN__TIN                        0x01 0x000
+#define MX1_PAD_TIN__GPIO1_1                    0x01 0x032
+#define MX1_PAD_TIN__SPI2_RXD                   0x01 0x022
+#define MX1_PAD_PWMO__PWMO                      0x02 0x004
+#define MX1_PAD_PWMO__GPIO1_2                   0x02 0x032
+#define MX1_PAD_CSI_MCLK__CSI_MCLK              0x03 0x004
+#define MX1_PAD_CSI_MCLK__GPIO1_3               0x03 0x032
+#define MX1_PAD_CSI_D0__CSI_D0                  0x04 0x000
+#define MX1_PAD_CSI_D0__GPIO1_4                 0x04 0x032
+#define MX1_PAD_CSI_D1__CSI_D1                  0x05 0x000
+#define MX1_PAD_CSI_D1__GPIO1_5                 0x05 0x032
+#define MX1_PAD_CSI_D2__CSI_D2                  0x06 0x000
+#define MX1_PAD_CSI_D2__GPIO1_6                 0x06 0x032
+#define MX1_PAD_CSI_D3__CSI_D3                  0x07 0x000
+#define MX1_PAD_CSI_D3__GPIO1_7                 0x07 0x032
+#define MX1_PAD_CSI_D4__CSI_D4                  0x08 0x000
+#define MX1_PAD_CSI_D4__GPIO1_8                 0x08 0x032
+#define MX1_PAD_CSI_D5__CSI_D5                  0x09 0x000
+#define MX1_PAD_CSI_D5__GPIO1_9                 0x09 0x032
+#define MX1_PAD_CSI_D6__CSI_D6                  0x0a 0x000
+#define MX1_PAD_CSI_D6__GPIO1_10                0x0a 0x032
+#define MX1_PAD_CSI_D7__CSI_D7                  0x0b 0x000
+#define MX1_PAD_CSI_D7__GPIO1_11                0x0b 0x032
+#define MX1_PAD_CSI_VSYNC__CSI_VSYNC            0x0c 0x000
+#define MX1_PAD_CSI_VSYNC__GPIO1_12             0x0c 0x032
+#define MX1_PAD_CSI_HSYNC__CSI_HSYNC            0x0d 0x000
+#define MX1_PAD_CSI_HSYNC__GPIO1_13             0x0d 0x032
+#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK          0x0e 0x000
+#define MX1_PAD_CSI_PIXCLK__GPIO1_14            0x0e 0x032
+#define MX1_PAD_I2C_SDA__I2C_SDA                0x0f 0x000
+#define MX1_PAD_I2C_SDA__GPIO1_15               0x0f 0x032
+#define MX1_PAD_I2C_SCL__I2C_SCL                0x10 0x004
+#define MX1_PAD_I2C_SCL__GPIO1_16               0x10 0x032
+#define MX1_PAD_DTACK__DTACK                    0x11 0x000
+#define MX1_PAD_DTACK__GPIO1_17                 0x11 0x032
+#define MX1_PAD_DTACK__SPI2_SS                  0x11 0x002
+#define MX1_PAD_DTACK__A25                      0x11 0x016
+#define MX1_PAD_BCLK__BCLK                      0x12 0x004
+#define MX1_PAD_BCLK__GPIO1_18                  0x12 0x032
+#define MX1_PAD_LBA__LBA                        0x13 0x004
+#define MX1_PAD_LBA__GPIO1_19                   0x13 0x032
+#define MX1_PAD_ECB__ECB                        0x14 0x000
+#define MX1_PAD_ECB__GPIO1_20                   0x14 0x032
+#define MX1_PAD_A0__A0                          0x15 0x004
+#define MX1_PAD_A0__GPIO1_21                    0x15 0x032
+#define MX1_PAD_CS4__CS4                        0x16 0x004
+#define MX1_PAD_CS4__GPIO1_22                   0x16 0x032
+#define MX1_PAD_CS5__CS5                        0x17 0x004
+#define MX1_PAD_CS5__GPIO1_23                   0x17 0x032
+#define MX1_PAD_A16__A16                        0x18 0x004
+#define MX1_PAD_A16__GPIO1_24                   0x18 0x032
+#define MX1_PAD_A17__A17                        0x19 0x004
+#define MX1_PAD_A17__GPIO1_25                   0x19 0x032
+#define MX1_PAD_A18__A18                        0x1a 0x004
+#define MX1_PAD_A18__GPIO1_26                   0x1a 0x032
+#define MX1_PAD_A19__A19                        0x1b 0x004
+#define MX1_PAD_A19__GPIO1_27                   0x1b 0x032
+#define MX1_PAD_A20__A20                        0x1c 0x004
+#define MX1_PAD_A20__GPIO1_28                   0x1c 0x032
+#define MX1_PAD_A21__A21                        0x1d 0x004
+#define MX1_PAD_A21__GPIO1_29                   0x1d 0x032
+#define MX1_PAD_A22__A22                        0x1e 0x004
+#define MX1_PAD_A22__GPIO1_30                   0x1e 0x032
+#define MX1_PAD_A23__A23                        0x1f 0x004
+#define MX1_PAD_A23__GPIO1_31                   0x1f 0x032
+#define MX1_PAD_SD_DAT0__SD_DAT0                0x28 0x000
+#define MX1_PAD_SD_DAT0__MS_PI0                 0x28 0x001
+#define MX1_PAD_SD_DAT0__GPIO2_8                0x28 0x032
+#define MX1_PAD_SD_DAT1__SD_DAT1                0x29 0x000
+#define MX1_PAD_SD_DAT1__MS_PI1                 0x29 0x001
+#define MX1_PAD_SD_DAT1__GPIO2_9                0x29 0x032
+#define MX1_PAD_SD_DAT2__SD_DAT2                0x2a 0x000
+#define MX1_PAD_SD_DAT2__MS_SCLKI               0x2a 0x001
+#define MX1_PAD_SD_DAT2__GPIO2_10               0x2a 0x032
+#define MX1_PAD_SD_DAT3__SD_DAT3                0x2b 0x000
+#define MX1_PAD_SD_DAT3__MS_SDIO                0x2b 0x001
+#define MX1_PAD_SD_DAT3__GPIO2_11               0x2b 0x032
+#define MX1_PAD_SD_SCLK__SD_SCLK                0x2c 0x004
+#define MX1_PAD_SD_SCLK__MS_SCLKO               0x2c 0x005
+#define MX1_PAD_SD_SCLK__GPIO2_12               0x2c 0x032
+#define MX1_PAD_SD_CMD__SD_CMD                  0x2d 0x000
+#define MX1_PAD_SD_CMD__MS_BS                   0x2d 0x005
+#define MX1_PAD_SD_CMD__GPIO2_13                0x2d 0x032
+#define MX1_PAD_SIM_SVEN__SIM_SVEN              0x2e 0x004
+#define MX1_PAD_SIM_SVEN__SSI_RXFS              0x2e 0x001
+#define MX1_PAD_SIM_SVEN__GPIO2_14              0x2e 0x032
+#define MX1_PAD_SIM_PD__SIM_PD                  0x2f 0x000
+#define MX1_PAD_SIM_PD__SSI_RXCLK               0x2f 0x001
+#define MX1_PAD_SIM_PD__GPIO2_15                0x2f 0x032
+#define MX1_PAD_SIM_TX__SIM_TX                  0x30 0x000
+#define MX1_PAD_SIM_TX__SSI_RXDAT               0x30 0x001
+#define MX1_PAD_SIM_TX__GPIO2_16                0x30 0x032
+#define MX1_PAD_SIM_RX__SIM_RX                  0x31 0x000
+#define MX1_PAD_SIM_RX__SSI_TXDAT               0x31 0x005
+#define MX1_PAD_SIM_RX__GPIO2_17                0x31 0x032
+#define MX1_PAD_SIM_RST__SIM_RST                0x32 0x004
+#define MX1_PAD_SIM_RST__SSI_TXFS               0x32 0x001
+#define MX1_PAD_SIM_RST__GPIO2_18               0x32 0x032
+#define MX1_PAD_SIM_CLK__SIM_CLK                0x33 0x004
+#define MX1_PAD_SIM_CLK__SSI_TXCLK              0x33 0x001
+#define MX1_PAD_SIM_CLK__GPIO2_19               0x33 0x032
+#define MX1_PAD_USBD_AFE__USBD_AFE              0x34 0x004
+#define MX1_PAD_USBD_AFE__GPIO2_20              0x34 0x032
+#define MX1_PAD_USBD_OE__USBD_OE                0x35 0x004
+#define MX1_PAD_USBD_OE__GPIO2_21               0x35 0x032
+#define MX1_PAD_USBD_RCV__USBD_RCV              0x36 0x000
+#define MX1_PAD_USBD_RCV__GPIO2_22              0x36 0x032
+#define MX1_PAD_USBD_SUSPND__USBD_SUSPND        0x37 0x004
+#define MX1_PAD_USBD_SUSPND__GPIO2_23           0x37 0x032
+#define MX1_PAD_USBD_VP__USBD_VP                0x38 0x000
+#define MX1_PAD_USBD_VP__GPIO2_24               0x38 0x032
+#define MX1_PAD_USBD_VM__USBD_VM                0x39 0x000
+#define MX1_PAD_USBD_VM__GPIO2_25               0x39 0x032
+#define MX1_PAD_USBD_VPO__USBD_VPO              0x3a 0x004
+#define MX1_PAD_USBD_VPO__GPIO2_26              0x3a 0x032
+#define MX1_PAD_USBD_VMO__USBD_VMO              0x3b 0x004
+#define MX1_PAD_USBD_VMO__GPIO2_27              0x3b 0x032
+#define MX1_PAD_UART2_CTS__UART2_CTS            0x3c 0x004
+#define MX1_PAD_UART2_CTS__GPIO2_28             0x3c 0x032
+#define MX1_PAD_UART2_RTS__UART2_RTS            0x3d 0x000
+#define MX1_PAD_UART2_RTS__GPIO2_29             0x3d 0x032
+#define MX1_PAD_UART2_TXD__UART2_TXD            0x3e 0x004
+#define MX1_PAD_UART2_TXD__GPIO2_30             0x3e 0x032
+#define MX1_PAD_UART2_RXD__UART2_RXD            0x3f 0x000
+#define MX1_PAD_UART2_RXD__GPIO2_31             0x3f 0x032
+#define MX1_PAD_SSI_RXFS__SSI_RXFS              0x43 0x000
+#define MX1_PAD_SSI_RXFS__GPIO3_3               0x43 0x032
+#define MX1_PAD_SSI_RXCLK__SSI_RXCLK            0x44 0x000
+#define MX1_PAD_SSI_RXCLK__GPIO3_4              0x44 0x032
+#define MX1_PAD_SSI_RXDAT__SSI_RXDAT            0x45 0x000
+#define MX1_PAD_SSI_RXDAT__GPIO3_5              0x45 0x032
+#define MX1_PAD_SSI_TXDAT__SSI_TXDAT            0x46 0x004
+#define MX1_PAD_SSI_TXDAT__GPIO3_6              0x46 0x032
+#define MX1_PAD_SSI_TXFS__SSI_TXFS              0x47 0x000
+#define MX1_PAD_SSI_TXFS__GPIO3_7               0x47 0x032
+#define MX1_PAD_SSI_TXCLK__SSI_TXCLK            0x48 0x000
+#define MX1_PAD_SSI_TXCLK__GPIO3_8              0x48 0x032
+#define MX1_PAD_UART1_CTS__UART1_CTS            0x49 0x004
+#define MX1_PAD_UART1_CTS__GPIO3_9              0x49 0x032
+#define MX1_PAD_UART1_RTS__UART1_RTS            0x4a 0x000
+#define MX1_PAD_UART1_RTS__GPIO3_10             0x4a 0x032
+#define MX1_PAD_UART1_TXD__UART1_TXD            0x4b 0x004
+#define MX1_PAD_UART1_TXD__GPIO3_11             0x4b 0x032
+#define MX1_PAD_UART1_RXD__UART1_RXD            0x4c 0x000
+#define MX1_PAD_UART1_RXD__GPIO3_12             0x4c 0x032
+#define MX1_PAD_SPI1_RDY__SPI1_RDY              0x4d 0x000
+#define MX1_PAD_SPI1_RDY__GPIO3_13              0x4d 0x032
+#define MX1_PAD_SPI1_SCLK__SPI1_SCLK            0x4e 0x004
+#define MX1_PAD_SPI1_SCLK__GPIO3_14             0x4e 0x032
+#define MX1_PAD_SPI1_SS__SPI1_SS                0x4f 0x000
+#define MX1_PAD_SPI1_SS__GPIO3_15               0x4f 0x032
+#define MX1_PAD_SPI1_MISO__SPI1_MISO            0x50 0x000
+#define MX1_PAD_SPI1_MISO__GPIO3_16             0x50 0x032
+#define MX1_PAD_SPI1_MOSI__SPI1_MOSI            0x51 0x004
+#define MX1_PAD_SPI1_MOSI__GPIO3_17             0x51 0x032
+#define MX1_PAD_BT13__BT13                      0x53 0x004
+#define MX1_PAD_BT13__SSI2_RXCLK                0x53 0x001
+#define MX1_PAD_BT13__GPIO3_19                  0x53 0x032
+#define MX1_PAD_BT12__BT12                      0x54 0x004
+#define MX1_PAD_BT12__SSI2_TXFS                 0x54 0x001
+#define MX1_PAD_BT12__GPIO3_20                  0x54 0x032
+#define MX1_PAD_BT11__BT11                      0x55 0x004
+#define MX1_PAD_BT11__SSI2_TXCLK                0x55 0x001
+#define MX1_PAD_BT11__GPIO3_21                  0x55 0x032
+#define MX1_PAD_BT10__BT10                      0x56 0x004
+#define MX1_PAD_BT10__SSI2_TX                   0x56 0x001
+#define MX1_PAD_BT10__GPIO3_22                  0x56 0x032
+#define MX1_PAD_BT9__BT9                        0x57 0x004
+#define MX1_PAD_BT9__SSI2_RX                    0x57 0x001
+#define MX1_PAD_BT9__GPIO3_23                   0x57 0x032
+#define MX1_PAD_BT8__BT8                        0x58 0x004
+#define MX1_PAD_BT8__SSI2_RXFS                  0x58 0x001
+#define MX1_PAD_BT8__GPIO3_24                   0x58 0x032
+#define MX1_PAD_BT8__UART3_RI                   0x58 0x016
+#define MX1_PAD_BT7__BT7                        0x59 0x004
+#define MX1_PAD_BT7__GPIO3_25                   0x59 0x032
+#define MX1_PAD_BT7__UART3_DSR                  0x59 0x016
+#define MX1_PAD_BT6__BT6                        0x5a 0x004
+#define MX1_PAD_BT6__GPIO3_26                   0x5a 0x032
+#define MX1_PAD_BT6__SPI2_SS3                   0x5a 0x016
+#define MX1_PAD_BT6__UART3_DTR                  0x5a 0x022
+#define MX1_PAD_BT5__BT5                        0x5b 0x000
+#define MX1_PAD_BT5__GPIO3_27                   0x5b 0x032
+#define MX1_PAD_BT5__UART3_DCD                  0x5b 0x016
+#define MX1_PAD_BT4__BT4                        0x5c 0x000
+#define MX1_PAD_BT4__GPIO3_28                   0x5c 0x032
+#define MX1_PAD_BT4__UART3_CTS                  0x5c 0x016
+#define MX1_PAD_BT3__BT3                        0x5d 0x000
+#define MX1_PAD_BT3__GPIO3_29                   0x5d 0x032
+#define MX1_PAD_BT3__UART3_RTS                  0x5d 0x022
+#define MX1_PAD_BT2__BT2                        0x5e 0x004
+#define MX1_PAD_BT2__GPIO3_30                   0x5e 0x032
+#define MX1_PAD_BT2__UART3_TX                   0x5e 0x016
+#define MX1_PAD_BT1__BT1                        0x5f 0x000
+#define MX1_PAD_BT1__GPIO3_31                   0x5f 0x032
+#define MX1_PAD_BT1__UART3_RX                   0x5f 0x022
+#define MX1_PAD_LSCLK__LSCLK                    0x66 0x004
+#define MX1_PAD_LSCLK__GPIO4_6                  0x66 0x032
+#define MX1_PAD_REV__REV                        0x67 0x004
+#define MX1_PAD_REV__UART2_DTR                  0x67 0x001
+#define MX1_PAD_REV__GPIO4_7                    0x67 0x032
+#define MX1_PAD_REV__SPI2_CLK                   0x67 0x006
+#define MX1_PAD_CLS__CLS                        0x68 0x004
+#define MX1_PAD_CLS__UART2_DCD                  0x68 0x005
+#define MX1_PAD_CLS__GPIO4_8                    0x68 0x032
+#define MX1_PAD_CLS__SPI2_SS                    0x68 0x002
+#define MX1_PAD_PS__PS                          0x69 0x004
+#define MX1_PAD_PS__UART2_RI                    0x69 0x005
+#define MX1_PAD_PS__GPIO4_9                     0x69 0x032
+#define MX1_PAD_PS__SPI2_RXD                    0x69 0x022
+#define MX1_PAD_SPL_SPR__SPL_SPR                0x6a 0x004
+#define MX1_PAD_SPL_SPR__UART2_DSR              0x6a 0x005
+#define MX1_PAD_SPL_SPR__GPIO4_10               0x6a 0x032
+#define MX1_PAD_SPL_SPR__SPI2_TXD               0x6a 0x006
+#define MX1_PAD_CONTRAST__CONTRAST              0x6b 0x004
+#define MX1_PAD_CONTRAST__GPIO4_11              0x6b 0x032
+#define MX1_PAD_CONTRAST__SPI2_SS2              0x6b 0x012
+#define MX1_PAD_ACD_OE__ACD_OE                  0x6c 0x004
+#define MX1_PAD_ACD_OE__GPIO4_12                0x6c 0x032
+#define MX1_PAD_LP_HSYNC__LP_HSYNC              0x6d 0x004
+#define MX1_PAD_LP_HSYNC__GPIO4_13              0x6d 0x032
+#define MX1_PAD_FLM_VSYNC__FLM_VSYNC            0x6e 0x004
+#define MX1_PAD_FLM_VSYNC__GPIO4_14             0x6e 0x032
+#define MX1_PAD_LD0__LD0                        0x6f 0x004
+#define MX1_PAD_LD0__GPIO4_15                   0x6f 0x032
+#define MX1_PAD_LD1__LD1                        0x70 0x004
+#define MX1_PAD_LD1__GPIO4_16                   0x70 0x032
+#define MX1_PAD_LD2__LD2                        0x71 0x004
+#define MX1_PAD_LD2__GPIO4_17                   0x71 0x032
+#define MX1_PAD_LD3__LD3                        0x72 0x004
+#define MX1_PAD_LD3__GPIO4_18                   0x72 0x032
+#define MX1_PAD_LD4__LD4                        0x73 0x004
+#define MX1_PAD_LD4__GPIO4_19                   0x73 0x032
+#define MX1_PAD_LD5__LD5                        0x74 0x004
+#define MX1_PAD_LD5__GPIO4_20                   0x74 0x032
+#define MX1_PAD_LD6__LD6                        0x75 0x004
+#define MX1_PAD_LD6__GPIO4_21                   0x75 0x032
+#define MX1_PAD_LD7__LD7                        0x76 0x004
+#define MX1_PAD_LD7__GPIO4_22                   0x76 0x032
+#define MX1_PAD_LD8__LD8                        0x77 0x004
+#define MX1_PAD_LD8__GPIO4_23                   0x77 0x032
+#define MX1_PAD_LD9__LD9                        0x78 0x004
+#define MX1_PAD_LD9__GPIO4_24                   0x78 0x032
+#define MX1_PAD_LD10__LD10                      0x79 0x004
+#define MX1_PAD_LD10__GPIO4_25                  0x79 0x032
+#define MX1_PAD_LD11__LD11                      0x7a 0x004
+#define MX1_PAD_LD11__GPIO4_26                  0x7a 0x032
+#define MX1_PAD_LD12__LD12                      0x7b 0x004
+#define MX1_PAD_LD12__GPIO4_27                  0x7b 0x032
+#define MX1_PAD_LD13__LD13                      0x7c 0x004
+#define MX1_PAD_LD13__GPIO4_28                  0x7c 0x032
+#define MX1_PAD_LD14__LD14                      0x7d 0x004
+#define MX1_PAD_LD14__GPIO4_29                  0x7d 0x032
+#define MX1_PAD_LD15__LD15                      0x7e 0x004
+#define MX1_PAD_LD15__GPIO4_30                  0x7e 0x032
+#define MX1_PAD_TMR2OUT__TMR2OUT                0x7f 0x000
+#define MX1_PAD_TMR2OUT__GPIO4_31               0x7f 0x032
+#define MX1_PAD_TMR2OUT__SPI2_TXD               0x7f 0x006
+
+#endif
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
new file mode 100644
index 000000000000..22f5d1db5b31
--- /dev/null
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -0,0 +1,266 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include "imx1-pinfunc.h"
+
+#include <dt-bindings/clock/imx1-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        aliases {
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                i2c0 = &i2c;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                spi0 = &cspi1;
+                spi1 = &cspi2;
+        };
+
+        aitc: aitc-interrupt-controller@00223000 {
+                compatible = "fsl,imx1-aitc", "fsl,avic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x00223000 0x1000>;
+        };
+
+        cpus {
+                #size-cells = <0>;
+                #address-cells = <1>;
+
+                cpu: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,arm920t";
+                        operating-points = <200000 1900000>;
+                        clock-latency = <62500>;
+                        clocks = <&clks IMX1_CLK_MCU>;
+                        voltage-tolerance = <5>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&aitc>;
+                ranges;
+
+                aipi@00200000 {
+                        compatible = "fsl,aipi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x00200000 0x10000>;
+                        ranges;
+
+                        gpt1: timer@00202000 {
+                                compatible = "fsl,imx1-gpt";
+                                reg = <0x00202000 0x1000>;
+                                interrupts = <59>;
+                                clocks = <&clks IMX1_CLK_HCLK>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpt2: timer@00203000 {
+                                compatible = "fsl,imx1-gpt";
+                                reg = <0x00203000 0x1000>;
+                                interrupts = <58>;
+                                clocks = <&clks IMX1_CLK_HCLK>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        fb: fb@00205000 {
+                                compatible = "fsl,imx1-fb";
+                                reg = <0x00205000 0x1000>;
+                                interrupts = <14>;
+                                clocks = <&clks IMX1_CLK_DUMMY>,
+                                         <&clks IMX1_CLK_DUMMY>,
+                                         <&clks IMX1_CLK_PER2>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+
+                        uart1: serial@00206000 {
+                                compatible = "fsl,imx1-uart";
+                                reg = <0x00206000 0x1000>;
+                                interrupts = <30 29 26>;
+                                clocks = <&clks IMX1_CLK_HCLK>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart2: serial@00207000 {
+                                compatible = "fsl,imx1-uart";
+                                reg = <0x00207000 0x1000>;
+                                interrupts = <24 23 20>;
+                                clocks = <&clks IMX1_CLK_HCLK>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        pwm: pwm@00208000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx1-pwm";
+                                reg = <0x00208000 0x1000>;
+                                interrupts = <34>;
+                                clocks = <&clks IMX1_CLK_DUMMY>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        dma: dma@00209000 {
+                                compatible = "fsl,imx1-dma";
+                                reg = <0x00209000 0x1000>;
+                                interrupts = <61 60>;
+                                clocks = <&clks IMX1_CLK_HCLK>,
+                                         <&clks IMX1_CLK_DMA_GATE>;
+                                clock-names = "ipg", "ahb";
+                                #dma-cells = <1>;
+                        };
+
+                        uart3: serial@0020a000 {
+                                compatible = "fsl,imx1-uart";
+                                reg = <0x0020a000 0x1000>;
+                                interrupts = <54 4 1>;
+                                clocks = <&clks IMX1_CLK_UART3_GATE>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                };
+
+                aipi@00210000 {
+                        compatible = "fsl,aipi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x00210000 0x10000>;
+                        ranges;
+
+                        cspi1: cspi@00213000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx1-cspi";
+                                reg = <0x00213000 0x1000>;
+                                interrupts = <41>;
+                                clocks = <&clks IMX1_CLK_DUMMY>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        i2c: i2c@00217000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx1-i2c";
+                                reg = <0x00217000 0x1000>;
+                                interrupts = <39>;
+                                clocks = <&clks IMX1_CLK_HCLK>;
+                                status = "disabled";
+                        };
+
+                        cspi2: cspi@00219000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx1-cspi";
+                                reg = <0x00219000 0x1000>;
+                                interrupts = <40>;
+                                clocks = <&clks IMX1_CLK_DUMMY>,
+                                         <&clks IMX1_CLK_PER1>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        clks: ccm@0021b000 {
+                                compatible = "fsl,imx1-ccm";
+                                reg = <0x0021b000 0x1000>;
+                                #clock-cells = <1>;
+                        };
+
+                        iomuxc: iomuxc@0021c000 {
+                                compatible = "fsl,imx1-iomuxc";
+                                reg = <0x0021c000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges;
+
+                                gpio1: gpio@0021c000 {
+                                        compatible = "fsl,imx1-gpio";
+                                        reg = <0x0021c000 0x100>;
+                                        interrupts = <11>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                gpio2: gpio@0021c100 {
+                                        compatible = "fsl,imx1-gpio";
+                                        reg = <0x0021c100 0x100>;
+                                        interrupts = <12>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                gpio3: gpio@0021c200 {
+                                        compatible = "fsl,imx1-gpio";
+                                        reg = <0x0021c200 0x100>;
+                                        interrupts = <13>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                gpio4: gpio@0021c300 {
+                                        compatible = "fsl,imx1-gpio";
+                                        reg = <0x0021c300 0x100>;
+                                        interrupts = <62>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                        };
+                };
+
+                weim: weim@00220000 {
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        compatible = "fsl,imx1-weim";
+                        reg = <0x00220000 0x1000>;
+                        clocks = <&clks IMX1_CLK_DUMMY>;
+                        ranges = <
+                                0 0 0x10000000 0x02000000
+                                1 0 0x12000000 0x01000000
+                                2 0 0x13000000 0x01000000
+                                3 0 0x14000000 0x01000000
+                                4 0 0x15000000 0x01000000
+                                5 0 0x16000000 0x01000000
+                        >;
+                        status = "disabled";
+                };
+
+                esram: esram@00300000 {
+                        compatible = "mmio-sram";
+                        reg = <0x00300000 0x20000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index a33f66c11b73..57e29977ba06 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -60,10 +60,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&lcdif_24bit_pins_a>;
                                 lcd-supply = <&reg_lcd_3v3>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <24>;
 
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 9238a95d8e62..88eebb15da6a 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -247,6 +247,7 @@
 #define MX25_PAD_OE_ACD__GPIO_1_25              0x114 0x30c 0x000 0x15 0x000
 
 #define MX25_PAD_CONTRAST__CONTRAST             0x118 0x310 0x000 0x10 0x000
+#define MX25_PAD_CONTRAST__CC4                  0x118 0x310 0x000 0x11 0x000
 #define MX25_PAD_CONTRAST__PWM4_PWMO            0x118 0x310 0x000 0x14 0x000
 #define MX25_PAD_CONTRAST__FEC_CRS              0x118 0x310 0x508 0x15 0x001
 
@@ -260,6 +261,7 @@
 #define MX25_PAD_CSI_D2__CSPI3_MOSI             0x120 0x318 0x000 0x17 0x000
 
 #define MX25_PAD_CSI_D3__CSI_D3                 0x124 0x31c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D3__UART5_TXD_MUX          0x124 0x31c 0x000 0x11 0x000
 #define MX25_PAD_CSI_D3__GPIO_1_28              0x124 0x31c 0x000 0x15 0x000
 #define MX25_PAD_CSI_D3__CSPI3_MISO             0x124 0x31c 0x4b4 0x17 0x001
 
@@ -269,31 +271,46 @@
 #define MX25_PAD_CSI_D4__CSPI3_SCLK             0x128 0x320 0x000 0x17 0x000
 
 #define MX25_PAD_CSI_D5__CSI_D5                 0x12c 0x324 0x000 0x10 0x000
+#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x001
 #define MX25_PAD_CSI_D5__GPIO_1_30              0x12c 0x324 0x000 0x15 0x000
 #define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x17 0x000
 
 #define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x10 0x000
+#define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x12 0x001
 #define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK          0x134 0x32C 0x4dc 0x12 0x001
 #define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x10 0x000
+#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x001
 #define MX25_PAD_CSI_D8__GPIO_1_7               0x138 0x330 0x000 0x15 0x000
+#define MX25_PAD_CSI_D8__CSPI3_SS2              0x138 0x330 0x4c4 0x17 0x000
 
 #define MX25_PAD_CSI_D9__CSI_D9                 0x13c 0x334 0x000 0x10 0x000
+#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x001
 #define MX25_PAD_CSI_D9__GPIO_4_21              0x13c 0x334 0x000 0x15 0x000
+#define MX25_PAD_CSI_D9__CSPI3_SS3              0x13c 0x334 0x4c8 0x17 0x000
 
 #define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x10 0x000
+#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x001
+#define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x12 0x001
 #define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x10 0x000
+#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x001
+#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x12 0x001
 #define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x10 0x000
+#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x001
+#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x12 0x001
 #define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x10 0x000
+#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x001
+#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x12 0x001
 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x15 0x000
 
 #define MX25_PAD_I2C1_CLK__I2C1_CLK             0x150 0x348 0x000 0x10 0x000
@@ -303,18 +320,24 @@
 #define MX25_PAD_I2C1_DAT__GPIO_1_13            0x154 0x34c 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI         0x158 0x350 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MOSI__UART3_RXD          0x158 0x350 0x000 0x12 0x000
 #define MX25_PAD_CSPI1_MOSI__GPIO_1_14          0x158 0x350 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_MISO__CSPI1_MISO         0x15c 0x354 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MISO__UART3_TXD          0x15c 0x354 0x000 0x12 0x000
 #define MX25_PAD_CSPI1_MISO__GPIO_1_15          0x15c 0x354 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_SS0__CSPI1_SS0           0x160 0x358 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS0__PWM2_PWMO           0x160 0x358 0x000 0x12 0x000
 #define MX25_PAD_CSPI1_SS0__GPIO_1_16           0x160 0x358 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_SS1__CSPI1_SS1           0x164 0x35c 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS1__I2C3_DAT            0x164 0x35C 0x528 0x11 0x001
+#define MX25_PAD_CSPI1_SS1__UART3_RTS           0x164 0x35c 0x000 0x12 0x000
 #define MX25_PAD_CSPI1_SS1__GPIO_1_17           0x164 0x35c 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK         0x168 0x360 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SCLK__UART3_CTS          0x168 0x360 0x000 0x12 0x000
 #define MX25_PAD_CSPI1_SCLK__GPIO_1_18          0x168 0x360 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_RDY__CSPI1_RDY           0x16c 0x364 0x000 0x10 0x000
@@ -328,6 +351,7 @@
 
 #define MX25_PAD_UART1_RTS__UART1_RTS           0x178 0x370 0x000 0x10 0x000
 #define MX25_PAD_UART1_RTS__CSI_D0              0x178 0x370 0x488 0x11 0x001
+#define MX25_PAD_UART1_RTS__CC3                 0x178 0x370 0x000 0x12 0x000
 #define MX25_PAD_UART1_RTS__GPIO_4_24           0x178 0x370 0x000 0x15 0x000
 
 #define MX25_PAD_UART1_CTS__UART1_CTS           0x17c 0x374 0x000 0x10 0x000
@@ -342,6 +366,7 @@
 
 #define MX25_PAD_UART2_RTS__UART2_RTS           0x188 0x380 0x000 0x10 0x000
 #define MX25_PAD_UART2_RTS__FEC_COL             0x188 0x380 0x504 0x12 0x002
+#define MX25_PAD_UART2_RTS__CC1                 0x188 0x380 0x000 0x13 0x000
 #define MX25_PAD_UART2_RTS__GPIO_4_28           0x188 0x380 0x000 0x15 0x000
 
 #define MX25_PAD_UART2_CTS__FEC_RX_ER           0x18c 0x384 0x518 0x12 0x002
@@ -349,14 +374,17 @@
 #define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x15 0x000
 
 #define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__CSPI2_MOSI            0x190 0x388 0x4a0 0x11 0x001
 #define MX25_PAD_SD1_CMD__FEC_RDATA2            0x190 0x388 0x50c 0x12 0x002
 #define MX25_PAD_SD1_CMD__GPIO_2_23             0x190 0x388 0x000 0x15 0x000
 
 #define MX25_PAD_SD1_CLK__SD1_CLK               0x194 0x38c 0x000 0x10 0x000
+#define MX25_PAD_SD1_CLK__CSPI2_MISO            0x194 0x38c 0x49c 0x11 0x001
 #define MX25_PAD_SD1_CLK__FEC_RDATA3            0x194 0x38c 0x510 0x12 0x002
 #define MX25_PAD_SD1_CLK__GPIO_2_24             0x194 0x38c 0x000 0x15 0x000
 
 #define MX25_PAD_SD1_DATA0__SD1_DATA0           0x198 0x390 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA0__CSPI2_SCLK          0x198 0x390 0x494 0x11 0x001
 #define MX25_PAD_SD1_DATA0__GPIO_2_25           0x198 0x390 0x000 0x15 0x000
 
 #define MX25_PAD_SD1_DATA1__SD1_DATA1           0x19c 0x394 0x000 0x10 0x000
@@ -457,14 +485,15 @@
 #define MX25_PAD_GPIO_C__CAN2_TX                0x1fc 0x3f8 0x000 0x16 0x000
 
 #define MX25_PAD_GPIO_D__GPIO_D                 0x200 0x3fc 0x000 0x10 0x000
-#define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x02 0x000
 #define MX25_PAD_GPIO_D__CAN2_RX                0x200 0x3fc 0x484 0x16 0x001
 
 #define MX25_PAD_GPIO_E__GPIO_E                 0x204 0x400 0x000 0x10 0x000
-#define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x02 0x000
+#define MX25_PAD_GPIO_E__I2C3_CLK               0x204 0x400 0x524 0x11 0x002
+#define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x12 0x000
 #define MX25_PAD_GPIO_E__AUD7_TXD               0x204 0x400 0x000 0x14 0x000
 
 #define MX25_PAD_GPIO_F__GPIO_F                 0x208 0x404 0x000 0x10 0x000
+#define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x12 0x000
 #define MX25_PAD_GPIO_F__AUD7_TXC               0x208 0x404 0x000 0x14 0x000
 
 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK         0x20c 0x000 0x000 0x10 0x000
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index c1740396b2c9..58d3c3cf2923 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -239,6 +239,7 @@
                         };
 
                         ssi2: ssi@50014000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
                                 reg = <0x50014000 0x4000>;
                                 interrupts = <11>;
@@ -274,6 +275,7 @@
                         };
 
                         ssi1: ssi@50034000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
                                 reg = <0x50034000 0x4000>;
                                 interrupts = <12>;
@@ -453,7 +455,7 @@
                         };
 
                         sdma: sdma@53fd4000 {
-                                compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
+                                compatible = "fsl,imx25-sdma";
                                 reg = <0x53fd4000 0x4000>;
                                 clocks = <&clks 112>, <&clks 68>;
                                 clock-names = "ipg", "ahb";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 2b6d489dae69..da306c5dd678 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -67,6 +67,16 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
         status = "okay";
+
+        adc@0 {
+                compatible = "maxim,max1027";
+                reg = <0>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_max1027>;
+                spi-max-frequency = <10000000>;
+        };
 };
 
 &cspi2 {
@@ -189,6 +199,13 @@
                         >;
                 };
 
+                pinctrl_max1027: max1027 {
+                         fsl,pins = <
+                                 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
+                                 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
+                        >;
+                };
+
                 pinctrl_pwm: pwmgrp {
                         fsl,pins = <
                                 MX27_PAD_PWMO__PWMO 0x0
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 221cac4fb2cd..1f38a052ad4b 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -83,10 +83,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&lcdif_16bit_pins_a
                                                 &lcdif_pins_apf28dev>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <16>;
                                         bus-width = <16>;
 
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index e1ce9179db63..1092b761d7ac 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -94,10 +94,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&lcdif_24bit_pins_a
                                              &lcdif_pins_apx4>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <24>;
 
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 7d51459de5e8..ef944b6d4f01 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -177,10 +177,10 @@
                                 pinctrl-0 = <&lcdif_18bit_pins_cfa10049
                                              &lcdif_pins_cfa10049
                                              &lcdif_pins_cfa10049_pullup>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <18>;
 
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
index c3900e7ba331..6a34114bec29 100644
--- a/arch/arm/boot/dts/imx28-cfa10055.dts
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -92,10 +92,10 @@
                                 pinctrl-0 = <&lcdif_18bit_pins_cfa10055
                                              &lcdif_pins_cfa10055
                                              &lcdif_pins_cfa10055_pullup>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <18>;
 
diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts
index cef959a97219..ba6495ca44d2 100644
--- a/arch/arm/boot/dts/imx28-cfa10056.dts
+++ b/arch/arm/boot/dts/imx28-cfa10056.dts
@@ -64,10 +64,10 @@
                                 pinctrl-0 = <&lcdif_24bit_pins_a
                                                 &lcdif_pins_cfa10056
                                                 &lcdif_pins_cfa10056_pullup >;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <24>;
 
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index c4e00ce4b6da..5df0b24eaf59 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -78,10 +78,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&lcdif_18bit_pins_cfa10057
                                              &lcdif_pins_cfa10057>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <18>;
 
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 7c9cc783f0d1..f5c6dce34abe 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -51,10 +51,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&lcdif_24bit_pins_a
                                                  &lcdif_pins_cfa10058>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <24>;
 
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index e4cc44c98585..09664fcf5afb 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -124,10 +124,10 @@
                                 pinctrl-0 = <&lcdif_24bit_pins_a
                                              &lcdif_pins_evk>;
                                 lcd-supply = <&reg_lcd_3v3>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <24>;
 
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 9348ce59dda4..2df63bee6f4e 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -115,10 +115,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&lcdif_24bit_pins_a
                                              &lcdif_pins_m28>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display0 {
+                                display0: display0 {
                                         bits-per-pixel = <32>;
                                         bus-width = <24>;
 
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index b3c09ae3b928..e35cc6ba3ca6 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -81,10 +81,10 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&lcdif_24bit_pins_a
                                              &lcdif_pins_m28>;
-                                display = <&display>;
+                                display = <&display0>;
                                 status = "okay";
 
-                                display: display {
+                                display0: display0 {
                                         bits-per-pixel = <16>;
                                         bus-width = <18>;
 
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index e14bd86f3e99..a5b27c85a91c 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -21,12 +21,15 @@
         aliases {
                 can0 = &can0;
                 can1 = &can1;
-                display = &display;
+                display = &display0;
                 ds1339 = &ds1339;
                 gpio5 = &gpio5;
                 lcdif = &lcdif;
                 lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
                 lcdif_24bit_pins = &lcdif_24bit_pins_a;
+                reg_can_xcvr = &reg_can_xcvr;
+                spi_gpio = &spi_gpio;
+                spi_mxs = &ssp3;
                 stk5led = &user_led;
                 usbotg = &usb0;
         };
@@ -37,7 +40,7 @@
 
         onewire {
                 compatible = "w1-gpio";
-                gpios = <&gpio2 7 0>;
+                gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
                 status = "disabled";
         };
 
@@ -52,7 +55,7 @@
                         regulator-name = "usb0_vbus";
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio0 18 0>;
+                        gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -62,7 +65,7 @@
                         regulator-name = "usb1_vbus";
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio3 27 0>;
+                        gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -90,7 +93,7 @@
                         regulator-name = "CAN XCVR";
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
-                        gpio = <&gpio1 0 0>;
+                        gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
                 };
@@ -101,7 +104,7 @@
                         regulator-name = "LCD POWER";
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
-                        gpio = <&gpio1 31 0>;
+                        gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -111,7 +114,7 @@
                         regulator-name = "LCD RESET";
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
-                        gpio = <&gpio3 30 0>;
+                        gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
                         startup-delay-us = <300000>;
                         enable-active-high;
                         regulator-always-on;
@@ -143,7 +146,7 @@
 
                 user_led: user {
                         label = "Heartbeat";
-                        gpios = <&gpio4 10 0>;
+                        gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
         };
@@ -172,16 +175,16 @@
         matrix_keypad: matrix-keypad@0 {
                 compatible = "gpio-matrix-keypad";
                 col-gpios = <
-                        &gpio5 0 0
-                        &gpio5 1 0
-                        &gpio5 2 0
-                        &gpio5 3 0
+                        &gpio5 0 GPIO_ACTIVE_HIGH
+                        &gpio5 1 GPIO_ACTIVE_HIGH
+                        &gpio5 2 GPIO_ACTIVE_HIGH
+                        &gpio5 3 GPIO_ACTIVE_HIGH
                 >;
                 row-gpios = <
-                        &gpio5 4 0
-                        &gpio5 5 0
-                        &gpio5 6 0
-                        &gpio5 7 0
+                        &gpio5 4 GPIO_ACTIVE_HIGH
+                        &gpio5 5 GPIO_ACTIVE_HIGH
+                        &gpio5 6 GPIO_ACTIVE_HIGH
+                        &gpio5 7 GPIO_ACTIVE_HIGH
                 >;
                 /* sample keymap */
                 linux,keymap = <
@@ -203,6 +206,44 @@
                 col-scan-delay-us = <5000>;
                 linux,no-autorepeat;
         };
+
+        spi_gpio: spi-gpio {
+                compatible = "spi-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tx28_spi_gpio_pins>;
+
+                gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+                gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+                gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+                num-chipselects = <3>;
+                cs-gpios = <
+                        &gpio2 27 GPIO_ACTIVE_LOW
+                        &gpio3 8 GPIO_ACTIVE_LOW
+                        &gpio3 9 GPIO_ACTIVE_LOW
+                >;
+                /* enable this and disable ssp3 below, if you need full duplex SPI transfer */
+                status = "disabled";
+
+                spi@0 {
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <57600000>;
+                };
+
+                spi@1 {
+                        compatible = "spidev";
+                        reg = <1>;
+                        spi-max-frequency = <57600000>;
+                };
+
+                spi@2 {
+                        compatible = "spidev";
+                        reg = <2>;
+                        spi-max-frequency = <57600000>;
+                };
+        };
 };
 
 /* 2nd TX-Std UART - (A)UART1  */
@@ -284,8 +325,8 @@
                 pinctrl-0 = <&tx28_edt_ft5x06_pins>;
                 interrupt-parent = <&gpio2>;
                 interrupts = <5 0>;
-                reset-gpios = <&gpio2 6 1>;
-                wake-gpios = <&gpio4 9 0>;
+                reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+                wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
         };
 
         touchscreen: tsc2007@48 {
@@ -295,7 +336,7 @@
                 pinctrl-0 = <&tx28_tsc2007_pins>;
                 interrupt-parent = <&gpio3>;
                 interrupts = <20 0>;
-                pendown-gpio = <&gpio3 20 1>;
+                pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
                 ti,x-plate-ohms = /bits/ 16 <660>;
         };
 
@@ -309,10 +350,10 @@
         pinctrl-names = "default";
         pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>;
         lcd-supply = <&reg_lcd>;
-        display = <&display>;
+        display = <&display0>;
         status = "okay";
 
-        display: display@0 {
+        display0: display0 {
                 bits-per-pixel = <32>;
                 bus-width = <24>;
                 display-timings {
@@ -558,6 +599,20 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
+        tx28_spi_gpio_pins: spi-gpiogrp {
+                fsl,pinmux-ids = <
+                        MX28_PAD_AUART2_RX__GPIO_3_8
+                        MX28_PAD_AUART2_TX__GPIO_3_9
+                        MX28_PAD_SSP3_SCK__GPIO_2_24
+                        MX28_PAD_SSP3_MOSI__GPIO_2_25
+                        MX28_PAD_SSP3_MISO__GPIO_2_26
+                        MX28_PAD_SSP3_SS0__GPIO_2_27
+                >;
+                fsl,drive-strength = <MXS_DRIVE_8mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+
         tx28_tsc2007_pins: tx28-tsc2007-pins {
                 fsl,pinmux-ids = <
                         MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
@@ -619,17 +674,23 @@
         clock-frequency = <57600000>;
         status = "okay";
 
-        spidev0: spi@0 {
+        spi@0 {
                 compatible = "spidev";
                 reg = <0>;
                 spi-max-frequency = <57600000>;
         };
 
-        spidev1: spi@1 {
+        spi@1 {
                 compatible = "spidev";
                 reg = <1>;
                 spi-max-frequency = <57600000>;
         };
+
+        spi@2 {
+                compatible = "spidev";
+                reg = <2>;
+                spi-max-frequency = <57600000>;
+        };
 };
 
 &usb0 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index a95cc5358ff4..47f68ac868d4 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -489,6 +489,38 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
+                                mmc1_4bit_pins_a: mmc1-4bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_D00__SSP1_D0
+                                                MX28_PAD_GPMI_D01__SSP1_D1
+                                                MX28_PAD_GPMI_D02__SSP1_D2
+                                                MX28_PAD_GPMI_D03__SSP1_D3
+                                                MX28_PAD_GPMI_RDY1__SSP1_CMD
+                                                MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
+                                                MX28_PAD_GPMI_WRN__SSP1_SCK
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
+
+                                mmc1_cd_cfg: mmc1-cd-cfg {
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
+                                        >;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mmc1_sck_cfg: mmc1-sck-cfg {
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_WRN__SSP1_SCK
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_12mA>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+
                                 mmc2_4bit_pins_a: mmc2-4bit@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -553,6 +585,17 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
+                                i2c1_pins_b: i2c1@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_AUART2_CTS__I2C1_SCL
+                                                MX28_PAD_AUART2_RTS__I2C1_SDA
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
+
                                 saif0_pins_a: saif0@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 442e216ca9d9..6932928f3b45 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -114,6 +114,7 @@
                         };
 
                         ssi1: ssi@43fa0000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
                                 reg = <0x43fa0000 0x4000>;
                                 interrupts = <11>;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index c0e0f60ab6b2..620b0f030591 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -145,6 +145,7 @@
                                 };
 
                                 ssi2: ssi@50014000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx50-ssi",
                                                         "fsl,imx51-ssi",
                                                         "fsl,imx21-ssi";
@@ -454,6 +455,7 @@
                         };
 
                         ssi1: ssi@63fcc000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
                                                         "fsl,imx21-ssi";
                                 reg = <0x63fcc000 0x4000>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 17c05a6fa776..92660e1fe1fc 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -210,6 +210,7 @@
                                 };
 
                                 ssi2: ssi@70014000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                         reg = <0x70014000 0x4000>;
                                         interrupts = <30>;
@@ -499,6 +500,7 @@
                         };
 
                         ssi1: ssi@83fcc000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fcc000 0x4000>;
                                 interrupts = <29>;
@@ -554,6 +556,7 @@
                         };
 
                         ssi3: ssi@83fe8000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fe8000 0x4000>;
                                 interrupts = <96>;
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
index f1bbf9a32991..82d623d05915 100644
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -28,6 +28,12 @@
                                 MX53_PAD_CSI0_DAT9__I2C1_SCL      0x400001ec
                         >;
                 };
+
+                pinctrl_pmic: pmicgrp {
+                        fsl,pins = <
+                                MX53_PAD_CSI0_DAT5__GPIO5_23    0x1e4 /* IRQ */
+                        >;
+                };
         };
 };
 
@@ -38,6 +44,8 @@
 
         pmic: mc34708@8 {
                 compatible = "fsl,mc34708";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pmic>;
                 reg = <0x08>;
                 interrupt-parent = <&gpio5>;
                 interrupts = <23 0x8>;
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 5ec1590ff7bc..1d325576bcc0 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -265,7 +265,7 @@
         };
 
         pmic: dialog@48 {
-                compatible = "dialog,da9053", "dialog,da9052";
+                compatible = "dlg,da9053", "dlg,da9052";
                 reg = <0x48>;
         };
 };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 64fa27b36be0..f91725b2e8ab 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -221,6 +221,7 @@
                                 };
 
                                 ssi2: ssi@50014000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx53-ssi",
                                                         "fsl,imx51-ssi",
                                                         "fsl,imx21-ssi";
@@ -423,10 +424,14 @@
                                 status = "disabled";
 
                                 lvds-channel@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
                                         reg = <0>;
                                         status = "disabled";
 
-                                        port {
+                                        port@0 {
+                                                reg = <0>;
+
                                                 lvds0_in: endpoint {
                                                         remote-endpoint = <&ipu_di0_lvds0>;
                                                 };
@@ -434,10 +439,14 @@
                                 };
 
                                 lvds-channel@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
                                         reg = <1>;
                                         status = "disabled";
 
-                                        port {
+                                        port@1 {
+                                                reg = <1>;
+
                                                 lvds1_in: endpoint {
                                                         remote-endpoint = <&ipu_di1_lvds1>;
                                                 };
@@ -661,6 +670,7 @@
                         };
 
                         ssi1: ssi@63fcc000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
                                                 "fsl,imx21-ssi";
                                 reg = <0x63fcc000 0x4000>;
@@ -688,6 +698,7 @@
                         };
 
                         ssi3: ssi@63fe8000 {
+                                #sound-dai-cells = <0>;
                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
                                                 "fsl,imx21-ssi";
                                 reg = <0x63fe8000 0x4000>;
@@ -731,7 +742,7 @@
                                 compatible = "fsl,imx53-vpu";
                                 reg = <0x63ff4000 0x1000>;
                                 interrupts = <9>;
-                                clocks = <&clks IMX5_CLK_VPU_GATE>,
+                                clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
                                          <&clks IMX5_CLK_VPU_GATE>;
                                 clock-names = "per", "ahb";
                                 resets = <&src 1>;
@@ -744,5 +755,10 @@
                         reg = <0xf8000000 0x20000>;
                         clocks = <&clks IMX5_CLK_OCRAM>;
                 };
+
+                pmu {
+                        compatible = "arm,cortex-a8-pmu";
+                        interrupts = <77>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/imx6dl-gw552x.dts
new file mode 100644
index 000000000000..a4b700cef188
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw552x.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw552x.dtsi"
+
+/ {
+        model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
+        compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index c8e51dd41b8f..44a0e6736bb1 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,204 +1,13 @@
 /*
- * Copyright (C) 2013,2014 Russell King
+ * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
+ * Based on dt work by Russell King
  */
 /dts-v1/;
 
 #include "imx6dl.dtsi"
-#include "imx6qdl-microsom.dtsi"
-#include "imx6qdl-microsom-ar8035.dtsi"
+#include "imx6qdl-hummingboard.dtsi"
 
 / {
-        model = "SolidRun HummingBoard DL/Solo";
-        compatible = "solidrun,hummingboard", "fsl,imx6dl";
-
-        chosen {
-                stdout-path = &uart1;
-        };
-
-        ir_recv: ir-receiver {
-                compatible = "gpio-ir-receiver";
-                gpios = <&gpio1 2 1>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
-        };
-
-        regulators {
-                compatible = "simple-bus";
-
-                reg_3p3v: 3p3v {
-                        compatible = "regulator-fixed";
-                        regulator-name = "3P3V";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                };
-
-                reg_usbh1_vbus: usb-h1-vbus {
-                        compatible = "regulator-fixed";
-                        enable-active-high;
-                        gpio = <&gpio1 0 0>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
-                        regulator-name = "usb_h1_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                };
-
-                reg_usbotg_vbus: usb-otg-vbus {
-                        compatible = "regulator-fixed";
-                        enable-active-high;
-                        gpio = <&gpio3 22 0>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
-                        regulator-name = "usb_otg_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                };
-        };
-
-        sound-spdif {
-                compatible = "fsl,imx-audio-spdif";
-                model = "imx-spdif";
-                /* IMX6 doesn't implement this yet */
-                spdif-controller = <&spdif>;
-                spdif-out;
-        };
-};
-
-&can1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
-        status = "okay";
-};
-
-&hdmi {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
-        ddc-i2c-bus = <&i2c2>;
-        status = "okay";
-};
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
-
-        /*
-         * Not fitted on Carrier-1 board... yet
-        status = "okay";
-
-        rtc: pcf8523@68 {
-                compatible = "nxp,pcf8523";
-                reg = <0x68>;
-        };
-         */
-};
-
-&i2c2 {
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
-        status = "okay";
-};
-
-&iomuxc {
-        hummingboard {
-                pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
-                        fsl,pins = <
-                                MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
-                                MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
-                        >;
-                };
-
-                pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
-                        fsl,pins = <
-                                MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
-                        >;
-                };
-
-                pinctrl_hummingboard_hdmi: hummingboard-hdmi {
-                        fsl,pins = <
-                                MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-                        >;
-                };
-
-                pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
-                                MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
-                        >;
-                };
-
-                pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
-                        fsl,pins = <
-                                MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
-                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-                        >;
-                };
-
-                pinctrl_hummingboard_spdif: hummingboard-spdif {
-                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
-                };
-
-                pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
-                        fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
-                };
-
-                pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
-                        /*
-                         * Similar to pinctrl_usbotg_2, but we want it
-                         * pulled down for a fixed host connection.
-                         */
-                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
-                };
-
-                pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
-                        fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
-                };
-
-                pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
-                        fsl,pins = <
-                                MX6QDL_PAD_GPIO_4__GPIO1_IO04    0x1f071
-                        >;
-                };
-
-                pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
-                        fsl,pins = <
-                                MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
-                                MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
-                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
-                        >;
-                };
-        };
-};
-
-&spdif {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hummingboard_spdif>;
-        status = "okay";
-};
-
-&usbh1 {
-        vbus-supply = <&reg_usbh1_vbus>;
-        status = "okay";
-};
-
-&usbotg {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
-        vbus-supply = <&reg_usbotg_vbus>;
-        status = "okay";
-};
-
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <
-                &pinctrl_hummingboard_usdhc2_aux
-                &pinctrl_hummingboard_usdhc2
-        >;
-        vmmc-supply = <&reg_3p3v>;
-        cd-gpios = <&gpio1 4 0>;
-        status = "okay";
+        model = "SolidRun HummingBoard Solo/DualLite";
+        compatible = "solidrun,hummingboard/dl", "fsl,imx6dl";
 };
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index 8c1cb53464a0..4fa254347798 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -119,7 +119,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
         phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio3 23 0>;
+        phy-reset-gpios = <&gpio1 25 0>;
         phy-supply = <&vgen2_1v2_eth>;
         status = "okay";
 };
@@ -339,6 +339,7 @@
                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0
                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
                         >;
                 };
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 22e6f8e657d2..822ffb231c57 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -10,6 +10,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "imx6q.dtsi"
 
 / {
@@ -18,7 +19,6 @@
 
         /* these are used by bootloader for disabling nodes */
         aliases {
-                ethernet0 = &fec;
                 ethernet1 = &eth1;
                 i2c0 = &i2c1;
                 i2c1 = &i2c2;
@@ -26,12 +26,10 @@
                 led0 = &led0;
                 led1 = &led1;
                 led2 = &led2;
-                sky2 = &eth1;
                 ssi0 = &ssi1;
                 spi0 = &ecspi1;
                 usb0 = &usbh1;
                 usb1 = &usbotg;
-                usdhc2 = &usdhc3;
         };
 
         chosen {
@@ -40,23 +38,25 @@
 
         leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
 
                 led0: user1 {
                         label = "user1";
-                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */
                         default-state = "on";
                         linux,default-trigger = "heartbeat";
                 };
 
                 led1: user2 {
                         label = "user2";
-                        gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */
+                        gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */
                         default-state = "off";
                 };
 
                 led2: user3 {
                         label = "user3";
-                        gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */
                         default-state = "off";
                 };
         };
@@ -67,7 +67,9 @@
 
         pps {
                 compatible = "pps-gpio";
-                gpios = <&gpio1 5 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+                gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                 status = "okay";
         };
 
@@ -109,7 +111,7 @@
                         regulator-name = "usb_otg_vbus";
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio3 22 0>;
+                        gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -137,7 +139,7 @@
 
 &ecspi1 {
         fsl,spi-num-chipselects = <1>;
-        cs-gpios = <&gpio3 19 0>;
+        cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_ecspi1>;
         status = "okay";
@@ -153,7 +155,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
         phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio1 30 0>;
+        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
         status = "okay";
 };
 
@@ -199,11 +201,6 @@
                 #gpio-cells = <2>;
         };
 
-        hwmon: gsc@29 {
-                compatible = "gw,gsp";
-                reg = <0x29>;
-        };
-
         rtc: ds1672@68 {
                 compatible = "dallas,ds1672";
                 reg = <0x68>;
@@ -314,16 +311,6 @@
                         };
                 };
         };
-
-        pciswitch: pex8609@3f {
-                compatible = "plx,pex8609";
-                reg = <0x3f>;
-        };
-
-        pciclkgen: si52147@6b {
-                compatible = "sil,si52147";
-                reg = <0x6b>;
-        };
 };
 
 &i2c3 {
@@ -345,51 +332,73 @@
                 VDDIO-supply = <&reg_3p3v>;
         };
 
-        hdmiin: adv7611@4c {
-                compatible = "adi,adv7611";
-                reg = <0x4c>;
-        };
-
         touchscreen: egalax_ts@04 {
                 compatible = "eeti,egalax_ts";
                 reg = <0x04>;
                 interrupt-parent = <&gpio7>;
-                interrupts = <12 2>; /* gpio7_12 active low */
-                wakeup-gpios = <&gpio7 12 0>;
+                interrupts = <12 2>;
+                wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
         };
+};
 
-        videoout: adv7393@2a {
-                compatible = "adi,adv7393";
-                reg = <0x2a>;
-        };
+&ldb {
+        status = "okay";
+};
+
+&pcie {
+        reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+        status = "okay";
 
-        videoin: adv7180@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
+        eth1: sky2@8 { /* MAC/PHY on bus 8 */
+                compatible = "marvell,sky2";
         };
 };
 
-&iomuxc {
+&ssi1 {
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+
+&usdhc3 {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
 
+&iomuxc {
         imx6q-gw5400-a {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
-                                MX6QDL_PAD_EIM_D19__GPIO3_IO19    0x80000000 /* SPINOR_CS0# */
-                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
-                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
-                                MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
-                                MX6QDL_PAD_GPIO_5__GPIO1_IO05     0x80000000 /* GPS_PPS */
-                                MX6QDL_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* TOUCH_IRQ# */
-                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
-                                MX6QDL_PAD_KEY_COL2__GPIO4_IO10   0x80000000 /* user2 led */
-                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
-                                MX6QDL_PAD_SD1_DAT0__GPIO1_IO16   0x80000000 /* USBHUB_RST# */
-                                MX6QDL_PAD_SD1_DAT3__GPIO1_IO21   0x80000000 /* MIPI_DIO */
-                         >;
-                };
 
                 pinctrl_audmux: audmuxgrp {
                         fsl,pins = <
@@ -397,6 +406,7 @@
                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
                         >;
                 };
 
@@ -405,6 +415,7 @@
                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0 /* SPINOR_CS0# */
                         >;
                 };
 
@@ -429,6 +440,14 @@
                         >;
                 };
 
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0 /* user1 led */
+                                MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0 /* user2 led */
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0 /* user3 led */
+                        >;
+                };
+
                 pinctrl_i2c1: i2c1grp {
                         fsl,pins = <
                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
@@ -450,6 +469,19 @@
                         >;
                 };
 
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
+                        >;
+                };
+
+                pinctrl_pps: ppsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b0 /* GPS_PPS */
+                        >;
+                };
+
                 pinctrl_uart1: uart1grp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
@@ -474,6 +506,7 @@
                 pinctrl_usbotg: usbotggrp {
                         fsl,pins = <
                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
                         >;
                 };
 
@@ -489,59 +522,3 @@
                 };
         };
 };
-
-&ldb {
-        status = "okay";
-};
-
-&pcie {
-        reset-gpio = <&gpio1 29 0>;
-        status = "okay";
-
-        eth1: sky2@8 { /* MAC/PHY on bus 8 */
-                compatible = "marvell,sky2";
-        };
-};
-
-&ssi1 {
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-        status = "okay";
-};
-
-&uart5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        status = "okay";
-};
-
-&usbotg {
-        vbus-supply = <&reg_usb_otg_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg>;
-        disable-over-current;
-        status = "okay";
-};
-
-&usbh1 {
-        vbus-supply = <&reg_usb_h1_vbus>;
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3>;
-        cd-gpios = <&gpio7 0 0>;
-        vmmc-supply = <&reg_3p3v>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/imx6q-gw552x.dts
new file mode 100644
index 000000000000..f87a8fa6e04d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw552x.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2014 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-gw552x.dtsi"
+
+/ {
+        model = "Gateworks Ventana i.MX6 Dual/Quad GW552X";
+        compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q";
+};
+
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
new file mode 100644
index 000000000000..c2bf8476ce45
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
+ * Based on dt work by Russell King
+ */
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-hummingboard.dtsi"
+
+/ {
+        model = "SolidRun HummingBoard Dual/Quad";
+        compatible = "solidrun,hummingboard/q", "fsl,imx6q";
+};
+
+&sata {
+        status = "okay";
+        fsl,transmit-level-mV = <1025>;
+        fsl,transmit-boost-mdB = <3330>;
+        fsl,transmit-atten-16ths = <9>;
+        fsl,receive-eq-mdB = <3000>;
+};
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index e8e781656b3f..6a524ca011e7 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -61,7 +61,7 @@
 
         sound-spdif {
                 compatible = "fsl,imx-audio-spdif";
-                model = "imx-spdif";
+                model = "Integrated SPDIF";
                 /* IMX6 doesn't implement this yet */
                 spdif-controller = <&spdif>;
                 spdif-out;
@@ -130,16 +130,23 @@
                         fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                 };
 
+                pinctrl_cubox_i_usbh1: cubox-i-usbh1 {
+                        fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>;
+                };
+
                 pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
                         fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
                 };
 
-                pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id {
+                pinctrl_cubox_i_usbotg: cubox-i-usbotg {
                         /*
-                         * The Cubox-i pulls this low, but as it's pointless
+                         * The Cubox-i pulls ID low, but as it's pointless
                          * leaving it as a pull-up, even if it is just 10uA.
                          */
-                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
+                                MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+                        >;
                 };
 
                 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
@@ -173,13 +180,15 @@
 };
 
 &usbh1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_usbh1>;
         vbus-supply = <&reg_usbh1_vbus>;
         status = "okay";
 };
 
 &usbotg {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>;
+        pinctrl-0 = <&pinctrl_cubox_i_usbotg>;
         vbus-supply = <&reg_usbotg_vbus>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 0db15af41cb1..f2867c4b34a8 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -9,11 +9,11 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
         /* these are used by bootloader for disabling nodes */
         aliases {
-                can0 = &can1;
-                ethernet0 = &fec;
                 led0 = &led0;
                 led1 = &led1;
                 nand = &gpmi;
@@ -27,17 +27,19 @@
 
         leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
 
                 led0: user1 {
                         label = "user1";
-                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
                         default-state = "on";
                         linux,default-trigger = "heartbeat";
                 };
 
                 led1: user2 {
                         label = "user2";
-                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
                         default-state = "off";
                 };
         };
@@ -48,7 +50,9 @@
 
         pps {
                 compatible = "pps-gpio";
-                gpios = <&gpio1 26 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pps>;
+                gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
                 status = "okay";
         };
 
@@ -81,7 +85,7 @@
                         regulator-name = "usb_otg_vbus";
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio3 22 0>;
+                        gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -91,7 +95,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
         phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio1 30 0>;
+        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
@@ -143,11 +147,6 @@
                 #gpio-cells = <2>;
         };
 
-        hwmon: gsc@29 {
-                compatible = "gw,gsp";
-                reg = <0x29>;
-        };
-
         rtc: ds1672@68 {
                 compatible = "dallas,ds1672";
                 reg = <0x68>;
@@ -159,53 +158,6 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c2>;
         status = "okay";
-
-        pmic: ltc3676@3c {
-                compatible = "lltc,ltc3676";
-                reg = <0x3c>;
-
-                regulators {
-                        sw1_reg: ltc3676__sw1 {
-                                regulator-min-microvolt = <1175000>;
-                                regulator-max-microvolt = <1175000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sw2_reg: ltc3676__sw2 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sw3_reg: ltc3676__sw3 {
-                                regulator-min-microvolt = <1175000>;
-                                regulator-max-microvolt = <1175000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sw4_reg: ltc3676__sw4 {
-                                regulator-min-microvolt = <1500000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo2_reg: ltc3676__ldo2 {
-                                regulator-min-microvolt = <2500000>;
-                                regulator-max-microvolt = <2500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo4_reg: ltc3676__ldo4 {
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                        };
-                };
-        };
 };
 
 &i2c3 {
@@ -213,31 +165,53 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c3>;
         status = "okay";
+};
 
-        videoin: adv7180@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
-        };
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+        status = "okay";
 };
 
-&iomuxc {
+&uart1 {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
 
-        imx6qdl-gw51xx {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                                MX6QDL_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                                MX6QDL_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
-                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                                MX6QDL_PAD_GPIO_0__GPIO1_IO00    0x80000000 /* PCIE_RST# */
-                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                         >;
-                };
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
 
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&iomuxc {
+        imx6qdl-gw51xx {
                 pinctrl_enet: enetgrp {
                         fsl,pins = <
                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
@@ -256,6 +230,14 @@
                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0 /* PHY Reset */
+                        >;
+                };
+
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
                         >;
                 };
 
@@ -301,6 +283,18 @@
                         >;
                 };
 
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
+                        >;
+                };
+
+                pinctrl_pps: ppsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
+                        >;
+                };
+
                 pinctrl_uart1: uart1grp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
@@ -332,48 +326,8 @@
                 pinctrl_usbotg: usbotggrp {
                         fsl,pins = <
                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
                         >;
                 };
         };
 };
-
-&pcie {
-        reset-gpio = <&gpio1 0 0>;
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-        status = "okay";
-};
-
-&uart3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3>;
-        status = "okay";
-};
-
-&uart5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        status = "okay";
-};
-
-&usbotg {
-        vbus-supply = <&reg_usb_otg_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg>;
-        disable-over-current;
-        status = "okay";
-};
-
-&usbh1 {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 234e7b755232..d3c0bf5c84e3 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -9,10 +9,11 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
         /* these are used by bootloader for disabling nodes */
         aliases {
-                ethernet0 = &fec;
                 led0 = &led0;
                 led1 = &led1;
                 led2 = &led2;
@@ -20,7 +21,6 @@
                 ssi0 = &ssi1;
                 usb0 = &usbh1;
                 usb1 = &usbotg;
-                usdhc2 = &usdhc3;
         };
 
         chosen {
@@ -36,23 +36,25 @@
 
         leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
 
                 led0: user1 {
                         label = "user1";
-                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
                         default-state = "on";
                         linux,default-trigger = "heartbeat";
                 };
 
                 led1: user2 {
                         label = "user2";
-                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
                         default-state = "off";
                 };
 
                 led2: user3 {
                         label = "user3";
-                        gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
                         default-state = "off";
                 };
         };
@@ -63,7 +65,9 @@
 
         pps {
                 compatible = "pps-gpio";
-                gpios = <&gpio1 26 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pps>;
+                gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
                 status = "okay";
         };
 
@@ -115,7 +119,7 @@
                         regulator-name = "usb_otg_vbus";
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio3 22 0>;
+                        gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -141,11 +145,17 @@
         status = "okay";
 };
 
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        status = "okay";
+};
+
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
         phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio1 30 0>;
+        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
@@ -197,11 +207,6 @@
                 #gpio-cells = <2>;
         };
 
-        hwmon: gsc@29 {
-                compatible = "gw,gsp";
-                reg = <0x29>;
-        };
-
         rtc: ds1672@68 {
                 compatible = "dallas,ds1672";
                 reg = <0x68>;
@@ -213,65 +218,6 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c2>;
         status = "okay";
-
-        pciswitch: pex8609@3f {
-                compatible = "plx,pex8609";
-                reg = <0x3f>;
-        };
-
-        pmic: ltc3676@3c {
-                compatible = "lltc,ltc3676";
-                reg = <0x3c>;
-
-                regulators {
-                        sw1_reg: ltc3676__sw1 {
-                                regulator-min-microvolt = <1175000>;
-                                regulator-max-microvolt = <1175000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sw2_reg: ltc3676__sw2 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sw3_reg: ltc3676__sw3 {
-                                regulator-min-microvolt = <1175000>;
-                                regulator-max-microvolt = <1175000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        sw4_reg: ltc3676__sw4 {
-                                regulator-min-microvolt = <1500000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo2_reg: ltc3676__ldo2 {
-                                regulator-min-microvolt = <2500000>;
-                                regulator-max-microvolt = <2500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo3_reg: ltc3676__ldo3 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        ldo4_reg: ltc3676__ldo4 {
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                        };
-                };
-        };
 };
 
 &i2c3 {
@@ -280,11 +226,6 @@
         pinctrl-0 = <&pinctrl_i2c3>;
         status = "okay";
 
-        accelerometer: fxos8700@1e {
-                compatible = "fsl,fxos8700";
-                reg = <0x13>;
-        };
-
         codec: sgtl5000@0a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
@@ -297,49 +238,101 @@
                 compatible = "eeti,egalax_ts";
                 reg = <0x04>;
                 interrupt-parent = <&gpio7>;
-                interrupts = <12 2>; /* gpio7_12 active low */
-                wakeup-gpios = <&gpio7 12 0>;
+                interrupts = <12 2>;
+                wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
         };
+};
+
+&ldb {
+        status = "okay";
 
-        videoin: adv7180@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
         };
 };
 
-&iomuxc {
+&pcie {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
 
-        imx6qdl-gw52xx {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
-                                MX6QDL_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
-                                MX6QDL_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
-                                MX6QDL_PAD_EIM_D31__GPIO3_IO31   0x80000000 /* VIDDEC_PDN# */
-                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
-                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
-                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
-                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
-                                MX6QDL_PAD_GPIO_0__CCM_CLKO1     0x000130b0 /* AUD4_MCK */
-                                MX6QDL_PAD_GPIO_2__GPIO1_IO02    0x80000000 /* USB_SEL_PCI */
-                                MX6QDL_PAD_GPIO_17__GPIO7_IO12   0x80000000 /* TOUCH_IRQ# */
-                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
-                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
-                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x80000000 /* user3 led */
-                                MX6QDL_PAD_SD2_CMD__GPIO1_IO11   0x80000000 /* LVDS_TCH# */
-                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00  0x80000000 /* SD3_CD# */
-                                MX6QDL_PAD_SD4_DAT3__GPIO2_IO11  0x80000000 /* UART2_EN# */
-                         >;
-                };
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
+
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
 
+&iomuxc {
+        imx6qdl-gw52xx {
                 pinctrl_audmux: audmuxgrp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0 /* AUD4_MCK */
                         >;
                 };
 
@@ -361,6 +354,23 @@
                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0 /* PHY Reset */
+                        >;
+                };
+
+                pinctrl_flexcan1: flexcan1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
+                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
+                                MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
+                        >;
+                };
+
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
                         >;
                 };
 
@@ -406,6 +416,18 @@
                         >;
                 };
 
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE_RST# */
+                        >;
+                };
+
+                pinctrl_pps: ppsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
+                        >;
+                };
+
                 pinctrl_pwm4: pwm4grp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
@@ -436,6 +458,7 @@
                 pinctrl_usbotg: usbotggrp {
                         fsl,pins = <
                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0 /* OTG_PWR_EN */
                         >;
                 };
 
@@ -447,85 +470,8 @@
                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
                         >;
                 };
         };
 };
-
-&ldb {
-        status = "okay";
-
-        lvds-channel@0 {
-                fsl,data-mapping = "spwg";
-                fsl,data-width = <18>;
-                status = "okay";
-
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: hsd100pxn1 {
-                                clock-frequency = <65000000>;
-                                hactive = <1024>;
-                                vactive = <768>;
-                                hback-porch = <220>;
-                                hfront-porch = <40>;
-                                vback-porch = <21>;
-                                vfront-porch = <7>;
-                                hsync-len = <60>;
-                                vsync-len = <10>;
-                        };
-                };
-        };
-};
-
-&pcie {
-        reset-gpio = <&gpio1 29 0>;
-        status = "okay";
-};
-
-&pwm4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm4>;
-        status = "okay";
-};
-
-&ssi1 {
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-        status = "okay";
-};
-
-&uart5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        status = "okay";
-};
-
-&usbotg {
-        vbus-supply = <&reg_usb_otg_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg>;
-        disable-over-current;
-        status = "okay";
-};
-
-&usbh1 {
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3>;
-        cd-gpios = <&gpio7 0 0>;
-        vmmc-supply = <&reg_3p3v>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 143f84f7812c..cade1bdc97e9 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -9,21 +9,19 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
         /* these are used by bootloader for disabling nodes */
         aliases {
-                can0 = &can1;
-                ethernet0 = &fec;
                 ethernet1 = &eth1;
                 led0 = &led0;
                 led1 = &led1;
                 led2 = &led2;
                 nand = &gpmi;
-                sky2 = &eth1;
                 ssi0 = &ssi1;
                 usb0 = &usbh1;
                 usb1 = &usbotg;
-                usdhc2 = &usdhc3;
         };
 
         chosen {
@@ -39,23 +37,25 @@
 
         leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
 
                 led0: user1 {
                         label = "user1";
-                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
                         default-state = "on";
                         linux,default-trigger = "heartbeat";
                 };
 
                 led1: user2 {
                         label = "user2";
-                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
                         default-state = "off";
                 };
 
                 led2: user3 {
                         label = "user3";
-                        gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
                         default-state = "off";
                 };
         };
@@ -66,7 +66,9 @@
 
         pps {
                 compatible = "pps-gpio";
-                gpios = <&gpio1 26 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pps>;
+                gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
                 status = "okay";
         };
 
@@ -118,7 +120,7 @@
                         regulator-name = "usb_otg_vbus";
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio3 22 0>;
+                        gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -154,7 +156,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
         phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio1 30 0>;
+        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
@@ -206,11 +208,6 @@
                 #gpio-cells = <2>;
         };
 
-        hwmon: gsc@29 {
-                compatible = "gw,gsp";
-                reg = <0x29>;
-        };
-
         rtc: ds1672@68 {
                 compatible = "dallas,ds1672";
                 reg = <0x68>;
@@ -222,77 +219,6 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c2>;
         status = "okay";
-
-        pciclkgen: si53156@6b {
-                compatible = "sil,si53156";
-                reg = <0x6b>;
-        };
-
-        pciswitch: pex8606@3f {
-                compatible = "plx,pex8606";
-                reg = <0x3f>;
-        };
-
-        pmic: ltc3676@3c {
-                compatible = "lltc,ltc3676";
-                reg = <0x3c>;
-
-                regulators {
-                        /* VDD_SOC */
-                        sw1_reg: ltc3676__sw1 {
-                                regulator-min-microvolt = <1175000>;
-                                regulator-max-microvolt = <1175000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        /* VDD_1P8 */
-                        sw2_reg: ltc3676__sw2 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        /* VDD_ARM */
-                        sw3_reg: ltc3676__sw3 {
-                                regulator-min-microvolt = <1175000>;
-                                regulator-max-microvolt = <1175000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        /* VDD_DDR */
-                        sw4_reg: ltc3676__sw4 {
-                                regulator-min-microvolt = <1500000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        /* VDD_2P5 */
-                        ldo2_reg: ltc3676__ldo2 {
-                                regulator-min-microvolt = <2500000>;
-                                regulator-max-microvolt = <2500000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        /* VDD_1P8 */
-                        ldo3_reg: ltc3676__ldo3 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                        };
-
-                        /* VDD_HIGH */
-                        ldo4_reg: ltc3676__ldo4 {
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                        };
-                };
-        };
 };
 
 &i2c3 {
@@ -301,11 +227,6 @@
         pinctrl-0 = <&pinctrl_i2c3>;
         status = "okay";
 
-        accelerometer: fxos8700@1e {
-                compatible = "fsl,fxos8700";
-                reg = <0x1e>;
-        };
-
         codec: sgtl5000@0a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
@@ -314,65 +235,110 @@
                 VDDIO-supply = <&reg_3p3v>;
         };
 
-        hdmiin: adv7611@4c {
-                compatible = "adi,adv7611";
-                reg = <0x4c>;
-        };
-
         touchscreen: egalax_ts@04 {
                 compatible = "eeti,egalax_ts";
                 reg = <0x04>;
                 interrupt-parent = <&gpio1>;
-                interrupts = <11 2>; /* gpio1_11 active low */
-                wakeup-gpios = <&gpio1 11 0>;
+                interrupts = <11 2>;
+                wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
         };
+};
 
-        videoout: adv7393@2a {
-                compatible = "adi,adv7393";
-                reg = <0x2a>;
+&ldb {
+        status = "okay";
+
+        lvds-channel@1 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
         };
+};
 
-        videoin: adv7180@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+        status = "okay";
+
+        eth1: sky2@8 { /* MAC/PHY on bus 8 */
+                compatible = "marvell,sky2";
         };
 };
 
-&iomuxc {
+&pwm4 {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
 
-        imx6qdl-gw53xx {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_A19__GPIO2_IO19    0x80000000 /* PCIE6EXP_DIO0 */
-                                MX6QDL_PAD_EIM_A20__GPIO2_IO18    0x80000000 /* PCIE6EXP_DIO1 */
-                                MX6QDL_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
-                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27  0x80000000 /* GPS_SHDN */
-                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26  0x80000000 /* GPS_PPS */
-                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
-                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
-                                MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
-                                MX6QDL_PAD_GPIO_2__GPIO1_IO02     0x80000000 /* CAN_STBY */
-                                MX6QDL_PAD_GPIO_8__GPIO1_IO08     0x80000000 /* PMIC_IRQ# */
-                                MX6QDL_PAD_GPIO_9__GPIO1_IO09     0x80000000 /* HUB_RST# */
-                                MX6QDL_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* PCIE_WDIS# */
-                                MX6QDL_PAD_GPIO_19__GPIO4_IO05    0x80000000 /* ACCEL_IRQ# */
-                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
-                                MX6QDL_PAD_KEY_COL4__GPIO4_IO14   0x80000000 /* USBOTG_OC# */
-                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x80000000 /* user2 led */
-                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
-                                MX6QDL_PAD_SD2_CMD__GPIO1_IO11    0x80000000 /* TOUCH_IRQ# */
-                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00   0x80000000 /* SD3_DET# */
-                         >;
-                };
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
 
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+
+&iomuxc {
+        imx6qdl-gw53xx {
                 pinctrl_audmux: audmuxgrp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
                         >;
                 };
 
@@ -399,8 +365,17 @@
 
                 pinctrl_flexcan1: flexcan1grp {
                         fsl,pins = <
-                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x80000000
-                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x80000000
+                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
+                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
+                        >;
+                };
+
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x1b0b0
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x1b0b0
                         >;
                 };
 
@@ -446,6 +421,19 @@
                         >;
                 };
 
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x1b0b0 /* PCIE RST */
+                        >;
+                };
+
+                pinctrl_pps: ppsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
+                        >;
+                };
+
                 pinctrl_pwm4: pwm4grp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
@@ -476,6 +464,8 @@
                 pinctrl_usbotg: usbotggrp {
                         fsl,pins = <
                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
+                                MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
                         >;
                 };
 
@@ -487,90 +477,8 @@
                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0 /* CD */
                         >;
                 };
         };
 };
-
-&ldb {
-        status = "okay";
-
-        lvds-channel@1 {
-                fsl,data-mapping = "spwg";
-                fsl,data-width = <18>;
-                status = "okay";
-
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: hsd100pxn1 {
-                                clock-frequency = <65000000>;
-                                hactive = <1024>;
-                                vactive = <768>;
-                                hback-porch = <220>;
-                                hfront-porch = <40>;
-                                vback-porch = <21>;
-                                vfront-porch = <7>;
-                                hsync-len = <60>;
-                                vsync-len = <10>;
-                        };
-                };
-        };
-};
-
-&pcie {
-        reset-gpio = <&gpio1 29 0>;
-        status = "okay";
-
-        eth1: sky2@8 { /* MAC/PHY on bus 8 */
-                compatible = "marvell,sky2";
-        };
-};
-
-&pwm4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm4>;
-        status = "okay";
-};
-
-&ssi1 {
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-        status = "okay";
-};
-
-&uart5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        status = "okay";
-};
-
-&usbotg {
-        vbus-supply = <&reg_usb_otg_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg>;
-        disable-over-current;
-        status = "okay";
-};
-
-&usbh1 {
-        vbus-supply = <&reg_usb_h1_vbus>;
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3>;
-        cd-gpios = <&gpio7 0 0>;
-        vmmc-supply = <&reg_3p3v>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 16e7ad3d98ad..cf13239a1619 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -9,21 +9,19 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
         /* these are used by bootloader for disabling nodes */
         aliases {
-                can0 = &can1;
-                ethernet0 = &fec;
                 ethernet1 = &eth1;
                 led0 = &led0;
                 led1 = &led1;
                 led2 = &led2;
                 nand = &gpmi;
-                sky2 = &eth1;
                 ssi0 = &ssi1;
                 usb0 = &usbh1;
                 usb1 = &usbotg;
-                usdhc2 = &usdhc3;
         };
 
         chosen {
@@ -39,23 +37,25 @@
 
         leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
 
                 led0: user1 {
                         label = "user1";
-                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
                         default-state = "on";
                         linux,default-trigger = "heartbeat";
                 };
 
                 led1: user2 {
                         label = "user2";
-                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
                         default-state = "off";
                 };
 
                 led2: user3 {
                         label = "user3";
-                        gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
                         default-state = "off";
                 };
         };
@@ -66,7 +66,9 @@
 
         pps {
                 compatible = "pps-gpio";
-                gpios = <&gpio1 26 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pps>;
+                gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
                 status = "okay";
         };
 
@@ -108,7 +110,7 @@
                         regulator-name = "usb_otg_vbus";
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio3 22 0>;
+                        gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -144,7 +146,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
         phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio1 30 0>;
+        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
@@ -196,11 +198,6 @@
                 #gpio-cells = <2>;
         };
 
-        hwmon: gsc@29 {
-                compatible = "gw,gsp";
-                reg = <0x29>;
-        };
-
         rtc: ds1672@68 {
                 compatible = "dallas,ds1672";
                 reg = <0x68>;
@@ -311,16 +308,6 @@
                         };
                 };
         };
-
-        pciswitch: pex8609@3f {
-                compatible = "plx,pex8609";
-                reg = <0x3f>;
-        };
-
-        pciclkgen: si52147@6b {
-                compatible = "sil,si52147";
-                reg = <0x6b>;
-        };
 };
 
 &i2c3 {
@@ -329,11 +316,6 @@
         pinctrl-0 = <&pinctrl_i2c3>;
         status = "okay";
 
-        accelerometer: fxos8700@1e {
-                compatible = "fsl,fxos8700";
-                reg = <0x1e>;
-        };
-
         codec: sgtl5000@0a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
@@ -342,59 +324,115 @@
                 VDDIO-supply = <&reg_3p3v>;
         };
 
-        hdmiin: adv7611@4c {
-                compatible = "adi,adv7611";
-                reg = <0x4c>;
-        };
-
         touchscreen: egalax_ts@04 {
                 compatible = "eeti,egalax_ts";
                 reg = <0x04>;
                 interrupt-parent = <&gpio7>;
-                interrupts = <12 2>; /* gpio7_12 active low */
-                wakeup-gpios = <&gpio7 12 0>;
+                interrupts = <12 2>;
+                wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
         };
+};
 
-        videoout: adv7393@2a {
-                compatible = "adi,adv7393";
-                reg = <0x2a>;
+&ldb {
+        status = "okay";
+
+        lvds-channel@1 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
         };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+        status = "okay";
 
-        videoin: adv7180@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
+        eth1: sky2@8 { /* MAC/PHY on bus 8 */
+                compatible = "marvell,sky2";
         };
 };
 
-&iomuxc {
+&pwm4 {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
 
-        imx6qdl-gw54xx {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
-                                MX6QDL_PAD_EIM_D19__GPIO3_IO19    0x80000000 /* SPINOR_CS0# */
-                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26  0x80000000 /* GPS_PPS */
-                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
-                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
-                                MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
-                                MX6QDL_PAD_GPIO_2__GPIO1_IO02     0x80000000 /* CAN_STBY */
-                                MX6QDL_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* TOUCH_IRQ# */
-                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
-                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x80000000 /* user2 led */
-                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
-                                MX6QDL_PAD_SD1_DAT0__GPIO1_IO16   0x80000000 /* USBHUB_RST# */
-                                MX6QDL_PAD_SD1_DAT3__GPIO1_IO21   0x80000000 /* MIPI_DIO */
-                         >;
-                };
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
 
+&iomuxc {
+        imx6qdl-gw54xx {
                 pinctrl_audmux: audmuxgrp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
                         >;
                 };
 
@@ -421,8 +459,17 @@
 
                 pinctrl_flexcan1: flexcan1grp {
                         fsl,pins = <
-                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x80000000
-                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x80000000
+                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
+                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
+                        >;
+                };
+
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
                         >;
                 };
 
@@ -468,6 +515,19 @@
                         >;
                 };
 
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
+                        >;
+                };
+
+                pinctrl_pps: ppsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
+                        >;
+                };
+
                 pinctrl_pwm4: pwm4grp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
@@ -498,6 +558,7 @@
                 pinctrl_usbotg: usbotggrp {
                         fsl,pins = <
                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
                         >;
                 };
 
@@ -513,90 +574,3 @@
                 };
         };
 };
-
-&ldb {
-        status = "okay";
-
-        lvds-channel@1 {
-                fsl,data-mapping = "spwg";
-                fsl,data-width = <18>;
-                status = "okay";
-
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: hsd100pxn1 {
-                                clock-frequency = <65000000>;
-                                hactive = <1024>;
-                                vactive = <768>;
-                                hback-porch = <220>;
-                                hfront-porch = <40>;
-                                vback-porch = <21>;
-                                vfront-porch = <7>;
-                                hsync-len = <60>;
-                                vsync-len = <10>;
-                        };
-                };
-        };
-};
-
-&pcie {
-        reset-gpio = <&gpio1 29 0>;
-        status = "okay";
-
-        eth1: sky2@8 { /* MAC/PHY on bus 8 */
-                compatible = "marvell,sky2";
-        };
-};
-
-&pwm4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm4>;
-        status = "okay";
-};
-
-&ssi1 {
-        status = "okay";
-};
-
-&ssi2 {
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-        status = "okay";
-};
-
-&uart5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        status = "okay";
-};
-
-&usbotg {
-        vbus-supply = <&reg_usb_otg_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg>;
-        disable-over-current;
-        status = "okay";
-};
-
-&usbh1 {
-        vbus-supply = <&reg_usb_h1_vbus>;
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3>;
-        cd-gpios = <&gpio7 0 0>;
-        vmmc-supply = <&reg_3p3v>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
new file mode 100644
index 000000000000..5c6587f6c420
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2014 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        /* these are used by bootloader for disabling nodes */
+        aliases {
+                led0 = &led0;
+                led1 = &led1;
+                led2 = &led2;
+                nand = &gpmi;
+                usb0 = &usbh1;
+                usb1 = &usbotg;
+        };
+
+        chosen {
+                bootargs = "console=ttymxc1,115200";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+                        default-state = "off";
+                };
+
+                led2: user3 {
+                        label = "user3";
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+                        default-state = "off";
+                };
+        };
+
+        memory {
+                reg = <0x10000000 0x20000000>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                reg_1p0v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "1P0V";
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-always-on;
+                };
+
+                reg_3p3v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+
+                reg_5p0v: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "5P0V";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        status = "okay";
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+
+        gpio: pca9555@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        rtc: ds1672@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay"; };
+
+&usbh1 {
+        status = "okay";
+};
+
+&iomuxc {
+        imx6qdl-gw552x {
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
+                        >;
+                };
+
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        >;
+                };
+
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0
+                        >;
+                };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                        >;
+                };
+
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                        >;
+                };
+
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
new file mode 100644
index 000000000000..62841e85a91e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2013,2014 Russell King
+ */
+#include "imx6qdl-microsom.dtsi"
+#include "imx6qdl-microsom-ar8035.dtsi"
+
+/ {
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        ir_recv: ir-receiver {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpio3 5 1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+
+                reg_usbh1_vbus: usb-h1-vbus {
+                        compatible = "regulator-fixed";
+                        enable-active-high;
+                        gpio = <&gpio1 0 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+
+                reg_usbotg_vbus: usb-otg-vbus {
+                        compatible = "regulator-fixed";
+                        enable-active-high;
+                        gpio = <&gpio3 22 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+        };
+
+        sound-spdif {
+                compatible = "fsl,imx-audio-spdif";
+                model = "On-board SPDIF";
+                /* IMX6 doesn't implement this yet */
+                spdif-controller = <&spdif>;
+                spdif-out;
+        };
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
+        status = "okay";
+};
+
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
+
+        /*
+         * Not fitted on Carrier-1 board... yet
+        status = "okay";
+
+        rtc: pcf8523@68 {
+                compatible = "nxp,pcf8523";
+                reg = <0x68>;
+        };
+         */
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
+        status = "okay";
+};
+
+&iomuxc {
+        hummingboard {
+                pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
+                                MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
+                        >;
+                };
+
+                pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
+                        >;
+                };
+
+                pinctrl_hummingboard_hdmi: hummingboard-hdmi {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+                        >;
+                };
+
+                pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+                        >;
+                };
+
+                pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+                        >;
+                };
+
+                pinctrl_hummingboard_spdif: hummingboard-spdif {
+                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
+                };
+
+                pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
+                        fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
+                };
+
+                pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
+                        /*
+                         * Similar to pinctrl_usbotg_2, but we want it
+                         * pulled down for a fixed host connection.
+                         */
+                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+                };
+
+                pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
+                        fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
+                };
+
+                pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04    0x1f071
+                        >;
+                };
+
+                pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+                        >;
+                };
+        };
+};
+
+&spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_spdif>;
+        status = "okay";
+};
+
+&usbh1 {
+        disable-over-current;
+        vbus-supply = <&reg_usbh1_vbus>;
+        status = "okay";
+};
+
+&usbotg {
+        disable-over-current;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
+        vbus-supply = <&reg_usbotg_vbus>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &pinctrl_hummingboard_usdhc2_aux
+                &pinctrl_hummingboard_usdhc2
+        >;
+        vmmc-supply = <&reg_3p3v>;
+        cd-gpios = <&gpio1 4 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index d16066608e21..db9f45b2c573 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -17,7 +17,7 @@
         enet {
                 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
                         fsl,pins = <
-                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
                                 /* AR8035 reset */
                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x130b0
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 42ff525ebe13..08218120e770 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -174,6 +174,11 @@
         status = "okay";
 };
 
+&hdmi {
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+
 &i2c1 {
         clock-frequency = <100000>;
         pinctrl-names = "default";
@@ -187,6 +192,25 @@
                 VDDA-supply = <&reg_2p5v>;
                 VDDIO-supply = <&reg_3p3v>;
         };
+
+        rtc: rtc@6f {
+                compatible = "isil,isl1208";
+                reg = <0x6f>;
+        };
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
 };
 
 &iomuxc {
@@ -266,6 +290,20 @@
                         >;
                 };
 
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_16__I2C3_SDA            0x4001b8b1
+                        >;
+                };
+
                 pinctrl_pwm1: pwm1grp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 2694aa84e187..0e50bb0a6b94 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -83,7 +83,7 @@
         };
 
         pmic@58 {
-                compatible = "dialog,da9063";
+                compatible = "dlg,da9063";
                 reg = <0x58>;
                 interrupt-parent = <&gpio4>;
                 interrupts = <17 0x8>; /* active-low GPIO4_17 */
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index ec43dde78525..baf2f00d519a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -54,6 +54,19 @@
                         gpio = <&gpio4 10 0>;
                         enable-active-high;
                 };
+
+                reg_pcie: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_pcie_reg>;
+                        regulator-name = "MPCIE_3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 19 0>;
+                        regulator-always-on;
+                        enable-active-high;
+                };
         };
 
         gpio-keys {
@@ -314,15 +327,15 @@
         imx6qdl-sabresd {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
-                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
-                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
-                                MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+                                MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
-                                MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
-                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
-                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
-                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
+                                MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
+                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
                         >;
                 };
 
@@ -367,9 +380,9 @@
 
                 pinctrl_gpio_keys: gpio_keysgrp {
                         fsl,pins = <
-                                MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
-                                MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
-                                MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
+                                MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
+                                MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
                         >;
                 };
 
@@ -396,7 +409,13 @@
 
                 pinctrl_pcie: pciegrp {
                         fsl,pins = <
-                                MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x80000000
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0
+                        >;
+                };
+
+                pinctrl_pcie_reg: pciereggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b0b0
                         >;
                 };
 
@@ -468,7 +487,7 @@
         gpio_leds {
                 pinctrl_gpio_leds: gpioledsgrp {
                         fsl,pins = <
-                                MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index c701af958006..9596ed5867e6 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -137,7 +137,9 @@
 
                 pcie: pcie@0x01000000 {
                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
-                        reg = <0x01ffc000 0x4000>; /* DBI */
+                        reg = <0x01ffc000 0x04000>,
+                              <0x01f00000 0x80000>;
+                        reg-names = "dbi", "config";
                         #address-cells = <3>;
                         #size-cells = <2>;
                         device_type = "pci";
@@ -273,11 +275,14 @@
                                 };
 
                                 ssi1: ssi@02028000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6q-ssi",
                                                         "fsl,imx51-ssi";
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
-                                        clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
+                                        clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
+                                                 <&clks IMX6QDL_CLK_SSI1>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 37 1 0>,
                                                <&sdma 38 1 0>;
                                         dma-names = "rx", "tx";
@@ -286,11 +291,14 @@
                                 };
 
                                 ssi2: ssi@0202c000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6q-ssi",
                                                         "fsl,imx51-ssi";
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
-                                        clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
+                                        clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
+                                                 <&clks IMX6QDL_CLK_SSI2>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 41 1 0>,
                                                <&sdma 42 1 0>;
                                         dma-names = "rx", "tx";
@@ -299,11 +307,14 @@
                                 };
 
                                 ssi3: ssi@02030000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6q-ssi",
                                                         "fsl,imx51-ssi";
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
-                                        clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
+                                        clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
+                                                 <&clks IMX6QDL_CLK_SSI3>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 45 1 0>,
                                                <&sdma 46 1 0>;
                                         dma-names = "rx", "tx";
@@ -396,8 +407,9 @@
                                 reg = <0x02098000 0x4000>;
                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
-                                         <&clks IMX6QDL_CLK_GPT_IPG_PER>;
-                                clock-names = "ipg", "per";
+                                         <&clks IMX6QDL_CLK_GPT_IPG_PER>,
+                                         <&clks IMX6QDL_CLK_GPT_3M>;
+                                clock-names = "ipg", "per", "osc_per";
                         };
 
                         gpio1: gpio@0209c000 {
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 3f9e041c0252..898d14fd765f 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -20,6 +20,13 @@
                 reg = <0x80000000 0x40000000>;
         };
 
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -74,6 +81,14 @@
                         regulator-max-microvolt = <4325000>;
                         regulator-boot-on;
                 };
+
+                reg_lcd_3v3: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "lcd-3v3";
+                        gpio = <&gpio4 3 0>;
+                        enable-active-high;
+                };
         };
 
         sound {
@@ -329,12 +344,6 @@
                         >;
                 };
 
-                pinctrl_led: ledgrp {
-                        fsl,pins = <
-                                MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
-                        >;
-                };
-
                 pinctrl_kpp: kppgrp {
                         fsl,pins = <
                                 MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
@@ -346,6 +355,51 @@
                         >;
                 };
 
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
+                                MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
+                                MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
+                                MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
+                                MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
+                                MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
+                                MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
+                                MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
+                                MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
+                                MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
+                                MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
+                                MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
+                                MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
+                                MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
+                                MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
+                                MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
+                                MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
+                                MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
+                                MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
+                                MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
+                                MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
+                                MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
+                                MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
+                                MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
+                                MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
+                                MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
+                                MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
+                                MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
+                        >;
+                };
+
+                pinctrl_led: ledgrp {
+                        fsl,pins = <
+                                MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
+                        >;
+                };
+
+                pinctrl_pwm1: pwmgrp {
+                        fsl,pins = <
+                                MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
+                        >;
+                };
+
                 pinctrl_uart1: uart1grp {
                         fsl,pins = <
                                 MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x1b0b1
@@ -488,6 +542,44 @@
         status = "okay";
 };
 
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        lcd-supply = <&reg_lcd_3v3>;
+        display = <&display0>;
+        status = "okay";
+
+        display0: display0 {
+                bits-per-pixel = <32>;
+                bus-width = <24>;
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <33500000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <89>;
+                                hfront-porch = <164>;
+                                vback-porch = <23>;
+                                vfront-porch = <10>;
+                                hsync-len = <10>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
 &ssi2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c75800ca8b35..dfd83e6d8087 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -226,11 +226,14 @@
                                 };
 
                                 ssi1: ssi@02028000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6sl-ssi",
                                                         "fsl,imx51-ssi";
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
-                                        clocks = <&clks IMX6SL_CLK_SSI1>;
+                                        clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
+                                                 <&clks IMX6SL_CLK_SSI1>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 37 1 0>,
                                                <&sdma 38 1 0>;
                                         dma-names = "rx", "tx";
@@ -239,11 +242,14 @@
                                 };
 
                                 ssi2: ssi@0202c000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6sl-ssi",
                                                         "fsl,imx51-ssi";
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
-                                        clocks = <&clks IMX6SL_CLK_SSI2>;
+                                        clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
+                                                 <&clks IMX6SL_CLK_SSI2>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 41 1 0>,
                                                <&sdma 42 1 0>;
                                         dma-names = "rx", "tx";
@@ -252,11 +258,14 @@
                                 };
 
                                 ssi3: ssi@02030000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6sl-ssi",
                                                         "fsl,imx51-ssi";
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
-                                        clocks = <&clks IMX6SL_CLK_SSI3>;
+                                        clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
+                                                 <&clks IMX6SL_CLK_SSI3>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 45 1 0>,
                                                <&sdma 46 1 0>;
                                         dma-names = "rx", "tx";
@@ -529,6 +538,14 @@
                                 };
                         };
 
+                        tempmon: tempmon {
+                                compatible = "fsl,imx6q-tempmon";
+                                interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+                                fsl,tempmon = <&anatop>;
+                                fsl,tempmon-data = <&ocotp>;
+                                clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
+                        };
+
                         usbphy1: usbphy@020c9000 {
                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020c9000 0x1000>;
@@ -627,8 +644,14 @@
                         };
 
                         lcdif: lcdif@020f8000 {
+                                compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
                                 reg = <0x020f8000 0x4000>;
                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
+                                         <&clks IMX6SL_CLK_LCDIF_AXI>,
+                                         <&clks IMX6SL_CLK_DUMMY>;
+                                clock-names = "pix", "axi", "disp_axi";
+                                status = "disabled";
                         };
 
                         dcp: dcp@020fc000 {
@@ -784,7 +807,7 @@
                         };
 
                         ocotp: ocotp@021bc000 {
-                                compatible = "fsl,imx6sl-ocotp";
+                                compatible = "fsl,imx6sl-ocotp", "syscon";
                                 reg = <0x021bc000 0x4000>;
                         };
 
diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h
index 3e0b816dac08..bb9c6b78cb97 100644
--- a/arch/arm/boot/dts/imx6sx-pinfunc.h
+++ b/arch/arm/boot/dts/imx6sx-pinfunc.h
@@ -78,7 +78,7 @@
 #define MX6SX_PAD_GPIO1_IO07__USDHC2_WP                           0x0030 0x0378 0x0870 0x1 0x1
 #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO                          0x0030 0x0378 0x0770 0x2 0x0
 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK                         0x0030 0x0378 0x0000 0x3 0x0
-#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B                         0x0030 0x0378 0x082C 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B                         0x0030 0x0378 0x0000 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7                          0x0030 0x0378 0x0000 0x5 0x0
 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET                     0x0030 0x0378 0x0000 0x6 0x0
 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT                           0x0030 0x0378 0x0000 0x7 0x0
@@ -96,7 +96,7 @@
 #define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B                        0x0038 0x0380 0x0000 0x1 0x0
 #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1                    0x0038 0x0380 0x0820 0x2 0x0
 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0                            0x0038 0x0380 0x0000 0x3 0x0
-#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B                         0x0038 0x0380 0x0834 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B                         0x0038 0x0380 0x0000 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9                          0x0038 0x0380 0x0000 0x5 0x0
 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT                        0x0038 0x0380 0x0000 0x6 0x0
 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4                   0x0038 0x0380 0x0000 0x7 0x0
@@ -213,7 +213,7 @@
 #define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2                        0x0068 0x03B0 0x079C 0x1 0x1
 #define MX6SX_PAD_CSI_DATA07__I2C4_SDA                            0x0068 0x03B0 0x07C4 0x2 0x2
 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7                           0x0068 0x03B0 0x07DC 0x3 0x0
-#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B                         0x0068 0x03B0 0x0854 0x4 0x1
+#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B                         0x0068 0x03B0 0x0000 0x4 0x0
 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21                         0x0068 0x03B0 0x0000 0x5 0x0
 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16                        0x0068 0x03B0 0x0000 0x6 0x0
 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT                           0x0068 0x03B0 0x0000 0x7 0x0
@@ -254,7 +254,7 @@
 #define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC                           0x0078 0x03C0 0x0708 0x0 0x0
 #define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0                         0x0078 0x03C0 0x07A4 0x1 0x1
 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD                      0x0078 0x03C0 0x0674 0x2 0x1
-#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B                          0x0078 0x03C0 0x0844 0x3 0x3
+#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B                          0x0078 0x03C0 0x0000 0x3 0x0
 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT                            0x0078 0x03C0 0x0000 0x4 0x0
 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25                          0x0078 0x03C0 0x0000 0x5 0x0
 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24                         0x0078 0x03C0 0x0000 0x6 0x0
@@ -352,7 +352,7 @@
 #define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK                      0x00A0 0x03E8 0x0000 0x0 0x0
 #define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                    0x00A0 0x03E8 0x076C 0x1 0x1
 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA                          0x00A0 0x03E8 0x07BC 0x2 0x1
-#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B                       0x00A0 0x03E8 0x082C 0x3 0x3
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B                       0x00A0 0x03E8 0x0000 0x3 0x0
 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK                           0x00A0 0x03E8 0x07E8 0x4 0x1
 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9                        0x00A0 0x03E8 0x0000 0x5 0x0
 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR                      0x00A0 0x03E8 0x0000 0x6 0x0
@@ -404,7 +404,7 @@
 #define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK                          0x00B4 0x03FC 0x0808 0x7 0x0
 #define MX6SX_PAD_KEY_ROW0__KPP_ROW_0                             0x00B8 0x0400 0x0000 0x0 0x0
 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP                             0x00B8 0x0400 0x0000 0x1 0x0
-#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B                           0x00B8 0x0400 0x0854 0x2 0x3
+#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B                           0x00B8 0x0400 0x0000 0x2 0x0
 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI                           0x00B8 0x0400 0x0718 0x3 0x0
 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                       0x00B8 0x0400 0x0660 0x4 0x0
 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15                           0x00B8 0x0400 0x0000 0x5 0x0
@@ -423,7 +423,7 @@
 #define MX6SX_PAD_KEY_ROW1__M4_NMI                                0x00BC 0x0404 0x0000 0x8 0x0
 #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2                             0x00C0 0x0408 0x0000 0x0 0x0
 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP                             0x00C0 0x0408 0x0878 0x1 0x1
-#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B                           0x00C0 0x0408 0x084C 0x2 0x3
+#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B                           0x00C0 0x0408 0x0000 0x2 0x0
 #define MX6SX_PAD_KEY_ROW2__CAN1_RX                               0x00C0 0x0408 0x068C 0x3 0x1
 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1                             0x00C0 0x0408 0x0694 0x4 0x1
 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17                           0x00C0 0x0408 0x0000 0x5 0x0
@@ -815,7 +815,7 @@
 #define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05                     0x0164 0x04AC 0x0000 0x0 0x0
 #define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5                       0x0164 0x04AC 0x0000 0x1 0x0
 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS                        0x0164 0x04AC 0x0000 0x2 0x0
-#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B                        0x0164 0x04AC 0x083C 0x3 0x1
+#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B                        0x0164 0x04AC 0x0000 0x3 0x0
 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC                    0x0164 0x04AC 0x064C 0x4 0x0
 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9                         0x0164 0x04AC 0x0000 0x5 0x0
 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5                          0x0164 0x04AC 0x0000 0x6 0x0
@@ -957,7 +957,7 @@
 #define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12                    0x019C 0x04E4 0x0000 0x7 0x0
 #define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3                   0x019C 0x04E4 0x0000 0x9 0x0
 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0                    0x01A0 0x04E8 0x0000 0x0 0x0
-#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B                       0x01A0 0x04E8 0x083C 0x1 0x4
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B                       0x01A0 0x04E8 0x0000 0x1 0x0
 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI                       0x01A0 0x04E8 0x0738 0x2 0x1
 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS                        0x01A0 0x04E8 0x0778 0x3 0x2
 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22                      0x01A0 0x04E8 0x06F4 0x4 0x1
@@ -1236,7 +1236,7 @@
 #define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS                     0x0230 0x0578 0x0670 0x1 0x1
 #define MX6SX_PAD_SD1_DATA2__PWM3_OUT                             0x0230 0x0578 0x0000 0x2 0x0
 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2                         0x0230 0x0578 0x0000 0x3 0x0
-#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B                          0x0230 0x0578 0x0834 0x4 0x2
+#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B                          0x0230 0x0578 0x0000 0x4 0x0
 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4                           0x0230 0x0578 0x0000 0x5 0x0
 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY                           0x0230 0x0578 0x0000 0x6 0x0
 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0                             0x0230 0x0578 0x0000 0x7 0x0
@@ -1315,7 +1315,7 @@
 #define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3                 0x024C 0x0594 0x0000 0x8 0x0
 #define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31                        0x024C 0x0594 0x0000 0x9 0x0
 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK                             0x0250 0x0598 0x0000 0x0 0x0
-#define MX6SX_PAD_SD3_CLK__UART4_CTS_B                            0x0250 0x0598 0x0844 0x1 0x0
+#define MX6SX_PAD_SD3_CLK__UART4_CTS_B                            0x0250 0x0598 0x0000 0x1 0x0
 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK                            0x0250 0x0598 0x0740 0x2 0x0
 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS                       0x0250 0x0598 0x0680 0x3 0x0
 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC                           0x0250 0x0598 0x0000 0x4 0x0
@@ -1409,7 +1409,7 @@
 #define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7                         0x0274 0x05BC 0x0000 0x0 0x0
 #define MX6SX_PAD_SD3_DATA7__CAN1_RX                              0x0274 0x05BC 0x068C 0x1 0x0
 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1                            0x0274 0x05BC 0x0694 0x2 0x0
-#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B                          0x0274 0x05BC 0x083C 0x3 0x3
+#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B                          0x0274 0x05BC 0x0000 0x3 0x0
 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5                        0x0274 0x05BC 0x0000 0x4 0x0
 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9                           0x0274 0x05BC 0x0000 0x5 0x0
 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN                 0x0274 0x05BC 0x0000 0x6 0x0
@@ -1510,7 +1510,7 @@
 #define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1           0x0298 0x05E0 0x0000 0x9 0x0
 #define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7                         0x029C 0x05E4 0x0000 0x0 0x0
 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08                       0x029C 0x05E4 0x0000 0x1 0x0
-#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B                          0x029C 0x05E4 0x084C 0x2 0x1
+#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B                          0x029C 0x05E4 0x0000 0x2 0x0
 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0                           0x029C 0x05E4 0x073C 0x3 0x0
 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15                       0x029C 0x05E4 0x0000 0x4 0x0
 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21                          0x029C 0x05E4 0x0000 0x5 0x0
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index a3980d970590..82d6b34527b7 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -24,6 +24,13 @@
                 reg = <0x80000000 0x40000000>;
         };
 
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm3 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
                 pinctrl-names = "default";
@@ -90,6 +97,14 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                 };
+
+                reg_lcd_3v3: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "lcd-3v3";
+                        gpio = <&gpio3 27 0>;
+                        enable-active-high;
+                };
         };
 
         sound {
@@ -251,6 +266,44 @@
         };
 };
 
+&lcdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        lcd-supply = <&reg_lcd_3v3>;
+        display = <&display0>;
+        status = "okay";
+
+        display0: display0 {
+                bits-per-pixel = <16>;
+                bus-width = <24>;
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <33500000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <89>;
+                                hfront-porch = <164>;
+                                vback-porch = <23>;
+                                vfront-porch = <10>;
+                                hsync-len = <10>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+
 &ssi2 {
         status = "okay";
 };
@@ -365,6 +418,46 @@
                         >;
                 };
 
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+                                MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
+                                MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+                                MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
+                        >;
+                };
+
+                pinctrl_pwm3: pwm3grp-1 {
+                        fsl,pins = <
+                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+                        >;
+                };
+
                 pinctrl_vcc_sd3: vccsd3grp {
                         fsl,pins = <
                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f4b9da65bc0f..f3e88c03b1e4 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -298,6 +298,7 @@
                                 };
 
                                 ssi1: ssi@02028000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -311,6 +312,7 @@
                                 };
 
                                 ssi2: ssi@0202c000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -324,6 +326,7 @@
                                 };
 
                                 ssi3: ssi@02030000 {
+                                        #sound-dai-cells = <0>;
                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -418,7 +421,7 @@
                                 reg = <0x02098000 0x4000>;
                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
-                                         <&clks IMX6SX_CLK_GPT_SERIAL>;
+                                         <&clks IMX6SX_CLK_GPT_3M>;
                                 clock-names = "ipg", "per";
                         };
 
@@ -776,6 +779,8 @@
                                          <&clks IMX6SX_CLK_ENET_PTP>;
                                 clock-names = "ipg", "ahb", "ptp",
                                               "enet_clk_ref", "enet_out";
+                                fsl,num-tx-queues=<3>;
+                                fsl,num-rx-queues=<3>;
                                 status = "disabled";
                         };
 
@@ -1062,6 +1067,7 @@
                                 };
 
                                 lcdif1: lcdif@02220000 {
+                                        compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
                                         reg = <0x02220000 0x4000>;
                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
@@ -1072,6 +1078,7 @@
                                 };
 
                                 lcdif2: lcdif@02224000 {
+                                        compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
                                         reg = <0x02224000 0x4000>;
                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi
index 598afe91c676..4773d6af66a0 100644
--- a/arch/arm/boot/dts/k2e-clocks.dtsi
+++ b/arch/arm/boot/dts/k2e-clocks.dtsi
@@ -40,7 +40,7 @@ clocks {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,psc-clock";
                 clocks = <&chipclk16>;
-                clock-output-names = "usb";
+                clock-output-names = "usb1";
                 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
                 reg-names = "control", "domain";
                 domain-id = <0>;
@@ -60,8 +60,8 @@ clocks {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,psc-clock";
                 clocks = <&chipclk12>;
-                clock-output-names = "pcie";
-                reg = <0x0235006c 0xb00>, <0x02350000 0x400>;
+                clock-output-names = "pcie1";
+                reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
                 reg-names = "control", "domain";
                 domain-id = <18>;
         };
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index 03d01909525b..c358b4b9a073 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -67,6 +67,8 @@
                         clock-names = "usb";
                         interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
                         ranges;
+                        dma-coherent;
+                        dma-ranges;
                         status = "disabled";
 
                         dwc3@25010000 {
@@ -76,5 +78,16 @@
                                 usb-phy = <&usb1_phy>, <&usb1_phy>;
                         };
                 };
+
+                dspgpio0: keystone_dsp_gpio@02620240 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x240>;
+                };
         };
 };
+
+&mdio {
+        reg = <0x24200f00 0x100>;
+};
diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi
index c73899c73118..d721f4b737f7 100644
--- a/arch/arm/boot/dts/k2hk.dtsi
+++ b/arch/arm/boot/dts/k2hk.dtsi
@@ -42,5 +42,61 @@
 
         soc {
                 /include/ "k2hk-clocks.dtsi"
+
+                dspgpio0: keystone_dsp_gpio@02620240 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x240>;
+                };
+
+                dspgpio1: keystone_dsp_gpio@2620244 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x244>;
+                };
+
+                dspgpio2: keystone_dsp_gpio@2620248 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x248>;
+                };
+
+                dspgpio3: keystone_dsp_gpio@262024c {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x24c>;
+                };
+
+                dspgpio4: keystone_dsp_gpio@2620250 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x250>;
+                };
+
+                dspgpio5: keystone_dsp_gpio@2620254 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x254>;
+                };
+
+                dspgpio6: keystone_dsp_gpio@2620258 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x258>;
+                };
+
+                dspgpio7: keystone_dsp_gpio@262025c {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x25c>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi
index 1f7f479589e1..e32c3baa77b8 100644
--- a/arch/arm/boot/dts/k2l.dtsi
+++ b/arch/arm/boot/dts/k2l.dtsi
@@ -51,5 +51,51 @@
                         clocks  = <&clkuart3>;
                         interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
                 };
+
+                dspgpio0: keystone_dsp_gpio@02620240 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x240>;
+                };
+
+                dspgpio1: keystone_dsp_gpio@2620244 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x244>;
+                };
+
+                dspgpio2: keystone_dsp_gpio@2620248 {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x248>;
+                };
+
+                dspgpio3: keystone_dsp_gpio@262024c {
+                        compatible = "ti,keystone-dsp-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio,syscon-dev = <&devctrl 0x24c>;
+                };
         };
 };
+
+&spi0 {
+       ti,davinci-spi-num-cs = <5>;
+};
+
+&spi1 {
+       ti,davinci-spi-num-cs = <3>;
+};
+
+&spi2 {
+       ti,davinci-spi-num-cs = <5>;
+       /* Pin muxed. Enabled and configured by Bootloader */
+       status = "disabled";
+};
+
+&mdio {
+        reg = <0x26200f00 0x100>;
+};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 9e31fe7d31f8..5d3e83fa2242 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -172,7 +172,7 @@
                         compatible = "ti,keystone-usbphy";
                         #address-cells = <1>;
                         #size-cells = <1>;
-                        reg = <0x2620738 32>;
+                        reg = <0x2620738 24>;
                         status = "disabled";
                 };
 
@@ -277,5 +277,13 @@
                         clock-names = "fck";
                         bus_freq        = <2500000>;
                 };
+
+                kirq0: keystone_irq@26202a0 {
+                        compatible = "ti,keystone-irq";
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        ti,syscon-dev = <&devctrl 0x2a0>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 8f76d28759a3..f82827d6fcff 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -123,11 +123,11 @@
 
         dsa@0 {
                 compatible = "marvell,dsa";
-                #address-cells = <2>;
+                #address-cells = <1>;
                 #size-cells = <0>;
 
-                dsa,ethernet = <&eth0>;
-                dsa,mii-bus = <&ethphy0>;
+                dsa,ethernet = <&eth0port>;
+                dsa,mii-bus = <&mdio>;
 
                 switch@0 {
                         #address-cells = <1>;
@@ -169,17 +169,13 @@
 
 &mdio {
         status = "okay";
-
-        ethphy0: ethernet-phy@ff {
-                reg = <0xff>;   /* No phy attached */
-                speed = <1000>;
-                duplex = <1>;
-        };
 };
 
 &eth0 {
         status = "okay";
+
         ethernet0-port@0 {
-                phy-handle = <&ethphy0>;
+                speed = <1000>;
+                duplex = <1>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts
new file mode 100644
index 000000000000..f2e08b3b33ea
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts
@@ -0,0 +1,43 @@
+/*
+ * Marvell RD88F6181 A Board descrition
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions for the board with the A0 or
+ * higher stepping of the SoC. The ethernet switch does not have a
+ * "wan" port.
+ */
+
+/dts-v1/;
+#include "kirkwood-rd88f6281.dtsi"
+
+/ {
+        model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
+        compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        dsa@0 {
+                switch@0 {
+                        reg = <10 0>;    /* MDIO address 10, switch 0 in tree */
+                };
+        };
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy1: ethernet-phy@11 {
+                 reg = <11>;
+        };
+};
+
+&eth1 {
+        status = "okay";
+
+        ethernet1-port@0 {
+                 phy-handle = <&ethphy1>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
deleted file mode 100644
index a803bbb70bc8..000000000000
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Marvell RD88F6181 A0 Board descrition
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * This file contains the definitions for the board with the A0 variant of
- * the SoC. The ethernet switch does not have a "wan" port.
- */
-
-/dts-v1/;
-#include "kirkwood-rd88f6281.dtsi"
-
-/ {
-        model = "Marvell RD88f6281 Reference design, with A0 SoC";
-        compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
-
-        dsa@0 {
-                switch@0 {
-                        reg = <10 0>;    /* MDIO address 10, switch 0 in tree */
-                };
-        };
-};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
index baeebbf1d8c7..f4272b64ed7f 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
@@ -1,5 +1,5 @@
 /*
- * Marvell RD88F6181 A1 Board descrition
+ * Marvell RD88F6181 Z0 stepping descrition
  *
  * Andrew Lunn <andrew@lunn.ch>
  *
@@ -7,17 +7,17 @@
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  *
- * This file contains the definitions for the board with the A1 variant of
- * the SoC. The ethernet switch has a "wan" port.
- */
+ * This file contains the definitions for the board using the Z0
+ * stepping of the SoC. The ethernet switch has a "wan" port.
+*/
 
 /dts-v1/;
 
 #include "kirkwood-rd88f6281.dtsi"
 
 / {
-        model = "Marvell RD88f6281 Reference design, with A1 SoC";
-        compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
+        model = "Marvell RD88f6281 Reference design, with Z0 SoC";
+        compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
 
         dsa@0 {
                 switch@0 {
@@ -28,4 +28,8 @@
                         };
                 };
         };
-};
\ No newline at end of file
+};
+
+&eth1 {
+      status = "disabled";
+};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
index 26cf0e0ccefd..d195e884b3b5 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -37,7 +37,6 @@
 
         ocp@f1000000 {
                 pinctrl: pin-controller@10000 {
-                        pinctrl-0 = <&pmx_sdio_cd>;
                         pinctrl-names = "default";
 
                         pmx_sdio_cd: pmx-sdio-cd {
@@ -69,8 +68,8 @@
                 #address-cells = <2>;
                 #size-cells = <0>;
 
-                dsa,ethernet = <&eth0>;
-                dsa,mii-bus = <&ethphy1>;
+                dsa,ethernet = <&eth0port>;
+                dsa,mii-bus = <&mdio>;
 
                 switch@0 {
                         #address-cells = <1>;
@@ -119,35 +118,19 @@
         };
 
         partition@300000 {
-                label = "data";
+                label = "rootfs";
                 reg = <0x0300000 0x500000>;
         };
 };
 
 &mdio {
         status = "okay";
-
-        ethphy0: ethernet-phy@0 {
-                reg = <0>;
-        };
-
-        ethphy1: ethernet-phy@ff {
-                reg = <0xff>; /* No PHY attached */
-                speed = <1000>;
-                duple = <1>;
-        };
 };
 
 &eth0 {
         status = "okay";
         ethernet0-port@0 {
-                phy-handle = <&ethphy0>;
-        };
-};
-
-&eth1 {
-        status = "okay";
-        ethernet1-port@0 {
-                phy-handle = <&ethphy1>;
+                speed = <1000>;
+                duplex = <1>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index afc640cd80c5..464f09a1a4a5 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -309,7 +309,7 @@
                         marvell,tx-checksum-limit = <1600>;
                         status = "disabled";
 
-                        ethernet0-port@0 {
+                        eth0port: ethernet0-port@0 {
                                 compatible = "marvell,kirkwood-eth-port";
                                 reg = <0>;
                                 interrupts = <11>;
@@ -342,7 +342,7 @@
                         pinctrl-names = "default";
                         status = "disabled";
 
-                        ethernet1-port@0 {
+                        eth1port: ethernet1-port@0 {
                                 compatible = "marvell,kirkwood-eth-port";
                                 reg = <0>;
                                 interrupts = <15>;
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
new file mode 100644
index 000000000000..e6539ea5a711
--- /dev/null
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        gic: interrupt-controller@c4301000 {
+                compatible = "arm,cortex-a9-gic";
+                reg = <0xc4301000 0x1000>,
+                      <0xc4300100 0x0100>;
+                interrupt-controller;
+                #interrupt-cells = <3>;
+        };
+
+        timer@c1109940 {
+                compatible = "amlogic,meson6-timer";
+                reg = <0xc1109940 0x14>;
+                interrupts = <0 10 1>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                wdt: watchdog@c1109900 {
+                        compatible = "amlogic,meson6-wdt";
+                        reg = <0xc1109900 0x8>;
+                };
+
+                uart_AO: serial@c81004c0 {
+                        compatible = "amlogic,meson-uart";
+                        reg = <0xc81004c0 0x14>;
+                        interrupts = <0 90 1>;
+                        clocks = <&clk81>;
+                        status = "disabled";
+                };
+
+                uart_A: serial@c81084c0 {
+                        compatible = "amlogic,meson-uart";
+                        reg = <0xc81084c0 0x14>;
+                        interrupts = <0 90 1>;
+                        clocks = <&clk81>;
+                        status = "disabled";
+                };
+
+                uart_B: serial@c81084dc {
+                        compatible = "amlogic,meson-uart";
+                        reg = <0xc81084dc 0x14>;
+                        interrupts = <0 90 1>;
+                        clocks = <&clk81>;
+                        status = "disabled";
+                };
+
+                uart_C: serial@c8108700 {
+                        compatible = "amlogic,meson-uart";
+                        reg = <0xc8108700 0x14>;
+                        interrupts = <0 90 1>;
+                        clocks = <&clk81>;
+                        status = "disabled";
+                };
+        };
+}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
new file mode 100644
index 000000000000..dc2541faf1ec
--- /dev/null
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "meson6.dtsi"
+
+/ {
+        model = "Geniatech ATV1200";
+        compatible = "geniatech,atv1200";
+
+        aliases {
+                serial0 = &uart_AO;
+        };
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+};
+
+&uart_AO {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
new file mode 100644
index 000000000000..4ba49127779f
--- /dev/null
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "meson.dtsi"
+
+/ {
+        model = "Amlogic Meson6 SoC";
+        compatible = "amlogic,meson6";
+
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@200 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x200>;
+                };
+
+                cpu@201 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x201>;
+                };
+        };
+
+        clk81: clk@0 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <200000000>;
+        };
+}; /* end of / */
diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts
index 443b4467de15..0da047013120 100644
--- a/arch/arm/boot/dts/mt6589-aquaris5.dts
+++ b/arch/arm/boot/dts/mt6589-aquaris5.dts
@@ -18,6 +18,11 @@
 
 / {
         model = "bq Aquaris5";
+        compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
+
+        chosen {
+                bootargs = "earlyprintk";
+        };
 
         memory {
                 reg = <0x80000000 0x40000000>;
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index d0297a051549..e3c7600ddb38 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -81,8 +81,8 @@
                         clock-names = "system-clk", "rtc-clk";
                 };
 
-                gic: interrupt-controller@10212000 {
-                        compatible = "arm,cortex-a15-gic";
+                gic: interrupt-controller@10211000 {
+                        compatible = "arm,cortex-a7-gic";
                         interrupt-controller;
                         #interrupt-cells = <3>;
                         reg = <0x10211000 0x1000>,
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 8f8c07da4ac1..59d1c297bb30 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -75,7 +75,6 @@
                         compatible = "ti,omap2-intc";
                         interrupt-controller;
                         #interrupt-cells = <1>;
-                        ti,intc-size = <96>;
                         reg = <0x480FE000 0x1000>;
                 };
 
diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts
index 21baec154b78..b604d26bd48c 100644
--- a/arch/arm/boot/dts/omap2420-n810.dts
+++ b/arch/arm/boot/dts/omap2420-n810.dts
@@ -6,3 +6,10 @@
         model = "Nokia N810";
         compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";
 };
+
+&i2c2 {
+        aic3x@18 {
+                compatible = "tlv320aic3x";
+                reg = <0x18>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 89608b206519..24c50db2a478 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -27,6 +27,12 @@
 
 &i2c1 {
         clock-frequency = <400000>;
+
+        pmic@72 {
+                compatible = "menelaus";
+                reg = <0x72>;
+                interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+        };
 };
 
 &i2c2 {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 9be3c1266378..ae89aad01595 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -159,6 +159,14 @@
                         ti,hwmods = "mailbox";
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <6>;
+                        mbox_dsp: dsp {
+                                ti,mbox-tx = <0 0 0>;
+                                ti,mbox-rx = <1 0 0>;
+                        };
+                        mbox_iva: iva {
+                                ti,mbox-tx = <2 1 3>;
+                                ti,mbox-rx = <3 1 3>;
+                        };
                 };
 
                 timer1: timer@48028000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 1a00f15d9096..b56d71611026 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -249,6 +249,10 @@
                         ti,hwmods = "mailbox";
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <6>;
+                        mbox_dsp: dsp {
+                                ti,mbox-tx = <0 0 0>;
+                                ti,mbox-rx = <1 0 0>;
+                        };
                 };
 
                 timer1: timer@49018000 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 1becefce821b..06a8aec4e6ea 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -174,8 +174,8 @@
 
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
-                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
-                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                        0x16e (PIN_INPUT | MUX_MODE0)   /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0)  /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
                 >;
         };
 
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 3c3e6da1deac..a9aae88b74f5 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -292,6 +292,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart3_pins>;
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
 };
 
 &gpio1 {
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dtsi
index 021311f7964b..fd34f913ace3 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -26,6 +26,10 @@
                 reg = <0x80000000 0x20000000>; /* 512 MB */
         };
 
+        aliases {
+                display0 = &lcd;
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
@@ -74,9 +78,30 @@
                         };
                 };
         };
+
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+        };
 };
 
 &omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusb2_pins
+        >;
+
+        hsusb2_pins: pinmux_hsusb2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
+                        OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
+                        OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
+                        OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
+                        OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
+                        OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
+                >;
+        };
+
         uart1_pins: pinmux_uart1_pins {
                 pinctrl-single,pins = <
                         0x152 (PIN_INPUT | MUX_MODE0)           /* uart1_rx.uart1_rx */
@@ -141,12 +166,31 @@
                        0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
                >;
        };
+};
+
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusb2_2_pins
+        >;
+
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
 
         spi_gpio_pins: spi_gpio_pinmux {
-                pinctrl-single,pins = <0x5a8 (PIN_OUTPUT | MUX_MODE4) /* clk */
-                        0x5b6 (PIN_OUTPUT | MUX_MODE4) /* cs */
-                        0x5b8 (PIN_OUTPUT | MUX_MODE4) /* tx */
-                        0x5b4 (PIN_INPUT | MUX_MODE4) /* rx */
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */
                 >;
         };
 };
@@ -196,6 +240,9 @@
                 #size-cells = <0>;
                 reg = <0x45>;
 
+                gpio-controller;
+                #gpio-cells = <2>;
+
                 gta04_led0: red_aux@0 {
                         label = "gta04:red:aux";
                         reg = <0x0>;
@@ -216,11 +263,16 @@
                         label = "gta04:green:power";
                         reg = <0x4>;
                 };
+
+                wifi_reset: wifi_reset@6 {
+                        reg = <0x6>;
+                        compatible = "gpio";
+                };
         };
 
         /* compass aka magnetometer */
         hmc5843@1e {
-                compatible = "honeywell,hmc5843";
+                compatible = "honeywell,hmc5883l";
                 reg = <0x1e>;
         };
 
@@ -248,6 +300,14 @@
         power = <50>;
 };
 
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy>;
+};
+
 &mmc1 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc1_pins>;
@@ -286,11 +346,37 @@
         bb_uamp = <150>;
 };
 
+/* spare */
+&vaux1 {
+        regulator-min-microvolt = <2500000>;
+        regulator-max-microvolt = <3000000>;
+};
+
+/* sensors */
+&vaux2 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+        regulator-always-on;
+};
+
+/* camera */
+&vaux3 {
+        regulator-min-microvolt = <2500000>;
+        regulator-max-microvolt = <2500000>;
+};
+
+/* WLAN/BT */
 &vaux4 {
         regulator-min-microvolt = <2800000>;
         regulator-max-microvolt = <3150000>;
 };
 
+/* GPS LNA */
+&vsim {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <3150000>;
+};
+
 /* Needed to power the DPI pins */
 &vpll2 {
         regulator-always-on;
@@ -309,3 +395,57 @@
                 };
         };
 };
+
+&gpmc {
+        ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
+
+        nand@0,0 {
+                reg = <0 0 0>; /* CS0, offset 0 */
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,device-width = <2>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                x-loader@0 {
+                        label = "X-Loader";
+                        reg = <0 0x80000>;
+                };
+
+                bootloaders@80000 {
+                        label = "U-Boot";
+                        reg = <0x80000 0x1e0000>;
+                };
+
+                bootloaders_env@260000 {
+                        label = "U-Boot Env";
+                        reg = <0x260000 0x20000>;
+                };
+
+                kernel@280000 {
+                        label = "Kernel";
+                        reg = <0x280000 0x400000>;
+                };
+
+                filesystem@680000 {
+                        label = "File System";
+                        reg = <0x680000 0xf980000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/omap3-gta04a3.dts
new file mode 100644
index 000000000000..3099a892cf50
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a3.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-gta04.dtsi"
+
+/ {
+        model = "Goldelico GTA04A3";
+};
+
+&i2c2 {
+
+        /* alternate accelerometer that might be installed on some GTA04A3 boards */
+        lis302@1d {
+                compatible = "st,lis331dlh", "st,lis3lv02d";
+                reg = <0x1d>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
+                Vdd-supply = <&vaux2>;
+                Vdd_IO-supply = <&vaux2>;
+
+                st,click-single-x;
+                st,click-single-y;
+                st,click-single-z;
+                st,click-thresh-x = <8>;
+                st,click-thresh-y = <8>;
+                st,click-thresh-z = <10>;
+                st,click-click-time-limit = <9>;
+                st,click-latency = <50>;
+                st,irq1-click;
+                st,wakeup-x-lo;
+                st,wakeup-x-hi;
+                st,wakeup-y-lo;
+                st,wakeup-y-hi;
+                st,wakeup-z-lo;
+                st,wakeup-z-hi;
+                st,min-limit-x = <32>;
+                st,min-limit-y = <3>;
+                st,min-limit-z = <3>;
+                st,max-limit-x = <3>;
+                st,max-limit-y = <32>;
+                st,max-limit-z = <32>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/omap3-gta04a4.dts
new file mode 100644
index 000000000000..c918bb1f0529
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a4.dts
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2014 Marek Belisko <marek@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-gta04.dtsi"
+
+/ {
+        model = "Goldelico GTA04A4";
+};
diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts
new file mode 100644
index 000000000000..52b386f6865b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a5.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-gta04.dtsi"
+
+/ {
+        model = "Goldelico GTA04A5";
+
+        sound {
+                ti,jack-det-gpio = <&twl_gpio 2 0>;    /* GTA04A5 only */
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi
new file mode 100644
index 000000000000..bd66545ef954
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha-common.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-tao3530.dtsi"
+
+/ {
+        gpio_poweroff {
+                pinctrl-names = "default";
+                pinctrl-0 = <&poweroff_pins>;
+
+                compatible = "gpio-poweroff";
+                gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;     /* GPIO 168 */
+        };
+};
+
+&omap3_pmx_core {
+        sound2_pins: pinmux_sound2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4)       /* gpmc_d8 gpio_44 */
+                >;
+        };
+
+        led_blue_pins: pinmux_led_blue_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4)       /* cam_xclka gpio_96, LED blue */
+                >;
+        };
+
+        led_green_pins: pinmux_led_green_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4)       /* cam_d8 gpio_107, LED green */
+                >;
+        };
+
+        led_red_pins: pinmux_led_red_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4)        /* cam_xclkb gpio_111, LED red */
+                >;
+        };
+
+        poweroff_pins: pinmux_poweroff_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4)        /* i2c2_scl gpio_168 */
+                >;
+        };
+
+        powerdown_input_pins: pinmux_powerdown_input_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */
+                >;
+        };
+
+        fpga_boot0_pins: fpga_boot0_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4)        /* cam_d2 gpio_101 */
+                        OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4)       /* cam_d3 gpio_102 */
+                        OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4)       /* cam_d4 gpio_103 */
+                        OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */
+                >;
+        };
+
+        fpga_boot1_pins: fpga_boot1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4)        /* gpmc_d10 gpio_46 */
+                        OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4)       /* gpmc_d11 gpio_47 */
+                        OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4)       /* gpmc_d12 gpio_48 */
+                        OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */
+                >;
+        };
+};
+
+/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
+&i2c2 {
+        status = "disabled";
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts
new file mode 100644
index 000000000000..11aa28d73f3a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha-lcd.dts
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-ha-common.dtsi"
+
+/ {
+        model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM";
+        compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+};
+
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusbb2_pins
+                &powerdown_input_pins
+                &fpga_boot0_pins
+                &fpga_boot1_pins
+                &led_blue_pins
+                &led_green_pins
+                &led_red_pins
+                &touchscreen_wake_pins
+        >;
+
+        touchscreen_irq_pins: pinmux_touchscreen_irq_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */
+                >;
+        };
+
+        touchscreen_wake_pins: pinmux_touchscreen_wake_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4)        /* gpio_110, Touchscreen Wake */
+                >;
+        };
+
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)       /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)       /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)       /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)       /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)       /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)       /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)       /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)       /* dss_data23.dss_data23 */
+                >;
+        };
+
+        lte430_pins: pinmux_lte430_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat6.gpio_138 */
+                >;
+        };
+
+        backlight_pins: pinmux_backlight_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 */
+                >;
+        };
+};
+
+/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
+&i2c2 {
+        status = "disabled";
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+};
+
+/* Needed to power the DPI pins */
+&vpll2 {
+        regulator-always-on;
+};
+
+&dss {
+        status = "ok";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_dpi_pins>;
+
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+
+/ {
+        aliases {
+                display0 = &lcd0;
+        };
+
+        lcd0: display@0 {
+                compatible = "panel-dpi";
+                label = "lcd";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&lte430_pins>;
+                enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;     /* gpio_138 */
+
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+
+                panel-timing {
+                        clock-frequency = <31250000>;
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <40>;
+                        hback-porch = <86>;
+                        hsync-len = <1>;
+                        vback-porch = <30>;
+                        vfront-porch = <13>;
+                        vsync-len = <3>;
+
+                        hsync-active = <0>;
+                        vsync-active = <0>;
+                        de-active = <1>;
+                        pixelclk-active = <1>;
+                };
+        };
+
+        backlight {
+                compatible = "gpio-backlight";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&backlight_pins>;
+                gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>;           /* gpio_139 */
+
+                default-on;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts
new file mode 100644
index 000000000000..fde325688fb9
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-ha-common.dtsi"
+
+/ {
+        model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM";
+        compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+};
+
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusbb2_pins
+                &powerdown_input_pins
+                &fpga_boot0_pins
+                &fpga_boot1_pins
+                &led_blue_pins
+                &led_green_pins
+                &led_red_pins
+        >;
+};
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index af272c156e21..72dca0b7904d 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -159,6 +159,11 @@
                 reg = <0x48>;
                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                 interrupt-parent = <&intc>;
+
+                twl_power: power {
+                        compatible = "ti,twl4030-power-idle";
+                        ti,use_poweroff;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index b15f1a77d684..9b0494a8ab45 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -93,7 +93,7 @@
         };
 
         tv: connector {
-                compatible = "composite-connector";
+                compatible = "composite-video-connector";
                 label = "tv";
 
                 port {
@@ -134,24 +134,32 @@
                 >;
         };
 
+        ethernet_pins: pinmux_ethernet_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4)       /* gpmc_ncs3.gpio_54 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4)               /* dss_data16.gpio_86 */
+                        OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)               /* uart3_rts_sd.gpio_164 */
+                >;
+        };
+
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
-                        0x18a (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl */
-                        0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda */
+                        0x18a (PIN_INPUT | MUX_MODE0)           /* i2c1_scl */
+                        0x18c (PIN_INPUT | MUX_MODE0)           /* i2c1_sda */
                 >;
         };
 
         i2c2_pins: pinmux_i2c2_pins {
                 pinctrl-single,pins = <
-                        0x18e (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c2_scl */
-                        0x190 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c2_sda */
+                        0x18e (PIN_INPUT | MUX_MODE0)           /* i2c2_scl */
+                        0x190 (PIN_INPUT | MUX_MODE0)           /* i2c2_sda */
                 >;
         };
 
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
-                        0x192 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c3_scl */
-                        0x194 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c3_sda */
+                        0x192 (PIN_INPUT | MUX_MODE0)           /* i2c3_scl */
+                        0x194 (PIN_INPUT | MUX_MODE0)           /* i2c3_sda */
                 >;
         };
 
@@ -353,7 +361,7 @@
         };
 
         twl_power: power {
-                compatible = "ti,twl4030-power-n900";
+                compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
                 ti,use_poweroff;
         };
 };
@@ -578,6 +586,8 @@
 
 &gpmc {
         ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
+        ranges = <0 0 0x01000000 0x01000000>,   /* 16 MB for OneNAND */
+                 <1 0 0x02000000 0x01000000>;   /* 16 MB for smc91c96 */
 
         /* gpio-irq for dma: 65 */
 
@@ -646,6 +656,38 @@
                         reg = <0x004c0000 0x0fb40000>;
                 };
         };
+
+        ethernet@gpmc {
+                compatible = "smsc,lan91c94";
+                interrupt-parent = <&gpio2>;
+                interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;  /* gpio54 */
+                reg = <1 0x300 0xf>;            /* 16 byte IO range at offset 0x300 */
+                bank-width = <2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&ethernet_pins>;
+                gpmc,device-width = <2>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <48>;
+                gpmc,cs-wr-off-ns = <24>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <0>;
+                gpmc,adv-wr-off-ns = <0>;
+                gpmc,we-on-ns = <12>;
+                gpmc,we-off-ns = <18>;
+                gpmc,oe-on-ns = <12>;
+                gpmc,oe-off-ns = <48>;
+                gpmc,page-burst-access-ns = <0>;
+                gpmc,access-ns = <42>;
+                gpmc,rd-cycle-ns = <180>;
+                gpmc,wr-cycle-ns = <180>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-access-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <12>;
+        };
 };
 
 &mcspi1 {
diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
index 5831bcc52966..520453d95704 100644
--- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
@@ -36,8 +36,8 @@
 
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
-                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
-                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)               /* uart3_tx_irtx.uart3_tx_irtx */
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)        /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)       /* uart3_tx_irtx.uart3_tx_irtx */
                 >;
         };
 };
@@ -88,6 +88,7 @@
 };
 
 &uart3 {
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
         pinctrl-names = "default";
         pinctrl-0 = <&uart3_pins>;
 };
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
new file mode 100644
index 000000000000..b30f387d3a83
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -0,0 +1,337 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap34xx-hs.dtsi"
+
+/ {
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vcc>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+
+        /* HS USB Port 2 Power */
+        hsusb2_power: hsusb2_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 18 0>;        /* GPIO LEDA */
+                startup-delay-us = <70000>;
+        };
+
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;       /* gpio_162 */
+                vcc-supply = <&hsusb2_power>;
+        };
+
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "omap3beagle";
+
+                /* McBSP2 is used for onboard sound, same as on beagle */
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
+
+        /* Regulator to enable/switch the vcc of the Wifi module */
+        mmc2_sdio_poweron: regulator-mmc2-sdio-poweron {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-mmc2-sdio-poweron";
+                regulator-min-microvolt = <3150000>;
+                regulator-max-microvolt = <3150000>;
+                gpio = <&gpio5 29 GPIO_ACTIVE_LOW>;             /* gpio_157 */
+                enable-active-low;
+                startup-delay-us = <10000>;
+        };
+};
+
+&omap3_pmx_core {
+        hsusbb2_pins: pinmux_hsusbb2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)               /* etk_d10.hsusb2_clk */
+                        OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)               /* etk_d11.hsusb2_stp */
+                        OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* etk_d12.hsusb2_dir */
+                        OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* etk_d13.hsusb2_nxt */
+                        OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* etk_d14.hsusb2_data0 */
+                        OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* etk_d15.hsusb2_data1 */
+                        OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
+                        OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
+                        OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
+                        OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
+                        OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
+                        OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
+                >;
+        };
+
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
+                        OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
+                        OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
+                        OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
+                >;
+        };
+
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
+                >;
+        };
+
+        /* wlan GPIO output for WLAN_EN */
+        wlan_gpio: pinmux_wlan_gpio {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4)       /* mcbsp1_fsr gpio_157 */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)       /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */
+                        OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */
+                >;
+        };
+
+        mcspi1_pins: pinmux_mcspi1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
+                        OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
+                        OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
+                        OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
+                >;
+        };
+
+        mcspi3_pins: pinmux_mcspi3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1)       /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */
+                        OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */
+                        OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1)       /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */
+                        OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1)        /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */
+                >;
+        };
+
+        mcbsp3_pins: pinmux_mcbsp3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0)       /* mcbsp3_dx.uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0)        /* mcbsp3_dr.uart2_rts */
+                        OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0)        /* mcbsp3_clk.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0)        /* mcbsp3_fsx.uart2_rx */
+                >;
+        };
+};
+
+/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */
+&mcbsp1 {
+        status = "disabled";
+};
+
+&mcbsp2 {
+        status = "okay";
+};
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
+        };
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+};
+
+&mcspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi1_pins>;
+
+        spidev@0 {
+                compatible = "spidev";
+                spi-max-frequency = <48000000>;
+                reg = <0>;
+                spi-cpha;
+        };
+};
+
+&mcspi3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi3_pins>;
+
+        spidev@0 {
+                compatible = "spidev";
+                spi-max-frequency = <48000000>;
+                reg = <0>;
+                spi-cpha;
+        };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmc1>;
+        vmmc_aux-supply = <&vsim>;
+        cd-gpios = <&twl_gpio 0 0>;
+        bus-width = <8>;
+};
+
+// WiFi (Marvell 88W8686) on MMC2/SDIO
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&mmc2_sdio_poweron>;
+        non-removable;
+        bus-width = <4>;
+        cap-power-off-card;
+};
+
+&mmc3 {
+        status = "disabled";
+};
+
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&mcbsp3 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp3_pins>;
+};
+
+&gpmc {
+        ranges = <0 0 0x00000000 0x01000000>;
+
+        nand@0,0 {
+                reg = <0 0 0>; /* CS0, offset 0 */
+                nand-bus-width = <16>;
+                gpmc,device-width = <2>;        /* GPMC_DEVWIDTH_16BIT */
+                ti,nand-ecc-opt = "sw";
+
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <36>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <24>;
+                gpmc,adv-wr-off-ns = <36>;
+                gpmc,oe-on-ns = <6>;
+                gpmc,oe-off-ns = <48>;
+                gpmc,we-on-ns = <6>;
+                gpmc,we-off-ns = <30>;
+                gpmc,rd-cycle-ns = <72>;
+                gpmc,wr-cycle-ns = <72>;
+                gpmc,access-ns = <54>;
+                gpmc,wr-access-ns = <30>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                x-loader@0 {
+                        label = "X-Loader";
+                        reg = <0 0x80000>;
+                };
+
+                bootloaders@80000 {
+                        label = "U-Boot";
+                        reg = <0x80000 0x1e0000>;
+                };
+
+                bootloaders_env@260000 {
+                        label = "U-Boot Env";
+                        reg = <0x260000 0x20000>;
+                };
+
+                kernel@280000 {
+                        label = "Kernel";
+                        reg = <0x280000 0x400000>;
+                };
+
+                filesystem@680000 {
+                        label = "File System";
+                        reg = <0x680000 0xf980000>;
+                };
+        };
+};
+
+&usb_otg_hs {
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        phys = <&usb2_phy>;
+        phy-names = "usb2-phy";
+        mode = <3>;
+        power = <50>;
+};
+
+&vaux2 {
+        regulator-name = "vdd_ehci";
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+        regulator-always-on;
+};
diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts
new file mode 100644
index 000000000000..d659515ab9b8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-thunder.dts
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-tao3530.dtsi"
+
+/ {
+        model = "TI OMAP3 Thunder baseboard with TAO3530 SOM";
+        compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+};
+
+&omap3_pmx_core {
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)       /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)       /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)       /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)       /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)       /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)       /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)       /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)       /* dss_data23.dss_data23 */
+                >;
+        };
+
+        lte430_pins: pinmux_lte430_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat6.gpio_138 */
+                >;
+        };
+
+        backlight_pins: pinmux_backlight_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 */
+                >;
+        };
+};
+
+/* Needed to power the DPI pins */
+&vpll2 {
+        regulator-always-on;
+};
+
+&dss {
+        status = "ok";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_dpi_pins>;
+
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+
+/ {
+        aliases {
+                display0 = &lcd0;
+        };
+
+        lcd0: display@0 {
+                compatible = "samsung,lte430wq-f0c", "panel-dpi";
+                label = "lcd";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&lte430_pins>;
+                enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;     /* gpio_138 */
+
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+
+                panel-timing {
+                        clock-frequency = <9000000>;
+                        hactive = <480>;
+                        vactive = <272>;
+                        hfront-porch = <3>;
+                        hback-porch = <2>;
+                        hsync-len = <42>;
+                        vback-porch = <2>;
+                        vfront-porch = <3>;
+                        vsync-len = <11>;
+
+                        hsync-active = <0>;
+                        vsync-active = <0>;
+                        de-active = <1>;
+                        pixelclk-active = <1>;
+                };
+        };
+
+        backlight {
+                compatible = "gpio-backlight";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&backlight_pins>;
+                gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>;           /* gpio_139 */
+
+                default-on;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 575a49bf968d..d0e884d3a737 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -97,6 +97,7 @@
                 prm: prm@48306000 {
                         compatible = "ti,omap3-prm";
                         reg = <0x48306000 0x4000>;
+                        interrupts = <11>;
 
                         prm_clocks: clocks {
                                 #address-cells = <1>;
@@ -140,10 +141,9 @@
                 };
 
                 intc: interrupt-controller@48200000 {
-                        compatible = "ti,omap2-intc";
+                        compatible = "ti,omap3-intc";
                         interrupt-controller;
                         #interrupt-cells = <1>;
-                        ti,intc-size = <96>;
                         reg = <0x48200000 0x1000>;
                 };
 
@@ -334,6 +334,10 @@
                         interrupts = <26>;
                         ti,mbox-num-users = <2>;
                         ti,mbox-num-fifos = <2>;
+                        mbox_dsp: dsp {
+                                ti,mbox-tx = <0 0 0>;
+                                ti,mbox-rx = <1 0 0>;
+                        };
                 };
 
                 mcspi1: spi@48098000 {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 02f69f4a8fd3..9bad94efe1c8 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -107,7 +107,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 reg = <1 0 0x08000000>;
-                ti,nand-ecc-opt = "ham1";
+                ti,nand-ecc-opt = "sw";
                 nand-bus-width = <8>;
                 gpmc,cs-on-ns = <0>;
                 gpmc,cs-rd-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index e47ff69dcf70..5c375003bad1 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -467,6 +467,7 @@
                 ti,bit-shift = <0x1e>;
                 reg = <0x0d00>;
                 ti,set-bit-to-disable;
+                ti,set-rate-parent;
         };
 
         dpll4_m6_ck: dpll4_m6_ck {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 8cfa3c8a72b0..150513506c19 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -8,9 +8,6 @@
 #include "elpida_ecb240abacn.dtsi"
 
 / {
-        model = "TI OMAP4 PandaBoard";
-        compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
-
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 816d1c95b592..2f1dabcc6adf 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -10,6 +10,11 @@
 #include "omap4460.dtsi"
 #include "omap4-panda-common.dtsi"
 
+/ {
+        model = "TI OMAP4 PandaBoard-ES";
+        compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
+};
+
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
         ti,model = "PandaBoardES";
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 6189a8b77d7f..a0e28b2e254e 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -9,3 +9,8 @@
 
 #include "omap443x.dtsi"
 #include "omap4-panda-common.dtsi"
+
+/ {
+        model = "TI OMAP4 PandaBoard";
+        compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 69408b53200d..878c979203d0 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -81,6 +81,7 @@
                 mpu {
                         compatible = "ti,omap4-mpu";
                         ti,hwmods = "mpu";
+                        sram = <&ocmcram>;
                 };
 
                 dsp {
@@ -129,6 +130,7 @@
                 prm: prm@4a306000 {
                         compatible = "ti,omap4-prm";
                         reg = <0x4a306000 0x3000>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
                         prm_clocks: clocks {
                                 #address-cells = <1>;
@@ -208,6 +210,11 @@
                         };
                 };
 
+                ocmcram: ocmcram@40304000 {
+                        compatible = "mmio-sram";
+                        reg = <0x40304000 0xa000>; /* 40k */
+                };
+
                 sdma: dma-controller@4a056000 {
                         compatible = "ti,omap4430-sdma";
                         reg = <0x4a056000 0x1000>;
@@ -656,6 +663,14 @@
                         ti,hwmods = "mailbox";
                         ti,mbox-num-users = <3>;
                         ti,mbox-num-fifos = <8>;
+                        mbox_ipu: mbox_ipu {
+                                ti,mbox-tx = <0 0 0>;
+                                ti,mbox-rx = <1 0 0>;
+                        };
+                        mbox_dsp: mbox_dsp {
+                                ti,mbox-tx = <3 0 0>;
+                                ti,mbox-rx = <2 0 0>;
+                        };
                 };
 
                 timer1: timer@4a318000 {
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index b8698ca68647..b54b271e153b 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -16,6 +16,12 @@
                 reg = <0x80000000 0x7F000000>; /* 2048 MB */
         };
 
+        aliases {
+                display0 = &hdmi0;
+                display1 = &dvi0;
+                display2 = &lcd0;
+        };
+
         vmmcsd_fixed: fixed-regulator-mmcsd {
                 compatible = "regulator-fixed";
                 regulator-name = "vmmcsd_fixed";
@@ -45,6 +51,13 @@
                 enable-active-high;
         };
 
+        ads7846reg: ads7846-reg {
+                compatible = "regulator-fixed";
+                regulator-name = "ads7846-reg";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
         /* HS USB Host PHY on PORT 2 */
         hsusb2_phy: hsusb2_phy {
                 compatible = "usb-nop-xceiv";
@@ -66,6 +79,105 @@
                         default-state = "off";
                 };
         };
+
+        lcd0: display {
+                compatible = "startek,startek-kd050c", "panel-dpi";
+                label = "lcd";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&lcd_pins>;
+
+                enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
+
+                panel-timing {
+                        clock-frequency = <33000000>;
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <40>;
+                        hback-porch = <40>;
+                        hsync-len = <43>;
+                        vback-porch = <29>;
+                        vfront-porch = <13>;
+                        vsync-len = <3>;
+                        hsync-active = <0>;
+                        vsync-active = <0>;
+                        de-active = <1>;
+                        pixelclk-active = <1>;
+                };
+
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_lcd_out>;
+                        };
+                };
+        };
+
+        hdmi0: connector@0 {
+                compatible = "hdmi-connector";
+                label = "hdmi";
+
+                type = "a";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&hdmi_conn_pins>;
+
+                hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
+
+                port {
+                        hdmi_connector_in: endpoint {
+                                remote-endpoint = <&hdmi_out>;
+                        };
+                };
+        };
+
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_dvi_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+
+        dvi0: connector@1 {
+                compatible = "dvi-connector";
+                label = "dvi";
+
+                digital;
+
+                ddc-i2c-bus = <&i2c2>;
+
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+};
+
+&omap5_pmx_wkup {
+
+        ads7846_pins: pinmux_ads7846_pins {
+                pinctrl-single,pins = <
+                        0x02 (PIN_INPUT_PULLDOWN | MUX_MODE6)  /* llib_wakereqin.gpio1_wk15 */
+                >;
+        };
 };
 
 &omap5_pmx_core {
@@ -88,6 +200,13 @@
                 >;
         };
 
+        i2c2_pins: pinmux_i2c2_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+                        OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+                >;
+        };
+
         mmc1_pins: pinmux_mmc1_pins {
                 pinctrl-single,pins = <
                         OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */
@@ -127,8 +246,8 @@
 
         wlan_gpios_pins: pinmux_wlan_gpios_pins {
                 pinctrl-single,pins = <
-                        OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */
-                        OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */
+                        OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */
+                        OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */
                 >;
         };
 
@@ -144,6 +263,104 @@
                         OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */
                 >;
         };
+
+        dss_hdmi_pins: pinmux_dss_hdmi_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */
+                        OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */
+                        OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */
+                >;
+        };
+
+        lcd_pins: pinmux_lcd_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */
+                >;
+        };
+
+        hdmi_conn_pins: pinmux_hdmi_conn_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
+                >;
+        };
+
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */
+                        OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */
+                        OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */
+                        OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */
+                        OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */
+                        OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */
+                        OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */
+                        OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */
+                        OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */
+                        OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */
+                        OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */
+                        OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */
+                        OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */
+                        OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */
+                        OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */
+                        OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */
+                        OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */
+                        OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */
+                        OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */
+                        OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */
+                        OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */
+                        OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */
+                        OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */
+                        OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */
+                        OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */
+                        OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */
+                        OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */
+                        OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */
+                >;
+        };
+
+        mcspi2_pins: pinmux_mcspi1_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
+                        OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
+                        OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */
+                        OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */
+                >;
+        };
+};
+
+&mcspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi2_pins>;
+
+        /* touch controller */
+        ads7846@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&ads7846_pins>;
+
+                compatible = "ti,ads7846";
+                vcc-supply = <&ads7846reg>;
+
+                reg = <0>;                              /* CS0 */
+                spi-max-frequency = <1500000>;
+
+                interrupt-parent = <&gpio1>;
+                interrupts = <15 0>;                    /* gpio1_wk15 */
+                pendown-gpio = <&gpio1 15 0>;
+
+
+                ti,x-min = /bits/ 16 <0x0>;
+                ti,x-max = /bits/ 16 <0x0fff>;
+                ti,y-min = /bits/ 16 <0x0>;
+                ti,y-max = /bits/ 16 <0x0fff>;
+
+                ti,x-plate-ohms = /bits/ 16 <180>;
+                ti,pressure-max = /bits/ 16 <255>;
+
+                ti,debounce-max = /bits/ 16 <30>;
+                ti,debounce-tol = /bits/ 16 <10>;
+                ti,debounce-rep = /bits/ 16 <1>;
+
+                linux,wakeup;
+        };
 };
 
 &mmc1 {
@@ -353,13 +570,12 @@
                                 };
 
                                 ldo8_reg: ldo8 {
-                                        /* VDD_3v0: Does not go anywhere */
+                                        /* VDD_3V_GP: act led/serial console */
                                         regulator-name = "ldo8";
                                         regulator-min-microvolt = <3000000>;
                                         regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
                                         regulator-boot-on;
-                                        /* Unused */
-                                        status = "disabled";
                                 };
 
                                 ldo9_reg: ldo9 {
@@ -399,6 +615,13 @@
         };
 };
 
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+
+        clock-frequency = <100000>;
+};
+
 &usbhshost {
         port2-mode = "ehci-hsic";
         port3-mode = "ehci-hsic";
@@ -408,6 +631,50 @@
         phys = <0 &hsusb2_phy &hsusb3_phy>;
 };
 
+&usb3 {
+       extcon = <&extcon_usb3>;
+       vbus-supply = <&smps10_out1_reg>;
+};
+
 &cpu0 {
         cpu0-supply = <&smps123_reg>;
 };
+
+&dss {
+        status = "ok";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_dpi_pins>;
+
+        port {
+                dpi_dvi_out: endpoint@0 {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+
+                dpi_lcd_out: endpoint@1 {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+
+&dsi2 {
+        status = "ok";
+        vdd-supply = <&ldo4_reg>;
+};
+
+&hdmi {
+        status = "ok";
+        vdda-supply = <&ldo4_reg>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_hdmi_pins>;
+
+        port {
+                hdmi_out: endpoint {
+                        remote-endpoint = <&hdmi_connector_in>;
+                        lanes = <1 0 3 2 5 4 7 6>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts
index aa98fea3f2b3..337bbbc01a35 100644
--- a/arch/arm/boot/dts/omap5-sbc-t54.dts
+++ b/arch/arm/boot/dts/omap5-sbc-t54.dts
@@ -1,11 +1,11 @@
 /*
- * Suppport for CompuLab SBC-T54 with CM-T54
+ * Suppport for CompuLab CM-T54 on SB-T54 baseboard
  */
 
 #include "omap5-cm-t54.dts"
 
 / {
-        model = "CompuLab SBC-T54 with CM-T54";
+        model = "CompuLab CM-T54 on SB-T54";
         compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5";
 };
 
@@ -19,8 +19,8 @@
 
         mmc1_aux_pins: pinmux_mmc1_aux_pins {
                 pinctrl-single,pins = <
-                        OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */
-                        OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */
+                        OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */
+                        OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */
                 >;
         };
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc8df1739f39..256b7f69e45b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -104,8 +104,9 @@
         soc {
                 compatible = "ti,omap-infra";
                 mpu {
-                        compatible = "ti,omap5-mpu";
+                        compatible = "ti,omap4-mpu";
                         ti,hwmods = "mpu";
+                        sram = <&ocmcram>;
                 };
         };
 
@@ -131,6 +132,7 @@
                 prm: prm@4ae06000 {
                         compatible = "ti,omap5-prm";
                         reg = <0x4ae06000 0x3000>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
                         prm_clocks: clocks {
                                 #address-cells = <1>;
@@ -187,18 +189,22 @@
                 };
 
                 omap5_pmx_core: pinmux@4a002840 {
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        compatible = "ti,omap5-padconf", "pinctrl-single";
                         reg = <0x4a002840 0x01b6>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
                         pinctrl-single,register-width = <16>;
                         pinctrl-single,function-mask = <0x7fff>;
                 };
                 omap5_pmx_wkup: pinmux@4ae0c840 {
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        compatible = "ti,omap5-padconf", "pinctrl-single";
                         reg = <0x4ae0c840 0x0038>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
                         pinctrl-single,register-width = <16>;
                         pinctrl-single,function-mask = <0x7fff>;
                 };
@@ -219,6 +225,11 @@
                         };
                 };
 
+                ocmcram: ocmcram@40300000 {
+                        compatible = "mmio-sram";
+                        reg = <0x40300000 0x20000>; /* 128k */
+                };
+
                 sdma: dma-controller@4a056000 {
                         compatible = "ti,omap4430-sdma";
                         reg = <0x4a056000 0x1000>;
@@ -447,7 +458,7 @@
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
@@ -455,7 +466,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
@@ -463,7 +474,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
@@ -471,7 +482,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
@@ -479,7 +490,7 @@
                 uart5: serial@48066000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48066000 0x100>;
-                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
                 };
@@ -487,7 +498,7 @@
                 uart6: serial@48068000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48068000 0x100>;
-                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                 };
@@ -642,6 +653,14 @@
                         ti,hwmods = "mailbox";
                         ti,mbox-num-users = <3>;
                         ti,mbox-num-fifos = <8>;
+                        mbox_ipu: mbox_ipu {
+                                ti,mbox-tx = <0 0 0>;
+                                ti,mbox-rx = <1 0 0>;
+                        };
+                        mbox_dsp: mbox_dsp {
+                                ti,mbox-tx = <3 0 0>;
+                                ti,mbox-rx = <2 0 0>;
+                        };
                 };
 
                 timer1: timer@4ae18000 {
@@ -945,6 +964,15 @@
                                 clock-names = "fck";
                         };
 
+                        rfbi: encoder@58002000  {
+                                compatible = "ti,omap5-rfbi";
+                                reg = <0x58002000 0x100>;
+                                status = "disabled";
+                                ti,hwmods = "dss_rfbi";
+                                clocks = <&dss_dss_clk>, <&l3_iclk_div>;
+                                clock-names = "fck", "ick";
+                        };
+
                         dsi1: encoder@58004000 {
                                 compatible = "ti,omap5-dsi";
                                 reg = <0x58004000 0x200>,
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index e67a23b5d788..58c27466f012 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -367,10 +367,12 @@
 
         l3_iclk_div: l3_iclk_div {
                 #clock-cells = <0>;
-                compatible = "fixed-factor-clock";
+                compatible = "ti,divider-clock";
+                ti,max-div = <2>;
+                ti,bit-shift = <4>;
+                reg = <0x100>;
                 clocks = <&dpll_core_h12x2_ck>;
-                clock-mult = <1>;
-                clock-div = <1>;
+                ti,index-power-of-two;
         };
 
         gpu_l3_iclk: gpu_l3_iclk {
@@ -383,10 +385,12 @@
 
         l4_root_clk_div: l4_root_clk_div {
                 #clock-cells = <0>;
-                compatible = "fixed-factor-clock";
+                compatible = "ti,divider-clock";
+                ti,max-div = <2>;
+                ti,bit-shift = <8>;
+                reg = <0x100>;
                 clocks = <&l3_iclk_div>;
-                clock-mult = <1>;
-                clock-div = <1>;
+                ti,index-power-of-two;
         };
 
         slimbus1_slimbus_clk: slimbus1_slimbus_clk {
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index a5e90f078aa9..c08f84629aa9 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -113,14 +113,14 @@
                 };
 
                 usb0: ohci@4c000000 {
-                        compatible = "mrvl,pxa-ohci";
+                        compatible = "marvell,pxa-ohci";
                         reg = <0x4c000000 0x10000>;
                         interrupts = <3>;
                         status = "disabled";
                 };
 
                 mmc0: mmc@41100000 {
-                        compatible = "mrvl,pxa-mmc";
+                        compatible = "marvell,pxa-mmc";
                         reg = <0x41100000 0x1000>;
                         interrupts = <23>;
                         status = "disabled";
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 7c2441d526bc..b396c8311b27 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -5,6 +5,33 @@
         compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
 
         soc {
+                pinctrl@800000 {
+                        i2c1_pins: i2c1 {
+                                mux {
+                                        pins = "gpio20", "gpio21";
+                                        function = "gsbi1";
+                                };
+                        };
+                };
+
+                gsbi@12440000 {
+                        status = "okay";
+                        qcom,mode = <GSBI_PROT_I2C>;
+
+                        i2c@12460000 {
+                                status = "okay";
+                                clock-frequency = <200000>;
+                                pinctrl-0 = <&i2c1_pins>;
+                                pinctrl-names = "default";
+
+                                eeprom: eeprom@52 {
+                                        compatible = "atmel,24c128";
+                                        reg = <0x52>;
+                                        pagesize = <32>;
+                                };
+                        };
+                };
+
                 gsbi@16600000 {
                         status = "ok";
                         qcom,mode = <GSBI_PROT_I2C_UART>;
@@ -12,5 +39,21 @@
                                 status = "ok";
                         };
                 };
+
+                amba {
+                        /* eMMC */
+                        sdcc1: sdcc@12400000 {
+                                status = "okay";
+                        };
+
+                        /* External micro SD card */
+                        sdcc3: sdcc@12180000 {
+                                status = "okay";
+                        };
+                        /* WLAN */
+                        sdcc4: sdcc@121c0000 {
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92bf793622c3..b3154c071652 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -2,7 +2,9 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
         model = "Qualcomm APQ8064";
@@ -70,6 +72,34 @@
                 ranges;
                 compatible = "simple-bus";
 
+                tlmm_pinmux: pinctrl@800000 {
+                        compatible = "qcom,apq8064-pinctrl";
+                        reg = <0x800000 0x4000>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ps_hold>;
+
+                        sdc4_gpios: sdc4-gpios {
+                                pios {
+                                        pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
+                                        function = "sdc4";
+                                };
+                        };
+
+                        ps_hold: ps_hold {
+                                mux {
+                                        pins = "gpio78";
+                                        function = "ps_hold";
+                                };
+                        };
+                };
+
                 intc: interrupt-controller@2000000 {
                         compatible = "qcom,msm-qgic2";
                         interrupt-controller;
@@ -133,6 +163,48 @@
                         regulator;
                 };
 
+                gsbi1: gsbi@12440000 {
+                        status = "disabled";
+                        compatible = "qcom,gsbi-v1.0.0";
+                        reg = <0x12440000 0x100>;
+                        clocks = <&gcc GSBI1_H_CLK>;
+                        clock-names = "iface";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        i2c1: i2c@12460000 {
+                                compatible = "qcom,i2c-qup-v1.1.1";
+                                reg = <0x12460000 0x1000>;
+                                interrupts = <0 194 IRQ_TYPE_NONE>;
+                                clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+                                clock-names = "core", "iface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
+                gsbi2: gsbi@12480000 {
+                        status = "disabled";
+                        compatible = "qcom,gsbi-v1.0.0";
+                        reg = <0x12480000 0x100>;
+                        clocks = <&gcc GSBI2_H_CLK>;
+                        clock-names = "iface";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        i2c2: i2c@124a0000 {
+                                compatible = "qcom,i2c-qup-v1.1.1";
+                                reg = <0x124a0000 0x1000>;
+                                interrupts = <0 196 IRQ_TYPE_NONE>;
+                                clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
+                                clock-names = "core", "iface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
                 gsbi7: gsbi@16600000 {
                         status = "disabled";
                         compatible = "qcom,gsbi-v1.0.0";
@@ -166,5 +238,116 @@
                         #clock-cells = <1>;
                         #reset-cells = <1>;
                 };
+
+                mmcc: clock-controller@4000000 {
+                        compatible = "qcom,mmcc-apq8064";
+                        reg = <0x4000000 0x1000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+
+                /* Temporary fixed regulator */
+                vsdcc_fixed: vsdcc-regulator {
+                        compatible = "regulator-fixed";
+                        regulator-name = "SDCC Power";
+                        regulator-min-microvolt = <2700000>;
+                        regulator-max-microvolt = <2700000>;
+                        regulator-always-on;
+                };
+
+                sdcc1bam:dma@12402000{
+                        compatible = "qcom,bam-v1.3.0";
+                        reg = <0x12402000 0x8000>;
+                        interrupts = <0 98 0>;
+                        clocks = <&gcc SDC1_H_CLK>;
+                        clock-names = "bam_clk";
+                        #dma-cells = <1>;
+                        qcom,ee = <0>;
+                };
+
+                sdcc3bam:dma@12182000{
+                        compatible = "qcom,bam-v1.3.0";
+                        reg = <0x12182000 0x8000>;
+                        interrupts = <0 96 0>;
+                        clocks = <&gcc SDC3_H_CLK>;
+                        clock-names = "bam_clk";
+                        #dma-cells = <1>;
+                        qcom,ee = <0>;
+                };
+
+                sdcc4bam:dma@121c2000{
+                        compatible = "qcom,bam-v1.3.0";
+                        reg = <0x121c2000 0x8000>;
+                        interrupts = <0 95 0>;
+                        clocks = <&gcc SDC4_H_CLK>;
+                        clock-names = "bam_clk";
+                        #dma-cells = <1>;
+                        qcom,ee = <0>;
+                };
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        sdcc1: sdcc@12400000 {
+                                status          = "disabled";
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                reg             = <0x12400000 0x2000>;
+                                interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <8>;
+                                max-frequency   = <96000000>;
+                                non-removable;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                vmmc-supply = <&vsdcc_fixed>;
+                                dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+                                dma-names = "tx", "rx";
+                        };
+
+                        sdcc3: sdcc@12180000 {
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                status          = "disabled";
+                                reg             = <0x12180000 0x2000>;
+                                interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <4>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                max-frequency   = <192000000>;
+                                no-1-8-v;
+                                vmmc-supply = <&vsdcc_fixed>;
+                                dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+                                dma-names = "tx", "rx";
+                        };
+
+                        sdcc4: sdcc@121c0000 {
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                status          = "disabled";
+                                reg             = <0x121c0000 0x2000>;
+                                interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <4>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                max-frequency   = <48000000>;
+                                vmmc-supply = <&vsdcc_fixed>;
+                                vqmmc-supply = <&vsdcc_fixed>;
+                                dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
+                                dma-names = "tx", "rx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&sdc4_gpios>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index b4dfb01fe6fb..47370494d0f8 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -22,6 +22,13 @@
 
 
                 pinctrl@fd510000 {
+                        i2c11_pins: i2c11 {
+                                mux {
+                                        pins = "gpio83", "gpio84";
+                                        function = "blsp_i2c11";
+                                };
+                        };
+
                         spi8_default: spi8_default {
                                 mosi {
                                         pins = "gpio45";
@@ -41,5 +48,19 @@
                                 };
                         };
                 };
+
+                i2c@f9967000 {
+                        status = "okay";
+                        clock-frequency = <200000>;
+                        pinctrl-0 = <&i2c11_pins>;
+                        pinctrl-names = "default";
+
+                        eeprom: eeprom@52 {
+                                compatible = "atmel,24c128";
+                                reg = <0x52>;
+                                pagesize = <32>;
+                                read-only;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
new file mode 100644
index 000000000000..c9ff10821ad9
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -0,0 +1,23 @@
+#include "qcom-apq8084.dtsi"
+
+/ {
+        model = "Qualcomm APQ8084/IFC6540";
+        compatible = "qcom,apq8084-ifc6540", "qcom,apq8084";
+
+        soc {
+                serial@f995e000 {
+                        status = "okay";
+                };
+
+                sdhci@f9824900 {
+                        bus-width = <8>;
+                        non-removable;
+                        status = "okay";
+                };
+
+                sdhci@f98a4900 {
+                        cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
+                        bus-width = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 9dae3878b71d..8ecec58a9ff6 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -3,4 +3,10 @@
 / {
         model = "Qualcomm APQ 8084-MTP";
         compatible = "qcom,apq8084-mtp", "qcom,apq8084";
+
+        soc {
+                serial@f995e000 {
+                        status = "okay";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index e3e009a5912b..1f130bc16858 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -2,6 +2,9 @@
 
 #include "skeleton.dtsi"
 
+#include <dt-bindings/clock/qcom,gcc-apq8084.h>
+#include <dt-bindings/gpio/gpio.h>
+
 / {
         model = "Qualcomm APQ 8084";
         compatible = "qcom,apq8084";
@@ -175,5 +178,53 @@
                         compatible = "qcom,pshold";
                         reg = <0xfc4ab000 0x4>;
                 };
+
+                gcc: clock-controller@fc400000 {
+                        compatible = "qcom,gcc-apq8084";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        reg = <0xfc400000 0x4000>;
+                };
+
+                tlmm: pinctrl@fd510000 {
+                        compatible = "qcom,apq8084-pinctrl";
+                        reg = <0xfd510000 0x4000>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 208 0>;
+                };
+
+                serial@f995e000 {
+                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                        reg = <0xf995e000 0x1000>;
+                        interrupts = <0 114 0x0>;
+                        clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+
+                sdhci@f9824900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 123 0>, <0 138 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+
+                sdhci@f98a4900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 125 0>, <0 221 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
new file mode 100644
index 000000000000..95e64955fb8e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -0,0 +1,85 @@
+#include "qcom-ipq8064-v1.0.dtsi"
+
+/ {
+        model = "Qualcomm IPQ8064/AP148";
+        compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
+
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                rsvd@41200000 {
+                        reg = <0x41200000 0x300000>;
+                        no-map;
+                };
+        };
+
+        soc {
+                pinmux@800000 {
+                        i2c4_pins: i2c4_pinmux {
+                                pins = "gpio12", "gpio13";
+                                function = "gsbi4";
+                                bias-disable;
+                        };
+
+                        spi_pins: spi_pins {
+                                mux {
+                                        pins = "gpio18", "gpio19", "gpio21";
+                                        function = "gsbi5";
+                                        drive-strength = <10>;
+                                        bias-none;
+                                };
+                        };
+                };
+
+                gsbi@16300000 {
+                        qcom,mode = <GSBI_PROT_I2C_UART>;
+                        status = "ok";
+                        serial@16340000 {
+                                status = "ok";
+                        };
+
+                        i2c4: i2c@16380000 {
+                                status = "ok";
+
+                                clock-frequency = <200000>;
+
+                                pinctrl-0 = <&i2c4_pins>;
+                                pinctrl-names = "default";
+                        };
+                };
+
+                gsbi5: gsbi@1a200000 {
+                        qcom,mode = <GSBI_PROT_SPI>;
+                        status = "ok";
+
+                        spi4: spi@1a280000 {
+                                status = "ok";
+                                spi-max-frequency = <50000000>;
+
+                                pinctrl-0 = <&spi_pins>;
+                                pinctrl-names = "default";
+
+                                cs-gpios = <&qcom_pinmux 20 0>;
+
+                                flash: m25p80@0 {
+                                        compatible = "s25fl256s1";
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+
+                                        partition@0 {
+                                                label = "rootfs";
+                                                reg = <0x0 0x1000000>;
+                                        };
+
+                                        partition@1 {
+                                                label = "scratch";
+                                                reg = <0x1000000 0x1000000>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
new file mode 100644
index 000000000000..7093b075e408
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -0,0 +1 @@
+#include "qcom-ipq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
new file mode 100644
index 000000000000..244f857f0e6f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -0,0 +1,250 @@
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
+
+/ {
+        model = "Qualcomm IPQ8064";
+        compatible = "qcom,ipq8064";
+        interrupt-parent = <&intc>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                };
+
+                cpu@1 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                };
+
+                L2: l2-cache {
+                        compatible = "cache";
+                        cache-level = <2>;
+                };
+        };
+
+        cpu-pmu {
+                compatible = "qcom,krait-pmu";
+                interrupts = <1 10 0x304>;
+        };
+
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                nss@40000000 {
+                        reg = <0x40000000 0x1000000>;
+                        no-map;
+                };
+
+                smem@41000000 {
+                        reg = <0x41000000 0x200000>;
+                        no-map;
+                };
+        };
+
+        soc: soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "simple-bus";
+
+                qcom_pinmux: pinmux@800000 {
+                        compatible = "qcom,ipq8064-pinctrl";
+                        reg = <0x800000 0x4000>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 32 0x4>;
+                };
+
+                intc: interrupt-controller@2000000 {
+                        compatible = "qcom,msm-qgic2";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x02000000 0x1000>,
+                              <0x02002000 0x1000>;
+                };
+
+                timer@200a000 {
+                        compatible = "qcom,kpss-timer", "qcom,msm-timer";
+                        interrupts = <1 1 0x301>,
+                                     <1 2 0x301>,
+                                     <1 3 0x301>;
+                        reg = <0x0200a000 0x100>;
+                        clock-frequency = <25000000>,
+                                          <32768>;
+                        cpu-offset = <0x80000>;
+                };
+
+                acc0: clock-controller@2088000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+                };
+
+                acc1: clock-controller@2098000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+                };
+
+                saw0: regulator@2089000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+                        regulator;
+                };
+
+                saw1: regulator@2099000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+                        regulator;
+                };
+
+                gsbi2: gsbi@12480000 {
+                        compatible = "qcom,gsbi-v1.0.0";
+                        reg = <0x12480000 0x100>;
+                        clocks = <&gcc GSBI2_H_CLK>;
+                        clock-names = "iface";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        status = "disabled";
+
+                        serial@12490000 {
+                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                                reg = <0x12490000 0x1000>,
+                                      <0x12480000 0x1000>;
+                                interrupts = <0 195 0x0>;
+                                clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+                        };
+
+                        i2c@124a0000 {
+                                compatible = "qcom,i2c-qup-v1.1.1";
+                                reg = <0x124a0000 0x1000>;
+                                interrupts = <0 196 0>;
+
+                                clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                };
+
+                gsbi4: gsbi@16300000 {
+                        compatible = "qcom,gsbi-v1.0.0";
+                        reg = <0x16300000 0x100>;
+                        clocks = <&gcc GSBI4_H_CLK>;
+                        clock-names = "iface";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        status = "disabled";
+
+                        serial@16340000 {
+                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                                reg = <0x16340000 0x1000>,
+                                      <0x16300000 0x1000>;
+                                interrupts = <0 152 0x0>;
+                                clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+                        };
+
+                        i2c@16380000 {
+                                compatible = "qcom,i2c-qup-v1.1.1";
+                                reg = <0x16380000 0x1000>;
+                                interrupts = <0 153 0>;
+
+                                clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
+                gsbi5: gsbi@1a200000 {
+                        compatible = "qcom,gsbi-v1.0.0";
+                        reg = <0x1a200000 0x100>;
+                        clocks = <&gcc GSBI5_H_CLK>;
+                        clock-names = "iface";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        status = "disabled";
+
+                        serial@1a240000 {
+                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                                reg = <0x1a240000 0x1000>,
+                                      <0x1a200000 0x1000>;
+                                interrupts = <0 154 0x0>;
+                                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+                        };
+
+                        i2c@1a280000 {
+                                compatible = "qcom,i2c-qup-v1.1.1";
+                                reg = <0x1a280000 0x1000>;
+                                interrupts = <0 155 0>;
+
+                                clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        spi@1a280000 {
+                                compatible = "qcom,spi-qup-v1.1.1";
+                                reg = <0x1a280000 0x1000>;
+                                interrupts = <0 155 0>;
+
+                                clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
+                qcom,ssbi@500000 {
+                        compatible = "qcom,ssbi";
+                        reg = <0x00500000 0x1000>;
+                        qcom,controller-type = "pmic-arbiter";
+                };
+
+                gcc: clock-controller@900000 {
+                        compatible = "qcom,gcc-ipq8064";
+                        reg = <0x00900000 0x4000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 45180adfadf1..e0883c376248 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/input/input.h>
+
 #include "qcom-msm8660.dtsi"
 
 / {
@@ -12,5 +14,45 @@
                                 status = "ok";
                         };
                 };
+
+                amba {
+                        /* eMMC */
+                        sdcc1: sdcc@12400000 {
+                                status = "okay";
+                        };
+
+                        /* External micro SD card */
+                        sdcc3: sdcc@12180000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
+
+&pmicintc {
+        keypad@148 {
+                linux,keymap = <
+                        MATRIX_KEY(0, 0, KEY_FN_F1)
+                        MATRIX_KEY(0, 1, KEY_UP)
+                        MATRIX_KEY(0, 2, KEY_LEFT)
+                        MATRIX_KEY(0, 3, KEY_VOLUMEUP)
+                        MATRIX_KEY(1, 0, KEY_FN_F2)
+                        MATRIX_KEY(1, 1, KEY_RIGHT)
+                        MATRIX_KEY(1, 2, KEY_DOWN)
+                        MATRIX_KEY(1, 3, KEY_VOLUMEDOWN)
+                        MATRIX_KEY(2, 3, KEY_ENTER)
+                        MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS)
+                        MATRIX_KEY(4, 1, KEY_UP)
+                        MATRIX_KEY(4, 2, KEY_LEFT)
+                        MATRIX_KEY(4, 3, KEY_HOME)
+                        MATRIX_KEY(4, 4, KEY_FN_F3)
+                        MATRIX_KEY(5, 0, KEY_CAMERA)
+                        MATRIX_KEY(5, 1, KEY_RIGHT)
+                        MATRIX_KEY(5, 2, KEY_DOWN)
+                        MATRIX_KEY(5, 3, KEY_BACK)
+                        MATRIX_KEY(5, 4, KEY_MENU)
+                        >;
+                keypad,num-rows = <6>;
+                keypad,num-columns = <5>;
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 53837aaa2f72..0affd6193f56 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -2,6 +2,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
 
@@ -103,6 +104,98 @@
                         compatible = "qcom,ssbi";
                         reg = <0x500000 0x1000>;
                         qcom,controller-type = "pmic-arbiter";
+
+                        pmicintc: pmic@0 {
+                                compatible = "qcom,pm8058";
+                                interrupt-parent = <&msmgpio>;
+                                interrupts = <88 8>;
+                                #interrupt-cells = <2>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                pwrkey@1c {
+                                        compatible = "qcom,pm8058-pwrkey";
+                                        reg = <0x1c>;
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts = <50 1>, <51 1>;
+                                        debounce = <15625>;
+                                        pull-up;
+                                };
+
+                                keypad@148 {
+                                        compatible = "qcom,pm8058-keypad";
+                                        reg = <0x148>;
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts = <74 1>, <75 1>;
+                                        debounce = <15>;
+                                        scan-delay = <32>;
+                                        row-hold = <91500>;
+                                };
+
+                                rtc@11d {
+                                        compatible = "qcom,pm8058-rtc";
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts = <39 1>;
+                                        reg = <0x11d>;
+                                        allow-set-time;
+                                };
+
+                                vibrator@4a {
+                                        compatible = "qcom,pm8058-vib";
+                                        reg = <0x4a>;
+                                };
+                        };
+                };
+
+                /* Temporary fixed regulator */
+                vsdcc_fixed: vsdcc-regulator {
+                        compatible = "regulator-fixed";
+                        regulator-name = "SDCC Power";
+                        regulator-min-microvolt = <2700000>;
+                        regulator-max-microvolt = <2700000>;
+                        regulator-always-on;
+                };
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        sdcc1: sdcc@12400000 {
+                                status          = "disabled";
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                reg             = <0x12400000 0x8000>;
+                                interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <8>;
+                                max-frequency   = <48000000>;
+                                non-removable;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                vmmc-supply = <&vsdcc_fixed>;
+                        };
+
+                        sdcc3: sdcc@12180000 {
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                status          = "disabled";
+                                reg             = <0x12180000 0x8000>;
+                                interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <4>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                max-frequency   = <48000000>;
+                                no-1-8-v;
+                                vmmc-supply = <&vsdcc_fixed>;
+                        };
                 };
         };
+
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 8f75cc4c8340..7f70fae90959 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -1,3 +1,5 @@
+#include <dt-bindings/input/input.h>
+
 #include "qcom-msm8960.dtsi"
 
 / {
@@ -12,5 +14,30 @@
                                 status = "ok";
                         };
                 };
+
+                amba {
+                        /* eMMC */
+                        sdcc1: sdcc@12400000 {
+                                status = "okay";
+                        };
+
+                        /* External micro SD card */
+                        sdcc3: sdcc@12180000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
+
+&pmicintc {
+        keypad@148 {
+                linux,keymap = <
+                        MATRIX_KEY(0, 0, KEY_VOLUMEUP)
+                        MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
+                        MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
+                        MATRIX_KEY(0, 3, KEY_CAMERA)
+                        >;
+                keypad,num-rows = <1>;
+                keypad,num-columns = <5>;
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 5303e53e34dc..e1b0d5cd9e3c 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -2,6 +2,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
 
@@ -143,6 +144,43 @@
                         compatible = "qcom,ssbi";
                         reg = <0x500000 0x1000>;
                         qcom,controller-type = "pmic-arbiter";
+
+                        pmicintc: pmic@0 {
+                                compatible = "qcom,pm8921";
+                                interrupt-parent = <&msmgpio>;
+                                interrupts = <104 8>;
+                                #interrupt-cells = <2>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                pwrkey@1c {
+                                        compatible = "qcom,pm8921-pwrkey";
+                                        reg = <0x1c>;
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts = <50 1>, <51 1>;
+                                        debounce = <15625>;
+                                        pull-up;
+                                };
+
+                                keypad@148 {
+                                        compatible = "qcom,pm8921-keypad";
+                                        reg = <0x148>;
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts = <74 1>, <75 1>;
+                                        debounce = <15>;
+                                        scan-delay = <32>;
+                                        row-hold = <91500>;
+                                };
+
+                                rtc@11d {
+                                        compatible = "qcom,pm8921-rtc";
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts = <39 1>;
+                                        reg = <0x11d>;
+                                        allow-set-time;
+                                };
+                        };
                 };
 
                 rng@1a500000 {
@@ -151,5 +189,54 @@
                         clocks = <&gcc PRNG_CLK>;
                         clock-names = "core";
                 };
+
+                /* Temporary fixed regulator */
+                vsdcc_fixed: vsdcc-regulator {
+                        compatible = "regulator-fixed";
+                        regulator-name = "SDCC Power";
+                        regulator-min-microvolt = <2700000>;
+                        regulator-max-microvolt = <2700000>;
+                        regulator-always-on;
+                };
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        sdcc1: sdcc@12400000 {
+                                status          = "disabled";
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                reg             = <0x12400000 0x8000>;
+                                interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <8>;
+                                max-frequency   = <96000000>;
+                                non-removable;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                vmmc-supply = <&vsdcc_fixed>;
+                        };
+
+                        sdcc3: sdcc@12180000 {
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                status          = "disabled";
+                                reg             = <0x12180000 0x8000>;
+                                interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <4>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                max-frequency   = <192000000>;
+                                no-1-8-v;
+                                vmmc-supply = <&vsdcc_fixed>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 69dca2aca25a..e265ec16a787 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,8 +1,8 @@
 /dts-v1/;
 
-#include "skeleton.dtsi"
-
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
+#include "skeleton.dtsi"
 
 / {
         model = "Qualcomm MSM8974";
@@ -236,5 +236,16 @@
                         #interrupt-cells = <2>;
                         interrupts = <0 208 0>;
                 };
+
+                blsp_i2c11: i2c@f9967000 {
+                        status = "disable";
+                        compatible = "qcom,i2c-qup-v2.1.1";
+                        reg = <0xf9967000 0x1000>;
+                        interrupts = <0 105 IRQ_TYPE_NONE>;
+                        clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 20705467f4c9..a3ed23c0a8f5 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -43,6 +43,10 @@
         clock-frequency = <48000000>;
 };
 
+&mtu2 {
+        status = "ok";
+};
+
 &i2c2 {
         status = "okay";
         clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index bdee22541189..801a556e264b 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -229,6 +229,16 @@
                 status = "disabled";
         };
 
+        mtu2: timer@fcff0000 {
+                compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+                reg = <0xfcff0000 0x400>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "tgi0a";
+                clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+                clock-names = "fck";
+                status = "disabled";
+        };
+
         scif0: serial@e8007000 {
                 compatible = "renesas,scif-r7s72100", "renesas,scif";
                 reg = <0xe8007000 64>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index d8ec5058c351..ef152e384822 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -51,7 +51,7 @@
         };
 
         irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc";
+                compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
@@ -90,7 +90,7 @@
         };
 
         irqc1: interrupt-controller@e61c0200 {
-                compatible = "renesas,irqc";
+                compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0 0xe61c0200 0 0x200>;
@@ -165,7 +165,7 @@
         };
 
         thermal@e61f0000 {
-                compatible = "renesas,rcar-thermal";
+                compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
                          <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
deleted file mode 100644
index ee9e7d5c97a9..000000000000
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Reference Device Tree Source for the armadillo 800 eva board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-#include "r8a7740.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
-        model = "armadillo 800 eva reference";
-        compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
-
-        aliases {
-                serial1 = &scifa1;
-        };
-
-        chosen {
-                bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x40000000 0x20000000>;
-        };
-
-        reg_3p3v: regulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-3.3V";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                regulator-always-on;
-                regulator-boot-on;
-        };
-
-        vcc_sdhi0: regulator@1 {
-                compatible = "regulator-fixed";
-
-                regulator-name = "SDHI0 Vcc";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-
-                gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
-                enable-active-high;
-        };
-
-        vccq_sdhi0: regulator@2 {
-                compatible = "regulator-gpio";
-
-                regulator-name = "SDHI0 VccQ";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <3300000>;
-                vin-supply = <&vcc_sdhi0>;
-
-                enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
-                gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
-                states = <3300000 0
-                          1800000 1>;
-
-                enable-active-high;
-        };
-
-        reg_5p0v: regulator@3 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-5.0V";
-                regulator-min-microvolt = <5000000>;
-                regulator-max-microvolt = <5000000>;
-                regulator-always-on;
-                regulator-boot-on;
-        };
-
-        gpio-keys {
-                compatible = "gpio-keys";
-
-                power-key {
-                        gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_POWER>;
-                        label = "SW3";
-                        gpio-key,wakeup;
-                };
-
-                back-key {
-                        gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_BACK>;
-                        label = "SW4";
-                };
-
-                menu-key {
-                        gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_MENU>;
-                        label = "SW5";
-                };
-
-                home-key {
-                        gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_HOME>;
-                        label = "SW6";
-                };
-        };
-
-        leds {
-                compatible = "gpio-leds";
-                led3 {
-                        gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
-                        label = "LED3";
-                };
-                led4 {
-                        gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
-                        label = "LED4";
-                };
-                led5 {
-                        gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
-                        label = "LED5";
-                };
-                led6 {
-                        gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
-                        label = "LED6";
-                };
-        };
-
-        i2c2: i2c@2 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "i2c-gpio";
-                gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
-                         &pfc 91 GPIO_ACTIVE_HIGH /* scl */
-                        >;
-                i2c-gpio,delay-us = <5>;
-        };
-
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
-                brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
-                default-brightness-level = <9>;
-                pinctrl-0 = <&backlight_pins>;
-                pinctrl-names = "default";
-                power-supply = <&reg_5p0v>;
-                enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
-        };
-
-        sound {
-                compatible = "simple-audio-card";
-
-                simple-audio-card,format = "i2s";
-
-                simple-audio-card,cpu {
-                        sound-dai = <&sh_fsi2 0>;
-                        bitclock-inversion;
-                };
-
-                simple-audio-card,codec {
-                        sound-dai = <&wm8978>;
-                        bitclock-master;
-                        frame-master;
-                        system-clock-frequency = <12288000>;
-                };
-        };
-};
-
-&ether {
-        pinctrl-0 = <&ether_pins>;
-        pinctrl-names = "default";
-
-        phy-handle = <&phy0>;
-        status = "ok";
-
-        phy0: ethernet-phy@0 {
-                reg = <0>;
-        };
-};
-
-&i2c0 {
-        status = "okay";
-        touchscreen@55 {
-                compatible = "sitronix,st1232";
-                reg = <0x55>;
-                interrupt-parent = <&irqpin1>;
-                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-                pinctrl-0 = <&st1232_pins>;
-                pinctrl-names = "default";
-                gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
-        };
-
-        wm8978: wm8978@1a {
-                #sound-dai-cells = <0>;
-                compatible = "wlf,wm8978";
-                reg = <0x1a>;
-        };
-};
-
-&i2c2 {
-        status = "okay";
-        rtc@30 {
-                compatible = "sii,s35390a";
-                reg = <0x30>;
-        };
-};
-
-&pfc {
-        ether_pins: ether {
-                renesas,groups = "gether_mii", "gether_int";
-                renesas,function = "gether";
-        };
-
-        scifa1_pins: serial1 {
-                renesas,groups = "scifa1_data";
-                renesas,function = "scifa1";
-        };
-
-        st1232_pins: touchscreen {
-                renesas,groups = "intc_irq10";
-                renesas,function = "intc";
-        };
-
-        backlight_pins: backlight {
-                renesas,groups = "tpu0_to2_1";
-                renesas,function = "tpu0";
-        };
-
-        mmc0_pins: mmc0 {
-                renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
-                renesas,function = "mmc0";
-        };
-
-        sdhi0_pins: sd0 {
-                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
-                renesas,function = "sdhi0";
-        };
-
-        fsia_pins: sounda {
-                renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
-                                 "fsia_data_in_1", "fsia_data_out_0";
-                renesas,function = "fsia";
-        };
-};
-
-&tpu {
-        status = "okay";
-};
-
-&mmcif0 {
-        pinctrl-0 = <&mmc0_pins>;
-        pinctrl-names = "default";
-
-        vmmc-supply = <&reg_3p3v>;
-        bus-width = <8>;
-        non-removable;
-        status = "okay";
-};
-
-&scifa1 {
-        pinctrl-0 = <&scifa1_pins>;
-        pinctrl-names = "default";
-
-        status = "okay";
-};
-
-&sdhi0 {
-        pinctrl-0 = <&sdhi0_pins>;
-        pinctrl-names = "default";
-
-        vmmc-supply = <&vcc_sdhi0>;
-        vqmmc-supply = <&vccq_sdhi0>;
-        bus-width = <4>;
-        cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
-        status = "okay";
-};
-
-&sh_fsi2 {
-        pinctrl-0 = <&fsia_pins>;
-        pinctrl-names = "default";
-
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index a06a11e1a840..effb7b46f131 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -10,10 +10,18 @@
 
 /dts-v1/;
 #include "r8a7740.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
 
 / {
         model = "armadillo 800 eva";
-        compatible = "renesas,armadillo800eva";
+        compatible = "renesas,armadillo800eva", "renesas,r8a7740";
+
+        aliases {
+                serial1 = &scifa1;
+        };
 
         chosen {
                 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
@@ -23,4 +31,270 @@
                 device_type = "memory";
                 reg = <0x40000000 0x20000000>;
         };
+
+        reg_3p3v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        vcc_sdhi0: regulator@1 {
+                compatible = "regulator-fixed";
+
+                regulator-name = "SDHI0 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+
+                gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        vccq_sdhi0: regulator@2 {
+                compatible = "regulator-gpio";
+
+                regulator-name = "SDHI0 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vcc_sdhi0>;
+
+                enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
+                gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
+                states = <3300000 0
+                          1800000 1>;
+
+                enable-active-high;
+        };
+
+        reg_5p0v: regulator@3 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-5.0V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power-key {
+                        gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        label = "SW3";
+                        gpio-key,wakeup;
+                };
+
+                back-key {
+                        gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_BACK>;
+                        label = "SW4";
+                };
+
+                menu-key {
+                        gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_MENU>;
+                        label = "SW5";
+                };
+
+                home-key {
+                        gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_HOME>;
+                        label = "SW6";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led3 {
+                        gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
+                        label = "LED3";
+                };
+                led4 {
+                        gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
+                        label = "LED4";
+                };
+                led5 {
+                        gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
+                        label = "LED5";
+                };
+                led6 {
+                        gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
+                        label = "LED6";
+                };
+        };
+
+        i2c2: i2c@2 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
+                         &pfc 91 GPIO_ACTIVE_HIGH /* scl */
+                        >;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
+                default-brightness-level = <9>;
+                pinctrl-0 = <&backlight_pins>;
+                pinctrl-names = "default";
+                power-supply = <&reg_5p0v>;
+                enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,format = "i2s";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&sh_fsi2 0>;
+                        bitclock-inversion;
+                };
+
+                simple-audio-card,codec {
+                        sound-dai = <&wm8978>;
+                        bitclock-master;
+                        frame-master;
+                        system-clock-frequency = <12288000>;
+                };
+        };
+};
+
+&ether {
+        pinctrl-0 = <&ether_pins>;
+        pinctrl-names = "default";
+
+        phy-handle = <&phy0>;
+        status = "ok";
+
+        phy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+
+&extal1_clk {
+        clock-frequency = <25000000>;
+};
+&extal2_clk {
+        clock-frequency = <48000000>;
+};
+&fsibck_clk {
+        clock-frequency = <12288000>;
+};
+&cpg_clocks {
+        renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
+};
+
+&cmt1 {
+        status = "ok";
+};
+
+&i2c0 {
+        status = "okay";
+        touchscreen@55 {
+                compatible = "sitronix,st1232";
+                reg = <0x55>;
+                interrupt-parent = <&irqpin1>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-0 = <&st1232_pins>;
+                pinctrl-names = "default";
+                gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
+        };
+
+        wm8978: wm8978@1a {
+                #sound-dai-cells = <0>;
+                compatible = "wlf,wm8978";
+                reg = <0x1a>;
+        };
+};
+
+&i2c2 {
+        status = "okay";
+        rtc@30 {
+                compatible = "sii,s35390a";
+                reg = <0x30>;
+        };
+};
+
+&pfc {
+        ether_pins: ether {
+                renesas,groups = "gether_mii", "gether_int";
+                renesas,function = "gether";
+        };
+
+        scifa1_pins: serial1 {
+                renesas,groups = "scifa1_data";
+                renesas,function = "scifa1";
+        };
+
+        st1232_pins: touchscreen {
+                renesas,groups = "intc_irq10";
+                renesas,function = "intc";
+        };
+
+        backlight_pins: backlight {
+                renesas,groups = "tpu0_to2_1";
+                renesas,function = "tpu0";
+        };
+
+        mmc0_pins: mmc0 {
+                renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
+                renesas,function = "mmc0";
+        };
+
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
+                renesas,function = "sdhi0";
+        };
+
+        fsia_pins: sounda {
+                renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
+                                 "fsia_data_in_1", "fsia_data_out_0";
+                renesas,function = "fsia";
+        };
+};
+
+&tpu {
+        status = "okay";
+};
+
+&mmcif0 {
+        pinctrl-0 = <&mmc0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&reg_3p3v>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+
+&scifa1 {
+        pinctrl-0 = <&scifa1_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&vcc_sdhi0>;
+        vqmmc-supply = <&vccq_sdhi0>;
+        bus-width = <4>;
+        cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&sh_fsi2 {
+        pinctrl-0 = <&fsia_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index bda18fb3d9e5..d46c213a17ad 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -10,6 +10,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/r8a7740-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -40,6 +41,18 @@
                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
         };
 
+        cmt1: timer@e6138000 {
+                compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
+                reg = <0xe6138000 0x170>;
+                interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
+                clock-names = "fck";
+
+                renesas,channels-mask = <0x3f>;
+
+                status = "disabled";
+        };
+
         /* irqpin0: IRQ0 - IRQ7 */
         irqpin0: irqpin@e6900000 {
                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
@@ -125,7 +138,7 @@
                 reg = <0xe9a00000 0x800>,
                       <0xe9a01800 0x800>;
                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
-                /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */
+                clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
                 phy-mode = "mii";
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -141,6 +154,7 @@
                               0 202 IRQ_TYPE_LEVEL_HIGH
                               0 203 IRQ_TYPE_LEVEL_HIGH
                               0 204 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
                 status = "disabled";
         };
 
@@ -153,6 +167,7 @@
                               0 71 IRQ_TYPE_LEVEL_HIGH
                               0 72 IRQ_TYPE_LEVEL_HIGH
                               0 73 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
                 status = "disabled";
         };
 
@@ -160,6 +175,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6c40000 0x100>;
                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -167,6 +184,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6c50000 0x100>;
                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -174,6 +193,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6c60000 0x100>;
                 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -181,6 +202,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6c70000 0x100>;
                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -188,6 +211,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6c80000 0x100>;
                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -195,6 +220,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6cb0000 0x100>;
                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -202,6 +229,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6cc0000 0x100>;
                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -209,6 +238,8 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6cd0000 0x100>;
                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -216,6 +247,8 @@
                 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
                 reg = <0xe6c30000 0x100>;
                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -239,6 +272,7 @@
         tpu: pwm@e6600000 {
                 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
                 reg = <0xe6600000 0x100>;
+                clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
                 status = "disabled";
                 #pwm-cells = <3>;
         };
@@ -248,6 +282,7 @@
                 reg = <0xe6bd0000 0x100>;
                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
                               0 57 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7740_CLK_MMC>;
                 status = "disabled";
         };
 
@@ -257,6 +292,7 @@
                 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
                               0 118 IRQ_TYPE_LEVEL_HIGH
                               0 119 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -268,6 +304,7 @@
                 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
                               0 122 IRQ_TYPE_LEVEL_HIGH
                               0 123 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -279,6 +316,7 @@
                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
                               0 126 IRQ_TYPE_LEVEL_HIGH
                               0 127 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -289,6 +327,186 @@
                 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
                 reg = <0xfe1f0000 0x400>;
                 interrupts = <0 9 0x4>;
+                clocks = <&mstp3_clks R8A7740_CLK_FSI>;
                 status = "disabled";
         };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* External root clock */
+                extalr_clk: extalr_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "extalr";
+                };
+                extal1_clk: extal1_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "extal1";
+                };
+                extal2_clk: extal2_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "extal2";
+                };
+                dv_clk: dv_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                        clock-output-names = "dv";
+                };
+                fsiack_clk: fsiack_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fsiack";
+                };
+                fsibck_clk: fsibck_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fsibck";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7740-cpg-clocks";
+                        reg = <0xe6150000 0x10000>;
+                        clocks = <&extal1_clk>, <&extalr_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "system", "pllc0", "pllc1",
+                                             "pllc2", "r",
+                                             "usb24s",
+                                             "i", "zg", "b", "m1", "hp",
+                                             "hpp", "usbp", "s", "zb", "m3",
+                                             "cp";
+                };
+
+                /* Variable factor clocks (DIV6) */
+                sub_clk: sub_clk@e6150080 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150080 4>;
+                        clocks = <&pllc1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sub";
+                };
+
+                /* Fixed factor clocks */
+                pllc1_div2_clk: pllc1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pllc1_div2";
+                };
+                extal1_div2_clk: extal1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal1_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "extal1_div2";
+                };
+
+                /* Gate clocks */
+                subck_clks: subck_clks@e6150080 {
+                        compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150080 4>;
+                        clocks = <&sub_clk>, <&sub_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
+                        >;
+                        clock-output-names =
+                                "subck", "subck2";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150134 4>, <0xe6150038 4>;
+                        clocks = <&cpg_clocks R8A7740_CLK_S>,
+                                 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
+                                 <&cpg_clocks R8A7740_CLK_B>,
+                                 <&sub_clk>, <&sub_clk>,
+                                 <&cpg_clocks R8A7740_CLK_B>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
+                                R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
+                                R8A7740_CLK_LCDC0
+                        >;
+                        clock-output-names =
+                                "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
+                                "tmu1", "lcdc0";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150138 4>, <0xe6150040 4>;
+                        clocks = <&sub_clk>, <&sub_clk>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&sub_clk>, <&sub_clk>, <&sub_clk>,
+                                 <&sub_clk>, <&sub_clk>, <&sub_clk>,
+                                 <&sub_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
+                                R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
+                                R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
+                                R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
+                                R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
+                                R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
+                                R8A7740_CLK_SCIFA4
+                        >;
+                        clock-output-names =
+                                "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
+                                "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
+                                "scifa2", "scifa3", "scifa4";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe615013c 4>, <0xe6150048 4>;
+                        clocks = <&cpg_clocks R8A7740_CLK_R>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&sub_clk>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
+                                R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
+                                R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
+                        >;
+                        clock-output-names =
+                                "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
+                                "mmc", "gether", "tpu0";
+                };
+                mstp4_clks: mstp4_clks@e6150140 {
+                        compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150140 4>, <0xe615004c 4>;
+                        clocks = <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&cpg_clocks R8A7740_CLK_HP>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7740_CLK_USBH R8A7740_CLK_SDHI2
+                                R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
+                        >;
+                        clock-output-names =
+                                "usbhost", "sdhi2", "usbfunc", "usphy";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ecfdf4b01b5a..315ec62cb96b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -23,8 +23,14 @@
         interrupt-parent = <&gic>;
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        clock-frequency = <800000000>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 5745555df943..c160404e4d40 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -78,6 +78,10 @@
         clock-frequency = <31250000>;
 };
 
+&tmu0 {
+        status = "okay";
+};
+
 &pfc {
         lan0_pins: lan0 {
                 intc {
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 58d0d952d60e..7cfba9aa1b41 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -199,7 +199,6 @@
         scif0: serial@ffe40000 {
                 compatible = "renesas,scif-r8a7779", "renesas,scif";
                 reg = <0xffe40000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cpg_clocks R8A7779_CLK_P>;
                 clock-names = "sci_ick";
@@ -209,7 +208,6 @@
         scif1: serial@ffe41000 {
                 compatible = "renesas,scif-r8a7779", "renesas,scif";
                 reg = <0xffe41000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cpg_clocks R8A7779_CLK_P>;
                 clock-names = "sci_ick";
@@ -219,7 +217,6 @@
         scif2: serial@ffe42000 {
                 compatible = "renesas,scif-r8a7779", "renesas,scif";
                 reg = <0xffe42000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cpg_clocks R8A7779_CLK_P>;
                 clock-names = "sci_ick";
@@ -229,7 +226,6 @@
         scif3: serial@ffe43000 {
                 compatible = "renesas,scif-r8a7779", "renesas,scif";
                 reg = <0xffe43000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cpg_clocks R8A7779_CLK_P>;
                 clock-names = "sci_ick";
@@ -239,7 +235,6 @@
         scif4: serial@ffe44000 {
                 compatible = "renesas,scif-r8a7779", "renesas,scif";
                 reg = <0xffe44000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cpg_clocks R8A7779_CLK_P>;
                 clock-names = "sci_ick";
@@ -249,7 +244,6 @@
         scif5: serial@ffe45000 {
                 compatible = "renesas,scif-r8a7779", "renesas,scif";
                 reg = <0xffe45000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cpg_clocks R8A7779_CLK_P>;
                 clock-names = "sci_ick";
@@ -262,10 +256,52 @@
         };
 
         thermal@ffc48000 {
-                compatible = "renesas,rcar-thermal";
+                compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
                 reg = <0xffc48000 0x38>;
         };
 
+        tmu0: timer@ffd80000 {
+                compatible = "renesas,tmu-r8a7779", "renesas,tmu";
+                reg = <0xffd80000 0x30>;
+                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 34 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
+                clock-names = "fck";
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
+        tmu1: timer@ffd81000 {
+                compatible = "renesas,tmu-r8a7779", "renesas,tmu";
+                reg = <0xffd81000 0x30>;
+                interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 37 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 38 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
+                clock-names = "fck";
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
+        tmu2: timer@ffd82000 {
+                compatible = "renesas,tmu-r8a7779", "renesas,tmu";
+                reg = <0xffd82000 0x30>;
+                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 42 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
+                clock-names = "fck";
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
         sata: sata@fc600000 {
                 compatible = "renesas,rcar-sata";
                 reg = <0xfc600000 0x2000>;
@@ -404,10 +440,10 @@
                 /* Gate clocks */
                 mstp0_clks: clocks@ffc80030 {
                         compatible = "renesas,r8a7779-mstp-clocks",
-                                     "renesas,cpg-mstp-clocks";
+                                     "renesas,cpg-mstp-clocks";
                         reg = <0xffc80030 4>;
                         clocks = <&cpg_clocks R8A7779_CLK_S>,
-                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
                                  <&cpg_clocks R8A7779_CLK_P>,
                                  <&cpg_clocks R8A7779_CLK_P>,
                                  <&cpg_clocks R8A7779_CLK_S>,
@@ -441,7 +477,7 @@
                 };
                 mstp1_clks: clocks@ffc80034 {
                         compatible = "renesas,r8a7779-mstp-clocks",
-                                     "renesas,cpg-mstp-clocks";
+                                     "renesas,cpg-mstp-clocks";
                         reg = <0xffc80034 4>, <0xffc80044 4>;
                         clocks = <&cpg_clocks R8A7779_CLK_P>,
                                  <&cpg_clocks R8A7779_CLK_P>,
@@ -470,7 +506,7 @@
                 };
                 mstp3_clks: clocks@ffc8003c {
                         compatible = "renesas,r8a7779-mstp-clocks",
-                                     "renesas,cpg-mstp-clocks";
+                                     "renesas,cpg-mstp-clocks";
                         reg = <0xffc8003c 4>;
                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
                                  <&s4_clk>, <&s4_clk>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 856b4236b674..69098b906b39 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -32,7 +32,7 @@
                 reg = <0 0x40000000 0 0x40000000>;
         };
 
-        memory@180000000 {
+        memory@140000000 {
                 device_type = "memory";
                 reg = <1 0x40000000 0 0xc0000000>;
         };
@@ -234,6 +234,11 @@
                 renesas,groups = "usb2";
                 renesas,function = "usb2";
         };
+
+        vin1_pins: vin {
+                renesas,groups = "vin1_data8", "vin1_clk";
+                renesas,function = "vin1";
+        };
 };
 
 &ether {
@@ -252,6 +257,10 @@
         };
 };
 
+&cmt0 {
+        status = "ok";
+};
+
 &mmcif1 {
         pinctrl-0 = <&mmc1_pins>;
         pinctrl-names = "default";
@@ -366,6 +375,19 @@
         status = "ok";
         pinctrl-0 = <&iic2_pins>;
         pinctrl-names = "default";
+
+        composite-in@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+                remote = <&vin1>;
+
+                port {
+                        adv7180: endpoint {
+                                bus-width = <8>;
+                                remote-endpoint = <&vin1ep0>;
+                        };
+                };
+        };
 };
 
 &iic3 {
@@ -374,7 +396,7 @@
         status = "okay";
 
         vdd_dvfs: regulator@68 {
-                compatible = "diasemi,da9210";
+                compatible = "dlg,da9210";
                 reg = <0x68>;
 
                 regulator-min-microvolt = <1000000>;
@@ -401,3 +423,21 @@
         pinctrl-0 = <&usb2_pins>;
         pinctrl-names = "default";
 };
+
+/* composite video input */
+&vin1 {
+        pinctrl-0 = <&vin1_pins>;
+        pinctrl-names = "default";
+
+        status = "ok";
+
+        port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vin1ep0: endpoint {
+                        remote-endpoint = <&adv7180>;
+                        bus-width = <8>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d9ddecbb859c..d0e17733dc1a 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -33,6 +33,10 @@
                 spi2 = &msiof1;
                 spi3 = &msiof2;
                 spi4 = &msiof3;
+                vin0 = &vin0;
+                vin1 = &vin1;
+                vin2 = &vin2;
+                vin3 = &vin3;
         };
 
         cpus {
@@ -206,6 +210,38 @@
                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
+        cmt0: timer@ffca0000 {
+                compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+                reg = <0 0xffca0000 0 0x1004>;
+                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
+                clock-names = "fck";
+
+                renesas,channels-mask = <0x60>;
+
+                status = "disabled";
+        };
+
+        cmt1: timer@e6130000 {
+                compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+                reg = <0 0xe6130000 0 0x1004>;
+                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 122 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 123 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 124 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 125 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 126 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
+                clock-names = "fck";
+
+                renesas,channels-mask = <0xff>;
+
+                status = "disabled";
+        };
+
         irqc0: interrupt-controller@e61c0000 {
                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
                 #interrupt-cells = <2>;
@@ -217,6 +253,65 @@
                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
         };
 
+        dmac0: dma-controller@e6700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6700000 0 0x20000>;
+                interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
+                              0 200 IRQ_TYPE_LEVEL_HIGH
+                              0 201 IRQ_TYPE_LEVEL_HIGH
+                              0 202 IRQ_TYPE_LEVEL_HIGH
+                              0 203 IRQ_TYPE_LEVEL_HIGH
+                              0 204 IRQ_TYPE_LEVEL_HIGH
+                              0 205 IRQ_TYPE_LEVEL_HIGH
+                              0 206 IRQ_TYPE_LEVEL_HIGH
+                              0 207 IRQ_TYPE_LEVEL_HIGH
+                              0 208 IRQ_TYPE_LEVEL_HIGH
+                              0 209 IRQ_TYPE_LEVEL_HIGH
+                              0 210 IRQ_TYPE_LEVEL_HIGH
+                              0 211 IRQ_TYPE_LEVEL_HIGH
+                              0 212 IRQ_TYPE_LEVEL_HIGH
+                              0 213 IRQ_TYPE_LEVEL_HIGH
+                              0 214 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
+
+        dmac1: dma-controller@e6720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6720000 0 0x20000>;
+                interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                              0 216 IRQ_TYPE_LEVEL_HIGH
+                              0 217 IRQ_TYPE_LEVEL_HIGH
+                              0 218 IRQ_TYPE_LEVEL_HIGH
+                              0 219 IRQ_TYPE_LEVEL_HIGH
+                              0 308 IRQ_TYPE_LEVEL_HIGH
+                              0 309 IRQ_TYPE_LEVEL_HIGH
+                              0 310 IRQ_TYPE_LEVEL_HIGH
+                              0 311 IRQ_TYPE_LEVEL_HIGH
+                              0 312 IRQ_TYPE_LEVEL_HIGH
+                              0 313 IRQ_TYPE_LEVEL_HIGH
+                              0 314 IRQ_TYPE_LEVEL_HIGH
+                              0 315 IRQ_TYPE_LEVEL_HIGH
+                              0 316 IRQ_TYPE_LEVEL_HIGH
+                              0 317 IRQ_TYPE_LEVEL_HIGH
+                              0 318 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
         i2c0: i2c@e6508000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -473,6 +568,38 @@
                 status = "disabled";
         };
 
+        vin0: video@e6ef0000 {
+                compatible = "renesas,vin-r8a7790";
+                clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
+                reg = <0 0xe6ef0000 0 0x1000>;
+                interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        vin1: video@e6ef1000 {
+                compatible = "renesas,vin-r8a7790";
+                clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
+                reg = <0 0xe6ef1000 0 0x1000>;
+                interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        vin2: video@e6ef2000 {
+                compatible = "renesas,vin-r8a7790";
+                clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
+                reg = <0 0xe6ef2000 0 0x1000>;
+                interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        vin3: video@e6ef3000 {
+                compatible = "renesas,vin-r8a7790";
+                clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
+                reg = <0 0xe6ef3000 0 0x1000>;
+                interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
         clocks {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -741,33 +868,36 @@
                 mstp1_clks: mstp1_clks@e6150134 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                        clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
                                  <&zs_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
-                                R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                                R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
                         >;
                         clock-output-names =
-                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
                 };
                 mstp2_clks: mstp2_clks@e6150138 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
-                                 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                                 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
+                                 <&zs_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+                                R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
                         >;
                         clock-output-names =
                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
-                                "scifb1", "msiof1", "msiof3", "scifb2";
+                                "scifb1", "msiof1", "msiof3", "scifb2",
+                                "sys-dmac1", "sys-dmac0";
                 };
                 mstp3_clks: mstp3_clks@e615013c {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -884,6 +1014,8 @@
                 reg = <0 0xe6b10000 0 0x2c>;
                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
+                dmas = <&dmac0 0x17>, <&dmac0 0x18>;
+                dma-names = "tx", "rx";
                 num-cs = <1>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -892,9 +1024,11 @@
 
         msiof0: spi@e6e20000 {
                 compatible = "renesas,msiof-r8a7790";
-                reg = <0 0xe6e20000 0 0x0064>;
+                reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
+                dmas = <&dmac0 0x51>, <&dmac0 0x52>;
+                dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
@@ -902,9 +1036,11 @@
 
         msiof1: spi@e6e10000 {
                 compatible = "renesas,msiof-r8a7790";
-                reg = <0 0xe6e10000 0 0x0064>;
+                reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
+                dmas = <&dmac0 0x55>, <&dmac0 0x56>;
+                dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
@@ -912,9 +1048,11 @@
 
         msiof2: spi@e6e00000 {
                 compatible = "renesas,msiof-r8a7790";
-                reg = <0 0xe6e00000 0 0x0064>;
+                reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
+                dmas = <&dmac0 0x41>, <&dmac0 0x42>;
+                dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
@@ -922,9 +1060,11 @@
 
         msiof3: spi@e6c90000 {
                 compatible = "renesas,msiof-r8a7790";
-                reg = <0 0xe6c90000 0 0x0064>;
+                reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
+                dmas = <&dmac0 0x45>, <&dmac0 0x46>;
+                dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
@@ -1018,7 +1158,6 @@
         rcar_sound: rcar_sound@0xec500000 {
                 #sound-dai-cells = <1>;
                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
-                interrupt-parent = <&gic>;
                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
                         <0 0xec5a0000 0 0x100>,  /* ADG */
                         <0 0xec540000 0 0x1000>, /* SSIU */
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index 3a2ef0a2a137..f1b56de10205 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -135,6 +135,11 @@
                 renesas,groups = "usb1";
                 renesas,function = "usb1";
         };
+
+        vin0_pins: vin0 {
+                renesas,groups = "vin0_data8", "vin0_clk";
+                renesas,function = "vin0";
+        };
 };
 
 &scif0 {
@@ -191,6 +196,19 @@
 
         status = "okay";
         clock-frequency = <400000>;
+
+        composite-in@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+                remote = <&vin0>;
+
+                port {
+                        adv7180: endpoint {
+                                bus-width = <8>;
+                                remote-endpoint = <&vin0ep>;
+                        };
+                };
+        };
 };
 
 &qspi {
@@ -260,3 +278,20 @@
 &pciec {
         status = "okay";
 };
+
+/* composite video input */
+&vin0 {
+        status = "ok";
+        pinctrl-0 = <&vin0_pins>;
+        pinctrl-names = "default";
+
+        port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vin0ep: endpoint {
+                        remote-endpoint = <&adv7180>;
+                        bus-width = <8>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 23486c081a69..07550e775e80 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -275,11 +275,6 @@
                 renesas,function = "msiof0";
         };
 
-        i2c6_pins: i2c6 {
-                renesas,groups = "i2c6";
-                renesas,function = "i2c6";
-        };
-
         usb0_pins: usb0 {
                 renesas,groups = "usb0";
                 renesas,function = "usb0";
@@ -289,6 +284,11 @@
                 renesas,groups = "usb1";
                 renesas,function = "usb1";
         };
+
+        vin1_pins: vin1 {
+                renesas,groups = "vin1_data8", "vin1_clk";
+                renesas,function = "vin1";
+        };
 };
 
 &ether {
@@ -307,6 +307,10 @@
         };
 };
 
+&cmt0 {
+        status = "ok";
+};
+
 &sata0 {
         status = "okay";
 };
@@ -412,6 +416,19 @@
         status = "okay";
         clock-frequency = <400000>;
 
+        composite-in@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+                remote = <&vin1>;
+
+                port {
+                        adv7180: endpoint {
+                                bus-width = <8>;
+                                remote-endpoint = <&vin1ep>;
+                        };
+                };
+        };
+
         eeprom@50 {
                 compatible = "renesas,24c02";
                 reg = <0x50>;
@@ -420,13 +437,11 @@
 };
 
 &i2c6 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c6_pins>;
         status = "okay";
         clock-frequency = <100000>;
 
         vdd_dvfs: regulator@68 {
-                compatible = "diasemi,da9210";
+                compatible = "dlg,da9210";
                 reg = <0x68>;
 
                 regulator-min-microvolt = <1000000>;
@@ -459,3 +474,20 @@
 &cpu0 {
         cpu0-supply = <&vdd_dvfs>;
 };
+
+/* composite video input */
+&vin1 {
+        status = "ok";
+        pinctrl-0 = <&vin1_pins>;
+        pinctrl-names = "default";
+
+        port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vin1ep: endpoint {
+                        remote-endpoint = <&adv7180>;
+                        bus-width = <8>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 0d82a4b3c650..e06c11fa8698 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -34,6 +34,9 @@
                 spi1 = &msiof0;
                 spi2 = &msiof1;
                 spi3 = &msiof2;
+                vin0 = &vin0;
+                vin1 = &vin1;
+                vin2 = &vin2;
         };
 
         cpus {
@@ -189,6 +192,38 @@
                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
+        cmt0: timer@ffca0000 {
+                compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+                reg = <0 0xffca0000 0 0x1004>;
+                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
+                clock-names = "fck";
+
+                renesas,channels-mask = <0x60>;
+
+                status = "disabled";
+        };
+
+        cmt1: timer@e6130000 {
+                compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+                reg = <0 0xe6130000 0 0x1004>;
+                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 122 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 123 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 124 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 125 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 126 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
+                clock-names = "fck";
+
+                renesas,channels-mask = <0xff>;
+
+                status = "disabled";
+        };
+
         irqc0: interrupt-controller@e61c0000 {
                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
                 #interrupt-cells = <2>;
@@ -206,6 +241,66 @@
                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
         };
 
+        dmac0: dma-controller@e6700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6700000 0 0x20000>;
+                interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
+                              0 200 IRQ_TYPE_LEVEL_HIGH
+                              0 201 IRQ_TYPE_LEVEL_HIGH
+                              0 202 IRQ_TYPE_LEVEL_HIGH
+                              0 203 IRQ_TYPE_LEVEL_HIGH
+                              0 204 IRQ_TYPE_LEVEL_HIGH
+                              0 205 IRQ_TYPE_LEVEL_HIGH
+                              0 206 IRQ_TYPE_LEVEL_HIGH
+                              0 207 IRQ_TYPE_LEVEL_HIGH
+                              0 208 IRQ_TYPE_LEVEL_HIGH
+                              0 209 IRQ_TYPE_LEVEL_HIGH
+                              0 210 IRQ_TYPE_LEVEL_HIGH
+                              0 211 IRQ_TYPE_LEVEL_HIGH
+                              0 212 IRQ_TYPE_LEVEL_HIGH
+                              0 213 IRQ_TYPE_LEVEL_HIGH
+                              0 214 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
+
+        dmac1: dma-controller@e6720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6720000 0 0x20000>;
+                interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                              0 216 IRQ_TYPE_LEVEL_HIGH
+                              0 217 IRQ_TYPE_LEVEL_HIGH
+                              0 218 IRQ_TYPE_LEVEL_HIGH
+                              0 219 IRQ_TYPE_LEVEL_HIGH
+                              0 308 IRQ_TYPE_LEVEL_HIGH
+                              0 309 IRQ_TYPE_LEVEL_HIGH
+                              0 310 IRQ_TYPE_LEVEL_HIGH
+                              0 311 IRQ_TYPE_LEVEL_HIGH
+                              0 312 IRQ_TYPE_LEVEL_HIGH
+                              0 313 IRQ_TYPE_LEVEL_HIGH
+                              0 314 IRQ_TYPE_LEVEL_HIGH
+                              0 315 IRQ_TYPE_LEVEL_HIGH
+                              0 316 IRQ_TYPE_LEVEL_HIGH
+                              0 317 IRQ_TYPE_LEVEL_HIGH
+                              0 318 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
+
         /* The memory map in the User's Manual maps the cores to bus numbers */
         i2c0: i2c@e6508000 {
                 #address-cells = <1>;
@@ -518,6 +613,30 @@
                 status = "disabled";
         };
 
+        vin0: video@e6ef0000 {
+                compatible = "renesas,vin-r8a7791";
+                clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
+                reg = <0 0xe6ef0000 0 0x1000>;
+                interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        vin1: video@e6ef1000 {
+                compatible = "renesas,vin-r8a7791";
+                clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
+                reg = <0 0xe6ef1000 0 0x1000>;
+                interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        vin2: video@e6ef2000 {
+                compatible = "renesas,vin-r8a7791";
+                clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
+                reg = <0 0xe6ef2000 0 0x1000>;
+                interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
         clocks {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -770,16 +889,16 @@
                 mstp1_clks: mstp1_clks@e6150134 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                        clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
-                                R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
+                                R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
                         >;
                         clock-output-names =
-                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
                                 "vsp1-du0", "vsp1-sy";
                 };
                 mstp2_clks: mstp2_clks@e6150138 {
@@ -925,6 +1044,8 @@
                 reg = <0 0xe6b10000 0 0x2c>;
                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
+                dmas = <&dmac0 0x17>, <&dmac0 0x18>;
+                dma-names = "tx", "rx";
                 num-cs = <1>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -933,9 +1054,11 @@
 
         msiof0: spi@e6e20000 {
                 compatible = "renesas,msiof-r8a7791";
-                reg = <0 0xe6e20000 0 0x0064>;
+                reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
+                dmas = <&dmac0 0x51>, <&dmac0 0x52>;
+                dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
@@ -943,9 +1066,11 @@
 
         msiof1: spi@e6e10000 {
                 compatible = "renesas,msiof-r8a7791";
-                reg = <0 0xe6e10000 0 0x0064>;
+                reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
+                dmas = <&dmac0 0x55>, <&dmac0 0x56>;
+                dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
@@ -953,9 +1078,11 @@
 
         msiof2: spi@e6e00000 {
                 compatible = "renesas,msiof-r8a7791";
-                reg = <0 0xe6e00000 0 0x0064>;
+                reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
+                dmas = <&dmac0 0x41>, <&dmac0 0x42>;
+                dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
@@ -1029,7 +1156,6 @@
         rcar_sound: rcar_sound@0xec500000 {
                 #sound-dai-cells = <1>;
                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
-                interrupt-parent = <&gic>;
                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
                         <0 0xec5a0000 0 0x100>,  /* ADG */
                         <0 0xec540000 0 0x1000>, /* SSIU */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
new file mode 100644
index 000000000000..79d06ef017a0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -0,0 +1,47 @@
+/*
+ * Device Tree Source for the Alt board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+
+/ {
+        model = "Alt";
+        compatible = "renesas,alt", "renesas,r8a7794";
+
+        aliases {
+                serial0 = &scif2;
+        };
+
+        chosen {
+                bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+        };
+
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0 0x40000000 0 0x40000000>;
+        };
+
+        lbsc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+
+&cmt0 {
+        status = "ok";
+};
+
+&scif2 {
+        status = "ok";
+};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
new file mode 100644
index 000000000000..d4e8bce1e0b7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -0,0 +1,531 @@
+/*
+ * Device Tree Source for the r8a7794 SoC
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014 Ulrich Hecht
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a7794-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        compatible = "renesas,r8a7794";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <1>;
+                        clock-frequency = <1000000000>;
+                };
+        };
+
+        gic: interrupt-controller@f1001000 {
+                compatible = "arm,cortex-a7-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0xf1001000 0 0x1000>,
+                        <0 0xf1002000 0 0x1000>,
+                        <0 0xf1004000 0 0x2000>,
+                        <0 0xf1006000 0 0x2000>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
+        cmt0: timer@ffca0000 {
+                compatible = "renesas,cmt-48-gen2";
+                reg = <0 0xffca0000 0 0x1004>;
+                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
+                clock-names = "fck";
+
+                renesas,channels-mask = <0x60>;
+
+                status = "disabled";
+        };
+
+        cmt1: timer@e6130000 {
+                compatible = "renesas,cmt-48-gen2";
+                reg = <0 0xe6130000 0 0x1004>;
+                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 122 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 123 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 124 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 125 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 126 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
+                clock-names = "fck";
+
+                renesas,channels-mask = <0xff>;
+
+                status = "disabled";
+        };
+
+        irqc0: interrupt-controller@e61c0000 {
+                compatible = "renesas,irqc-r8a7794", "renesas,irqc";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0 0xe61c0000 0 0x200>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 14 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 15 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 16 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 17 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        scifa0: serial@e6c40000 {
+                compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+                reg = <0 0xe6c40000 0 64>;
+                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifa1: serial@e6c50000 {
+                compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+                reg = <0 0xe6c50000 0 64>;
+                interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifa2: serial@e6c60000 {
+                compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+                reg = <0 0xe6c60000 0 64>;
+                interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifa3: serial@e6c70000 {
+                compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+                reg = <0 0xe6c70000 0 64>;
+                interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifa4: serial@e6c78000 {
+                compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+                reg = <0 0xe6c78000 0 64>;
+                interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifa5: serial@e6c80000 {
+                compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+                reg = <0 0xe6c80000 0 64>;
+                interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifb0: serial@e6c20000 {
+                compatible = "renesas,scifb-r8a7794", "renesas,scifb";
+                reg = <0 0xe6c20000 0 64>;
+                interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifb1: serial@e6c30000 {
+                compatible = "renesas,scifb-r8a7794", "renesas,scifb";
+                reg = <0 0xe6c30000 0 64>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scifb2: serial@e6ce0000 {
+                compatible = "renesas,scifb-r8a7794", "renesas,scifb";
+                reg = <0 0xe6ce0000 0 64>;
+                interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif0: serial@e6e60000 {
+                compatible = "renesas,scif-r8a7794", "renesas,scif";
+                reg = <0 0xe6e60000 0 64>;
+                interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif1: serial@e6e68000 {
+                compatible = "renesas,scif-r8a7794", "renesas,scif";
+                reg = <0 0xe6e68000 0 64>;
+                interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif2: serial@e6e58000 {
+                compatible = "renesas,scif-r8a7794", "renesas,scif";
+                reg = <0 0xe6e58000 0 64>;
+                interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif3: serial@e6ea8000 {
+                compatible = "renesas,scif-r8a7794", "renesas,scif";
+                reg = <0 0xe6ea8000 0 64>;
+                interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif4: serial@e6ee0000 {
+                compatible = "renesas,scif-r8a7794", "renesas,scif";
+                reg = <0 0xe6ee0000 0 64>;
+                interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif5: serial@e6ee8000 {
+                compatible = "renesas,scif-r8a7794", "renesas,scif";
+                reg = <0 0xe6ee8000 0 64>;
+                interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        hscif0: serial@e62c0000 {
+                compatible = "renesas,hscif-r8a7794", "renesas,hscif";
+                reg = <0 0xe62c0000 0 96>;
+                interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        hscif1: serial@e62c8000 {
+                compatible = "renesas,hscif-r8a7794", "renesas,hscif";
+                reg = <0 0xe62c8000 0 96>;
+                interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        hscif2: serial@e62d0000 {
+                compatible = "renesas,hscif-r8a7794", "renesas,hscif";
+                reg = <0 0xe62d0000 0 96>;
+                interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7794-cpg-clocks",
+                                     "renesas,rcar-gen2-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll3",
+                                             "lb", "qspi", "sdh", "sd0", "z";
+                };
+
+                /* Fixed factor clocks */
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                zg_clk: zg_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                        clock-output-names = "zg";
+                };
+                zx_clk: zx_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zx";
+                };
+                zs_clk: zs_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                        clock-output-names = "zs";
+                };
+                hp_clk: hp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "hp";
+                };
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                b_clk: b_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "b";
+                };
+                p_clk: p_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "p";
+                };
+                cl_clk: cl_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                        clock-output-names = "cl";
+                };
+                m2_clk: m2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "m2";
+                };
+                imp_clk: imp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "imp";
+                };
+                rclk_clk: rclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(48 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "rclk";
+                };
+                oscclk_clk: oscclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(12 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "oscclk";
+                };
+                zb3_clk: zb3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3";
+                };
+                zb3d2_clk: zb3d2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3d2";
+                };
+                ddr_clk: ddr_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "ddr";
+                };
+                mp_clk: mp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <15>;
+                        clock-mult = <1>;
+                        clock-output-names = "mp";
+                };
+                cp_clk: cp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                        clock-output-names = "cp";
+                };
+
+                acp_clk: acp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "acp";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@e6150130 {
+                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                        clocks = <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
+                        clock-output-names = "msiof0";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>,
+                                 <&zs_clk>, <&zs_clk>, <&zs_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
+                                R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
+                        >;
+                        clock-output-names =
+                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+                                 <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
+                                R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
+                                R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
+                        >;
+                        clock-output-names =
+                                "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+                                "scifb1", "msiof1", "scifb2";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                        clocks = <&rclk_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7794_CLK_CMT1
+                        >;
+                        clock-output-names =
+                                "cmt1";
+                };
+                mstp7_clks: mstp7_clks@e615014c {
+                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                        clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
+                                R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
+                                R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
+                                R8A7794_CLK_SCIF0
+                        >;
+                        clock-output-names =
+                                "hscif2", "scif5", "scif4", "hscif1", "hscif0",
+                                "scif3", "scif2", "scif1", "scif0";
+                };
+                mstp8_clks: mstp8_clks@e6150990 {
+                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+                        clocks = <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7794_CLK_ETHER
+                        >;
+                        clock-output-names =
+                                "ether";
+                };
+                mstp11_clks: mstp11_clks@e615099c {
+                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
+                        >;
+                        clock-output-names = "scifa3", "scifa4", "scifa5";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 042f821d9e4d..d5344510c676 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -149,13 +149,11 @@
 &mmc0 { /* sdmmc */
         num-slots = <1>;
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
         vmmc-supply = <&vcc_sd0>;
-
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-                disable-wp;
-        };
+        bus-width = <4>;
+        disable-wp;
 };
 
 &mmc1 { /* wifi */
@@ -166,11 +164,8 @@
         pinctrl-names = "default";
         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
 
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-                disable-wp;
-        };
+        bus-width = <4>;
+        disable-wp;
 };
 
 &uart0 {
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 879a818fba51..ad9c2db59670 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -179,6 +179,27 @@
                         bias-disable;
                 };
 
+                emmc {
+                        emmc_clk: emmc-clk {
+                                rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+
+                        emmc_cmd: emmc-cmd {
+                                rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+
+                        emmc_rst: emmc-rst {
+                                rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+
+                        /*
+                         * The data pins are shared between nandc and emmc and
+                         * not accessible through pinctrl. Also they should've
+                         * been already set correctly by firmware, as
+                         * flash/emmc is the boot-device.
+                         */
+                };
+
                 i2c0 {
                         i2c0_xfer: i2c0-xfer {
                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
@@ -238,6 +259,42 @@
                         };
                 };
 
+                spi0 {
+                        spi0_clk: spi0-clk {
+                                rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi0_cs0: spi0-cs0 {
+                                rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi0_tx: spi0-tx {
+                                rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi0_rx: spi0-rx {
+                                rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi0_cs1: spi0-cs1 {
+                                rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
+                        };
+                };
+
+                spi1 {
+                        spi1_clk: spi1-clk {
+                                rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi1_cs0: spi1-cs0 {
+                                rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi1_rx: spi1-rx {
+                                rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi1_tx: spi1-tx {
+                                rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                        spi1_cs1: spi1-cs1 {
+                                rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
+                        };
+                };
+
                 uart0 {
                         uart0_xfer: uart0-xfer {
                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
@@ -406,6 +463,16 @@
         pinctrl-0 = <&pwm3_out>;
 };
 
+&spi0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+};
+
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_xfer>;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 171b610db709..15910c9ddbc7 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -65,6 +65,19 @@
                 pinctrl-0 = <&ir_recv_pin>;
         };
 
+        vcc_otg: usb-otg-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&otg_vbus_drv>;
+                regulator-name = "otg-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
         vcc_sd0: sdmmc-regulator {
                 compatible = "regulator-fixed";
                 regulator-name = "sdmmc-supply";
@@ -74,12 +87,52 @@
                 startup-delay-us = <100000>;
                 vin-supply = <&vcc_io>;
         };
+
+        vcc_host: usb-host-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&host_vbus_drv>;
+                regulator-name = "host-pwr";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+
+&emac {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+
+        phy = <&phy0>;
+        phy-supply = <&vcc_rmii>;
+
+        phy0: ethernet-phy@0 {
+                reg = <0>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+        };
 };
 
 &i2c1 {
         status = "okay";
         clock-frequency = <400000>;
 
+        rtc@51 {
+                compatible = "haoyu,hym8563";
+                reg = <0x51>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&rtc_int>;
+                #clock-cells = <0>;
+                clock-output-names = "xin32k";
+        };
+
         act8846: act8846@5a {
                 compatible = "active-semi,act8846";
                 reg = <0x5a>;
@@ -149,7 +202,6 @@
                                 regulator-name = "VCC_RMII";
                                 regulator-min-microvolt = <3300000>;
                                 regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
                         };
 
                         vccio_wl: REG10 {
@@ -179,13 +231,12 @@
 &mmc0 {
         num-slots = <1>;
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
         vmmc-supply = <&vcc_sd0>;
 
-        slot@0 {
-                reg = <0>;
-                bus-width = <4>;
-                disable-wp;
-        };
+        bus-width = <4>;
+        disable-wp;
 };
 
 &pinctrl {
@@ -199,11 +250,32 @@
                 };
         };
 
+        hym8563 {
+                rtc_int: rtc-int {
+                        rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        lan8720a  {
+                phy_int: phy-int {
+                        rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
         ir-receiver {
                 ir_recv_pin: ir-recv-pin {
                         rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
                 };
         };
+
+        usb {
+                host_vbus_drv: host-vbus-drv {
+                        rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+                otg_vbus_drv: otg-vbus-drv {
+                        rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
 };
 
 &uart0 {
@@ -222,6 +294,14 @@
         status = "okay";
 };
 
+&usb_host {
+        status = "okay";
+};
+
+&usb_otg {
+        status = "okay";
+};
+
 &wdt {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ee801a9c6b74..ddaada788b45 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -147,6 +147,45 @@
                         bias-disable;
                 };
 
+                emmc {
+                        emmc_clk: emmc-clk {
+                                rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
+                        };
+
+                        emmc_cmd: emmc-cmd {
+                                rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+
+                        emmc_rst: emmc-rst {
+                                rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
+                        };
+
+                        /*
+                         * The data pins are shared between nandc and emmc and
+                         * not accessible through pinctrl. Also they should've
+                         * been already set correctly by firmware, as
+                         * flash/emmc is the boot-device.
+                         */
+                };
+
+                emac {
+                        emac_xfer: emac-xfer {
+                                rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
+                                                <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
+                                                <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
+                                                <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
+                                                <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
+                                                <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
+                                                <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
+                                                <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
+                        };
+
+                        emac_mdio: emac-mdio {
+                                rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
+                                                <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
+                        };
+                };
+
                 i2c0 {
                         i2c0_xfer: i2c0-xfer {
                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
@@ -206,6 +245,42 @@
                         };
                 };
 
+                spi0 {
+                        spi0_clk: spi0-clk {
+                                rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                        spi0_cs0: spi0-cs0 {
+                                rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                        spi0_tx: spi0-tx {
+                                rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                        spi0_rx: spi0-rx {
+                                rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                        spi0_cs1: spi0-cs1 {
+                                rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                };
+
+                spi1 {
+                        spi1_clk: spi1-clk {
+                                rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi1_cs0: spi1-cs0 {
+                                rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi1_rx: spi1-rx {
+                                rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi1_tx: spi1-tx {
+                                rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi1_cs1: spi1-cs1 {
+                                rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                };
+
                 uart0 {
                         uart0_xfer: uart0-xfer {
                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
@@ -323,6 +398,10 @@
         };
 };
 
+&emac {
+        compatible = "rockchip,rk3188-emac";
+};
+
 &global_timer {
         interrupts = <GIC_PPI 11 0xf04>;
 };
@@ -381,6 +460,18 @@
         pinctrl-0 = <&pwm3_out>;
 };
 
+&spi0 {
+        compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+};
+
+&spi1 {
+        compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_xfer>;
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 7d59ff4de408..a76dd44adb53 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -26,7 +26,7 @@
                 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
 
                 pinctrl-names = "default";
-                pinctrl-0 = <&hym8563_int>;
+                pinctrl-0 = <&pmic_int>;
 
                 #clock-cells = <0>;
                 clock-output-names = "xin32k";
@@ -124,11 +124,3 @@
                 };
         };
 };
-
-&pinctrl {
-        hym8563 {
-                hym8563_int: hym8563-int {
-                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index 9a88b6c66396..ff522f8e3df4 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -16,3 +16,135 @@
 / {
         compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
 };
+
+&i2c0 {
+        clock-frequency = <400000>;
+        status = "okay";
+
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int>;
+                rockchip,system-power-controller;
+                wakeup-source;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+
+                vcc8-supply = <&vcc_18>;
+                vcc9-supply = <&vcc_io>;
+                vcc10-supply = <&vcc_io>;
+                vcc12-supply = <&vcc_io>;
+                vddio-supply = <&vccio_pmu>;
+
+                regulators {
+                        vdd_cpu: DCDC_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-name = "vdd_arm";
+                        };
+
+                        vdd_gpu: DCDC_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-name = "vdd_gpu";
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_ddr";
+                        };
+
+                        vcc_io: DCDC_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_io";
+                        };
+
+                        vccio_pmu: LDO_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_pmu";
+                        };
+
+                        vcc_tp: LDO_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_tp";
+                        };
+
+                        vdd_10: LDO_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd_10";
+                        };
+
+                        vcc18_lcd: LDO_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_lcd";
+                        };
+
+                        vccio_sd: LDO_REG5 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_sd";
+                        };
+
+                        vdd10_lcd: LDO_REG6 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd10_lcd";
+                        };
+
+                        vcc_18: LDO_REG7 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc_18";
+                        };
+
+                        vcca_codec: LDO_REG8 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcca_codec";
+                        };
+
+                        vcc_wl: SWITCH_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_wl";
+                        };
+
+                        vcc_lcd: SWITCH_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_lcd";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 4f572093c8b4..cb83cea52fa1 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -10,6 +10,7 @@
  * GNU General Public License for more details.
  */
 
+#include <dt-bindings/pwm/pwm.h>
 #include "rk3288.dtsi"
 
 / {
@@ -17,6 +18,48 @@
                 reg = <0x0 0x80000000>;
         };
 
+        backlight {
+                compatible = "pwm-backlight";
+                brightness-levels = <
+                          0   1   2   3   4   5   6   7
+                          8   9  10  11  12  13  14  15
+                         16  17  18  19  20  21  22  23
+                         24  25  26  27  28  29  30  31
+                         32  33  34  35  36  37  38  39
+                         40  41  42  43  44  45  46  47
+                         48  49  50  51  52  53  54  55
+                         56  57  58  59  60  61  62  63
+                         64  65  66  67  68  69  70  71
+                         72  73  74  75  76  77  78  79
+                         80  81  82  83  84  85  86  87
+                         88  89  90  91  92  93  94  95
+                         96  97  98  99 100 101 102 103
+                        104 105 106 107 108 109 110 111
+                        112 113 114 115 116 117 118 119
+                        120 121 122 123 124 125 126 127
+                        128 129 130 131 132 133 134 135
+                        136 137 138 139 140 141 142 143
+                        144 145 146 147 148 149 150 151
+                        152 153 154 155 156 157 158 159
+                        160 161 162 163 164 165 166 167
+                        168 169 170 171 172 173 174 175
+                        176 177 178 179 180 181 182 183
+                        184 185 186 187 188 189 190 191
+                        192 193 194 195 196 197 198 199
+                        200 201 202 203 204 205 206 207
+                        208 209 210 211 212 213 214 215
+                        216 217 218 219 220 221 222 223
+                        224 225 226 227 228 229 230 231
+                        232 233 234 235 236 237 238 239
+                        240 241 242 243 244 245 246 247
+                        248 249 250 251 252 253 254 255>;
+                default-brightness-level = <128>;
+                enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&bl_en>;
+                pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
@@ -49,6 +92,30 @@
         };
 };
 
+&emmc {
+        broken-cd;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        disable-wp;
+        non-removable;
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+        status = "okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        card-detect-delay = <200>;
+        disable-wp;                     /* wp not hooked up */
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        status = "okay";
+};
+
 &i2c0 {
         status = "okay";
 };
@@ -57,6 +124,10 @@
         status = "okay";
 };
 
+&pwm0 {
+        status = "okay";
+};
+
 &uart0 {
         status = "okay";
 };
@@ -78,12 +149,24 @@
 };
 
 &pinctrl {
+        backlight {
+                bl_en: bl-en {
+                        rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
         buttons {
                 pwrbtn: pwrbtn {
                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
                 };
         };
 
+        pmic {
+                pmic_int: pmic-int {
+                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
         usb {
                 host_vbus_drv: host-vbus-drv {
                         rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -94,3 +177,7 @@
 &usb_host0_ehci {
         status = "okay";
 };
+
+&usb_host1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a53224..874e66dbb93b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -29,11 +29,18 @@
                 i2c3 = &i2c3;
                 i2c4 = &i2c4;
                 i2c5 = &i2c5;
+                mshc0 = &emmc;
+                mshc1 = &sdmmc;
+                mshc2 = &sdio0;
+                mshc3 = &sdio1;
                 serial0 = &uart0;
                 serial1 = &uart1;
                 serial2 = &uart2;
                 serial3 = &uart3;
                 serial4 = &uart4;
+                spi0 = &spi0;
+                spi1 = &spi1;
+                spi2 = &spi2;
         };
 
         cpus {
@@ -62,6 +69,44 @@
                 };
         };
 
+        amba {
+                compatible = "arm,amba-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                dmac_peri: dma-controller@ff250000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0xff250000 0x4000>;
+                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <1>;
+                        clocks = <&cru ACLK_DMAC2>;
+                        clock-names = "apb_pclk";
+                };
+
+                dmac_bus_ns: dma-controller@ff600000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0xff600000 0x4000>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <1>;
+                        clocks = <&cru ACLK_DMAC1>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                dmac_bus_s: dma-controller@ffb20000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0xffb20000 0x4000>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <1>;
+                        clocks = <&cru ACLK_DMAC1>;
+                        clock-names = "apb_pclk";
+                };
+        };
+
         xin24m: oscillator {
                 compatible = "fixed-clock";
                 clock-frequency = <24000000>;
@@ -78,6 +123,95 @@
                 clock-frequency = <24000000>;
         };
 
+        sdmmc: dwmmc@ff0c0000 {
+                compatible = "rockchip,rk3288-dw-mshc";
+                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x100>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                reg = <0xff0c0000 0x4000>;
+                status = "disabled";
+        };
+
+        sdio0: dwmmc@ff0d0000 {
+                compatible = "rockchip,rk3288-dw-mshc";
+                clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x100>;
+                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                reg = <0xff0d0000 0x4000>;
+                status = "disabled";
+        };
+
+        sdio1: dwmmc@ff0e0000 {
+                compatible = "rockchip,rk3288-dw-mshc";
+                clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x100>;
+                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                reg = <0xff0e0000 0x4000>;
+                status = "disabled";
+        };
+
+        emmc: dwmmc@ff0f0000 {
+                compatible = "rockchip,rk3288-dw-mshc";
+                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x100>;
+                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                reg = <0xff0f0000 0x4000>;
+                status = "disabled";
+        };
+
+        saradc: saradc@ff100000 {
+                compatible = "rockchip,saradc";
+                reg = <0xff100000 0x100>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                #io-channel-cells = <1>;
+                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+                clock-names = "saradc", "apb_pclk";
+                status = "disabled";
+        };
+
+        spi0: spi@ff110000 {
+                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
+                clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+                clock-names = "spiclk", "apb_pclk";
+                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+                reg = <0xff110000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi1: spi@ff120000 {
+                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
+                clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+                clock-names = "spiclk", "apb_pclk";
+                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+                reg = <0xff120000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi2: spi@ff130000 {
+                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
+                clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
+                clock-names = "spiclk", "apb_pclk";
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+                reg = <0xff130000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
         i2c1: i2c@ff140000 {
                 compatible = "rockchip,rk3288-i2c";
                 reg = <0xff140000 0x1000>;
@@ -206,6 +340,26 @@
 
         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 
+        usb_host1: usb@ff540000 {
+                compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+                                "snps,dwc2";
+                reg = <0xff540000 0x40000>;
+                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_USBHOST1>;
+                clock-names = "otg";
+                status = "disabled";
+        };
+
+        usb_otg: usb@ff580000 {
+                compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+                                "snps,dwc2";
+                reg = <0xff580000 0x40000>;
+                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_OTG0>;
+                clock-names = "otg";
+                status = "disabled";
+        };
+
         usb_hsic: usb@ff5c0000 {
                 compatible = "generic-ehci";
                 reg = <0xff5c0000 0x100>;
@@ -241,6 +395,50 @@
                 status = "disabled";
         };
 
+        pwm0: pwm@ff680000 {
+                compatible = "rockchip,rk3288-pwm";
+                reg = <0xff680000 0x10>;
+                #pwm-cells = <3>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm0_pin>;
+                clocks = <&cru PCLK_PWM>;
+                clock-names = "pwm";
+                status = "disabled";
+        };
+
+        pwm1: pwm@ff680010 {
+                compatible = "rockchip,rk3288-pwm";
+                reg = <0xff680010 0x10>;
+                #pwm-cells = <3>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm1_pin>;
+                clocks = <&cru PCLK_PWM>;
+                clock-names = "pwm";
+                status = "disabled";
+        };
+
+        pwm2: pwm@ff680020 {
+                compatible = "rockchip,rk3288-pwm";
+                reg = <0xff680020 0x10>;
+                #pwm-cells = <3>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm2_pin>;
+                clocks = <&cru PCLK_PWM>;
+                clock-names = "pwm";
+                status = "disabled";
+        };
+
+        pwm3: pwm@ff680030 {
+                compatible = "rockchip,rk3288-pwm";
+                reg = <0xff680030 0x10>;
+                #pwm-cells = <2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm3_pin>;
+                clocks = <&cru PCLK_PWM>;
+                clock-names = "pwm";
+                status = "disabled";
+        };
+
         pmu: power-management@ff730000 {
                 compatible = "rockchip,rk3288-pmu", "syscon";
                 reg = <0xff730000 0x100>;
@@ -271,6 +469,21 @@
                 status = "disabled";
         };
 
+        i2s: i2s@ff890000 {
+                compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
+                reg = <0xff890000 0x10000>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s0_bus>;
+                status = "disabled";
+        };
+
         gic: interrupt-controller@ffc01000 {
                 compatible = "arm,gic-400";
                 interrupt-controller;
@@ -463,6 +676,17 @@
                         };
                 };
 
+                i2s0 {
+                        i2s0_bus: i2s0-bus {
+                                rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
+                                                <6 1 RK_FUNC_1 &pcfg_pull_none>,
+                                                <6 2 RK_FUNC_1 &pcfg_pull_none>,
+                                                <6 3 RK_FUNC_1 &pcfg_pull_none>,
+                                                <6 4 RK_FUNC_1 &pcfg_pull_none>,
+                                                <6 8 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
+
                 sdmmc {
                         sdmmc_clk: sdmmc-clk {
                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
@@ -488,6 +712,88 @@
                         };
                 };
 
+                sdio0 {
+                        sdio0_bus1: sdio0-bus1 {
+                                rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        sdio0_bus4: sdio0-bus4 {
+                                rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
+                                                <4 21 RK_FUNC_1 &pcfg_pull_up>,
+                                                <4 22 RK_FUNC_1 &pcfg_pull_up>,
+                                                <4 23 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        sdio0_cmd: sdio0-cmd {
+                                rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        sdio0_clk: sdio0-clk {
+                                rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+
+                        sdio0_cd: sdio0-cd {
+                                rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        sdio0_wp: sdio0-wp {
+                                rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        sdio0_pwr: sdio0-pwr {
+                                rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        sdio0_bkpwr: sdio0-bkpwr {
+                                rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        sdio0_int: sdio0-int {
+                                rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                };
+
+                sdio1 {
+                        sdio1_bus1: sdio1-bus1 {
+                                rockchip,pins = <3 24 4 &pcfg_pull_up>;
+                        };
+
+                        sdio1_bus4: sdio1-bus4 {
+                                rockchip,pins = <3 24 4 &pcfg_pull_up>,
+                                                <3 25 4 &pcfg_pull_up>,
+                                                <3 26 4 &pcfg_pull_up>,
+                                                <3 27 4 &pcfg_pull_up>;
+                        };
+
+                        sdio1_cd: sdio1-cd {
+                                rockchip,pins = <3 28 4 &pcfg_pull_up>;
+                        };
+
+                        sdio1_wp: sdio1-wp {
+                                rockchip,pins = <3 29 4 &pcfg_pull_up>;
+                        };
+
+                        sdio1_bkpwr: sdio1-bkpwr {
+                                rockchip,pins = <3 30 4 &pcfg_pull_up>;
+                        };
+
+                        sdio1_int: sdio1-int {
+                                rockchip,pins = <3 31 4 &pcfg_pull_up>;
+                        };
+
+                        sdio1_cmd: sdio1-cmd {
+                                rockchip,pins = <4 6 4 &pcfg_pull_up>;
+                        };
+
+                        sdio1_clk: sdio1-clk {
+                                rockchip,pins = <4 7 4 &pcfg_pull_none>;
+                        };
+
+                        sdio1_pwr: sdio1-pwr {
+                                rockchip,pins = <4 9 4 &pcfg_pull_up>;
+                        };
+                };
+
                 emmc {
                         emmc_clk: emmc-clk {
                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
@@ -524,6 +830,56 @@
                         };
                 };
 
+                spi0 {
+                        spi0_clk: spi0-clk {
+                                rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi0_cs0: spi0-cs0 {
+                                rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi0_tx: spi0-tx {
+                                rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi0_rx: spi0-rx {
+                                rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi0_cs1: spi0-cs1 {
+                                rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                };
+                spi1 {
+                        spi1_clk: spi1-clk {
+                                rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                        spi1_cs0: spi1-cs0 {
+                                rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                        spi1_rx: spi1-rx {
+                                rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                        spi1_tx: spi1-tx {
+                                rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                };
+
+                spi2 {
+                        spi2_cs1: spi2-cs1 {
+                                rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi2_clk: spi2-clk {
+                                rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi2_cs0: spi2-cs0 {
+                                rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi2_rx: spi2-rx {
+                                rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                        spi2_tx: spi2-tx {
+                                rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                };
+
                 uart0 {
                         uart0_xfer: uart0-xfer {
                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
@@ -591,5 +947,29 @@
                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
                         };
                 };
+
+                pwm0 {
+                        pwm0_pin: pwm0-pin {
+                                rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm1 {
+                        pwm1_pin: pwm1-pin {
+                                rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm2 {
+                        pwm2_pin: pwm2-pin {
+                                rockchip,pins = <7 22 3 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm3 {
+                        pwm3_pin: pwm3-pin {
+                                rockchip,pins = <7 23 3 &pcfg_pull_none>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 8caf85d83901..499468d42ada 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -26,6 +26,49 @@
                 i2c2 = &i2c2;
                 i2c3 = &i2c3;
                 i2c4 = &i2c4;
+                mshc0 = &emmc;
+                mshc1 = &mmc0;
+                mshc2 = &mmc1;
+                spi0 = &spi0;
+                spi1 = &spi1;
+        };
+
+        amba {
+                compatible = "arm,amba-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                dmac1_s: dma-controller@20018000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x20018000 0x4000>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <1>;
+                        clocks = <&cru ACLK_DMA1>;
+                        clock-names = "apb_pclk";
+                };
+
+                dmac1_ns: dma-controller@2001c000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x2001c000 0x4000>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <1>;
+                        clocks = <&cru ACLK_DMA1>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                dmac2: dma-controller@20078000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x20078000 0x4000>;
+                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <1>;
+                        clocks = <&cru ACLK_DMA2>;
+                        clock-names = "apb_pclk";
+                };
         };
 
         xin24m: oscillator {
@@ -91,12 +134,45 @@
                 status = "disabled";
         };
 
+        usb_otg: usb@10180000 {
+                compatible = "rockchip,rk3066-usb", "snps,dwc2";
+                reg = <0x10180000 0x40000>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_OTG0>;
+                clock-names = "otg";
+                status = "disabled";
+        };
+
+        usb_host: usb@101c0000 {
+                compatible = "snps,dwc2";
+                reg = <0x101c0000 0x40000>;
+                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_OTG1>;
+                clock-names = "otg";
+                status = "disabled";
+        };
+
+        emac: ethernet@10204000 {
+                compatible = "snps,arc-emac";
+                reg = <0x10204000 0x3c>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                rockchip,grf = <&grf>;
+
+                clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
+                clock-names = "hclk", "macref";
+                max-speed = <100>;
+                phy-mode = "rmii";
+
+                status = "disabled";
+        };
+
         mmc0: dwmmc@10214000 {
                 compatible = "rockchip,rk2928-dw-mshc";
                 reg = <0x10214000 0x1000>;
                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
                 clock-names = "biu", "ciu";
@@ -108,8 +184,6 @@
                 compatible = "rockchip,rk2928-dw-mshc";
                 reg = <0x10218000 0x1000>;
                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
                 clock-names = "biu", "ciu";
@@ -117,6 +191,17 @@
                 status = "disabled";
         };
 
+        emmc: dwmmc@1021c000 {
+                compatible = "rockchip,rk2928-dw-mshc";
+                reg = <0x1021c000 0x1000>;
+                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+
+                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
+                clock-names = "biu", "ciu";
+
+                status = "disabled";
+        };
+
         pmu: pmu@20004000 {
                 compatible = "rockchip,rk3066-pmu", "syscon";
                 reg = <0x20004000 0x100>;
@@ -135,7 +220,6 @@
                 #size-cells = <0>;
 
                 rockchip,grf = <&grf>;
-                rockchip,bus-index = <0>;
 
                 clock-names = "i2c";
                 clocks = <&cru PCLK_I2C0>;
@@ -264,4 +348,36 @@
                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
                 status = "disabled";
         };
+
+        saradc: saradc@2006c000 {
+                compatible = "rockchip,saradc";
+                reg = <0x2006c000 0x100>;
+                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                #io-channel-cells = <1>;
+                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+                clock-names = "saradc", "apb_pclk";
+                status = "disabled";
+        };
+
+        spi0: spi@20070000 {
+                compatible = "rockchip,rk3066-spi";
+                clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+                clock-names = "spiclk", "apb_pclk";
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                reg = <0x20070000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi1: spi@20074000 {
+                compatible = "rockchip,rk3066-spi";
+                clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+                clock-names = "spiclk", "apb_pclk";
+                interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+                reg = <0x20074000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 45013b867c8d..5f4144d1e3a1 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -177,6 +177,9 @@
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf001c000 0x100>;
                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
+                                       <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart0>;
                                 clocks = <&usart0_clk>;
@@ -188,6 +191,9 @@
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf0020000 0x100>;
                                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
+                                       <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart1>;
                                 clocks = <&usart1_clk>;
@@ -333,6 +339,9 @@
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x100>;
                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
+                                       <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart2>;
                                 clocks = <&usart2_clk>;
@@ -344,6 +353,9 @@
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x100>;
                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
+                                       <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart3>;
                                 clocks = <&usart3_clk>;
@@ -402,14 +414,19 @@
                         };
 
                         ramc0: ramc@ffffea00 {
-                                compatible = "atmel,at91sam9g45-ddramc";
+                                compatible = "atmel,sama5d3-ddramc";
                                 reg = <0xffffea00 0x200>;
+                                clocks = <&ddrck>, <&mpddr_clk>;
+                                clock-names = "ddrck", "mpddr";
                         };
 
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
+                                       <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 clocks = <&dbgu_clk>;
@@ -428,7 +445,7 @@
                         pinctrl@fffff200 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                                compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
                                 ranges = <0xfffff200 0xfffff200 0xa00>;
                                 atmel,mux-mask = <
                                         /*   A          B          C  */
@@ -1003,6 +1020,11 @@
                                                 reg = <2>;
                                         };
 
+                                        hsmc_clk: hsmc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <5>;
+                                        };
+
                                         pioA_clk: pioA_clk {
                                                 #clock-cells = <0>;
                                                 reg = <6>;
@@ -1170,6 +1192,11 @@
                                                 #clock-cells = <0>;
                                                 reg = <48>;
                                         };
+
+                                        mpddr_clk: mpddr_clk {
+                                                #clock-cells = <0>;
+                                                reg = <49>;
+                                        };
                                 };
                         };
 
@@ -1178,6 +1205,11 @@
                                 reg = <0xfffffe00 0x10>;
                         };
 
+                        shutdown-controller@fffffe10 {
+                                compatible = "atmel,at91sam9x5-shdwc";
+                                reg = <0xfffffe10 0x10>;
+                        };
+
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
@@ -1393,6 +1425,7 @@
                                         0xffffc000 0x00000070   /* NFC HSMC regs */
                                         0x00200000 0x00100000   /* NFC SRAM banks */
                                         >;
+                                clocks = <&hsmc_clk>;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index a0775851cce5..eaf41451ad0c 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -40,7 +40,7 @@
                                                 atmel,clk-output-range = <0 66000000>;
                                         };
 
-                                        can1_clk: can0_clk {
+                                        can1_clk: can1_clk {
                                                 #clock-cells = <0>;
                                                 reg = <41>;
                                                 atmel,clk-output-range = <0 66000000>;
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index f7d8583eef82..962dc28dc37b 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -36,6 +36,36 @@
 
                         macb0: ethernet@f0028000 {
                                 phy-mode = "rgmii";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ethernet-phy@1 {
+                                        reg = <0x1>;
+                                        interrupt-parent = <&pioB>;
+                                        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+                                        txen-skew-ps = <800>;
+                                        txc-skew-ps = <3000>;
+                                        rxdv-skew-ps = <400>;
+                                        rxc-skew-ps = <3000>;
+                                        rxd0-skew-ps = <400>;
+                                        rxd1-skew-ps = <400>;
+                                        rxd2-skew-ps = <400>;
+                                        rxd3-skew-ps = <400>;
+                                };
+
+                                ethernet-phy@7 {
+                                        reg = <0x7>;
+                                        interrupt-parent = <&pioB>;
+                                        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+                                        txen-skew-ps = <800>;
+                                        txc-skew-ps = <3000>;
+                                        rxdv-skew-ps = <400>;
+                                        rxc-skew-ps = <3000>;
+                                        rxd0-skew-ps = <400>;
+                                        rxd1-skew-ps = <400>;
+                                        rxd2-skew-ps = <400>;
+                                        rxd3-skew-ps = <400>;
+                                };
                         };
 
                         pmc: pmc@fffffc00 {
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index b8c6f20e780c..49c10d33df30 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -25,6 +25,8 @@
                         };
 
                         spi0: spi@f0004000 {
+                                dmas = <0>, <0>;        /*  Do not use DMA for spi0 */
+
                                 m25p80@0 {
                                         compatible = "atmel,at25df321a";
                                         spi-max-frequency = <50000000>;
@@ -51,6 +53,7 @@
                         };
 
                         usart1: serial@f0020000 {
+                                dmas = <0>, <0>;        /*  Do not use DMA for usart1 */
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
                                 status = "okay";
@@ -132,6 +135,7 @@
                         };
 
                         dbgu: serial@ffffee00 {
+                                dmas = <0>, <0>;        /*  Do not use DMA for dbgu */
                                 status = "okay";
                         };
 
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
new file mode 100644
index 000000000000..e0157b0f075c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -0,0 +1,1240 @@
+/*
+ * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
+ *
+ *  Copyright (C) 2014 Atmel,
+ *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Atmel SAMA5D4 family SoC";
+        compatible = "atmel,sama5d4";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &usart3;
+                serial1 = &usart4;
+                serial2 = &usart2;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+                i2c2 = &i2c2;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a5";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                reg = <0x20000000 0x20000000>;
+        };
+
+        clocks {
+                slow_xtal: slow_xtal {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                };
+
+                main_xtal: main_xtal {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                };
+
+                adc_op_clk: adc_op_clk{
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                };
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                usb0: gadget@00400000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "atmel,at91sam9rl-udc";
+                        reg = <0x00400000 0x100000
+                               0xfc02c000 0x4000>;
+                        interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&udphs_clk>, <&utmi>;
+                        clock-names = "pclk", "hclk";
+                        status = "disabled";
+
+                        ep0 {
+                                reg = <0>;
+                                atmel,fifo-size = <64>;
+                                atmel,nb-banks = <1>;
+                        };
+
+                        ep1 {
+                                reg = <1>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep2 {
+                                reg = <2>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep3 {
+                                reg = <3>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep4 {
+                                reg = <4>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep5 {
+                                reg = <5>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep6 {
+                                reg = <6>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep7 {
+                                reg = <7>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep8 {
+                                reg = <8>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+
+                        ep9 {
+                                reg = <9>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+
+                        ep10 {
+                                reg = <10>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+
+                        ep11 {
+                                reg = <11>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+
+                        ep12 {
+                                reg = <12>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+
+                        ep13 {
+                                reg = <13>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+
+                        ep14 {
+                                reg = <14>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+
+                        ep15 {
+                                reg = <15>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-isoc;
+                        };
+                };
+
+                usb1: ohci@00500000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00500000 0x100000>;
+                        interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
+                                 <&uhpck>;
+                        clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
+                        status = "disabled";
+                };
+
+                usb2: ehci@00600000 {
+                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                        reg = <0x00600000 0x100000>;
+                        interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
+                        clock-names = "usb_clk", "ehci_clk", "uhpck";
+                        status = "disabled";
+                };
+
+                L2: cache-controller@00a00000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x00a00000 0x1000>;
+                        interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                nand0: nand@80000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        reg = < 0x80000000 0x08000000   /* EBI CS3 */
+                                0xfc05c070 0x00000490   /* SMC PMECC regs */
+                                0xfc05c500 0x00000100   /* SMC PMECC Error Location regs */
+                                >;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        atmel,nand-has-dma;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
+                        status = "disabled";
+
+                        nfc@90000000 {
+                                compatible = "atmel,sama5d3-nfc";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <
+                                        0x90000000 0x10000000   /* NFC Command Registers */
+                                        0xfc05c000 0x00000070   /* NFC HSMC regs */
+                                        0x00100000 0x00100000   /* NFC SRAM banks */
+                                         >;
+                                clocks = <&hsmc_clk>;
+                                atmel,write-by-sram;
+                        };
+                };
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        ramc0: ramc@f0010000 {
+                                compatible = "atmel,sama5d3-ddramc";
+                                reg = <0xf0010000 0x200>;
+                                clocks = <&ddrck>, <&mpddr_clk>;
+                                clock-names = "ddrck", "mpddr";
+                        };
+
+                        pmc: pmc@f0018000 {
+                                compatible = "atmel,sama5d3-pmc";
+                                reg = <0xf0018000 0x120>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #interrupt-cells = <1>;
+
+                                main_rc_osc: main_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-main-rc-osc";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MOSCRCS>;
+                                        clock-frequency = <12000000>;
+                                        clock-accuracy = <100000000>;
+                                };
+
+                                main_osc: main_osc {
+                                        compatible = "atmel,at91rm9200-clk-main-osc";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MOSCS>;
+                                        clocks = <&main_xtal>;
+                                };
+
+                                main: mainck {
+                                        compatible = "atmel,at91sam9x5-clk-main";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MOSCSELS>;
+                                        clocks = <&main_rc_osc &main_osc>;
+                                };
+
+                                plla: pllack {
+                                        compatible = "atmel,sama5d3-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_LOCKA>;
+                                        clocks = <&main>;
+                                        reg = <0>;
+                                        atmel,clk-input-range = <12000000 12000000>;
+                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
+                                };
+
+                                plladiv: plladivck {
+                                        compatible = "atmel,at91sam9x5-clk-plldiv";
+                                        #clock-cells = <0>;
+                                        clocks = <&plla>;
+                                };
+
+                                utmi: utmick {
+                                        compatible = "atmel,at91sam9x5-clk-utmi";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_LOCKU>;
+                                        clocks = <&main>;
+                                };
+
+                                mck: masterck {
+                                        compatible = "atmel,at91sam9x5-clk-master";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MCKRDY>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+                                        atmel,clk-output-range = <125000000 177000000>;
+                                        atmel,clk-divisors = <1 2 4 3>;
+                                };
+
+                                h32ck: h32mxck {
+                                        #clock-cells = <0>;
+                                        compatible = "atmel,sama5d4-clk-h32mx";
+                                        clocks = <&mck>;
+                                };
+
+                                usb: usbck {
+                                        compatible = "atmel,at91sam9x5-clk-usb";
+                                        #clock-cells = <0>;
+                                        clocks = <&plladiv>, <&utmi>;
+                                };
+
+                                prog: progck {
+                                        compatible = "atmel,at91sam9x5-clk-programmable";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+                                        prog0: prog0 {
+                                                #clock-cells = <0>;
+                                                reg = <0>;
+                                                interrupts = <AT91_PMC_PCKRDY(0)>;
+                                        };
+
+                                        prog1: prog1 {
+                                                #clock-cells = <0>;
+                                                reg = <1>;
+                                                interrupts = <AT91_PMC_PCKRDY(1)>;
+                                        };
+
+                                        prog2: prog2 {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                                interrupts = <AT91_PMC_PCKRDY(2)>;
+                                        };
+                                };
+
+                                smd: smdclk {
+                                        compatible = "atmel,at91sam9x5-clk-smd";
+                                        #clock-cells = <0>;
+                                        clocks = <&plladiv>, <&utmi>;
+                                };
+
+                                systemck {
+                                        compatible = "atmel,at91rm9200-clk-system";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        ddrck: ddrck {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                                clocks = <&mck>;
+                                        };
+
+                                        lcdck: lcdck {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                                clocks = <&smd>;
+                                        };
+
+                                        smdck: smdck {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                                clocks = <&smd>;
+                                        };
+
+                                        uhpck: uhpck {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                                clocks = <&usb>;
+                                        };
+
+                                        udpck: udpck {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                                clocks = <&usb>;
+                                        };
+
+                                        pck0: pck0 {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                                clocks = <&prog0>;
+                                        };
+
+                                        pck1: pck1 {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                                clocks = <&prog1>;
+                                        };
+
+                                        pck2: pck2 {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                                clocks = <&prog2>;
+                                        };
+                                };
+
+                                periph32ck {
+                                        compatible = "atmel,at91sam9x5-clk-peripheral";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        clocks = <&h32ck>;
+
+                                        pioD_clk: pioD_clk {
+                                                #clock-cells = <0>;
+                                                reg = <5>;
+                                        };
+
+                                        usart0_clk: usart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                        };
+
+                                        usart1_clk: usart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                        };
+
+                                        icm_clk: icm_clk {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                        };
+
+                                        aes_clk: aes_clk {
+                                                #clock-cells = <0>;
+                                                reg = <12>;
+                                        };
+
+                                        tdes_clk: tdes_clk {
+                                                #clock-cells = <0>;
+                                                reg = <14>;
+                                        };
+
+                                        sha_clk: sha_clk {
+                                                #clock-cells = <0>;
+                                                reg = <15>;
+                                        };
+
+                                        matrix1_clk: matrix1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <17>;
+                                        };
+
+                                        hsmc_clk: hsmc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <22>;
+                                        };
+
+                                        pioA_clk: pioA_clk {
+                                                #clock-cells = <0>;
+                                                reg = <23>;
+                                        };
+
+                                        pioB_clk: pioB_clk {
+                                                #clock-cells = <0>;
+                                                reg = <24>;
+                                        };
+
+                                        pioC_clk: pioC_clk {
+                                                #clock-cells = <0>;
+                                                reg = <25>;
+                                        };
+
+                                        pioE_clk: pioE_clk {
+                                                #clock-cells = <0>;
+                                                reg = <26>;
+                                        };
+
+                                        uart0_clk: uart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <27>;
+                                        };
+
+                                        uart1_clk: uart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <28>;
+                                        };
+
+                                        usart2_clk: usart2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <29>;
+                                        };
+
+                                        usart3_clk: usart3_clk {
+                                                #clock-cells = <0>;
+                                                reg = <30>;
+                                        };
+
+                                        usart4_clk: usart4_clk {
+                                                #clock-cells = <0>;
+                                                reg = <31>;
+                                        };
+
+                                        twi0_clk: twi0_clk {
+                                                reg = <32>;
+                                                #clock-cells = <0>;
+                                        };
+
+                                        twi1_clk: twi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <33>;
+                                        };
+
+                                        twi2_clk: twi2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <34>;
+                                        };
+
+                                        mci0_clk: mci0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <35>;
+                                        };
+
+                                        mci1_clk: mci1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <36>;
+                                        };
+
+                                        spi0_clk: spi0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <37>;
+                                        };
+
+                                        spi1_clk: spi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <38>;
+                                        };
+
+                                        spi2_clk: spi2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <39>;
+                                        };
+
+                                        tcb0_clk: tcb0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <40>;
+                                        };
+
+                                        tcb1_clk: tcb1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <41>;
+                                        };
+
+                                        tcb2_clk: tcb2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <42>;
+                                        };
+
+                                        pwm_clk: pwm_clk {
+                                                #clock-cells = <0>;
+                                                reg = <43>;
+                                        };
+
+                                        adc_clk: adc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <44>;
+                                        };
+
+                                        dbgu_clk: dbgu_clk {
+                                                #clock-cells = <0>;
+                                                reg = <45>;
+                                        };
+
+                                        uhphs_clk: uhphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <46>;
+                                        };
+
+                                        udphs_clk: udphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <47>;
+                                        };
+
+                                        ssc0_clk: ssc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <48>;
+                                        };
+
+                                        ssc1_clk: ssc1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <49>;
+                                        };
+
+                                        trng_clk: trng_clk {
+                                                #clock-cells = <0>;
+                                                reg = <53>;
+                                        };
+
+                                        macb0_clk: macb0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <54>;
+                                        };
+
+                                        macb1_clk: macb1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <55>;
+                                        };
+
+                                        fuse_clk: fuse_clk {
+                                                #clock-cells = <0>;
+                                                reg = <57>;
+                                        };
+
+                                        securam_clk: securam_clk {
+                                                #clock-cells = <0>;
+                                                reg = <59>;
+                                        };
+
+                                        smd_clk: smd_clk {
+                                                #clock-cells = <0>;
+                                                reg = <61>;
+                                        };
+
+                                        twi3_clk: twi3_clk {
+                                                #clock-cells = <0>;
+                                                reg = <62>;
+                                        };
+
+                                        catb_clk: catb_clk {
+                                                #clock-cells = <0>;
+                                                reg = <63>;
+                                        };
+                                };
+
+                                periph64ck {
+                                        compatible = "atmel,at91sam9x5-clk-peripheral";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        clocks = <&mck>;
+
+                                        dma0_clk: dma0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                        };
+
+                                        cpkcc_clk: cpkcc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                        };
+
+                                        aesb_clk: aesb_clk {
+                                                #clock-cells = <0>;
+                                                reg = <13>;
+                                        };
+
+                                        mpddr_clk: mpddr_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                        };
+
+                                        matrix0_clk: matrix0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <18>;
+                                        };
+
+                                        vdec_clk: vdec_clk {
+                                                #clock-cells = <0>;
+                                                reg = <19>;
+                                        };
+
+                                        dma1_clk: dma1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <50>;
+                                        };
+
+                                        lcd_clk: lcd_clk {
+                                                #clock-cells = <0>;
+                                                reg = <51>;
+                                        };
+
+                                        isi_clk: isi_clk {
+                                                #clock-cells = <0>;
+                                                reg = <52>;
+                                        };
+                                };
+                        };
+
+                        mmc0: mmc@f8000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf8000000 0x600>;
+                                interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&mci0_clk>;
+                                clock-names = "mci_clk";
+                        };
+
+                        spi0: spi@f8010000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xf8010000 0x100>;
+                                interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                clocks = <&spi0_clk>;
+                                clock-names = "spi_clk";
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@f8014000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8014000 0x4000>;
+                                interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&twi0_clk>;
+                                status = "disabled";
+                        };
+
+                        tcb0: timer@f801c000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf801c000 0x100>;
+                                interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb0_clk>;
+                                clock-names = "t0_clk";
+                        };
+
+                        macb0: ethernet@f8020000 {
+                                compatible = "atmel,sama5d4-gem";
+                                reg = <0xf8020000 0x100>;
+                                interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb0_rmii>;
+                                clocks = <&macb0_clk>, <&macb0_clk>;
+                                clock-names = "hclk", "pclk";
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@f8024000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8024000 0x4000>;
+                                interrupts = <34 4 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&twi2_clk>;
+                                status = "disabled";
+                        };
+
+                        mmc1: mmc@fc000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfc000000 0x600>;
+                                interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&mci1_clk>;
+                                clock-names = "mci_clk";
+                        };
+
+                        usart2: serial@fc008000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfc008000 0x100>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
+                                clocks = <&usart2_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+
+                        usart3: serial@fc00c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfc00c000 0x100>;
+                                interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
+                                clocks = <&usart3_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+
+                        usart4: serial@fc010000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfc010000 0x100>;
+                                interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart4>;
+                                clocks = <&usart4_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+
+                        tcb1: timer@fc020000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xfc020000 0x100>;
+                                interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb1_clk>;
+                                clock-names = "t0_clk";
+                        };
+
+                        adc0: adc@fc034000 {
+                                compatible = "atmel,at91sam9x5-adc";
+                                reg = <0xfc034000 0x100>;
+                                interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        /* external trigger is conflict with USBA_VBUS */
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        >;
+                                clocks = <&adc_clk>,
+                                         <&adc_op_clk>;
+                                clock-names = "adc_clk", "adc_op_clk";
+                                atmel,adc-channels-used = <0x01f>;
+                                atmel,adc-startup-time = <40>;
+                                atmel,adc-use-external;
+                                atmel,adc-vref = <3000>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-sample-hold-time = <11>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-ts-pressure-threshold = <10000>;
+                                status = "disabled";
+
+                                trigger@0 {
+                                        trigger-name = "external-rising";
+                                        trigger-value = <0x1>;
+                                        trigger-external;
+                                };
+                                trigger@1 {
+                                        trigger-name = "external-falling";
+                                        trigger-value = <0x2>;
+                                        trigger-external;
+                                };
+                                trigger@2 {
+                                        trigger-name = "external-any";
+                                        trigger-value = <0x3>;
+                                        trigger-external;
+                                };
+                                trigger@3 {
+                                        trigger-name = "continuous";
+                                        trigger-value = <0x6>;
+                                };
+                        };
+
+                        rstc@fc068600 {
+                                compatible = "atmel,at91sam9g45-rstc";
+                                reg = <0xfc068600 0x10>;
+                        };
+
+                        shdwc@fc068610 {
+                                compatible = "atmel,at91sam9x5-shdwc";
+                                reg = <0xfc068610 0x10>;
+                        };
+
+                        pit: timer@fc068630 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfc068630 0xf>;
+                                interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
+                                clocks = <&h32ck>;
+                        };
+
+                        watchdog@fc068640 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfc068640 0x10>;
+                                status = "disabled";
+                        };
+
+                        sckc@fc068650 {
+                                compatible = "atmel,at91sam9x5-sckc";
+                                reg = <0xfc068650 0x4>;
+
+                                slow_rc_osc: slow_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                        #clock-cells = <0>;
+                                        clock-frequency = <32768>;
+                                        clock-accuracy = <250000000>;
+                                        atmel,startup-time-usec = <75>;
+                                };
+
+                                slow_osc: slow_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_xtal>;
+                                        atmel,startup-time-usec = <1200000>;
+                                };
+
+                                clk32k: slowck {
+                                        compatible = "atmel,at91sam9x5-clk-slow";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_rc_osc &slow_osc>;
+                                };
+                        };
+
+                        rtc@fc0686b0 {
+                                compatible = "atmel,at91rm9200-rtc";
+                                reg = <0xfc0686b0 0x30>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                        };
+
+                        dbgu: serial@fc069000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfc069000 0x200>;
+                                interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
+                                clocks = <&dbgu_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+
+
+                        pinctrl@fc06a000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                                ranges = <0xfc06a000 0xfc06a000 0x4000>;
+                                /* WARNING: revisit as pin spec has changed */
+                                atmel,mux-mask = <
+                                        /*   A          B          C  */
+                                        0xffffffff 0x3ffcfe7c 0x1c010101        /* pioA */
+                                        0x7fffffff 0xfffccc3a 0x3f00cc3a        /* pioB */
+                                        0xffffffff 0x3ff83fff 0xff00ffff        /* pioC */
+                                        0x00000000 0x00000000 0x00000000        /* pioD */
+                                        0xffffffff 0x7fffffff 0x76fff1bf        /* pioE */
+                                        >;
+
+                                pioA: gpio@fc06a000 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfc06a000 0x100>;
+                                        interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioA_clk>;
+                                };
+
+                                pioB: gpio@fc06b000 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfc06b000 0x100>;
+                                        interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioB_clk>;
+                                };
+
+                                pioC: gpio@fc06c000 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfc06c000 0x100>;
+                                        interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioC_clk>;
+                                };
+
+                                pioE: gpio@fc06d000 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfc06d000 0x100>;
+                                        interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioE_clk>;
+                                };
+
+                                /* pinctrl pin settings */
+                                adc0 {
+                                        pinctrl_adc0_adtrg: adc0_adtrg {
+                                                atmel,pins =
+                                                        <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
+                                        };
+                                        pinctrl_adc0_ad0: adc0_ad0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad1: adc0_ad1 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad2: adc0_ad2 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad3: adc0_ad3 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad4: adc0_ad4 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,     /* conflicts with D14 and TDI */
+                                                        <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;  /* conflicts with D15 and TDO */
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2: i2c2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* TWD2, conflicts with RD0 and PWML1 */
+                                                         AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
+                                        };
+                                };
+
+                                macb0 {
+                                        pinctrl_macb0_rmii: macb0_rmii-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX0 */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX1 */
+                                                         AT91_PIOB  8 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX0 */
+                                                         AT91_PIOB  9 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX1 */
+                                                         AT91_PIOB  6 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXDV */
+                                                         AT91_PIOB  7 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXER */
+                                                         AT91_PIOB  2 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXEN */
+                                                         AT91_PIOB  0 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXCK */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDC */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDIO */
+                                                        >;
+                                        };
+                                };
+
+                                mmc0 {
+                                        pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* MCI0_CK, conflict with PCK1(ISI_MCK) */
+                                                         AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
+                                                         AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
+                                                        >;
+                                        };
+                                        pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
+                                                         AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
+                                                         AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
+                                                        >;
+                                        };
+                                };
+
+                                mmc1 {
+                                        pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE           /* MCI1_CK */
+                                                         AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_CDA */
+                                                         AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA0 */
+                                                        >;
+                                        };
+                                        pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA1 */
+                                                         AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA2 */
+                                                         AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA3 */
+                                                        >;
+                                        };
+                                };
+
+                                nand0 {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC13 periph A Read Enable */
+                                                         AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC14 periph A Write Enable */
+
+                                                         AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC17 ALE */
+                                                         AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC18 CLE */
+
+                                                         AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC15 NCS3/Chip Enable */
+                                                         AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC16 NANDRDY */
+                                                         AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC5 Data bit 0 */
+                                                         AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 Data bit 1 */
+                                                         AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 Data bit 2 */
+                                                         AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 Data bit 3 */
+                                                         AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC9 Data bit 4 */
+                                                         AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC10 Data bit 5 */
+                                                         AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC11 periph A Data bit 6 */
+                                                         AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
+                                        };
+                                };
+
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MISO */
+                                                         AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MOSI */
+                                                         AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_SPCK */
+                                                        >;
+                                        };
+                                };
+
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE            /* RXD - conflicts with G0_CRS, ISI_HSYNC */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP         /* TXD - conflicts with G0_COL, PCK2 */
+                                                        >;
+                                        };
+                                        pinctrl_usart2_rts: usart2_rts-0 {
+                                                atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with G0_RX3, PWMH1 */
+                                        };
+                                        pinctrl_usart2_cts: usart2_cts-0 {
+                                                atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;     /* conflicts with G0_TXER, ISI_VSYNC */
+                                        };
+                                };
+
+                                usart3 {
+                                        pinctrl_usart3: usart3-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
+                                                         AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        >;
+                                        };
+                                };
+
+                                usart4 {
+                                        pinctrl_usart4: usart4-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
+                                                         AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        >;
+                                        };
+                                        pinctrl_usart4_rts: usart4_rts-0 {
+                                                atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with NWAIT, A19 */
+                                        };
+                                        pinctrl_usart4_cts: usart4_cts-0 {
+                                                atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>;     /* conflicts with A0/NBS0, MCI0_CDB */
+                                        };
+                                };
+                        };
+
+                        aic: interrupt-controller@fc06e000 {
+                                #interrupt-cells = <3>;
+                                compatible = "atmel,sama5d4-aic";
+                                interrupt-controller;
+                                reg = <0xfc06e000 0x200>;
+                                atmel,external-irqs = <56>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 249f65be2a50..f863a10cb1b2 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -21,6 +21,7 @@
                         compatible = "arm,cortex-a8";
                         device_type = "cpu";
                         reg = <0x0>;
+                        clock-frequency = <800000000>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 18662aec2ec4..30ef97e99dc5 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -66,7 +66,7 @@
         };
 
         vmmc_sdhi0: regulator@2 {
-                compatible = "regulator-fixed";
+                compatible = "regulator-fixed";
                 regulator-name = "SDHI0 Vcc";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
@@ -75,7 +75,7 @@
         };
 
         vmmc_sdhi2: regulator@3 {
-                compatible = "regulator-fixed";
+                compatible = "regulator-fixed";
                 regulator-name = "SDHI2 Vcc";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
@@ -173,6 +173,10 @@
         };
 };
 
+&cmt1 {
+        status = "ok";
+};
+
 &i2c0 {
         status = "okay";
         as3711@40 {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 910b79079d5a..030a5920312f 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -14,6 +14,7 @@
 
 / {
         compatible = "renesas,sh73a0";
+        interrupt-parent = <&gic>;
 
         cpus {
                 #address-cells = <1>;
@@ -23,11 +24,13 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
+                        clock-frequency = <1196000000>;
                 };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <1>;
+                        clock-frequency = <1196000000>;
                 };
         };
 
@@ -45,6 +48,16 @@
                              <0 56 IRQ_TYPE_LEVEL_HIGH>;
         };
 
+        cmt1: timer@e6138000 {
+                compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
+                reg = <0xe6138000 0x200>;
+                interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
+
+                renesas,channels-mask = <0x3f>;
+
+                status = "disabled";
+        };
+
         irqpin0: irqpin@e6900000 {
                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
@@ -54,7 +67,6 @@
                         <0xe6900020 1>,
                         <0xe6900040 1>,
                         <0xe6900060 1>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
                               0 2 IRQ_TYPE_LEVEL_HIGH
                               0 3 IRQ_TYPE_LEVEL_HIGH
@@ -74,7 +86,6 @@
                         <0xe6900024 1>,
                         <0xe6900044 1>,
                         <0xe6900064 1>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
                               0 10 IRQ_TYPE_LEVEL_HIGH
                               0 11 IRQ_TYPE_LEVEL_HIGH
@@ -95,7 +106,6 @@
                         <0xe6900028 1>,
                         <0xe6900048 1>,
                         <0xe6900068 1>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
                               0 18 IRQ_TYPE_LEVEL_HIGH
                               0 19 IRQ_TYPE_LEVEL_HIGH
@@ -115,7 +125,6 @@
                         <0xe690002c 1>,
                         <0xe690004c 1>,
                         <0xe690006c 1>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
                               0 26 IRQ_TYPE_LEVEL_HIGH
                               0 27 IRQ_TYPE_LEVEL_HIGH
@@ -131,7 +140,6 @@
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6820000 0x425>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
                               0 168 IRQ_TYPE_LEVEL_HIGH
                               0 169 IRQ_TYPE_LEVEL_HIGH
@@ -144,7 +152,6 @@
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6822000 0x425>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
                               0 52 IRQ_TYPE_LEVEL_HIGH
                               0 53 IRQ_TYPE_LEVEL_HIGH
@@ -157,7 +164,6 @@
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6824000 0x425>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
                               0 172 IRQ_TYPE_LEVEL_HIGH
                               0 173 IRQ_TYPE_LEVEL_HIGH
@@ -170,7 +176,6 @@
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6826000 0x425>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
                               0 184 IRQ_TYPE_LEVEL_HIGH
                               0 185 IRQ_TYPE_LEVEL_HIGH
@@ -183,7 +188,6 @@
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6828000 0x425>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
                               0 188 IRQ_TYPE_LEVEL_HIGH
                               0 189 IRQ_TYPE_LEVEL_HIGH
@@ -194,7 +198,6 @@
         mmcif: mmc@e6bd0000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0xe6bd0000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
                               0 141 IRQ_TYPE_LEVEL_HIGH>;
                 reg-io-width = <4>;
@@ -204,7 +207,6 @@
         sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee100000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
                               0 84 IRQ_TYPE_LEVEL_HIGH
                               0 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -216,7 +218,6 @@
         sdhi1: sd@ee120000 {
                 compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee120000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
                               0 89 IRQ_TYPE_LEVEL_HIGH>;
                 toshiba,mmc-wrprotect-disable;
@@ -227,7 +228,6 @@
         sdhi2: sd@ee140000 {
                 compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee140000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
                               0 105 IRQ_TYPE_LEVEL_HIGH>;
                 toshiba,mmc-wrprotect-disable;
@@ -238,7 +238,6 @@
         scifa0: serial@e6c40000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c40000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -246,7 +245,6 @@
         scifa1: serial@e6c50000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c50000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -254,7 +252,6 @@
         scifa2: serial@e6c60000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c60000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -262,7 +259,6 @@
         scifa3: serial@e6c70000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c70000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -270,7 +266,6 @@
         scifa4: serial@e6c80000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6c80000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -278,7 +273,6 @@
         scifa5: serial@e6cb0000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6cb0000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -286,7 +280,6 @@
         scifa6: serial@e6cc0000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6cc0000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -294,7 +287,6 @@
         scifa7: serial@e6cd0000 {
                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
                 reg = <0xe6cd0000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -302,7 +294,6 @@
         scifb8: serial@e6c30000 {
                 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
                 reg = <0xe6c30000 0x100>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
@@ -328,7 +319,6 @@
                 #sound-dai-cells = <1>;
                 compatible = "renesas,sh_fsi2";
                 reg = <0xec230000 0x400>;
-                interrupt-parent = <&gic>;
                 interrupts = <0 146 0x4>;
                 status = "disabled";
         };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4d77ad690ed5..45fce2cf6fed 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -607,6 +607,17 @@
                         };
                 };
 
+                sdr: sdr@ffc25000 {
+                        compatible = "syscon";
+                        reg = <0xffc25000 0x1000>;
+                };
+
+                sdramedac {
+                        compatible = "altr,sdram-edac";
+                        altr,sdr-syscon = <&sdr>;
+                        interrupts = <0 39 4>;
+                };
+
                 L2: l2-cache@fffef000 {
                         compatible = "arm,pl310-cache";
                         reg = <0xfffef000 0x1000>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2ccaf5b..03e8268ae219 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -15,6 +15,8 @@
  */
 
 /dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
 #include "socfpga.dtsi"
 
 / {
@@ -29,13 +31,10 @@
 
                 dwmmc0@ff704000 {
                         num-slots = <1>;
-                        supports-highspeed;
                         broken-cd;
-
-                        slot@0 {
-                                reg = <0>;
-                                bus-width = <4>;
-                        };
+                        bus-width = <4>;
+                        cap-mmc-highspeed;
+                        cap-sd-highspeed;
                 };
 
                 sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index d532d171e391..27d551c384d0 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,13 +37,6 @@
                 */
                 ethernet0 = &gmac1;
         };
-
-        aliases {
-                /* this allow the ethaddr uboot environmnet variable contents
-                 * to be added to the gmac1 device tree blob.
-                 */
-                ethernet0 = &gmac1;
-        };
 };
 
 &gmac1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf511828729f..28c05e7a31c9 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -16,6 +16,8 @@
  */
 
 /dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
 #include "socfpga.dtsi"
 
 / {
@@ -28,15 +30,12 @@
                         };
                 };
 
-                dwmmc0@ff704000 {
+                mmc0: dwmmc0@ff704000 {
                         num-slots = <1>;
-                        supports-highspeed;
                         broken-cd;
-
-                        slot@0 {
-                                reg = <0>;
-                                bus-width = <4>;
-                        };
+                        bus-width = <4>;
+                        cap-mmc-highspeed;
+                        cap-sd-highspeed;
                 };
 
                 ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 45de1514af0a..d7296a5f750c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -68,6 +68,10 @@
         };
 };
 
+&mmc0 {
+        cd-gpios = <&gpio1 18 0>;
+};
+
 &usb1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b411110..f9345e02ca49 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
 
                 dwmmc0@ff704000 {
                         num-slots = <1>;
-                        supports-highspeed;
                         broken-cd;
-
-                        slot@0 {
-                                reg = <0>;
-                                bus-width = <4>;
-                        };
+                        bus-width = <4>;
+                        cap-mmc-highspeed;
+                        cap-sd-highspeed;
                 };
 
                 ethernet@ff700000 {
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index fa5f2bb5f106..9d342920695a 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -85,7 +85,8 @@
 
                 pcie0: pcie@b1000000 {
                         compatible = "st,spear1340-pcie", "snps,dw-pcie";
-                        reg = <0xb1000000 0x4000>;
+                        reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
+                        reg-names = "dbi", "config";
                         interrupts = <0 68 0x4>;
                         interrupt-map-mask = <0 0 0 0>;
                         interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -95,15 +96,15 @@
                         #address-cells = <3>;
                         #size-cells = <2>;
                         device_type = "pci";
-                        ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
-                                0x81000000 0 0   0x80020000 0 0x00010000   /* downstream I/O */
+                        ranges = <0x81000000 0 0         0x80020000 0 0x00010000   /* downstream I/O */
                                 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
                         status = "disabled";
                 };
 
                 pcie1: pcie@b1800000 {
                         compatible = "st,spear1340-pcie", "snps,dw-pcie";
-                        reg = <0xb1800000 0x4000>;
+                        reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
+                        reg-names = "dbi", "config";
                         interrupts = <0 69 0x4>;
                         interrupt-map-mask = <0 0 0 0>;
                         interrupt-map = <0x0 0 &gic 0 69 0x4>;
@@ -113,15 +114,15 @@
                         #address-cells = <3>;
                         #size-cells = <2>;
                         device_type = "pci";
-                        ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000   /* configuration space */
-                                0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
+                        ranges = <0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
                                 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
                         status = "disabled";
                 };
 
                 pcie2: pcie@b4000000 {
                         compatible = "st,spear1340-pcie", "snps,dw-pcie";
-                        reg = <0xb4000000 0x4000>;
+                        reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
+                        reg-names = "dbi", "config";
                         interrupts = <0 70 0x4>;
                         interrupt-map-mask = <0 0 0 0>;
                         interrupt-map = <0x0 0 &gic 0 70 0x4>;
@@ -131,8 +132,7 @@
                         #address-cells = <3>;
                         #size-cells = <2>;
                         device_type = "pci";
-                        ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000   /* configuration space */
-                                0x81000000 0 0   0xc0020000 0 0x00010000   /* downstream I/O */
+                        ranges = <0x81000000 0 0         0xc0020000 0 0x00010000   /* downstream I/O */
                                 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
                         status = "disabled";
                 };
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index e71df0f2cb52..13e1aa33daa2 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -50,7 +50,8 @@
 
                 pcie0: pcie@b1000000 {
                         compatible = "st,spear1340-pcie", "snps,dw-pcie";
-                        reg = <0xb1000000 0x4000>;
+                        reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
+                        reg-names = "dbi", "config";
                         interrupts = <0 68 0x4>;
                         interrupt-map-mask = <0 0 0 0>;
                         interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -60,8 +61,7 @@
                         #address-cells = <3>;
                         #size-cells = <2>;
                         device_type = "pci";
-                        ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
-                                0x81000000 0 0   0x80020000 0 0x00010000   /* downstream I/O */
+                        ranges = <0x81000000 0 0         0x80020000 0 0x00010000   /* downstream I/O */
                                 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
                         status = "disabled";
                 };
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 4a2000c620ad..3e97a669f15e 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -116,7 +116,6 @@
                 msp2: msp@80117000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&msp2_default_mode>;
-                        status = "okay";
                 };
 
                 msp3: msp@80125000 {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 459cb6377764..380f914b226d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -339,12 +339,22 @@
                 #size-cells = <1>;
                 ranges;
 
+                dma: dma-controller@01c02000 {
+                        compatible = "allwinner,sun4i-a10-dma";
+                        reg = <0x01c02000 0x1000>;
+                        interrupts = <27>;
+                        clocks = <&ahb_gates 6>;
+                        #dma-cells = <2>;
+                };
+
                 spi0: spi@01c05000 {
                         compatible = "allwinner,sun4i-a10-spi";
                         reg = <0x01c05000 0x1000>;
                         interrupts = <10>;
                         clocks = <&ahb_gates 20>, <&spi0_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 27>, <&dma 1 26>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -356,6 +366,8 @@
                         interrupts = <11>;
                         clocks = <&ahb_gates 21>, <&spi1_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 9>, <&dma 1 8>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -451,6 +463,8 @@
                         interrupts = <12>;
                         clocks = <&ahb_gates 22>, <&spi2_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 29>, <&dma 1 28>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -490,6 +504,8 @@
                         interrupts = <50>;
                         clocks = <&ahb_gates 23>, <&spi3_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 31>, <&dma 1 30>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -749,7 +765,6 @@
                         reg = <0x01c2ac00 0x400>;
                         interrupts = <7>;
                         clocks = <&apb1_gates 0>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -760,7 +775,6 @@
                         reg = <0x01c2b000 0x400>;
                         interrupts = <8>;
                         clocks = <&apb1_gates 1>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -771,7 +785,6 @@
                         reg = <0x01c2b400 0x400>;
                         interrupts = <9>;
                         clocks = <&apb1_gates 2>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 24b0ad3a7c07..d73a2287b37a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -300,12 +300,22 @@
                 #size-cells = <1>;
                 ranges;
 
+                dma: dma-controller@01c02000 {
+                        compatible = "allwinner,sun4i-a10-dma";
+                        reg = <0x01c02000 0x1000>;
+                        interrupts = <27>;
+                        clocks = <&ahb_gates 6>;
+                        #dma-cells = <2>;
+                };
+
                 spi0: spi@01c05000 {
                         compatible = "allwinner,sun4i-a10-spi";
                         reg = <0x01c05000 0x1000>;
                         interrupts = <10>;
                         clocks = <&ahb_gates 20>, <&spi0_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 27>, <&dma 1 26>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -317,6 +327,8 @@
                         interrupts = <11>;
                         clocks = <&ahb_gates 21>, <&spi1_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 9>, <&dma 1 8>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -403,6 +415,8 @@
                         interrupts = <12>;
                         clocks = <&ahb_gates 22>, <&spi2_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 29>, <&dma 1 28>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -564,7 +578,6 @@
                         reg = <0x01c2ac00 0x400>;
                         interrupts = <7>;
                         clocks = <&apb1_gates 0>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                 };
 
@@ -575,7 +588,6 @@
                         reg = <0x01c2b000 0x400>;
                         interrupts = <8>;
                         clocks = <&apb1_gates 1>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                 };
 
@@ -586,7 +598,6 @@
                         reg = <0x01c2b400 0x400>;
                         interrupts = <9>;
                         clocks = <&apb1_gates 2>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
new file mode 100644
index 000000000000..8b3cd0907b32
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun5i-a13.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+
+/ {
+        model = "HSG H702";
+        compatible = "hsg,h702", "allwinner,sun5i-a13";
+
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 6 0 0>; /* PG0 */
+                        cd-inverted;
+                        status = "okay";
+                };
+
+                usbphy: phy@01c13400 {
+                        /*
+                         * There doesn't seem to be a GPIO for controlling
+                         * usb1 vbus, despite the fex file saying otherwise.
+                         */
+                        usb1_vbus-supply = <&reg_vcc5v0>;
+                        status = "okay";
+                };
+
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+
+                pinctrl@01c20800 {
+                        mmc0_cd_pin_h702: mmc0_cd_pin@0 {
+                                allwinner,pins = "PG0";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                };
+
+                uart1: serial@01c28400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_pins_b>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupts = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+
+                        pcf8563: rtc@51 {
+                                compatible = "nxp,pcf8563";
+                                reg = <0x51>;
+                        };
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index bf86e65dd167..c4b5d7825b9f 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -298,12 +298,22 @@
                 #size-cells = <1>;
                 ranges;
 
+                dma: dma-controller@01c02000 {
+                        compatible = "allwinner,sun4i-a10-dma";
+                        reg = <0x01c02000 0x1000>;
+                        interrupts = <27>;
+                        clocks = <&ahb_gates 6>;
+                        #dma-cells = <2>;
+                };
+
                 spi0: spi@01c05000 {
                         compatible = "allwinner,sun4i-a10-spi";
                         reg = <0x01c05000 0x1000>;
                         interrupts = <10>;
                         clocks = <&ahb_gates 20>, <&spi0_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 27>, <&dma 1 26>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -315,6 +325,8 @@
                         interrupts = <11>;
                         clocks = <&ahb_gates 21>, <&spi1_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 9>, <&dma 1 8>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -376,6 +388,8 @@
                         interrupts = <12>;
                         clocks = <&ahb_gates 22>, <&spi2_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 29>, <&dma 1 28>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -490,7 +504,6 @@
                         reg = <0x01c2ac00 0x400>;
                         interrupts = <7>;
                         clocks = <&apb1_gates 0>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -501,7 +514,6 @@
                         reg = <0x01c2b000 0x400>;
                         interrupts = <8>;
                         clocks = <&apb1_gates 1>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -512,7 +524,6 @@
                         reg = <0x01c2b400 0x400>;
                         interrupts = <9>;
                         clocks = <&apb1_gates 2>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 44b07e512c24..543f895d18d3 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /include/ "skeleton.dtsi"
@@ -657,9 +693,10 @@
                         reg = <0x01c2ac00 0x400>;
                         interrupts = <0 6 4>;
                         clocks = <&apb2_gates 0>;
-                        clock-frequency = <100000>;
                         resets = <&apb2_rst 0>;
                         status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
                 i2c1: i2c@01c2b000 {
@@ -667,9 +704,10 @@
                         reg = <0x01c2b000 0x400>;
                         interrupts = <0 7 4>;
                         clocks = <&apb2_gates 1>;
-                        clock-frequency = <100000>;
                         resets = <&apb2_rst 1>;
                         status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
                 i2c2: i2c@01c2b400 {
@@ -677,9 +715,10 @@
                         reg = <0x01c2b400 0x400>;
                         interrupts = <0 8 4>;
                         clocks = <&apb2_gates 2>;
-                        clock-frequency = <100000>;
                         resets = <&apb2_rst 2>;
                         status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
                 i2c3: i2c@01c2b800 {
@@ -687,9 +726,10 @@
                         reg = <0x01c2b800 0x400>;
                         interrupts = <0 9 4>;
                         clocks = <&apb2_gates 3>;
-                        clock-frequency = <100000>;
                         resets = <&apb2_rst 3>;
                         status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
                 gmac: ethernet@01c30000 {
@@ -779,6 +819,12 @@
                         interrupts = <1 9 0xf04>;
                 };
 
+                rtc: rtc@01f00000 {
+                        compatible = "allwinner,sun6i-a31-rtc";
+                        reg = <0x01f00000 0x54>;
+                        interrupts = <0 40 4>, <0 41 4>;
+                };
+
                 nmi_intc: interrupt-controller@01f00c0c {
                         compatible = "allwinner,sun6i-a31-sc-nmi";
                         interrupt-controller;
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
new file mode 100644
index 000000000000..0e4bfa3b2b85
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2013 Wills Wang
+ *
+ * Wills Wang <wills.wang.open@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+
+/ {
+        model = "Merrii A20 Hummingbird";
+        compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v0>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+
+                mmc3: mmc@01c12000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc3_pins_a>;
+                        vmmc-supply = <&reg_mmc3_vdd>;
+                        bus-width = <4>;
+                        non-removable;
+                        status = "okay";
+                };
+
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+
+                pio: pinctrl@01c20800 {
+                        ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
+                                allwinner,pins = "PH15";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
+                                allwinner,pins = "PH9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
+                                allwinner,pins = "PH16";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                pwm: pwm@01c20e00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pwm0_pins_a>;
+                        status = "okay";
+                };
+
+                ir0: ir@01c21800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ir0_pins_a>;
+                        status = "okay";
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                uart2: serial@01c28800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart2_pins_a>;
+                        status = "okay";
+                };
+
+                uart3: serial@01c28c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart3_pins_a>;
+                        status = "okay";
+                };
+
+                uart4: serial@01c29000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart4_pins_a>;
+                        status = "okay";
+                };
+
+                uart5: serial@01c29400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart5_pins_a>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
+
+                i2c3: i2c@01c2b800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c3_pins_a>;
+                        status = "okay";
+                };
+
+                spi2: spi@01c17000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi2_pins_b>;
+                        status = "okay";
+                };
+
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_rgmii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "rgmii";
+                        phy-supply = <&reg_gmac_vdd>;
+                        /* phy reset config */
+                        snps,reset-gpio = <&pio 0 17 0>; /* PA17 */
+                        snps,reset-active-low;
+                        /* wait 1s after reset, otherwise fail to read phy id */
+                        snps,reset-delays-us = <0 10000 1000000>;
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+
+        reg_ahci_5v: ahci-5v {
+                pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>;
+                gpio = <&pio 7 15 0>; /* PH15 */
+                status = "okay";
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>;
+                gpio = <&pio 7 2 0>; /* PH2 */
+                status = "okay";
+        };
+
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+
+        reg_mmc3_vdd: mmc3_vdd {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>;
+                regulator-name = "mmc3_vdd";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+                enable-active-high;
+                gpio = <&pio 7 9 0>; /* PH9 */
+        };
+
+        reg_gmac_vdd: gmac_vdd {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>;
+                regulator-name = "gmac_vdd";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+                enable-active-high;
+                gpio = <&pio 7 16 0>; /* PH16 */
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
new file mode 100644
index 000000000000..1eb8175959a6
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -0,0 +1,137 @@
+/*
+ * This is based on sun4i-a10-olinuxino-lime.dts
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+
+/ {
+        model = "Olimex A20-OLinuXino-LIME";
+        compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+
+                pinctrl@01c20800 {
+                        ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
+                                allwinner,pins = "PC3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        led_pins_olinuxinolime: led_pins@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                };
+
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxinolime>;
+
+                green {
+                        label = "a20-olinuxino-lime:green:usr";
+                        gpios = <&pio 7 2 0>;
+                        default-state = "on";
+                };
+        };
+
+        reg_ahci_5v: ahci-5v {
+                pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
+                gpio = <&pio 2 3 0>;
+                status = "okay";
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4011628c7381..a96b99465069 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /include/ "skeleton.dtsi"
@@ -423,12 +459,22 @@
                         interrupts = <0 0 4>;
                 };
 
+                dma: dma-controller@01c02000 {
+                        compatible = "allwinner,sun4i-a10-dma";
+                        reg = <0x01c02000 0x1000>;
+                        interrupts = <0 27 4>;
+                        clocks = <&ahb_gates 6>;
+                        #dma-cells = <2>;
+                };
+
                 spi0: spi@01c05000 {
                         compatible = "allwinner,sun4i-a10-spi";
                         reg = <0x01c05000 0x1000>;
                         interrupts = <0 10 4>;
                         clocks = <&ahb_gates 20>, <&spi0_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 27>, <&dma 1 26>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -440,6 +486,8 @@
                         interrupts = <0 11 4>;
                         clocks = <&ahb_gates 21>, <&spi1_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 9>, <&dma 1 8>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -535,6 +583,8 @@
                         interrupts = <0 12 4>;
                         clocks = <&ahb_gates 22>, <&spi2_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 29>, <&dma 1 28>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -574,6 +624,8 @@
                         interrupts = <0 50 4>;
                         clocks = <&ahb_gates 23>, <&spi3_clk>;
                         clock-names = "ahb", "mod";
+                        dmas = <&dma 1 31>, <&dma 1 30>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -618,6 +670,27 @@
                                 allwinner,pull = <0>;
                         };
 
+                        uart3_pins_a: uart3@0 {
+                                allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart4_pins_a: uart4@0 {
+                                allwinner,pins = "PG10", "PG11";
+                                allwinner,function = "uart4";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart5_pins_a: uart5@0 {
+                                allwinner,pins = "PI10", "PI11";
+                                allwinner,function = "uart5";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
                         uart6_pins_a: uart6@0 {
                                 allwinner,pins = "PI12", "PI13";
                                 allwinner,function = "uart6";
@@ -653,6 +726,13 @@
                                 allwinner,pull = <0>;
                         };
 
+                        i2c3_pins_a: i2c3@0 {
+                                allwinner,pins = "PI0", "PI1";
+                                allwinner,function = "i2c3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
                         emac_pins_a: emac0@0 {
                                 allwinner,pins = "PA0", "PA1", "PA2",
                                                 "PA3", "PA4", "PA5", "PA6",
@@ -718,6 +798,13 @@
                                 allwinner,pull = <0>;
                         };
 
+                        spi2_pins_b: spi2@1 {
+                                allwinner,pins = "PB14", "PB15", "PB16", "PB17";
+                                allwinner,function = "spi2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
                         mmc0_pins_a: mmc0@0 {
                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
                                 allwinner,function = "mmc0";
@@ -899,7 +986,6 @@
                         reg = <0x01c2ac00 0x400>;
                         interrupts = <0 7 4>;
                         clocks = <&apb1_gates 0>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -910,7 +996,6 @@
                         reg = <0x01c2b000 0x400>;
                         interrupts = <0 8 4>;
                         clocks = <&apb1_gates 1>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -921,7 +1006,6 @@
                         reg = <0x01c2b400 0x400>;
                         interrupts = <0 9 4>;
                         clocks = <&apb1_gates 2>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -932,7 +1016,6 @@
                         reg = <0x01c2b800 0x400>;
                         interrupts = <0 88 4>;
                         clocks = <&apb1_gates 3>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -943,7 +1026,6 @@
                         reg = <0x01c2c000 0x400>;
                         interrupts = <0 89 4>;
                         clocks = <&apb1_gates 15>;
-                        clock-frequency = <100000>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index 34002e3eba9d..e9b8cca8dcc1 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -13,6 +13,7 @@
 
 /dts-v1/;
 /include/ "sun8i-a23.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 
 / {
         model = "Ippo Q8H Dual Core Tablet (v5)";
@@ -23,7 +24,47 @@
         };
 
         soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
+                        vmmc-supply = <&reg_vcc3v0>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 1 4 0>; /* PB4 */
+                        cd-inverted;
+                        status = "okay";
+                };
+
+                pinctrl@01c20800 {
+                        mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
+                                allwinner,pins = "PB4";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        /* pull-ups and devices require PMIC regulator */
+                        status = "failed";
+                };
+
                 r_uart: serial@01f02800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&r_uart_pins_a>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 54ac0787216a..6146ef15efbe 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -3,12 +3,48 @@
  *
  * Chen-Yu Tsai <wens@csie.org>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /include/ "skeleton.dtsi"
@@ -179,6 +215,30 @@
                                         "apb2_uart1", "apb2_uart2",
                                         "apb2_uart3", "apb2_uart4";
                 };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "mmc2";
+                };
         };
 
         soc@01c00000 {
@@ -187,6 +247,104 @@
                 #size-cells = <1>;
                 ranges;
 
+                dma: dma-controller@01c02000 {
+                        compatible = "allwinner,sun8i-a23-dma";
+                        reg = <0x01c02000 0x1000>;
+                        interrupts = <0 50 4>;
+                        clocks = <&ahb1_gates 6>;
+                        resets = <&ahb1_rst 6>;
+                        #dma-cells = <1>;
+                };
+
+                mmc0: mmc@01c0f000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c0f000 0x1000>;
+                        clocks = <&ahb1_gates 8>, <&mmc0_clk>;
+                        clock-names = "ahb", "mmc";
+                        resets = <&ahb1_rst 8>;
+                        reset-names = "ahb";
+                        interrupts = <0 60 4>;
+                        status = "disabled";
+                };
+
+                mmc1: mmc@01c10000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c10000 0x1000>;
+                        clocks = <&ahb1_gates 9>, <&mmc1_clk>;
+                        clock-names = "ahb", "mmc";
+                        resets = <&ahb1_rst 9>;
+                        reset-names = "ahb";
+                        interrupts = <0 61 4>;
+                        status = "disabled";
+                };
+
+                mmc2: mmc@01c11000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c11000 0x1000>;
+                        clocks = <&ahb1_gates 10>, <&mmc2_clk>;
+                        clock-names = "ahb", "mmc";
+                        resets = <&ahb1_rst 10>;
+                        reset-names = "ahb";
+                        interrupts = <0 62 4>;
+                        status = "disabled";
+                };
+
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun8i-a23-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <0 11 4>,
+                                     <0 15 4>,
+                                     <0 17 4>;
+                        clocks = <&apb1_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PF2", "PF4";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+                                allwinner,function = "mmc0";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
+
+                        mmc1_pins_a: mmc1@0 {
+                                allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
+                                allwinner,function = "mmc1";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PH2", "PH3";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PH4", "PH5";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PE12", "PE13";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
                 ahb1_rst: reset@01c202c0 {
                         #reset-cells = <1>;
                         compatible = "allwinner,sun6i-a31-clock-reset";
@@ -227,6 +385,8 @@
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 16>;
                         resets = <&apb2_rst 16>;
+                        dmas = <&dma 6>, <&dma 6>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
 
@@ -238,6 +398,8 @@
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 17>;
                         resets = <&apb2_rst 17>;
+                        dmas = <&dma 7>, <&dma 7>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
 
@@ -249,6 +411,8 @@
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 18>;
                         resets = <&apb2_rst 18>;
+                        dmas = <&dma 8>, <&dma 8>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
 
@@ -260,6 +424,8 @@
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 19>;
                         resets = <&apb2_rst 19>;
+                        dmas = <&dma 9>, <&dma 9>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
 
@@ -271,9 +437,44 @@
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 20>;
                         resets = <&apb2_rst 20>;
+                        dmas = <&dma 10>, <&dma 10>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
 
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <0 6 4>;
+                        clocks = <&apb2_gates 0>;
+                        resets = <&apb2_rst 0>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <0 7 4>;
+                        clocks = <&apb2_gates 1>;
+                        resets = <&apb2_rst 1>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <0 8 4>;
+                        clocks = <&apb2_gates 2>;
+                        resets = <&apb2_rst 2>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 gic: interrupt-controller@01c81000 {
                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
                         reg = <0x01c81000 0x1000>,
@@ -285,6 +486,12 @@
                         interrupts = <1 9 0xf04>;
                 };
 
+                rtc: rtc@01f00000 {
+                        compatible = "allwinner,sun6i-a31-rtc";
+                        reg = <0x01f00000 0x54>;
+                        interrupts = <0 40 4>, <0 41 4>;
+                };
+
                 prcm@01f01400 {
                         compatible = "allwinner,sun8i-a23-prcm";
                         reg = <0x01f01400 0x200>;
@@ -339,5 +546,25 @@
                         resets = <&apb0_rst 4>;
                         status = "disabled";
                 };
+
+                r_pio: pinctrl@01f02c00 {
+                        compatible = "allwinner,sun8i-a23-r-pinctrl";
+                        reg = <0x01f02c00 0x400>;
+                        interrupts = <0 45 4>;
+                        clocks = <&apb0_gates 0>;
+                        resets = <&apb0_rst 0>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        r_uart_pins_a: r_uart@0 {
+                                allwinner,pins = "PL2", "PL3";
+                                allwinner,function = "s_uart";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index 3d021efd1a38..c9c5b10e03eb 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -86,4 +86,11 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
         };
+
+        reg_vcc5v0: vcc5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc5v0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 80b8eddb4105..2ca9c1807f72 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -157,6 +157,11 @@
                 #reset-cells = <1>;
         };
 
+        flow-controller@60007000 {
+                compatible = "nvidia,tegra114-flowctrl";
+                reg = <0x60007000 0x1000>;
+        };
+
         apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra114-apbdma";
                 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 624b0fba2d0a..029c9a021541 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -16,6 +16,26 @@
                 reg = <0x0 0x80000000 0x0 0x80000000>;
         };
 
+        pcie-controller@0,01003000 {
+                status = "okay";
+
+                avddio-pex-supply = <&vdd_1v05_run>;
+                dvddio-pex-supply = <&vdd_1v05_run>;
+                avdd-pex-pll-supply = <&vdd_1v05_run>;
+                hvdd-pex-supply = <&vdd_3v3_lp0>;
+                hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+                vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
+                avdd-pll-erefe-supply = <&avdd_1v05_run>;
+
+                pci@1,0 {
+                        status = "okay";
+                };
+
+                pci@2,0 {
+                        status = "okay";
+                };
+        };
+
         host1x@0,50000000 {
                 hdmi@0,54280000 {
                         status = "okay";
@@ -31,10 +51,10 @@
         };
 
         pinmux: pinmux@0,70000868 {
-                pinctrl-names = "default";
-                pinctrl-0 = <&state_default>;
+                pinctrl-names = "boot";
+                pinctrl-0 = <&state_boot>;
 
-                state_default: pinmux {
+                state_boot: pinmux {
                         clk_32k_out_pa0 {
                                 nvidia,pins = "clk_32k_out_pa0";
                                 nvidia,function = "soc";
@@ -1231,6 +1251,41 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "pe0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "pe0";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "pe";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "pe1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "pe1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
                         clk3_out_pee0 {
                                 nvidia,pins = "clk3_out_pee0";
                                 nvidia,function = "extperiph3";
@@ -1515,7 +1570,7 @@
                                         regulator-always-on;
                                 };
 
-                                ldo0 {
+                                avdd_1v05_run: ldo0 {
                                         regulator-name = "+1.05V_RUN_AVDD";
                                         regulator-min-microvolt = <1050000>;
                                         regulator-max-microvolt = <1050000>;
@@ -1619,6 +1674,18 @@
                 nvidia,sys-clock-req-active-high;
         };
 
+        /* Serial ATA */
+        sata@0,70020000 {
+                status = "okay";
+
+                hvdd-supply = <&vdd_3v3_lp0>;
+                vddio-supply = <&vdd_1v05_run>;
+                avdd-supply = <&vdd_1v05_run>;
+
+                target-5v-supply = <&vdd_5v0_sata>;
+                target-12v-supply = <&vdd_12v0_sata>;
+        };
+
         padctl@0,7009f000 {
                 pinctrl-0 = <&padctl_default>;
                 pinctrl-names = "default";
@@ -1828,6 +1895,29 @@
                         enable-active-high;
                         vin-supply = <&vdd_5v0_sys>;
                 };
+
+                /* Molex power connector */
+                vdd_5v0_sata: regulator@13 {
+                        compatible = "regulator-fixed";
+                        reg = <13>;
+                        regulator-name = "+5V_SATA";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+
+                vdd_12v0_sata: regulator@14 {
+                        compatible = "regulator-fixed";
+                        reg = <14>;
+                        regulator-name = "+12V_SATA";
+                        regulator-min-microvolt = <12000000>;
+                        regulator-max-microvolt = <12000000>;
+                        gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_mux>;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
new file mode 100644
index 000000000000..7d0784ce4c74
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -0,0 +1,1136 @@
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+        model = "Acer Chromebook 13 CB5-311";
+        compatible = "google,nyan-big", "nvidia,tegra124";
+
+        aliases {
+                rtc0 = "/i2c@0,7000d000/pmic@40";
+                rtc1 = "/rtc@0,7000e000";
+        };
+
+        memory {
+                reg = <0x0 0x80000000 0x0 0x80000000>;
+        };
+
+        host1x@0,50000000 {
+                hdmi@0,54280000 {
+                        status = "okay";
+
+                        vdd-supply = <&vdd_3v3_hdmi>;
+                        pll-supply = <&vdd_hdmi_pll>;
+                        hdmi-supply = <&vdd_5v0_hdmi>;
+
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+
+                sor@0,54540000 {
+                        status = "okay";
+
+                        nvidia,dpaux = <&dpaux>;
+                        nvidia,panel = <&panel>;
+                };
+
+                dpaux@0,545c0000 {
+                        vdd-supply = <&vdd_3v3_panel>;
+                        status = "okay";
+                };
+        };
+
+        pinmux@0,70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinmux_default>;
+
+                pinmux_default: common {
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5",
+                                              "dap2_fs_pa2",
+                                              "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0",
+                                              "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0",
+                                              "ulpi_nxt_py2",
+                                              "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1",
+                                              "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5",
+                                              "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg4 {
+                                nvidia,pins = "pg4",
+                                              "pg5",
+                                              "pg6",
+                                              "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0",
+                                              "kb_row15_ps7",
+                                              "clk_32k_out_pa0";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1",
+                                              "sdmmc1_dat0_py7",
+                                              "sdmmc1_dat1_py6",
+                                              "sdmmc1_dat2_py5",
+                                              "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7",
+                                              "sdmmc3_dat0_pb7",
+                                              "sdmmc3_dat1_pb6",
+                                              "sdmmc3_dat2_pb5",
+                                              "sdmmc3_dat3_pb4",
+                                              "kb_col4_pq4",
+                                              "sdmmc3_clk_lb_out_pee4",
+                                              "sdmmc3_clk_lb_in_pee5",
+                                              "sdmmc3_cd_n_pv2";
+                                nvidia,function = "sdmmc3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7",
+                                              "sdmmc4_dat0_paa0",
+                                              "sdmmc4_dat1_paa1",
+                                              "sdmmc4_dat2_paa2",
+                                              "sdmmc4_dat3_paa3",
+                                              "sdmmc4_dat4_paa4",
+                                              "sdmmc4_dat5_paa5",
+                                              "sdmmc4_dat6_paa6",
+                                              "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6",
+                                              "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5",
+                                              "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4",
+                                              "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4",
+                                              "usb_vbus_en1_pn5";
+                                nvidia,function = "usb";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        drive_sdio1 {
+                                nvidia,pins = "drive_sdio1";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull-down-strength = <36>;
+                                nvidia,pull-up-strength = <20>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                        };
+                        drive_sdio3 {
+                                nvidia,pins = "drive_sdio3";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull-down-strength = <22>;
+                                nvidia,pull-up-strength = <36>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                        };
+                        drive_gma {
+                                nvidia,pins = "drive_gma";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull-down-strength = <2>;
+                                nvidia,pull-up-strength = <1>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,drive-type = <1>;
+                        };
+                        codec_irq_l {
+                                nvidia,pins = "ph4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_bl_en {
+                                nvidia,pins = "ph2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        touch_irq_l {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        tpm_davint_l {
+                                nvidia,pins = "ph6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ts_irq_l {
+                                nvidia,pins = "pk2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ts_reset_l {
+                                nvidia,pins = "pk4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ts_shdn_l {
+                                nvidia,pins = "pk1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph7 {
+                                nvidia,pins = "ph7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col0_ap {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lid_open {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        en_vdd_sd {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ac_ok {
+                                nvidia,pins = "pj0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sensor_irq_l {
+                                nvidia,pins = "pi6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        wifi_en {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        en_vdd_bl {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        en_vdd_hdmi {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        soc_warm_reset_l {
+                                nvidia,pins = "pi5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        hp_det_l {
+                                nvidia,pins = "pi7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        mic_det_l {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                };
+        };
+
+        serial@0,70006000 {
+                /* Debug connector on the bottom of the board near SD card. */
+                status = "okay";
+        };
+
+        pwm@0,7000a000 {
+                status = "okay";
+        };
+
+        i2c@0,7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                acodec: audio-codec@10 {
+                        compatible = "maxim,max98090";
+                        reg = <0x10>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                };
+
+                temperature-sensor@4c {
+                        compatible = "ti,tmp451";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+
+                        #thermal-sensor-cells = <1>;
+                };
+        };
+
+        i2c@0,7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@0,7000c500 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                tpm@20 {
+                        compatible = "infineon,slb9645tt";
+                        reg = <0x20>;
+                };
+        };
+
+        hdmi_ddc: i2c@0,7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@0,7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                pmic: pmic@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+                        ams,system-power-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+
+                        as3722_default: pinmux {
+                                gpio0 {
+                                        pins = "gpio0";
+                                        function = "gpio";
+                                        bias-pull-down;
+                                };
+
+                                gpio1 {
+                                        pins = "gpio1";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio2_4_7 {
+                                        pins = "gpio2", "gpio4", "gpio7";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio3_6 {
+                                        pins = "gpio3", "gpio6";
+                                        bias-high-impedance;
+                                };
+
+                                gpio5 {
+                                        pins = "gpio5";
+                                        function = "clk32k-out";
+                                        bias-pull-down;
+                                };
+                        };
+
+                        regulators {
+                                vsup-sd2-supply = <&vdd_5v0_sys>;
+                                vsup-sd3-supply = <&vdd_5v0_sys>;
+                                vsup-sd4-supply = <&vdd_5v0_sys>;
+                                vsup-sd5-supply = <&vdd_5v0_sys>;
+                                vin-ldo0-supply = <&vdd_1v35_lp0>;
+                                vin-ldo1-6-supply = <&vdd_3v3_run>;
+                                vin-ldo2-5-7-supply = <&vddio_1v8>;
+                                vin-ldo3-4-supply = <&vdd_3v3_sys>;
+                                vin-ldo9-10-supply = <&vdd_5v0_sys>;
+                                vin-ldo11-supply = <&vdd_3v3_run>;
+
+                                sd0 {
+                                        regulator-name = "+VDD_CPU_AP";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <2>;
+                                };
+
+                                sd1 {
+                                        regulator-name = "+VDD_CORE";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <4000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                vdd_1v35_lp0: sd2 {
+                                        regulator-name = "+1.35V_LP0(sd2)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd3 {
+                                        regulator-name = "+1.35V_LP0(sd3)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                vdd_1v05_run: sd4 {
+                                        regulator-name = "+1.05V_RUN";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                vddio_1v8: sd5 {
+                                        regulator-name = "+1.8V_VDDIO";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                sd6 {
+                                        regulator-name = "+VDD_GPU_AP";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo0 {
+                                        regulator-name = "+1.05V_RUN_AVDD";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                ldo1 {
+                                        regulator-name = "+1.8V_RUN_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo2 {
+                                        regulator-name = "+1.2V_GEN_AVDD";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo3 {
+                                        regulator-name = "+1.00V_LP0_VDD_RTC";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+
+                                vdd_run_cam: ldo4 {
+                                        regulator-name = "+3.3V_RUN_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo5 {
+                                        regulator-name = "+1.2V_RUN_CAM_FRONT";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                vddio_sdmmc3: ldo6 {
+                                        regulator-name = "+VDDIO_SDMMC3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo7 {
+                                        regulator-name = "+1.05V_RUN_CAM_REAR";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                ldo9 {
+                                        regulator-name = "+2.8V_RUN_TOUCH";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo10 {
+                                        regulator-name = "+2.8V_RUN_CAM_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo11 {
+                                        regulator-name = "+1.8V_RUN_VPP_FUSE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+        };
+
+        spi@0,7000d400 {
+                status = "okay";
+
+                cros_ec: cros-ec@0 {
+                        compatible = "google,cros-ec-spi";
+                        spi-max-frequency = <3000000>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+                        reg = <0>;
+
+                        google,cros-ec-spi-msg-delay = <2000>;
+
+                        i2c-tunnel {
+                                compatible = "google,cros-ec-i2c-tunnel";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                google,remote-bus = <0>;
+
+                                charger: bq24735@9 {
+                                        compatible = "ti,bq24735";
+                                        reg = <0x9>;
+                                        interrupt-parent = <&gpio>;
+                                        interrupts = <TEGRA_GPIO(J, 0)
+                                                        GPIO_ACTIVE_HIGH>;
+                                        ti,ac-detect-gpios = <&gpio
+                                                        TEGRA_GPIO(J, 0)
+                                                        GPIO_ACTIVE_HIGH>;
+                                };
+
+                                battery: sbs-battery@b {
+                                        compatible = "sbs,sbs-battery";
+                                        reg = <0xb>;
+                                        sbs,i2c-retry-count = <2>;
+                                        sbs,poll-retry-count = <10>;
+                                        power-supplies = <&charger>;
+                                };
+                        };
+                };
+        };
+
+        spi@0,7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+
+                flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        reg = <0>;
+                };
+        };
+
+        pmc@0,7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <0>;
+                nvidia,cpu-pwr-good-time = <500>;
+                nvidia,cpu-pwr-off-time = <300>;
+                nvidia,core-pwr-good-time = <641 3845>;
+                nvidia,core-pwr-off-time = <61036>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+        };
+
+        hda@0,70030000 {
+                status = "okay";
+        };
+
+        sdhci@0,700b0000 { /* WiFi/BT on this bus */
+                status = "okay";
+                power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                no-1-8-v;
+                non-removable;
+        };
+
+        sdhci@0,700b0400 { /* SD Card on this bus */
+                status = "okay";
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+                bus-width = <4>;
+                no-1-8-v;
+                vqmmc-supply = <&vddio_sdmmc3>;
+        };
+
+        sdhci@0,700b0600 { /* eMMC on this bus */
+                status = "okay";
+                bus-width = <8>;
+                no-1-8-v;
+                non-removable;
+        };
+
+        ahub@0,70300000 {
+                i2s@0,70301100 {
+                        status = "okay";
+                };
+        };
+
+        usb@0,7d000000 { /* Rear external USB port. */
+                status = "okay";
+        };
+
+        usb-phy@0,7d000000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb1_vbus>;
+        };
+
+        usb@0,7d004000 { /* Internal webcam. */
+                status = "okay";
+        };
+
+        usb-phy@0,7d004000 {
+                status = "okay";
+                vbus-supply = <&vdd_run_cam>;
+        };
+
+        usb@0,7d008000 { /* Left external USB port. */
+                status = "okay";
+        };
+
+        usb-phy@0,7d008000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb3_vbus>;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_led>;
+                pwms = <&pwm 1 1000000>;
+
+                default-brightness-level = <224>;
+                brightness-levels =
+                        <  0   1   2   3   4   5   6   7
+                           8   9  10  11  12  13  14  15
+                          16  17  18  19  20  21  22  23
+                          24  25  26  27  28  29  30  31
+                          32  33  34  35  36  37  38  39
+                          40  41  42  43  44  45  46  47
+                          48  49  50  51  52  53  54  55
+                          56  57  58  59  60  61  62  63
+                          64  65  66  67  68  69  70  71
+                          72  73  74  75  76  77  78  79
+                          80  81  82  83  84  85  86  87
+                          88  89  90  91  92  93  94  95
+                          96  97  98  99 100 101 102 103
+                         104 105 106 107 108 109 110 111
+                         112 113 114 115 116 117 118 119
+                         120 121 122 123 124 125 126 127
+                         128 129 130 131 132 133 134 135
+                         136 137 138 139 140 141 142 143
+                         144 145 146 147 148 149 150 151
+                         152 153 154 155 156 157 158 159
+                         160 161 162 163 164 165 166 167
+                         168 169 170 171 172 173 174 175
+                         176 177 178 179 180 181 182 183
+                         184 185 186 187 188 189 190 191
+                         192 193 194 195 196 197 198 199
+                         200 201 202 203 204 205 206 207
+                         208 209 210 211 212 213 214 215
+                         216 217 218 219 220 221 222 223
+                         224 225 226 227 228 229 230 231
+                         232 233 234 235 236 237 238 239
+                         240 241 242 243 244 245 246 247
+                         248 249 250 251 252 253 254 255
+                         256>;
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                lid {
+                        label = "Lid";
+                        gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+                        linux,input-type = <5>;
+                        linux,code = <KEY_RESERVED>;
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        debounce-interval = <30>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        panel: panel {
+                compatible = "auo,b133xtn01";
+
+                backlight = <&backlight>;
+                ddc-i2c-bus = <&dpaux>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_mux: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "+VDD_MUX";
+                        regulator-min-microvolt = <12000000>;
+                        regulator-max-microvolt = <12000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                vdd_5v0_sys: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "+5V_SYS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+
+                vdd_3v3_sys: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "+3.3V_SYS";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+
+                vdd_3v3_run: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "+3.3V_RUN";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+
+                vdd_3v3_hdmi: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+
+                vdd_led: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "+VDD_LED";
+                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_mux>;
+                };
+
+                vdd_5v0_ts: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "+5V_VDD_TS_SW";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+
+                vdd_usb1_vbus: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "+5V_USB_HS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+
+                vdd_usb3_vbus: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "+5V_USB_SS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+
+                vdd_3v3_panel: regulator@9 {
+                        compatible = "regulator-fixed";
+                        reg = <9>;
+                        regulator-name = "+3.3V_PANEL";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+
+                vdd_3v3_lp0: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "+3.3V_LP0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        /*
+                         * TODO: find a way to wire this up with the USB EHCI
+                         * controllers so that it can be enabled on demand.
+                         */
+                        regulator-always-on;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+
+                vdd_hdmi_pll: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1050000>;
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                        vin-supply = <&vdd_1v05_run>;
+                };
+
+                vdd_5v0_hdmi: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "+5V_HDMI_CON";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-max98090-nyan-big",
+                             "nvidia,tegra-audio-max98090";
+                nvidia,model = "Acer Chromebook 13";
+
+                nvidia,audio-routing =
+                        "Headphones", "HPR",
+                        "Headphones", "HPL",
+                        "Speakers", "SPKR",
+                        "Speakers", "SPKL",
+                        "Mic Jack", "MICBIAS",
+                        "DMICL", "Int Mic",
+                        "DMICR", "Int Mic",
+                        "IN34", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&acodec>;
+
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
+        };
+};
+
+#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 70ad91d1a20b..13008858e967 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -36,17 +36,17 @@
                         nvidia,panel = <&panel>;
                 };
 
-                dpaux: dpaux@0,545c0000 {
+                dpaux@0,545c0000 {
                         vdd-supply = <&vdd_3v3_panel>;
                         status = "okay";
                 };
         };
 
         pinmux: pinmux@0,70000868 {
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinmux_default>;
+                pinctrl-names = "boot";
+                pinctrl-0 = <&pinmux_boot>;
 
-                pinmux_default: common {
+                pinmux_boot: common {
                         dap_mclk1_pw4 {
                                 nvidia,pins = "dap_mclk1_pw4";
                                 nvidia,function = "extperiph1";
@@ -587,7 +587,7 @@
                 status = "okay";
         };
 
-        pwm: pwm@0,7000a000 {
+        pwm@0,7000a000 {
                 status = "okay";
         };
 
@@ -606,6 +606,14 @@
         i2c@0,7000c400 {
                 status = "okay";
                 clock-frequency = <100000>;
+
+                trackpad@4b {
+                        compatible = "atmel,maxtouch";
+                        reg = <0x4b>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
+                        linux,gpio-keymap = <0 0 0 BTN_LEFT>;
+                };
         };
 
         i2c@0,7000c500 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 03916efd6fa9..478c555ebd96 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -12,6 +12,72 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
+        pcie-controller@0,01003000 {
+                compatible = "nvidia,tegra124-pcie";
+                device_type = "pci";
+                reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
+                       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
+                       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+                reg-names = "pads", "afi", "cs";
+                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+                             <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+                interrupt-names = "intr", "msi";
+
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+                bus-range = <0x00 0xff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+
+                ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
+                          0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
+                          0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
+                          0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
+                          0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+
+                clocks = <&tegra_car TEGRA124_CLK_PCIE>,
+                         <&tegra_car TEGRA124_CLK_AFI>,
+                         <&tegra_car TEGRA124_CLK_PLL_E>,
+                         <&tegra_car TEGRA124_CLK_CML0>;
+                clock-names = "pex", "afi", "pll_e", "cml";
+                resets = <&tegra_car 70>,
+                         <&tegra_car 72>,
+                         <&tegra_car 74>;
+                reset-names = "pex", "afi", "pcie_x";
+                status = "disabled";
+
+                phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
+                phy-names = "pcie";
+
+                pci@1,0 {
+                        device_type = "pci";
+                        assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
+                        reg = <0x000800 0 0 0 0>;
+                        status = "disabled";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        ranges;
+
+                        nvidia,num-lanes = <2>;
+                };
+
+                pci@2,0 {
+                        device_type = "pci";
+                        assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
+                        reg = <0x001000 0 0 0 0>;
+                        status = "disabled";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        ranges;
+
+                        nvidia,num-lanes = <1>;
+                };
+        };
+
         host1x@0,50000000 {
                 compatible = "nvidia,tegra124-host1x", "simple-bus";
                 reg = <0x0 0x50000000 0x0 0x00034000>;
@@ -78,7 +144,7 @@
                         status = "disabled";
                 };
 
-                dpaux@0,545c0000 {
+                dpaux: dpaux@0,545c0000 {
                         compatible = "nvidia,tegra124-dpaux";
                         reg = <0x0 0x545c0000 0x0 0x00040000>;
                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@@ -137,6 +203,11 @@
                 #reset-cells = <1>;
         };
 
+        flow-controller@0,60007000 {
+                compatible = "nvidia,tegra124-flowctrl";
+                reg = <0x0 0x60007000 0x0 0x1000>;
+        };
+
         gpio: gpio@0,6000d000 {
                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
                 reg = <0x0 0x6000d000 0x0 0x1000>;
@@ -267,7 +338,7 @@
                 status = "disabled";
         };
 
-        pwm@0,7000a000 {
+        pwm: pwm@0,7000a000 {
                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
                 reg = <0x0 0x7000a000 0x0 0x100>;
                 #pwm-cells = <2>;
@@ -480,6 +551,31 @@
                 reset-names = "fuse";
         };
 
+        sata@0,70020000 {
+                compatible = "nvidia,tegra124-ahci";
+
+                reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
+                        <0x0 0x70020000 0x0 0x7000>; /* SATA */
+
+                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+
+                clocks = <&tegra_car TEGRA124_CLK_SATA>,
+                        <&tegra_car TEGRA124_CLK_SATA_OOB>,
+                        <&tegra_car TEGRA124_CLK_CML1>,
+                        <&tegra_car TEGRA124_CLK_PLL_E>;
+                clock-names = "sata", "sata-oob", "cml1", "pll_e";
+
+                resets = <&tegra_car 124>,
+                        <&tegra_car 123>,
+                        <&tegra_car 129>;
+                reset-names = "sata", "sata-oob", "sata-cold";
+
+                phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
+                phy-names = "sata-phy";
+
+                status = "disabled";
+        };
+
         hda@0,70030000 {
                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
                 reg = <0x0 0x70030000 0x0 0x10000>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 1908f6937e53..3b374c49d04d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -190,6 +190,11 @@
                 #reset-cells = <1>;
         };
 
+        flow-controller@60007000 {
+                compatible = "nvidia,tegra20-flowctrl";
+                reg = <0x60007000 0x1000>;
+        };
+
         apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1200>;
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 8adaa7871dd3..a5446cba9804 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -423,7 +423,7 @@
                         vcc4-supply = <&sys_3v3_reg>;
                         vcc5-supply = <&sys_3v3_reg>;
                         vcc6-supply = <&vio_reg>;
-                        vcc7-supply = <&sys_5v0_reg>;
+                        vcc7-supply = <&charge_pump_5v0_reg>;
                         vccio-supply = <&sys_3v3_reg>;
 
                         regulators {
@@ -674,5 +674,14 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                charge_pump_5v0_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index bf16f8e65627..c4ed1bec4d92 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -201,7 +201,7 @@
                         vcc4-supply = <&sys_3v3_reg>;
                         vcc5-supply = <&sys_3v3_reg>;
                         vcc6-supply = <&vio_reg>;
-                        vcc7-supply = <&sys_5v0_reg>;
+                        vcc7-supply = <&charge_pump_5v0_reg>;
                         vccio-supply = <&sys_3v3_reg>;
 
                         regulators {
@@ -373,5 +373,14 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                charge_pump_5v0_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 6b35c29278d7..aa6ccea13d30 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -272,6 +272,11 @@
                 #reset-cells = <1>;
         };
 
+        flow-controller@60007000 {
+                compatible = "nvidia,tegra30-flowctrl";
+                reg = <0x60007000 0x1000>;
+        };
+
         apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 2e3bd3172b23..55eb35f068fb 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -83,10 +83,6 @@
                 regulator-always-on;
         };
 
-        clk32kg: regulator-clk32kg {
-                compatible = "ti,twl6030-clk32kg";
-        };
-
         twl_usb_comparator: usb-comparator {
                 compatible = "ti,twl6030-usb";
                 interrupts = <4>, <10>;
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 756c986995a3..2efb2058ba49 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -41,7 +41,7 @@
                         bank-width = <4>;
                 };
 
-                vram@2,00000000 {
+                v2m_video_ram: vram@2,00000000 {
                         compatible = "arm,vexpress-vram";
                         reg = <2 0x00000000 0x00800000>;
                 };
@@ -246,9 +246,41 @@
                         clcd@1f0000 {
                                 compatible = "arm,pl111", "arm,primecell";
                                 reg = <0x1f0000 0x1000>;
+                                interrupt-names = "combined";
                                 interrupts = <14>;
                                 clocks = <&v2m_oscclk1>, <&smbclk>;
                                 clock-names = "clcdclk", "apb_pclk";
+                                memory-region = <&v2m_video_ram>;
+                                max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
+
+                                port {
+                                        v2m_clcd_pads: endpoint {
+                                                remote-endpoint = <&v2m_clcd_panel>;
+                                                arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+                                        };
+                                };
+
+                                panel {
+                                        compatible = "panel-dpi";
+
+                                        port {
+                                                v2m_clcd_panel: endpoint {
+                                                        remote-endpoint = <&v2m_clcd_pads>;
+                                                };
+                                        };
+
+                                        panel-timing {
+                                                clock-frequency = <25175000>;
+                                                hactive = <640>;
+                                                hback-porch = <40>;
+                                                hfront-porch = <24>;
+                                                hsync-len = <96>;
+                                                vactive = <480>;
+                                                vback-porch = <32>;
+                                                vfront-porch = <11>;
+                                                vsync-len = <2>;
+                                        };
+                                };
                         };
                 };
 
@@ -350,7 +382,7 @@
                                 /* CLCD clock */
                                 compatible = "arm,vexpress-osc";
                                 arm,vexpress-sysreg,func = <1 1>;
-                                freq-range = <23750000 63500000>;
+                                freq-range = <23750000 65000000>;
                                 #clock-cells = <0>;
                                 clock-output-names = "v2m:oscclk1";
                         };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index ba856d604fb7..cb3090f919a7 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -40,7 +40,7 @@
                         bank-width = <4>;
                 };
 
-                vram@3,00000000 {
+                v2m_video_ram: vram@3,00000000 {
                         compatible = "arm,vexpress-vram";
                         reg = <3 0x00000000 0x00800000>;
                 };
@@ -245,9 +245,41 @@
                         clcd@1f000 {
                                 compatible = "arm,pl111", "arm,primecell";
                                 reg = <0x1f000 0x1000>;
+                                interrupt-names = "combined";
                                 interrupts = <14>;
                                 clocks = <&v2m_oscclk1>, <&smbclk>;
                                 clock-names = "clcdclk", "apb_pclk";
+                                memory-region = <&v2m_video_ram>;
+                                max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
+
+                                port {
+                                        v2m_clcd_pads: endpoint {
+                                                remote-endpoint = <&v2m_clcd_panel>;
+                                                arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+                                        };
+                                };
+
+                                panel {
+                                        compatible = "panel-dpi";
+
+                                        port {
+                                                v2m_clcd_panel: endpoint {
+                                                        remote-endpoint = <&v2m_clcd_pads>;
+                                                };
+                                        };
+
+                                        panel-timing {
+                                                clock-frequency = <25175000>;
+                                                hactive = <640>;
+                                                hback-porch = <40>;
+                                                hfront-porch = <24>;
+                                                hsync-len = <96>;
+                                                vactive = <480>;
+                                                vback-porch = <32>;
+                                                vfront-porch = <11>;
+                                                vsync-len = <2>;
+                                        };
+                                };
                         };
                 };
 
@@ -349,7 +381,7 @@
                                 /* CLCD clock */
                                 compatible = "arm,vexpress-osc";
                                 arm,vexpress-sysreg,func = <1 1>;
-                                freq-range = <23750000 63500000>;
+                                freq-range = <23750000 65000000>;
                                 #clock-cells = <0>;
                                 clock-output-names = "v2m:oscclk1";
                         };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index a25c262326dc..322fd1519b09 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -38,6 +38,7 @@
                         compatible = "arm,cortex-a15";
                         reg = <0>;
                         cci-control-port = <&cci_control1>;
+                        cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
                 };
 
                 cpu1: cpu@1 {
@@ -45,6 +46,7 @@
                         compatible = "arm,cortex-a15";
                         reg = <1>;
                         cci-control-port = <&cci_control1>;
+                        cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
                 };
 
                 cpu2: cpu@2 {
@@ -52,6 +54,7 @@
                         compatible = "arm,cortex-a7";
                         reg = <0x100>;
                         cci-control-port = <&cci_control2>;
+                        cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
                 };
 
                 cpu3: cpu@3 {
@@ -59,6 +62,7 @@
                         compatible = "arm,cortex-a7";
                         reg = <0x101>;
                         cci-control-port = <&cci_control2>;
+                        cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
                 };
 
                 cpu4: cpu@4 {
@@ -66,6 +70,25 @@
                         compatible = "arm,cortex-a7";
                         reg = <0x102>;
                         cci-control-port = <&cci_control2>;
+                        cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
+                };
+
+                idle-states {
+                        CLUSTER_SLEEP_BIG: cluster-sleep-big {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                entry-latency-us = <1000>;
+                                exit-latency-us = <700>;
+                                min-residency-us = <2000>;
+                        };
+
+                        CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                entry-latency-us = <1000>;
+                                exit-latency-us = <500>;
+                                min-residency-us = <2500>;
+                        };
                 };
         };
 
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 62d9b225dcce..23662b5a5e9d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -70,9 +70,40 @@
         clcd@10020000 {
                 compatible = "arm,pl111", "arm,primecell";
                 reg = <0x10020000 0x1000>;
+                interrupt-names = "combined";
                 interrupts = <0 44 4>;
                 clocks = <&oscclk1>, <&oscclk2>;
                 clock-names = "clcdclk", "apb_pclk";
+                max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
+
+                port {
+                        clcd_pads: endpoint {
+                                remote-endpoint = <&clcd_panel>;
+                                arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+                        };
+                };
+
+                panel {
+                        compatible = "panel-dpi";
+
+                        port {
+                                clcd_panel: endpoint {
+                                        remote-endpoint = <&clcd_pads>;
+                                };
+                        };
+
+                        panel-timing {
+                                clock-frequency = <63500127>;
+                                hactive = <1024>;
+                                hback-porch = <152>;
+                                hfront-porch = <48>;
+                                hsync-len = <104>;
+                                vactive = <768>;
+                                vback-porch = <23>;
+                                vfront-porch = <3>;
+                                vsync-len = <4>;
+                        };
+                };
         };
 
         memory-controller@100e0000 {
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7fb306679341
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf610-colibri.dtsi"
+
+/ {
+        model = "Toradex Colibri VF61 on Colibri Evaluation Board";
+        compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
+
+        chosen {
+                bootargs = "console=ttyLP0,115200";
+        };
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dtsi
index aecc7dbc65e8..0cd83434b073 100644
--- a/arch/arm/boot/dts/vf610-colibri.dts
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -7,16 +7,11 @@
  * (at your option) any later version.
  */
 
-/dts-v1/;
 #include "vf610.dtsi"
 
 / {
         model = "Toradex Colibri VF61 COM";
-        compatible = "toradex,vf610-colibri", "fsl,vf610";
-
-        chosen {
-                bootargs = "console=ttyLP0,115200";
-        };
+        compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
 
         memory {
                 reg = <0x80000000 0x10000000>;
@@ -36,14 +31,12 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc1>;
         bus-width = <4>;
-        status = "okay";
 };
 
 &fec1 {
         phy-mode = "rmii";
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_fec1>;
-        status = "okay";
 };
 
 &L2 {
@@ -54,25 +47,32 @@
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart0>;
-        status = "okay";
 };
 
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
+};
+
+&usbdev0 {
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        disable-over-current;
         status = "okay";
 };
 
 &iomuxc {
         vf610-colibri {
                 pinctrl_esdhc1: esdhc1grp {
-                        fsl,fsl,pins = <
+                        fsl,pins = <
                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 11d733406c7e..189b6975fe7d 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -76,7 +76,6 @@
 
                 simple-audio-card,cpu {
                         sound-dai = <&sai2>;
-                        master-clkdir-out;
                         frame-master;
                         bitclock-master;
                 };
@@ -168,7 +167,7 @@
                 };
 
                 pinctrl_esdhc1: esdhc1grp {
-                        fsl,fsl,pins = <
+                        fsl,pins = <
                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
@@ -221,8 +220,6 @@
                                 VF610_PAD_PTB1__FTM0_CH1                0x1582
                                 VF610_PAD_PTB2__FTM0_CH2                0x1582
                                 VF610_PAD_PTB3__FTM0_CH3                0x1582
-                                VF610_PAD_PTB6__FTM0_CH6                0x1582
-                                VF610_PAD_PTB7__FTM0_CH7                0x1582
                         >;
                 };
 
@@ -244,6 +241,13 @@
                                 VF610_PAD_PTB5__UART1_RX                0x21a1
                         >;
                 };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB6__UART2_TX                0x21a2
+                                VF610_PAD_PTB7__UART2_RX                0x21a1
+                        >;
+                };
         };
 };
 
@@ -265,3 +269,19 @@
         pinctrl-0 = <&pinctrl_uart1>;
         status = "okay";
 };
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&usbdev0 {
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        disable-over-current;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 583dd363c9dc..4d2ec32de96f 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -27,6 +27,8 @@
                 gpio2 = &gpio3;
                 gpio3 = &gpio4;
                 gpio4 = &gpio5;
+                usbphy0 = &usbphy0;
+                usbphy1 = &usbphy1;
         };
 
         cpus {
@@ -297,9 +299,25 @@
                                 gpio-ranges = <&iomuxc 0 128 7>;
                         };
 
-                        anatop@40050000 {
-                                compatible = "fsl,vf610-anatop";
-                                reg = <0x40050000 0x1000>;
+                        anatop: anatop@40050000 {
+                                compatible = "fsl,vf610-anatop", "syscon";
+                                reg = <0x40050000 0x400>;
+                        };
+
+                        usbphy0: usbphy@40050800 {
+                                compatible = "fsl,vf610-usbphy";
+                                reg = <0x40050800 0x400>;
+                                interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_USBPHY0>;
+                                fsl,anatop = <&anatop>;
+                        };
+
+                        usbphy1: usbphy@40050c00 {
+                                compatible = "fsl,vf610-usbphy";
+                                reg = <0x40050c00 0x400>;
+                                interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_USBPHY1>;
+                                fsl,anatop = <&anatop>;
                         };
 
                         i2c0: i2c@40066000 {
@@ -321,6 +339,24 @@
                                 reg = <0x4006b000 0x1000>;
                                 #clock-cells = <1>;
                         };
+
+                        usbdev0: usb@40034000 {
+                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
+                                reg = <0x40034000 0x800>;
+                                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_USBC0>;
+                                fsl,usbphy = <&usbphy0>;
+                                fsl,usbmisc = <&usbmisc0 0>;
+                                dr_mode = "peripheral";
+                                status = "disabled";
+                        };
+
+                        usbmisc0: usb@40034800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,vf610-usbmisc";
+                                reg = <0x40034800 0x200>;
+                                clocks = <&clks VF610_CLK_USBC0>;
+                        };
                 };
 
                 aips1: aips-bus@40080000 {
@@ -383,6 +419,24 @@
                                 status = "disabled";
                         };
 
+                        usbh1: usb@400b4000 {
+                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
+                                reg = <0x400b4000 0x800>;
+                                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_USBC1>;
+                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc1 0>;
+                                dr_mode = "host";
+                                status = "disabled";
+                        };
+
+                        usbmisc1: usb@400b4800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,vf610-usbmisc";
+                                reg = <0x400b4800 0x200>;
+                                clocks = <&clks VF610_CLK_USBC1>;
+                        };
+
                         ftm: ftm@400b8000 {
                                 compatible = "fsl,ftm-timer";
                                 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6cc83d4c6c76..24036c440440 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -146,6 +146,11 @@
                         cache-level = <2>;
                 };
 
+                memory-controller@f8006000 {
+                        compatible = "xlnx,zynq-ddrc-a05";
+                        reg = <0xf8006000 0x1000>;
+                } ;
+
                 uart0: serial@e0000000 {
                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
                         status = "disabled";
@@ -195,6 +200,8 @@
                         interrupts = <0 22 4>;
                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
                         clock-names = "pclk", "hclk", "tx_clk";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
                 gem1: ethernet@e000c000 {
@@ -204,6 +211,8 @@
                         interrupts = <0 45 4>;
                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
                         clock-names = "pclk", "hclk", "tx_clk";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
                 sdhci0: sdhci@e0100000 {
@@ -214,7 +223,7 @@
                         interrupt-parent = <&intc>;
                         interrupts = <0 24 4>;
                         reg = <0xe0100000 0x1000>;
-                } ;
+                };
 
                 sdhci1: sdhci@e0101000 {
                         compatible = "arasan,sdhci-8.9a";
@@ -224,7 +233,7 @@
                         interrupt-parent = <&intc>;
                         interrupts = <0 47 4>;
                         reg = <0xe0101000 0x1000>;
-                } ;
+                };
 
                 slcr: slcr@f8000000 {
                         #address-cells = <1>;
@@ -256,6 +265,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0xf8003000 0x1000>;
                         interrupt-parent = <&intc>;
+                        interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
+                                "dma4", "dma5", "dma6", "dma7";
                         interrupts = <0 13 4>,
                                      <0 14 4>, <0 15 4>,
                                      <0 16 4>, <0 17 4>,
@@ -271,7 +282,7 @@
                 devcfg: devcfg@f8007000 {
                         compatible = "xlnx,zynq-devcfg-1.0";
                         reg = <0xf8007000 0x100>;
-                } ;
+                };
 
                 global_timer: timer@f8f00200 {
                         compatible = "arm,cortex-a9-global-timer";
@@ -303,6 +314,6 @@
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xf8f00600 0x20>;
                         clocks = <&clkc 4>;
-                } ;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 41afd9da6876..e1f51ca127fe 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -25,7 +25,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0 0x40000000>;
+                reg = <0x0 0x40000000>;
         };
 
         chosen {
@@ -38,8 +38,6 @@
         status = "okay";
         phy-mode = "rgmii-id";
         phy-handle = <&ethernet_phy>;
-        #address-cells = <1>;
-        #size-cells = <0>;
 
         ethernet_phy: ethernet-phy@0 {
                 /* Marvell 88E1318 */
@@ -53,6 +51,29 @@
 
 &i2c0 {
         status = "okay";
+
+        isl9305: isl9305@68 {
+                compatible = "isl,isl9305";
+                reg = <0x68>;
+
+                regulators {
+                        dcd1 {
+                                regulator-name = "VDD_DSP";
+                                regulator-always-on;
+                        };
+                        dcd2 {
+                                regulator-name = "1P35V";
+                                regulator-always-on;
+                        };
+                        ldo1 {
+                                regulator-name = "VDD_ADJ";
+                        };
+                        ldo2 {
+                                regulator-name = "VDD_GPIO";
+                                regulator-always-on;
+                        };
+                };
+        };
 };
 
 &sdhci1 {
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 835c3089c61c..94e2cda6f9b6 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2011 - 2014 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
  *
  * This software is licensed under the terms of the GNU General Public
@@ -27,6 +27,15 @@
                 bootargs = "console=ttyPS0,115200 earlyprintk";
         };
 
+        leds {
+                compatible = "gpio-leds";
+
+                ds23 {
+                        label = "ds23";
+                        gpios = <&gpio0 10 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
 };
 
 &can0 {
@@ -35,7 +44,12 @@
 
 &gem0 {
         status = "okay";
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@7 {
+                reg = <7>;
+        };
 };
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 4cc9913078cd..a8bbdfbc7093 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -1,7 +1,6 @@
 /*
- *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2011 - 2014 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *  Copyright (C) 2013 Xilinx
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -21,7 +20,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0 0x40000000>;
+                reg = <0x0 0x40000000>;
         };
 
         chosen {
@@ -32,7 +31,12 @@
 
 &gem0 {
         status = "okay";
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@7 {
+                reg = <7>;
+        };
 };
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 82d7ef1a9a9c..697779a353ed 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -1,7 +1,6 @@
 /*
- *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2011 - 2014 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *  Copyright (C) 2013 Xilinx
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -17,11 +16,11 @@
 
 / {
         model = "Zynq Zed Development Board";
-        compatible = "xlnx,zynq-7000";
+        compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
 
         memory {
                 device_type = "memory";
-                reg = <0 0x20000000>;
+                reg = <0x0 0x20000000>;
         };
 
         chosen {
@@ -32,7 +31,12 @@
 
 &gem0 {
         status = "okay";
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
 &sdhci0 {
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 88099175fc56..d86771abbf57 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1443,14 +1443,14 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
 EXPORT_SYMBOL(edma_assign_channel_eventq);
 
 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
-                              struct edma *edma_cc)
+                              struct edma *edma_cc, int cc_id)
 {
         int i;
         u32 value, cccfg;
         s8 (*queue_priority_map)[2];
 
         /* Decode the eDMA3 configuration from CCCFG register */
-        cccfg = edma_read(0, EDMA_CCCFG);
+        cccfg = edma_read(cc_id, EDMA_CCCFG);
 
         value = GET_NUM_REGN(cccfg);
         edma_cc->num_region = BIT(value);
@@ -1464,7 +1464,8 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
         value = GET_NUM_EVQUE(cccfg);
         edma_cc->num_tc = value + 1;
 
-        dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
+        dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
+                cccfg);
         dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
         dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
         dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
@@ -1684,7 +1685,7 @@ static int edma_probe(struct platform_device *pdev)
                         return -ENOMEM;
 
                 /* Get eDMA3 configuration from IP */
-                ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
+                ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
                 if (ret)
                         return ret;
 
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index a20fa80776d3..45f4c21e393c 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -243,18 +243,12 @@ err_ioremap:
 static int scoop_remove(struct platform_device *pdev)
 {
         struct scoop_dev *sdev = platform_get_drvdata(pdev);
-        int ret;
 
         if (!sdev)
                 return -EINVAL;
 
-        if (sdev->gpio.base != -1) {
-                ret = gpiochip_remove(&sdev->gpio);
-                if (ret) {
-                        dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret);
-                        return ret;
-                }
-        }
+        if (sdev->gpio.base != -1)
+                gpiochip_remove(&sdev->gpio);
 
         platform_set_drvdata(pdev, NULL);
         iounmap(sdev->base);
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index bb396c0e5fda..b54b28fc5a70 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -12,7 +12,6 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
 CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A73A4=y
 CONFIG_MACH_APE6EVM=y
@@ -64,6 +63,8 @@ CONFIG_SERIAL_NONSTANDARD=y
 CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=12
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_I2C_SH_MOBILE=y
 CONFIG_GPIO_SH_PFC=y
 CONFIG_GPIOLIB=y
 # CONFIG_HWMON is not set
@@ -72,11 +73,17 @@ CONFIG_RCAR_THERMAL=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8973=y
 # CONFIG_HID is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
 CONFIG_TMPFS=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 300ded9acbe9..3b515c179487 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -18,15 +18,14 @@ CONFIG_SOC_AT91RM9200=y
 CONFIG_SOC_AT91SAM9260=y
 CONFIG_SOC_AT91SAM9261=y
 CONFIG_SOC_AT91SAM9263=y
+CONFIG_SOC_AT91SAM9RL=y
 CONFIG_SOC_AT91SAM9G45=y
 CONFIG_SOC_AT91SAM9X5=y
 CONFIG_SOC_AT91SAM9N12=y
-CONFIG_SOC_AT91SAM9RL=y
 CONFIG_MACH_AT91RM9200_DT=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -63,23 +62,20 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_MACB=y
@@ -105,9 +101,8 @@ CONFIG_RT2800USB=m
 CONFIG_RT2800USB_RT53XX=y
 CONFIG_RT2800USB_RT55XX=y
 CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RTLWIFI=m
-# CONFIG_RTLWIFI_DEBUG is not set
 CONFIG_RTL8192CU=m
+# CONFIG_RTLWIFI_DEBUG is not set
 CONFIG_MWIFIEX=m
 CONFIG_MWIFIEX_SDIO=m
 CONFIG_MWIFIEX_USB=m
@@ -128,9 +123,12 @@ CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_AT91=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
@@ -144,11 +142,14 @@ CONFIG_BACKLIGHT_ATMEL_LCDC=y
 # CONFIG_BACKLIGHT_GENERIC is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_ACORN_8x8=y
-CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_ATMEL_SOC=y
+CONFIG_SND_AT91_SOC_SAM9G20_WM8731=y
+CONFIG_SND_ATMEL_SOC_WM8904=y
+CONFIG_SND_AT91_SOC_SAM9X5_WM8731=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_EHCI_HCD=y
@@ -169,6 +170,7 @@ CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -178,7 +180,12 @@ CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
+CONFIG_AT_HDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IIO=y
+CONFIG_AT91_ADC=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
 CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
@@ -209,3 +216,7 @@ CONFIG_CRC_CCITT=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=m
 CONFIG_AVERAGE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_ACORN_8x8=y
+CONFIG_FONT_MINI_4x6=y
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index c4c160fc8791..3ada05d639ad 100644
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -54,7 +54,6 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
@@ -66,13 +65,10 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_MII=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
@@ -86,7 +82,6 @@ CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -97,6 +92,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
@@ -127,6 +124,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_IIO=y
+CONFIG_AT91_ADC=y
 CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
@@ -139,10 +138,8 @@ CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_INFO=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_LL=y
-CONFIG_AT91_DEBUG_LL_DBGU0=y
 CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9261_9g10_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
index f80e993b04ce..0c505d801e25 100644
--- a/arch/arm/configs/at91sam9261_9g10_defconfig
+++ b/arch/arm/configs/at91sam9261_9g10_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_KERNEL_LZMA=y
 # CONFIG_SWAP is not set
@@ -20,7 +19,6 @@ CONFIG_MACH_AT91SAM9261EK=y
 CONFIG_MACH_AT91SAM9G10EK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
@@ -55,7 +53,6 @@ CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_DM9000=y
 CONFIG_USB_ZD1201=m
@@ -87,6 +84,8 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index e40026364e57..8b671c977b81 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -18,7 +18,6 @@ CONFIG_MACH_AT91SAM9263EK=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
@@ -51,7 +50,6 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_NFTL=y
 CONFIG_NFTL_RW=y
@@ -64,13 +62,10 @@ CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
-CONFIG_MII=y
 CONFIG_MACB=y
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
@@ -92,6 +87,8 @@ CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
@@ -103,7 +100,6 @@ CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FONTS=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -129,12 +125,14 @@ CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_ATMEL_PWM=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
 CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
@@ -150,3 +148,4 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
+CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index c6661a60025d..f66d1a1b64bf 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -20,7 +20,6 @@ CONFIG_MACH_AT91SAM9M10G45EK=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -51,7 +50,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
@@ -62,15 +60,12 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_MII=y
 CONFIG_MACB=y
 CONFIG_DAVICOM_PHY=y
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -93,18 +88,22 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_ATMEL_LCDC=y
-CONFIG_BACKLIGHT_ATMEL_PWM=y
 # CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FONTS=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -135,6 +134,7 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -147,6 +147,8 @@ CONFIG_DMATEST=m
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
 CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
@@ -159,8 +161,8 @@ CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_SCHED_DEBUG is not set
 CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_SCHED_DEBUG is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_LL=y
@@ -170,3 +172,4 @@ CONFIG_CRYPTO_ECB=y
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
+CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index 5d7797d43d23..4c26d344ae88 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -2,8 +2,8 @@
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EMBEDDED=y
 CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -37,7 +37,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=24576
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
@@ -54,20 +53,31 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ATMEL_USBA=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_UBIFS_FS=y
@@ -77,7 +87,6 @@ CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 0302d293fba0..31cb07388885 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -98,6 +98,7 @@ CONFIG_LEDS_TRIGGER_TRANSIENT=y
 CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_STAGING=y
 CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_HOST=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index fbebcbce1e8c..bc614f44b33d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -83,7 +83,6 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_MFD_BCM590XX=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_USERSPACE_CONSUMER=y
 CONFIG_REGULATOR_BCM590XX=y
 
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index e816140d81c5..1dde5daa84f9 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -29,7 +29,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_SUSPEND is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -55,6 +54,7 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
@@ -82,6 +82,7 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HWMON is not set
 CONFIG_I2C=y
 CONFIG_I2C_RCAR=y
+CONFIG_GPIO_RCAR=y
 CONFIG_REGULATOR=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 0facf9da047c..fc105c9178cc 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -68,8 +68,8 @@ CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CLPS711X=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_PWM=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -77,6 +77,8 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_CLPS711X=y
 CONFIG_EXT2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_MINIX_FS=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 1b650c85bdd0..72233b9c9d07 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -107,5 +107,6 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_PL01X=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index d95763d5f0d8..eb440aae4283 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -230,7 +230,6 @@ CONFIG_POWER_SUPPLY=y
 CONFIG_EZX_PCAP=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_USERSPACE_CONSUMER=y
 CONFIG_REGULATOR_PCAP=y
 CONFIG_MEDIA_SUPPORT=y
diff --git a/arch/arm/configs/hi3xxx_defconfig b/arch/arm/configs/hisi_defconfig
index 9630687e7d07..1772505caeba 100644
--- a/arch/arm/configs/hi3xxx_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -6,10 +6,15 @@ CONFIG_RD_LZMA=y
 CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_HIX5HD2=y
+CONFIG_ARCH_HIP04=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=16
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
 CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
 CONFIG_NET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -21,6 +26,12 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
@@ -56,3 +67,5 @@ CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_LOCKUP_DETECTOR=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index fd996bb13022..182e54692664 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -208,7 +208,6 @@ CONFIG_POWER_SUPPLY=y
 CONFIG_PMIC_DA903X=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_USERSPACE_CONSUMER=y
 CONFIG_REGULATOR_DA903X=y
 CONFIG_MEDIA_SUPPORT=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 63bde0efc041..e688741c89aa 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -21,8 +21,6 @@ CONFIG_ARCH_MULTI_V4T=y
 CONFIG_ARCH_MULTI_V5=y
 # CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_MXC=y
-CONFIG_MXC_IRQ_PRIOR=y
-CONFIG_ARCH_MX1ADS=y
 CONFIG_MACH_SCB9328=y
 CONFIG_MACH_APF9328=y
 CONFIG_MACH_MX21ADS=y
@@ -30,10 +28,6 @@ CONFIG_MACH_MX25_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX25SD=y
 CONFIG_MACH_IMX25_DT=y
 CONFIG_MACH_MX27ADS=y
-CONFIG_MACH_PCM038=y
-CONFIG_MACH_CPUIMX27=y
-CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
-CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
 CONFIG_MACH_MX27_3DS=y
 CONFIG_MACH_IMX27_VISSTRIM_M10=y
 CONFIG_MACH_PCA100=y
@@ -43,8 +37,6 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -63,6 +55,7 @@ CONFIG_NETFILTER=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_IMX_WEIM=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
@@ -78,8 +71,8 @@ CONFIG_MTD_NAND_MXC=y
 CONFIG_MTD_UBI=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
-CONFIG_ATA=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
 CONFIG_PATA_IMX=y
 CONFIG_NETDEVICES=y
 CONFIG_CS89x0=y
@@ -102,10 +95,8 @@ CONFIG_SERIAL_8250=m
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_IMX=y
-CONFIG_SPI=y
 CONFIG_SPI_IMX=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_GPIO_SYSFS=y
@@ -132,10 +123,7 @@ CONFIG_VIDEO_CODA=y
 CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_FB=y
 CONFIG_FB_IMX=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 16cfec4385c8..8fca6e276b69 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,8 +32,8 @@ CONFIG_MACH_IMX35_DT=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
-CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX50=y
+CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
@@ -105,7 +105,6 @@ CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
@@ -153,14 +152,12 @@ CONFIG_SERIAL_IMX_CONSOLE=y
 CONFIG_SERIAL_FSL_LPUART=y
 CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MXC_RNGA=y
 # CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_ALGOPCF=m
 CONFIG_I2C_ALGOPCA=m
 CONFIG_I2C_IMX=y
-CONFIG_SPI=y
 CONFIG_SPI_IMX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_MC9S08DZ60=y
@@ -198,7 +195,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
 CONFIG_LCD_PLATFORM=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -206,6 +202,7 @@ CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SOC=y
+CONFIG_SND_SOC_FSL_SAI=y
 CONFIG_SND_IMX_SOC=y
 CONFIG_SND_SOC_PHYCORE_AC97=y
 CONFIG_SND_SOC_EUKREA_TLV320=y
@@ -213,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y
 CONFIG_SND_SOC_IMX_SGTL5000=y
 CONFIG_SND_SOC_IMX_SPDIF=y
 CONFIG_SND_SOC_IMX_MC13783=y
+CONFIG_SND_SIMPLE_CARD=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
@@ -240,6 +238,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_ISL1208=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
@@ -254,7 +253,6 @@ CONFIG_DRM_IMX_FB_HELPER=y
 CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
 CONFIG_DRM_IMX_TVE=y
 CONFIG_DRM_IMX_LDB=y
-CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
 CONFIG_DRM_IMX_HDMI=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index 86faab565a96..b33d19b7f134 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -15,6 +15,9 @@ CONFIG_MACH_KOELSCH=y
 CONFIG_CPU_BPREDICT_DISABLE=y
 CONFIG_PL310_ERRATA_588369=y
 CONFIG_ARM_ERRATA_754322=y
+CONFIG_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PCI_RCAR_GEN2_PCIE=y
 CONFIG_SMP=y
 CONFIG_SCHED_MC=y
 CONFIG_NR_CPUS=8
@@ -42,6 +45,8 @@ CONFIG_ATA=y
 CONFIG_SATA_RCAR=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_EEPROM_AT24=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_ARC is not set
 # CONFIG_NET_CADENCE is not set
@@ -66,9 +71,12 @@ CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=20
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_SH_MOBILE=y
 CONFIG_I2C_RCAR=y
 CONFIG_SPI=y
 CONFIG_SPI_RSPI=y
+CONFIG_SPI_SH_MSIOF=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_RCAR=y
 # CONFIG_HWMON is not set
@@ -76,7 +84,16 @@ CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_DA9210=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_PLATFORM=y
+CONFIG_VIDEO_RCAR_VIN=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_VIDEO_ADV7180=y
 # CONFIG_HID is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index bd097d455f87..8cb115d74fdf 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -119,6 +119,7 @@ CONFIG_MMC_SDHI=y
 CONFIG_MMC_SH_MMCIF=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RS5C372=y
 CONFIG_DMADEVICES=y
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 58702440472a..929c571ea29b 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -22,6 +22,9 @@ CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_754322=y
+CONFIG_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PCI_RCAR_GEN2_PCIE=y
 CONFIG_HAVE_ARM_ARCH_TIMER=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -53,6 +56,7 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_RCAR=y
@@ -85,11 +89,12 @@ CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=10
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
+CONFIG_I2C_SH_MOBILE=y
 CONFIG_I2C_RCAR=y
 CONFIG_SPI=y
 CONFIG_SPI_RSPI=y
+CONFIG_SPI_SH_MSIOF=y
 CONFIG_GPIO_SH_PFC=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_RCAR=y
@@ -98,6 +103,7 @@ CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_DA9210=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 398a367ffce8..9f56ca3985ae 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -59,6 +59,7 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_SLC_LPC32XX=y
 CONFIG_MTD_NAND_MLC_LPC32XX=y
+CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
@@ -189,6 +190,7 @@ CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_UBIFS_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 92994f7f6fd8..ff91630d34e1 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -84,6 +84,7 @@ CONFIG_GPIO_RCAR=y
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
+CONFIG_REGULATOR=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fb95fb758d9..491b7d5523bf 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -28,7 +28,9 @@ CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_HIX5HD2=y
+CONFIG_ARCH_HIP04=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARCH_MESON=y
 CONFIG_ARCH_MXC=y
 CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX53=y
@@ -42,6 +44,7 @@ CONFIG_SOC_AM33XX=y
 CONFIG_SOC_AM43XX=y
 CONFIG_SOC_DRA7XX=y
 CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_MEDIATEK=y
 CONFIG_ARCH_MSM8X60=y
 CONFIG_ARCH_MSM8960=y
 CONFIG_ARCH_MSM8974=y
@@ -74,6 +77,7 @@ CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PCI_TEGRA=y
+CONFIG_PCIEPORTBUS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=8
 CONFIG_HIGHPTE=y
@@ -86,6 +90,7 @@ CONFIG_CPU_FREQ_STAT_DETAILS=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
 CONFIG_NEON=y
+CONFIG_ARM_ZYNQ_CPUIDLE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -106,6 +111,7 @@ CONFIG_CAN=y
 CONFIG_CAN_RAW=y
 CONFIG_CAN_BCM=y
 CONFIG_CAN_DEV=y
+CONFIG_CAN_XILINXCAN=y
 CONFIG_CAN_MCP251X=y
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
@@ -119,7 +125,10 @@ CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_OMAP_OCP2SCP=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_AD525X_DPOT=y
+CONFIG_AD525X_DPOT_I2C=y
 CONFIG_ICS932S401=y
 CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
@@ -129,9 +138,11 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_AHCI_ST=y
 CONFIG_AHCI_SUNXI=y
+CONFIG_AHCI_TEGRA=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
@@ -146,6 +157,7 @@ CONFIG_R8169=y
 CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=y
 CONFIG_TI_CPSW=y
+CONFIG_XILINX_EMACLITE=y
 CONFIG_AT803X_PHY=y
 CONFIG_MARVELL_PHY=y
 CONFIG_ICPLUS_PHY=y
@@ -156,6 +168,7 @@ CONFIG_USB_NET_SMSC95XX=y
 CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=m
 CONFIG_RT2800USB=m
+CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_TEGRA=y
@@ -164,6 +177,7 @@ CONFIG_KEYBOARD_ST_KEYSCAN=y
 CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
 CONFIG_TOUCHSCREEN_STMPE=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
@@ -173,6 +187,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MESON=y
+CONFIG_SERIAL_MESON_CONSOLE=y
 CONFIG_SERIAL_SAMSUNG=y
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_SIRFSOC=y
@@ -205,6 +221,8 @@ CONFIG_I2C_SIRF=y
 CONFIG_I2C_TEGRA=y
 CONFIG_I2C_ST=y
 CONFIG_SPI=y
+CONFIG_I2C_XILINX=y
+CONFIG_SPI_CADENCE=y
 CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_ORION=y
 CONFIG_SPI_PL022=y
@@ -214,11 +232,14 @@ CONFIG_SPI_SUN6I=y
 CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
+CONFIG_SPI_XILINX=y
 CONFIG_PINCTRL_AS3722=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_XILINX=y
+CONFIG_GPIO_ZYNQ=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TWL4030=y
@@ -237,6 +258,7 @@ CONFIG_ARMADA_THERMAL=y
 CONFIG_ST_THERMAL_SYSCFG=y
 CONFIG_ST_THERMAL_MEMMAP=y
 CONFIG_WATCHDOG=y
+CONFIG_XILINX_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
 CONFIG_MFD_AS3722=y
@@ -250,7 +272,6 @@ CONFIG_MFD_PALMAS=y
 CONFIG_MFD_TPS65090=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_AB8500=y
 CONFIG_REGULATOR_AS3722=y
 CONFIG_REGULATOR_BCM590XX=y
@@ -281,6 +302,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SOC=y
@@ -333,7 +355,18 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y
@@ -349,6 +382,7 @@ CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RTC_DRV_VT8500=y
+CONFIG_RTC_DRV_SUN6I=y
 CONFIG_RTC_DRV_SUNXI=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_RTC_DRV_TEGRA=y
@@ -364,6 +398,7 @@ CONFIG_IMX_SDMA=y
 CONFIG_IMX_DMA=y
 CONFIG_MXS_DMA=y
 CONFIG_DMA_OMAP=y
+CONFIG_XILINX_VDMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
@@ -371,6 +406,7 @@ CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
 CONFIG_NVEC_POWER=y
+CONFIG_NVEC_PAZ00=y
 CONFIG_QCOM_GSBI=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_MSM_GCC_8660=y
@@ -380,6 +416,7 @@ CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_XILINX_XADC=y
 CONFIG_AK8975=y
 CONFIG_PWM=y
 CONFIG_PWM_TEGRA=y
@@ -403,3 +440,4 @@ CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_LOCKUP_DETECTOR=y
 CONFIG_CRYPTO_DEV_TEGRA_AES=y
+CONFIG_GENERIC_CPUFREQ_CPU0=y
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index fdfda1fa9521..ed0a0d1be0f3 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_FHANDLE=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
@@ -15,9 +14,6 @@ CONFIG_MACH_ARMADA_375=y
 CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
-CONFIG_NEON=y
-# CONFIG_CACHE_L2X0 is not set
-# CONFIG_SWP_EMULATE is not set
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
@@ -29,12 +25,14 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_FREQ=y
 CONFIG_CPU_IDLE=y
 CONFIG_ARM_MVEBU_V7_CPUIDLE=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPUFREQ_GENERIC=y
 CONFIG_VFP=y
+CONFIG_NEON=y
 CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
@@ -44,11 +42,24 @@ CONFIG_BT_MRVL=y
 CONFIG_BT_MRVL_SDIO=y
 CONFIG_CFG80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PXA3xx=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_AHCI_MVEBU=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
+CONFIG_MV643XX_ETH=y
 CONFIG_MVNETA=y
 CONFIG_MVPP2=y
 CONFIG_MARVELL_PHY=y
@@ -58,47 +69,36 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
+CONFIG_I2C_MV64XXX=y
 CONFIG_SPI=y
 CONFIG_SPI_ORION=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PXA3xx=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_GPIO_FAN=y
 CONFIG_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SOC=y
 CONFIG_SND_KIRKWOOD_SOC=y
 CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=y
-CONFIG_WATCHDOG=y
-CONFIG_ORION_WATCHDOG=y
-CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MVEBU=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MVEBU=y
 CONFIG_MMC=y
-CONFIG_MMC_SDHCI_PXAV3=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_DOVE=y
 CONFIG_MMC_MVSDIO=y
-CONFIG_NEW_LEDS=y
 CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -107,12 +107,9 @@ CONFIG_RTC_DRV_S35390A=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_DMADEVICES=y
 CONFIG_MV_XOR=y
-CONFIG_MEMORY=y
-CONFIG_MVEBU_DEVBUS=y
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_MEMORY=y
+CONFIG_EXT4_FS=y
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -126,10 +123,11 @@ CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=y
 CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f650f00e8cee..69c7bed3c634 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -1,11 +1,28 @@
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_SLAB=y
@@ -32,19 +49,26 @@ CONFIG_SOC_OMAP5=y
 CONFIG_SOC_AM33XX=y
 CONFIG_SOC_AM43XX=y
 CONFIG_SOC_DRA7XX=y
-CONFIG_CACHE_L2X0=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_CMA=y
+CONFIG_SECCOMP=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
 CONFIG_KEXEC=y
-CONFIG_FPE_NWFPE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_GENERIC_CPUFREQ_CPU0=y
+# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
 CONFIG_CPU_IDLE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_PM_DEBUG=y
@@ -61,7 +85,7 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
 CONFIG_NETFILTER=y
 CONFIG_CAN=m
 CONFIG_CAN_C_CAN=m
@@ -75,9 +99,6 @@ CONFIG_BT_HCIBCM203X=m
 CONFIG_BT_HCIBPA10X=m
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
-CONFIG_MAC80211_RC_PID=y
-CONFIG_MAC80211_RC_DEFAULT_PID=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_DMA_CMA=y
@@ -101,9 +122,9 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
 CONFIG_SENSORS_TSL2550=m
 CONFIG_BMP085_I2C=m
 CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_SRAM=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_MD=y
 CONFIG_NETDEVICES=y
@@ -138,7 +159,9 @@ CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_MATRIX=m
 CONFIG_KEYBOARD_TWL4030=y
 CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_TSC2005=m
+CONFIG_TOUCHSCREEN_TSC2007=m
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_TWL4030_PWRBUTTON=y
 # CONFIG_LEGACY_PTYS is not set
@@ -162,7 +185,13 @@ CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_TWL4030=y
 CONFIG_W1=y
-CONFIG_POWER_SUPPLY=y
+CONFIG_BATTERY_BQ27x00=m
+CONFIG_CHARGER_ISP1704=m
+CONFIG_CHARGER_TWL4030=m
+CONFIG_CHARGER_BQ2415X=m
+CONFIG_CHARGER_BQ24190=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_POWER_RESET=y
 CONFIG_POWER_AVS=y
 CONFIG_SENSORS_LM75=m
 CONFIG_THERMAL=y
@@ -183,8 +212,8 @@ CONFIG_MFD_TPS65217=y
 CONFIG_MFD_TPS65218=y
 CONFIG_MFD_TPS65910=y
 CONFIG_TWL6040_CORE=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_PBIAS=y
 CONFIG_REGULATOR_TI_ABB=y
 CONFIG_REGULATOR_TPS65023=y
 CONFIG_REGULATOR_TPS6507X=y
@@ -192,12 +221,12 @@ CONFIG_REGULATOR_TPS65217=y
 CONFIG_REGULATOR_TPS65218=y
 CONFIG_REGULATOR_TPS65910=y
 CONFIG_REGULATOR_TWL4030=y
-CONFIG_REGULATOR_PBIAS=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_TILEBLITTING=y
 CONFIG_OMAP2_DSS=m
+CONFIG_OMAP5_DSS_HDMI=y
 CONFIG_OMAP2_DSS_SDI=y
 CONFIG_OMAP2_DSS_DSI=y
 CONFIG_FB_OMAP2=m
@@ -205,11 +234,25 @@ CONFIG_DISPLAY_ENCODER_TFP410=m
 CONFIG_DISPLAY_ENCODER_TPD12S015=m
 CONFIG_DISPLAY_CONNECTOR_DVI=m
 CONFIG_DISPLAY_CONNECTOR_HDMI=m
+CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=m
 CONFIG_DISPLAY_PANEL_DPI=m
+CONFIG_DISPLAY_PANEL_DSI_CM=m
+CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m
+CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=m
+CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=m
+CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=m
+CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=m
+CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=m
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_PANDORA=m
+CONFIG_BACKLIGHT_GPIO=m
 CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_LOGO=y
 CONFIG_SOUND=m
@@ -221,8 +264,6 @@ CONFIG_SND_DEBUG=y
 CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_SOC=m
 CONFIG_SND_OMAP_SOC=m
-CONFIG_SND_AM33XX_SOC_EVM=m
-CONFIG_SND_DAVINCI_SOC=m
 CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
 CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
 CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
@@ -233,9 +274,6 @@ CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC3=m
 CONFIG_USB_TEST=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_OMAP_USB2=y
-CONFIG_TI_PIPE3=y
 CONFIG_AM335X_PHY_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DEBUG=y
@@ -243,7 +281,6 @@ CONFIG_USB_GADGET_DEBUG_FILES=y
 CONFIG_USB_GADGET_DEBUG_FS=y
 CONFIG_USB_ZERO=m
 CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_SDIO_UART=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
@@ -267,15 +304,23 @@ CONFIG_TI_EDMA=y
 CONFIG_DMA_OMAP=y
 CONFIG_EXTCON=y
 CONFIG_EXTCON_PALMAS=y
+CONFIG_PWM=y
+CONFIG_PWM_TWL=y
+CONFIG_PWM_TWL_LED=y
+CONFIG_OMAP_USB2=y
+CONFIG_TI_PIPE3=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
 CONFIG_EXT4_FS=y
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA=y
 CONFIG_QFMT_V2=y
+CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_SUMMARY=y
 CONFIG_JFFS2_FS_XATTR=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index 60e313834b3f..5f337d7ceb5b 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -77,7 +77,6 @@ CONFIG_BATTERY_DA9030=y
 CONFIG_PMIC_DA903X=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_DA903X=y
 CONFIG_FB=y
 CONFIG_FB_PXA=y
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 42ebd72799e6..8c7da3319d82 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -29,6 +29,7 @@ CONFIG_HIGHPTE=y
 CONFIG_CLEANCACHE=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -53,14 +54,13 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_SCSI=y
-CONFIG_SCSI_TGT=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_CHR_DEV_SCH=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
@@ -86,7 +86,6 @@ CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MSM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_QUP=y
@@ -94,7 +93,9 @@ CONFIG_SPI=y
 CONFIG_SPI_QUP=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_APQ8064=y
+CONFIG_PINCTRL_APQ8084=y
 CONFIG_PINCTRL_IPQ8064=y
+CONFIG_PINCTRL_MSM8960=y
 CONFIG_PINCTRL_MSM8X74=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
@@ -103,6 +104,7 @@ CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_MSM=y
 CONFIG_THERMAL=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_FB=y
 CONFIG_SOUND=y
@@ -124,6 +126,7 @@ CONFIG_USB_GADGET_DEBUG_FILES=y
 CONFIG_USB_GADGET_VBUS_DRAW=500
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_MSM=y
@@ -133,11 +136,14 @@ CONFIG_QCOM_BAM_DMA=y
 CONFIG_STAGING=y
 CONFIG_QCOM_GSBI=y
 CONFIG_COMMON_CLK_QCOM=y
+CONFIG_APQ_MMCC_8084=y
+CONFIG_IPQ_GCC_806X=y
 CONFIG_MSM_GCC_8660=y
 CONFIG_MSM_MMCC_8960=y
 CONFIG_MSM_MMCC_8974=y
 CONFIG_MSM_IOMMU=y
-CONFIG_GENERIC_PHY=y
+CONFIG_PHY_QCOM_APQ8064_SATA=y
+CONFIG_PHY_QCOM_IPQ806X_SATA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 4414990521d3..c9089c927daf 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -19,9 +19,9 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_SOC_SAM_V7=y
 CONFIG_SOC_SAMA5D3=y
+CONFIG_SOC_SAMA5D4=y
 CONFIG_MACH_SAMA5_DT=y
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -65,15 +65,14 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
@@ -83,10 +82,8 @@ CONFIG_ATMEL_SSC=y
 CONFIG_EEPROM_AT24=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_MII=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_CIRRUS is not set
@@ -135,6 +132,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_GPIO=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
 # CONFIG_HWMON is not set
 CONFIG_SSB=m
 CONFIG_REGULATOR=y
@@ -145,6 +144,11 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_ATMEL_SOC=y
+CONFIG_SND_ATMEL_SOC_WM8904=y
 # CONFIG_HID_GENERIC is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -165,6 +169,7 @@ CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
@@ -174,6 +179,8 @@ CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
 CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
@@ -188,8 +195,8 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
-# CONFIG_SCHED_DEBUG is not set
 CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_SCHED_DEBUG is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 3b136144cc83..d7346ad51043 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -3,6 +3,7 @@ CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
@@ -11,9 +12,11 @@ CONFIG_SLAB=y
 CONFIG_ARCH_SHMOBILE_MULTI=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R7S72100=y
+CONFIG_ARCH_R8A7740=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_ARCH_R8A7791=y
+CONFIG_ARCH_R8A7794=y
 CONFIG_MACH_KOELSCH=y
 CONFIG_MACH_LAGER=y
 CONFIG_MACH_MARZEN=y
@@ -49,6 +52,7 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_EEPROM_AT24=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
@@ -73,6 +77,8 @@ CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ST1232=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
@@ -82,6 +88,7 @@ CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=20
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C_GPIO=y
+CONFIG_I2C_RIIC=y
 CONFIG_I2C_SH_MOBILE=y
 CONFIG_I2C_RCAR=y
 CONFIG_SPI=y
@@ -110,10 +117,16 @@ CONFIG_VIDEO_RENESAS_VSP1=y
 CONFIG_VIDEO_ADV7180=y
 CONFIG_DRM=y
 CONFIG_DRM_RCAR_DU=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SOC=y
+CONFIG_SND_SOC_SH4_FSI=y
 CONFIG_SND_SOC_RCAR=y
+CONFIG_SND_SOC_WM8978=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
@@ -130,9 +143,12 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S35390A=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_RENESAS_TPU=y
 # CONFIG_DNOTIFY is not set
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 7209bfd62074..c1a4ca4f6e6d 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -75,7 +75,6 @@ CONFIG_POWER_RESET_SUN6I=y
 CONFIG_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
 CONFIG_MFD_AXP20X=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -93,6 +92,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_INTF_SYSFS is not set
 # CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_DRV_SUN6I=y
 CONFIG_RTC_DRV_SUNXI=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_PHY_SUN4I_USB=y
@@ -103,5 +103,7 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 285c433a9aad..888fc1521322 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -102,6 +102,9 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_AHCI_TEGRA=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
 CONFIG_IGB=y
@@ -120,6 +123,7 @@ CONFIG_KEYBOARD_TEGRA=y
 CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
 CONFIG_TOUCHSCREEN_STMPE=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
@@ -165,7 +169,6 @@ CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_AS3722=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MAX8907=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index d52b4ffe2012..ea49d37564da 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -82,5 +82,6 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_PL01X=y
 CONFIG_FONTS=y
 CONFIG_FONT_ACORN_8x8=y
diff --git a/arch/arm/crypto/sha1-armv7-neon.S b/arch/arm/crypto/sha1-armv7-neon.S
index 50013c0e2864..dcd01f3f0bb0 100644
--- a/arch/arm/crypto/sha1-armv7-neon.S
+++ b/arch/arm/crypto/sha1-armv7-neon.S
@@ -9,7 +9,7 @@
  */
 
 #include <linux/linkage.h>
-
+#include <asm/assembler.h>
 
 .syntax unified
 .code   32
@@ -61,13 +61,13 @@
 #define RT3 r12
 
 #define W0 q0
-#define W1 q1
+#define W1 q7
 #define W2 q2
 #define W3 q3
 #define W4 q4
-#define W5 q5
-#define W6 q6
-#define W7 q7
+#define W5 q6
+#define W6 q5
+#define W7 q1
 
 #define tmp0 q8
 #define tmp1 q9
@@ -79,6 +79,11 @@
 #define qK3 q14
 #define qK4 q15
 
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define ARM_LE(code...)
+#else
+#define ARM_LE(code...)         code
+#endif
 
 /* Round function macros. */
 
@@ -150,45 +155,45 @@
 #define W_PRECALC_00_15() \
         add       RWK, sp, #(WK_offs(0));                       \
         \
-        vld1.32   {tmp0, tmp1}, [RDATA]!;                       \
-        vrev32.8  W0, tmp0;             /* big => little */     \
-        vld1.32   {tmp2, tmp3}, [RDATA]!;                       \
+        vld1.32   {W0, W7}, [RDATA]!;                           \
+ ARM_LE(vrev32.8  W0, W0;       )       /* big => little */     \
+        vld1.32   {W6, W5}, [RDATA]!;                           \
         vadd.u32  tmp0, W0, curK;                               \
-        vrev32.8  W7, tmp1;             /* big => little */     \
-        vrev32.8  W6, tmp2;             /* big => little */     \
+ ARM_LE(vrev32.8  W7, W7;       )       /* big => little */     \
+ ARM_LE(vrev32.8  W6, W6;       )       /* big => little */     \
         vadd.u32  tmp1, W7, curK;                               \
-        vrev32.8  W5, tmp3;             /* big => little */     \
+ ARM_LE(vrev32.8  W5, W5;       )       /* big => little */     \
         vadd.u32  tmp2, W6, curK;                               \
         vst1.32   {tmp0, tmp1}, [RWK]!;                         \
         vadd.u32  tmp3, W5, curK;                               \
         vst1.32   {tmp2, tmp3}, [RWK];                          \
 
 #define WPRECALC_00_15_0(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
-        vld1.32   {tmp0, tmp1}, [RDATA]!;                       \
+        vld1.32   {W0, W7}, [RDATA]!;                           \
 
 #define WPRECALC_00_15_1(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
         add       RWK, sp, #(WK_offs(0));                       \
 
 #define WPRECALC_00_15_2(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
-        vrev32.8  W0, tmp0;             /* big => little */     \
+ ARM_LE(vrev32.8  W0, W0;       )       /* big => little */     \
 
 #define WPRECALC_00_15_3(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
-        vld1.32   {tmp2, tmp3}, [RDATA]!;                       \
+        vld1.32   {W6, W5}, [RDATA]!;                           \
 
 #define WPRECALC_00_15_4(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
         vadd.u32  tmp0, W0, curK;                               \
 
 #define WPRECALC_00_15_5(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
-        vrev32.8  W7, tmp1;             /* big => little */     \
+ ARM_LE(vrev32.8  W7, W7;       )       /* big => little */     \
 
 #define WPRECALC_00_15_6(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
-        vrev32.8  W6, tmp2;             /* big => little */     \
+ ARM_LE(vrev32.8  W6, W6;       )       /* big => little */     \
 
 #define WPRECALC_00_15_7(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
         vadd.u32  tmp1, W7, curK;                               \
 
 #define WPRECALC_00_15_8(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
-        vrev32.8  W5, tmp3;             /* big => little */     \
+ ARM_LE(vrev32.8  W5, W5;       )       /* big => little */     \
 
 #define WPRECALC_00_15_9(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
         vadd.u32  tmp2, W6, curK;                               \
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 0704e0cf5571..92793ba69c40 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -99,31 +99,6 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl)
         asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
 }
 
-static inline void arch_counter_set_user_access(void)
-{
-        u32 cntkctl = arch_timer_get_cntkctl();
-
-        /* Disable user access to both physical/virtual counters/timers */
-        /* Also disable virtual event stream */
-        cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
-                        | ARCH_TIMER_USR_VT_ACCESS_EN
-                        | ARCH_TIMER_VIRT_EVT_EN
-                        | ARCH_TIMER_USR_VCT_ACCESS_EN
-                        | ARCH_TIMER_USR_PCT_ACCESS_EN);
-        arch_timer_set_cntkctl(cntkctl);
-}
-
-static inline void arch_timer_evtstrm_enable(int divider)
-{
-        u32 cntkctl = arch_timer_get_cntkctl();
-        cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
-        /* Set the divider and enable virtual event stream */
-        cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
-                        | ARCH_TIMER_VIRT_EVT_EN;
-        arch_timer_set_cntkctl(cntkctl);
-        elf_hwcap |= HWCAP_EVTSTRM;
-}
-
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index fd43f7f55b70..10e78d00a0bb 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -466,13 +466,13 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
  */
 #define v7_exit_coherency_flush(level) \
         asm volatile( \
+        ".arch  armv7-a \n\t" \
         "stmfd  sp!, {fp, ip} \n\t" \
         "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR \n\t" \
         "bic    r0, r0, #"__stringify(CR_C)" \n\t" \
         "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR \n\t" \
         "isb    \n\t" \
         "bl     v7_flush_dcache_"__stringify(level)" \n\t" \
-        "clrex  \n\t" \
         "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR \n\t" \
         "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t" \
         "mcr    p15, 0, r0, c1, c0, 1   @ set ACTLR \n\t" \
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 963a2515906d..819777d0e91f 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -74,6 +74,7 @@
 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
+#define ARM_CPU_PART_MASK               0xff00fff0
 
 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
@@ -179,7 +180,7 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
  */
 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 {
-        return read_cpuid_id() & 0xff00fff0;
+        return read_cpuid_id() & ARM_CPU_PART_MASK;
 }
 
 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index f4b46d39b9cf..afb9cafd3786 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -50,6 +50,7 @@ typedef struct user_fp elf_fpregset_t;
 #define R_ARM_ABS32             2
 #define R_ARM_CALL              28
 #define R_ARM_JUMP24            29
+#define R_ARM_TARGET1           38
 #define R_ARM_V4BX              40
 #define R_ARM_PREL31            42
 #define R_ARM_MOVW_ABS_NC       43
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index 39eb16b0066f..bfe2a2f5a644 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -45,7 +45,7 @@ void *return_address(unsigned int);
 
 #else
 
-extern inline void *return_address(unsigned int level)
+static inline void *return_address(unsigned int level)
 {
         return NULL;
 }
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 3d23418cbddd..180567408ee8 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -178,6 +178,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 
 /* PCI fixed i/o mapping */
 #define PCI_IO_VIRT_BASE        0xfee00000
+#define PCI_IOBASE              ((void __iomem *)PCI_IO_VIRT_BASE)
 
 #if defined(CONFIG_PCI)
 void pci_ioremap_set_mem_type(int mem_type);
diff --git a/arch/arm/include/asm/irq_work.h b/arch/arm/include/asm/irq_work.h
new file mode 100644
index 000000000000..712d03e5973a
--- /dev/null
+++ b/arch/arm/include/asm/irq_work.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_ARM_IRQ_WORK_H
+#define __ASM_ARM_IRQ_WORK_H
+
+#include <asm/smp_plat.h>
+
+static inline bool arch_irq_work_has_interrupt(void)
+{
+        return is_smp();
+}
+
+#endif /* _ASM_ARM_IRQ_WORK_H */
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 69b746955fca..b9db269c6e61 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -149,6 +149,11 @@ static inline bool kvm_vcpu_trap_is_iabt(struct kvm_vcpu *vcpu)
 
 static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)
 {
+        return kvm_vcpu_get_hsr(vcpu) & HSR_FSC;
+}
+
+static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)
+{
         return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;
 }
 
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 6dfb404f6c46..53036e21756b 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -19,6 +19,8 @@
 #ifndef __ARM_KVM_HOST_H__
 #define __ARM_KVM_HOST_H__
 
+#include <linux/types.h>
+#include <linux/kvm_types.h>
 #include <asm/kvm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
@@ -40,9 +42,8 @@
 
 #include <kvm/arm_vgic.h>
 
-struct kvm_vcpu;
 u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
-int kvm_target_cpu(void);
+int __attribute_const__ kvm_target_cpu(void);
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
 void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
 
@@ -149,20 +150,17 @@ struct kvm_vcpu_stat {
         u32 halt_wakeup;
 };
 
-struct kvm_vcpu_init;
 int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
                         const struct kvm_vcpu_init *init);
 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
-struct kvm_one_reg;
 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 u64 kvm_call_hyp(void *hypfn, ...);
 void force_vm_exit(const cpumask_t *mask);
 
 #define KVM_ARCH_WANT_MMU_NOTIFIER
-struct kvm;
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 int kvm_unmap_hva_range(struct kvm *kvm,
                         unsigned long start, unsigned long end);
@@ -172,7 +170,8 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
 
 /* We do not have shadow page tables, hence the empty hooks */
-static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+static inline int kvm_age_hva(struct kvm *kvm, unsigned long start,
+                              unsigned long end)
 {
         return 0;
 }
@@ -182,12 +181,16 @@ static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
         return 0;
 }
 
+static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
+                                                         unsigned long address)
+{
+}
+
 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
 struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
 
 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
 unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
-struct kvm_one_reg;
 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 
@@ -233,4 +236,10 @@ static inline void vgic_arch_setup(const struct vgic_params *vgic)
 int kvm_perf_init(void);
 int kvm_perf_teardown(void);
 
+static inline void kvm_arch_hardware_disable(void) {}
+static inline void kvm_arch_hardware_unsetup(void) {}
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
+
 #endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 5cc0b0f5f72f..3f688b458143 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -78,17 +78,6 @@ static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
         flush_pmd_entry(pte);
 }
 
-static inline bool kvm_is_write_fault(unsigned long hsr)
-{
-        unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
-        if (hsr_ec == HSR_EC_IABT)
-                return false;
-        else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
-                return false;
-        else
-                return true;
-}
-
 static inline void kvm_clean_pgd(pgd_t *pgd)
 {
         clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h
index 57ff7f2a3084..d428e386c88e 100644
--- a/arch/arm/include/asm/mcpm.h
+++ b/arch/arm/include/asm/mcpm.h
@@ -20,7 +20,12 @@
  * to consider dynamic allocation.
  */
 #define MAX_CPUS_PER_CLUSTER    4
+
+#ifdef CONFIG_MCPM_QUAD_CLUSTER
+#define MAX_NR_CLUSTERS         4
+#else
 #define MAX_NR_CLUSTERS         2
+#endif
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 219ac88a9542..f0279411847d 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -182,6 +182,8 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 #define pmd_addr_end(addr,end) (end)
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
+#define pte_special(pte)        (0)
+static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 
 /*
  * We don't have huge page support for short descriptors, for the moment
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 06e0bc0f8b00..a31ecdad4b59 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -213,10 +213,19 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 #define pmd_isclear(pmd, val)   (!(pmd_val(pmd) & (val)))
 
 #define pmd_young(pmd)          (pmd_isset((pmd), PMD_SECT_AF))
+#define pte_special(pte)        (pte_isset((pte), L_PTE_SPECIAL))
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+        pte_val(pte) |= L_PTE_SPECIAL;
+        return pte;
+}
+#define __HAVE_ARCH_PTE_SPECIAL
 
 #define __HAVE_ARCH_PMD_WRITE
 #define pmd_write(pmd)          (pmd_isclear((pmd), L_PMD_SECT_RDONLY))
 #define pmd_dirty(pmd)          (pmd_isset((pmd), L_PMD_SECT_DIRTY))
+#define pud_page(pud)           pmd_page(__pmd(pud_val(pud)))
+#define pud_write(pud)          pmd_write(__pmd(pud_val(pud)))
 
 #define pmd_hugewillfault(pmd)  (!pmd_young(pmd) || !pmd_write(pmd))
 #define pmd_thp_or_huge(pmd)    (pmd_huge(pmd) || pmd_trans_huge(pmd))
@@ -224,6 +233,12 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 #define pmd_trans_huge(pmd)     (pmd_val(pmd) && !pmd_table(pmd))
 #define pmd_trans_splitting(pmd) (pmd_isset((pmd), L_PMD_SECT_SPLITTING))
+
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
+void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
+                          pmd_t *pmdp);
+#endif
 #endif
 
 #define PMD_BIT_FUNC(fn,op) \
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 01baef07cd0c..90aa4583b308 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -226,7 +226,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 #define pte_dirty(pte)          (pte_isset((pte), L_PTE_DIRTY))
 #define pte_young(pte)          (pte_isset((pte), L_PTE_YOUNG))
 #define pte_exec(pte)           (pte_isclear((pte), L_PTE_XN))
-#define pte_special(pte)        (0)
 
 #define pte_valid_user(pte)     \
         (pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
@@ -245,7 +244,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
         unsigned long ext = 0;
 
         if (addr < TASK_SIZE && pte_valid_user(pteval)) {
-                __sync_icache_dcache(pteval);
+                if (!pte_special(pteval))
+                        __sync_icache_dcache(pteval);
                 ext |= PTE_EXT_NG;
         }
 
@@ -264,8 +264,6 @@ PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
 PTE_BIT_FUNC(mkexec,   &= ~L_PTE_XN);
 PTE_BIT_FUNC(mknexec,   |= L_PTE_XN);
 
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
         const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 2ec765c39ab4..18f5a554134f 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -49,12 +49,6 @@ extern void smp_init_cpus(void);
 extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
 
 /*
- * Boot a secondary CPU, and assign it the specified idle task.
- * This also gives us the initial stack to use for this CPU.
- */
-extern int boot_secondary(unsigned int cpu, struct task_struct *);
-
-/*
  * Called from platform specific assembly code, this is the
  * secondary CPU entry point.
  */
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index a252c0bfacf5..0ad7d490ee6f 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -8,6 +8,7 @@
 #include <linux/cpumask.h>
 #include <linux/err.h>
 
+#include <asm/cpu.h>
 #include <asm/cputype.h>
 
 /*
@@ -25,6 +26,20 @@ static inline bool is_smp(void)
 #endif
 }
 
+/**
+ * smp_cpuid_part() - return part id for a given cpu
+ * @cpu:        logical cpu id.
+ *
+ * Return: part id of logical cpu passed as argument.
+ */
+static inline unsigned int smp_cpuid_part(int cpu)
+{
+        struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpu);
+
+        return is_smp() ? cpu_info->cpuid & ARM_CPU_PART_MASK :
+                          read_cpuid_part();
+}
+
 /* all SMP configurations have the extended CPUID registers */
 #ifndef CONFIG_MMU
 #define tlb_ops_need_broadcast()        0
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index 4651f6999b7d..e86c985b8c7a 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -63,8 +63,8 @@ static inline void syscall_get_arguments(struct task_struct *task,
         if (i + n > SYSCALL_MAX_ARGS) {
                 unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
                 unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
-                pr_warning("%s called with max args %d, handling only %d\n",
-                           __func__, i + n, SYSCALL_MAX_ARGS);
+                pr_warn("%s called with max args %d, handling only %d\n",
+                        __func__, i + n, SYSCALL_MAX_ARGS);
                 memset(args_bad, 0, n_bad * sizeof(args[0]));
                 n = SYSCALL_MAX_ARGS - i;
         }
@@ -88,8 +88,8 @@ static inline void syscall_set_arguments(struct task_struct *task,
                 return;
 
         if (i + n > SYSCALL_MAX_ARGS) {
-                pr_warning("%s called with max args %d, handling only %d\n",
-                           __func__, i + n, SYSCALL_MAX_ARGS);
+                pr_warn("%s called with max args %d, handling only %d\n",
+                        __func__, i + n, SYSCALL_MAX_ARGS);
                 n = SYSCALL_MAX_ARGS - i;
         }
 
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index f1a0dace3efe..3cadb726ec88 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -35,12 +35,39 @@
 
 #define MMU_GATHER_BUNDLE       8
 
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+static inline void __tlb_remove_table(void *_table)
+{
+        free_page_and_swap_cache((struct page *)_table);
+}
+
+struct mmu_table_batch {
+        struct rcu_head         rcu;
+        unsigned int            nr;
+        void                    *tables[0];
+};
+
+#define MAX_TABLE_BATCH         \
+        ((PAGE_SIZE - sizeof(struct mmu_table_batch)) / sizeof(void *))
+
+extern void tlb_table_flush(struct mmu_gather *tlb);
+extern void tlb_remove_table(struct mmu_gather *tlb, void *table);
+
+#define tlb_remove_entry(tlb, entry)    tlb_remove_table(tlb, entry)
+#else
+#define tlb_remove_entry(tlb, entry)    tlb_remove_page(tlb, entry)
+#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
+
 /*
  * TLB handling.  This allows us to remove pages from the page
  * tables, and efficiently handle the TLB issues.
  */
 struct mmu_gather {
         struct mm_struct        *mm;
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+        struct mmu_table_batch  *batch;
+        unsigned int            need_flush;
+#endif
         unsigned int            fullmm;
         struct vm_area_struct   *vma;
         unsigned long           start, end;
@@ -101,6 +128,9 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb)
 static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb)
 {
         tlb_flush(tlb);
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+        tlb_table_flush(tlb);
+#endif
 }
 
 static inline void tlb_flush_mmu_free(struct mmu_gather *tlb)
@@ -129,6 +159,10 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start
         tlb->pages = tlb->local;
         tlb->nr = 0;
         __tlb_alloc_page(tlb);
+
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+        tlb->batch = NULL;
+#endif
 }
 
 static inline void
@@ -205,7 +239,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
         tlb_add_flush(tlb, addr + SZ_1M);
 #endif
 
-        tlb_remove_page(tlb, pte);
+        tlb_remove_entry(tlb, pte);
 }
 
 static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
@@ -213,7 +247,7 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 {
 #ifdef CONFIG_ARM_LPAE
         tlb_add_flush(tlb, addr);
-        tlb_remove_page(tlb, virt_to_page(pmdp));
+        tlb_remove_entry(tlb, virt_to_page(pmdp));
 #endif
 }
 
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 83259b873333..5f833f7adba1 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -1,6 +1,9 @@
 #ifndef __ASMARM_TLS_H
 #define __ASMARM_TLS_H
 
+#include <linux/compiler.h>
+#include <asm/thread_info.h>
+
 #ifdef __ASSEMBLY__
 #include <asm/asm-offsets.h>
         .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
@@ -50,6 +53,49 @@
 #endif
 
 #ifndef __ASSEMBLY__
+
+static inline void set_tls(unsigned long val)
+{
+        struct thread_info *thread;
+
+        thread = current_thread_info();
+
+        thread->tp_value[0] = val;
+
+        /*
+         * This code runs with preemption enabled and therefore must
+         * be reentrant with respect to switch_tls.
+         *
+         * We need to ensure ordering between the shadow state and the
+         * hardware state, so that we don't corrupt the hardware state
+         * with a stale shadow state during context switch.
+         *
+         * If we're preempted here, switch_tls will load TPIDRURO from
+         * thread_info upon resuming execution and the following mcr
+         * is merely redundant.
+         */
+        barrier();
+
+        if (!tls_emu) {
+                if (has_tls_reg) {
+                        asm("mcr p15, 0, %0, c13, c0, 3"
+                            : : "r" (val));
+                } else {
+#ifdef CONFIG_KUSER_HELPERS
+                        /*
+                         * User space must never try to access this
+                         * directly.  Expect your app to break
+                         * eventually if you do so.  The user helper
+                         * at 0xffff0fe0 must be used instead.  (see
+                         * entry-armv.S for details)
+                         */
+                        *((unsigned int *)0xffff0ff0) = val;
+#endif
+                }
+
+        }
+}
+
 static inline unsigned long get_tpuser(void)
 {
         unsigned long reg = 0;
@@ -59,5 +105,23 @@ static inline unsigned long get_tpuser(void)
 
         return reg;
 }
+
+static inline void set_tpuser(unsigned long val)
+{
+        /* Since TPIDRURW is fully context-switched (unlike TPIDRURO),
+         * we need not update thread_info.
+         */
+        if (has_tls_reg && !tls_emu) {
+                asm("mcr p15, 0, %0, c13, c0, 2"
+                    : : "r" (val));
+        }
+}
+
+static inline void flush_tls(void)
+{
+        set_tls(0);
+        set_tpuser(0);
+}
+
 #endif
 #endif  /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index a4cd7af475e9..4767eb9caa78 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -107,8 +107,11 @@ static inline void set_fs(mm_segment_t fs)
 extern int __get_user_1(void *);
 extern int __get_user_2(void *);
 extern int __get_user_4(void *);
-extern int __get_user_lo8(void *);
+extern int __get_user_32t_8(void *);
 extern int __get_user_8(void *);
+extern int __get_user_64t_1(void *);
+extern int __get_user_64t_2(void *);
+extern int __get_user_64t_4(void *);
 
 #define __GUP_CLOBBER_1 "lr", "cc"
 #ifdef CONFIG_CPU_USE_DOMAINS
@@ -117,7 +120,7 @@ extern int __get_user_8(void *);
 #define __GUP_CLOBBER_2 "lr", "cc"
 #endif
 #define __GUP_CLOBBER_4 "lr", "cc"
-#define __GUP_CLOBBER_lo8 "lr", "cc"
+#define __GUP_CLOBBER_32t_8 "lr", "cc"
 #define __GUP_CLOBBER_8 "lr", "cc"
 
 #define __get_user_x(__r2,__p,__e,__l,__s)                              \
@@ -131,12 +134,30 @@ extern int __get_user_8(void *);
 
 /* narrowing a double-word get into a single 32bit word register: */
 #ifdef __ARMEB__
-#define __get_user_xb(__r2, __p, __e, __l, __s)                         \
-        __get_user_x(__r2, __p, __e, __l, lo8)
+#define __get_user_x_32t(__r2, __p, __e, __l, __s)                              \
+        __get_user_x(__r2, __p, __e, __l, 32t_8)
 #else
-#define __get_user_xb __get_user_x
+#define __get_user_x_32t __get_user_x
 #endif
 
+/*
+ * storing result into proper least significant word of 64bit target var,
+ * different only for big endian case where 64 bit __r2 lsw is r3:
+ */
+#ifdef __ARMEB__
+#define __get_user_x_64t(__r2, __p, __e, __l, __s)                      \
+           __asm__ __volatile__ (                                       \
+                __asmeq("%0", "r0") __asmeq("%1", "r2")                 \
+                __asmeq("%3", "r1")                                     \
+                "bl     __get_user_64t_" #__s                           \
+                : "=&r" (__e), "=r" (__r2)                              \
+                : "0" (__p), "r" (__l)                                  \
+                : __GUP_CLOBBER_##__s)
+#else
+#define __get_user_x_64t __get_user_x
+#endif
+
+
 #define __get_user_check(x,p)                                                   \
         ({                                                              \
                 unsigned long __limit = current_thread_info()->addr_limit - 1; \
@@ -146,17 +167,26 @@ extern int __get_user_8(void *);
                 register int __e asm("r0");                             \
                 switch (sizeof(*(__p))) {                               \
                 case 1:                                                 \
-                        __get_user_x(__r2, __p, __e, __l, 1);           \
+                        if (sizeof((x)) >= 8)                           \
+                                __get_user_x_64t(__r2, __p, __e, __l, 1); \
+                        else                                            \
+                                __get_user_x(__r2, __p, __e, __l, 1);   \
                         break;                                          \
                 case 2:                                                 \
-                        __get_user_x(__r2, __p, __e, __l, 2);           \
+                        if (sizeof((x)) >= 8)                           \
+                                __get_user_x_64t(__r2, __p, __e, __l, 2); \
+                        else                                            \
+                                __get_user_x(__r2, __p, __e, __l, 2);   \
                         break;                                          \
                 case 4:                                                 \
-                        __get_user_x(__r2, __p, __e, __l, 4);           \
+                        if (sizeof((x)) >= 8)                           \
+                                __get_user_x_64t(__r2, __p, __e, __l, 4); \
+                        else                                            \
+                                __get_user_x(__r2, __p, __e, __l, 4);   \
                         break;                                          \
                 case 8:                                                 \
                         if (sizeof((x)) < 8)                            \
-                                __get_user_xb(__r2, __p, __e, __l, 4);  \
+                                __get_user_x_32t(__r2, __p, __e, __l, 4); \
                         else                                            \
                                 __get_user_x(__r2, __p, __e, __l, 8);   \
                         break;                                          \
diff --git a/arch/arm/include/asm/xen/page-coherent.h b/arch/arm/include/asm/xen/page-coherent.h
index 1109017499e5..e8275ea88e88 100644
--- a/arch/arm/include/asm/xen/page-coherent.h
+++ b/arch/arm/include/asm/xen/page-coherent.h
@@ -26,25 +26,14 @@ static inline void xen_dma_map_page(struct device *hwdev, struct page *page,
         __generic_dma_ops(hwdev)->map_page(hwdev, page, offset, size, dir, attrs);
 }
 
-static inline void xen_dma_unmap_page(struct device *hwdev, dma_addr_t handle,
+void xen_dma_unmap_page(struct device *hwdev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir,
-                struct dma_attrs *attrs)
-{
-        if (__generic_dma_ops(hwdev)->unmap_page)
-                __generic_dma_ops(hwdev)->unmap_page(hwdev, handle, size, dir, attrs);
-}
+                struct dma_attrs *attrs);
 
-static inline void xen_dma_sync_single_for_cpu(struct device *hwdev,
-                dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
-        if (__generic_dma_ops(hwdev)->sync_single_for_cpu)
-                __generic_dma_ops(hwdev)->sync_single_for_cpu(hwdev, handle, size, dir);
-}
+void xen_dma_sync_single_for_cpu(struct device *hwdev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir);
+
+void xen_dma_sync_single_for_device(struct device *hwdev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir);
 
-static inline void xen_dma_sync_single_for_device(struct device *hwdev,
-                dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
-        if (__generic_dma_ops(hwdev)->sync_single_for_device)
-                __generic_dma_ops(hwdev)->sync_single_for_device(hwdev, handle, size, dir);
-}
 #endif /* _ASM_ARM_XEN_PAGE_COHERENT_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index ded062f9b358..135c24a5ba26 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -33,7 +33,6 @@ typedef struct xpaddr {
 #define INVALID_P2M_ENTRY      (~0UL)
 
 unsigned long __pfn_to_mfn(unsigned long pfn);
-unsigned long __mfn_to_pfn(unsigned long mfn);
 extern struct rb_root phys_to_mach;
 
 static inline unsigned long pfn_to_mfn(unsigned long pfn)
@@ -51,14 +50,6 @@ static inline unsigned long pfn_to_mfn(unsigned long pfn)
 
 static inline unsigned long mfn_to_pfn(unsigned long mfn)
 {
-        unsigned long pfn;
-
-        if (phys_to_mach.rb_node != NULL) {
-                pfn = __mfn_to_pfn(mfn);
-                if (pfn != INVALID_P2M_ENTRY)
-                        return pfn;
-        }
-
         return mfn;
 }
 
diff --git a/arch/arm/include/debug/bcm63xx.S b/arch/arm/include/debug/bcm63xx.S
new file mode 100644
index 000000000000..e7164d570f44
--- /dev/null
+++ b/arch/arm/include/debug/bcm63xx.S
@@ -0,0 +1,33 @@
+/*
+ * Broadcom BCM63xx low-level UART debug
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_bcm63xx.h>
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =CONFIG_DEBUG_UART_PHYS
+        ldr     \rv, =CONFIG_DEBUG_UART_VIRT
+        .endm
+
+        .macro  senduart, rd, rx
+        /* word access do not work */
+        strb    \rd, [\rx, #UART_FIFO_REG]
+        .endm
+
+        .macro  waituart, rd, rx
+1001:   ldr     \rd, [\rx, #UART_IR_REG]
+        tst     \rd, #(1 << UART_IR_TXEMPTY)
+        beq     1001b
+        .endm
+
+        .macro  busyuart, rd, rx
+1002:   ldr     \rd, [\rx, #UART_IR_REG]
+        tst     \rd, #(1 << UART_IR_TXTRESH)
+        beq     1002b
+        .endm
diff --git a/arch/arm/include/debug/meson.S b/arch/arm/include/debug/meson.S
new file mode 100644
index 000000000000..1bae99bf6f11
--- /dev/null
+++ b/arch/arm/include/debug/meson.S
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 Carlo Caione
+ * Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define MESON_AO_UART_WFIFO             0x0
+#define MESON_AO_UART_STATUS            0xc
+
+#define MESON_AO_UART_TX_FIFO_EMPTY     (1 << 22)
+#define MESON_AO_UART_TX_FIFO_FULL      (1 << 21)
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =(CONFIG_DEBUG_UART_PHYS)          @ physical
+        ldr     \rv, =(CONFIG_DEBUG_UART_VIRT)          @ virtual
+        .endm
+
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #MESON_AO_UART_WFIFO]
+        .endm
+
+        .macro  busyuart,rd,rx
+1002:   ldr     \rd, [\rx, #MESON_AO_UART_STATUS]
+        tst     \rd, #MESON_AO_UART_TX_FIFO_EMPTY
+        beq     1002b
+        .endm
+
+        .macro  waituart,rd,rx
+1001:   ldr     \rd, [\rx, #MESON_AO_UART_STATUS]
+        tst     \rd, #MESON_AO_UART_TX_FIFO_FULL
+        bne     1001b
+        .endm
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index e6ebdd3471e5..09ee408c1a67 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -25,6 +25,7 @@
 
 #define __KVM_HAVE_GUEST_DEBUG
 #define __KVM_HAVE_IRQ_LINE
+#define __KVM_HAVE_READONLY_MEM
 
 #define KVM_REG_SIZE(id)                                                \
         (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
@@ -173,6 +174,7 @@ struct kvm_arch_memory_slot {
 #define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
 #define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
 #define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
+#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
 
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT          24
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index f7b450f97e68..a88671cfe1ff 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -98,6 +98,14 @@ EXPORT_SYMBOL(__clear_user);
 EXPORT_SYMBOL(__get_user_1);
 EXPORT_SYMBOL(__get_user_2);
 EXPORT_SYMBOL(__get_user_4);
+EXPORT_SYMBOL(__get_user_8);
+
+#ifdef __ARMEB__
+EXPORT_SYMBOL(__get_user_64t_1);
+EXPORT_SYMBOL(__get_user_64t_2);
+EXPORT_SYMBOL(__get_user_64t_4);
+EXPORT_SYMBOL(__get_user_32t_8);
+#endif
 
 EXPORT_SYMBOL(__put_user_1);
 EXPORT_SYMBOL(__put_user_2);
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
index 7807ef58a2ab..528f8af2addb 100644
--- a/arch/arm/kernel/atags_parse.c
+++ b/arch/arm/kernel/atags_parse.c
@@ -130,7 +130,7 @@ static int __init parse_tag_cmdline(const struct tag *tag)
         strlcat(default_command_line, tag->u.cmdline.cmdline,
                 COMMAND_LINE_SIZE);
 #elif defined(CONFIG_CMDLINE_FORCE)
-        pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
+        pr_warn("Ignoring tag cmdline (using the default kernel command line)\n");
 #else
         strlcpy(default_command_line, tag->u.cmdline.cmdline,
                 COMMAND_LINE_SIZE);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 36276cdccfbc..2f5555d307b3 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -146,7 +146,7 @@ ENDPROC(__und_invalid)
 #define SPFIX(code...)
 #endif
 
-        .macro  svc_entry, stack_hole=0
+        .macro  svc_entry, stack_hole=0, trace=1
  UNWIND(.fnstart                )
  UNWIND(.save {r0 - pc}         )
         sub     sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
@@ -182,9 +182,11 @@ ENDPROC(__und_invalid)
         @
         stmia   r7, {r2 - r6}
 
+        .if \trace
 #ifdef CONFIG_TRACE_IRQFLAGS
         bl      trace_hardirqs_off
 #endif
+        .endif
         .endm
 
         .align  5
@@ -295,6 +297,15 @@ __pabt_svc:
 ENDPROC(__pabt_svc)
 
         .align  5
+__fiq_svc:
+        svc_entry trace=0
+        mov     r0, sp                          @ struct pt_regs *regs
+        bl      handle_fiq_as_nmi
+        svc_exit_via_fiq
+ UNWIND(.fnend          )
+ENDPROC(__fiq_svc)
+
+        .align  5
 .LCcralign:
         .word   cr_alignment
 #ifdef MULTI_DABORT
@@ -305,6 +316,46 @@ ENDPROC(__pabt_svc)
         .word   fp_enter
 
 /*
+ * Abort mode handlers
+ */
+
+@
+@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
+@ and reuses the same macros. However in abort mode we must also
+@ save/restore lr_abt and spsr_abt to make nested aborts safe.
+@
+        .align 5
+__fiq_abt:
+        svc_entry trace=0
+
+ ARM(   msr     cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( mov     r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( msr     cpsr_c, r0 )
+        mov     r1, lr          @ Save lr_abt
+        mrs     r2, spsr        @ Save spsr_abt, abort is now safe
+ ARM(   msr     cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( mov     r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( msr     cpsr_c, r0 )
+        stmfd   sp!, {r1 - r2}
+
+        add     r0, sp, #8                      @ struct pt_regs *regs
+        bl      handle_fiq_as_nmi
+
+        ldmfd   sp!, {r1 - r2}
+ ARM(   msr     cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( mov     r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( msr     cpsr_c, r0 )
+        mov     lr, r1          @ Restore lr_abt, abort is unsafe
+        msr     spsr_cxsf, r2   @ Restore spsr_abt
+ ARM(   msr     cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( mov     r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+ THUMB( msr     cpsr_c, r0 )
+
+        svc_exit_via_fiq
+ UNWIND(.fnend          )
+ENDPROC(__fiq_abt)
+
+/*
  * User mode handlers
  *
  * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
@@ -314,13 +365,16 @@ ENDPROC(__pabt_svc)
 #error "sizeof(struct pt_regs) must be a multiple of 8"
 #endif
 
-        .macro  usr_entry
+        .macro  usr_entry, trace=1
  UNWIND(.fnstart        )
  UNWIND(.cantunwind     )       @ don't unwind the user space
         sub     sp, sp, #S_FRAME_SIZE
  ARM(   stmib   sp, {r1 - r12}  )
  THUMB( stmia   sp, {r0 - r12}  )
 
+ ATRAP( mrc     p15, 0, r7, c1, c0, 0)
+ ATRAP( ldr     r8, .LCcralign)
+
         ldmia   r0, {r3 - r5}
         add     r0, sp, #S_PC           @ here for interlock avoidance
         mov     r6, #-1                 @  ""  ""     ""        ""
@@ -328,6 +382,8 @@ ENDPROC(__pabt_svc)
         str     r3, [sp]                @ save the "real" r0 copied
                                         @ from the exception stack
 
+ ATRAP( ldr     r8, [r8, #0])
+
         @
         @ We are now ready to fill in the remaining blanks on the stack:
         @
@@ -341,20 +397,21 @@ ENDPROC(__pabt_svc)
  ARM(   stmdb   r0, {sp, lr}^                   )
  THUMB( store_user_sp_lr r0, r1, S_SP - S_PC    )
 
-        @
         @ Enable the alignment trap while in kernel mode
-        @
-        alignment_trap r0, .LCcralign
+ ATRAP( teq     r8, r7)
+ ATRAP( mcrne   p15, 0, r8, c1, c0, 0)
 
         @
         @ Clear FP to mark the first stack frame
         @
         zero_fp
 
+        .if     \trace
 #ifdef CONFIG_IRQSOFF_TRACER
         bl      trace_hardirqs_off
 #endif
         ct_user_exit save = 0
+        .endif
         .endm
 
         .macro  kuser_cmpxchg_check
@@ -683,6 +740,17 @@ ENTRY(ret_from_exception)
 ENDPROC(__pabt_usr)
 ENDPROC(ret_from_exception)
 
+        .align  5
+__fiq_usr:
+        usr_entry trace=0
+        kuser_cmpxchg_check
+        mov     r0, sp                          @ struct pt_regs *regs
+        bl      handle_fiq_as_nmi
+        get_thread_info tsk
+        restore_user_regs fast = 0, offset = 0
+ UNWIND(.fnend          )
+ENDPROC(__fiq_usr)
+
 /*
  * Register switch for ARMv3 and ARMv4 processors
  * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
@@ -1118,17 +1186,29 @@ vector_addrexcptn:
         b       vector_addrexcptn
 
 /*=============================================================================
- * Undefined FIQs
+ * FIQ "NMI" handler
  *-----------------------------------------------------------------------------
- * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
- * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
- * Basically to switch modes, we *HAVE* to clobber one register...  brain
- * damage alert!  I don't think that we can execute any code in here in any
- * other mode than FIQ...  Ok you can switch to another mode, but you can't
- * get out of that mode without clobbering one register.
+ * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
+ * systems.
  */
-vector_fiq:
-        subs    pc, lr, #4
+        vector_stub     fiq, FIQ_MODE, 4
+
+        .long   __fiq_usr                       @  0  (USR_26 / USR_32)
+        .long   __fiq_svc                       @  1  (FIQ_26 / FIQ_32)
+        .long   __fiq_svc                       @  2  (IRQ_26 / IRQ_32)
+        .long   __fiq_svc                       @  3  (SVC_26 / SVC_32)
+        .long   __fiq_svc                       @  4
+        .long   __fiq_svc                       @  5
+        .long   __fiq_svc                       @  6
+        .long   __fiq_abt                       @  7
+        .long   __fiq_svc                       @  8
+        .long   __fiq_svc                       @  9
+        .long   __fiq_svc                       @  a
+        .long   __fiq_svc                       @  b
+        .long   __fiq_svc                       @  c
+        .long   __fiq_svc                       @  d
+        .long   __fiq_svc                       @  e
+        .long   __fiq_svc                       @  f
 
         .globl  vector_fiq_offset
         .equ    vector_fiq_offset, vector_fiq
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index e52fe5a2d843..6bb09d4abdea 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -366,7 +366,7 @@ ENTRY(vector_swi)
         str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
 #endif
         zero_fp
-        alignment_trap ip, __cr_alignment
+        alignment_trap r10, ip, __cr_alignment
         enable_irq
         ct_user_exit
         get_thread_info tsk
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 8db307d0954b..4176df721bf0 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -37,11 +37,19 @@
 #endif
         .endm
 
-        .macro  alignment_trap, rtemp, label
 #ifdef CONFIG_ALIGNMENT_TRAP
-        ldr     \rtemp, \label
-        ldr     \rtemp, [\rtemp]
-        mcr     p15, 0, \rtemp, c1, c0
+#define ATRAP(x...) x
+#else
+#define ATRAP(x...)
+#endif
+
+        .macro  alignment_trap, rtmp1, rtmp2, label
+#ifdef CONFIG_ALIGNMENT_TRAP
+        mrc     p15, 0, \rtmp2, c1, c0, 0
+        ldr     \rtmp1, \label
+        ldr     \rtmp1, [\rtmp1]
+        teq     \rtmp1, \rtmp2
+        mcrne   p15, 0, \rtmp1, c1, c0, 0
 #endif
         .endm
 
@@ -208,26 +216,49 @@
 #endif
         .endif
         msr     spsr_cxsf, \rpsr
-#if defined(CONFIG_CPU_V6)
-        ldr     r0, [sp]
-        strex   r1, r2, [sp]                    @ clear the exclusive monitor
-        ldmib   sp, {r1 - pc}^                  @ load r1 - pc, cpsr
-#elif defined(CONFIG_CPU_32v6K)
-        clrex                                   @ clear the exclusive monitor
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
-#else
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
+        @ We must avoid clrex due to Cortex-A15 erratum #830321
+        sub     r0, sp, #4                      @ uninhabited address
+        strex   r1, r2, [r0]                    @ clear the exclusive monitor
 #endif
+        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        .endm
+
+        @
+        @ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
+        @
+        @ This macro acts in a similar manner to svc_exit but switches to FIQ
+        @ mode to restore the final part of the register state.
+        @
+        @ We cannot use the normal svc_exit procedure because that would
+        @ clobber spsr_svc (FIQ could be delivered during the first few
+        @ instructions of vector_swi meaning its contents have not been
+        @ saved anywhere).
+        @
+        @ Note that, unlike svc_exit, this macro also does not allow a caller
+        @ supplied rpsr. This is because the FIQ exceptions are not re-entrant
+        @ and the handlers cannot call into the scheduler (meaning the value
+        @ on the stack remains correct).
+        @
+        .macro  svc_exit_via_fiq
+        mov     r0, sp
+        ldmib   r0, {r1 - r14}  @ abort is deadly from here onward (it will
+                                @ clobber state restored below)
+        msr     cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+        add     r8, r0, #S_PC
+        ldr     r9, [r0, #S_PSR]
+        msr     spsr_cxsf, r9
+        ldr     r0, [r0, #S_R0]
+        ldmia   r8, {pc}^
         .endm
 
         .macro  restore_user_regs, fast = 0, offset = 0
         ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
         ldr     lr, [sp, #\offset + S_PC]!      @ get pc
         msr     spsr_cxsf, r1                   @ save in spsr_svc
-#if defined(CONFIG_CPU_V6)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
+        @ We must avoid clrex due to Cortex-A15 erratum #830321
         strex   r1, r2, [sp]                    @ clear the exclusive monitor
-#elif defined(CONFIG_CPU_32v6K)
-        clrex                                   @ clear the exclusive monitor
 #endif
         .if     \fast
         ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
@@ -261,7 +292,10 @@
         .endif
         ldr     lr, [sp, #S_SP]                 @ top of the stack
         ldrd    r0, r1, [sp, #S_LR]             @ calling lr and pc
-        clrex                                   @ clear the exclusive monitor
+
+        @ We must avoid clrex due to Cortex-A15 erratum #830321
+        strex   r2, r1, [sp, #S_LR]             @ clear the exclusive monitor
+
         stmdb   lr!, {r0, r1, \rpsr}            @ calling lr and rfe context
         ldmia   sp, {r0 - r12}
         mov     sp, lr
@@ -269,6 +303,25 @@
         rfeia   sp!
         .endm
 
+        @
+        @ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
+        @
+        @ For full details see non-Thumb implementation above.
+        @
+        .macro  svc_exit_via_fiq
+        add     r0, sp, #S_R2
+        ldr     lr, [sp, #S_LR]
+        ldr     sp, [sp, #S_SP] @ abort is deadly from here onward (it will
+                                @ clobber state restored below)
+        ldmia   r0, {r2 - r12}
+        mov     r1, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+        msr     cpsr_c, r1
+        sub     r0, #S_R2
+        add     r8, r0, #S_PC
+        ldmia   r0, {r0 - r1}
+        rfeia   r8
+        .endm
+
 #ifdef CONFIG_CPU_V7M
         /*
          * Note we don't need to do clrex here as clearing the local monitor is
@@ -282,13 +335,16 @@
         .endm
 #else   /* ifdef CONFIG_CPU_V7M */
         .macro  restore_user_regs, fast = 0, offset = 0
-        clrex                                   @ clear the exclusive monitor
         mov     r2, sp
         load_user_sp_lr r2, r3, \offset + S_SP  @ calling sp, lr
         ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
         ldr     lr, [sp, #\offset + S_PC]       @ get pc
         add     sp, sp, #\offset + S_SP
         msr     spsr_cxsf, r1                   @ save in spsr_svc
+
+        @ We must avoid clrex due to Cortex-A15 erratum #830321
+        strex   r1, r2, [sp]                    @ clear the exclusive monitor
+
         .if     \fast
         ldmdb   sp, {r1 - r12}                  @ get calling r1 - r12
         .else
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 918875d96d5d..b37752a96652 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -52,7 +52,8 @@
                 (unsigned)&vector_fiq_offset;           \
         })
 
-static unsigned long no_fiq_insn;
+static unsigned long dfl_fiq_insn;
+static struct pt_regs dfl_fiq_regs;
 
 /* Default reacquire function
  * - we always relinquish FIQ control
@@ -60,8 +61,15 @@ static unsigned long no_fiq_insn;
  */
 static int fiq_def_op(void *ref, int relinquish)
 {
-        if (!relinquish)
-                set_fiq_handler(&no_fiq_insn, sizeof(no_fiq_insn));
+        if (!relinquish) {
+                /* Restore default handler and registers */
+                local_fiq_disable();
+                set_fiq_regs(&dfl_fiq_regs);
+                set_fiq_handler(&dfl_fiq_insn, sizeof(dfl_fiq_insn));
+                local_fiq_enable();
+
+                /* FIXME: notify irq controller to standard enable FIQs */
+        }
 
         return 0;
 }
@@ -150,6 +158,7 @@ EXPORT_SYMBOL(disable_fiq);
 void __init init_FIQ(int start)
 {
         unsigned offset = FIQ_OFFSET;
-        no_fiq_insn = *(unsigned long *)(0xffff0000 + offset);
+        dfl_fiq_insn = *(unsigned long *)(0xffff0000 + offset);
+        get_fiq_regs(&dfl_fiq_regs);
         fiq_start = start;
 }
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
index bb8b79648643..c4cc50e58c13 100644
--- a/arch/arm/kernel/hibernate.c
+++ b/arch/arm/kernel/hibernate.c
@@ -21,8 +21,7 @@
 #include <asm/idmap.h>
 #include <asm/suspend.h>
 #include <asm/memory.h>
-
-extern const void __nosave_begin, __nosave_end;
+#include <asm/sections.h>
 
 int pfn_is_nosave(unsigned long pfn)
 {
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 4d963fb66e3f..b5b452f90f76 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -113,8 +113,8 @@ static u32 read_wb_reg(int n)
         GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
         GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
         default:
-                pr_warning("attempt to read from unknown breakpoint "
-                                "register %d\n", n);
+                pr_warn("attempt to read from unknown breakpoint register %d\n",
+                        n);
         }
 
         return val;
@@ -128,8 +128,8 @@ static void write_wb_reg(int n, u32 val)
         GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
         GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
         default:
-                pr_warning("attempt to write to unknown breakpoint "
-                                "register %d\n", n);
+                pr_warn("attempt to write to unknown breakpoint register %d\n",
+                        n);
         }
         isb();
 }
@@ -292,7 +292,7 @@ int hw_breakpoint_slots(int type)
         case TYPE_DATA:
                 return get_num_wrps();
         default:
-                pr_warning("unknown slot type: %d\n", type);
+                pr_warn("unknown slot type: %d\n", type);
                 return 0;
         }
 }
@@ -365,7 +365,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
         }
 
         if (i == max_slots) {
-                pr_warning("Can't find any breakpoint slot\n");
+                pr_warn("Can't find any breakpoint slot\n");
                 return -EBUSY;
         }
 
@@ -417,7 +417,7 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
         }
 
         if (i == max_slots) {
-                pr_warning("Can't find any breakpoint slot\n");
+                pr_warn("Can't find any breakpoint slot\n");
                 return;
         }
 
@@ -894,8 +894,8 @@ static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
 {
         int cpu = smp_processor_id();
 
-        pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
-                   instr, cpu);
+        pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
+                instr, cpu);
 
         /* Set the error flag for this CPU and skip the faulting instruction. */
         cpumask_set_cpu(cpu, &debug_err_mask);
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c4257604513..7c81ec428b9b 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -65,24 +65,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
  */
 void handle_IRQ(unsigned int irq, struct pt_regs *regs)
 {
-        struct pt_regs *old_regs = set_irq_regs(regs);
-
-        irq_enter();
-
-        /*
-         * Some hardware gives randomly wrong interrupts.  Rather
-         * than crashing, do something sensible.
-         */
-        if (unlikely(irq >= nr_irqs)) {
-                if (printk_ratelimit())
-                        printk(KERN_WARNING "Bad IRQ%u\n", irq);
-                ack_bad_irq(irq);
-        } else {
-                generic_handle_irq(irq);
-        }
-
-        irq_exit();
-        set_irq_regs(old_regs);
+        __handle_domain_irq(NULL, irq, false, regs);
 }
 
 /*
@@ -175,7 +158,7 @@ static bool migrate_one_irq(struct irq_desc *desc)
         c = irq_data_get_irq_chip(d);
         if (!c->irq_set_affinity)
                 pr_debug("IRQ%u: unable to set affinity\n", d->irq);
-        else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
+        else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
                 cpumask_copy(d->affinity, affinity);
 
         return ret;
@@ -205,8 +188,8 @@ void migrate_irqs(void)
                 raw_spin_unlock(&desc->lock);
 
                 if (affinity_broken && printk_ratelimit())
-                        pr_warning("IRQ%u no longer affine to CPU%u\n", i,
-                                smp_processor_id());
+                        pr_warn("IRQ%u no longer affine to CPU%u\n",
+                                i, smp_processor_id());
         }
 
         local_irq_restore(flags);
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
index 08d731294bcd..b206d7790c77 100644
--- a/arch/arm/kernel/kprobes-test.c
+++ b/arch/arm/kernel/kprobes-test.c
@@ -110,10 +110,13 @@
  *
  *      @ TESTCASE_START
  *      bl      __kprobes_test_case_start
- *      @ start of inline data...
+ *      .pushsection .rodata
+ *      "10:
  *      .ascii "mov r0, r7"     @ text title for test case
  *      .byte   0
- *      .align  2, 0
+ *      .popsection
+ *      @ start of inline data...
+ *      .word   10b             @ pointer to title in .rodata section
  *
  *      @ TEST_ARG_REG
  *      .byte   ARG_TYPE_REG
@@ -971,7 +974,7 @@ void __naked __kprobes_test_case_start(void)
         __asm__ __volatile__ (
                 "stmdb  sp!, {r4-r11}                           \n\t"
                 "sub    sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
-                "bic    r0, lr, #1  @ r0 = inline title string  \n\t"
+                "bic    r0, lr, #1  @ r0 = inline data          \n\t"
                 "mov    r1, sp                                  \n\t"
                 "bl     kprobes_test_case_start                 \n\t"
                 "bx     r0                                      \n\t"
@@ -1349,15 +1352,14 @@ static unsigned long next_instruction(unsigned long pc)
         return pc + 4;
 }
 
-static uintptr_t __used kprobes_test_case_start(const char *title, void *stack)
+static uintptr_t __used kprobes_test_case_start(const char **title, void *stack)
 {
         struct test_arg *args;
         struct test_arg_end *end_arg;
         unsigned long test_code;
 
-        args = (struct test_arg *)PTR_ALIGN(title + strlen(title) + 1, 4);
-
-        current_title = title;
+        current_title = *title++;
+        args = (struct test_arg *)title;
         current_args = args;
         current_stack = stack;
 
diff --git a/arch/arm/kernel/kprobes-test.h b/arch/arm/kernel/kprobes-test.h
index eecc90a0fd91..4430990e90e7 100644
--- a/arch/arm/kernel/kprobes-test.h
+++ b/arch/arm/kernel/kprobes-test.h
@@ -111,11 +111,14 @@ struct test_arg_end {
 #define TESTCASE_START(title)                                   \
         __asm__ __volatile__ (                                  \
         "bl     __kprobes_test_case_start               \n\t"   \
+        ".pushsection .rodata                           \n\t"   \
+        "10:                                            \n\t"   \
         /* don't use .asciz here as 'title' may be */           \
         /* multiple strings to be concatenated.  */             \
         ".ascii "#title"                                \n\t"   \
         ".byte  0                                       \n\t"   \
-        ".align 2, 0                                    \n\t"
+        ".popsection                                    \n\t"   \
+        ".word  10b                                     \n\t"
 
 #define TEST_ARG_REG(reg, val)                                  \
         ".byte  "__stringify(ARG_TYPE_REG)"             \n\t"   \
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 45e478157278..6a4dffefd357 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -91,6 +91,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                         break;
 
                 case R_ARM_ABS32:
+                case R_ARM_TARGET1:
                         *(u32 *)loc += sym->st_value;
                         break;
 
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index e6a6edbec613..eb2c4d55666b 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -76,21 +76,15 @@ static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
 
 static void cpu_pmu_enable_percpu_irq(void *data)
 {
-        struct arm_pmu *cpu_pmu = data;
-        struct platform_device *pmu_device = cpu_pmu->plat_device;
-        int irq = platform_get_irq(pmu_device, 0);
+        int irq = *(int *)data;
 
         enable_percpu_irq(irq, IRQ_TYPE_NONE);
-        cpumask_set_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
 }
 
 static void cpu_pmu_disable_percpu_irq(void *data)
 {
-        struct arm_pmu *cpu_pmu = data;
-        struct platform_device *pmu_device = cpu_pmu->plat_device;
-        int irq = platform_get_irq(pmu_device, 0);
+        int irq = *(int *)data;
 
-        cpumask_clear_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
         disable_percpu_irq(irq);
 }
 
@@ -103,7 +97,7 @@ static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
 
         irq = platform_get_irq(pmu_device, 0);
         if (irq >= 0 && irq_is_percpu(irq)) {
-                on_each_cpu(cpu_pmu_disable_percpu_irq, cpu_pmu, 1);
+                on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
                 free_percpu_irq(irq, &percpu_pmu);
         } else {
                 for (i = 0; i < irqs; ++i) {
@@ -138,7 +132,7 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
                                 irq);
                         return err;
                 }
-                on_each_cpu(cpu_pmu_enable_percpu_irq, cpu_pmu, 1);
+                on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
         } else {
                 for (i = 0; i < irqs; ++i) {
                         err = 0;
@@ -152,8 +146,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
                          * continue. Otherwise, continue without this interrupt.
                          */
                         if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
-                                pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-                                            irq, i);
+                                pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                                        irq, i);
                                 continue;
                         }
 
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 81ef686a91ca..a0a691d1cbee 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -306,7 +306,6 @@ void __show_regs(struct pt_regs *regs)
 
 void show_regs(struct pt_regs * regs)
 {
-        printk("\n");
         __show_regs(regs);
         dump_stack();
 }
@@ -334,6 +333,8 @@ void flush_thread(void)
         memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
         memset(&thread->fpstate, 0, sizeof(union fp_state));
 
+        flush_tls();
+
         thread_notify(THREAD_NOTIFY_FLUSH, thread);
 }
 
@@ -472,19 +473,57 @@ int in_gate_area_no_mm(unsigned long addr)
 
 const char *arch_vma_name(struct vm_area_struct *vma)
 {
-        return is_gate_vma(vma) ? "[vectors]" :
-                (vma->vm_mm && vma->vm_start == vma->vm_mm->context.sigpage) ?
-                 "[sigpage]" : NULL;
+        return is_gate_vma(vma) ? "[vectors]" : NULL;
+}
+
+/* If possible, provide a placement hint at a random offset from the
+ * stack for the signal page.
+ */
+static unsigned long sigpage_addr(const struct mm_struct *mm,
+                                  unsigned int npages)
+{
+        unsigned long offset;
+        unsigned long first;
+        unsigned long last;
+        unsigned long addr;
+        unsigned int slots;
+
+        first = PAGE_ALIGN(mm->start_stack);
+
+        last = TASK_SIZE - (npages << PAGE_SHIFT);
+
+        /* No room after stack? */
+        if (first > last)
+                return 0;
+
+        /* Just enough room? */
+        if (first == last)
+                return first;
+
+        slots = ((last - first) >> PAGE_SHIFT) + 1;
+
+        offset = get_random_int() % slots;
+
+        addr = first + (offset << PAGE_SHIFT);
+
+        return addr;
 }
 
 static struct page *signal_page;
 extern struct page *get_signal_page(void);
 
+static const struct vm_special_mapping sigpage_mapping = {
+        .name = "[sigpage]",
+        .pages = &signal_page,
+};
+
 int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 {
         struct mm_struct *mm = current->mm;
+        struct vm_area_struct *vma;
         unsigned long addr;
-        int ret;
+        unsigned long hint;
+        int ret = 0;
 
         if (!signal_page)
                 signal_page = get_signal_page();
@@ -492,18 +531,23 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
                 return -ENOMEM;
 
         down_write(&mm->mmap_sem);
-        addr = get_unmapped_area(NULL, 0, PAGE_SIZE, 0, 0);
+        hint = sigpage_addr(mm, 1);
+        addr = get_unmapped_area(NULL, hint, PAGE_SIZE, 0, 0);
         if (IS_ERR_VALUE(addr)) {
                 ret = addr;
                 goto up_fail;
         }
 
-        ret = install_special_mapping(mm, addr, PAGE_SIZE,
+        vma = _install_special_mapping(mm, addr, PAGE_SIZE,
                 VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
-                &signal_page);
+                &sigpage_mapping);
+
+        if (IS_ERR(vma)) {
+                ret = PTR_ERR(vma);
+                goto up_fail;
+        }
 
-        if (ret == 0)
-                mm->context.sigpage = addr;
+        mm->context.sigpage = addr;
 
  up_fail:
         up_write(&mm->mmap_sem);
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c
index fafedd86885d..98ea4b7eb406 100644
--- a/arch/arm/kernel/return_address.c
+++ b/arch/arm/kernel/return_address.c
@@ -59,15 +59,6 @@ void *return_address(unsigned int level)
 
 #else /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) */
 
-#if defined(CONFIG_ARM_UNWIND)
-#warning "TODO: return_address should use unwind tables"
-#endif
-
-void *return_address(unsigned int level)
-{
-        return NULL;
-}
-
 #endif /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) / else */
 
 EXPORT_SYMBOL_GPL(return_address);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 84db893dedc2..c03106378b49 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -133,6 +133,7 @@ struct stack {
         u32 irq[3];
         u32 abt[3];
         u32 und[3];
+        u32 fiq[3];
 } ____cacheline_aligned;
 
 #ifndef CONFIG_CPU_V7M
@@ -470,7 +471,10 @@ void notrace cpu_init(void)
         "msr    cpsr_c, %5\n\t"
         "add    r14, %0, %6\n\t"
         "mov    sp, r14\n\t"
-        "msr    cpsr_c, %7"
+        "msr    cpsr_c, %7\n\t"
+        "add    r14, %0, %8\n\t"
+        "mov    sp, r14\n\t"
+        "msr    cpsr_c, %9"
             :
             : "r" (stk),
               PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
@@ -479,6 +483,8 @@ void notrace cpu_init(void)
               "I" (offsetof(struct stack, abt[0])),
               PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
               "I" (offsetof(struct stack, und[0])),
+              PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
+              "I" (offsetof(struct stack, fiq[0])),
               PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
             : "r14");
 #endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 9388a3d479e1..13396d3d600e 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -95,6 +95,9 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
         int ret;
 
+        if (!smp_ops.smp_boot_secondary)
+                return -ENOSYS;
+
         /*
          * We need to tell the secondary core where to find
          * its stack and the page tables.
@@ -113,7 +116,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
         /*
          * Now bring the CPU into our world.
          */
-        ret = boot_secondary(cpu, idle);
+        ret = smp_ops.smp_boot_secondary(cpu, idle);
         if (ret == 0) {
                 /*
                  * CPU was successfully started, wait for it
@@ -142,13 +145,6 @@ void __init smp_init_cpus(void)
                 smp_ops.smp_init_cpus();
 }
 
-int boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        if (smp_ops.smp_boot_secondary)
-                return smp_ops.smp_boot_secondary(cpu, idle);
-        return -ENOSYS;
-}
-
 int platform_can_cpu_hotplug(void)
 {
 #ifdef CONFIG_HOTPLUG_CPU
@@ -503,7 +499,7 @@ void arch_send_call_function_single_ipi(int cpu)
 #ifdef CONFIG_IRQ_WORK
 void arch_irq_work_raise(void)
 {
-        if (is_smp())
+        if (arch_irq_work_has_interrupt())
                 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
 }
 #endif
@@ -650,7 +646,7 @@ void smp_send_stop(void)
                 udelay(1);
 
         if (num_online_cpus() > 1)
-                pr_warning("SMP: failed to stop secondary CPUs\n");
+                pr_warn("SMP: failed to stop secondary CPUs\n");
 }
 
 /*
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index 67ca8578c6d8..587fdfe1a72c 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -142,14 +142,6 @@ static int emulate_swpX(unsigned int address, unsigned int *data,
         while (1) {
                 unsigned long temp;
 
-                /*
-                 * Barrier required between accessing protected resource and
-                 * releasing a lock for it. Legacy code might not have done
-                 * this, and we cannot determine that this is not the case
-                 * being emulated, so insert always.
-                 */
-                smp_mb();
-
                 if (type == TYPE_SWPB)
                         __user_swpb_asm(*data, address, res, temp);
                 else
@@ -162,13 +154,6 @@ static int emulate_swpX(unsigned int address, unsigned int *data,
         }
 
         if (res == 0) {
-                /*
-                 * Barrier also required between acquiring a lock for a
-                 * protected resource and accessing the resource. Inserted for
-                 * same reason as above.
-                 */
-                smp_mb();
-
                 if (type == TYPE_SWPB)
                         swpbcounter++;
                 else
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index 7b8403b76666..80f0d69205e7 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -45,7 +45,7 @@ static int thumbee_notifier(struct notifier_block *self, unsigned long cmd, void
 
         switch (cmd) {
         case THREAD_NOTIFY_FLUSH:
-                thread->thumbee_state = 0;
+                teehbr_write(0);
                 break;
         case THREAD_NOTIFY_SWITCH:
                 current_thread_info()->thumbee_state = teehbr_read();
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index c8e4bb714944..0c8b10801d36 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/irq.h>
 
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
@@ -460,10 +461,29 @@ die_sig:
         arm_notify_die("Oops - undefined instruction", regs, &info, 0, 6);
 }
 
-asmlinkage void do_unexp_fiq (struct pt_regs *regs)
+/*
+ * Handle FIQ similarly to NMI on x86 systems.
+ *
+ * The runtime environment for NMIs is extremely restrictive
+ * (NMIs can pre-empt critical sections meaning almost all locking is
+ * forbidden) meaning this default FIQ handling must only be used in
+ * circumstances where non-maskability improves robustness, such as
+ * watchdog or debug logic.
+ *
+ * This handler is not appropriate for general purpose use in drivers
+ * platform code and can be overrideen using set_fiq_handler.
+ */
+asmlinkage void __exception_irq_entry handle_fiq_as_nmi(struct pt_regs *regs)
 {
-        printk("Hmm.  Unexpected FIQ received, but trying to continue\n");
-        printk("You may have a hardware problem...\n");
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
+        nmi_enter();
+
+        /* nop. FIQ handlers for special arch/arm features can be added here. */
+
+        nmi_exit();
+
+        set_irq_regs(old_regs);
 }
 
 /*
@@ -581,7 +601,6 @@ do_cache_op(unsigned long start, unsigned long end, int flags)
 #define NR(x) ((__ARM_NR_##x) - __ARM_NR_BASE)
 asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 {
-        struct thread_info *thread = current_thread_info();
         siginfo_t info;
 
         if ((no >> 16) != (__ARM_NR_BASE>> 16))
@@ -632,21 +651,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
                 return regs->ARM_r0;
 
         case NR(set_tls):
-                thread->tp_value[0] = regs->ARM_r0;
-                if (tls_emu)
-                        return 0;
-                if (has_tls_reg) {
-                        asm ("mcr p15, 0, %0, c13, c0, 3"
-                                : : "r" (regs->ARM_r0));
-                } else {
-                        /*
-                         * User space must never try to access this directly.
-                         * Expect your app to break eventually if you do so.
-                         * The user helper at 0xffff0fe0 must be used instead.
-                         * (see entry-armv.S for details)
-                         */
-                        *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
-                }
+                set_tls(regs->ARM_r0);
                 return 0;
 
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index a61a1dfbb0db..cbb85c5fabf9 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -157,7 +157,7 @@ static const struct unwind_idx *search_index(unsigned long addr,
         if (likely(start->addr_offset <= addr_prel31))
                 return start;
         else {
-                pr_warning("unwind: Unknown symbol address %08lx\n", addr);
+                pr_warn("unwind: Unknown symbol address %08lx\n", addr);
                 return NULL;
         }
 }
@@ -225,7 +225,7 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl)
         unsigned long ret;
 
         if (ctrl->entries <= 0) {
-                pr_warning("unwind: Corrupt unwind table\n");
+                pr_warn("unwind: Corrupt unwind table\n");
                 return 0;
         }
 
@@ -333,8 +333,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
                 insn = (insn << 8) | unwind_get_byte(ctrl);
                 mask = insn & 0x0fff;
                 if (mask == 0) {
-                        pr_warning("unwind: 'Refuse to unwind' instruction %04lx\n",
-                                   insn);
+                        pr_warn("unwind: 'Refuse to unwind' instruction %04lx\n",
+                                insn);
                         return -URC_FAILURE;
                 }
 
@@ -357,8 +357,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
                 unsigned long mask = unwind_get_byte(ctrl);
 
                 if (mask == 0 || mask & 0xf0) {
-                        pr_warning("unwind: Spare encoding %04lx\n",
-                               (insn << 8) | mask);
+                        pr_warn("unwind: Spare encoding %04lx\n",
+                                (insn << 8) | mask);
                         return -URC_FAILURE;
                 }
 
@@ -370,7 +370,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 
                 ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
         } else {
-                pr_warning("unwind: Unhandled instruction %02lx\n", insn);
+                pr_warn("unwind: Unhandled instruction %02lx\n", insn);
                 return -URC_FAILURE;
         }
 
@@ -403,7 +403,7 @@ int unwind_frame(struct stackframe *frame)
 
         idx = unwind_find_idx(frame->pc);
         if (!idx) {
-                pr_warning("unwind: Index not found %08lx\n", frame->pc);
+                pr_warn("unwind: Index not found %08lx\n", frame->pc);
                 return -URC_FAILURE;
         }
 
@@ -422,8 +422,8 @@ int unwind_frame(struct stackframe *frame)
                 /* only personality routine 0 supported in the index */
                 ctrl.insn = &idx->insn;
         else {
-                pr_warning("unwind: Unsupported personality routine %08lx in the index at %p\n",
-                           idx->insn, idx);
+                pr_warn("unwind: Unsupported personality routine %08lx in the index at %p\n",
+                        idx->insn, idx);
                 return -URC_FAILURE;
         }
 
@@ -435,8 +435,8 @@ int unwind_frame(struct stackframe *frame)
                 ctrl.byte = 1;
                 ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16);
         } else {
-                pr_warning("unwind: Unsupported personality routine %08lx at %p\n",
-                           *ctrl.insn, ctrl.insn);
+                pr_warn("unwind: Unsupported personality routine %08lx at %p\n",
+                        *ctrl.insn, ctrl.insn);
                 return -URC_FAILURE;
         }
 
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 6f57cb94367f..8e95aa47457a 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -219,8 +219,8 @@ SECTIONS
         __data_loc = ALIGN(4);          /* location in binary */
         . = PAGE_OFFSET + TEXT_OFFSET;
 #else
-        __init_end = .;
         . = ALIGN(THREAD_SIZE);
+        __init_end = .;
         __data_loc = .;
 #endif
 
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index a99e0cdf8ba2..779605122f32 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -82,12 +82,12 @@ struct kvm_vcpu *kvm_arm_get_running_vcpu(void)
 /**
  * kvm_arm_get_running_vcpus - get the per-CPU array of currently running vcpus.
  */
-struct kvm_vcpu __percpu **kvm_get_running_vcpus(void)
+struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void)
 {
         return &kvm_arm_running_vcpu;
 }
 
-int kvm_arch_hardware_enable(void *garbage)
+int kvm_arch_hardware_enable(void)
 {
         return 0;
 }
@@ -97,27 +97,16 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
 }
 
-void kvm_arch_hardware_disable(void *garbage)
-{
-}
-
 int kvm_arch_hardware_setup(void)
 {
         return 0;
 }
 
-void kvm_arch_hardware_unsetup(void)
-{
-}
-
 void kvm_arch_check_processor_compat(void *rtn)
 {
         *(int *)rtn = 0;
 }
 
-void kvm_arch_sync_events(struct kvm *kvm)
-{
-}
 
 /**
  * kvm_arch_init_vm - initializes a VM data structure
@@ -172,6 +161,8 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
                         kvm->vcpus[i] = NULL;
                 }
         }
+
+        kvm_vgic_destroy(kvm);
 }
 
 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
@@ -188,6 +179,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
         case KVM_CAP_ONE_REG:
         case KVM_CAP_ARM_PSCI:
         case KVM_CAP_ARM_PSCI_0_2:
+        case KVM_CAP_READONLY_MEM:
                 r = 1;
                 break;
         case KVM_CAP_COALESCED_MMIO:
@@ -253,6 +245,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 {
         kvm_mmu_free_memory_caches(vcpu);
         kvm_timer_vcpu_terminate(vcpu);
+        kvm_vgic_vcpu_destroy(vcpu);
         kmem_cache_free(kvm_vcpu_cache, vcpu);
 }
 
@@ -268,26 +261,15 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
 
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
 {
-        int ret;
-
         /* Force users to call KVM_ARM_VCPU_INIT */
         vcpu->arch.target = -1;
 
-        /* Set up VGIC */
-        ret = kvm_vgic_vcpu_init(vcpu);
-        if (ret)
-                return ret;
-
         /* Set up the timer */
         kvm_timer_vcpu_init(vcpu);
 
         return 0;
 }
 
-void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
-{
-}
-
 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
         vcpu->cpu = cpu;
@@ -428,9 +410,9 @@ static void update_vttbr(struct kvm *kvm)
 
         /* update vttbr to be used with the new vmid */
         pgd_phys = virt_to_phys(kvm->arch.pgd);
+        BUG_ON(pgd_phys & ~VTTBR_BADDR_MASK);
         vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK;
-        kvm->arch.vttbr = pgd_phys & VTTBR_BADDR_MASK;
-        kvm->arch.vttbr |= vmid;
+        kvm->arch.vttbr = pgd_phys | vmid;
 
         spin_unlock(&kvm_vmid_lock);
 }
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 37a0fe1bb9bb..7928dbdf2102 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -791,7 +791,7 @@ static bool is_valid_cache(u32 val)
         u32 level, ctype;
 
         if (val >= CSSELR_MAX)
-                return -ENOENT;
+                return false;
 
         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
         level = (val >> 1);
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
index 813e49258690..cc0b78769bd8 100644
--- a/arch/arm/kvm/guest.c
+++ b/arch/arm/kvm/guest.c
@@ -163,7 +163,7 @@ static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 
         ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
         if (ret != 0)
-                return ret;
+                return -EFAULT;
 
         return kvm_arm_timer_set_reg(vcpu, reg->id, val);
 }
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
index 4c979d466cc1..a96a8043277c 100644
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@@ -93,6 +93,8 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
         else
                 kvm_vcpu_block(vcpu);
 
+        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+
         return 1;
 }
 
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 991415d978b6..3988e72d16ff 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -99,6 +99,10 @@ __do_hyp_init:
         mrc     p15, 0, r0, c10, c2, 1
         mcr     p15, 4, r0, c10, c2, 1
 
+        @ Invalidate the stale TLBs from Bootloader
+        mcr     p15, 4, r0, c8, c7, 0   @ TLBIALLH
+        dsb     ish
+
         @ Set the HSCTLR to:
         @  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
         @  - Endianness: Kernel config
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 16e7994bf347..eea03069161b 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -746,22 +746,29 @@ static bool transparent_hugepage_adjust(pfn_t *pfnp, phys_addr_t *ipap)
         return false;
 }
 
+static bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
+{
+        if (kvm_vcpu_trap_is_iabt(vcpu))
+                return false;
+
+        return kvm_vcpu_dabt_iswrite(vcpu);
+}
+
 static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
-                          struct kvm_memory_slot *memslot,
+                          struct kvm_memory_slot *memslot, unsigned long hva,
                           unsigned long fault_status)
 {
         int ret;
         bool write_fault, writable, hugetlb = false, force_pte = false;
         unsigned long mmu_seq;
         gfn_t gfn = fault_ipa >> PAGE_SHIFT;
-        unsigned long hva = gfn_to_hva(vcpu->kvm, gfn);
         struct kvm *kvm = vcpu->kvm;
         struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
         struct vm_area_struct *vma;
         pfn_t pfn;
         pgprot_t mem_type = PAGE_S2;
 
-        write_fault = kvm_is_write_fault(kvm_vcpu_get_hsr(vcpu));
+        write_fault = kvm_is_write_fault(vcpu);
         if (fault_status == FSC_PERM && !write_fault) {
                 kvm_err("Unexpected L2 read permission error\n");
                 return -EFAULT;
@@ -863,7 +870,8 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
         unsigned long fault_status;
         phys_addr_t fault_ipa;
         struct kvm_memory_slot *memslot;
-        bool is_iabt;
+        unsigned long hva;
+        bool is_iabt, write_fault, writable;
         gfn_t gfn;
         int ret, idx;
 
@@ -874,17 +882,22 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
                               kvm_vcpu_get_hfar(vcpu), fault_ipa);
 
         /* Check the stage-2 fault is trans. fault or write fault */
-        fault_status = kvm_vcpu_trap_get_fault(vcpu);
+        fault_status = kvm_vcpu_trap_get_fault_type(vcpu);
         if (fault_status != FSC_FAULT && fault_status != FSC_PERM) {
-                kvm_err("Unsupported fault status: EC=%#x DFCS=%#lx\n",
-                        kvm_vcpu_trap_get_class(vcpu), fault_status);
+                kvm_err("Unsupported FSC: EC=%#x xFSC=%#lx ESR_EL2=%#lx\n",
+                        kvm_vcpu_trap_get_class(vcpu),
+                        (unsigned long)kvm_vcpu_trap_get_fault(vcpu),
+                        (unsigned long)kvm_vcpu_get_hsr(vcpu));
                 return -EFAULT;
         }
 
         idx = srcu_read_lock(&vcpu->kvm->srcu);
 
         gfn = fault_ipa >> PAGE_SHIFT;
-        if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) {
+        memslot = gfn_to_memslot(vcpu->kvm, gfn);
+        hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable);
+        write_fault = kvm_is_write_fault(vcpu);
+        if (kvm_is_error_hva(hva) || (write_fault && !writable)) {
                 if (is_iabt) {
                         /* Prefetch Abort on I/O address */
                         kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
@@ -892,13 +905,6 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
                         goto out_unlock;
                 }
 
-                if (fault_status != FSC_FAULT) {
-                        kvm_err("Unsupported fault status on io memory: %#lx\n",
-                                fault_status);
-                        ret = -EFAULT;
-                        goto out_unlock;
-                }
-
                 /*
                  * The IPA is reported as [MAX:12], so we need to
                  * complement it with the bottom 12 bits from the
@@ -910,9 +916,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
                 goto out_unlock;
         }
 
-        memslot = gfn_to_memslot(vcpu->kvm, gfn);
-
-        ret = user_mem_abort(vcpu, fault_ipa, memslot, fault_status);
+        ret = user_mem_abort(vcpu, fault_ipa, memslot, hva, fault_status);
         if (ret == 0)
                 ret = 1;
 out_unlock:
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 938600098b88..8ecfd15c3a02 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -80,7 +80,7 @@ ENTRY(__get_user_8)
 ENDPROC(__get_user_8)
 
 #ifdef __ARMEB__
-ENTRY(__get_user_lo8)
+ENTRY(__get_user_32t_8)
         check_uaccess r0, 8, r1, r2, __get_user_bad
 #ifdef CONFIG_CPU_USE_DOMAINS
         add     r0, r0, #4
@@ -90,7 +90,37 @@ ENTRY(__get_user_lo8)
 #endif
         mov     r0, #0
         ret     lr
-ENDPROC(__get_user_lo8)
+ENDPROC(__get_user_32t_8)
+
+ENTRY(__get_user_64t_1)
+        check_uaccess r0, 1, r1, r2, __get_user_bad8
+8: TUSER(ldrb)  r3, [r0]
+        mov     r0, #0
+        ret     lr
+ENDPROC(__get_user_64t_1)
+
+ENTRY(__get_user_64t_2)
+        check_uaccess r0, 2, r1, r2, __get_user_bad8
+#ifdef CONFIG_CPU_USE_DOMAINS
+rb      .req    ip
+9:      ldrbt   r3, [r0], #1
+10:     ldrbt   rb, [r0], #0
+#else
+rb      .req    r0
+9:      ldrb    r3, [r0]
+10:     ldrb    rb, [r0, #1]
+#endif
+        orr     r3, rb, r3, lsl #8
+        mov     r0, #0
+        ret     lr
+ENDPROC(__get_user_64t_2)
+
+ENTRY(__get_user_64t_4)
+        check_uaccess r0, 4, r1, r2, __get_user_bad8
+11: TUSER(ldr)  r3, [r0]
+        mov     r0, #0
+        ret     lr
+ENDPROC(__get_user_64t_4)
 #endif
 
 __get_user_bad8:
@@ -111,5 +141,9 @@ ENDPROC(__get_user_bad8)
         .long   6b, __get_user_bad8
 #ifdef __ARMEB__
         .long   7b, __get_user_bad
+        .long   8b, __get_user_bad8
+        .long   9b, __get_user_bad8
+        .long   10b, __get_user_bad8
+        .long   11b, __get_user_bad8
 #endif
 .popsection
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6cc6f7aebdae..0e6d548b70d9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,6 +12,9 @@ config HAVE_AT91_DBGU0
 config HAVE_AT91_DBGU1
         bool
 
+config HAVE_AT91_DBGU2
+        bool
+
 config AT91_USE_OLD_CLK
         bool
 
@@ -28,36 +31,33 @@ config OLD_CLK_AT91
         bool
         default AT91_PMC_UNIT && AT91_USE_OLD_CLK
 
-config AT91_SAM9_ALT_RESET
+config OLD_IRQ_AT91
         bool
-        default !ARCH_AT91X40
-
-config AT91_SAM9G45_RESET
-        bool
-        default !ARCH_AT91X40
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
 
-config AT91_SAM9_TIME
+config HAVE_AT91_SMD
         bool
 
-config HAVE_AT91_SMD
+config HAVE_AT91_H32MX
         bool
 
 config SOC_AT91SAM9
         bool
-        select AT91_SAM9_TIME
+        select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
+        select MEMORY if USE_OF
+        select ATMEL_SDRAMC if USE_OF
 
 config SOC_SAMA5
         bool
-        select AT91_SAM9_TIME
+        select ATMEL_AIC5_IRQ
         select CPU_V7
         select GENERIC_CLOCKEVENTS
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
         select USE_OF
+        select MEMORY
+        select ATMEL_SDRAMC
 
 menu "Atmel AT91 System-on-Chip"
 
@@ -70,8 +70,7 @@ config ARCH_AT91X40
         depends on !MMU
         select CPU_ARM7TDMI
         select ARCH_USES_GETTIMEOFFSET
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
+        select OLD_IRQ_AT91
 
         help
           Select this if you are using one of Atmel's AT91X40 SoC.
@@ -103,16 +102,30 @@ config SOC_SAMA5D3
         help
           Select this if you are using one of Atmel's SAMA5D3 family SoC.
           This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
+
+config SOC_SAMA5D4
+        bool "SAMA5D4 family"
+        select SOC_SAMA5
+        select HAVE_AT91_DBGU2
+        select CLKSRC_MMIO
+        select CACHE_L2X0
+        select CACHE_PL310
+        select HAVE_FB_ATMEL
+        select HAVE_AT91_UTMI
+        select HAVE_AT91_SMD
+        select HAVE_AT91_USB_CLK
+        select HAVE_AT91_H32MX
+        help
+          Select this if you are using one of Atmel's SAMA5D4 family SoC.
 endif
 
 if SOC_SAM_V4_V5
 config SOC_AT91RM9200
         bool "AT91RM9200"
+        select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
         select CPU_ARM920T
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_DBGU0
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
         select HAVE_AT91_USB_CLK
 
 config SOC_AT91SAM9260
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 44ace320d2e1..d8e88219edb4 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,31 +14,37 @@ config ARCH_AT91RM9200
         bool "AT91RM9200"
         select SOC_AT91RM9200
         select AT91_USE_OLD_CLK
+        select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9260
         bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
         select SOC_AT91SAM9260
         select AT91_USE_OLD_CLK
+        select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261 or AT91SAM9G10"
         select SOC_AT91SAM9261
         select AT91_USE_OLD_CLK
+        select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9263
         bool "AT91SAM9263"
         select SOC_AT91SAM9263
         select AT91_USE_OLD_CLK
+        select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
         select SOC_AT91SAM9RL
         select AT91_USE_OLD_CLK
+        select OLD_IRQ_AT91
 
 config ARCH_AT91SAM9G45
         bool "AT91SAM9G45"
         select SOC_AT91SAM9G45
         select AT91_USE_OLD_CLK
+        select OLD_IRQ_AT91
 
 endchoice
 
@@ -132,12 +138,6 @@ config MACH_ECO920
         bool "eco920"
         help
           Select this if you are using the eco920 board
-
-config MACH_RSI_EWS
-        bool "RSI Embedded Webserver"
-        depends on ARCH_AT91RM9200
-        help
-          Select this if you are using RSIs EWS board.
 endif
 
 # ----------------------------------------------------------
@@ -212,12 +212,6 @@ config MACH_CPU9G20
           Select this if you are using a Eukrea Electromatique's
           CPU9G20 Board <http://www.eukrea.com/>
 
-config MACH_ACMENETUSFOXG20
-        bool "Acme Systems srl FOX Board G20"
-        help
-          Select this if you are using Acme Systems
-          FOX Board G20 <http://www.acmesystems.it>
-
 config MACH_PORTUXG20
         bool "taskit PortuxG20"
         help
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 78e9cec282f4..ac99d87ffefe 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,15 +2,13 @@
 # Makefile for the linux kernel.
 #
 
-obj-y           := irq.o gpio.o setup.o sysirq_mask.o
+obj-y           := gpio.o setup.o sysirq_mask.o
 obj-m           :=
 obj-n           :=
 obj-            :=
 
+obj-$(CONFIG_OLD_IRQ_AT91)      += irq.o
 obj-$(CONFIG_OLD_CLK_AT91)      += clock.o
-obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
-obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
-obj-$(CONFIG_AT91_SAM9_TIME)    += at91sam926x_time.o
 obj-$(CONFIG_SOC_AT91SAM9)      += sam9_smc.o
 
 # CPU-specific support
@@ -23,6 +21,7 @@ obj-$(CONFIG_SOC_AT91SAM9N12)	+= at91sam9n12.o
 obj-$(CONFIG_SOC_AT91SAM9X5)    += at91sam9x5.o
 obj-$(CONFIG_SOC_AT91SAM9RL)    += at91sam9rl.o
 obj-$(CONFIG_SOC_SAMA5D3)       += sama5d3.o
+obj-$(CONFIG_SOC_SAMA5D4)       += sama5d4.o
 
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
@@ -46,7 +45,6 @@ obj-$(CONFIG_MACH_ECBAT91)	+= board-ecbat91.o
 obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
 obj-$(CONFIG_MACH_CPUAT91)      += board-cpuat91.o
 obj-$(CONFIG_MACH_ECO920)       += board-eco920.o
-obj-$(CONFIG_MACH_RSI_EWS)      += board-rsi-ews.o
 
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
@@ -69,7 +67,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
 # AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
-obj-$(CONFIG_MACH_ACMENETUSFOXG20) += board-foxg20.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
diff --git a/arch/arm/mach-at91/at91_rstc.h b/arch/arm/mach-at91/at91_rstc.h
deleted file mode 100644
index a600e6992920..000000000000
--- a/arch/arm/mach-at91/at91_rstc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_rstc.h
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Reset Controller (RSTC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_RSTC_H
-#define AT91_RSTC_H
-
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_rstc_base;
-
-#define at91_rstc_read(field) \
-        __raw_readl(at91_rstc_base + field)
-
-#define at91_rstc_write(field, value) \
-        __raw_writel(value, at91_rstc_base + field)
-#else
-.extern at91_rstc_base
-#endif
-
-#define AT91_RSTC_CR            0x00                    /* Reset Controller Control Register */
-#define         AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
-#define         AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
-#define         AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
-#define         AT91_RSTC_KEY           (0xa5 << 24)            /* KEY Password */
-
-#define AT91_RSTC_SR            0x04                    /* Reset Controller Status Register */
-#define         AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
-#define         AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
-#define                 AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
-#define                 AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
-#define                 AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
-#define                 AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
-#define                 AT91_RSTC_RSTTYP_USER   (4 << 8)
-#define         AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
-#define         AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
-
-#define AT91_RSTC_MR            0x08                    /* Reset Controller Mode Register */
-#define         AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
-#define         AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
-#define         AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
-
-#endif
diff --git a/arch/arm/mach-at91/at91_shdwc.h b/arch/arm/mach-at91/at91_shdwc.h
deleted file mode 100644
index 9e29f31ec9a6..000000000000
--- a/arch/arm/mach-at91/at91_shdwc.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_shdwc.h
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Shutdown Controller (SHDWC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SHDWC_H
-#define AT91_SHDWC_H
-
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_shdwc_base;
-
-#define at91_shdwc_read(field) \
-        __raw_readl(at91_shdwc_base + field)
-
-#define at91_shdwc_write(field, value) \
-        __raw_writel(value, at91_shdwc_base + field)
-#endif
-
-#define AT91_SHDW_CR            0x00                    /* Shut Down Control Register */
-#define         AT91_SHDW_SHDW          (1    << 0)             /* Shut Down command */
-#define         AT91_SHDW_KEY           (0xa5 << 24)            /* KEY Password */
-
-#define AT91_SHDW_MR            0x04                    /* Shut Down Mode Register */
-#define         AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
-#define                 AT91_SHDW_WKMODE0_NONE          0
-#define                 AT91_SHDW_WKMODE0_HIGH          1
-#define                 AT91_SHDW_WKMODE0_LOW           2
-#define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
-#define         AT91_SHDW_CPTWK0_MAX    0xf                     /* Maximum Counter On Wake Up 0 */
-#define         AT91_SHDW_CPTWK0        (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
-#define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
-#define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
-#define         AT91_SHDW_RTCWKEN       (1   << 17)             /* Real Time Clock Wake-up Enable */
-
-#define AT91_SHDW_SR            0x08                    /* Shut Down Status Register */
-#define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
-#define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
-#define         AT91_SHDW_RTCWK         (1 << 17)               /* Real-time Clock Wake-up [SAM9RL] */
-
-#endif
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 3477ba94c4c5..aab1f969a7c3 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
@@ -24,7 +25,6 @@
 #include <mach/hardware.h>
 
 #include "at91_aic.h"
-#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "sam9_smc.h"
@@ -342,8 +342,6 @@ static void __init at91sam9260_map_io(void)
 
 static void __init at91sam9260_ioremap_registers(void)
 {
-        at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
-        at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
         at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
@@ -354,7 +352,6 @@ static void __init at91sam9260_ioremap_registers(void)
 static void __init at91sam9260_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
-        arm_pm_restart = at91sam9_alt_restart;
 
         at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
 
@@ -362,6 +359,45 @@ static void __init at91sam9260_initialize(void)
         at91_gpio_init(at91sam9260_gpio, 3);
 }
 
+static struct resource rstc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_RSTC,
+                .end    = AT91SAM9260_BASE_RSTC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_BASE_SDRAMC,
+                .end    = AT91SAM9260_BASE_SDRAMC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device rstc_device = {
+        .name           = "at91-sam9260-reset",
+        .resource       = rstc_resources,
+        .num_resources  = ARRAY_SIZE(rstc_resources),
+};
+
+static struct resource shdwc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_SHDWC,
+                .end    = AT91SAM9260_BASE_SHDWC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device shdwc_device = {
+        .name           = "at91-poweroff",
+        .resource       = shdwc_resources,
+        .num_resources  = ARRAY_SIZE(shdwc_resources),
+};
+
+static void __init at91sam9260_register_devices(void)
+{
+        platform_device_register(&rstc_device);
+        platform_device_register(&shdwc_device);
+}
+
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
@@ -404,6 +440,11 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
+static void __init at91sam9260_init_time(void)
+{
+        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
+}
+
 AT91_SOC_START(at91sam9260)
         .map_io = at91sam9260_map_io,
         .default_irq_priority = at91sam9260_default_irq_priority,
@@ -411,5 +452,7 @@ AT91_SOC_START(at91sam9260)
                     | (1 << AT91SAM9260_ID_IRQ2),
         .ioremap_registers = at91sam9260_ioremap_registers,
         .register_clocks = at91sam9260_register_clocks,
+        .register_devices = at91sam9260_register_devices,
         .init = at91sam9260_initialize,
+        .init_time = at91sam9260_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index fb164a5d04a9..a8bd35963332 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
@@ -23,7 +24,6 @@
 #include <mach/hardware.h>
 
 #include "at91_aic.h"
-#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "sam9_smc.h"
@@ -301,8 +301,6 @@ static void __init at91sam9261_map_io(void)
 
 static void __init at91sam9261_ioremap_registers(void)
 {
-        at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
-        at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
         at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
@@ -313,7 +311,6 @@ static void __init at91sam9261_ioremap_registers(void)
 static void __init at91sam9261_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
-        arm_pm_restart = at91sam9_alt_restart;
 
         at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
 
@@ -321,6 +318,45 @@ static void __init at91sam9261_initialize(void)
         at91_gpio_init(at91sam9261_gpio, 3);
 }
 
+static struct resource rstc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_RSTC,
+                .end    = AT91SAM9261_BASE_RSTC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_BASE_SDRAMC,
+                .end    = AT91SAM9261_BASE_SDRAMC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device rstc_device = {
+        .name           = "at91-sam9260-reset",
+        .resource       = rstc_resources,
+        .num_resources  = ARRAY_SIZE(rstc_resources),
+};
+
+static struct resource shdwc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_SHDWC,
+                .end    = AT91SAM9261_BASE_SHDWC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device shdwc_device = {
+        .name           = "at91-poweroff",
+        .resource       = shdwc_resources,
+        .num_resources  = ARRAY_SIZE(shdwc_resources),
+};
+
+static void __init at91sam9261_register_devices(void)
+{
+        platform_device_register(&rstc_device);
+        platform_device_register(&shdwc_device);
+}
+
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
@@ -363,6 +399,11 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
+static void __init at91sam9261_init_time(void)
+{
+        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
+}
+
 AT91_SOC_START(at91sam9261)
         .map_io = at91sam9261_map_io,
         .default_irq_priority = at91sam9261_default_irq_priority,
@@ -370,5 +411,7 @@ AT91_SOC_START(at91sam9261)
                     | (1 << AT91SAM9261_ID_IRQ2),
         .ioremap_registers = at91sam9261_ioremap_registers,
         .register_clocks = at91sam9261_register_clocks,
+        .register_devices = at91sam9261_register_devices,
         .init = at91sam9261_initialize,
+        .init_time = at91sam9261_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 810fa5f15a51..fbff228cc63e 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
@@ -22,7 +23,6 @@
 #include <mach/hardware.h>
 
 #include "at91_aic.h"
-#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "sam9_smc.h"
@@ -321,8 +321,6 @@ static void __init at91sam9263_map_io(void)
 
 static void __init at91sam9263_ioremap_registers(void)
 {
-        at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
-        at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
         at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
         at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
         at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
@@ -335,7 +333,6 @@ static void __init at91sam9263_ioremap_registers(void)
 static void __init at91sam9263_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
-        arm_pm_restart = at91sam9_alt_restart;
 
         at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
         at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
@@ -344,6 +341,45 @@ static void __init at91sam9263_initialize(void)
         at91_gpio_init(at91sam9263_gpio, 5);
 }
 
+static struct resource rstc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9263_BASE_RSTC,
+                .end    = AT91SAM9263_BASE_RSTC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9263_BASE_SDRAMC0,
+                .end    = AT91SAM9263_BASE_SDRAMC0 + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device rstc_device = {
+        .name           = "at91-sam9260-reset",
+        .resource       = rstc_resources,
+        .num_resources  = ARRAY_SIZE(rstc_resources),
+};
+
+static struct resource shdwc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9263_BASE_SHDWC,
+                .end    = AT91SAM9263_BASE_SHDWC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device shdwc_device = {
+        .name           = "at91-poweroff",
+        .resource       = shdwc_resources,
+        .num_resources  = ARRAY_SIZE(shdwc_resources),
+};
+
+static void __init at91sam9263_register_devices(void)
+{
+        platform_device_register(&rstc_device);
+        platform_device_register(&shdwc_device);
+}
+
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
@@ -386,11 +422,18 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ1) */
 };
 
+static void __init at91sam9263_init_time(void)
+{
+        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
+}
+
 AT91_SOC_START(at91sam9263)
         .map_io = at91sam9263_map_io,
         .default_irq_priority = at91sam9263_default_irq_priority,
         .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
         .ioremap_registers = at91sam9263_ioremap_registers,
         .register_clocks = at91sam9263_register_clocks,
+        .register_devices = at91sam9263_register_devices,
         .init = at91sam9263_initialize,
+        .init_time = at91sam9263_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
deleted file mode 100644
index 0a9e2fc8f796..000000000000
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
- *
- * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
- * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
- * Converted to ClockSource/ClockEvents by David Brownell.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
-#define AT91_PIT_MR             0x00                    /* Mode Register */
-#define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
-#define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
-#define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
-
-#define AT91_PIT_SR             0x04                    /* Status Register */
-#define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
-
-#define AT91_PIT_PIVR           0x08                    /* Periodic Interval Value Register */
-#define AT91_PIT_PIIR           0x0c                    /* Periodic Interval Image Register */
-#define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
-#define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
-
-#define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
-#define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
-
-static u32 pit_cycle;           /* write-once */
-static u32 pit_cnt;             /* access only w/system irq blocked */
-static void __iomem *pit_base_addr __read_mostly;
-static struct clk *mck;
-
-static inline unsigned int pit_read(unsigned int reg_offset)
-{
-        return __raw_readl(pit_base_addr + reg_offset);
-}
-
-static inline void pit_write(unsigned int reg_offset, unsigned long value)
-{
-        __raw_writel(value, pit_base_addr + reg_offset);
-}
-
-/*
- * Clocksource:  just a monotonic counter of MCK/16 cycles.
- * We don't care whether or not PIT irqs are enabled.
- */
-static cycle_t read_pit_clk(struct clocksource *cs)
-{
-        unsigned long flags;
-        u32 elapsed;
-        u32 t;
-
-        raw_local_irq_save(flags);
-        elapsed = pit_cnt;
-        t = pit_read(AT91_PIT_PIIR);
-        raw_local_irq_restore(flags);
-
-        elapsed += PIT_PICNT(t) * pit_cycle;
-        elapsed += PIT_CPIV(t);
-        return elapsed;
-}
-
-static struct clocksource pit_clk = {
-        .name           = "pit",
-        .rating         = 175,
-        .read           = read_pit_clk,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-
-/*
- * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
- */
-static void
-pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
-{
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                /* update clocksource counter */
-                pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
-                pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
-                                | AT91_PIT_PITIEN);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                BUG();
-                /* FALLTHROUGH */
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-                /* disable irq, leaving the clocksource active */
-                pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
-                break;
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
-{
-        /* Disable timer */
-        pit_write(AT91_PIT_MR, 0);
-}
-
-static void at91sam926x_pit_reset(void)
-{
-        /* Disable timer and irqs */
-        pit_write(AT91_PIT_MR, 0);
-
-        /* Clear any pending interrupts, wait for PIT to stop counting */
-        while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
-                cpu_relax();
-
-        /* Start PIT but don't enable IRQ */
-        pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
-}
-
-static void at91sam926x_pit_resume(struct clock_event_device *cedev)
-{
-        at91sam926x_pit_reset();
-}
-
-static struct clock_event_device pit_clkevt = {
-        .name           = "pit",
-        .features       = CLOCK_EVT_FEAT_PERIODIC,
-        .shift          = 32,
-        .rating         = 100,
-        .set_mode       = pit_clkevt_mode,
-        .suspend        = at91sam926x_pit_suspend,
-        .resume         = at91sam926x_pit_resume,
-};
-
-
-/*
- * IRQ handler for the timer.
- */
-static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
-{
-        /*
-         * irqs should be disabled here, but as the irq is shared they are only
-         * guaranteed to be off if the timer irq is registered first.
-         */
-        WARN_ON_ONCE(!irqs_disabled());
-
-        /* The PIT interrupt may be disabled, and is shared */
-        if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
-                        && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
-                unsigned nr_ticks;
-
-                /* Get number of ticks performed before irq, and ack it */
-                nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
-                do {
-                        pit_cnt += pit_cycle;
-                        pit_clkevt.event_handler(&pit_clkevt);
-                        nr_ticks--;
-                } while (nr_ticks);
-
-                return IRQ_HANDLED;
-        }
-
-        return IRQ_NONE;
-}
-
-static struct irqaction at91sam926x_pit_irq = {
-        .name           = "at91_tick",
-        .flags          = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91sam926x_pit_interrupt,
-        .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
-};
-
-#ifdef CONFIG_OF
-static struct of_device_id pit_timer_ids[] = {
-        { .compatible = "atmel,at91sam9260-pit" },
-        { /* sentinel */ }
-};
-
-static int __init of_at91sam926x_pit_init(void)
-{
-        struct device_node      *np;
-        int                     ret;
-
-        np = of_find_matching_node(NULL, pit_timer_ids);
-        if (!np)
-                goto err;
-
-        pit_base_addr = of_iomap(np, 0);
-        if (!pit_base_addr)
-                goto node_err;
-
-        mck = of_clk_get(np, 0);
-
-        /* Get the interrupts property */
-        ret = irq_of_parse_and_map(np, 0);
-        if (!ret) {
-                pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
-                if (!IS_ERR(mck))
-                        clk_put(mck);
-                goto ioremap_err;
-        }
-        at91sam926x_pit_irq.irq = ret;
-
-        of_node_put(np);
-
-        return 0;
-
-ioremap_err:
-        iounmap(pit_base_addr);
-node_err:
-        of_node_put(np);
-err:
-        return -EINVAL;
-}
-#else
-static int __init of_at91sam926x_pit_init(void)
-{
-        return -EINVAL;
-}
-#endif
-
-/*
- * Set up both clocksource and clockevent support.
- */
-void __init at91sam926x_pit_init(void)
-{
-        unsigned long   pit_rate;
-        unsigned        bits;
-        int             ret;
-
-        mck = ERR_PTR(-ENOENT);
-
-        /* For device tree enabled device: initialize here */
-        of_at91sam926x_pit_init();
-
-        /*
-         * Use our actual MCK to figure out how many MCK/16 ticks per
-         * 1/HZ period (instead of a compile-time constant LATCH).
-         */
-        if (IS_ERR(mck))
-                mck = clk_get(NULL, "mck");
-
-        if (IS_ERR(mck))
-                panic("AT91: PIT: Unable to get mck clk\n");
-        pit_rate = clk_get_rate(mck) / 16;
-        pit_cycle = (pit_rate + HZ/2) / HZ;
-        WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
-
-        /* Initialize and enable the timer */
-        at91sam926x_pit_reset();
-
-        /*
-         * Register clocksource.  The high order bits of PIV are unused,
-         * so this isn't a 32-bit counter unless we get clockevent irqs.
-         */
-        bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
-        pit_clk.mask = CLOCKSOURCE_MASK(bits);
-        clocksource_register_hz(&pit_clk, pit_rate);
-
-        /* Set up irq handler */
-        ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
-        if (ret)
-                pr_crit("AT91: PIT: Unable to setup IRQ\n");
-
-        /* Set up and register clockevents */
-        pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
-        pit_clkevt.cpumask = cpumask_of(0);
-        clockevents_register_device(&pit_clkevt);
-}
-
-void __init at91sam926x_ioremap_pit(u32 addr)
-{
-#if defined(CONFIG_OF)
-        struct device_node *np =
-                of_find_matching_node(NULL, pit_timer_ids);
-
-        if (np) {
-                of_node_put(np);
-                return;
-        }
-#endif
-        pit_base_addr = ioremap(addr, 16);
-
-        if (!pit_base_addr)
-                panic("Impossible to ioremap PIT\n");
-}
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
deleted file mode 100644
index f039538d3bdb..000000000000
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * reset AT91SAM9G20 as per errata
- *
- * (C) BitBox Ltd 2010
- *
- * unless the SDRAM is cleanly shutdown before we hit the
- * reset register it can be left driving the data bus and
- * killing the chance of a subsequent boot from NAND
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include "at91_rstc.h"
-
-                        .arm
-
-                        .globl  at91sam9_alt_restart
-
-at91sam9_alt_restart:   ldr     r0, =at91_ramc_base             @ preload constants
-                        ldr     r0, [r0]
-                        ldr     r4, =at91_rstc_base
-                        ldr     r1, [r4]
-
-                        mov     r2, #1
-                        mov     r3, #AT91_SDRAMC_LPCB_POWER_DOWN
-                        ldr     r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
-
-                        .balign 32                              @ align to cache line
-
-                        str     r2, [r0, #AT91_SDRAMC_TR]       @ disable SDRAM access
-                        str     r3, [r0, #AT91_SDRAMC_LPR]      @ power down SDRAM
-                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
-
-                        b       .
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9d45496e4932..405427ec05f8 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
 #include <linux/clk/at91_pmc.h>
+#include <linux/platform_device.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -371,8 +372,6 @@ static void __init at91sam9g45_map_io(void)
 
 static void __init at91sam9g45_ioremap_registers(void)
 {
-        at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
-        at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
         at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
         at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
         at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
@@ -384,7 +383,6 @@ static void __init at91sam9g45_ioremap_registers(void)
 static void __init at91sam9g45_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
-        arm_pm_restart = at91sam9g45_restart;
 
         at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
         at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
@@ -393,6 +391,50 @@ static void __init at91sam9g45_initialize(void)
         at91_gpio_init(at91sam9g45_gpio, 5);
 }
 
+static struct resource rstc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_RSTC,
+                .end    = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_BASE_DDRSDRC1,
+                .end    = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = AT91SAM9G45_BASE_DDRSDRC0,
+                .end    = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device rstc_device = {
+        .name           = "at91-sam9g45-reset",
+        .resource       = rstc_resources,
+        .num_resources  = ARRAY_SIZE(rstc_resources),
+};
+
+static struct resource shdwc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SHDWC,
+                .end    = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device shdwc_device = {
+        .name           = "at91-poweroff",
+        .resource       = shdwc_resources,
+        .num_resources  = ARRAY_SIZE(shdwc_resources),
+};
+
+static void __init at91sam9g45_register_devices(void)
+{
+        platform_device_register(&rstc_device);
+        platform_device_register(&shdwc_device);
+}
+
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
@@ -435,11 +477,18 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ0) */
 };
 
+static void __init at91sam9g45_init_time(void)
+{
+        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
+}
+
 AT91_SOC_START(at91sam9g45)
         .map_io = at91sam9g45_map_io,
         .default_irq_priority = at91sam9g45_default_irq_priority,
         .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
         .ioremap_registers = at91sam9g45_ioremap_registers,
         .register_clocks = at91sam9g45_register_clocks,
+        .register_devices = at91sam9g45_register_devices,
         .init = at91sam9g45_initialize,
+        .init_time = at91sam9g45_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
deleted file mode 100644
index c40c1e2ef80f..000000000000
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * reset AT91SAM9G45 as per errata
- *
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
- *
- * unless the SDRAM is cleanly shutdown before we hit the
- * reset register it can be left driving the data bus and
- * killing the chance of a subsequent boot from NAND
- *
- * GPLv2 Only
- */
-
-#include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include "at91_rstc.h"
-                        .arm
-
-/*
- * at91_ramc_base is an array void*
- * init at NULL if only one DDR controler is present in or DT
- */
-                        .globl  at91sam9g45_restart
-
-at91sam9g45_restart:
-                        ldr     r5, =at91_ramc_base             @ preload constants
-                        ldr     r0, [r5]
-                        ldr     r5, [r5, #4]                    @ ddr1
-                        cmp     r5, #0
-                        ldr     r4, =at91_rstc_base
-                        ldr     r1, [r4]
-
-                        mov     r2, #1
-                        mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
-                        ldr     r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
-
-                        .balign 32                              @ align to cache line
-
-                        strne   r2, [r5, #AT91_DDRSDRC_RTR]     @ disable DDR1 access
-                        strne   r3, [r5, #AT91_DDRSDRC_LPR]     @ power down DDR1
-                        str     r2, [r0, #AT91_DDRSDRC_RTR]     @ disable DDR0 access
-                        str     r3, [r0, #AT91_DDRSDRC_LPR]     @ power down DDR0
-                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
-
-                        b       .
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 878d5015daab..f553e4ea034b 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
@@ -23,7 +24,6 @@
 #include <mach/hardware.h>
 
 #include "at91_aic.h"
-#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "sam9_smc.h"
@@ -311,8 +311,6 @@ static void __init at91sam9rl_map_io(void)
 
 static void __init at91sam9rl_ioremap_registers(void)
 {
-        at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
-        at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
         at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
@@ -323,7 +321,6 @@ static void __init at91sam9rl_ioremap_registers(void)
 static void __init at91sam9rl_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
-        arm_pm_restart = at91sam9_alt_restart;
 
         at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
         at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
@@ -332,6 +329,45 @@ static void __init at91sam9rl_initialize(void)
         at91_gpio_init(at91sam9rl_gpio, 4);
 }
 
+static struct resource rstc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_BASE_RSTC,
+                .end    = AT91SAM9RL_BASE_RSTC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9RL_BASE_SDRAMC,
+                .end    = AT91SAM9RL_BASE_SDRAMC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device rstc_device = {
+        .name           = "at91-sam9260-reset",
+        .resource       = rstc_resources,
+        .num_resources  = ARRAY_SIZE(rstc_resources),
+};
+
+static struct resource shdwc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_BASE_SHDWC,
+                .end    = AT91SAM9RL_BASE_SHDWC + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device shdwc_device = {
+        .name           = "at91-poweroff",
+        .resource       = shdwc_resources,
+        .num_resources  = ARRAY_SIZE(shdwc_resources),
+};
+
+static void __init at91sam9rl_register_devices(void)
+{
+        platform_device_register(&rstc_device);
+        platform_device_register(&shdwc_device);
+}
+
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
@@ -374,6 +410,11 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
+static void __init at91sam9rl_init_time(void)
+{
+        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
+}
+
 AT91_SOC_START(at91sam9rl)
         .map_io = at91sam9rl_map_io,
         .default_irq_priority = at91sam9rl_default_irq_priority,
@@ -382,5 +423,7 @@ AT91_SOC_START(at91sam9rl)
 #if defined(CONFIG_OLD_CLK_AT91)
         .register_clocks = at91sam9rl_register_clocks,
 #endif
+        .register_devices = at91sam9rl_register_devices,
         .init = at91sam9rl_initialize,
+        .init_time = at91sam9rl_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 597c649170aa..e76e35ce81e7 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -167,6 +167,8 @@ static struct at91_cf_data afeb9260_cf_data = {
 
 static void __init afeb9260_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -211,7 +213,7 @@ static void __init afeb9260_board_init(void)
 
 MACHINE_START(AFEB9260, "Custom afeb9260 board")
         /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = afeb9260_init_early,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index a30502c8d379..ae827dd2d0d2 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -170,6 +170,8 @@ static void __init cam60_add_device_nand(void)
 
 static void __init cam60_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -188,7 +190,7 @@ static void __init cam60_board_init(void)
 
 MACHINE_START(CAM60, "KwikByte CAM60")
         /* Maintainer: KwikByte */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = cam60_init_early,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 2037f78c84e7..731c8318f4f5 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -322,6 +322,8 @@ static struct mci_platform_data __initdata cpu9krea_mci0_data = {
 
 static void __init cpu9krea_board_init(void)
 {
+        at91_register_devices();
+
         /* NOR */
         cpu9krea_add_device_nor();
         /* Serial */
@@ -375,7 +377,7 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
 MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
 #endif
         /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = cpu9krea_init_early,
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3a185faee795..226563f850b8 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -14,6 +14,7 @@
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/clk-provider.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -24,15 +25,12 @@
 #include "at91_aic.h"
 #include "generic.h"
 
-
-static const struct of_device_id irq_of_match[] __initconst = {
-        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-        { /*sentinel*/ }
-};
-
-static void __init at91rm9200_dt_init_irq(void)
+static void __init at91rm9200_dt_timer_init(void)
 {
-        of_irq_init(irq_of_match);
+#if defined(CONFIG_COMMON_CLK)
+        of_clk_init(NULL);
+#endif
+        at91rm9200_timer_init();
 }
 
 static const char *at91rm9200_dt_board_compat[] __initdata = {
@@ -41,10 +39,8 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
 };
 
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
-        .init_time      = at91rm9200_timer_init,
+        .init_time      = at91rm9200_dt_timer_init,
         .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
         .init_early     = at91rm9200_dt_initialize,
-        .init_irq       = at91rm9200_dt_init_irq,
         .dt_compat      = at91rm9200_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 575b0be66ca8..d3048ccdc41f 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -25,26 +25,6 @@
 #include "board.h"
 #include "generic.h"
 
-
-static void __init sam9_dt_timer_init(void)
-{
-#if defined(CONFIG_COMMON_CLK)
-        of_clk_init(NULL);
-#endif
-        at91sam926x_pit_init();
-}
-
-static const struct of_device_id irq_of_match[] __initconst = {
-
-        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-        { /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-        of_irq_init(irq_of_match);
-}
-
 static const char *at91_dt_board_compat[] __initdata = {
         "atmel,at91sam9",
         NULL
@@ -52,10 +32,7 @@ static const char *at91_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
         /* Maintainer: Atmel */
-        .init_time      = sam9_dt_timer_init,
         .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
         .init_early     = at91_dt_initialize,
-        .init_irq       = at91_dt_init_irq,
         .dt_compat      = at91_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 075ec0576ada..129e2917506b 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -27,64 +27,34 @@
 #include "at91_aic.h"
 #include "generic.h"
 
-static void __init sama5_dt_timer_init(void)
-{
-#if defined(CONFIG_COMMON_CLK)
-        of_clk_init(NULL);
-#endif
-        at91sam926x_pit_init();
-}
-
-static const struct of_device_id irq_of_match[] __initconst = {
-
-        { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
-        { /*sentinel*/ }
-};
-
-static void __init at91_dt_init_irq(void)
-{
-        of_irq_init(irq_of_match);
-}
-
-static int ksz9021rn_phy_fixup(struct phy_device *phy)
-{
-        int value;
-
-        /* Set delay values */
-        value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
-        phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-        value = 0xF2F4;
-        phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-        value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
-        phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-        value = 0x2222;
-        phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-
-        return 0;
-}
-
 static void __init sama5_dt_device_init(void)
 {
-        if (of_machine_is_compatible("atmel,sama5d3xcm") &&
-            IS_ENABLED(CONFIG_PHYLIB))
-                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-                        ksz9021rn_phy_fixup);
-
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *sama5_dt_board_compat[] __initdata = {
+static const char *sama5_dt_board_compat[] __initconst = {
         "atmel,sama5",
         NULL
 };
 
 DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
         /* Maintainer: Atmel */
-        .init_time      = sama5_dt_timer_init,
         .map_io         = at91_map_io,
-        .handle_irq     = at91_aic5_handle_irq,
         .init_early     = at91_dt_initialize,
-        .init_irq       = at91_dt_init_irq,
         .init_machine   = sama5_dt_device_init,
         .dt_compat      = sama5_dt_board_compat,
 MACHINE_END
+
+static const char *sama5_alt_dt_board_compat[] __initconst = {
+        "atmel,sama5d4",
+        NULL
+};
+
+DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5 (Device Tree)")
+        /* Maintainer: Atmel */
+        .map_io         = at91_alt_map_io,
+        .init_early     = at91_dt_initialize,
+        .init_machine   = sama5_dt_device_init,
+        .dt_compat      = sama5_alt_dt_board_compat,
+        .l2c_aux_mask   = ~0UL,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 68f1ab6bd08f..a6aa4a2432f2 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -138,6 +138,8 @@ static struct gpio_led flexibity_leds[] = {
 
 static void __init flexibity_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -160,7 +162,7 @@ static void __init flexibity_board_init(void)
 
 MACHINE_START(FLEXIBITY, "Flexibity Connect")
         /* Maintainer: Maxim Osipov */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = flexibity_init_early,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
deleted file mode 100644
index 8b22c60bb238..000000000000
--- a/arch/arm/mach-at91/board-foxg20.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2008 Atmel
- *  Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com
- *  Copyright (C) 2010 Sergio Tanzilli - tanzilli@acmesystems.it
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/at73c213.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/clk.h>
-#include <linux/w1-gpio.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/at91sam9_smc.h>
-
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-
-/*
- * The FOX Board G20 hardware comes as the "Netus G20" board with
- * just the cpu, ram, dataflash and two header connectors.
- * This is plugged into the FOX Board which provides the ethernet,
- * usb, rtc, leds, switch, ...
- *
- * For more info visit: http://www.acmesystems.it/foxg20
- */
-
-
-static void __init foxg20_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata foxg20_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata foxg20_udc_data = {
-        .vbus_pin       = AT91_PIN_PC6,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-
-
-/*
- * SPI devices.
- */
-static struct spi_board_info foxg20_spi_devices[] = {
-#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
-        {
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata foxg20_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA7,
-        .is_rmii        = 1,
-};
-
-/*
- * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
- */
-static struct mci_platform_data __initdata foxg20_mci0_data = {
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-
-
-/*
- * LEDs
- */
-static struct gpio_led foxg20_leds[] = {
-        {       /* user led, red */
-                .name                   = "user_led",
-                .gpio                   = AT91_PIN_PC7,
-                .active_low             = 0,
-                .default_trigger        = "heartbeat",
-        },
-};
-
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button foxg20_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PC4,
-                .code           = BTN_1,
-                .desc           = "Button 1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-};
-
-static struct gpio_keys_platform_data foxg20_button_data = {
-        .buttons        = foxg20_buttons,
-        .nbuttons       = ARRAY_SIZE(foxg20_buttons),
-};
-
-static struct platform_device foxg20_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &foxg20_button_data,
-        }
-};
-
-static void __init foxg20_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PC4, 1);   /* btn1 */
-        at91_set_deglitch(AT91_PIN_PC4, 1);
-
-        platform_device_register(&foxg20_button_device);
-}
-#else
-static void __init foxg20_add_device_buttons(void) {}
-#endif
-
-
-#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-static struct w1_gpio_platform_data w1_gpio_pdata = {
-        /* If you choose to use a pin other than PB16 it needs to be 3.3V */
-        .pin            = AT91_PIN_PB16,
-        .is_open_drain  = 1,
-        .ext_pullup_enable_pin  = -EINVAL,
-};
-
-static struct platform_device w1_device = {
-        .name                   = "w1-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &w1_gpio_pdata,
-};
-
-static void __init at91_add_device_w1(void)
-{
-        at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
-        at91_set_multi_drive(w1_gpio_pdata.pin, 1);
-        platform_device_register(&w1_device);
-}
-
-#endif
-
-
-static struct i2c_board_info __initdata foxg20_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50),
-        },
-};
-
-
-static void __init foxg20_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                                ATMEL_UART_CTS
-                                | ATMEL_UART_RTS
-                                | ATMEL_UART_DTR
-                                | ATMEL_UART_DSR
-                                | ATMEL_UART_DCD
-                                | ATMEL_UART_RI);
-
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                ATMEL_UART_CTS
-                | ATMEL_UART_RTS);
-
-        /* USART2 on ttyS3. (Rx & Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
-
-        /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US3, 4,
-                ATMEL_UART_CTS
-                | ATMEL_UART_RTS);
-
-        /* USART4 on ttyS5. (Rx & Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
-
-        /* USART5 on ttyS6. (Rx & Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-
-        /* Set the internal pull-up resistor on DRXD */
-        at91_set_A_periph(AT91_PIN_PB14, 1);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&foxg20_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&foxg20_udc_data);
-        /* SPI */
-        at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices));
-        /* Ethernet */
-        at91_add_device_eth(&foxg20_macb_data);
-        /* MMC */
-        at91_add_device_mci(0, &foxg20_mci0_data);
-        /* I2C */
-        at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices));
-        /* LEDs */
-        at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds));
-        /* Push Buttons */
-        foxg20_add_device_buttons();
-#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-        at91_add_device_w1();
-#endif
-}
-
-MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
-        /* Maintainer: Sergio Tanzilli */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = foxg20_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = foxg20_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index b729dd1271bf..bf5cc55c7db6 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -576,7 +576,7 @@ static void __init gsia18s_board_init(void)
 }
 
 MACHINE_START(GSIA18S, "GS_IA18_S")
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = gsia18s_init_early,
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index b48d95ec5152..9c26b94ce448 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -219,7 +219,7 @@ static void __init pcontrol_g20_board_init(void)
 
 MACHINE_START(PCONTROL_G20, "PControl G20")
         /* Maintainer: pgsellmann@portner-elektronik.at */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = pcontrol_g20_init_early,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
deleted file mode 100644
index f28e8b74df4b..000000000000
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * board-rsi-ews.c
- *
- *  Copyright (C)
- *  2005 SAN People,
- *  2008-2011 R-S-I Elektrotechnik GmbH & Co. KG
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-
-#include <linux/gpio.h>
-
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-
-static void __init rsi_ews_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-
-/*
- * Ethernet
- */
-static struct macb_platform_data rsi_ews_eth_data __initdata = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-
-/*
- * USB Host
- */
-static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * SD/MC
- */
-static struct mci_platform_data __initdata rsi_ews_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PB27,
-                .wp_pin         = AT91_PIN_PB29,
-        },
-};
-
-/*
- * I2C
- */
-static struct i2c_board_info rsi_ews_i2c_devices[] __initdata = {
-        {
-                I2C_BOARD_INFO("ds1337", 0x68),
-        },
-        {
-                I2C_BOARD_INFO("24c01", 0x50),
-        }
-};
-
-/*
- * LEDs
- */
-static struct gpio_led rsi_ews_leds[] = {
-        {
-                .name                   = "led0",
-                .gpio                   = AT91_PIN_PB6,
-                .active_low             = 0,
-        },
-        {
-                .name                   = "led1",
-                .gpio                   = AT91_PIN_PB7,
-                .active_low             = 0,
-        },
-        {
-                .name                   = "led2",
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 0,
-        },
-        {
-                .name                   = "led3",
-                .gpio                   = AT91_PIN_PB9,
-                .active_low             = 0,
-        },
-};
-
-/*
- * DataFlash
- */
-static struct spi_board_info rsi_ews_spi_devices[] = {
-        {       /* DataFlash chip 1*/
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 5 * 1000 * 1000,
-        },
-        {       /* DataFlash chip 2*/
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 5 * 1000 * 1000,
-        },
-};
-
-/*
- * NOR flash
- */
-static struct mtd_partition rsiews_nor_partitions[] = {
-        {
-                .name           = "boot",
-                .offset         = 0,
-                .size           = 3 * SZ_128K,
-                .mask_flags     = MTD_WRITEABLE
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = SZ_2M - (3 * SZ_128K)
-        },
-        {
-                .name           = "root",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = SZ_8M
-        },
-        {
-                .name           = "kernelupd",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = 3 * SZ_512K,
-                .mask_flags     = MTD_WRITEABLE
-        },
-        {
-                .name           = "rootupd",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = 9 * SZ_512K,
-                .mask_flags     = MTD_WRITEABLE
-        },
-};
-
-static struct physmap_flash_data rsiews_nor_data = {
-        .width          = 2,
-        .parts          = rsiews_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(rsiews_nor_partitions),
-};
-
-#define NOR_BASE        AT91_CHIPSELECT_0
-#define NOR_SIZE        SZ_16M
-
-static struct resource nor_flash_resources[] = {
-        {
-                .start  = NOR_BASE,
-                .end    = NOR_BASE + NOR_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device rsiews_nor_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &rsiews_nor_data,
-        },
-        .resource       = nor_flash_resources,
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-};
-
-/*
- * Init Func
- */
-static void __init rsi_ews_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        /* This one is for debugging */
-        at91_register_uart(0, 0, 0);
-
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        /* Dialin/-out modem interface */
-        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-
-        /* USART3 on ttyS4. (Rx, Tx, RTS) */
-        /* RS485 communication */
-        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
-        at91_add_device_serial();
-        at91_set_gpio_output(AT91_PIN_PA21, 0);
-        /* Ethernet */
-        at91_add_device_eth(&rsi_ews_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&rsi_ews_usbh_data);
-        /* I2C */
-        at91_add_device_i2c(rsi_ews_i2c_devices,
-                        ARRAY_SIZE(rsi_ews_i2c_devices));
-        /* SPI */
-        at91_add_device_spi(rsi_ews_spi_devices,
-                        ARRAY_SIZE(rsi_ews_spi_devices));
-        /* MMC */
-        at91_add_device_mci(0, &rsi_ews_mci0_data);
-        /* NOR Flash */
-        platform_device_register(&rsiews_nor_flash);
-        /* LEDs */
-        at91_gpio_leds(rsi_ews_leds, ARRAY_SIZE(rsi_ews_leds));
-}
-
-MACHINE_START(RSI_EWS, "RSI EWS")
-        /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = rsi_ews_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = rsi_ews_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index d24dda67e2d3..c2166e3a236c 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -187,6 +187,8 @@ static struct gpio_led ek_leds[] = {
 
 static void __init ek_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -219,7 +221,7 @@ static void __init ek_board_init(void)
 
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
         /* Maintainer: Olimex */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 65dea12d685e..bf8a946b4cd0 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -45,7 +45,6 @@
 #include <mach/system_rev.h>
 
 #include "at91_aic.h"
-#include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
@@ -307,6 +306,8 @@ static void __init ek_add_device_buttons(void) {}
 
 static void __init ek_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -344,7 +345,7 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 4637432de08f..e85ada820bfb 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -49,7 +49,6 @@
 #include <mach/system_rev.h>
 
 #include "at91_aic.h"
-#include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
@@ -561,6 +560,8 @@ static struct gpio_led ek_leds[] = {
 
 static void __init ek_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -603,7 +604,7 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
@@ -613,7 +614,7 @@ MACHINE_END
 
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index fc446097f410..d76680f2a209 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -50,7 +50,6 @@
 #include <mach/system_rev.h>
 
 #include "at91_aic.h"
-#include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
@@ -439,6 +438,8 @@ static struct platform_device *devices[] __initdata = {
 
 static void __init ek_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -483,7 +484,7 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index e1be6e25b380..49f075213451 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -410,7 +410,7 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
@@ -420,7 +420,7 @@ MACHINE_END
 
 MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index b227732b0c83..a517c7f7af92 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -48,7 +48,6 @@
 #include <mach/system_rev.h>
 
 #include "at91_aic.h"
-#include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
@@ -471,6 +470,8 @@ static struct platform_device *devices[] __initdata = {
 
 static void __init ek_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DGBU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -517,7 +518,7 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index b64648b4a1fc..8bca329b0293 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -35,7 +35,6 @@
 
 
 #include "at91_aic.h"
-#include "at91_shdwc.h"
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
@@ -292,6 +291,8 @@ static void __init ek_add_device_buttons(void) {}
 
 static void __init ek_board_init(void)
 {
+        at91_register_devices();
+
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -323,7 +324,7 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 1b870e6def0c..b4aff840a1a0 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -154,6 +154,8 @@ static void __init snapper9260_add_device_nand(void)
 
 static void __init snapper9260_board_init(void)
 {
+        at91_register_devices();
+
         at91_add_device_i2c(snapper9260_i2c_devices,
                             ARRAY_SIZE(snapper9260_i2c_devices));
 
@@ -178,7 +180,7 @@ static void __init snapper9260_board_init(void)
 }
 
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = snapper9260_init_early,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 3b575036ff96..e825641a1dee 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -275,7 +275,7 @@ static void __init stamp9g20evb_board_init(void)
 
 MACHINE_START(PORTUXG20, "taskit PortuxG20")
         /* Maintainer: taskit GmbH */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = stamp9g20_init_early,
@@ -285,7 +285,7 @@ MACHINE_END
 
 MACHINE_START(STAMP9G20, "taskit Stamp9G20")
         /* Maintainer: taskit GmbH */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = at91_init_time,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic_handle_irq,
         .init_early     = stamp9g20_init_early,
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 034529d801b2..d66f102c352a 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -962,6 +962,7 @@ static int __init at91_clock_reset(void)
         }
 
         at91_pmc_write(AT91_PMC_SCDR, scdr);
+        at91_pmc_write(AT91_PMC_PCDR, pcdr);
         if (cpu_is_sama5d3())
                 at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
 
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 631fa3b8c16d..81959cf4a137 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -8,12 +8,16 @@
  * published by the Free Software Foundation.
  */
 
+#ifndef _AT91_GENERIC_H
+#define _AT91_GENERIC_H
+
 #include <linux/clkdev.h>
 #include <linux/of.h>
 #include <linux/reboot.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
+extern void __init at91_alt_map_io(void);
 extern void __init at91_init_sram(int bank, unsigned long base,
                                   unsigned int length);
 
@@ -37,12 +41,15 @@ extern int  __init at91_aic5_of_init(struct device_node *node,
 extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
 extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
 
+ /* Devices */
+extern void __init at91_register_devices(void);
 
  /* Timer */
+extern void __init at91_init_time(void);
 extern void at91rm9200_ioremap_st(u32 addr);
 extern void at91rm9200_timer_init(void);
 extern void at91sam926x_ioremap_pit(u32 addr);
-extern void at91sam926x_pit_init(void);
+extern void at91sam926x_pit_init(int irq);
 extern void at91x40_timer_init(void);
 
  /* Clocks */
@@ -62,14 +69,6 @@ extern void at91_irq_resume(void);
 /* idle */
 extern void at91sam9_idle(void);
 
-/* reset */
-extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(enum reboot_mode, const char *);
-extern void at91sam9g45_restart(enum reboot_mode, const char *);
-
-/* shutdown */
-extern void at91_ioremap_shdwc(u32 base_addr);
-
 /* Matrix */
 extern void at91_ioremap_matrix(u32 base_addr);
 
@@ -90,3 +89,5 @@ extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
                                           struct device_node *parent);
 
 extern u32 at91_get_extern_irq(void);
+
+#endif /* _AT91_GENERIC_H */
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index 732b11c37f1a..7b7366253ceb 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -71,4 +71,10 @@
 #define ABCDSR_PERIPH_C 0x2
 #define ABCDSR_PERIPH_D 0x3
 
+#define SAMA5D3_PIO_DRIVER1             0x118  /*PIO Driver 1 register offset*/
+#define SAMA5D3_PIO_DRIVER2             0x11C  /*PIO Driver 2 register offset*/
+
+#define AT91SAM9X5_PIO_DRIVER1  0x114  /*PIO Driver 1 register offset*/
+#define AT91SAM9X5_PIO_DRIVER2  0x118  /*PIO Driver 2 register offset*/
+
 #endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 86c71debab5b..b27e9ca65653 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -36,7 +36,7 @@
 #define ARCH_ID_AT91M40807      0x14080745
 #define ARCH_ID_AT91R40008      0x44000840
 
-#define ARCH_ID_SAMA5D3         0x8A5C07C0
+#define ARCH_ID_SAMA5           0x8A5C07C0
 
 #define ARCH_EXID_AT91SAM9M11   0x00000001
 #define ARCH_EXID_AT91SAM9M10   0x00000002
@@ -49,12 +49,19 @@
 #define ARCH_EXID_AT91SAM9G25   0x00000003
 #define ARCH_EXID_AT91SAM9X25   0x00000004
 
+#define ARCH_EXID_SAMA5D3       0x00004300
 #define ARCH_EXID_SAMA5D31      0x00444300
 #define ARCH_EXID_SAMA5D33      0x00414300
 #define ARCH_EXID_SAMA5D34      0x00414301
 #define ARCH_EXID_SAMA5D35      0x00584300
 #define ARCH_EXID_SAMA5D36      0x00004301
 
+#define ARCH_EXID_SAMA5D4       0x00000007
+#define ARCH_EXID_SAMA5D41      0x00000001
+#define ARCH_EXID_SAMA5D42      0x00000002
+#define ARCH_EXID_SAMA5D43      0x00000003
+#define ARCH_EXID_SAMA5D44      0x00000004
+
 #define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
@@ -86,6 +93,9 @@ enum at91_soc_type {
         /* SAMA5D3 */
         AT91_SOC_SAMA5D3,
 
+        /* SAMA5D4 */
+        AT91_SOC_SAMA5D4,
+
         /* Unknown type */
         AT91_SOC_UNKNOWN,
 };
@@ -108,6 +118,10 @@ enum at91_soc_subtype {
         AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
         AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
 
+        /* SAMA5D4 */
+        AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
+        AT91_SOC_SAMA5D44,
+
         /* No subtype for this SoC */
         AT91_SOC_SUBTYPE_NONE,
 
@@ -211,6 +225,12 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_sama5d3()        (0)
 #endif
 
+#ifdef CONFIG_SOC_SAMA5D4
+#define cpu_is_sama5d4()        (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
+#else
+#define cpu_is_sama5d4()        (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index c6bb9e2d9baa..2103a90f2261 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -16,8 +16,11 @@
 
 #if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
 #define AT91_DBGU AT91_BASE_DBGU0
-#else
+#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
 #define AT91_DBGU AT91_BASE_DBGU1
+#else
+/* On sama5d4, use USART3 as low level serial console */
+#define AT91_DBGU SAMA5D4_BASE_USART3
 #endif
 
         .macro  addruart, rp, rv, tmp
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 56338245653a..c13797352688 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,8 +19,10 @@
 /* DBGU base */
 /* rm9200, 9260/9g20, 9261/9g10, 9rl */
 #define AT91_BASE_DBGU0 0xfffff200
-/* 9263, 9g45 */
+/* 9263, 9g45, sama5d3 */
 #define AT91_BASE_DBGU1 0xffffee00
+/* sama5d4 */
+#define AT91_BASE_DBGU2 0xfc069000
 
 #if defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
@@ -34,6 +36,7 @@
 #include <mach/at91sam9x5.h>
 #include <mach/at91sam9n12.h>
 #include <mach/sama5d3.h>
+#include <mach/sama5d4.h>
 
 /*
  * On all at91 except rm9200 and x40 have the System Controller starts
@@ -47,9 +50,15 @@
  * and map the same memory space
  */
 #define AT91_BASE_SYS   0xffffc000
+
 #endif
 
 /*
+ * On sama5d4 there is no system controller, we map some needed peripherals
+ */
+#define AT91_ALT_BASE_SYS       0xfc069000
+
+/*
  * On all at91 have the Advanced Interrupt Controller starts at address
  * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
  */
@@ -69,23 +78,35 @@
  */
 #define AT91_IO_PHYS_BASE       0xFFF78000
 #define AT91_IO_VIRT_BASE       IOMEM(0xFF000000 - AT91_IO_SIZE)
+
+/*
+ * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
+ * to 0xFB069000 .. 0xFB06F000.  (24Kb)
+ */
+#define AT91_ALT_IO_PHYS_BASE   AT91_ALT_BASE_SYS
+#define AT91_ALT_IO_VIRT_BASE   IOMEM(0xFB069000)
 #else
 /*
  * Identity mapping for the non MMU case.
  */
 #define AT91_IO_PHYS_BASE       AT91_BASE_SYS
 #define AT91_IO_VIRT_BASE       IOMEM(AT91_IO_PHYS_BASE)
+
+#define AT91_ALT_IO_PHYS_BASE   AT91_ALT_BASE_SYS
+#define AT91_ALT_IO_VIRT_BASE   IOMEM(AT91_ALT_BASE_SYS)
 #endif
 
 #define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
 
  /* Convert a physical IO address to virtual IO address */
 #define AT91_IO_P2V(x)          ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
+#define AT91_ALT_IO_P2V(x)      ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
 
 /*
  * Virtual to Physical Address mapping for IO devices.
  */
 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
+#define AT91_ALT_VA_BASE_SYS    AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
 
  /* Internal SRAM is mapped below the IO devices */
 #define AT91_SRAM_MAX           SZ_1M
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
new file mode 100644
index 000000000000..f256a45d9854
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -0,0 +1,33 @@
+/*
+ * Chip-specific header file for the SAMA5D4 family
+ *
+ *  Copyright (C) 2013 Atmel Corporation,
+ *                     Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Common definitions.
+ * Based on SAMA5D4 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef SAMA5D4_H
+#define SAMA5D4_H
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define SAMA5D4_BASE_USART3     0xfc00c000 /* (USART3 non-secure) Base Address */
+#define SAMA5D4_BASE_PMC        0xf0018000 /* (PMC) Base Address */
+#define SAMA5D4_BASE_MPDDRC     0xf0010000 /* (MPDDRC) Base Address */
+#define SAMA5D4_BASE_PIOD       0xfc068000 /* (PIOD) Base Address */
+
+/* Some other peripherals */
+#define SAMA5D4_BASE_SYS2       SAMA5D4_BASE_PIOD
+
+/*
+ * Internal Memory.
+ */
+#define SAMA5D4_NS_SRAM_BASE     0x00210000      /* Internal SRAM base address Non-Secure */
+#define SAMA5D4_NS_SRAM_SIZE     (64 * SZ_1K)   /* Internal SRAM size Non-Secure part (64Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 4bb644f8e87c..acb2d890ad7e 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
         0,
 };
 
-static const u32 uarts_sama5[] = {
+static const u32 uarts_sama5d3[] = {
         AT91_BASE_DBGU1,
         SAMA5D3_BASE_USART0,
         SAMA5D3_BASE_USART1,
@@ -103,6 +103,12 @@ static const u32 uarts_sama5[] = {
         0,
 };
 
+static const u32 uarts_sama5d4[] = {
+        AT91_BASE_DBGU2,
+        SAMA5D4_BASE_USART3,
+        0,
+};
+
 static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 {
         u32 cidr, socid;
@@ -134,8 +140,14 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
         case ARCH_ID_AT91SAM9X5:
                 return uarts_sam9x5;
 
-        case ARCH_ID_SAMA5D3:
-                return uarts_sama5;
+        case ARCH_ID_SAMA5:
+                cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
+                if (cidr & ARCH_EXID_SAMA5D3)
+                        return uarts_sama5d3;
+                else if (cidr & ARCH_EXID_SAMA5D4)
+                        return uarts_sama5d4;
+
+                break;
         }
 
         /* at91sam9g10 */
@@ -156,9 +168,10 @@ static inline void arch_decomp_setup(void)
         const u32* usarts;
 
         usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
-
         if (!usarts)
                 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
+        if (!usarts)
+                usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
         if (!usarts) {
                 at91_uart = NULL;
                 return;
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 3d192c5aee66..cdb3ec9efd2b 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -48,11 +48,6 @@ void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
 static struct device_node *at91_aic_np;
 static unsigned int n_irqs = NR_AIC_IRQS;
-static unsigned long at91_aic_caps = 0;
-
-/* AIC5 introduces a Source Select Register */
-#define AT91_AIC_CAP_AIC5       (1 << 0)
-#define has_aic5()              (at91_aic_caps & AT91_AIC_CAP_AIC5)
 
 #ifdef CONFIG_PM
 
@@ -92,50 +87,14 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 
 void at91_irq_suspend(void)
 {
-        int bit = -1;
-
-        if (has_aic5()) {
-                /* disable enabled irqs */
-                while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
-                        at91_aic_write(AT91_AIC5_SSR,
-                                       bit & AT91_AIC5_INTSEL_MSK);
-                        at91_aic_write(AT91_AIC5_IDCR, 1);
-                }
-                /* enable wakeup irqs */
-                bit = -1;
-                while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
-                        at91_aic_write(AT91_AIC5_SSR,
-                                       bit & AT91_AIC5_INTSEL_MSK);
-                        at91_aic_write(AT91_AIC5_IECR, 1);
-                }
-        } else {
-                at91_aic_write(AT91_AIC_IDCR, *backups);
-                at91_aic_write(AT91_AIC_IECR, *wakeups);
-        }
+        at91_aic_write(AT91_AIC_IDCR, *backups);
+        at91_aic_write(AT91_AIC_IECR, *wakeups);
 }
 
 void at91_irq_resume(void)
 {
-        int bit = -1;
-
-        if (has_aic5()) {
-                /* disable wakeup irqs */
-                while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
-                        at91_aic_write(AT91_AIC5_SSR,
-                                       bit & AT91_AIC5_INTSEL_MSK);
-                        at91_aic_write(AT91_AIC5_IDCR, 1);
-                }
-                /* enable irqs disabled for suspend */
-                bit = -1;
-                while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
-                        at91_aic_write(AT91_AIC5_SSR,
-                                       bit & AT91_AIC5_INTSEL_MSK);
-                        at91_aic_write(AT91_AIC5_IECR, 1);
-                }
-        } else {
-                at91_aic_write(AT91_AIC_IDCR, *wakeups);
-                at91_aic_write(AT91_AIC_IECR, *backups);
-        }
+        at91_aic_write(AT91_AIC_IDCR, *wakeups);
+        at91_aic_write(AT91_AIC_IECR, *backups);
 }
 
 #else
@@ -169,21 +128,6 @@ at91_aic_handle_irq(struct pt_regs *regs)
                 handle_IRQ(irqnr, regs);
 }
 
-asmlinkage void __exception_irq_entry
-at91_aic5_handle_irq(struct pt_regs *regs)
-{
-        u32 irqnr;
-        u32 irqstat;
-
-        irqnr = at91_aic_read(AT91_AIC5_IVR);
-        irqstat = at91_aic_read(AT91_AIC5_ISR);
-
-        if (!irqstat)
-                at91_aic_write(AT91_AIC5_EOICR, 0);
-        else
-                handle_IRQ(irqnr, regs);
-}
-
 static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
@@ -192,15 +136,6 @@ static void at91_aic_mask_irq(struct irq_data *d)
         clear_backup(d->hwirq);
 }
 
-static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
-{
-        /* Disable interrupt on AIC5 */
-        at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
-        at91_aic_write(AT91_AIC5_IDCR, 1);
-        /* Update ISR cache */
-        clear_backup(d->hwirq);
-}
-
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
@@ -209,15 +144,6 @@ static void at91_aic_unmask_irq(struct irq_data *d)
         set_backup(d->hwirq);
 }
 
-static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
-{
-        /* Enable interrupt on AIC5 */
-        at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
-        at91_aic_write(AT91_AIC5_IECR, 1);
-        /* Update ISR cache */
-        set_backup(d->hwirq);
-}
-
 static void at91_aic_eoi(struct irq_data *d)
 {
         /*
@@ -227,11 +153,6 @@ static void at91_aic_eoi(struct irq_data *d)
         at91_aic_write(AT91_AIC_EOICR, 0);
 }
 
-static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
-{
-        at91_aic_write(AT91_AIC5_EOICR, 0);
-}
-
 static unsigned long *at91_extern_irq;
 
 u32 at91_get_extern_irq(void)
@@ -282,16 +203,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
         if (srctype < 0)
                 return srctype;
 
-        if (has_aic5()) {
-                at91_aic_write(AT91_AIC5_SSR,
-                               d->hwirq & AT91_AIC5_INTSEL_MSK);
-                smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
-                at91_aic_write(AT91_AIC5_SMR, smr | srctype);
-        } else {
-                smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
-                      & ~AT91_AIC_SRCTYPE;
-                at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
-        }
+        smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
+        at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
 
         return 0;
 }
@@ -331,177 +244,6 @@ static void __init at91_aic_hw_init(unsigned int spu_vector)
         at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }
 
-static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
-{
-        int i;
-
-        /*
-         * Perform 8 End Of Interrupt Command to make sure AIC
-         * will not Lock out nIRQ
-         */
-        for (i = 0; i < 8; i++)
-                at91_aic_write(AT91_AIC5_EOICR, 0);
-
-        /*
-         * Spurious Interrupt ID in Spurious Vector Register.
-         * When there is no current interrupt, the IRQ Vector Register
-         * reads the value stored in AIC_SPU
-         */
-        at91_aic_write(AT91_AIC5_SPU, spu_vector);
-
-        /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_aic_write(AT91_AIC5_DCR, 0);
-
-        /* Disable and clear all interrupts initially */
-        for (i = 0; i < n_irqs; i++) {
-                at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
-                at91_aic_write(AT91_AIC5_IDCR, 1);
-                at91_aic_write(AT91_AIC5_ICCR, 1);
-        }
-}
-
-#if defined(CONFIG_OF)
-static unsigned int *at91_aic_irq_priorities;
-
-static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
-                                                        irq_hw_number_t hw)
-{
-        /* Put virq number in Source Vector Register */
-        at91_aic_write(AT91_AIC_SVR(hw), virq);
-
-        /* Active Low interrupt, with priority */
-        at91_aic_write(AT91_AIC_SMR(hw),
-                       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
-
-        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
-        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
-
-        return 0;
-}
-
-static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
-                irq_hw_number_t hw)
-{
-        at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
-
-        /* Put virq number in Source Vector Register */
-        at91_aic_write(AT91_AIC5_SVR, virq);
-
-        /* Active Low interrupt, with priority */
-        at91_aic_write(AT91_AIC5_SMR,
-                       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
-
-        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
-        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
-
-        return 0;
-}
-
-static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
-                                const u32 *intspec, unsigned int intsize,
-                                irq_hw_number_t *out_hwirq, unsigned int *out_type)
-{
-        if (WARN_ON(intsize < 3))
-                return -EINVAL;
-        if (WARN_ON(intspec[0] >= n_irqs))
-                return -EINVAL;
-        if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
-                    || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
-                return -EINVAL;
-
-        *out_hwirq = intspec[0];
-        *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
-        at91_aic_irq_priorities[*out_hwirq] = intspec[2];
-
-        return 0;
-}
-
-static struct irq_domain_ops at91_aic_irq_ops = {
-        .map    = at91_aic_irq_map,
-        .xlate  = at91_aic_irq_domain_xlate,
-};
-
-int __init at91_aic_of_common_init(struct device_node *node,
-                                    struct device_node *parent)
-{
-        struct property *prop;
-        const __be32 *p;
-        u32 val;
-
-        at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
-                                  * sizeof(*at91_extern_irq), GFP_KERNEL);
-        if (!at91_extern_irq)
-                return -ENOMEM;
-
-        if (at91_aic_pm_init()) {
-                kfree(at91_extern_irq);
-                return -ENOMEM;
-        }
-
-        at91_aic_irq_priorities = kzalloc(n_irqs
-                                          * sizeof(*at91_aic_irq_priorities),
-                                          GFP_KERNEL);
-        if (!at91_aic_irq_priorities)
-                return -ENOMEM;
-
-        at91_aic_base = of_iomap(node, 0);
-        at91_aic_np = node;
-
-        at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
-                                                &at91_aic_irq_ops, NULL);
-        if (!at91_aic_domain)
-                panic("Unable to add AIC irq domain (DT)\n");
-
-        of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
-                if (val >= n_irqs)
-                        pr_warn("AIC: external irq %d >= %d skip it\n",
-                                val, n_irqs);
-                else
-                        set_bit(val, at91_extern_irq);
-        }
-
-        irq_set_default_host(at91_aic_domain);
-
-        return 0;
-}
-
-int __init at91_aic_of_init(struct device_node *node,
-                                     struct device_node *parent)
-{
-        int err;
-
-        err = at91_aic_of_common_init(node, parent);
-        if (err)
-                return err;
-
-        at91_aic_hw_init(n_irqs);
-
-        return 0;
-}
-
-int __init at91_aic5_of_init(struct device_node *node,
-                                     struct device_node *parent)
-{
-        int err;
-
-        at91_aic_caps |= AT91_AIC_CAP_AIC5;
-        n_irqs = NR_AIC5_IRQS;
-        at91_aic_chip.irq_ack           = at91_aic5_mask_irq;
-        at91_aic_chip.irq_mask          = at91_aic5_mask_irq;
-        at91_aic_chip.irq_unmask        = at91_aic5_unmask_irq;
-        at91_aic_chip.irq_eoi           = at91_aic5_eoi;
-        at91_aic_irq_ops.map            = at91_aic5_irq_map;
-
-        err = at91_aic_of_common_init(node, parent);
-        if (err)
-                return err;
-
-        at91_aic5_hw_init(n_irqs);
-
-        return 0;
-}
-#endif
-
 /*
  * Initialize the AIC interrupt controller.
  */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e95554532987..4073ab7f38f3 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -34,79 +34,8 @@
 #include "pm.h"
 #include "gpio.h"
 
-/*
- * Show the reason for the previous system reset.
- */
-
-#include "at91_rstc.h"
-#include "at91_shdwc.h"
-
 static void (*at91_pm_standby)(void);
 
-static void __init show_reset_status(void)
-{
-        static char reset[] __initdata = "reset";
-
-        static char general[] __initdata = "general";
-        static char wakeup[] __initdata = "wakeup";
-        static char watchdog[] __initdata = "watchdog";
-        static char software[] __initdata = "software";
-        static char user[] __initdata = "user";
-        static char unknown[] __initdata = "unknown";
-
-        static char signal[] __initdata = "signal";
-        static char rtc[] __initdata = "rtc";
-        static char rtt[] __initdata = "rtt";
-        static char restore[] __initdata = "power-restored";
-
-        char *reason, *r2 = reset;
-        u32 reset_type, wake_type;
-
-        if (!at91_shdwc_base || !at91_rstc_base)
-                return;
-
-        reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
-        wake_type = at91_shdwc_read(AT91_SHDW_SR);
-
-        switch (reset_type) {
-        case AT91_RSTC_RSTTYP_GENERAL:
-                reason = general;
-                break;
-        case AT91_RSTC_RSTTYP_WAKEUP:
-                /* board-specific code enabled the wakeup sources */
-                reason = wakeup;
-
-                /* "wakeup signal" */
-                if (wake_type & AT91_SHDW_WAKEUP0)
-                        r2 = signal;
-                else {
-                        r2 = reason;
-                        if (wake_type & AT91_SHDW_RTTWK)        /* rtt wakeup */
-                                reason = rtt;
-                        else if (wake_type & AT91_SHDW_RTCWK)   /* rtc wakeup */
-                                reason = rtc;
-                        else if (wake_type == 0)        /* power-restored wakeup */
-                                reason = restore;
-                        else                            /* unknown wakeup */
-                                reason = unknown;
-                }
-                break;
-        case AT91_RSTC_RSTTYP_WATCHDOG:
-                reason = watchdog;
-                break;
-        case AT91_RSTC_RSTTYP_SOFTWARE:
-                reason = software;
-                break;
-        case AT91_RSTC_RSTTYP_USER:
-                reason = user;
-                break;
-        default:
-                reason = unknown;
-                break;
-        }
-        pr_info("AT91: Starting after %s %s\n", reason, r2);
-}
-
 static int at91_pm_valid_state(suspend_state_t state)
 {
         switch (state) {
@@ -206,16 +135,19 @@ static int at91_pm_enter(suspend_state_t state)
                 at91_pinctrl_gpio_suspend();
         else
                 at91_gpio_suspend();
-        at91_irq_suspend();
 
-        pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
-                        /* remember all the always-wake irqs */
-                        (at91_pmc_read(AT91_PMC_PCSR)
-                                        | (1 << AT91_ID_FIQ)
-                                        | (1 << AT91_ID_SYS)
-                                        | (at91_get_extern_irq()))
-                                & at91_aic_read(AT91_AIC_IMR),
-                        state);
+        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
+                at91_irq_suspend();
+
+                pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
+                                /* remember all the always-wake irqs */
+                                (at91_pmc_read(AT91_PMC_PCSR)
+                                                | (1 << AT91_ID_FIQ)
+                                                | (1 << AT91_ID_SYS)
+                                                | (at91_get_extern_irq()))
+                                        & at91_aic_read(AT91_AIC_IMR),
+                                state);
+        }
 
         switch (state) {
                 /*
@@ -280,12 +212,17 @@ static int at91_pm_enter(suspend_state_t state)
                         goto error;
         }
 
-        pr_debug("AT91: PM - wakeup %08x\n",
-                        at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR));
+        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
+                pr_debug("AT91: PM - wakeup %08x\n",
+                         at91_aic_read(AT91_AIC_IPR) &
+                         at91_aic_read(AT91_AIC_IMR));
 
 error:
         target_state = PM_SUSPEND_ON;
-        at91_irq_resume();
+
+        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
+                at91_irq_resume();
+
         if (of_have_populated_dt())
                 at91_pinctrl_gpio_resume();
         else
@@ -338,7 +275,6 @@ static int __init at91_pm_init(void)
 
         suspend_set_ops(&at91_pm_ops);
 
-        show_reset_status();
         return 0;
 }
 arch_initcall(at91_pm_init);
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
new file mode 100644
index 000000000000..7638509639f4
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -0,0 +1,64 @@
+/*
+ *  Chip-specific setup code for the SAMA5D4 family
+ *
+ *  Copyright (C) 2013 Atmel Corporation,
+ *                     Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk/at91_pmc.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/sama5d4.h>
+#include <mach/cpu.h>
+#include <mach/hardware.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Processor initialization
+ * -------------------------------------------------------------------- */
+static struct map_desc at91_io_desc[] __initdata = {
+        {
+        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
+        .pfn            = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
+        .length         = SZ_512,
+        .type           = MT_DEVICE,
+        },
+        {
+        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
+        .pfn            = __phys_to_pfn(SAMA5D4_BASE_PMC),
+        .length         = SZ_512,
+        .type           = MT_DEVICE,
+        },
+        { /* On sama5d4, we use USART3 as serial console */
+        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
+        .pfn            = __phys_to_pfn(SAMA5D4_BASE_USART3),
+        .length         = SZ_256,
+        .type           = MT_DEVICE,
+        },
+        { /* A bunch of peripheral with fine grained IO space */
+        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
+        .pfn            = __phys_to_pfn(SAMA5D4_BASE_SYS2),
+        .length         = SZ_2K,
+        .type           = MT_DEVICE,
+        },
+};
+
+
+static void __init sama5d4_map_io(void)
+{
+        iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
+        at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
+}
+
+AT91_SOC_START(sama5d4)
+        .map_io = sama5d4_map_io,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f7a07a58ebb6..961079250b83 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -5,6 +5,8 @@
  * Under GPLv2
  */
 
+#define pr_fmt(fmt)     "AT91: " fmt
+
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/mm.h>
@@ -20,7 +22,6 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 
-#include "at91_shdwc.h"
 #include "soc.h"
 #include "generic.h"
 #include "pm.h"
@@ -37,7 +38,7 @@ void __init at91rm9200_set_type(int type)
         else
                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 
-        pr_info("AT91: filled in soc subtype: %s\n",
+        pr_info("filled in soc subtype: %s\n",
                 at91_get_soc_subtype(&at91_soc_initdata));
 }
 
@@ -49,7 +50,8 @@ void __init at91_init_irq_default(void)
 void __init at91_init_interrupts(unsigned int *priority)
 {
         /* Initialize the AIC interrupt controller */
-        at91_aic_init(priority, at91_boot_soc.extern_irq);
+        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
+                at91_aic_init(priority, at91_boot_soc.extern_irq);
 
         /* Enable GPIO interrupts */
         at91_gpio_irq_setup();
@@ -66,7 +68,7 @@ void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
         }
         at91_ramc_base[id] = ioremap(addr, size);
         if (!at91_ramc_base[id])
-                panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
+                panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
 }
 
 static struct map_desc sram_desc[2] __initdata;
@@ -83,7 +85,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
         desc->length = length;
         desc->type = MT_MEMORY_RWX_NONCACHED;
 
-        pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
+        pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
                 base, length, desc->virtual);
 
         iotable_init(desc, 1);
@@ -96,6 +98,13 @@ static struct map_desc at91_io_desc __initdata __maybe_unused = {
         .type           = MT_DEVICE,
 };
 
+static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
+        .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
+        .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
+        .length         = 24 * SZ_1K,
+        .type           = MT_DEVICE,
+};
+
 static void __init soc_detect(u32 dbgu_base)
 {
         u32 cidr, socid;
@@ -158,9 +167,12 @@ static void __init soc_detect(u32 dbgu_base)
                 at91_boot_soc = at91sam9n12_soc;
                 break;
 
-        case ARCH_ID_SAMA5D3:
-                at91_soc_initdata.type = AT91_SOC_SAMA5D3;
-                at91_boot_soc = sama5d3_soc;
+        case ARCH_ID_SAMA5:
+                at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+                if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
+                        at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+                        at91_boot_soc = sama5d3_soc;
+                }
                 break;
         }
 
@@ -183,7 +195,8 @@ static void __init soc_detect(u32 dbgu_base)
         at91_soc_initdata.cidr = cidr;
 
         /* sub version of soc */
-        at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+        if (!at91_soc_initdata.exid)
+                at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 
         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
                 switch (at91_soc_initdata.exid) {
@@ -240,6 +253,54 @@ static void __init soc_detect(u32 dbgu_base)
         }
 }
 
+static void __init alt_soc_detect(u32 dbgu_base)
+{
+        u32 cidr, socid;
+
+        /* SoC ID */
+        cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
+        socid = cidr & ~AT91_CIDR_VERSION;
+
+        switch (socid) {
+        case ARCH_ID_SAMA5:
+                at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+                if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
+                        at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+                        at91_boot_soc = sama5d3_soc;
+                } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
+                        at91_soc_initdata.type = AT91_SOC_SAMA5D4;
+                        at91_boot_soc = sama5d4_soc;
+                }
+                break;
+        }
+
+        if (!at91_soc_is_detected())
+                return;
+
+        at91_soc_initdata.cidr = cidr;
+
+        /* sub version of soc */
+        if (!at91_soc_initdata.exid)
+                at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+
+        if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
+                switch (at91_soc_initdata.exid) {
+                case ARCH_EXID_SAMA5D41:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
+                        break;
+                case ARCH_EXID_SAMA5D42:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
+                        break;
+                case ARCH_EXID_SAMA5D43:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
+                        break;
+                case ARCH_EXID_SAMA5D44:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
+                        break;
+                }
+        }
+}
+
 static const char *soc_name[] = {
         [AT91_SOC_RM9200]       = "at91rm9200",
         [AT91_SOC_SAM9260]      = "at91sam9260",
@@ -252,6 +313,7 @@ static const char *soc_name[] = {
         [AT91_SOC_SAM9X5]       = "at91sam9x5",
         [AT91_SOC_SAM9N12]      = "at91sam9n12",
         [AT91_SOC_SAMA5D3]      = "sama5d3",
+        [AT91_SOC_SAMA5D4]      = "sama5d4",
         [AT91_SOC_UNKNOWN]      = "Unknown",
 };
 
@@ -279,6 +341,10 @@ static const char *soc_subtype_name[] = {
         [AT91_SOC_SAMA5D34]     = "sama5d34",
         [AT91_SOC_SAMA5D35]     = "sama5d35",
         [AT91_SOC_SAMA5D36]     = "sama5d36",
+        [AT91_SOC_SAMA5D41]     = "sama5d41",
+        [AT91_SOC_SAMA5D42]     = "sama5d42",
+        [AT91_SOC_SAMA5D43]     = "sama5d43",
+        [AT91_SOC_SAMA5D44]     = "sama5d44",
         [AT91_SOC_SUBTYPE_NONE] = "None",
         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 };
@@ -302,43 +368,44 @@ void __init at91_map_io(void)
                 soc_detect(AT91_BASE_DBGU1);
 
         if (!at91_soc_is_detected())
-                panic("AT91: Impossible to detect the SOC type");
+                panic(pr_fmt("Impossible to detect the SOC type"));
 
-        pr_info("AT91: Detected soc type: %s\n",
+        pr_info("Detected soc type: %s\n",
                 at91_get_soc_type(&at91_soc_initdata));
         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
-                pr_info("AT91: Detected soc subtype: %s\n",
+                pr_info("Detected soc subtype: %s\n",
                         at91_get_soc_subtype(&at91_soc_initdata));
 
         if (!at91_soc_is_enabled())
-                panic("AT91: Soc not enabled");
+                panic(pr_fmt("Soc not enabled"));
 
         if (at91_boot_soc.map_io)
                 at91_boot_soc.map_io();
 }
 
-void __iomem *at91_shdwc_base = NULL;
-
-static void at91sam9_poweroff(void)
+void __init at91_alt_map_io(void)
 {
-        at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
+        /* Map peripherals */
+        iotable_init(&at91_alt_io_desc, 1);
 
-void __init at91_ioremap_shdwc(u32 base_addr)
-{
-        at91_shdwc_base = ioremap(base_addr, 16);
-        if (!at91_shdwc_base)
-                panic("Impossible to ioremap at91_shdwc_base\n");
-        pm_power_off = at91sam9_poweroff;
-}
+        at91_soc_initdata.type = AT91_SOC_UNKNOWN;
+        at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 
-void __iomem *at91_rstc_base;
+        alt_soc_detect(AT91_BASE_DBGU2);
+        if (!at91_soc_is_detected())
+                panic("AT91: Impossible to detect the SOC type");
 
-void __init at91_ioremap_rstc(u32 base_addr)
-{
-        at91_rstc_base = ioremap(base_addr, 16);
-        if (!at91_rstc_base)
-                panic("Impossible to ioremap at91_rstc_base\n");
+        pr_info("AT91: Detected soc type: %s\n",
+                at91_get_soc_type(&at91_soc_initdata));
+        if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
+                pr_info("AT91: Detected soc subtype: %s\n",
+                        at91_get_soc_subtype(&at91_soc_initdata));
+
+        if (!at91_soc_is_enabled())
+                panic("AT91: Soc not enabled");
+
+        if (at91_boot_soc.map_io)
+                at91_boot_soc.map_io();
 }
 
 void __iomem *at91_matrix_base;
@@ -348,42 +415,15 @@ void __init at91_ioremap_matrix(u32 base_addr)
 {
         at91_matrix_base = ioremap(base_addr, 512);
         if (!at91_matrix_base)
-                panic("Impossible to ioremap at91_matrix_base\n");
+                panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 }
 
 #if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
-static struct of_device_id rstc_ids[] = {
-        { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
-        { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
-        { /*sentinel*/ }
-};
-
-static void at91_dt_rstc(void)
-{
-        struct device_node *np;
-        const struct of_device_id *of_id;
-
-        np = of_find_matching_node(NULL, rstc_ids);
-        if (!np)
-                panic("unable to find compatible rstc node in dtb\n");
-
-        at91_rstc_base = of_iomap(np, 0);
-        if (!at91_rstc_base)
-                panic("unable to map rstc cpu registers\n");
-
-        of_id = of_match_node(rstc_ids, np);
-        if (!of_id)
-                panic("AT91: rtsc no restart function available\n");
-
-        arm_pm_restart = of_id->data;
-
-        of_node_put(np);
-}
-
 static struct of_device_id ramc_ids[] = {
         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
+        { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
         { /*sentinel*/ }
 };
 
@@ -391,100 +431,29 @@ static void at91_dt_ramc(void)
 {
         struct device_node *np;
         const struct of_device_id *of_id;
+        int idx = 0;
+        const void *standby = NULL;
 
-        np = of_find_matching_node(NULL, ramc_ids);
-        if (!np)
-                panic("unable to find compatible ram controller node in dtb\n");
-
-        at91_ramc_base[0] = of_iomap(np, 0);
-        if (!at91_ramc_base[0])
-                panic("unable to map ramc[0] cpu registers\n");
-        /* the controller may have 2 banks */
-        at91_ramc_base[1] = of_iomap(np, 1);
+        for_each_matching_node_and_match(np, ramc_ids, &of_id) {
+                at91_ramc_base[idx] = of_iomap(np, 0);
+                if (!at91_ramc_base[idx])
+                        panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 
-        of_id = of_match_node(ramc_ids, np);
-        if (!of_id)
-                pr_warn("AT91: ramc no standby function available\n");
-        else
-                at91_pm_set_standby(of_id->data);
+                if (!standby)
+                        standby = of_id->data;
 
-        of_node_put(np);
-}
-
-static struct of_device_id shdwc_ids[] = {
-        { .compatible = "atmel,at91sam9260-shdwc", },
-        { .compatible = "atmel,at91sam9rl-shdwc", },
-        { .compatible = "atmel,at91sam9x5-shdwc", },
-        { /*sentinel*/ }
-};
-
-static const char *shdwc_wakeup_modes[] = {
-        [AT91_SHDW_WKMODE0_NONE]        = "none",
-        [AT91_SHDW_WKMODE0_HIGH]        = "high",
-        [AT91_SHDW_WKMODE0_LOW]         = "low",
-        [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
-};
-
-const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
-{
-        const char *pm;
-        int err, i;
-
-        err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
-        if (err < 0)
-                return AT91_SHDW_WKMODE0_ANYLEVEL;
-
-        for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
-                if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
-                        return i;
-
-        return -ENODEV;
-}
-
-static void at91_dt_shdwc(void)
-{
-        struct device_node *np;
-        int wakeup_mode;
-        u32 reg;
-        u32 mode = 0;
-
-        np = of_find_matching_node(NULL, shdwc_ids);
-        if (!np) {
-                pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
-                return;
+                idx++;
         }
 
-        at91_shdwc_base = of_iomap(np, 0);
-        if (!at91_shdwc_base)
-                panic("AT91: unable to map shdwc cpu registers\n");
-
-        wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
-        if (wakeup_mode < 0) {
-                pr_warn("AT91: shdwc unknown wakeup mode\n");
-                goto end;
-        }
+        if (!idx)
+                panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
 
-        if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
-                if (reg > AT91_SHDW_CPTWK0_MAX) {
-                        pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
-                                reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
-                        reg = AT91_SHDW_CPTWK0_MAX;
-                }
-                mode |= AT91_SHDW_CPTWK0_(reg);
+        if (!standby) {
+                pr_warn("ramc no standby function available\n");
+                return;
         }
 
-        if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
-                        mode |= AT91_SHDW_RTCWKEN;
-
-        if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
-                        mode |= AT91_SHDW_RTTWKEN;
-
-        at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
-
-end:
-        pm_power_off = at91sam9_poweroff;
-
-        of_node_put(np);
+        at91_pm_set_standby(standby);
 }
 
 void __init at91rm9200_dt_initialize(void)
@@ -503,9 +472,7 @@ void __init at91rm9200_dt_initialize(void)
 
 void __init at91_dt_initialize(void)
 {
-        at91_dt_rstc();
         at91_dt_ramc();
-        at91_dt_shdwc();
 
         /* Init clock subsystem */
         at91_dt_clock_init();
@@ -533,3 +500,13 @@ void __init at91_initialize(unsigned long main_clock)
 
         pinctrl_provide_dummies();
 }
+
+void __init at91_register_devices(void)
+{
+        at91_boot_soc.register_devices();
+}
+
+void __init at91_init_time(void)
+{
+        at91_boot_soc.init_time();
+}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index a1e1482c6da8..9a8fd97a8bef 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -11,7 +11,9 @@ struct at91_init_soc {
         void (*map_io)(void);
         void (*ioremap_registers)(void);
         void (*register_clocks)(void);
+        void (*register_devices)(void);
         void (*init)(void);
+        void (*init_time)(void);
 };
 
 extern struct at91_init_soc at91_boot_soc;
@@ -24,6 +26,7 @@ extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
 extern struct at91_init_soc at91sam9n12_soc;
 extern struct at91_init_soc sama5d3_soc;
+extern struct at91_init_soc sama5d4_soc;
 
 #define AT91_SOC_START(_name)                           \
 struct at91_init_soc __initdata _name##_soc             \
@@ -74,3 +77,7 @@ static inline int at91_soc_is_enabled(void)
 #if !defined(CONFIG_SOC_SAMA5D3)
 #define sama5d3_soc     at91_boot_soc
 #endif
+
+#if !defined(CONFIG_SOC_SAMA5D4)
+#define sama5d4_soc     at91_boot_soc
+#endif
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index fc938005ad39..2abad742516d 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -99,6 +99,23 @@ config ARCH_BCM_5301X
           different SoC or with the older BCM47XX and BCM53XX based
           network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 
+config ARCH_BCM_63XX
+        bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
+        depends on MMU
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_764369 if SMP
+        select ARM_GIC
+        select ARM_GLOBAL_TIMER
+        select CACHE_L2X0
+        select HAVE_ARM_ARCH_TIMER
+        select HAVE_ARM_TWD if SMP
+        select HAVE_ARM_SCU if SMP
+        select HAVE_SMP
+        help
+          This enables support for systems based on Broadcom DSL SoCs.
+          It currently supports the 'BCM63XX' ARM-based family, which includes
+          the BCM63138 variant.
+
 config ARCH_BRCMSTB
         bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
         depends on MMU
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 67c492aabf4d..300ae4b79ae6 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -34,7 +34,9 @@ obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
 # BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)    += bcm_5301x.o
 
+# BCM63XXx
+obj-$(CONFIG_ARCH_BCM_63XX)     := bcm63xx.o
+
 ifeq ($(CONFIG_ARCH_BRCMSTB),y)
 obj-y                           += brcmstb.o
-obj-$(CONFIG_SMP)               += headsmp-brcmstb.o platsmp-brcmstb.o
 endif
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/bcm63xx.c
index ec0c3d112b36..c4c66ae51308 100644
--- a/arch/arm/mach-bcm/brcmstb.h
+++ b/arch/arm/mach-bcm/bcm63xx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013-2014 Broadcom Corporation
+ * Copyright (C) 2014 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -11,9 +11,17 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __BRCMSTB_H__
-#define __BRCMSTB_H__
+#include <linux/of_platform.h>
 
-void brcmstb_secondary_startup(void);
+#include <asm/mach/arch.h>
 
-#endif /* __BRCMSTB_H__ */
+static const char * const bcm63xx_dt_compat[] = {
+        "brcm,bcm63138",
+        NULL
+};
+
+DT_MACHINE_START(BCM63XXX_DT, "BCM63xx DSL SoC")
+        .dt_compat      = bcm63xx_dt_compat,
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
deleted file mode 100644
index 199c1ea58248..000000000000
--- a/arch/arm/mach-bcm/headsmp-brcmstb.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * SMP boot code for secondary CPUs
- * Based on arch/arm/mach-tegra/headsmp.S
- *
- * Copyright (C) 2010 NVIDIA, Inc.
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <asm/assembler.h>
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-        .section ".text.head", "ax"
-
-ENTRY(brcmstb_secondary_startup)
-        /*
-         * Ensure CPU is in a sane state by disabling all IRQs and switching
-         * into SVC mode.
-         */
-        setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
-
-        bl      v7_invalidate_l1
-        b       secondary_startup
-ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
deleted file mode 100644
index af780e9c23a6..000000000000
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Broadcom STB CPU SMP and hotplug support for ARM
- *
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/printk.h>
-#include <linux/regmap.h>
-#include <linux/smp.h>
-#include <linux/mfd/syscon.h>
-#include <linux/spinlock.h>
-
-#include <asm/cacheflush.h>
-#include <asm/cp15.h>
-#include <asm/mach-types.h>
-#include <asm/smp_plat.h>
-
-#include "brcmstb.h"
-
-enum {
-        ZONE_MAN_CLKEN_MASK             = BIT(0),
-        ZONE_MAN_RESET_CNTL_MASK        = BIT(1),
-        ZONE_MAN_MEM_PWR_MASK           = BIT(4),
-        ZONE_RESERVED_1_MASK            = BIT(5),
-        ZONE_MAN_ISO_CNTL_MASK          = BIT(6),
-        ZONE_MANUAL_CONTROL_MASK        = BIT(7),
-        ZONE_PWR_DN_REQ_MASK            = BIT(9),
-        ZONE_PWR_UP_REQ_MASK            = BIT(10),
-        ZONE_BLK_RST_ASSERT_MASK        = BIT(12),
-        ZONE_PWR_OFF_STATE_MASK         = BIT(25),
-        ZONE_PWR_ON_STATE_MASK          = BIT(26),
-        ZONE_DPG_PWR_STATE_MASK         = BIT(28),
-        ZONE_MEM_PWR_STATE_MASK         = BIT(29),
-        ZONE_RESET_STATE_MASK           = BIT(31),
-        CPU0_PWR_ZONE_CTRL_REG          = 1,
-        CPU_RESET_CONFIG_REG            = 2,
-};
-
-static void __iomem *cpubiuctrl_block;
-static void __iomem *hif_cont_block;
-static u32 cpu0_pwr_zone_ctrl_reg;
-static u32 cpu_rst_cfg_reg;
-static u32 hif_cont_reg;
-
-#ifdef CONFIG_HOTPLUG_CPU
-static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
-
-static int per_cpu_sw_state_rd(u32 cpu)
-{
-        sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
-        return per_cpu(per_cpu_sw_state, cpu);
-}
-
-static void per_cpu_sw_state_wr(u32 cpu, int val)
-{
-        per_cpu(per_cpu_sw_state, cpu) = val;
-        dmb();
-        sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
-        dsb_sev();
-}
-#else
-static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
-#endif
-
-static void __iomem *pwr_ctrl_get_base(u32 cpu)
-{
-        void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
-        base += (cpu_logical_map(cpu) * 4);
-        return base;
-}
-
-static u32 pwr_ctrl_rd(u32 cpu)
-{
-        void __iomem *base = pwr_ctrl_get_base(cpu);
-        return readl_relaxed(base);
-}
-
-static void pwr_ctrl_wr(u32 cpu, u32 val)
-{
-        void __iomem *base = pwr_ctrl_get_base(cpu);
-        writel(val, base);
-}
-
-static void cpu_rst_cfg_set(u32 cpu, int set)
-{
-        u32 val;
-        val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
-        if (set)
-                val |= BIT(cpu_logical_map(cpu));
-        else
-                val &= ~BIT(cpu_logical_map(cpu));
-        writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
-}
-
-static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
-{
-        const int reg_ofs = cpu_logical_map(cpu) * 8;
-        writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
-        writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
-}
-
-static void brcmstb_cpu_boot(u32 cpu)
-{
-        pr_info("SMP: Booting CPU%d...\n", cpu);
-
-        /*
-         * set the reset vector to point to the secondary_startup
-         * routine
-         */
-        cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
-
-        /* unhalt the cpu */
-        cpu_rst_cfg_set(cpu, 0);
-}
-
-static void brcmstb_cpu_power_on(u32 cpu)
-{
-        /*
-         * The secondary cores power was cut, so we must go through
-         * power-on initialization.
-         */
-        u32 tmp;
-
-        pr_info("SMP: Powering up CPU%d...\n", cpu);
-
-        /* Request zone power up */
-        pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
-
-        /* Wait for the power up FSM to complete */
-        do {
-                tmp = pwr_ctrl_rd(cpu);
-        } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
-
-        per_cpu_sw_state_wr(cpu, 1);
-}
-
-static int brcmstb_cpu_get_power_state(u32 cpu)
-{
-        int tmp = pwr_ctrl_rd(cpu);
-        return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-static void brcmstb_cpu_die(u32 cpu)
-{
-        v7_exit_coherency_flush(all);
-
-        /* Prevent all interrupts from reaching this CPU. */
-        arch_local_irq_disable();
-
-        /*
-         * Final full barrier to ensure everything before this instruction has
-         * quiesced.
-         */
-        isb();
-        dsb();
-
-        per_cpu_sw_state_wr(cpu, 0);
-
-        /* Sit and wait to die */
-        wfi();
-
-        /* We should never get here... */
-        panic("Spurious interrupt on CPU %d received!\n", cpu);
-}
-
-static int brcmstb_cpu_kill(u32 cpu)
-{
-        u32 tmp;
-
-        pr_info("SMP: Powering down CPU%d...\n", cpu);
-
-        while (per_cpu_sw_state_rd(cpu))
-                ;
-
-        /* Program zone reset */
-        pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
-                              ZONE_PWR_DN_REQ_MASK);
-
-        /* Verify zone reset */
-        tmp = pwr_ctrl_rd(cpu);
-        if (!(tmp & ZONE_RESET_STATE_MASK))
-                pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
-                        __func__, cpu);
-
-        /* Wait for power down */
-        do {
-                tmp = pwr_ctrl_rd(cpu);
-        } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
-
-        /* Settle-time from Broadcom-internal DVT reference code */
-        udelay(7);
-
-        /* Assert reset on the CPU */
-        cpu_rst_cfg_set(cpu, 1);
-
-        return 1;
-}
-
-#endif /* CONFIG_HOTPLUG_CPU */
-
-static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
-{
-        int rc = 0;
-        char *name;
-        struct device_node *syscon_np = NULL;
-
-        name = "syscon-cpu";
-
-        syscon_np = of_parse_phandle(np, name, 0);
-        if (!syscon_np) {
-                pr_err("can't find phandle %s\n", name);
-                rc = -EINVAL;
-                goto cleanup;
-        }
-
-        cpubiuctrl_block = of_iomap(syscon_np, 0);
-        if (!cpubiuctrl_block) {
-                pr_err("iomap failed for cpubiuctrl_block\n");
-                rc = -EINVAL;
-                goto cleanup;
-        }
-
-        rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
-                                        &cpu0_pwr_zone_ctrl_reg);
-        if (rc) {
-                pr_err("failed to read 1st entry from %s property (%d)\n", name,
-                        rc);
-                rc = -EINVAL;
-                goto cleanup;
-        }
-
-        rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
-                                        &cpu_rst_cfg_reg);
-        if (rc) {
-                pr_err("failed to read 2nd entry from %s property (%d)\n", name,
-                        rc);
-                rc = -EINVAL;
-                goto cleanup;
-        }
-
-cleanup:
-        if (syscon_np)
-                of_node_put(syscon_np);
-
-        return rc;
-}
-
-static int __init setup_hifcont_regs(struct device_node *np)
-{
-        int rc = 0;
-        char *name;
-        struct device_node *syscon_np = NULL;
-
-        name = "syscon-cont";
-
-        syscon_np = of_parse_phandle(np, name, 0);
-        if (!syscon_np) {
-                pr_err("can't find phandle %s\n", name);
-                rc = -EINVAL;
-                goto cleanup;
-        }
-
-        hif_cont_block = of_iomap(syscon_np, 0);
-        if (!hif_cont_block) {
-                pr_err("iomap failed for hif_cont_block\n");
-                rc = -EINVAL;
-                goto cleanup;
-        }
-
-        /* offset is at top of hif_cont_block */
-        hif_cont_reg = 0;
-
-cleanup:
-        if (syscon_np)
-                of_node_put(syscon_np);
-
-        return rc;
-}
-
-static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
-{
-        int rc;
-        struct device_node *np;
-        char *name;
-
-        name = "brcm,brcmstb-smpboot";
-        np = of_find_compatible_node(NULL, NULL, name);
-        if (!np) {
-                pr_err("can't find compatible node %s\n", name);
-                return;
-        }
-
-        rc = setup_hifcpubiuctrl_regs(np);
-        if (rc)
-                return;
-
-        rc = setup_hifcont_regs(np);
-        if (rc)
-                return;
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
-static void brcmstb_secondary_init(unsigned int cpu)
-{
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
-}
-
-static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
-
-        /* Bring up power to the core if necessary */
-        if (brcmstb_cpu_get_power_state(cpu) == 0)
-                brcmstb_cpu_power_on(cpu);
-
-        brcmstb_cpu_boot(cpu);
-
-        /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
-         */
-        spin_unlock(&boot_lock);
-
-        return 0;
-}
-
-static struct smp_operations brcmstb_smp_ops __initdata = {
-        .smp_prepare_cpus       = brcmstb_cpu_ctrl_setup,
-        .smp_secondary_init     = brcmstb_secondary_init,
-        .smp_boot_secondary     = brcmstb_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_kill               = brcmstb_cpu_kill,
-        .cpu_die                = brcmstb_cpu_die,
-#endif
-};
-
-CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index fdf54d40909a..f33979784f38 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -14,8 +14,9 @@
 #include <linux/types.h>
 #include <linux/i2c-gpio.h>
 #include <linux/interrupt.h>
-#include <linux/backlight.h>
 #include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/pwm_backlight.h>
 #include <linux/memblock.h>
 
 #include <linux/mtd/physmap.h>
@@ -108,23 +109,23 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
         .set_power      = edb7211_lcd_power_set,
 };
 
-static void edb7211_lcd_backlight_set_intensity(int intensity)
-{
-        gpio_set_value(EDB7211_LCDBL, !!intensity);
-        clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON);
-}
+static struct pwm_lookup edb7211_pwm_lookup[] = {
+        PWM_LOOKUP("clps711x-pwm", 0, "pwm-backlight.0", NULL,
+                   0, PWM_POLARITY_NORMAL),
+};
 
-static struct generic_bl_info edb7211_lcd_backlight_pdata = {
-        .name                   = "lcd-backlight.0",
-        .default_intensity      = 0x01,
-        .max_intensity          = 0x0f,
-        .set_bl_intensity       = edb7211_lcd_backlight_set_intensity,
+static struct platform_pwm_backlight_data pwm_bl_pdata = {
+        .dft_brightness = 0x01,
+        .max_brightness = 0x0f,
+        .enable_gpio    = EDB7211_LCDBL,
 };
 
+static struct resource clps711x_pwm_res =
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + PMPCON, SZ_4);
+
 static struct gpio edb7211_gpios[] __initconst = {
         { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW,     "LCD DC-DC" },
         { EDB7211_LCDEN,        GPIOF_OUT_INIT_LOW,     "LCD POWER" },
-        { EDB7211_LCDBL,        GPIOF_OUT_INIT_LOW,     "LCD BACKLIGHT" },
 };
 
 /* Reserve screen memory region at the start of main system memory. */
@@ -153,12 +154,18 @@ static void __init edb7211_init_late(void)
         gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
 
         platform_device_register(&edb7211_flash_pdev);
+
         platform_device_register_data(NULL, "platform-lcd", 0,
                                       &edb7211_lcd_power_pdata,
                                       sizeof(edb7211_lcd_power_pdata));
-        platform_device_register_data(NULL, "generic-bl", 0,
-                                      &edb7211_lcd_backlight_pdata,
-                                      sizeof(edb7211_lcd_backlight_pdata));
+
+        platform_device_register_simple("clps711x-pwm", PLATFORM_DEVID_NONE,
+                                        &clps711x_pwm_res, 1);
+        pwm_add_table(edb7211_pwm_lookup, ARRAY_SIZE(edb7211_pwm_lookup));
+
+        platform_device_register_data(&platform_bus, "pwm-backlight", 0,
+                                      &pwm_bl_pdata, sizeof(pwm_bl_pdata));
+
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
         platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
                                         ARRAY_SIZE(edb7211_cs8900_resource));
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 2a6323b15782..671acc5a3282 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -19,29 +19,17 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <linux/io.h>
+
 #include <linux/init.h>
 #include <linux/sizes.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/clk-provider.h>
-#include <linux/sched_clock.h>
 
 #include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
 #include <mach/hardware.h>
 
 #include "common.h"
 
-static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
-                  *clk_tint, *clk_spi;
-
 /*
  * This maps the generic CLPS711x registers
  */
@@ -64,129 +52,11 @@ void __init clps711x_init_irq(void)
         clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
 }
 
-static u64 notrace clps711x_sched_clock_read(void)
-{
-        return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
-}
-
-static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
-                                         struct clock_event_device *evt)
-{
-        disable_irq(IRQ_TC2OI);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                enable_irq(IRQ_TC2OI);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* Not supported */
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_RESUME:
-                /* Left event sources disabled, no more interrupts appear */
-                break;
-        }
-}
-
-static struct clock_event_device clockevent_clps711x = {
-        .name           = "clps711x-clockevent",
-        .rating         = 300,
-        .features       = CLOCK_EVT_FEAT_PERIODIC,
-        .set_mode       = clps711x_clockevent_set_mode,
-};
-
-static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
-{
-        clockevent_clps711x.event_handler(&clockevent_clps711x);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction clps711x_timer_irq = {
-        .name           = "clps711x-timer",
-        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = clps711x_timer_interrupt,
-};
-
-static void add_fixed_clk(struct clk *clk, const char *name, int rate)
-{
-        clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
-        clk_register_clkdev(clk, name, NULL);
-}
-
 void __init clps711x_timer_init(void)
 {
-        int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
-        u32 tmp;
-
-        osc = 3686400;
-        ext = 13000000;
-
-        tmp = clps_readl(PLLR) >> 24;
-        if (tmp)
-                pll = (osc * tmp) / 2;
-        else
-                pll = 73728000; /* Default value */
-
-        tmp = clps_readl(SYSFLG2);
-        if (tmp & SYSFLG2_CKMODE) {
-                cpu = ext;
-                bus = cpu;
-                spi = 135400;
-                pll = 0;
-        } else {
-                cpu = pll;
-                if (cpu >= 36864000)
-                        bus = cpu / 2;
-                else
-                        bus = 36864000 / 2;
-                spi = cpu / 576;
-        }
-
-        uart = bus / 10;
-
-        if (tmp & SYSFLG2_CKMODE) {
-                tmp = clps_readl(SYSCON2);
-                if (tmp & SYSCON2_OSTB)
-                        timh = ext / 26;
-                else
-                        timh = 541440;
-        } else
-                timh = DIV_ROUND_CLOSEST(cpu, 144);
-
-        timl = DIV_ROUND_CLOSEST(timh, 256);
-
-        /* All clocks are fixed */
-        add_fixed_clk(clk_pll, "pll", pll);
-        add_fixed_clk(clk_bus, "bus", bus);
-        add_fixed_clk(clk_uart, "uart", uart);
-        add_fixed_clk(clk_timerl, "timer_lf", timl);
-        add_fixed_clk(clk_timerh, "timer_hf", timh);
-        add_fixed_clk(clk_tint, "tint", 64);
-        add_fixed_clk(clk_spi, "spi", spi);
-
-        pr_info("CPU frequency set at %i Hz.\n", cpu);
-
-        /* Start Timer1 in free running mode (Low frequency) */
-        tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
-        clps_writel(tmp, SYSCON1);
-
-        sched_clock_register(clps711x_sched_clock_read, 16, timl);
-
-        clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
-                              "clps711x_clocksource", timl, 300, 16,
-                              clocksource_mmio_readw_down);
-
-        /* Set Timer2 prescaler */
-        clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
-
-        /* Start Timer2 in prescale mode (High frequency)*/
-        tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
-        clps_writel(tmp, SYSCON1);
-
-        clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
-
-        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
+        clps711x_clk_init(CLPS711X_VIRT_BASE);
+        clps711x_clksrc_init(CLPS711X_VIRT_BASE + TC1D,
+                             CLPS711X_VIRT_BASE + TC2D, IRQ_TC2OI);
 }
 
 void clps711x_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f88189963898..370200b26333 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -16,3 +16,8 @@ extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
 
 /* drivers/irqchip/irq-clps711x.c */
 void clps711x_intc_init(phys_addr_t, resource_size_t);
+/* drivers/clk/clk-clps711x.c */
+void clps711x_clk_init(void __iomem *base);
+/* drivers/clocksource/clps711x-timer.c */
+void clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
+                          unsigned int irq);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index 0c689d3a6710..77a9617c216d 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -1,7 +1,7 @@
 /*
  *  CLPS711X common devices definitions
  *
- *  Author: Alexander Shiyan <shc_work@mail.ru>, 2013
+ *  Author: Alexander Shiyan <shc_work@mail.ru>, 2013-2014
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,8 +9,15 @@
  * (at your option) any later version.
  */
 
+#include <linux/io.h>
+#include <linux/of_fdt.h>
 #include <linux/platform_device.h>
+#include <linux/random.h>
 #include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
+
+#include <asm/system_info.h>
 
 #include <mach/hardware.h>
 
@@ -90,10 +97,53 @@ static void __init clps711x_add_uart(void)
                                         ARRAY_SIZE(clps711x_uart2_res));
 };
 
+static void __init clps711x_soc_init(void)
+{
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        void __iomem *base;
+        u32 id[5];
+
+        base = ioremap(CLPS711X_PHYS_BASE, SZ_32K);
+        if (!base)
+                return;
+
+        id[0] = readl(base + UNIQID);
+        id[1] = readl(base + RANDID0);
+        id[2] = readl(base + RANDID1);
+        id[3] = readl(base + RANDID2);
+        id[4] = readl(base + RANDID3);
+        system_rev = SYSFLG1_VERID(readl(base + SYSFLG1));
+
+        add_device_randomness(id, sizeof(id));
+
+        system_serial_low = id[0];
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                goto out_unmap;
+
+        soc_dev_attr->machine = of_flat_dt_get_machine_name();
+        soc_dev_attr->family = "Cirrus Logic CLPS711X";
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", system_rev);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%08x", id[0]);
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+        }
+
+out_unmap:
+        iounmap(base);
+}
+
 void __init clps711x_devices_init(void)
 {
         clps711x_add_cpuidle();
         clps711x_add_gpio();
         clps711x_add_syscon();
         clps711x_add_uart();
+        clps711x_soc_init();
 }
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index d863d8729edc..6428bcc77e87 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -250,5 +250,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
         .init_irq       = cns3xxx_init_irq,
         .init_time      = cns3xxx_timer_init,
         .init_machine   = cns3420_init,
+        .init_late      = cns3xxx_pcie_init_late,
         .restart        = cns3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index f85449a6accd..4e9837ded96d 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -404,5 +404,6 @@ DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
         .init_irq       = cns3xxx_init_irq,
         .init_time      = cns3xxx_timer_init,
         .init_machine   = cns3xxx_init,
+        .init_late      = cns3xxx_pcie_init_late,
         .restart        = cns3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index 5218b6198dc2..dc5df7f1e39f 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -21,6 +21,12 @@ void __init cns3xxx_l2x0_init(void);
 static inline void cns3xxx_l2x0_init(void) {}
 #endif /* CONFIG_CACHE_L2X0 */
 
+#ifdef CONFIG_PCI
+extern void __init cns3xxx_pcie_init_late(void);
+#else
+static inline void __init cns3xxx_pcie_init_late(void) {}
+#endif
+
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 413134c54452..45d6bd09e6ef 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -60,11 +60,10 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
         struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
         int busno = bus->number;
         int slot = PCI_SLOT(devfn);
-        int offset;
         void __iomem *base;
 
         /* If there is no link, just show the CNS PCI bridge. */
-        if (!cnspci->linked && (busno > 0 || slot > 0))
+        if (!cnspci->linked && busno > 0)
                 return NULL;
 
         /*
@@ -72,22 +71,21 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
          * we still want to access it. For this to work, we must place
          * the first device on the same bus as the CNS PCI bridge.
          */
-        if (busno == 0) { /* directly connected PCIe bus */
-                switch (slot) {
-                case 0: /* host bridge device, function 0 only */
+        if (busno == 0) { /* internal PCIe bus, host bridge device */
+                if (devfn == 0) /* device# and function# are ignored by hw */
                         base = cnspci->host_regs;
-                        break;
-                case 1: /* directly connected device */
+                else
+                        return NULL; /* no such device */
+
+        } else if (busno == 1) { /* directly connected PCIe device */
+                if (slot == 0) /* device# is ignored by hw */
                         base = cnspci->cfg0_regs;
-                        break;
-                default:
+                else
                         return NULL; /* no such device */
-                }
         } else /* remote PCI bus */
-                base = cnspci->cfg1_regs;
+                base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
 
-        offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
-        return base + offset;
+        return base + (where & 0xffc) + (devfn << 12);
 }
 
 static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
@@ -167,7 +165,7 @@ static struct pci_ops cns3xxx_pcie_ops = {
 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
         struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
-        int irq = cnspci->irqs[slot];
+        int irq = cnspci->irqs[!!dev->bus->number];
 
         pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
                 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
@@ -297,15 +295,19 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
                 return;
 
         /* Set Device Max_Read_Request_Size to 128 byte */
-        devfn = PCI_DEVFN(1, 0);
+        bus.number = 1; /* directly connected PCIe device */
+        devfn = PCI_DEVFN(0, 0);
         pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
         pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
-        dc &= ~(0x3 << 12);     /* Clear Device Control Register [14:12] */
-        pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
-        pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
-        if (!(dc & (0x3 << 12)))
-                pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
-
+        if (dc & PCI_EXP_DEVCTL_READRQ) {
+                dc &= ~PCI_EXP_DEVCTL_READRQ;
+                pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
+                pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+                if (dc & PCI_EXP_DEVCTL_READRQ)
+                        pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
+                else
+                        pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
+        }
         /* Disable PCIe0 Interrupt Mask INTA to INTD */
         __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
 }
@@ -318,7 +320,7 @@ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
         return 0;
 }
 
-static int __init cns3xxx_pcie_init(void)
+void __init cns3xxx_pcie_init_late(void)
 {
         int i;
 
@@ -337,7 +339,4 @@ static int __init cns3xxx_pcie_init(void)
         }
 
         pci_assign_unassigned_resources();
-
-        return 0;
 }
-device_initcall(cns3xxx_pcie_init);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 234c5bb091f5..fa11415e906a 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -35,6 +35,7 @@
 #include <linux/platform_data/uio_pruss.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/tps6507x.h>
+#include <linux/regulator/fixed.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/wl12xx.h>
@@ -842,6 +843,16 @@ static int da850_lcd_hw_init(void)
         return 0;
 }
 
+/* Fixed regulator support */
+static struct regulator_consumer_supply fixed_supplies[] = {
+        /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */
+        REGULATOR_SUPPLY("AVDD", "1-0018"),
+        REGULATOR_SUPPLY("DRVDD", "1-0018"),
+
+        /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
+        REGULATOR_SUPPLY("DVDD", "1-0018"),
+};
+
 /* TPS65070 voltage regulator support */
 
 /* 3.3V */
@@ -865,6 +876,7 @@ static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
         {
                 .supply = "dvdd3318_c",
         },
+        REGULATOR_SUPPLY("IOVDD", "1-0018"),
 };
 
 /* 1.2V */
@@ -936,6 +948,7 @@ static struct regulator_init_data tps65070_regulator_data[] = {
                         .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
                                 REGULATOR_CHANGE_STATUS),
                         .boot_on = 1,
+                        .always_on = 1,
                 },
                 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
                 .consumer_supplies = tps65070_dcdc2_consumers,
@@ -1446,6 +1459,8 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
 
+        regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies));
+
         ret = pmic_tps65070_init();
         if (ret)
                 pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index ed1928740b5f..f703d82f08a8 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -46,6 +46,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL),
         OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1",
                        NULL),
+        OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
         {}
 };
 
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6a24e111d6e1..b89e5f35db84 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -193,7 +193,6 @@ static void __init exynos_init_late(void)
                 /* to be supported later */
                 return;
 
-        pm_genpd_poweroff_unused();
         exynos_pm_init();
 }
 
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
deleted file mode 100644
index e19df1f18c0d..000000000000
--- a/arch/arm/mach-exynos/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Memory definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H __FILE__
-
-#define PLAT_PHYS_OFFSET                UL(0x40000000)
-
-#ifndef CONFIG_ARM_LPAE
-/* Maximum of 256MiB in one bank */
-#define MAX_PHYSMEM_BITS        32
-#define SECTION_SIZE_BITS       28
-#else
-#define MAX_PHYSMEM_BITS        36
-#define SECTION_SIZE_BITS       31
-#endif
-
-#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index b2f8b60cf0e9..dc9a764a7c37 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -43,7 +43,6 @@
         "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
         "isb\n\t"\
         "bl     v7_flush_dcache_"__stringify(level)"\n\t" \
-        "clrex\n\t"\
         "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
         "bic    r0, r0, #(1 << 6)       @ disable local coherency\n\t" \
         /* Dummy Load of a device register to avoid Erratum 799270 */ \
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a9f1cf759949..41ae28d69e6f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -224,7 +224,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                                 ret = PTR_ERR(boot_reg);
                                 goto fail;
                         }
-                        __raw_writel(boot_addr, cpu_boot_reg(core_id));
+                        __raw_writel(boot_addr, boot_reg);
                 }
 
                 call_firmware_op(cpu_boot, core_id);
@@ -313,7 +313,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 
                         if (IS_ERR(boot_reg))
                                 break;
-                        __raw_writel(boot_addr, cpu_boot_reg(core_id));
+                        __raw_writel(boot_addr, boot_reg);
                 }
         }
 }
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index fd76e1b5a471..20f267121b3e 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -105,78 +105,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
         return exynos_pd_power(domain, false);
 }
 
-static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
-                                         struct device *dev)
-{
-        int ret;
-
-        dev_dbg(dev, "adding to power domain %s\n", pd->pd.name);
-
-        while (1) {
-                ret = pm_genpd_add_device(&pd->pd, dev);
-                if (ret != -EAGAIN)
-                        break;
-                cond_resched();
-        }
-
-        pm_genpd_dev_need_restore(dev, true);
-}
-
-static void exynos_remove_device_from_domain(struct device *dev)
-{
-        struct generic_pm_domain *genpd = dev_to_genpd(dev);
-        int ret;
-
-        dev_dbg(dev, "removing from power domain %s\n", genpd->name);
-
-        while (1) {
-                ret = pm_genpd_remove_device(genpd, dev);
-                if (ret != -EAGAIN)
-                        break;
-                cond_resched();
-        }
-}
-
-static void exynos_read_domain_from_dt(struct device *dev)
-{
-        struct platform_device *pd_pdev;
-        struct exynos_pm_domain *pd;
-        struct device_node *node;
-
-        node = of_parse_phandle(dev->of_node, "samsung,power-domain", 0);
-        if (!node)
-                return;
-        pd_pdev = of_find_device_by_node(node);
-        if (!pd_pdev)
-                return;
-        pd = platform_get_drvdata(pd_pdev);
-        exynos_add_device_to_domain(pd, dev);
-}
-
-static int exynos_pm_notifier_call(struct notifier_block *nb,
-                                    unsigned long event, void *data)
-{
-        struct device *dev = data;
-
-        switch (event) {
-        case BUS_NOTIFY_BIND_DRIVER:
-                if (dev->of_node)
-                        exynos_read_domain_from_dt(dev);
-
-                break;
-
-        case BUS_NOTIFY_UNBOUND_DRIVER:
-                exynos_remove_device_from_domain(dev);
-
-                break;
-        }
-        return NOTIFY_DONE;
-}
-
-static struct notifier_block platform_nb = {
-        .notifier_call = exynos_pm_notifier_call,
-};
-
 static __init int exynos4_pm_init_power_domain(void)
 {
         struct platform_device *pdev;
@@ -202,7 +130,6 @@ static __init int exynos4_pm_init_power_domain(void)
                 pd->base = of_iomap(np, 0);
                 pd->pd.power_off = exynos_pd_power_off;
                 pd->pd.power_on = exynos_pd_power_on;
-                pd->pd.of_node = np;
 
                 pd->oscclk = clk_get(dev, "oscclk");
                 if (IS_ERR(pd->oscclk))
@@ -228,15 +155,12 @@ static __init int exynos4_pm_init_power_domain(void)
                         clk_put(pd->oscclk);
 
 no_clk:
-                platform_set_drvdata(pdev, pd);
-
                 on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
 
                 pm_genpd_init(&pd->pd, NULL, !on);
+                of_genpd_add_provider_simple(np, &pd->pd);
         }
 
-        bus_register_notifier(&platform_bus_type, &platform_nb);
-
         return 0;
 }
 arch_initcall(exynos4_pm_init_power_domain);
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 984882943f77..cd19433f76d3 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,6 +1,6 @@
 config ARCH_HISI
         bool "Hisilicon SoC Support"
-        depends on ARCH_MULTIPLATFORM
+        depends on ARCH_MULTI_V7
         select ARM_AMBA
         select ARM_GIC
         select ARM_TIMER_SP804
@@ -22,6 +22,15 @@ config ARCH_HI3xxx
         help
           Support for Hisilicon Hi36xx SoC family
 
+config ARCH_HIP04
+        bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7
+        select ARM_ERRATA_798181 if SMP
+        select HAVE_ARM_ARCH_TIMER
+        select MCPM if SMP
+        select MCPM_QUAD_CLUSTER if SMP
+        help
+          Support for Hisilicon HiP04 SoC family
+
 config ARCH_HIX5HD2
         bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
         select CACHE_L2X0
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index ee2506b9cde3..6b7b3033de0b 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -2,5 +2,8 @@
 # Makefile for Hisilicon processors family
 #
 
+CFLAGS_platmcpm.o       := -march=armv7-a
+
 obj-y   += hisilicon.o
+obj-$(CONFIG_MCPM)              += platmcpm.o
 obj-$(CONFIG_SMP)               += platsmp.o hotplug.o headsmp.o
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 7cda6dda3cd0..7744c351bbfd 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -63,3 +63,12 @@ static const char *hix5hd2_compat[] __initconst = {
 DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
         .dt_compat      = hix5hd2_compat,
 MACHINE_END
+
+static const char *hip04_compat[] __initconst = {
+        "hisilicon,hip04-d01",
+        NULL,
+};
+
+DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
+        .dt_compat      = hip04_compat,
+MACHINE_END
diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
new file mode 100644
index 000000000000..280f3f14f77c
--- /dev/null
+++ b/arch/arm/mach-hisi/platmcpm.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/memblock.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "core.h"
+
+/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
+ * 1 -- unreset; 0 -- reset
+ */
+#define CORE_RESET_BIT(x)               (1 << x)
+#define NEON_RESET_BIT(x)               (1 << (x + 4))
+#define CORE_DEBUG_RESET_BIT(x)         (1 << (x + 9))
+#define CLUSTER_L2_RESET_BIT            (1 << 8)
+#define CLUSTER_DEBUG_RESET_BIT         (1 << 13)
+
+/*
+ * bits definition in SC_CPU_RESET_STATUS[x]
+ * 1 -- reset status; 0 -- unreset status
+ */
+#define CORE_RESET_STATUS(x)            (1 << x)
+#define NEON_RESET_STATUS(x)            (1 << (x + 4))
+#define CORE_DEBUG_RESET_STATUS(x)      (1 << (x + 9))
+#define CLUSTER_L2_RESET_STATUS         (1 << 8)
+#define CLUSTER_DEBUG_RESET_STATUS      (1 << 13)
+#define CORE_WFI_STATUS(x)              (1 << (x + 16))
+#define CORE_WFE_STATUS(x)              (1 << (x + 20))
+#define CORE_DEBUG_ACK(x)               (1 << (x + 24))
+
+#define SC_CPU_RESET_REQ(x)             (0x520 + (x << 3))      /* reset */
+#define SC_CPU_RESET_DREQ(x)            (0x524 + (x << 3))      /* unreset */
+#define SC_CPU_RESET_STATUS(x)          (0x1520 + (x << 3))
+
+#define FAB_SF_MODE                     0x0c
+#define FAB_SF_INVLD                    0x10
+
+/* bits definition in FB_SF_INVLD */
+#define FB_SF_INVLD_START               (1 << 8)
+
+#define HIP04_MAX_CLUSTERS              4
+#define HIP04_MAX_CPUS_PER_CLUSTER      4
+
+#define POLL_MSEC       10
+#define TIMEOUT_MSEC    1000
+
+static void __iomem *sysctrl, *fabric;
+static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
+static DEFINE_SPINLOCK(boot_lock);
+static u32 fabric_phys_addr;
+/*
+ * [0]: bootwrapper physical address
+ * [1]: bootwrapper size
+ * [2]: relocation address
+ * [3]: relocation size
+ */
+static u32 hip04_boot_method[4];
+
+static bool hip04_cluster_is_down(unsigned int cluster)
+{
+        int i;
+
+        for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
+                if (hip04_cpu_table[cluster][i])
+                        return false;
+        return true;
+}
+
+static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
+{
+        unsigned long data;
+
+        if (!fabric)
+                BUG();
+        data = readl_relaxed(fabric + FAB_SF_MODE);
+        if (on)
+                data |= 1 << cluster;
+        else
+                data &= ~(1 << cluster);
+        writel_relaxed(data, fabric + FAB_SF_MODE);
+        do {
+                cpu_relax();
+        } while (data != readl_relaxed(fabric + FAB_SF_MODE));
+}
+
+static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
+{
+        unsigned long data;
+        void __iomem *sys_dreq, *sys_status;
+
+        if (!sysctrl)
+                return -ENODEV;
+        if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
+                return -EINVAL;
+
+        spin_lock_irq(&boot_lock);
+
+        if (hip04_cpu_table[cluster][cpu])
+                goto out;
+
+        sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster);
+        sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster);
+        if (hip04_cluster_is_down(cluster)) {
+                data = CLUSTER_DEBUG_RESET_BIT;
+                writel_relaxed(data, sys_dreq);
+                do {
+                        cpu_relax();
+                        data = readl_relaxed(sys_status);
+                } while (data & CLUSTER_DEBUG_RESET_STATUS);
+        }
+
+        data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+               CORE_DEBUG_RESET_BIT(cpu);
+        writel_relaxed(data, sys_dreq);
+        do {
+                cpu_relax();
+        } while (data == readl_relaxed(sys_status));
+        /*
+         * We may fail to power up core again without this delay.
+         * It's not mentioned in document. It's found by test.
+         */
+        udelay(20);
+out:
+        hip04_cpu_table[cluster][cpu]++;
+        spin_unlock_irq(&boot_lock);
+
+        return 0;
+}
+
+static void hip04_mcpm_power_down(void)
+{
+        unsigned int mpidr, cpu, cluster;
+        bool skip_wfi = false, last_man = false;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        __mcpm_cpu_going_down(cpu, cluster);
+
+        spin_lock(&boot_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        hip04_cpu_table[cluster][cpu]--;
+        if (hip04_cpu_table[cluster][cpu] == 1) {
+                /* A power_up request went ahead of us. */
+                skip_wfi = true;
+        } else if (hip04_cpu_table[cluster][cpu] > 1) {
+                pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
+                BUG();
+        }
+
+        last_man = hip04_cluster_is_down(cluster);
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                spin_unlock(&boot_lock);
+                /* Since it's Cortex A15, disable L2 prefetching. */
+                asm volatile(
+                "mcr    p15, 1, %0, c15, c0, 3 \n\t"
+                "isb    \n\t"
+                "dsb    "
+                : : "r" (0x400) );
+                v7_exit_coherency_flush(all);
+                hip04_set_snoop_filter(cluster, 0);
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                spin_unlock(&boot_lock);
+                v7_exit_coherency_flush(louis);
+        }
+
+        __mcpm_cpu_down(cpu, cluster);
+
+        if (!skip_wfi)
+                wfi();
+}
+
+static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
+{
+        unsigned int data, tries, count;
+        int ret = -ETIMEDOUT;
+
+        BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
+               cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
+
+        count = TIMEOUT_MSEC / POLL_MSEC;
+        spin_lock_irq(&boot_lock);
+        for (tries = 0; tries < count; tries++) {
+                if (hip04_cpu_table[cluster][cpu]) {
+                        ret = -EBUSY;
+                        goto err;
+                }
+                cpu_relax();
+                data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
+                if (data & CORE_WFI_STATUS(cpu))
+                        break;
+                spin_unlock_irq(&boot_lock);
+                /* Wait for clean L2 when the whole cluster is down. */
+                msleep(POLL_MSEC);
+                spin_lock_irq(&boot_lock);
+        }
+        if (tries >= count)
+                goto err;
+        data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+               CORE_DEBUG_RESET_BIT(cpu);
+        writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
+        for (tries = 0; tries < count; tries++) {
+                cpu_relax();
+                data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
+                if (data & CORE_RESET_STATUS(cpu))
+                        break;
+        }
+        if (tries >= count)
+                goto err;
+        spin_unlock_irq(&boot_lock);
+        return 0;
+err:
+        spin_unlock_irq(&boot_lock);
+        return ret;
+}
+
+static void hip04_mcpm_powered_up(void)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        spin_lock(&boot_lock);
+        if (!hip04_cpu_table[cluster][cpu])
+                hip04_cpu_table[cluster][cpu] = 1;
+        spin_unlock(&boot_lock);
+}
+
+static void __naked hip04_mcpm_power_up_setup(unsigned int affinity_level)
+{
+        asm volatile ("                 \n"
+"       cmp     r0, #0                  \n"
+"       bxeq    lr                      \n"
+        /* calculate fabric phys address */
+"       adr     r2, 2f                  \n"
+"       ldmia   r2, {r1, r3}            \n"
+"       sub     r0, r2, r1              \n"
+"       ldr     r2, [r0, r3]            \n"
+        /* get cluster id from MPIDR */
+"       mrc     p15, 0, r0, c0, c0, 5   \n"
+"       ubfx    r1, r0, #8, #8          \n"
+        /* 1 << cluster id */
+"       mov     r0, #1                  \n"
+"       mov     r3, r0, lsl r1          \n"
+"       ldr     r0, [r2, #"__stringify(FAB_SF_MODE)"]   \n"
+"       tst     r0, r3                  \n"
+"       bxne    lr                      \n"
+"       orr     r1, r0, r3              \n"
+"       str     r1, [r2, #"__stringify(FAB_SF_MODE)"]   \n"
+"1:     ldr     r0, [r2, #"__stringify(FAB_SF_MODE)"]   \n"
+"       tst     r0, r3                  \n"
+"       beq     1b                      \n"
+"       bx      lr                      \n"
+
+"       .align  2                       \n"
+"2:     .word   .                       \n"
+"       .word   fabric_phys_addr        \n"
+        );
+}
+
+static const struct mcpm_platform_ops hip04_mcpm_ops = {
+        .power_up               = hip04_mcpm_power_up,
+        .power_down             = hip04_mcpm_power_down,
+        .wait_for_powerdown     = hip04_mcpm_wait_for_powerdown,
+        .powered_up             = hip04_mcpm_powered_up,
+};
+
+static bool __init hip04_cpu_table_init(void)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        if (cluster >= HIP04_MAX_CLUSTERS ||
+            cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
+                pr_err("%s: boot CPU is out of bound!\n", __func__);
+                return false;
+        }
+        hip04_set_snoop_filter(cluster, 1);
+        hip04_cpu_table[cluster][cpu] = 1;
+        return true;
+}
+
+static int __init hip04_mcpm_init(void)
+{
+        struct device_node *np, *np_sctl, *np_fab;
+        struct resource fab_res;
+        void __iomem *relocation;
+        int ret = -ENODEV;
+
+        np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper");
+        if (!np)
+                goto err;
+        ret = of_property_read_u32_array(np, "boot-method",
+                                         &hip04_boot_method[0], 4);
+        if (ret)
+                goto err;
+        np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+        if (!np_sctl)
+                goto err;
+        np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
+        if (!np_fab)
+                goto err;
+
+        ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]);
+        if (ret)
+                goto err;
+
+        relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]);
+        if (!relocation) {
+                pr_err("failed to map relocation space\n");
+                ret = -ENOMEM;
+                goto err_reloc;
+        }
+        sysctrl = of_iomap(np_sctl, 0);
+        if (!sysctrl) {
+                pr_err("failed to get sysctrl base\n");
+                ret = -ENOMEM;
+                goto err_sysctrl;
+        }
+        ret = of_address_to_resource(np_fab, 0, &fab_res);
+        if (ret) {
+                pr_err("failed to get fabric base phys\n");
+                goto err_fabric;
+        }
+        fabric_phys_addr = fab_res.start;
+        sync_cache_w(&fabric_phys_addr);
+        fabric = of_iomap(np_fab, 0);
+        if (!fabric) {
+                pr_err("failed to get fabric base\n");
+                ret = -ENOMEM;
+                goto err_fabric;
+        }
+
+        if (!hip04_cpu_table_init()) {
+                ret = -EINVAL;
+                goto err_table;
+        }
+        ret = mcpm_platform_register(&hip04_mcpm_ops);
+        if (ret) {
+                goto err_table;
+        }
+
+        /*
+         * Fill the instruction address that is used after secondary core
+         * out of reset.
+         */
+        writel_relaxed(hip04_boot_method[0], relocation);
+        writel_relaxed(0xa5a5a5a5, relocation + 4);     /* magic number */
+        writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8);
+        writel_relaxed(0, relocation + 12);
+        iounmap(relocation);
+
+        mcpm_sync_init(hip04_mcpm_power_up_setup);
+        mcpm_smp_set_ops();
+        pr_info("HiP04 MCPM initialized\n");
+        return ret;
+err_table:
+        iounmap(fabric);
+err_fabric:
+        iounmap(sysctrl);
+err_sysctrl:
+        iounmap(relocation);
+err_reloc:
+        memblock_free(hip04_boot_method[0], hip04_boot_method[1]);
+err:
+        return ret;
+}
+early_initcall(hip04_mcpm_init);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9de84a215abd..11b2957f792b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -69,6 +69,7 @@ config SOC_IMX1
         select CPU_ARM920T
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
+        select PINCTRL_IMX1
 
 config SOC_IMX21
         bool
@@ -85,7 +86,6 @@ config SOC_IMX25
 
 config SOC_IMX27
         bool
-        select ARCH_HAS_OPP
         select CPU_ARM926T
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
@@ -109,17 +109,6 @@ config SOC_IMX35
 if ARCH_MULTI_V4T
 
 comment "MX1 platforms:"
-config MACH_MXLADS
-        bool
-
-config ARCH_MX1ADS
-        bool "MX1ADS platform"
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select MACH_MXLADS
-        select SOC_IMX1
-        help
-          Say Y here if you are using Motorola MX1ADS/MXLADS boards
 
 config MACH_SCB9328
         bool "Synertronixx scb9328"
@@ -136,6 +125,13 @@ config MACH_APF9328
         help
           Say Yes here if you are using the Armadeus APF9328 development board
 
+config MACH_IMX1_DT
+        bool "Support i.MX1 platforms from device tree"
+        select SOC_IMX1
+        help
+          Include support for Freescale i.MX1 based platforms
+          using the device tree for discovery.
+
 endif
 
 if ARCH_MULTI_V5
@@ -224,86 +220,6 @@ config MACH_MX27ADS
           Include support for MX27ADS platform. This includes specific
           configurations for the board and its peripherals.
 
-config MACH_PCM038
-        bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_MXC_W1
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select USB_ULPI_VIEWPORT if USB_ULPI
-        select SOC_IMX27
-        help
-          Include support for phyCORE-i.MX27 (aka pcm038) platform. This
-          includes specific configurations for the module and its peripherals.
-
-choice
-        prompt "Baseboard"
-        depends on MACH_PCM038
-        default MACH_PCM970_BASEBOARD
-
-config MACH_PCM970_BASEBOARD
-        bool "PHYTEC PCM970 development board"
-        select IMX_HAVE_PLATFORM_IMX_FB
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        help
-          This adds board specific devices that can be found on Phytec's
-          PCM970 evaluation board.
-
-endchoice
-
-config MACH_CPUIMX27
-        bool "Eukrea CPUIMX27 module"
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_MXC_W1
-        select USB_ULPI_VIEWPORT if USB_ULPI
-        select SOC_IMX27
-        help
-          Include support for Eukrea CPUIMX27 platform. This includes
-          specific configurations for the module and its peripherals.
-
-config MACH_EUKREA_CPUIMX27_USESDHC2
-        bool "CPUIMX27 integrates SDHC2 module"
-        depends on MACH_CPUIMX27
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        help
-          This adds support for the internal SDHC2 used on CPUIMX27
-          for wifi or eMMC.
-
-config MACH_EUKREA_CPUIMX27_USEUART4
-        bool "CPUIMX27 integrates UART4 module"
-        depends on MACH_CPUIMX27
-        help
-          This adds support for the internal UART4 used on CPUIMX27
-          for bluetooth.
-
-choice
-        prompt "Baseboard"
-        depends on MACH_CPUIMX27
-        default MACH_EUKREA_MBIMX27_BASEBOARD
-
-config MACH_EUKREA_MBIMX27_BASEBOARD
-        bool "Eukrea MBIMX27 development board"
-        select IMX_HAVE_PLATFORM_IMX_FB
-        select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMX27 evaluation board.
-
-endchoice
-
 config MACH_MX27_3DS
         bool "MX27PDK platform"
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
@@ -360,18 +276,6 @@ config MACH_PCA100
           Include support for phyCARD-s (aka pca100) platform. This
           includes specific configurations for the module and its peripherals.
 
-config MACH_MXT_TD60
-        bool "Maxtrack i-MXT TD60"
-        select IMX_HAVE_PLATFORM_IMX_FB
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select SOC_IMX27
-        help
-          Include support for i-MXT (aka td60) platform. This
-          includes specific configurations for the module and its peripherals.
-
 config MACH_IMX27_DT
         bool "Support i.MX27 platforms from device tree"
         select SOC_IMX27
@@ -659,7 +563,6 @@ comment "Device tree only"
 
 config SOC_IMX5
         bool
-        select ARCH_HAS_OPP
         select HAVE_IMX_SRC
         select MXC_TZIC
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ac88599ca080..6e4fcd8339cd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                             clk-pfd.o clk-busy.o clk.o \
-                            clk-fixup-div.o clk-fixup-mux.o
+                            clk-fixup-div.o clk-fixup-mux.o \
+                            clk-gate-exclusive.o
 
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
@@ -41,9 +42,9 @@ obj-y += ssi-fiq-ksym.o
 endif
 
 # i.MX1 based machines
-obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
 obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
 obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
+obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
 
 # i.MX21 based machines
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
@@ -56,14 +57,9 @@ obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
 
 # i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
-obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
-obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
 obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
-obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
-obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
-obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
 obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
 
 # i.MX31 based machines
@@ -93,9 +89,11 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+ifdef CONFIG_SOC_IMX6
 AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+endif
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 4a40bbb46183..8259a625a920 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -104,6 +104,19 @@ void __init imx_init_revision_from_anatop(void)
         case 2:
                 revision = IMX_CHIP_REVISION_1_2;
                 break;
+        case 3:
+                revision = IMX_CHIP_REVISION_1_3;
+                break;
+        case 4:
+                revision = IMX_CHIP_REVISION_1_4;
+                break;
+        case 5:
+                /*
+                 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
+                 * as 'D' in Part Number last character.
+                 */
+                revision = IMX_CHIP_REVISION_1_5;
+                break;
         default:
                 revision = IMX_CHIP_REVISION_UNKNOWN;
         }
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 24b103c67f82..1a8932335b21 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -144,7 +144,7 @@ static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
                 if (nivector == 0xffff)
                         break;
 
-                handle_IRQ(irq_find_mapping(domain, nivector), regs);
+                handle_domain_irq(domain, nivector, regs);
         } while (1);
 }
 
diff --git a/arch/arm/mach-imx/board-pcm038.h b/arch/arm/mach-imx/board-pcm038.h
deleted file mode 100644
index 6f371e35753d..000000000000
--- a/arch/arm/mach-imx/board-pcm038.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
-#define __ASM_ARCH_MXC_BOARD_PCM038_H__
-
-#ifndef __ASSEMBLY__
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- * TODO: Add your own baseboard init function and call it from
- * inside pcm038_init().
- *
- * This example here is for the development board. Refer pcm970-baseboard.c
- */
-
-extern void pcm970_baseboard_init(void);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/arch/arm/mach-imx/clk-gate-exclusive.c b/arch/arm/mach-imx/clk-gate-exclusive.c
new file mode 100644
index 000000000000..c12f5f2e04dc
--- /dev/null
+++ b/arch/arm/mach-imx/clk-gate-exclusive.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+/**
+ * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
+ * exclusive with other gate clocks
+ *
+ * @gate: the parent class
+ * @exclusive_mask: mask of gate bits which are mutually exclusive to this
+ *      gate clock
+ *
+ * The imx exclusive gate clock is a subclass of basic clk_gate
+ * with an addtional mask to indicate which other gate bits in the same
+ * register is mutually exclusive to this gate clock.
+ */
+struct clk_gate_exclusive {
+        struct clk_gate gate;
+        u32 exclusive_mask;
+};
+
+static int clk_gate_exclusive_enable(struct clk_hw *hw)
+{
+        struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
+        struct clk_gate_exclusive *exgate = container_of(gate,
+                                        struct clk_gate_exclusive, gate);
+        u32 val = readl(gate->reg);
+
+        if (val & exgate->exclusive_mask)
+                return -EBUSY;
+
+        return clk_gate_ops.enable(hw);
+}
+
+static void clk_gate_exclusive_disable(struct clk_hw *hw)
+{
+        clk_gate_ops.disable(hw);
+}
+
+static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
+{
+        return clk_gate_ops.is_enabled(hw);
+}
+
+static const struct clk_ops clk_gate_exclusive_ops = {
+        .enable = clk_gate_exclusive_enable,
+        .disable = clk_gate_exclusive_disable,
+        .is_enabled = clk_gate_exclusive_is_enabled,
+};
+
+struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
+         void __iomem *reg, u8 shift, u32 exclusive_mask)
+{
+        struct clk_gate_exclusive *exgate;
+        struct clk_gate *gate;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        if (exclusive_mask == 0)
+                return ERR_PTR(-EINVAL);
+
+        exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
+        if (!exgate)
+                return ERR_PTR(-ENOMEM);
+        gate = &exgate->gate;
+
+        init.name = name;
+        init.ops = &clk_gate_exclusive_ops;
+        init.flags = CLK_SET_RATE_PARENT;
+        init.parent_names = parent ? &parent : NULL;
+        init.num_parents = parent ? 1 : 0;
+
+        gate->reg = reg;
+        gate->bit_idx = shift;
+        gate->lock = &imx_ccm_lock;
+        gate->hw.init = &init;
+        exgate->exclusive_mask = exclusive_mask;
+
+        clk = clk_register(NULL, &gate->hw);
+        if (IS_ERR(clk))
+                kfree(exgate);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 84acdfd1d715..5a75cdc81891 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
         struct clk_gate2 *gate = to_clk_gate2(hw);
 
         if (gate->share_count)
-                return !!(*gate->share_count);
+                return !!__clk_get_enable_count(hw->clk);
         else
                 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
 }
@@ -127,10 +127,6 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
         gate->bit_idx = bit_idx;
         gate->flags = clk_gate2_flags;
         gate->lock = lock;
-
-        /* Initialize share_count per hardware state */
-        if (share_count)
-                *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0;
         gate->share_count = share_count;
 
         init.name = name;
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 6cceb7765c14..1412daf4a714 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -64,7 +64,7 @@ static const char *cko2_sels[] = {
         "ipu2", "vdo_axi", "osc", "gpu2d_core",
         "gpu3d_core", "usdhc2", "ssi1", "ssi2",
         "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
-        "ldb_di0", "ldb_di1", "esai", "eim_slow",
+        "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
         "uart_serial", "spdif", "asrc", "hsi_tx",
 };
 static const char *cko_sels[] = { "cko1", "cko2", };
@@ -73,6 +73,14 @@ static const char *lvds_sels[] = {
         "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
         "pcie_ref_125m", "sata_ref_100m",
 };
+static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
+static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
+static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
+static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
+static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
+static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
+static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
+static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
 
 static struct clk *clk[IMX6QDL_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -107,6 +115,10 @@ static struct clk_div_table video_div_table[] = {
 };
 
 static unsigned int share_count_esai;
+static unsigned int share_count_asrc;
+static unsigned int share_count_ssi1;
+static unsigned int share_count_ssi2;
+static unsigned int share_count_ssi3;
 
 static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
@@ -119,6 +131,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
         clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
         clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
+        /* Clock source from external clock via CLK1/2 PADs */
+        clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
+        clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
         base = of_iomap(np, 0);
@@ -132,14 +147,47 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                 video_div_table[2].div = 1;
         };
 
-        /*                                             type             name         parent_name  base     div_mask */
-        clk[IMX6QDL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,   "pll1_sys",     "osc", base,        0x7f);
-        clk[IMX6QDL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,       "pll2_bus",     "osc", base + 0x30, 0x1);
-        clk[IMX6QDL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,   "pll3_usb_otg", "osc", base + 0x10, 0x3);
-        clk[IMX6QDL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,    "pll4_audio",   "osc", base + 0x70, 0x7f);
-        clk[IMX6QDL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,    "pll5_video",   "osc", base + 0xa0, 0x7f);
-        clk[IMX6QDL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,  "pll6_enet",    "osc", base + 0xe0, 0x3);
-        clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,   "pll7_usb_host","osc", base + 0x20, 0x3);
+        clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+
+        /*                                    type               name    parent_name        base         div_mask */
+        clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
+        clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
+        clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3", "pll3_bypass_src", base + 0x10, 0x3);
+        clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
+        clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
+        clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
+        clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7", "pll7_bypass_src", base + 0x20, 0x3);
+
+        clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
+
+        /* Do not bypass PLLs initially */
+        clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
+        clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
+        clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
+        clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
+        clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
+        clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
+        clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
+
+        clk[IMX6QDL_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
+        clk[IMX6QDL_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
+        clk[IMX6QDL_CLK_PLL3_USB_OTG]  = imx_clk_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);
+        clk[IMX6QDL_CLK_PLL4_AUDIO]    = imx_clk_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
+        clk[IMX6QDL_CLK_PLL5_VIDEO]    = imx_clk_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);
+        clk[IMX6QDL_CLK_PLL6_ENET]     = imx_clk_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);
+        clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
 
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,8 +224,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
          * the "output_enable" bit as a gate, even though it's really just
          * enabling clock output.
          */
-        clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
-        clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
+        clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
+        clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
+
+        clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
+        clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
 
         /*                                            name              parent_name        reg       idx */
         clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
@@ -194,6 +245,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[IMX6QDL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
         clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
         clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+        clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
+        if (cpu_is_imx6dl()) {
+                clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
+                clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
+        }
 
         clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
         clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
@@ -217,8 +273,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[IMX6QDL_CLK_ESAI_SEL]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
         clk[IMX6QDL_CLK_ASRC_SEL]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
         clk[IMX6QDL_CLK_SPDIF_SEL]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[IMX6QDL_CLK_GPU2D_AXI]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
-        clk[IMX6QDL_CLK_GPU3D_AXI]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        if (cpu_is_imx6q()) {
+                clk[IMX6QDL_CLK_GPU2D_AXI]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+                clk[IMX6QDL_CLK_GPU3D_AXI]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        }
         clk[IMX6QDL_CLK_GPU2D_CORE_SEL]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
         clk[IMX6QDL_CLK_GPU3D_CORE_SEL]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
         clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
@@ -311,7 +369,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 
         /*                                            name             parent_name          reg         shift */
         clk[IMX6QDL_CLK_APBH_DMA]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
-        clk[IMX6QDL_CLK_ASRC]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
+        clk[IMX6QDL_CLK_ASRC]         = imx_clk_gate2_shared("asrc",         "asrc_podf",   base + 0x68, 6, &share_count_asrc);
+        clk[IMX6QDL_CLK_ASRC_IPG]     = imx_clk_gate2_shared("asrc_ipg",     "ahb",         base + 0x68, 6, &share_count_asrc);
+        clk[IMX6QDL_CLK_ASRC_MEM]     = imx_clk_gate2_shared("asrc_mem",     "ahb",         base + 0x68, 6, &share_count_asrc);
         clk[IMX6QDL_CLK_CAN1_IPG]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
         clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
         clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
@@ -325,8 +385,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         else
                 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
         clk[IMX6QDL_CLK_ENET]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
-        clk[IMX6QDL_CLK_ESAI]         = imx_clk_gate2_shared("esai",   "esai_podf",         base + 0x6c, 16, &share_count_esai);
-        clk[IMX6QDL_CLK_ESAI_AHB]     = imx_clk_gate2_shared("esai_ahb", "ahb",             base + 0x6c, 16, &share_count_esai);
+        clk[IMX6QDL_CLK_ESAI_EXTAL]   = imx_clk_gate2_shared("esai_extal",   "esai_podf",   base + 0x6c, 16, &share_count_esai);
+        clk[IMX6QDL_CLK_ESAI_IPG]     = imx_clk_gate2_shared("esai_ipg",   "ipg",           base + 0x6c, 16, &share_count_esai);
+        clk[IMX6QDL_CLK_ESAI_MEM]     = imx_clk_gate2_shared("esai_mem", "ahb",             base + 0x6c, 16, &share_count_esai);
         clk[IMX6QDL_CLK_GPT_IPG]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
         clk[IMX6QDL_CLK_GPT_IPG_PER]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
         if (cpu_is_imx6dl())
@@ -382,9 +443,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
         clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
         clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
-        clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
-        clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
-        clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
+        clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
+        clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
+        clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
+        clk[IMX6QDL_CLK_SSI1]         = imx_clk_gate2_shared("ssi1",          "ssi1_podf",  base + 0x7c, 18, &share_count_ssi1);
+        clk[IMX6QDL_CLK_SSI2]         = imx_clk_gate2_shared("ssi2",          "ssi2_podf",  base + 0x7c, 20, &share_count_ssi2);
+        clk[IMX6QDL_CLK_SSI3]         = imx_clk_gate2_shared("ssi3",          "ssi3_podf",  base + 0x7c, 22, &share_count_ssi3);
         clk[IMX6QDL_CLK_UART_IPG]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
         clk[IMX6QDL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
         clk[IMX6QDL_CLK_USBOH3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
@@ -398,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[IMX6QDL_CLK_CKO1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
         clk[IMX6QDL_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
 
+        /*
+         * The gpt_3m clock is not available on i.MX6Q TO1.0.  Let's point it
+         * to clock gpt_ipg_per to ease the gpt driver code.
+         */
+        if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
+                clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];
+
         imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_data.clks = clk;
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index fef46faf692f..e982ebe10814 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -43,11 +43,13 @@ static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", "dummy",
 static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "pll2_bus", };
 static const char *periph_sels[]        = { "pre_periph_sel", "periph_clk2_podf", };
 static const char *periph2_sels[]       = { "pre_periph2_sel", "periph2_clk2_podf", };
-static const char *csi_lcdif_sels[]     = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char *csi_sels[]           = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char *lcdif_axi_sels[]     = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
 static const char *usdhc_sels[]         = { "pll2_pfd2", "pll2_pfd0", };
 static const char *ssi_sels[]           = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
 static const char *perclk_sels[]        = { "ipg", "osc", };
-static const char *epdc_pxp_sels[]      = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char *pxp_axi_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
+static const char *epdc_axi_sels[]      = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
 static const char *gpu2d_ovg_sels[]     = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
 static const char *gpu2d_sels[]         = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
 static const char *lcdif_pix_sels[]     = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
@@ -55,6 +57,20 @@ static const char *epdc_pix_sels[]	= { "pll2_bus", "pll3_usb_otg", "pll5_video_d
 static const char *audio_sels[]         = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
 static const char *ecspi_sels[]         = { "pll3_60m", "osc", };
 static const char *uart_sels[]          = { "pll3_80m", "osc", };
+static const char *lvds_sels[]          = {
+        "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
+        "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
+        "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
+         "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
+};
+static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
+static const char *pll1_bypass_sels[]   = { "pll1", "pll1_bypass_src", };
+static const char *pll2_bypass_sels[]   = { "pll2", "pll2_bypass_src", };
+static const char *pll3_bypass_sels[]   = { "pll3", "pll3_bypass_src", };
+static const char *pll4_bypass_sels[]   = { "pll4", "pll4_bypass_src", };
+static const char *pll5_bypass_sels[]   = { "pll5", "pll5_bypass_src", };
+static const char *pll6_bypass_sels[]   = { "pll6", "pll6_bypass_src", };
+static const char *pll7_bypass_sels[]   = { "pll7", "pll7_bypass_src", };
 
 static struct clk_div_table clk_enet_ref_table[] = {
         { .val = 0, .div = 20, },
@@ -79,6 +95,10 @@ static struct clk_div_table video_div_table[] = {
         { }
 };
 
+static unsigned int share_count_ssi1;
+static unsigned int share_count_ssi2;
+static unsigned int share_count_ssi3;
+
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
 static void __iomem *ccm_base;
@@ -175,20 +195,59 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
         clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
         clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
+        /* Clock source from external clock via CLK1 PAD */
+        clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
         base = of_iomap(np, 0);
         WARN_ON(!base);
         anatop_base = base;
 
-        /*                                             type               name            parent  base         div_mask */
-        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
-        clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1);
-        clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3);
-        clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f);
-        clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f);
-        clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3);
-        clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3);
+        clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+
+        /*                                    type               name    parent_name        base         div_mask */
+        clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
+        clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
+        clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3", "pll3_bypass_src", base + 0x10, 0x3);
+        clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
+        clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
+        clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
+        clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7", "pll7_bypass_src", base + 0x20, 0x3);
+
+        clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
+
+        /* Do not bypass PLLs initially */
+        clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
+        clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
+        clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
+        clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
+        clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
+        clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
+        clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
+
+        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
+        clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
+        clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);
+        clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
+        clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);
+        clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);
+        clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
+
+        clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+        clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
+        clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
 
         /*
          * usbphy1 and usbphy2 are implemented as dummy gates using reserve
@@ -241,8 +300,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_PRE_PERIPH_SEL]   = imx_clk_mux("pre_periph_sel",   base + 0x18, 18, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
         clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
         clks[IMX6SL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
-        clks[IMX6SL_CLK_CSI_SEL]          = imx_clk_mux("csi_sel",          base + 0x3c, 9,  2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
-        clks[IMX6SL_CLK_LCDIF_AXI_SEL]    = imx_clk_mux("lcdif_axi_sel",    base + 0x3c, 14, 2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+        clks[IMX6SL_CLK_CSI_SEL]          = imx_clk_mux("csi_sel",          base + 0x3c, 9,  2, csi_sels,          ARRAY_SIZE(csi_sels));
+        clks[IMX6SL_CLK_LCDIF_AXI_SEL]    = imx_clk_mux("lcdif_axi_sel",    base + 0x3c, 14, 2, lcdif_axi_sels,    ARRAY_SIZE(lcdif_axi_sels));
         clks[IMX6SL_CLK_USDHC1_SEL]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),  imx_cscmr1_fixup);
         clks[IMX6SL_CLK_USDHC2_SEL]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),  imx_cscmr1_fixup);
         clks[IMX6SL_CLK_USDHC3_SEL]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),  imx_cscmr1_fixup);
@@ -251,8 +310,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_SSI2_SEL]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),    imx_cscmr1_fixup);
         clks[IMX6SL_CLK_SSI3_SEL]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),    imx_cscmr1_fixup);
         clks[IMX6SL_CLK_PERCLK_SEL]       = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6,  1, perclk_sels,       ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
-        clks[IMX6SL_CLK_PXP_AXI_SEL]      = imx_clk_mux("pxp_axi_sel",      base + 0x34, 6,  3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
-        clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+        clks[IMX6SL_CLK_PXP_AXI_SEL]      = imx_clk_mux("pxp_axi_sel",      base + 0x34, 6,  3, pxp_axi_sels,      ARRAY_SIZE(pxp_axi_sels));
+        clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_axi_sels,     ARRAY_SIZE(epdc_axi_sels));
         clks[IMX6SL_CLK_GPU2D_OVG_SEL]    = imx_clk_mux("gpu2d_ovg_sel",    base + 0x18, 4,  2, gpu2d_ovg_sels,    ARRAY_SIZE(gpu2d_ovg_sels));
         clks[IMX6SL_CLK_GPU2D_SEL]        = imx_clk_mux("gpu2d_sel",        base + 0x18, 8,  2, gpu2d_sels,        ARRAY_SIZE(gpu2d_sels));
         clks[IMX6SL_CLK_LCDIF_PIX_SEL]    = imx_clk_mux("lcdif_pix_sel",    base + 0x38, 6,  3, lcdif_pix_sels,    ARRAY_SIZE(lcdif_pix_sels));
@@ -337,9 +396,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
         clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
         clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
-        clks[IMX6SL_CLK_SSI1]         = imx_clk_gate2("ssi1",         "ssi1_podf",         base + 0x7c, 18);
-        clks[IMX6SL_CLK_SSI2]         = imx_clk_gate2("ssi2",         "ssi2_podf",         base + 0x7c, 20);
-        clks[IMX6SL_CLK_SSI3]         = imx_clk_gate2("ssi3",         "ssi3_podf",         base + 0x7c, 22);
+        clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
+        clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
+        clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
+        clks[IMX6SL_CLK_SSI1]         = imx_clk_gate2_shared("ssi1",         "ssi1_podf",  base + 0x7c, 18, &share_count_ssi1);
+        clks[IMX6SL_CLK_SSI2]         = imx_clk_gate2_shared("ssi2",         "ssi2_podf",  base + 0x7c, 20, &share_count_ssi2);
+        clks[IMX6SL_CLK_SSI3]         = imx_clk_gate2_shared("ssi3",         "ssi3_podf",  base + 0x7c, 22, &share_count_ssi3);
         clks[IMX6SL_CLK_UART]         = imx_clk_gate2("uart",         "ipg",               base + 0x7c, 24);
         clks[IMX6SL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",  "uart_root",         base + 0x7c, 26);
         clks[IMX6SL_CLK_USBOH3]       = imx_clk_gate2("usboh3",       "ipg",               base + 0x80, 0);
@@ -375,6 +437,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         /* Audio-related clocks configuration */
         clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
 
+        /* set PLL5 video as lcdif pix parent clock */
+        clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
+                        clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
+
+        clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
+                       clks[IMX6SL_CLK_PLL2_PFD2]);
+
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
 }
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index ecde72bdfe88..17354a11356f 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -81,6 +81,14 @@ static const char *lvds_sels[]	= {
         "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
         "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
 };
+static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
+static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
+static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
+static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
+static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
+static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
+static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
+static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
 
 static struct clk *clks[IMX6SX_CLK_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -143,18 +151,54 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
         clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
 
+        /* Clock source from external clock via CLK1 PAD */
+        clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
+
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
         base = of_iomap(np, 0);
         WARN_ON(!base);
 
-        /*                                              type               name             parent_name   base         div_mask */
-        clks[IMX6SX_CLK_PLL1_SYS]       = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc",        base,        0x7f);
-        clks[IMX6SX_CLK_PLL2_BUS]       = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc",        base + 0x30, 0x1);
-        clks[IMX6SX_CLK_PLL3_USB_OTG]   = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc",        base + 0x10, 0x3);
-        clks[IMX6SX_CLK_PLL4_AUDIO]     = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc",        base + 0x70, 0x7f);
-        clks[IMX6SX_CLK_PLL5_VIDEO]     = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc",        base + 0xa0, 0x7f);
-        clks[IMX6SX_CLK_PLL6_ENET]      = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc",        base + 0xe0, 0x3);
-        clks[IMX6SX_CLK_PLL7_USB_HOST]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc",        base + 0x20, 0x3);
+        clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+
+        /*                                    type               name    parent_name        base         div_mask */
+        clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
+        clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
+        clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3", "pll3_bypass_src", base + 0x10, 0x3);
+        clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
+        clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
+        clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
+        clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7", "pll7_bypass_src", base + 0x20, 0x3);
+
+        clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
+
+        /* Do not bypass PLLs initially */
+        clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
+        clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
+        clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
+        clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
+        clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
+        clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
+        clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
+
+        clks[IMX6SX_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
+        clks[IMX6SX_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
+        clks[IMX6SX_CLK_PLL3_USB_OTG]  = imx_clk_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);
+        clks[IMX6SX_CLK_PLL4_AUDIO]    = imx_clk_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
+        clks[IMX6SX_CLK_PLL5_VIDEO]    = imx_clk_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);
+        clks[IMX6SX_CLK_PLL6_ENET]     = imx_clk_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);
+        clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
 
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,7 +220,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
         clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
 
-        clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
+        clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
+        clks[IMX6SX_CLK_LVDS1_IN]  = imx_clk_gate_exclusive("lvds1_in",  "anaclk1",   base + 0x160, 12, BIT(10));
 
         clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 61364050fccd..57de74da0acf 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -23,8 +23,6 @@
 #define PLL_DENOM_OFFSET        0x20
 
 #define BM_PLL_POWER            (0x1 << 12)
-#define BM_PLL_ENABLE           (0x1 << 13)
-#define BM_PLL_BYPASS           (0x1 << 16)
 #define BM_PLL_LOCK             (0x1 << 31)
 
 /**
@@ -84,10 +82,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
         if (ret)
                 return ret;
 
-        val = readl_relaxed(pll->base);
-        val &= ~BM_PLL_BYPASS;
-        writel_relaxed(val, pll->base);
-
         return 0;
 }
 
@@ -97,7 +91,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
         u32 val;
 
         val = readl_relaxed(pll->base);
-        val |= BM_PLL_BYPASS;
         if (pll->powerup_set)
                 val &= ~BM_PLL_POWER;
         else
@@ -105,28 +98,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
         writel_relaxed(val, pll->base);
 }
 
-static int clk_pllv3_enable(struct clk_hw *hw)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val;
-
-        val = readl_relaxed(pll->base);
-        val |= BM_PLL_ENABLE;
-        writel_relaxed(val, pll->base);
-
-        return 0;
-}
-
-static void clk_pllv3_disable(struct clk_hw *hw)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val;
-
-        val = readl_relaxed(pll->base);
-        val &= ~BM_PLL_ENABLE;
-        writel_relaxed(val, pll->base);
-}
-
 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
                                            unsigned long parent_rate)
 {
@@ -169,8 +140,6 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
 static const struct clk_ops clk_pllv3_ops = {
         .prepare        = clk_pllv3_prepare,
         .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
         .recalc_rate    = clk_pllv3_recalc_rate,
         .round_rate     = clk_pllv3_round_rate,
         .set_rate       = clk_pllv3_set_rate,
@@ -225,8 +194,6 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
 static const struct clk_ops clk_pllv3_sys_ops = {
         .prepare        = clk_pllv3_prepare,
         .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
         .recalc_rate    = clk_pllv3_sys_recalc_rate,
         .round_rate     = clk_pllv3_sys_round_rate,
         .set_rate       = clk_pllv3_sys_set_rate,
@@ -299,8 +266,6 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
 static const struct clk_ops clk_pllv3_av_ops = {
         .prepare        = clk_pllv3_prepare,
         .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
         .recalc_rate    = clk_pllv3_av_recalc_rate,
         .round_rate     = clk_pllv3_av_round_rate,
         .set_rate       = clk_pllv3_av_set_rate,
@@ -315,8 +280,6 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
 static const struct clk_ops clk_pllv3_enet_ops = {
         .prepare        = clk_pllv3_prepare,
         .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
         .recalc_rate    = clk_pllv3_enet_recalc_rate,
 };
 
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index f60d6d569ce3..a17818475050 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -58,6 +58,8 @@
 #define PFD_PLL1_BASE           (anatop_base + 0x2b0)
 #define PFD_PLL2_BASE           (anatop_base + 0x100)
 #define PFD_PLL3_BASE           (anatop_base + 0xf0)
+#define PLL3_CTRL               (anatop_base + 0x10)
+#define PLL7_CTRL               (anatop_base + 0x20)
 
 static void __iomem *anatop_base;
 static void __iomem *ccm_base;
@@ -98,9 +100,15 @@ static struct clk_div_table pll4_main_div_table[] = {
 static struct clk *clk[VF610_CLK_END];
 static struct clk_onecell_data clk_data;
 
+static unsigned int const clks_init_on[] __initconst = {
+        VF610_CLK_SYS_BUS,
+        VF610_CLK_DDR_SEL,
+};
+
 static void __init vf610_clocks_init(struct device_node *ccm_node)
 {
         struct device_node *np;
+        int i;
 
         clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
         clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
@@ -148,6 +156,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
         /* pll6: default 960Mhz */
         clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
+        /* pll7: USB1 PLL at 480MHz */
+        clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
+
         clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
         clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
         clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
@@ -160,8 +171,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
         clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
 
-        clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
-        clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
+        clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
+
+        clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
 
         clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
         clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
@@ -322,6 +336,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
         clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
 
+        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+                clk_prepare_enable(clk[clks_init_on[i]]);
+
         /* Add the clocks to provider list */
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d5ba76fee115..4cdf8b6a74e8 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -36,6 +36,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
 struct clk * imx_obtain_fixed_clock(
                         const char *name, unsigned long rate);
 
+struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
+         void __iomem *reg, u8 shift, u32 exclusive_mask);
+
 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
                 void __iomem *reg, u8 shift)
 {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 22ba8973bcb9..1dabf435c592 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -98,11 +98,9 @@ void imx_set_cpu_arg(int cpu, u32 arg);
 void v7_secondary_startup(void);
 void imx_scu_map_io(void);
 void imx_smp_prepare(void);
-void imx_scu_standby_enable(void);
 #else
 static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
-static inline void imx_scu_standby_enable(void) {}
 #endif
 void imx_src_init(void);
 void imx_gpc_init(void);
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 10844d3bb926..aa935787b743 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -66,10 +66,6 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
 
 int __init imx6q_cpuidle_init(void)
 {
-        /* Need to enable SCU standby for entering WAIT modes */
-        if (!cpu_is_imx6sx())
-                imx_scu_standby_enable();
-
         /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
         imx6q_set_int_mem_clk_lpm(true);
 
diff --git a/arch/arm/mach-imx/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h
index a21d3313f994..bb2c90d65914 100644
--- a/arch/arm/mach-imx/eukrea-baseboards.h
+++ b/arch/arm/mach-imx/eukrea-baseboards.h
@@ -27,23 +27,15 @@
  * This CPU module needs a baseboard to work. After basic initializing
  * its own devices, it calls baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
- * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
- * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
- * or eukrea_cpuimx51sd_init().
+ * inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init()
  *
  * This example here is for the development board. Refer
  * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
- * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
  * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
- * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
- * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
  */
 
 extern void eukrea_mbimxsd25_baseboard_init(void);
-extern void eukrea_mbimx27_baseboard_init(void);
 extern void eukrea_mbimxsd35_baseboard_init(void);
-extern void eukrea_mbimx51_baseboard_init(void);
-extern void eukrea_mbimxsd51_baseboard_init(void);
 
 #endif
 
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
deleted file mode 100644
index b2f08bfbbdd3..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/backlight.h>
-#include <video/platform_lcd.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-
-static const int eukrea_mbimx27_pins[] __initconst = {
-        /* UART2 */
-        PE3_PF_UART2_CTS,
-        PE4_PF_UART2_RTS,
-        PE6_PF_UART2_TXD,
-        PE7_PF_UART2_RXD,
-        /* UART3 */
-        PE8_PF_UART3_TXD,
-        PE9_PF_UART3_RXD,
-        PE10_PF_UART3_CTS,
-        PE11_PF_UART3_RTS,
-        /* UART4 */
-#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
-        PB26_AF_UART4_RTS,
-        PB28_AF_UART4_TXD,
-        PB29_AF_UART4_CTS,
-        PB31_AF_UART4_RXD,
-#endif
-        /* SDHC1*/
-        PE18_PF_SD1_D0,
-        PE19_PF_SD1_D1,
-        PE20_PF_SD1_D2,
-        PE21_PF_SD1_D3,
-        PE22_PF_SD1_CMD,
-        PE23_PF_SD1_CLK,
-        /* display */
-        PA5_PF_LSCLK,
-        PA6_PF_LD0,
-        PA7_PF_LD1,
-        PA8_PF_LD2,
-        PA9_PF_LD3,
-        PA10_PF_LD4,
-        PA11_PF_LD5,
-        PA12_PF_LD6,
-        PA13_PF_LD7,
-        PA14_PF_LD8,
-        PA15_PF_LD9,
-        PA16_PF_LD10,
-        PA17_PF_LD11,
-        PA18_PF_LD12,
-        PA19_PF_LD13,
-        PA20_PF_LD14,
-        PA21_PF_LD15,
-        PA22_PF_LD16,
-        PA23_PF_LD17,
-        PA28_PF_HSYNC,
-        PA29_PF_VSYNC,
-        PA30_PF_CONTRAST,
-        PA31_PF_OE_ACD,
-        /* SPI1 */
-        PD29_PF_CSPI1_SCLK,
-        PD30_PF_CSPI1_MISO,
-        PD31_PF_CSPI1_MOSI,
-        /* SSI4 */
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
-        || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
-        PC16_PF_SSI4_FS,
-        PC17_PF_SSI4_RXD | GPIO_PUEN,
-        PC18_PF_SSI4_TXD | GPIO_PUEN,
-        PC19_PF_SSI4_CLK,
-#endif
-};
-
-static const uint32_t eukrea_mbimx27_keymap[] = {
-        KEY(0, 0, KEY_UP),
-        KEY(0, 1, KEY_DOWN),
-        KEY(1, 0, KEY_RIGHT),
-        KEY(1, 1, KEY_LEFT),
-};
-
-static const struct matrix_keymap_data
-eukrea_mbimx27_keymap_data __initconst = {
-        .keymap         = eukrea_mbimx27_keymap,
-        .keymap_size    = ARRAY_SIZE(eukrea_mbimx27_keymap),
-};
-
-static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = {
-        {
-                .name                   = "led1",
-                .default_trigger        = "heartbeat",
-                .active_low             = 1,
-                .gpio                   = GPIO_PORTF | 16,
-        },
-        {
-                .name                   = "led2",
-                .default_trigger        = "none",
-                .active_low             = 1,
-                .gpio                   = GPIO_PORTF | 19,
-        },
-};
-
-static const struct gpio_led_platform_data
-                eukrea_mbimx27_gpio_led_info __initconst = {
-        .leds           = eukrea_mbimx27_gpio_leds,
-        .num_leds       = ARRAY_SIZE(eukrea_mbimx27_gpio_leds),
-};
-
-static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
-        {
-                .mode = {
-                        .name           = "CMO-QVGA",
-                        .refresh        = 60,
-                        .xres           = 320,
-                        .yres           = 240,
-                        .pixclock       = 156000,
-                        .hsync_len      = 30,
-                        .left_margin    = 38,
-                        .right_margin   = 20,
-                        .vsync_len      = 3,
-                        .upper_margin   = 15,
-                        .lower_margin   = 4,
-                },
-                .pcr            = 0xFAD08B80,
-                .bpp            = 16,
-        }, {
-                .mode = {
-                        .name           = "DVI-VGA",
-                        .refresh        = 60,
-                        .xres           = 640,
-                        .yres           = 480,
-                        .pixclock       = 32000,
-                        .hsync_len      = 1,
-                        .left_margin    = 35,
-                        .right_margin   = 0,
-                        .vsync_len      = 1,
-                        .upper_margin   = 7,
-                        .lower_margin   = 0,
-                },
-                .pcr            = 0xFA208B80,
-                .bpp            = 16,
-        }, {
-                .mode = {
-                        .name           = "DVI-SVGA",
-                        .refresh        = 60,
-                        .xres           = 800,
-                        .yres           = 600,
-                        .pixclock       = 25000,
-                        .hsync_len      = 1,
-                        .left_margin    = 35,
-                        .right_margin   = 0,
-                        .vsync_len      = 1,
-                        .upper_margin   = 7,
-                        .lower_margin   = 0,
-                },
-                .pcr            = 0xFA208B80,
-                .bpp            = 16,
-        },
-};
-
-static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
-        .mode = eukrea_mbimx27_modes,
-        .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
-
-        .pwmr           = 0x00A903FF,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00040060,
-};
-
-static void eukrea_mbimx27_bl_set_intensity(int intensity)
-{
-        if (intensity)
-                gpio_direction_output(GPIO_PORTE | 5, 1);
-        else
-                gpio_direction_output(GPIO_PORTE | 5, 0);
-}
-
-static struct generic_bl_info eukrea_mbimx27_bl_info = {
-        .name                   = "eukrea_mbimx27-bl",
-        .max_intensity          = 0xff,
-        .default_intensity      = 0xff,
-        .set_bl_intensity       = eukrea_mbimx27_bl_set_intensity,
-};
-
-static struct platform_device eukrea_mbimx27_bl_dev = {
-        .name                   = "generic-bl",
-        .id                     = 1,
-        .dev = {
-                .platform_data  = &eukrea_mbimx27_bl_info,
-        },
-};
-
-static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power)
-                gpio_direction_output(GPIO_PORTA | 25, 1);
-        else
-                gpio_direction_output(GPIO_PORTA | 25, 0);
-}
-
-static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
-        .set_power              = eukrea_mbimx27_lcd_power_set,
-};
-
-static struct platform_device eukrea_mbimx27_lcd_powerdev = {
-        .name                   = "platform-lcd",
-        .dev.platform_data      = &eukrea_mbimx27_lcd_power_data,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-#define ADS7846_PENDOWN (GPIO_PORTD | 25)
-
-static void __maybe_unused ads7846_dev_init(void)
-{
-        if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
-                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
-                return;
-        }
-        gpio_direction_input(ADS7846_PENDOWN);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(ADS7846_PENDOWN);
-}
-
-static struct ads7846_platform_data ads7846_config __initdata = {
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
-static struct spi_board_info __maybe_unused
-                eukrea_mbimx27_spi_board_info[] __initdata = {
-        [0] = {
-                .modalias       = "ads7846",
-                .bus_num        = 0,
-                .chip_select    = 0,
-                .max_speed_hz   = 1500000,
-                /* irq number is run-time assigned */
-                .platform_data  = &ads7846_config,
-                .mode           = SPI_MODE_2,
-        },
-};
-
-static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
-
-static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
-        .chipselect     = eukrea_mbimx27_spi_cs,
-        .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
-};
-
-static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-};
-
-static const struct imxmmc_platform_data sdhc_pdata __initconst = {
-        .dat3_card_detect = 1,
-};
-
-static const
-struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
-        .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
-};
-
-/*
- * system init for baseboard usage. Will be called by cpuimx27 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimx27_baseboard_init(void)
-{
-        mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
-                ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
-
-        imx27_add_imx_uart1(&uart_pdata);
-        imx27_add_imx_uart2(&uart_pdata);
-#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
-        imx27_add_imx_uart3(&uart_pdata);
-#endif
-
-        imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
-        imx27_add_mxc_mmc(0, &sdhc_pdata);
-
-        i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
-                                ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
-
-        imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
-
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
-        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        /* ADS7846 Touchscreen controller init */
-        mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
-        ads7846_dev_init();
-#endif
-
-        /* SPI_CS0 init */
-        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-        imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
-        eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
-        spi_register_board_info(eukrea_mbimx27_spi_board_info,
-                        ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
-
-        /* Leds configuration */
-        mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
-        mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
-        /* Backlight */
-        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
-        gpio_request(GPIO_PORTE | 5, "backlight");
-        platform_device_register(&eukrea_mbimx27_bl_dev);
-        /* LCD Reset */
-        mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
-        gpio_request(GPIO_PORTA | 25, "lcd_enable");
-        platform_device_register(&eukrea_mbimx27_lcd_powerdev);
-
-        imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
-
-        gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
-}
diff --git a/arch/arm/mach-imx/imx1-dt.c b/arch/arm/mach-imx/imx1-dt.c
new file mode 100644
index 000000000000..6f915b0961c4
--- /dev/null
+++ b/arch/arm/mach-imx/imx1-dt.c
@@ -0,0 +1,26 @@
+/*
+ *  Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const imx1_dt_board_compat[] __initconst = {
+        "fsl,imx1",
+        NULL
+};
+
+DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
+        .map_io         = mx1_map_io,
+        .init_early     = imx1_init_early,
+        .init_irq       = mx1_init_irq,
+        .dt_compat      = imx1_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 080e66c6a1d0..dc8f1a6f45f2 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -20,7 +20,7 @@
 
 static void __init imx27_dt_init(void)
 {
-        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+        struct platform_device_info devinfo = { .name = "cpufreq-dt", };
 
         mxc_arch_reset_init_dt();
 
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 7c66805d2cc0..1657fe64cd0f 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -64,7 +64,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
 
         return ret;
 }
-EXPORT_SYMBOL(mxc_iomux_mode);
 
 /*
  * This function configures the pad value for a IOMUX pin.
@@ -90,7 +89,6 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
 
         spin_unlock(&gpio_mux_lock);
 }
-EXPORT_SYMBOL(mxc_iomux_set_pad);
 
 /*
  * allocs a single pin:
@@ -116,7 +114,6 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
 
         return 0;
 }
-EXPORT_SYMBOL(mxc_iomux_alloc_pin);
 
 int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                 const char *label)
@@ -137,7 +134,6 @@ setup_error:
         mxc_iomux_release_multiple_pins(pin_list, i);
         return ret;
 }
-EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
 
 void mxc_iomux_release_pin(unsigned int pin)
 {
@@ -146,7 +142,6 @@ void mxc_iomux_release_pin(unsigned int pin)
         if (pad < (PIN_MAX + 1))
                 clear_bit(pad, mxc_pin_alloc_map);
 }
-EXPORT_SYMBOL(mxc_iomux_release_pin);
 
 void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
 {
@@ -158,7 +153,6 @@ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
                 p++;
         }
 }
-EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
 
 /*
  * This function enables/disables the general purpose function for a particular
@@ -178,4 +172,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
         __raw_writel(l, IOMUXGPR);
         spin_unlock(&gpio_mux_lock);
 }
-EXPORT_SYMBOL(mxc_iomux_set_gpr);
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index 2b156d1d9e21..ecd543664644 100644
--- a/arch/arm/mach-imx/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -153,7 +153,6 @@ int mxc_gpio_mode(int gpio_mode)
 
         return 0;
 }
-EXPORT_SYMBOL(mxc_gpio_mode);
 
 static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
 {
@@ -178,7 +177,6 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
         ret = imx_iomuxv1_setup_multiple(pin_list, count);
         return ret;
 }
-EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
 
 int __init imx_iomuxv1_init(void __iomem *base, int numports)
 {
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 9dae74bf47fc..d61f9606fc56 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -55,7 +55,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 
         return 0;
 }
-EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
 
 int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
 {
@@ -71,7 +70,6 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
         }
         return 0;
 }
-EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
 
 void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
 {
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index a7e9bd26a552..f2060523ba48 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -537,7 +537,7 @@ static void __init armadillo5x0_init(void)
                         gpio_free(ARMADILLO5X0_RTC_GPIO);
         }
         if (armadillo5x0_i2c_rtc.irq == 0)
-                pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
+                pr_warn("armadillo5x0_init: failed to get RTC IRQ\n");
         i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
 
         /* USB */
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
deleted file mode 100644
index e6d4b9929571..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
- *
- * Based on pcm038.c which is :
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "ehci.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
-
-static const int eukrea_cpuimx27_pins[] __initconst = {
-        /* UART1 */
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        PE14_PF_UART1_CTS,
-        PE15_PF_UART1_RTS,
-        /* UART4 */
-#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
-        PB26_AF_UART4_RTS,
-        PB28_AF_UART4_TXD,
-        PB29_AF_UART4_CTS,
-        PB31_AF_UART4_RXD,
-#endif
-        /* FEC */
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN,
-        /* I2C1 */
-        PD17_PF_I2C_DATA,
-        PD18_PF_I2C_CLK,
-        /* SDHC2 */
-#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
-        PB4_PF_SD2_D0,
-        PB5_PF_SD2_D1,
-        PB6_PF_SD2_D2,
-        PB7_PF_SD2_D3,
-        PB8_PF_SD2_CMD,
-        PB9_PF_SD2_CLK,
-#endif
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-        /* Quad UART's IRQ */
-        GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
-#endif
-        /* OTG */
-        PC7_PF_USBOTG_DATA5,
-        PC8_PF_USBOTG_DATA6,
-        PC9_PF_USBOTG_DATA0,
-        PC10_PF_USBOTG_DATA2,
-        PC11_PF_USBOTG_DATA1,
-        PC12_PF_USBOTG_DATA4,
-        PC13_PF_USBOTG_DATA3,
-        PE0_PF_USBOTG_NXT,
-        PE1_PF_USBOTG_STP,
-        PE2_PF_USBOTG_DIR,
-        PE24_PF_USBOTG_CLK,
-        PE25_PF_USBOTG_DATA7,
-        /* USBH2 */
-        PA0_PF_USBH2_CLK,
-        PA1_PF_USBH2_DIR,
-        PA2_PF_USBH2_DATA7,
-        PA3_PF_USBH2_NXT,
-        PA4_PF_USBH2_STP,
-        PD19_AF_USBH2_DATA4,
-        PD20_AF_USBH2_DATA3,
-        PD21_AF_USBH2_DATA6,
-        PD22_AF_USBH2_DATA0,
-        PD23_AF_USBH2_DATA2,
-        PD24_AF_USBH2_DATA1,
-        PD26_AF_USBH2_DATA5,
-};
-
-static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
-        .width = 2,
-};
-
-static struct resource eukrea_cpuimx27_flash_resource = {
-        .start = 0xc0000000,
-        .end   = 0xc3ffffff,
-        .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
-        .name = "physmap-flash",
-        .id = 0,
-        .dev = {
-                .platform_data = &eukrea_cpuimx27_flash_data,
-        },
-        .num_resources = 1,
-        .resource = &eukrea_cpuimx27_flash_resource,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct mxc_nand_platform_data
-cpuimx27_nand_board_info __initconst = {
-        .width = 1,
-        .hw_ecc = 1,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
-        &eukrea_cpuimx27_nor_mtd_device,
-};
-
-static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
-        .bitrate = 100000,
-};
-
-static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        },
-};
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-static struct plat_serial8250_port serial_platform_data[] = {
-        {
-                .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
-                /* irq number is run-time assigned */
-                .uartclk = 14745600,
-                .regshift = 1,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-                .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
-                /* irq number is run-time assigned */
-                .uartclk = 14745600,
-                .regshift = 1,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-                .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
-                /* irq number is run-time assigned */
-                .uartclk = 14745600,
-                .regshift = 1,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-                .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
-                /* irq number is run-time assigned */
-                .uartclk = 14745600,
-                .regshift = 1,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-        }
-};
-
-static struct platform_device serial_device = {
-        .name = "serial8250",
-        .id = 0,
-        .dev = {
-                .platform_data = serial_platform_data,
-        },
-};
-#endif
-
-static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
-{
-        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
-        .init   = eukrea_cpuimx27_otg_init,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
-{
-        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
-        .init   = eukrea_cpuimx27_usbh2_init,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init eukrea_cpuimx27_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = true;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = false;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 1;
-}
-__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
-
-static void __init eukrea_cpuimx27_init(void)
-{
-        imx27_soc_init();
-
-        mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
-                ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
-
-        imx27_add_imx_uart0(&uart_pdata);
-
-        imx27_add_mxc_nand(&cpuimx27_nand_board_info);
-
-        i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
-                                ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
-
-        imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
-
-        imx27_add_fec(NULL);
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt();
-        imx27_add_mxc_w1();
-
-#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
-        /* SDHC2 can be used for Wifi */
-        imx27_add_mxc_mmc(1, NULL);
-#endif
-#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
-        /* in which case UART4 is also used for Bluetooth */
-        imx27_add_imx_uart3(&uart_pdata);
-#endif
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-        serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
-        serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
-        serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
-        serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
-        platform_device_register(&serial_device);
-#endif
-
-        if (otg_mode_host) {
-                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                                ULPI_OTG_DRVVBUS_EXT);
-                if (otg_pdata.otg)
-                        imx27_add_mxc_ehci_otg(&otg_pdata);
-        } else {
-                imx27_add_fsl_usb2_udc(&otg_device_pdata);
-        }
-
-        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS_EXT);
-        if (usbh2_pdata.otg)
-                imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-
-#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
-        eukrea_mbimx27_baseboard_init();
-#endif
-}
-
-static void __init eukrea_cpuimx27_timer_init(void)
-{
-        mx27_clocks_init(26000000);
-}
-
-MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
-        .atag_offset = 0x100,
-        .map_io = mx27_map_io,
-        .init_early = imx27_init_early,
-        .init_irq = mx27_init_irq,
-        .init_time      = eukrea_cpuimx27_timer_init,
-        .init_machine = eukrea_cpuimx27_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c
index c77deb3f0893..2c5fcaf8675b 100644
--- a/arch/arm/mach-imx/mach-imx51.c
+++ b/arch/arm/mach-imx/mach-imx51.c
@@ -51,7 +51,7 @@ static void __init imx51_ipu_mipi_setup(void)
 
 static void __init imx51_dt_init(void)
 {
-        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+        struct platform_device_info devinfo = { .name = "cpufreq-dt", };
 
         mxc_arch_reset_init_dt();
         imx51_ipu_mipi_setup();
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 673a734165ba..3de3b7369aef 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -42,6 +42,9 @@ static void __init imx6sx_init_irq(void)
 static void __init imx6sx_init_late(void)
 {
         imx6q_cpuidle_init();
+
+        if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
+                platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
 }
 
 static const char * const imx6sx_dt_compat[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
deleted file mode 100644
index 77fda3de4290..000000000000
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * arch/arm/mach-imx/mach-mx1ads.c
- *
- * Initially based on:
- *      linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
- *      Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/i2c.h>
-#include <linux/i2c/pcf857x.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx1.h"
-#include "hardware.h"
-#include "iomux-mx1.h"
-
-static const int mx1ads_pins[] __initconst = {
-        /* UART1 */
-        PC9_PF_UART1_CTS,
-        PC10_PF_UART1_RTS,
-        PC11_PF_UART1_TXD,
-        PC12_PF_UART1_RXD,
-        /* UART2 */
-        PB28_PF_UART2_CTS,
-        PB29_PF_UART2_RTS,
-        PB30_PF_UART2_TXD,
-        PB31_PF_UART2_RXD,
-        /* I2C */
-        PA15_PF_I2C_SDA,
-        PA16_PF_I2C_SCL,
-        /* SPI */
-        PC13_PF_SPI1_SPI_RDY,
-        PC14_PF_SPI1_SCLK,
-        PC15_PF_SPI1_SS,
-        PC16_PF_SPI1_MISO,
-        PC17_PF_SPI1_MOSI,
-};
-
-/*
- * UARTs platform data
- */
-
-static const struct imxuart_platform_data uart0_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-       
-static const struct imxuart_platform_data uart1_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/*
- * Physmap flash
- */
-
-static const struct physmap_flash_data mx1ads_flash_data __initconst = {
-        .width          = 4,            /* bankwidth in bytes */
-};
-
-static const struct resource flash_resource __initconst = {
-        .start  = MX1_CS0_PHYS,
-        .end    = MX1_CS0_PHYS + SZ_32M - 1,
-        .flags  = IORESOURCE_MEM,
-};
-
-/*
- * I2C
- */
-static struct pcf857x_platform_data pcf857x_data[] = {
-        {
-                .gpio_base = 4 * 32,
-        }, {
-                .gpio_base = 4 * 32 + 16,
-        }
-};
-
-static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static struct i2c_board_info mx1ads_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pcf8575", 0x22),
-                .platform_data = &pcf857x_data[0],
-        }, {
-                I2C_BOARD_INFO("pcf8575", 0x24),
-                .platform_data = &pcf857x_data[1],
-        },
-};
-
-/*
- * Board init
- */
-static void __init mx1ads_init(void)
-{
-        imx1_soc_init();
-
-        mxc_gpio_setup_multiple_pins(mx1ads_pins,
-                ARRAY_SIZE(mx1ads_pins), "mx1ads");
-
-        /* UART */
-        imx1_add_imx_uart0(&uart0_pdata);
-        imx1_add_imx_uart1(&uart1_pdata);
-
-        /* Physmap flash */
-        platform_device_register_resndata(NULL, "physmap-flash", 0,
-                        &flash_resource, 1,
-                        &mx1ads_flash_data, sizeof(mx1ads_flash_data));
-
-        /* I2C */
-        i2c_register_board_info(0, mx1ads_i2c_devices,
-                                ARRAY_SIZE(mx1ads_i2c_devices));
-
-        imx1_add_imx_i2c(&mx1ads_i2c_data);
-}
-
-static void __init mx1ads_timer_init(void)
-{
-        mx1_clocks_init(32000);
-}
-
-MACHINE_START(MX1ADS, "Freescale MX1ADS")
-        /* Maintainer: Sascha Hauer, Pengutronix */
-        .atag_offset = 0x100,
-        .map_io = mx1_map_io,
-        .init_early = imx1_init_early,
-        .init_irq = mx1_init_irq,
-        .init_time      = mx1ads_timer_init,
-        .init_machine = mx1ads_init,
-        .restart        = mxc_restart,
-MACHINE_END
-
-MACHINE_START(MXLADS, "Freescale MXLADS")
-        .atag_offset = 0x100,
-        .map_io = mx1_map_io,
-        .init_early = imx1_init_early,
-        .init_irq = mx1_init_irq,
-        .init_time      = mx1ads_timer_init,
-        .init_machine = mx1ads_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 453f41a2c5a9..65a0dc06a97c 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -307,7 +307,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
         ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
                                  ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
         if (ret) {
-                pr_warning("Unable to request the SD/MMC GPIOs.\n");
+                pr_warn("Unable to request the SD/MMC GPIOs.\n");
                 return ret;
         }
 
@@ -316,7 +316,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
                           IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
                           "sdhc1-detect", data);
         if (ret) {
-                pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
+                pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
                 goto gpio_free;
         }
 
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 57eac6f45fab..4822a1738de4 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -270,7 +270,7 @@ static void __init mx31lite_init(void)
         /* SMSC9117 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
         if (ret)
-                pr_warning("could not get LAN irq gpio\n");
+                pr_warn("could not get LAN irq gpio\n");
         else {
                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
                 smsc911x_resources[1].start =
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
deleted file mode 100644
index 0b5d1ca31b9f..000000000000
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/pca953x.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-
-static const int mxt_td60_pins[] __initconst = {
-        /* UART0 */
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        PE14_PF_UART1_CTS,
-        PE15_PF_UART1_RTS,
-        /* UART1 */
-        PE3_PF_UART2_CTS,
-        PE4_PF_UART2_RTS,
-        PE6_PF_UART2_TXD,
-        PE7_PF_UART2_RXD,
-        /* UART2 */
-        PE8_PF_UART3_TXD,
-        PE9_PF_UART3_RXD,
-        PE10_PF_UART3_CTS,
-        PE11_PF_UART3_RTS,
-        /* FEC */
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN,
-        /* I2C1 */
-        PD17_PF_I2C_DATA,
-        PD18_PF_I2C_CLK,
-        /* I2C2 */
-        PC5_PF_I2C2_SDA,
-        PC6_PF_I2C2_SCL,
-        /* FB */
-        PA5_PF_LSCLK,
-        PA6_PF_LD0,
-        PA7_PF_LD1,
-        PA8_PF_LD2,
-        PA9_PF_LD3,
-        PA10_PF_LD4,
-        PA11_PF_LD5,
-        PA12_PF_LD6,
-        PA13_PF_LD7,
-        PA14_PF_LD8,
-        PA15_PF_LD9,
-        PA16_PF_LD10,
-        PA17_PF_LD11,
-        PA18_PF_LD12,
-        PA19_PF_LD13,
-        PA20_PF_LD14,
-        PA21_PF_LD15,
-        PA22_PF_LD16,
-        PA23_PF_LD17,
-        PA25_PF_CLS,
-        PA27_PF_SPL_SPR,
-        PA28_PF_HSYNC,
-        PA29_PF_VSYNC,
-        PA30_PF_CONTRAST,
-        PA31_PF_OE_ACD,
-        /* OWIRE */
-        PE16_AF_OWIRE,
-        /* SDHC1*/
-        PE18_PF_SD1_D0,
-        PE19_PF_SD1_D1,
-        PE20_PF_SD1_D2,
-        PE21_PF_SD1_D3,
-        PE22_PF_SD1_CMD,
-        PE23_PF_SD1_CLK,
-        PF8_AF_ATA_IORDY,
-        /* SDHC2*/
-        PB4_PF_SD2_D0,
-        PB5_PF_SD2_D1,
-        PB6_PF_SD2_D2,
-        PB7_PF_SD2_D3,
-        PB8_PF_SD2_CMD,
-        PB9_PF_SD2_CLK,
-};
-
-static const struct mxc_nand_platform_data
-mxt_td60_nand_board_info __initconst = {
-        .width = 1,
-        .hw_ecc = 1,
-};
-
-static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
-        .bitrate = 100000,
-};
-
-/* PCA9557 */
-static int mxt_td60_pca9557_setup(struct i2c_client *client,
-                                unsigned gpio_base, unsigned ngpio,
-                                void *context)
-{
-        static int mxt_td60_gpio_value[] = {
-                -1, -1, -1, -1, -1, -1, -1, 1
-        };
-        int n;
-
-        for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
-                gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
-                if (mxt_td60_gpio_value[n] < 0)
-                        gpio_direction_input(gpio_base + n);
-                else
-                        gpio_direction_output(gpio_base + n,
-                                                mxt_td60_gpio_value[n]);
-                gpio_export(gpio_base + n, 0);
-        }
-
-        return 0;
-}
-
-static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
-        .gpio_base      = 240, /* place PCA9557 after all MX27 gpio pins */
-        .invert         = 0, /* Do not invert */
-        .setup          = mxt_td60_pca9557_setup,
-};
-
-static struct i2c_board_info mxt_td60_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pca9557", 0x18),
-                .platform_data = &mxt_td60_pca9557_pdata,
-        },
-};
-
-static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
-        .bitrate = 100000,
-};
-
-static struct i2c_board_info mxt_td60_i2c2_devices[] = {
-};
-
-static struct imx_fb_videomode mxt_td60_modes[] = {
-        {
-                .mode = {
-                        .name           = "Chimei LW700AT9003",
-                        .refresh        = 60,
-                        .xres           = 800,
-                        .yres           = 480,
-                        .pixclock       = 30303,
-                        .hsync_len      = 64,
-                        .left_margin    = 0x67,
-                        .right_margin   = 0x68,
-                        .vsync_len      = 16,
-                        .upper_margin   = 0x0f,
-                        .lower_margin   = 0x0f,
-                },
-                .bpp            = 16,
-                .pcr            = 0xFA208B83,
-        },
-};
-
-static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
-        .mode = mxt_td60_modes,
-        .num_modes = ARRAY_SIZE(mxt_td60_modes),
-
-        /*
-         * - HSYNC active high
-         * - VSYNC active high
-         * - clk notenabled while idle
-         * - clock inverted
-         * - data not inverted
-         * - data enable low active
-         * - enable sharp mode
-         */
-        .pwmr           = 0x00A903FF,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00020010,
-};
-
-static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
-                                void *data)
-{
-        return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
-                           IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
-}
-
-static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
-{
-        free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
-}
-
-static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
-        .init = mxt_td60_sdhc1_init,
-        .exit = mxt_td60_sdhc1_exit,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static void __init mxt_td60_board_init(void)
-{
-        imx27_soc_init();
-
-        mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
-                        "MXT_TD60");
-
-        imx27_add_imx_uart0(&uart_pdata);
-        imx27_add_imx_uart1(&uart_pdata);
-        imx27_add_imx_uart2(&uart_pdata);
-        imx27_add_mxc_nand(&mxt_td60_nand_board_info);
-
-        i2c_register_board_info(0, mxt_td60_i2c_devices,
-                                ARRAY_SIZE(mxt_td60_i2c_devices));
-
-        i2c_register_board_info(1, mxt_td60_i2c2_devices,
-                                ARRAY_SIZE(mxt_td60_i2c2_devices));
-
-        imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
-        imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
-        imx27_add_imx_fb(&mxt_td60_fb_data);
-        imx27_add_mxc_mmc(0, &sdhc1_pdata);
-        imx27_add_fec(NULL);
-}
-
-static void __init mxt_td60_timer_init(void)
-{
-        mx27_clocks_init(26000000);
-}
-
-MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
-        /* maintainer: Maxtrack Industrial */
-        .atag_offset = 0x100,
-        .map_io = mx27_map_io,
-        .init_early = imx27_init_early,
-        .init_irq = mx27_init_irq,
-        .init_time      = mxt_td60_timer_init,
-        .init_machine = mxt_td60_board_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 8eb1570f7851..6d879417db49 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -58,7 +58,7 @@ static int __init pcm037_variant_setup(char *str)
         if (!strcmp("eet", str))
                 pcm037_instance = PCM037_EET;
         else if (strcmp("pcm970", str))
-                pr_warning("Unknown pcm037 baseboard variant %s\n", str);
+                pr_warn("Unknown pcm037 baseboard variant %s\n", str);
 
         return 1;
 }
@@ -624,7 +624,7 @@ static void __init pcm037_init(void)
         /* LAN9217 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
         if (ret)
-                pr_warning("could not get LAN irq gpio\n");
+                pr_warn("could not get LAN irq gpio\n");
         else {
                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
                 smsc911x_resources[1].start =
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
deleted file mode 100644
index ee862ad6b6fc..000000000000
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
-#include <linux/io.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "board-pcm038.h"
-#include "common.h"
-#include "devices-imx27.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
-
-static const int pcm038_pins[] __initconst = {
-        /* UART1 */
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        PE14_PF_UART1_CTS,
-        PE15_PF_UART1_RTS,
-        /* UART2 */
-        PE3_PF_UART2_CTS,
-        PE4_PF_UART2_RTS,
-        PE6_PF_UART2_TXD,
-        PE7_PF_UART2_RXD,
-        /* UART3 */
-        PE8_PF_UART3_TXD,
-        PE9_PF_UART3_RXD,
-        PE10_PF_UART3_CTS,
-        PE11_PF_UART3_RTS,
-        /* FEC */
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN,
-        /* I2C2 */
-        PC5_PF_I2C2_SDA,
-        PC6_PF_I2C2_SCL,
-        /* SPI1 */
-        PD25_PF_CSPI1_RDY,
-        PD29_PF_CSPI1_SCLK,
-        PD30_PF_CSPI1_MISO,
-        PD31_PF_CSPI1_MOSI,
-        /* SSI1 */
-        PC20_PF_SSI1_FS,
-        PC21_PF_SSI1_RXD,
-        PC22_PF_SSI1_TXD,
-        PC23_PF_SSI1_CLK,
-        /* SSI4 */
-        PC16_PF_SSI4_FS,
-        PC17_PF_SSI4_RXD,
-        PC18_PF_SSI4_TXD,
-        PC19_PF_SSI4_CLK,
-        /* USB host */
-        PA0_PF_USBH2_CLK,
-        PA1_PF_USBH2_DIR,
-        PA2_PF_USBH2_DATA7,
-        PA3_PF_USBH2_NXT,
-        PA4_PF_USBH2_STP,
-        PD19_AF_USBH2_DATA4,
-        PD20_AF_USBH2_DATA3,
-        PD21_AF_USBH2_DATA6,
-        PD22_AF_USBH2_DATA0,
-        PD23_AF_USBH2_DATA2,
-        PD24_AF_USBH2_DATA1,
-        PD26_AF_USBH2_DATA5,
-};
-
-/*
- * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
- * 16 bit width
- */
-
-static struct platdata_mtd_ram pcm038_sram_data = {
-        .bankwidth = 2,
-};
-
-static struct resource pcm038_sram_resource = {
-        .start = MX27_CS1_BASE_ADDR,
-        .end   = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
-        .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm038_sram_mtd_device = {
-        .name = "mtd-ram",
-        .id = 0,
-        .dev = {
-                .platform_data = &pcm038_sram_data,
-        },
-        .num_resources = 1,
-        .resource = &pcm038_sram_resource,
-};
-
-/*
- * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
- * 16 bit width
- */
-static struct physmap_flash_data pcm038_flash_data = {
-        .width = 2,
-};
-
-static struct resource pcm038_flash_resource = {
-        .start = 0xc0000000,
-        .end   = 0xc1ffffff,
-        .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm038_nor_mtd_device = {
-        .name = "physmap-flash",
-        .id = 0,
-        .dev = {
-                .platform_data = &pcm038_flash_data,
-        },
-        .num_resources = 1,
-        .resource = &pcm038_flash_resource,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct mxc_nand_platform_data
-pcm038_nand_board_info __initconst = {
-        .width = 1,
-        .hw_ecc = 1,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
-        &pcm038_nor_mtd_device,
-        &pcm038_sram_mtd_device,
-};
-
-/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
- * setup other stuffs to access the sram. */
-static void __init pcm038_init_sram(void)
-{
-        __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1)));
-        __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1)));
-        __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1)));
-}
-
-static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
-        .bitrate = 100000,
-};
-
-static struct at24_platform_data board_eeprom = {
-        .byte_len = 4096,
-        .page_size = 32,
-        .flags = AT24_FLAG_ADDR16,
-};
-
-static struct i2c_board_info pcm038_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
-                .platform_data = &board_eeprom,
-        }, {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        }, {
-                I2C_BOARD_INFO("lm75", 0x4a),
-        }
-};
-
-static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
-
-static const struct spi_imx_master pcm038_spi0_data __initconst = {
-        .chipselect = pcm038_spi_cs,
-        .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
-};
-
-static struct regulator_consumer_supply sdhc1_consumers[] = {
-        {
-                .dev_name = "imx21-mmc.1",
-                .supply = "sdhc_vcc",
-        },
-};
-
-static struct regulator_init_data sdhc1_data = {
-        .constraints = {
-                .min_uV = 3000000,
-                .max_uV = 3400000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-                .valid_modes_mask = REGULATOR_MODE_NORMAL |
-                        REGULATOR_MODE_FAST,
-                .always_on = 0,
-                .boot_on = 0,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers),
-        .consumer_supplies = sdhc1_consumers,
-};
-
-static struct regulator_consumer_supply cam_consumers[] = {
-        {
-                .dev_name = NULL,
-                .supply = "imx_cam_vcc",
-        },
-};
-
-static struct regulator_init_data cam_data = {
-        .constraints = {
-                .min_uV = 3000000,
-                .max_uV = 3400000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-                .valid_modes_mask = REGULATOR_MODE_NORMAL |
-                        REGULATOR_MODE_FAST,
-                .always_on = 0,
-                .boot_on = 0,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
-        .consumer_supplies = cam_consumers,
-};
-
-static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
-        {
-                .id = MC13783_REG_VCAM,
-                .init_data = &cam_data,
-        }, {
-                .id = MC13783_REG_VMMC1,
-                .init_data = &sdhc1_data,
-        },
-};
-
-static struct mc13xxx_platform_data pcm038_pmic = {
-        .regulators = {
-                .regulators = pcm038_regulators,
-                .num_regulators = ARRAY_SIZE(pcm038_regulators),
-        },
-        .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
-};
-
-static struct spi_board_info pcm038_spi_board_info[] __initdata = {
-        {
-                .modalias = "mc13783",
-                /* irq number is run-time assigned */
-                .max_speed_hz = 300000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .platform_data = &pcm038_pmic,
-                .mode = SPI_CS_HIGH,
-        }
-};
-
-static int pcm038_usbh2_init(struct platform_device *pdev)
-{
-        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
-                        MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
-        .init   = pcm038_usbh2_init,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void __init pcm038_init(void)
-{
-        imx27_soc_init();
-
-        mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
-                        "PCM038");
-
-        pcm038_init_sram();
-
-        imx27_add_imx_uart0(&uart_pdata);
-        imx27_add_imx_uart1(&uart_pdata);
-        imx27_add_imx_uart2(&uart_pdata);
-
-        mxc_gpio_mode(PE16_AF_OWIRE);
-        imx27_add_mxc_nand(&pcm038_nand_board_info);
-
-        /* only the i2c master 1 is used on this CPU card */
-        i2c_register_board_info(1, pcm038_i2c_devices,
-                                ARRAY_SIZE(pcm038_i2c_devices));
-
-        imx27_add_imx_i2c(1, &pcm038_i2c1_data);
-
-        /* PE18 for user-LED D40 */
-        mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
-
-        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-
-        /* MC13783 IRQ */
-        mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
-
-        imx27_add_spi_imx0(&pcm038_spi0_data);
-        pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
-        spi_register_board_info(pcm038_spi_board_info,
-                                ARRAY_SIZE(pcm038_spi_board_info));
-
-        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-
-        imx27_add_fec(NULL);
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt();
-        imx27_add_mxc_w1();
-
-#ifdef CONFIG_MACH_PCM970_BASEBOARD
-        pcm970_baseboard_init();
-#endif
-}
-
-static void __init pcm038_timer_init(void)
-{
-        mx27_clocks_init(26000000);
-}
-
-MACHINE_START(PCM038, "phyCORE-i.MX27")
-        .atag_offset = 0x100,
-        .map_io = mx27_map_io,
-        .init_early = imx27_init_early,
-        .init_irq = mx27_init_irq,
-        .init_time      = pcm038_timer_init,
-        .init_machine = pcm038_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index a39b69ef4301..17a41ca65acf 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -43,6 +43,8 @@
 #define IMX_CHIP_REVISION_1_1           0x11
 #define IMX_CHIP_REVISION_1_2           0x12
 #define IMX_CHIP_REVISION_1_3           0x13
+#define IMX_CHIP_REVISION_1_4           0x14
+#define IMX_CHIP_REVISION_1_5           0x15
 #define IMX_CHIP_REVISION_2_0           0x20
 #define IMX_CHIP_REVISION_2_1           0x21
 #define IMX_CHIP_REVISION_2_2           0x22
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
deleted file mode 100644
index 51c608234089..000000000000
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/can/platform/sja1000.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-
-static const int pcm970_pins[] __initconst = {
-        /* SDHC */
-        PB4_PF_SD2_D0,
-        PB5_PF_SD2_D1,
-        PB6_PF_SD2_D2,
-        PB7_PF_SD2_D3,
-        PB8_PF_SD2_CMD,
-        PB9_PF_SD2_CLK,
-        /* display */
-        PA5_PF_LSCLK,
-        PA6_PF_LD0,
-        PA7_PF_LD1,
-        PA8_PF_LD2,
-        PA9_PF_LD3,
-        PA10_PF_LD4,
-        PA11_PF_LD5,
-        PA12_PF_LD6,
-        PA13_PF_LD7,
-        PA14_PF_LD8,
-        PA15_PF_LD9,
-        PA16_PF_LD10,
-        PA17_PF_LD11,
-        PA18_PF_LD12,
-        PA19_PF_LD13,
-        PA20_PF_LD14,
-        PA21_PF_LD15,
-        PA22_PF_LD16,
-        PA23_PF_LD17,
-        PA24_PF_REV,
-        PA25_PF_CLS,
-        PA26_PF_PS,
-        PA27_PF_SPL_SPR,
-        PA28_PF_HSYNC,
-        PA29_PF_VSYNC,
-        PA30_PF_CONTRAST,
-        PA31_PF_OE_ACD,
-        /*
-         * it seems the data line misses a pullup, so we must enable
-         * the internal pullup as a local workaround
-         */
-        PD17_PF_I2C_DATA | GPIO_PUEN,
-        PD18_PF_I2C_CLK,
-        /* Camera */
-        PB10_PF_CSI_D0,
-        PB11_PF_CSI_D1,
-        PB12_PF_CSI_D2,
-        PB13_PF_CSI_D3,
-        PB14_PF_CSI_D4,
-        PB15_PF_CSI_MCLK,
-        PB16_PF_CSI_PIXCLK,
-        PB17_PF_CSI_D5,
-        PB18_PF_CSI_D6,
-        PB19_PF_CSI_D7,
-        PB20_PF_CSI_VSYNC,
-        PB21_PF_CSI_HSYNC,
-};
-
-static int pcm970_sdhc2_get_ro(struct device *dev)
-{
-        return gpio_get_value(GPIO_PORTC + 28);
-}
-
-static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
-{
-        int ret;
-
-        ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
-                          IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
-        if (ret)
-                return ret;
-
-        ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
-        if (ret) {
-                free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
-                return ret;
-        }
-
-        gpio_direction_input(GPIO_PORTC + 28);
-
-        return 0;
-}
-
-static void pcm970_sdhc2_exit(struct device *dev, void *data)
-{
-        free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
-        gpio_free(GPIO_PORTC + 28);
-}
-
-static const struct imxmmc_platform_data sdhc_pdata __initconst = {
-        .get_ro = pcm970_sdhc2_get_ro,
-        .init = pcm970_sdhc2_init,
-        .exit = pcm970_sdhc2_exit,
-};
-
-static struct imx_fb_videomode pcm970_modes[] = {
-        {
-                .mode = {
-                        .name           = "Sharp-LQ035Q7",
-                        .refresh        = 60,
-                        .xres           = 240,
-                        .yres           = 320,
-                        .pixclock       = 188679, /* in ps (5.3MHz) */
-                        .hsync_len      = 7,
-                        .left_margin    = 5,
-                        .right_margin   = 16,
-                        .vsync_len      = 1,
-                        .upper_margin   = 7,
-                        .lower_margin   = 9,
-                },
-                /*
-                 * - HSYNC active high
-                 * - VSYNC active high
-                 * - clk notenabled while idle
-                 * - clock not inverted
-                 * - data not inverted
-                 * - data enable low active
-                 * - enable sharp mode
-                 */
-                .pcr            = 0xF00080C0,
-                .bpp            = 16,
-        }, {
-                .mode = {
-                        .name           = "TX090",
-                        .refresh        = 60,
-                        .xres           = 240,
-                        .yres           = 320,
-                        .pixclock       = 38255,
-                        .left_margin    = 144,
-                        .right_margin   = 0,
-                        .upper_margin   = 7,
-                        .lower_margin   = 40,
-                        .hsync_len      = 96,
-                        .vsync_len      = 1,
-                },
-                /*
-                 * - HSYNC active low (1 << 22)
-                 * - VSYNC active low (1 << 23)
-                 * - clk notenabled while idle
-                 * - clock not inverted
-                 * - data not inverted
-                 * - data enable low active
-                 * - enable sharp mode
-                 */
-                .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
-                .bpp = 32,
-        },
-};
-
-static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
-        .mode = pcm970_modes,
-        .num_modes = ARRAY_SIZE(pcm970_modes),
-
-        .pwmr           = 0x00A903FF,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00020010,
-};
-
-static struct resource pcm970_sja1000_resources[] = {
-        {
-                .start   = MX27_CS4_BASE_ADDR,
-                .end     = MX27_CS4_BASE_ADDR + 0x100 - 1,
-                .flags   = IORESOURCE_MEM,
-        }, {
-                /* irq number is run-time assigned */
-                .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
-        },
-};
-
-static struct sja1000_platform_data pcm970_sja1000_platform_data = {
-        .osc_freq       = 16000000,
-        .ocr            = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
-        .cdr            = CDR_CBP,
-};
-
-static struct platform_device pcm970_sja1000 = {
-        .name = "sja1000_platform",
-        .dev = {
-                .platform_data = &pcm970_sja1000_platform_data,
-        },
-        .resource = pcm970_sja1000_resources,
-        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
-};
-
-/*
- * system init for baseboard usage. Will be called by pcm038 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init pcm970_baseboard_init(void)
-{
-        mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
-                        "PCM970");
-
-        imx27_add_imx_fb(&pcm038_fb_data);
-        mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
-        imx27_add_mxc_mmc(1, &sdhc_pdata);
-        pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
-        pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
-        platform_device_register(&pcm970_sja1000);
-}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 5b57c17c06bd..771bd25c1025 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -20,8 +20,6 @@
 #include "common.h"
 #include "hardware.h"
 
-#define SCU_STANDBY_ENABLE      (1 << 5)
-
 u32 g_diag_reg;
 static void __iomem *scu_base;
 
@@ -45,14 +43,6 @@ void __init imx_scu_map_io(void)
         scu_base = IMX_IO_ADDRESS(base);
 }
 
-void imx_scu_standby_enable(void)
-{
-        u32 val = readl_relaxed(scu_base);
-
-        val |= SCU_STANDBY_ENABLE;
-        writel_relaxed(val, scu_base);
-}
-
 static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         imx_set_cpu_jump(cpu, v7_secondary_startup);
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 74b50f1982db..ca4ea2daf25b 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -173,6 +173,8 @@ ENTRY(imx6_suspend)
         ldr     r6, [r11, #0x0]
         ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
         ldr     r6, [r11, #0x0]
+        ldr     r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+        ldr     r6, [r11, #0x0]
 
         /* use r11 to store the IO address */
         ldr     r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bf92e5a351c0..15d18e198303 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -60,17 +60,22 @@
 #define MX2_TSTAT_CAPT          (1 << 1)
 #define MX2_TSTAT_COMP          (1 << 0)
 
-/* MX31, MX35, MX25, MX5 */
+/* MX31, MX35, MX25, MX5, MX6 */
 #define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
 #define V2_TCTL_CLK_IPG         (1 << 6)
 #define V2_TCTL_CLK_PER         (2 << 6)
+#define V2_TCTL_CLK_OSC_DIV8    (5 << 6)
 #define V2_TCTL_FRR             (1 << 9)
+#define V2_TCTL_24MEN           (1 << 10)
+#define V2_TPRER_PRE24M         12
 #define V2_IR                   0x0c
 #define V2_TSTAT                0x08
 #define V2_TSTAT_OF1            (1 << 0)
 #define V2_TCN                  0x24
 #define V2_TCMP                 0x10
 
+#define V2_TIMER_RATE_OSC_DIV8  3000000
+
 #define timer_is_v1()   (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 #define timer_is_v2()   (!timer_is_v1())
 
@@ -312,10 +317,22 @@ static void __init _mxc_timer_init(int irq,
         __raw_writel(0, timer_base + MXC_TCTL);
         __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
-        if (timer_is_v2())
-                tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
-        else
+        if (timer_is_v2()) {
+                tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
+                if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) {
+                        tctl_val |= V2_TCTL_CLK_OSC_DIV8;
+                        if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
+                                /* 24 / 8 = 3 MHz */
+                                __raw_writel(7 << V2_TPRER_PRE24M,
+                                        timer_base + MXC_TPRER);
+                                tctl_val |= V2_TCTL_24MEN;
+                        }
+                } else {
+                        tctl_val |= V2_TCTL_CLK_PER;
+                }
+        } else {
                 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
+        }
 
         __raw_writel(tctl_val, timer_base + MXC_TCTL);
 
@@ -349,9 +366,13 @@ static void __init mxc_timer_init_dt(struct device_node *np)
         WARN_ON(!timer_base);
         irq = irq_of_parse_and_map(np, 0);
 
-        clk_per = of_clk_get_by_name(np, "per");
         clk_ipg = of_clk_get_by_name(np, "ipg");
 
+        /* Try osc_per first, and fall back to per otherwise */
+        clk_per = of_clk_get_by_name(np, "osc_per");
+        if (IS_ERR(clk_per))
+                clk_per = of_clk_get_by_name(np, "per");
+
         _mxc_timer_init(irq, clk_per, clk_ipg);
 }
 CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 1d4f384ca773..4de65eeda1eb 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -141,8 +141,7 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
                         while (stat) {
                                 handled = 1;
                                 irqofs = fls(stat) - 1;
-                                handle_IRQ(irq_find_mapping(domain,
-                                                irqofs + i * 32), regs);
+                                handle_domain_irq(domain, irqofs + i * 32, regs);
                                 stat &= ~(1 << irqofs);
                         }
                 }
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 3ce880729cff..38b0da300dd5 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -20,10 +20,13 @@
 #include <linux/mm.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/amba/mmci.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/slab.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/gpio/machine.h>
 
 #include <asm/sizes.h>
 #include "lm.h"
@@ -52,6 +55,13 @@ void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
 EXPORT_SYMBOL(impd1_tweak_control);
 
 /*
+ * MMC support
+ */
+static struct mmci_platform_data mmc_data = {
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+};
+
+/*
  * CLCD support
  */
 #define PANEL           PROSPECTOR
@@ -291,6 +301,7 @@ static struct impd1_device impd1_devs[] = {
                 .offset = 0x00700000,
                 .irq    = { 7, 8 },
                 .id     = 0x00041181,
+                .platform_data = &mmc_data,
         }, {
                 .offset = 0x00800000,
                 .irq    = { 9 },
@@ -372,6 +383,43 @@ static int __init_refok impd1_probe(struct lm_device *dev)
 
                 pc_base = dev->resource.start + idev->offset;
                 snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
+
+                /* Add GPIO descriptor lookup table for the PL061 block */
+                if (idev->offset == 0x00400000) {
+                        struct gpiod_lookup_table *lookup;
+                        char *chipname;
+                        char *mmciname;
+
+                        lookup = devm_kzalloc(&dev->dev,
+                                              sizeof(*lookup) + 3 * sizeof(struct gpiod_lookup),
+                                              GFP_KERNEL);
+                        chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL);
+                        mmciname = kasprintf(GFP_KERNEL, "lm%x:00700", dev->id);
+                        lookup->dev_id = mmciname;
+                        /*
+                         * Offsets on GPIO block 1:
+                         * 3 = MMC WP (write protect)
+                         * 4 = MMC CD (card detect)
+                         *
+                         * Offsets on GPIO block 2:
+                         * 0 = Up key
+                         * 1 = Down key
+                         * 2 = Left key
+                         * 3 = Right key
+                         * 4 = Key lower left
+                         * 5 = Key lower right
+                         */
+                        /* We need the two MMCI GPIO entries */
+                        lookup->table[0].chip_label = chipname;
+                        lookup->table[0].chip_hwnum = 3;
+                        lookup->table[0].con_id = "wp";
+                        lookup->table[1].chip_label = chipname;
+                        lookup->table[1].chip_hwnum = 4;
+                        lookup->table[1].con_id = "cd";
+                        lookup->table[1].flags = GPIO_ACTIVE_LOW;
+                        gpiod_add_lookup_table(lookup);
+                }
+
                 d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K,
                                             irq1, irq2,
                                             idev->platform_data, idev->id,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 05e1f73a1e8d..c186a17c2cff 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -660,6 +660,7 @@ static void __init pci_v3_preinit(void)
 {
         unsigned long flags;
         unsigned int temp;
+        phys_addr_t io_address = pci_pio_to_address(io_mem.start);
 
         pcibios_min_mem = 0x00100000;
 
@@ -701,7 +702,7 @@ static void __init pci_v3_preinit(void)
         /*
          * Setup window 2 - PCI IO
          */
-        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
+        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
                         V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
 
@@ -742,6 +743,7 @@ static void __init pci_v3_preinit(void)
 static void __init pci_v3_postinit(void)
 {
         unsigned int pci_cmd;
+        phys_addr_t io_address = pci_pio_to_address(io_mem.start);
 
         pci_cmd = PCI_COMMAND_MEMORY |
                   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
@@ -758,7 +760,7 @@ static void __init pci_v3_postinit(void)
                        "interrupt: %d\n", ret);
 #endif
 
-        register_isa_ports(non_mem.start, io_mem.start, 0);
+        register_isa_ports(non_mem.start, io_address, 0);
 }
 
 /*
@@ -867,33 +869,32 @@ static int __init pci_v3_probe(struct platform_device *pdev)
 
         for_each_of_pci_range(&parser, &range) {
                 if (!range.flags) {
-                        of_pci_range_to_resource(&range, np, &conf_mem);
+                        ret = of_pci_range_to_resource(&range, np, &conf_mem);
                         conf_mem.name = "PCIv3 config";
                 }
                 if (range.flags & IORESOURCE_IO) {
-                        of_pci_range_to_resource(&range, np, &io_mem);
+                        ret = of_pci_range_to_resource(&range, np, &io_mem);
                         io_mem.name = "PCIv3 I/O";
                 }
                 if ((range.flags & IORESOURCE_MEM) &&
                         !(range.flags & IORESOURCE_PREFETCH)) {
                         non_mem_pci = range.pci_addr;
                         non_mem_pci_sz = range.size;
-                        of_pci_range_to_resource(&range, np, &non_mem);
+                        ret = of_pci_range_to_resource(&range, np, &non_mem);
                         non_mem.name = "PCIv3 non-prefetched mem";
                 }
                 if ((range.flags & IORESOURCE_MEM) &&
                         (range.flags & IORESOURCE_PREFETCH)) {
                         pre_mem_pci = range.pci_addr;
                         pre_mem_pci_sz = range.size;
-                        of_pci_range_to_resource(&range, np, &pre_mem);
+                        ret = of_pci_range_to_resource(&range, np, &pre_mem);
                         pre_mem.name = "PCIv3 prefetched mem";
                 }
-        }
 
-        if (!conf_mem.start || !io_mem.start ||
-            !non_mem.start || !pre_mem.start) {
-                dev_err(&pdev->dev, "missing ranges in device node\n");
-                return -EINVAL;
+                if (ret < 0) {
+                        dev_err(&pdev->dev, "missing ranges in device node\n");
+                        return ret;
+                }
         }
 
         pci_v3.map_irq = of_irq_parse_and_map_pci;
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index de03620d7fa7..716e83eb1db8 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -57,20 +57,6 @@ int clk_is_sysclk_mainosc(void)
 }
 
 /*
- * System reset via the watchdog timer
- */
-static void lpc32xx_watchdog_reset(void)
-{
-        /* Make sure WDT clocks are enabled */
-        __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
-                LPC32XX_CLKPWR_TIMER_CLK_CTRL);
-
-        /* Instant assert of RESETOUT_N with pulse length 1mS */
-        __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
-        __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
-}
-
-/*
  * Detects and returns IRAM size for the device variation
  */
 #define LPC32XX_IRAM_BANK_SIZE SZ_128K
@@ -210,16 +196,13 @@ void __init lpc32xx_map_io(void)
 
 void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
-        switch (mode) {
-        case REBOOT_SOFT:
-        case REBOOT_HARD:
-                lpc32xx_watchdog_reset();
-                break;
+        /* Make sure WDT clocks are enabled */
+        __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+                LPC32XX_CLKPWR_TIMER_CLK_CTRL);
 
-        default:
-                /* Do nothing */
-                break;
-        }
+        /* Instant assert of RESETOUT_N with pulse length 1mS */
+        __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
+        __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
 
         /* Wait for watchdog to reset system */
         while (1)
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
new file mode 100644
index 000000000000..2c1154e1794a
--- /dev/null
+++ b/arch/arm/mach-meson/Kconfig
@@ -0,0 +1,13 @@
+menuconfig ARCH_MESON
+        bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
+        select GENERIC_IRQ_CHIP
+        select ARM_GIC
+
+if ARCH_MESON
+
+config MACH_MESON6
+        bool "Amlogic Meson6 (8726MX) SoCs support"
+        default ARCH_MESON
+        select MESON6_TIMER
+
+endif
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
new file mode 100644
index 000000000000..9d7380eeeedd
--- /dev/null
+++ b/arch/arm/mach-meson/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_MESON) += meson.o
diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
new file mode 100644
index 000000000000..5ee064f5a89f
--- /dev/null
+++ b/arch/arm/mach-meson/meson.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+static const char * const m6_common_board_compat[] = {
+        "amlogic,meson6",
+        NULL,
+};
+
+DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
+        .dt_compat      = m6_common_board_compat,
+MACHINE_END
+
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
deleted file mode 100644
index 873c3ca3cd7e..000000000000
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* linux/arch/arm/mach-msm/board-mahimahi.c
- *
- * Copyright (C) 2009 Google, Inc.
- * Copyright (C) 2009 HTC Corporation.
- * Author: Dima Zavin <dima@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/memblock.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-
-#include <mach/hardware.h>
-
-#include "board-mahimahi.h"
-#include "devices.h"
-#include "proc_comm.h"
-#include "common.h"
-
-static uint debug_uart;
-
-module_param_named(debug_uart, debug_uart, uint, 0);
-
-static struct platform_device *devices[] __initdata = {
-#if !defined(CONFIG_MSM_SERIAL_DEBUGGER)
-        &msm_device_uart1,
-#endif
-        &msm_device_uart_dm1,
-        &msm_device_nand,
-};
-
-static void __init mahimahi_init(void)
-{
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init mahimahi_fixup(struct tag *tags, char **cmdline)
-{
-        memblock_add(PHYS_OFFSET, 219*SZ_1M);
-        memblock_add(MSM_HIGHMEM_BASE, MSM_HIGHMEM_SIZE);
-}
-
-static void __init mahimahi_map_io(void)
-{
-        msm_map_common_io();
-        msm_clock_init();
-}
-
-static void __init mahimahi_init_late(void)
-{
-        smd_debugfs_init();
-}
-
-void msm_timer_init(void);
-
-MACHINE_START(MAHIMAHI, "mahimahi")
-        .atag_offset    = 0x100,
-        .fixup          = mahimahi_fixup,
-        .map_io         = mahimahi_map_io,
-        .init_irq       = msm_init_irq,
-        .init_machine   = mahimahi_init,
-        .init_late      = mahimahi_init_late,
-        .init_time      = msm_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 245884319d2e..8f5ecdc4f3ce 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -124,7 +124,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
 static struct platform_device *devices[] __initdata = {
         &msm_clock_7x30,
         &msm_device_gpio_7x30,
-#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
+#if defined(CONFIG_SERIAL_MSM)
         &msm_device_uart2,
 #endif
         &msm_device_smd,
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 2c25050209ce..722ad63b7edc 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -94,7 +94,7 @@ static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
         }
 
 static struct msm_gpio_chip msm_gpio_banks[] = {
-#if defined(CONFIG_MSM_DEBUG_UART1)
+#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9a00000)
         /* H2W pins <-> UART1 */
         TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x40),
 #else
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index f72b07de2152..ba3edd3a46cb 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -88,7 +88,7 @@ static void __init trout_map_io(void)
         msm_map_common_io();
         iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
 
-#ifdef CONFIG_MSM_DEBUG_UART3
+#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9c00000)
         /* route UART3 to the "H2W" extended usb connector */
         writeb(0x80, TROUT_CPLD_BASE + 0x00);
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 34e09474636d..b042dca1f633 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -57,8 +57,7 @@ static struct map_desc msm_io_desc[] __initdata = {
                 .length =   MSM_SHARED_RAM_SIZE,
                 .type =     MT_DEVICE,
         },
-#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
-                defined(CONFIG_DEBUG_MSM_UART3)
+#if defined(CONFIG_DEBUG_MSM_UART)
         {
                 /* Must be last: virtual and pfn filled in by debug_ll_addr() */
                 .length = SZ_4K,
@@ -76,8 +75,7 @@ void __init msm_map_common_io(void)
          * pages are peripheral interface or not.
          */
         asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
-#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
-                defined(CONFIG_DEBUG_MSM_UART3)
+#if defined(CONFIG_DEBUG_MSM_UART)
 #ifdef CONFIG_MMU
         debug_ll_addr(&msm_io_desc[size - 1].pfn,
                       &msm_io_desc[size - 1].virtual);
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 8a70a51533fd..bbd8664d1bac 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -644,7 +644,7 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
                 }
         }
 
-        platform_device_register_simple("cpufreq-generic", -1, NULL, 0);
+        platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e7189dcc9309..f4d06aea8460 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,9 +1,6 @@
 menu "TI OMAP/AM/DM/DRA Family"
         depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
 
-config ARCH_OMAP
-        bool
-
 config ARCH_OMAP2
         bool "TI OMAP2"
         depends on ARCH_MULTI_V6
@@ -25,7 +22,6 @@ config ARCH_OMAP4
         bool "TI OMAP4"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
-        select ARCH_HAS_OPP
         select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
         select ARM_CPU_SUSPEND if PM
         select ARM_ERRATA_720789
@@ -44,7 +40,6 @@ config SOC_OMAP5
         bool "TI OMAP5"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
-        select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
         select ARM_GIC
         select HAVE_ARM_SCU if SMP
@@ -56,14 +51,12 @@ config SOC_AM33XX
         bool "TI AM33XX"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
-        select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
 
 config SOC_AM43XX
         bool "TI AM43x"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
-        select ARCH_HAS_OPP
         select ARM_GIC
         select MACH_OMAP_GENERIC
         select MIGHT_HAVE_CACHE_L2X0
@@ -72,7 +65,6 @@ config SOC_DRA7XX
         bool "TI DRA7XX"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
-        select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
         select ARM_GIC
         select HAVE_ARM_ARCH_TIMER
@@ -91,6 +83,7 @@ config ARCH_OMAP2PLUS
         select PINCTRL
         select SOC_BUS
         select TI_PRIV_EDMA
+        select OMAP_IRQCHIP
         help
           Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 69bbcba8842f..d9e94122073e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -10,7 +10,6 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
          common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
          omap_device.o sram.o drm.o
 
-omap-2-3-common                         = irq.o
 hwmod-common                            = omap_hwmod.o omap_hwmod_reset.o \
                                           omap_hwmod_common_data.o
 clock-common                            = clock.o clock_common_data.o \
@@ -20,7 +19,7 @@ secure-common				= omap-smc.o omap-secure.o
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
+obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common)
 obj-$(CONFIG_SOC_OMAP5)  += $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
@@ -87,9 +86,10 @@ ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_DRA7XX)                += omap-mpuss-lowpower.o
+omap-4-5-pm-common                      =  pm44xx.o omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-pm-common)
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-pm-common)
+obj-$(CONFIG_SOC_DRA7XX)                += $(omap-4-5-pm-common)
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 
 obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
@@ -102,7 +102,10 @@ endif
 
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+omap-4-5-idle-common                    =  cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-idle-common)
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-idle-common)
+obj-$(CONFIG_SOC_DRA7XX)                += $(omap-4-5-idle-common)
 endif
 
 # PRCM
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index d95d0ef1354a..d21a3048d06b 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -625,7 +625,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_3430sdp_init,
         .init_late      = omap3430_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 0d499a1878f6..212c3160de18 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -142,7 +142,6 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
         .map_io         = omap3_map_io,
         .init_early     = am35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = am3517_crane_init,
         .init_late      = am35xx_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4f9383cecf76..1c091b3fa312 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -366,7 +366,6 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
         .map_io         = omap3_map_io,
         .init_early     = am35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = am3517_evm_init,
         .init_late      = am35xx_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 018353d88b96..c6df8eec4553 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -766,7 +766,6 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = cm_t35_init,
         .init_late      = omap35xx_init_late,
         .init_time      = omap3_sync32k_timer_init,
@@ -779,7 +778,6 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
         .map_io         = omap3_map_io,
         .init_early     = omap3630_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = cm_t3730_init,
         .init_late     = omap3630_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 4eb5e6f2f7f5..8a2c1677964c 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -329,7 +329,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
         .map_io         = omap3_map_io,
         .init_early     = am35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = cm_t3517_init,
         .init_late      = am35xx_init_late,
         .init_time      = omap3_gptimer_timer_init,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index cdc4fb9960a9..d8e4f346936a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -647,7 +647,6 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = devkit8000_init,
         .init_late      = omap35xx_init_late,
         .init_time      = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index e87f2a83d6bf..2d245c2e641c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
         board_nand_data.nr_parts        = nr_parts;
         board_nand_data.devsize         = nand_type;
 
-        board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
+        board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
         gpmc_nand_init(&board_nand_data, gpmc_t);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 9480997ba616..608079a1aba6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -27,7 +27,7 @@
 #define gic_of_init             NULL
 #endif
 
-static struct of_device_id omap_dt_match_table[] __initdata = {
+static const struct of_device_id omap_dt_match_table[] __initconst = {
         { .compatible = "simple-bus", },
         { .compatible = "ti,omap-infra", },
         { }
@@ -43,7 +43,7 @@ static void __init omap_generic_init(void)
 }
 
 #ifdef CONFIG_SOC_OMAP2420
-static const char *omap242x_boards_compat[] __initconst = {
+static const char *const omap242x_boards_compat[] __initconst = {
         "ti,omap2420",
         NULL,
 };
@@ -52,8 +52,6 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap242x_map_io,
         .init_early     = omap2420_init_early,
-        .init_irq       = omap_intc_of_init,
-        .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .init_time      = omap2_sync32k_timer_init,
         .dt_compat      = omap242x_boards_compat,
@@ -62,7 +60,7 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_SOC_OMAP2430
-static const char *omap243x_boards_compat[] __initconst = {
+static const char *const omap243x_boards_compat[] __initconst = {
         "ti,omap2430",
         NULL,
 };
@@ -71,8 +69,6 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap243x_map_io,
         .init_early     = omap2430_init_early,
-        .init_irq       = omap_intc_of_init,
-        .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .init_time      = omap2_sync32k_timer_init,
         .dt_compat      = omap243x_boards_compat,
@@ -81,7 +77,7 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-static const char *omap3_boards_compat[] __initconst = {
+static const char *const omap3_boards_compat[] __initconst = {
         "ti,omap3430",
         "ti,omap3",
         NULL,
@@ -91,8 +87,6 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
-        .init_irq       = omap_intc_of_init,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .init_late      = omap3_init_late,
         .init_time      = omap3_sync32k_timer_init,
@@ -100,7 +94,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
         .restart        = omap3xxx_restart,
 MACHINE_END
 
-static const char *omap36xx_boards_compat[] __initconst = {
+static const char *const omap36xx_boards_compat[] __initconst = {
         "ti,omap36xx",
         NULL,
 };
@@ -109,8 +103,6 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3630_init_early,
-        .init_irq       = omap_intc_of_init,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .init_late      = omap3_init_late,
         .init_time      = omap3_sync32k_timer_init,
@@ -118,7 +110,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
         .restart        = omap3xxx_restart,
 MACHINE_END
 
-static const char *omap3_gp_boards_compat[] __initconst = {
+static const char *const omap3_gp_boards_compat[] __initconst = {
         "ti,omap3-beagle",
         "timll,omap3-devkit8000",
         NULL,
@@ -128,8 +120,6 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
-        .init_irq       = omap_intc_of_init,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .init_late      = omap3_init_late,
         .init_time      = omap3_secure_sync32k_timer_init,
@@ -137,7 +127,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
         .restart        = omap3xxx_restart,
 MACHINE_END
 
-static const char *am3517_boards_compat[] __initconst = {
+static const char *const am3517_boards_compat[] __initconst = {
         "ti,am3517",
         NULL,
 };
@@ -146,8 +136,6 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = am35xx_init_early,
-        .init_irq       = omap_intc_of_init,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .init_late      = omap3_init_late,
         .init_time      = omap3_gptimer_timer_init,
@@ -157,7 +145,7 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_SOC_AM33XX
-static const char *am33xx_boards_compat[] __initconst = {
+static const char *const am33xx_boards_compat[] __initconst = {
         "ti,am33xx",
         NULL,
 };
@@ -166,8 +154,6 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = am33xx_map_io,
         .init_early     = am33xx_init_early,
-        .init_irq       = omap_intc_of_init,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .init_late      = am33xx_init_late,
         .init_time      = omap3_gptimer_timer_init,
@@ -177,7 +163,7 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-static const char *omap4_boards_compat[] __initconst = {
+static const char *const omap4_boards_compat[] __initconst = {
         "ti,omap4460",
         "ti,omap4430",
         "ti,omap4",
@@ -199,7 +185,7 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_SOC_OMAP5
-static const char *omap5_boards_compat[] __initconst = {
+static const char *const omap5_boards_compat[] __initconst = {
         "ti,omap5432",
         "ti,omap5430",
         "ti,omap5",
@@ -221,7 +207,7 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_SOC_AM43XX
-static const char *am43_boards_compat[] __initconst = {
+static const char *const am43_boards_compat[] __initconst = {
         "ti,am4372",
         "ti,am43",
         NULL,
@@ -240,7 +226,9 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_SOC_DRA7XX
-static const char *dra74x_boards_compat[] __initconst = {
+static const char *const dra74x_boards_compat[] __initconst = {
+        "ti,am5728",
+        "ti,am5726",
         "ti,dra742",
         "ti,dra7",
         NULL,
@@ -259,7 +247,9 @@ DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
         .restart        = omap44xx_restart,
 MACHINE_END
 
-static const char *dra72x_boards_compat[] __initconst = {
+static const char *const dra72x_boards_compat[] __initconst = {
+        "ti,am5718",
+        "ti,am5716",
         "ti,dra722",
         NULL,
 };
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 44a59c3abfb0..c2975af4cd5d 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -422,7 +422,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_ldp_init,
         .init_late      = omap3430_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index aead77a4bc6d..97767a27ca9d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -33,6 +33,7 @@
 #include "mmc.h"
 #include "soc.h"
 #include "gpmc-onenand.h"
+#include "common-board-devices.h"
 
 #define TUSB6010_ASYNC_CS       1
 #define TUSB6010_SYNC_CS        4
@@ -568,29 +569,14 @@ static int n8x0_menelaus_late_init(struct device *dev)
 }
 #endif
 
-static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
+struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
         .late_init = n8x0_menelaus_late_init,
 };
 
-static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
-        {
-                I2C_BOARD_INFO("menelaus", 0x72),
-                .irq = 7 + OMAP_INTC_START,
-                .platform_data = &n8x0_menelaus_platform_data,
-        },
-};
-
-static struct aic3x_pdata n810_aic33_data __initdata = {
+struct aic3x_pdata n810_aic33_data __initdata = {
         .gpio_reset = 118,
 };
 
-static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
-        {
-                I2C_BOARD_INFO("tlv320aic3x", 0x18),
-                .platform_data = &n810_aic33_data,
-        },
-};
-
 static int __init n8x0_late_initcall(void)
 {
         if (!board_caps)
@@ -612,11 +598,5 @@ void * __init n8x0_legacy_init(void)
         board_check_revision();
         spi_register_board_info(n800_spi_board_info,
                                 ARRAY_SIZE(n800_spi_board_info));
-        i2c_register_board_info(0, n8x0_i2c_board_info_1,
-                                ARRAY_SIZE(n8x0_i2c_board_info_1));
-        if (board_is_n810())
-                i2c_register_board_info(1, n810_i2c_board_info_2,
-                                        ARRAY_SIZE(n810_i2c_board_info_2));
-
         return &mmc1_data;
 }
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index e2e52031f056..81de1c68b360 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -588,7 +588,6 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
         .map_io         = omap3_map_io,
         .init_early     = omap3_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap3_beagle_init,
         .init_late      = omap3_init_late,
         .init_time      = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index bab51e64c4b5..6049f60a8813 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -230,7 +230,6 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap3logic_init,
         .init_late      = omap35xx_init_late,
         .init_time      = omap3_sync32k_timer_init,
@@ -243,7 +242,6 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap3logic_init,
         .init_late      = omap35xx_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index cf18340eb3bb..f32201656cf3 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -624,7 +624,6 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap3pandora_init,
         .init_late      = omap35xx_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index a2e035e0792a..6311f4b1ee44 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -426,7 +426,6 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
         .map_io                 = omap3_map_io,
         .init_early             = omap35xx_init_early,
         .init_irq               = omap3_init_irq,
-        .handle_irq             = omap3_intc_handle_irq,
         .init_machine           = omap3_stalker_init,
         .init_late              = omap35xx_init_late,
         .init_time              = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 70b904c010c6..a01993e5500f 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -388,7 +388,6 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap3_touchbook_init,
         .init_late      = omap3430_init_late,
         .init_time      = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index f6d384111911..2dae6ccd39bb 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -564,7 +564,6 @@ MACHINE_START(OVERO, "Gumstix Overo")
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = overo_init,
         .init_late      = omap35xx_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index db168c9627a1..2d1e5a6beb85 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -134,7 +134,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
         .init_irq       = omap3_init_irq,
-        .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = rx51_init,
         .init_late      = omap3430_init_late,
         .init_time      = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index f338177e6900..07c88ae083fb 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -1,6 +1,8 @@
 #ifndef __OMAP_COMMON_BOARD_DEVICES__
 #define __OMAP_COMMON_BOARD_DEVICES__
 
+#include <sound/tlv320aic3x.h>
+#include <linux/mfd/menelaus.h>
 #include "twl-common.h"
 
 #define NAND_BLOCK_SIZE SZ_128K
@@ -12,4 +14,7 @@ void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
                        struct ads7846_platform_data *board_pdata);
 void *n8x0_legacy_init(void);
 
+extern struct menelaus_platform_data n8x0_menelaus_platform_data;
+extern struct aic3x_pdata n810_aic33_data;
+
 #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index dc571f1d3b8a..377eea849e7b 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -32,6 +32,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
 #include <linux/reboot.h>
+#include <linux/irqchip/irq-omap-intc.h>
 
 #include <asm/proc-fns.h>
 
@@ -60,7 +61,7 @@ static inline int omap3_pm_init(void)
 }
 #endif
 
-#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
 int omap4_pm_init(void);
 int omap4_pm_init_early(void);
 #else
@@ -210,18 +211,6 @@ extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
 extern struct device *omap4_get_dsp_device(void);
 
-void omap2_init_irq(void);
-void omap3_init_irq(void);
-void ti81xx_init_irq(void);
-extern int omap_irq_pending(void);
-void omap_intc_save_context(void);
-void omap_intc_restore_context(void);
-void omap3_intc_suspend(void);
-void omap3_intc_prepare_idle(void);
-void omap3_intc_resume_idle(void);
-void omap2_intc_handle_irq(struct pt_regs *regs);
-void omap3_intc_handle_irq(struct pt_regs *regs);
-void omap_intc_of_init(void);
 void omap_gic_of_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -229,16 +218,6 @@ extern void __iomem *omap4_get_l2cache_base(void);
 #endif
 
 struct device_node;
-#ifdef CONFIG_OF
-int __init intc_of_init(struct device_node *node,
-                             struct device_node *parent);
-#else
-int __init intc_of_init(struct device_node *node,
-                             struct device_node *parent)
-{
-        return 0;
-}
-#endif
 
 #ifdef CONFIG_SMP
 extern void __iomem *omap4_get_scu_base(void);
@@ -307,7 +286,7 @@ static inline void omap4_cpu_resume(void)
 
 #endif
 
-void pdata_quirks_init(struct of_device_id *);
+void pdata_quirks_init(const struct of_device_id *);
 void omap_auxdata_legacy_init(struct device *dev);
 void omap_pcs_legacy_init(int irq, void (*rearm)(void));
 
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index bf852d7ae951..7a050f9c37ff 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -544,7 +544,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
                         MAX_MODULE_SOFTRESET_WAIT, c);
 
         if (c == MAX_MODULE_SOFTRESET_WAIT)
-                pr_warning("dss_core: waiting for reset to finish failed\n");
+                pr_warn("dss_core: waiting for reset to finish failed\n");
         else
                 pr_debug("dss_core: softreset done\n");
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 8897ad7035fd..cb7764314f17 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -49,7 +49,8 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
                 return 0;
 
         /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
-        if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
+        if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
+            ecc_opt == OMAP_ECC_HAM1_CODE_SW)
                 return 1;
         else
                 return 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8bc13380f0a0..a4d52c42a438 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1207,8 +1207,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
                 }
         }
 
-        if ((p->wait_on_read || p->wait_on_write) &&
-            (p->wait_pin > gpmc_nr_waitpins)) {
+        if (p->wait_pin > gpmc_nr_waitpins) {
                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
                 return -EINVAL;
         }
@@ -1244,7 +1243,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
 }
 
 #ifdef CONFIG_OF
-static struct of_device_id gpmc_dt_ids[] = {
+static const struct of_device_id gpmc_dt_ids[] = {
         { .compatible = "ti,omap2420-gpmc" },
         { .compatible = "ti,omap2430-gpmc" },
         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
@@ -1288,8 +1287,8 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
                 p->wait_on_write = of_property_read_bool(np,
                                                          "gpmc,wait-on-write");
                 if (!p->wait_on_read && !p->wait_on_write)
-                        pr_warn("%s: read/write wait monitoring not enabled!\n",
-                                __func__);
+                        pr_debug("%s: rd/wr wait monitoring not enabled!\n",
+                                 __func__);
         }
 }
 
@@ -1403,8 +1402,11 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
                 return -ENODEV;
         }
-        if (!strcmp(s, "ham1") || !strcmp(s, "sw") ||
-                !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
+
+        if (!strcmp(s, "sw"))
+                gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
+        else if (!strcmp(s, "ham1") ||
+                 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
                 gpmc_nand_data->ecc_opt =
                                 OMAP_ECC_HAM1_CODE_HW;
         else if (!strcmp(s, "bch4"))
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index f78b4a161959..f3897d82e53e 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -67,8 +67,8 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
                           MAX_MODULE_SOFTRESET_WAIT, c);
 
         if (c == MAX_MODULE_SOFTRESET_WAIT)
-                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
-                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+                pr_warn("%s: %s: softreset failed (waited %d usec)\n",
+                        __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
         else
                 pr_debug("%s: %s: softreset in %d usec\n", __func__,
                          oh->name, c);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b456b4471f35..b9d8e47ffe8e 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -99,7 +99,7 @@ int omap_i2c_reset(struct omap_hwmod *oh)
                                 MAX_MODULE_SOFTRESET_WAIT, c);
 
         if (c == MAX_MODULE_SOFTRESET_WAIT)
-                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                pr_warn("%s: %s: softreset failed (waited %d usec)\n",
                         __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
         else
                 pr_debug("%s: %s: softreset in %d usec\n", __func__,
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index d42022f2a71e..53841dea80ea 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void)
 
         default:
                 /* Unknown default to latest silicon rev as default*/
-                pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
+                pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
                         __func__, idcode, hawkeye, rev);
                 omap_revision = DRA752_REV_ES1_1;
         }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5d0667c119f6..b8ad045bcb8d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -231,15 +231,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
                 .length         = L4_PER_44XX_SIZE,
                 .type           = MT_DEVICE,
         },
-#ifdef CONFIG_OMAP4_ERRATA_I688
-        {
-                .virtual        = OMAP4_SRAM_VA,
-                .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
-                .length         = PAGE_SIZE,
-                .type           = MT_MEMORY_RW_SO,
-        },
-#endif
-
 };
 #endif
 
@@ -269,14 +260,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
                 .length         = L4_PER_54XX_SIZE,
                 .type           = MT_DEVICE,
         },
-#ifdef CONFIG_OMAP4_ERRATA_I688
-        {
-                .virtual        = OMAP4_SRAM_VA,
-                .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
-                .length         = PAGE_SIZE,
-                .type           = MT_MEMORY_RW_SO,
-        },
-#endif
 };
 #endif
 
@@ -667,6 +650,7 @@ void __init omap5_init_early(void)
         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
                              OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap4_pm_init_early();
         omap_prm_base_init();
         omap_cm_base_init();
         omap44xx_prm_init();
@@ -682,6 +666,8 @@ void __init omap5_init_early(void)
 void __init omap5_init_late(void)
 {
         omap_common_late_init();
+        omap4_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 #endif
 
@@ -695,6 +681,7 @@ void __init dra7xx_init_early(void)
         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
                              OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap4_pm_init_early();
         omap_prm_base_init();
         omap_cm_base_init();
         omap44xx_prm_init();
@@ -709,6 +696,8 @@ void __init dra7xx_init_early(void)
 void __init dra7xx_init_late(void)
 {
         omap_common_late_init();
+        omap4_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
deleted file mode 100644
index 35b8590c322e..000000000000
--- a/arch/arm/mach-omap2/irq.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/irq.c
- *
- * Interrupt handler for OMAP2 boards.
- *
- * Copyright (C) 2005 Nokia Corporation
- * Author: Paul Mundt <paul.mundt@nokia.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
-
-/* selected INTC register offsets */
-
-#define INTC_REVISION           0x0000
-#define INTC_SYSCONFIG          0x0010
-#define INTC_SYSSTATUS          0x0014
-#define INTC_SIR                0x0040
-#define INTC_CONTROL            0x0048
-#define INTC_PROTECTION         0x004C
-#define INTC_IDLE               0x0050
-#define INTC_THRESHOLD          0x0068
-#define INTC_MIR0               0x0084
-#define INTC_MIR_CLEAR0         0x0088
-#define INTC_MIR_SET0           0x008c
-#define INTC_PENDING_IRQ0       0x0098
-/* Number of IRQ state bits in each MIR register */
-#define IRQ_BITS_PER_REG        32
-
-#define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-#define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
-#define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
-#define INTCPS_NR_MIR_REGS      3
-#define INTCPS_NR_IRQS          96
-
-/*
- * OMAP2 has a number of different interrupt controllers, each interrupt
- * controller is identified as its own "bank". Register definitions are
- * fairly consistent for each bank, but not all registers are implemented
- * for each bank.. when in doubt, consult the TRM.
- */
-static struct omap_irq_bank {
-        void __iomem *base_reg;
-        unsigned int nr_irqs;
-} __attribute__ ((aligned(4))) irq_banks[] = {
-        {
-                /* MPU INTC */
-                .nr_irqs        = 96,
-        },
-};
-
-static struct irq_domain *domain;
-
-/* Structure to save interrupt controller context */
-struct omap3_intc_regs {
-        u32 sysconfig;
-        u32 protection;
-        u32 idle;
-        u32 threshold;
-        u32 ilr[INTCPS_NR_IRQS];
-        u32 mir[INTCPS_NR_MIR_REGS];
-};
-
-/* INTC bank register get/set */
-
-static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
-{
-        writel_relaxed(val, bank->base_reg + reg);
-}
-
-static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
-{
-        return readl_relaxed(bank->base_reg + reg);
-}
-
-/* XXX: FIQ and additional INTC support (only MPU at the moment) */
-static void omap_ack_irq(struct irq_data *d)
-{
-        intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
-}
-
-static void omap_mask_ack_irq(struct irq_data *d)
-{
-        irq_gc_mask_disable_reg(d);
-        omap_ack_irq(d);
-}
-
-static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
-{
-        unsigned long tmp;
-
-        tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
-        pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
-                bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
-
-        tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
-        tmp |= 1 << 1;  /* soft reset */
-        intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
-
-        while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
-                /* Wait for reset to complete */;
-
-        /* Enable autoidle */
-        intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
-}
-
-int omap_irq_pending(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
-                struct omap_irq_bank *bank = irq_banks + i;
-                int irq;
-
-                for (irq = 0; irq < bank->nr_irqs; irq += 32)
-                        if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
-                                               ((irq >> 5) << 5)))
-                                return 1;
-        }
-        return 0;
-}
-
-static __init void
-omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
-                                        handle_level_irq);
-        ct = gc->chip_types;
-        ct->chip.irq_ack = omap_mask_ack_irq;
-        ct->chip.irq_mask = irq_gc_mask_disable_reg;
-        ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
-        ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
-
-        ct->regs.enable = INTC_MIR_CLEAR0;
-        ct->regs.disable = INTC_MIR_SET0;
-        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
-                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-}
-
-static void __init omap_init_irq(u32 base, int nr_irqs,
-                                 struct device_node *node)
-{
-        void __iomem *omap_irq_base;
-        unsigned long nr_of_irqs = 0;
-        unsigned int nr_banks = 0;
-        int i, j, irq_base;
-
-        omap_irq_base = ioremap(base, SZ_4K);
-        if (WARN_ON(!omap_irq_base))
-                return;
-
-        irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
-        if (irq_base < 0) {
-                pr_warn("Couldn't allocate IRQ numbers\n");
-                irq_base = 0;
-        }
-
-        domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
-                                       &irq_domain_simple_ops, NULL);
-
-        for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
-                struct omap_irq_bank *bank = irq_banks + i;
-
-                bank->nr_irqs = nr_irqs;
-
-                /* Static mapping, never released */
-                bank->base_reg = ioremap(base, SZ_4K);
-                if (!bank->base_reg) {
-                        pr_err("Could not ioremap irq bank%i\n", i);
-                        continue;
-                }
-
-                omap_irq_bank_init_one(bank);
-
-                for (j = 0; j < bank->nr_irqs; j += 32)
-                        omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
-
-                nr_of_irqs += bank->nr_irqs;
-                nr_banks++;
-        }
-
-        pr_info("Total of %ld interrupts on %d active controller%s\n",
-                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
-}
-
-void __init omap2_init_irq(void)
-{
-        omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
-}
-
-void __init omap3_init_irq(void)
-{
-        omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
-}
-
-void __init ti81xx_init_irq(void)
-{
-        omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
-}
-
-static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
-{
-        u32 irqnr;
-        int handled_irq = 0;
-
-        do {
-                irqnr = readl_relaxed(base_addr + 0x98);
-                if (irqnr)
-                        goto out;
-
-                irqnr = readl_relaxed(base_addr + 0xb8);
-                if (irqnr)
-                        goto out;
-
-                irqnr = readl_relaxed(base_addr + 0xd8);
-#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
-                if (irqnr)
-                        goto out;
-                irqnr = readl_relaxed(base_addr + 0xf8);
-#endif
-
-out:
-                if (!irqnr)
-                        break;
-
-                irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
-                irqnr &= ACTIVEIRQ_MASK;
-
-                if (irqnr) {
-                        irqnr = irq_find_mapping(domain, irqnr);
-                        handle_IRQ(irqnr, regs);
-                        handled_irq = 1;
-                }
-        } while (irqnr);
-
-        /* If an irq is masked or deasserted while active, we will
-         * keep ending up here with no irq handled. So remove it from
-         * the INTC with an ack.*/
-        if (!handled_irq)
-                omap_ack_irq(NULL);
-}
-
-asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
-{
-        void __iomem *base_addr = OMAP2_IRQ_BASE;
-        omap_intc_handle_irq(base_addr, regs);
-}
-
-int __init intc_of_init(struct device_node *node,
-                             struct device_node *parent)
-{
-        struct resource res;
-        u32 nr_irq = 96;
-
-        if (WARN_ON(!node))
-                return -ENODEV;
-
-        if (of_address_to_resource(node, 0, &res)) {
-                WARN(1, "unable to get intc registers\n");
-                return -EINVAL;
-        }
-
-        if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
-                pr_warn("unable to get intc-size, default to %d\n", nr_irq);
-
-        omap_init_irq(res.start, nr_irq, of_node_get(node));
-
-        return 0;
-}
-
-static struct of_device_id irq_match[] __initdata = {
-        { .compatible = "ti,omap2-intc", .data = intc_of_init, },
-        { }
-};
-
-void __init omap_intc_of_init(void)
-{
-        of_irq_init(irq_match);
-}
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
-static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
-
-void omap_intc_save_context(void)
-{
-        int ind = 0, i = 0;
-        for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
-                struct omap_irq_bank *bank = irq_banks + ind;
-                intc_context[ind].sysconfig =
-                        intc_bank_read_reg(bank, INTC_SYSCONFIG);
-                intc_context[ind].protection =
-                        intc_bank_read_reg(bank, INTC_PROTECTION);
-                intc_context[ind].idle =
-                        intc_bank_read_reg(bank, INTC_IDLE);
-                intc_context[ind].threshold =
-                        intc_bank_read_reg(bank, INTC_THRESHOLD);
-                for (i = 0; i < INTCPS_NR_IRQS; i++)
-                        intc_context[ind].ilr[i] =
-                                intc_bank_read_reg(bank, (0x100 + 0x4*i));
-                for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
-                        intc_context[ind].mir[i] =
-                                intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
-                                (0x20 * i));
-        }
-}
-
-void omap_intc_restore_context(void)
-{
-        int ind = 0, i = 0;
-
-        for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
-                struct omap_irq_bank *bank = irq_banks + ind;
-                intc_bank_write_reg(intc_context[ind].sysconfig,
-                                        bank, INTC_SYSCONFIG);
-                intc_bank_write_reg(intc_context[ind].sysconfig,
-                                        bank, INTC_SYSCONFIG);
-                intc_bank_write_reg(intc_context[ind].protection,
-                                        bank, INTC_PROTECTION);
-                intc_bank_write_reg(intc_context[ind].idle,
-                                        bank, INTC_IDLE);
-                intc_bank_write_reg(intc_context[ind].threshold,
-                                        bank, INTC_THRESHOLD);
-                for (i = 0; i < INTCPS_NR_IRQS; i++)
-                        intc_bank_write_reg(intc_context[ind].ilr[i],
-                                bank, (0x100 + 0x4*i));
-                for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
-                        intc_bank_write_reg(intc_context[ind].mir[i],
-                                 &irq_banks[0], INTC_MIR0 + (0x20 * i));
-        }
-        /* MIRs are saved and restore with other PRCM registers */
-}
-
-void omap3_intc_suspend(void)
-{
-        /* A pending interrupt would prevent OMAP from entering suspend */
-        omap_ack_irq(NULL);
-}
-
-void omap3_intc_prepare_idle(void)
-{
-        /*
-         * Disable autoidle as it can stall interrupt controller,
-         * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
-         */
-        intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
-}
-
-void omap3_intc_resume_idle(void)
-{
-        /* Re-enable autoidle */
-        intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
-}
-
-asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
-{
-        void __iomem *base_addr = OMAP3_IRQ_BASE;
-        omap_intc_handle_irq(base_addr, regs);
-}
-#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 828e0db3d943..8bdf182422bd 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -76,8 +76,8 @@ int omap_msdi_reset(struct omap_hwmod *oh)
                           MAX_MODULE_SOFTRESET_WAIT, c);
 
         if (c == MAX_MODULE_SOFTRESET_WAIT)
-                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
-                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+                pr_warn("%s: %s: softreset failed (waited %d usec)\n",
+                        __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
         else
                 pr_debug("%s: %s: softreset in %d usec\n", __func__,
                          oh->name, c);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ac8a249779f2..78064b0d4db5 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -814,7 +814,7 @@ int __init omap_mux_late_init(void)
                         "hwmod_io", omap_mux_late_init);
 
         if (ret)
-                pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
+                pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 4001325f90fb..6944ae3674e8 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -56,6 +56,7 @@
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
+#include "prcm_mpu54xx.h"
 #include "prminst44xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
@@ -68,7 +69,6 @@ struct omap4_cpu_pm_info {
         void __iomem *scu_sar_addr;
         void __iomem *wkup_sar_addr;
         void __iomem *l2x0_sar_addr;
-        void (*secondary_startup)(void);
 };
 
 /**
@@ -76,6 +76,7 @@ struct omap4_cpu_pm_info {
  * @finish_suspend:     CPU suspend finisher function pointer
  * @resume:             CPU resume function pointer
  * @scu_prepare:        CPU Snoop Control program function pointer
+ * @hotplug_restart:    CPU restart function pointer
  *
  * Structure holds functions pointer for CPU low power operations like
  * suspend, resume and scu programming.
@@ -84,11 +85,13 @@ struct cpu_pm_ops {
         int (*finish_suspend)(unsigned long cpu_state);
         void (*resume)(void);
         void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
+        void (*hotplug_restart)(void);
 };
 
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
 static struct powerdomain *mpuss_pd;
 static void __iomem *sar_base;
+static u32 cpu_context_offset;
 
 static int default_finish_suspend(unsigned long cpu_state)
 {
@@ -106,6 +109,7 @@ struct cpu_pm_ops omap_pm_ops = {
         .finish_suspend         = default_finish_suspend,
         .resume                 = dummy_cpu_resume,
         .scu_prepare            = dummy_scu_prepare,
+        .hotplug_restart        = dummy_cpu_resume,
 };
 
 /*
@@ -116,7 +120,8 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 {
         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 
-        writel_relaxed(addr, pm_info->wkup_sar_addr);
+        if (pm_info->wkup_sar_addr)
+                writel_relaxed(addr, pm_info->wkup_sar_addr);
 }
 
 /*
@@ -141,7 +146,8 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
                 break;
         }
 
-        writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
+        if (pm_info->scu_sar_addr)
+                writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
 }
 
 /* Helper functions for MPUSS OSWR */
@@ -161,14 +167,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
 
         if (cpu_id) {
                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
-                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+                                        cpu_context_offset);
                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
-                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+                                        cpu_context_offset);
         } else {
                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
-                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+                                        cpu_context_offset);
                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
-                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+                                        cpu_context_offset);
         }
 }
 
@@ -179,7 +185,8 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 {
         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 
-        writel_relaxed(save_state, pm_info->l2x0_sar_addr);
+        if (pm_info->l2x0_sar_addr)
+                writel_relaxed(save_state, pm_info->l2x0_sar_addr);
 }
 
 /*
@@ -189,10 +196,14 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 #ifdef CONFIG_CACHE_L2X0
 static void __init save_l2x0_context(void)
 {
-        writel_relaxed(l2x0_saved_regs.aux_ctrl,
-                     sar_base + L2X0_AUXCTRL_OFFSET);
-        writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
-                     sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+        void __iomem *l2x0_base = omap4_get_l2cache_base();
+
+        if (l2x0_base && sar_base) {
+                writel_relaxed(l2x0_saved_regs.aux_ctrl,
+                               sar_base + L2X0_AUXCTRL_OFFSET);
+                writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+                               sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+        }
 }
 #else
 static void __init save_l2x0_context(void)
@@ -231,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
                 save_state = 1;
                 break;
         case PWRDM_POWER_RET:
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
+                        save_state = 0;
+                        break;
+                }
         default:
                 /*
                  * CPUx CSWR is invalid hardware state. Also CPUx OSWR
@@ -298,12 +313,16 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
         if (omap_rev() == OMAP4430_REV_ES1_0)
                 return -ENXIO;
 
+        /* Use the achievable power state for the domain */
+        power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
+                                               false, power_state);
+
         if (power_state == PWRDM_POWER_OFF)
                 cpu_state = 1;
 
         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
         omap_pm_ops.scu_prepare(cpu, power_state);
 
         /*
@@ -319,6 +338,21 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 
 
 /*
+ * Enable Mercury Fast HG retention mode by default.
+ */
+static void enable_mercury_retention_mode(void)
+{
+        u32 reg;
+
+        reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
+                                  OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
+        /* Enable HG_EN, HG_RAMPUP = fast mode */
+        reg |= BIT(24) | BIT(25);
+        omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
+                                      OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
+}
+
+/*
  * Initialise OMAP4 MPUSS
  */
 int __init omap4_mpuss_init(void)
@@ -330,13 +364,17 @@ int __init omap4_mpuss_init(void)
                 return -ENODEV;
         }
 
-        sar_base = omap4_get_sar_ram_base();
+        if (cpu_is_omap44xx())
+                sar_base = omap4_get_sar_ram_base();
 
         /* Initilaise per CPU PM information */
         pm_info = &per_cpu(omap4_pm_info, 0x0);
-        pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
-        pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
-        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+        if (sar_base) {
+                pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
+                pm_info->wkup_sar_addr = sar_base +
+                                        CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
+                pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+        }
         pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
         if (!pm_info->pwrdm) {
                 pr_err("Lookup failed for CPU0 pwrdm\n");
@@ -351,13 +389,12 @@ int __init omap4_mpuss_init(void)
         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 
         pm_info = &per_cpu(omap4_pm_info, 0x1);
-        pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
-        pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
-        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
-        if (cpu_is_omap446x())
-                pm_info->secondary_startup = omap4460_secondary_startup;
-        else
-                pm_info->secondary_startup = omap4_secondary_startup;
+        if (sar_base) {
+                pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
+                pm_info->wkup_sar_addr = sar_base +
+                                        CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
+                pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+        }
 
         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
         if (!pm_info->pwrdm) {
@@ -380,20 +417,27 @@ int __init omap4_mpuss_init(void)
         pwrdm_clear_all_prev_pwrst(mpuss_pd);
         mpuss_clear_prev_logic_pwrst();
 
-        /* Save device type on scratchpad for low level code to use */
-        if (omap_type() != OMAP2_DEVICE_TYPE_GP)
-                writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
-        else
-                writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
-
-        save_l2x0_context();
+        if (sar_base) {
+                /* Save device type on scratchpad for low level code to use */
+                writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
+                               sar_base + OMAP_TYPE_OFFSET);
+                save_l2x0_context();
+        }
 
         if (cpu_is_omap44xx()) {
                 omap_pm_ops.finish_suspend = omap4_finish_suspend;
                 omap_pm_ops.resume = omap4_cpu_resume;
                 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+                omap_pm_ops.hotplug_restart = omap4_secondary_startup;
+                cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
+        } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
+                cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
+                enable_mercury_retention_mode();
         }
 
+        if (cpu_is_omap446x())
+                omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 3e97c6c8ecf1..dec2b05d184b 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -45,6 +45,7 @@
 #define OMAP4_MON_L2X0_PREFETCH_INDEX   0x113
 
 #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
+#define OMAP5_MON_AMBA_IF_INDEX         0x108
 
 /* Secure PPA(Primary Protected Application) APIs */
 #define OMAP4_PPA_L2_POR_INDEX          0x23
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 37843a7d3639..f961c46453b9 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -32,6 +32,7 @@
 #include "soc.h"
 #include "omap4-sar-layout.h"
 #include "common.h"
+#include "pm.h"
 
 #define AM43XX_NR_REG_BANKS     7
 #define AM43XX_IRQS             224
@@ -381,7 +382,7 @@ static struct notifier_block irq_notifier_block = {
 static void __init irq_pm_init(void)
 {
         /* FIXME: Remove this when MPU OSWR support is added */
-        if (!soc_is_omap54xx())
+        if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
                 cpu_pm_register_notifier(&irq_notifier_block);
 }
 #else
@@ -406,6 +407,7 @@ int __init omap_wakeupgen_init(void)
 {
         int i;
         unsigned int boot_cpu = smp_processor_id();
+        u32 val;
 
         /* Not supported on OMAP4 ES1.0 silicon */
         if (omap_rev() == OMAP4430_REV_ES1_0) {
@@ -451,6 +453,22 @@ int __init omap_wakeupgen_init(void)
         for (i = 0; i < max_irqs; i++)
                 irq_target_cpu[i] = boot_cpu;
 
+        /*
+         * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
+         * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
+         * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
+         * independently.
+         * This needs to be set one time thanks to always ON domain.
+         *
+         * We do not support ES1 behavior anymore. OMAP5 is assumed to be
+         * ES2.0, and the same is applicable for DRA7.
+         */
+        if (soc_is_omap54xx() || soc_is_dra7xx()) {
+                val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
+                val |= BIT(5);
+                omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
+        }
+
         irq_hotplug_init();
         irq_pm_init();
 
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h
index b0fd16f5c391..b3c8eccfae79 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
@@ -27,6 +27,7 @@
 #define OMAP_WKG_ENB_E_1                        0x420
 #define OMAP_AUX_CORE_BOOT_0                    0x800
 #define OMAP_AUX_CORE_BOOT_1                    0x804
+#define OMAP_AMBA_IF_MODE                       0x80c
 #define OMAP_PTMSYNCREQ_MASK                    0xc00
 #define OMAP_PTMSYNCREQ_EN                      0xc04
 #define OMAP_TIMESTAMPCYCLELO                   0xc08
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index a0fe747634c1..16b20cedc38d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -25,6 +25,7 @@
 #include <linux/irqchip/irq-crossbar.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
+#include <linux/genalloc.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -71,6 +72,26 @@ void omap_bus_sync(void)
 }
 EXPORT_SYMBOL(omap_bus_sync);
 
+static int __init omap4_sram_init(void)
+{
+        struct device_node *np;
+        struct gen_pool *sram_pool;
+
+        np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
+        if (!np)
+                pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
+                        __func__);
+        sram_pool = of_get_named_gen_pool(np, "sram", 0);
+        if (!sram_pool)
+                pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
+                        __func__);
+        else
+                sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
+
+        return 0;
+}
+omap_arch_initcall(omap4_sram_init);
+
 /* Steal one page physical memory for barrier implementation */
 int __init omap_barrier_reserve_memblock(void)
 {
@@ -91,7 +112,6 @@ void __init omap_barriers_init(void)
         dram_io_desc[0].type = MT_MEMORY_RW_SO;
         iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
         dram_sync = (void __iomem *) dram_io_desc[0].virtual;
-        sram_sync = (void __iomem *) OMAP4_SRAM_VA;
 
         pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
                 (long long) paddr, dram_io_desc[0].virtual);
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 01ef59def44b..d22c30d3ccfa 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
 
         r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
         if (!IS_ERR(r)) {
-                dev_warn(&od->pdev->dev,
+                dev_dbg(&od->pdev->dev,
                          "alias %s already exists\n", clk_alias);
                 clk_put(r);
                 return;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6c074f37cdd2..716247ed9e0c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -769,8 +769,8 @@ static int _init_main_clk(struct omap_hwmod *oh)
 
         oh->_clk = clk_get(NULL, oh->main_clk);
         if (IS_ERR(oh->_clk)) {
-                pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
-                           oh->name, oh->main_clk);
+                pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
+                        oh->name, oh->main_clk);
                 return -EINVAL;
         }
         /*
@@ -814,8 +814,8 @@ static int _init_interface_clks(struct omap_hwmod *oh)
 
                 c = clk_get(NULL, os->clk);
                 if (IS_ERR(c)) {
-                        pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
-                                   oh->name, os->clk);
+                        pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
+                                oh->name, os->clk);
                         ret = -EINVAL;
                         continue;
                 }
@@ -851,8 +851,8 @@ static int _init_opt_clks(struct omap_hwmod *oh)
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
                 c = clk_get(NULL, oc->clk);
                 if (IS_ERR(c)) {
-                        pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
-                                   oh->name, oc->clk);
+                        pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
+                                oh->name, oc->clk);
                         ret = -EINVAL;
                         continue;
                 }
@@ -1576,7 +1576,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
 
         oh->clkdm = clkdm_lookup(oh->clkdm_name);
         if (!oh->clkdm) {
-                pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
+                pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n",
                         oh->name, oh->clkdm_name);
                 return 0;
         }
@@ -1616,7 +1616,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
         if (!ret)
                 oh->_state = _HWMOD_STATE_CLKS_INITED;
         else
-                pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
+                pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
 
         return ret;
 }
@@ -1739,7 +1739,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
         _disable_clocks(oh);
 
         if (ret == -EBUSY)
-                pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
+                pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
 
         if (!ret) {
                 /*
@@ -1953,8 +1953,8 @@ static int _ocp_softreset(struct omap_hwmod *oh)
 
         c = _wait_softreset_complete(oh);
         if (c == MAX_MODULE_SOFTRESET_WAIT) {
-                pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
-                           oh->name, MAX_MODULE_SOFTRESET_WAIT);
+                pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n",
+                        oh->name, MAX_MODULE_SOFTRESET_WAIT);
                 ret = -ETIMEDOUT;
                 goto dis_opt_clks;
         } else {
@@ -2065,7 +2065,7 @@ static void _reconfigure_io_chain(void)
 
         spin_lock_irqsave(&io_chain_lock, flags);
 
-        if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl())
+        if (cpu_is_omap34xx())
                 omap3xxx_prm_reconfigure_io_chain();
         else if (cpu_is_omap44xx())
                 omap44xx_prm_reconfigure_io_chain();
@@ -2185,6 +2185,8 @@ static int _enable(struct omap_hwmod *oh)
                          oh->mux->pads_dynamic))) {
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
                 _reconfigure_io_chain();
+        } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
+                _reconfigure_io_chain();
         }
 
         _add_initiator_dep(oh, mpu_oh);
@@ -2291,6 +2293,8 @@ static int _idle(struct omap_hwmod *oh)
         if (oh->mux && oh->mux->pads_dynamic) {
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
                 _reconfigure_io_chain();
+        } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
+                _reconfigure_io_chain();
         }
 
         oh->_state = _HWMOD_STATE_IDLE;
@@ -2614,8 +2618,8 @@ static int __init _setup_reset(struct omap_hwmod *oh)
         if (oh->rst_lines_cnt == 0) {
                 r = _enable(oh);
                 if (r) {
-                        pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
-                                   oh->name, oh->_state);
+                        pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
+                                oh->name, oh->_state);
                         return -EINVAL;
                 }
         }
@@ -3345,6 +3349,9 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
         if (!ois)
                 return 0;
 
+        if (ois[0] == NULL) /* Empty list */
+                return 0;
+
         if (!linkspace) {
                 if (_alloc_linkspace(ois)) {
                         pr_err("omap_hwmod: could not allocate link space\n");
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0f97d635ff90..512f809a3f4d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -514,6 +514,9 @@ struct omap_hwmod_omap4_prcm {
  * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
  *     out of idle, but rely on smart-idle to the put it back in idle,
  *     so the wakeups are still functional (Only known case for now is UART)
+ * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up 
+ *     events by calling _reconfigure_io_chain() when a device is enabled
+ *     or idled.
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -528,6 +531,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_BLOCK_WFI                         (1 << 10)
 #define HWMOD_FORCE_MSTANDBY                    (1 << 11)
 #define HWMOD_SWSUP_SIDLE_ACT                   (1 << 12)
+#define HWMOD_RECONFIG_IO_CHAIN                 (1 << 13)
 
 /*
  * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e9516b454e76..2a78b093c0ce 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -490,7 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
         .mpu_irqs       = omap2_uart1_mpu_irqs,
         .sdma_reqs      = omap2_uart1_sdma_reqs,
         .main_clk       = "uart1_fck",
-        .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
         .prcm           = {
                 .omap2 = {
                         .module_offs = CORE_MOD,
@@ -509,7 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
         .mpu_irqs       = omap2_uart2_mpu_irqs,
         .sdma_reqs      = omap2_uart2_sdma_reqs,
         .main_clk       = "uart2_fck",
-        .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
         .prcm           = {
                 .omap2 = {
                         .module_offs = CORE_MOD,
@@ -529,7 +529,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
         .sdma_reqs      = omap2_uart3_sdma_reqs,
         .main_clk       = "uart3_fck",
         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
-                                HWMOD_SWSUP_SIDLE_ACT,
+                                HWMOD_SWSUP_SIDLE,
         .prcm           = {
                 .omap2 = {
                         .module_offs = OMAP3430_PER_MOD,
@@ -559,7 +559,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
         .mpu_irqs       = uart4_mpu_irqs,
         .sdma_reqs      = uart4_sdma_reqs,
         .main_clk       = "uart4_fck",
-        .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
         .prcm           = {
                 .omap2 = {
                         .module_offs = OMAP3430_PER_MOD,
@@ -1730,8 +1730,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
          * signal when MIDLEMODE is set to force-idle.
          */
-        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
-                                | HWMOD_FORCE_MSTANDBY,
+        .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
+                          HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
 };
 
 /* usb_otg_hs */
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 2757abf87fbc..5684f112654b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -35,6 +35,7 @@
 #include "i2c.h"
 #include "mmc.h"
 #include "wd_timer.h"
+#include "soc.h"
 
 /* Base offset for all DRA7XX interrupts external to MPUSS */
 #define DRA7XX_IRQ_GIC_START    32
@@ -3261,7 +3262,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_per3__usb_otg_ss1,
         &dra7xx_l4_per3__usb_otg_ss2,
         &dra7xx_l4_per3__usb_otg_ss3,
-        &dra7xx_l4_per3__usb_otg_ss4,
         &dra7xx_l3_main_1__vcp1,
         &dra7xx_l4_per2__vcp1,
         &dra7xx_l3_main_1__vcp2,
@@ -3270,8 +3270,26 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         NULL,
 };
 
+static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
+        &dra7xx_l4_per3__usb_otg_ss4,
+        NULL,
+};
+
+static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
+        NULL,
+};
+
 int __init dra7xx_hwmod_init(void)
 {
+        int ret;
+
         omap_hwmod_init();
-        return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
+        ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
+
+        if (!ret && soc_is_dra74x())
+                return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
+        else if (!ret && soc_is_dra72x())
+                return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
+
+        return ret;
 }
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 90c88d498485..c95346c94829 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -244,14 +244,22 @@ static void __init nokia_n900_legacy_init(void)
                         /* set IBE to 1 */
                         rx51_secure_update_aux_cr(BIT(6), 0);
                 } else {
-                        pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n");
-                        pr_warning("Thumb binaries may crash randomly without this workaround\n");
+                        pr_warn("RX-51: Not enabling ARM errata 430973 workaround\n");
+                        pr_warn("Thumb binaries may crash randomly without this workaround\n");
                 }
 
                 pr_info("RX-51: Registring OMAP3 HWRNG device\n");
                 platform_device_register(&omap3_rom_rng_device);
 
         }
+
+        /* Only on some development boards */
+        gpio_request_one(164, GPIOF_OUT_INIT_LOW, "smc91x reset");
+}
+
+static void __init omap3_tao3530_legacy_init(void)
+{
+        hsmmc2_internal_input_clk();
 }
 #endif /* CONFIG_ARCH_OMAP3 */
 
@@ -336,6 +344,8 @@ static struct pdata_init auxdata_quirks[] __initdata = {
 struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
 #ifdef CONFIG_MACH_NOKIA_N8X0
         OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
+        OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
+        OF_DEV_AUXDATA("tlv320aic3x", 0x18, "2-0018", &n810_aic33_data),
 #endif
 #ifdef CONFIG_ARCH_OMAP3
         OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
@@ -352,6 +362,16 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
         OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata),
 #endif
+#ifdef CONFIG_SOC_OMAP5
+        OF_DEV_AUXDATA("ti,omap5-padconf", 0x4a002840, "4a002840.pinmux", &pcs_pdata),
+        OF_DEV_AUXDATA("ti,omap5-padconf", 0x4ae0c840, "4ae0c840.pinmux", &pcs_pdata),
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+        OF_DEV_AUXDATA("ti,dra7-padconf", 0x4a003400, "4a003400.pinmux", &pcs_pdata),
+#endif
+#ifdef CONFIG_SOC_AM43XX
+        OF_DEV_AUXDATA("ti,am437-padconf", 0x44e10800, "44e10800.pinmux", &pcs_pdata),
+#endif
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
         OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
                        &omap4_iommu_pdata),
@@ -377,6 +397,7 @@ static struct pdata_init pdata_quirks[] __initdata = {
         { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
         { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
         { "ti,am3517-evm", am3517_evm_legacy_init, },
+        { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, },
 #endif
 #ifdef CONFIG_ARCH_OMAP4
         { "ti,omap4-sdp", omap4_sdp_legacy_init, },
@@ -405,7 +426,7 @@ static void pdata_quirks_check(struct pdata_init *quirks)
         }
 }
 
-void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
+void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
 {
         omap_sdrc_init(NULL, NULL);
         pdata_quirks_check(auxdata_quirks);
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 828aee9ea6a8..58920bc8807b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -282,7 +282,7 @@ static inline void omap_init_cpufreq(void)
         if (!of_have_populated_dt())
                 devinfo.name = "omap-cpufreq";
         else
-                devinfo.name = "cpufreq-cpu0";
+                devinfo.name = "cpufreq-dt";
         platform_device_register_full(&devinfo);
 }
 
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index e150102d6c06..425bfcd67db6 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -101,6 +101,7 @@ static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 
 #define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD      (1 << 0)
+#define PM_OMAP4_CPU_OSWR_DISABLE               (1 << 1)
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
 extern u16 pm44xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3f80929a5f7e..175564c88a30 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -465,7 +465,7 @@ int __init omap3_pm_init(void)
         int ret;
 
         if (!omap3_has_io_chain_ctrl())
-                pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
+                pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
 
         pm_errata_configure();
 
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 0dda6cf8b855..503097c72b82 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -29,6 +29,7 @@ u16 pm44xx_errata;
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
+        u32 next_logic_state;
 #ifdef CONFIG_SUSPEND
         u32 saved_state;
         u32 saved_logic_state;
@@ -36,6 +37,8 @@ struct power_state {
         struct list_head node;
 };
 
+static u32 cpu_suspend_state = PWRDM_POWER_OFF;
+
 static LIST_HEAD(pwrst_list);
 
 #ifdef CONFIG_SUSPEND
@@ -54,7 +57,7 @@ static int omap4_pm_suspend(void)
         /* Set targeted power domain states by suspend */
         list_for_each_entry(pwrst, &pwrst_list, node) {
                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
-                pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
+                pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
         }
 
         /*
@@ -66,7 +69,7 @@ static int omap4_pm_suspend(void)
          * domain CSWR is not supported by hardware.
          * More details can be found in OMAP4430 TRM section 4.3.4.2.
          */
-        omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+        omap4_enter_lowpower(cpu_id, cpu_suspend_state);
 
         /* Restore next powerdomain state */
         list_for_each_entry(pwrst, &pwrst_list, node) {
@@ -112,15 +115,22 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
          * through hotplug path and CPU0 explicitly programmed
          * further down in the code path
          */
-        if (!strncmp(pwrdm->name, "cpu", 3))
+        if (!strncmp(pwrdm->name, "cpu", 3)) {
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
+                        cpu_suspend_state = PWRDM_POWER_RET;
                 return 0;
+        }
 
         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
         if (!pwrst)
                 return -ENOMEM;
 
         pwrst->pwrdm = pwrdm;
-        pwrst->next_state = PWRDM_POWER_RET;
+        pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
+                                                     PWRDM_POWER_RET);
+        pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
+                                                           PWRDM_POWER_OFF);
+
         list_add(&pwrst->node, &pwrst_list);
 
         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
@@ -203,6 +213,32 @@ static inline int omap4_init_static_deps(void)
 }
 
 /**
+ * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
+ *                               DRA7
+ *
+ * The dynamic dependency between MPUSS -> EMIF is broken and has
+ * not worked as expected. The hardware recommendation is to
+ * enable static dependencies for these to avoid system
+ * lock ups or random crashes.
+ */
+static inline int omap5_dra7_init_static_deps(void)
+{
+        struct clockdomain *mpuss_clkdm, *emif_clkdm;
+        int ret;
+
+        mpuss_clkdm = clkdm_lookup("mpu_clkdm");
+        emif_clkdm = clkdm_lookup("emif_clkdm");
+        if (!mpuss_clkdm || !emif_clkdm)
+                return -EINVAL;
+
+        ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
+        if (ret)
+                pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");
+
+        return ret;
+}
+
+/**
  * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
  *
  * Initializes basic stuff for power management functionality.
@@ -212,6 +248,9 @@ int __init omap4_pm_init_early(void)
         if (cpu_is_omap446x())
                 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
 
+        if (soc_is_omap54xx() || soc_is_dra7xx())
+                pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;
+
         return 0;
 }
 
@@ -239,10 +278,14 @@ int __init omap4_pm_init(void)
                 goto err2;
         }
 
-        if (cpu_is_omap44xx()) {
+        if (cpu_is_omap44xx())
                 ret = omap4_init_static_deps();
-                if (ret)
-                        goto err2;
+        else if (soc_is_omap54xx() || soc_is_dra7xx())
+                ret = omap5_dra7_init_static_deps();
+
+        if (ret) {
+                pr_err("Failed to initialise static dependencies.\n");
+                goto err2;
         }
 
         ret = omap4_mpuss_init();
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index faebd5f076af..7fb033eca0a5 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -546,7 +546,8 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
                 return -EINVAL;
 
         for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
-                ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
+                if (pwrdm->pwrdm_clkdms[i])
+                        ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
 
         return ret;
 }
@@ -1080,6 +1081,82 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_get_valid_lp_state() - Find best match deep power state
+ * @pwrdm:      power domain for which we want to find best match
+ * @is_logic_state: Are we looking for logic state match here? Should
+ *                  be one of PWRDM_xxx macro values
+ * @req_state:  requested power state
+ *
+ * Returns: closest match for requested power state. default fallback
+ * is RET for logic state and ON for power state.
+ *
+ * This does a search from the power domain data looking for the
+ * closest valid power domain state that the hardware can achieve.
+ * PRCM definitions for PWRSTCTRL allows us to program whatever
+ * configuration we'd like, and PRCM will actually attempt such
+ * a transition, however if the powerdomain does not actually support it,
+ * we endup with a hung system. The valid power domain states are already
+ * available in our powerdomain data files. So this function tries to do
+ * the following:
+ * a) find if we have an exact match to the request - no issues.
+ * b) else find if a deeper power state is possible.
+ * c) failing which, it tries to find closest higher power state for the
+ * request.
+ */
+u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
+                            bool is_logic_state, u8 req_state)
+{
+        u8 pwrdm_states = is_logic_state ? pwrdm->pwrsts_logic_ret :
+                        pwrdm->pwrsts;
+        /* For logic, ret is highest and others, ON is highest */
+        u8 default_pwrst = is_logic_state ? PWRDM_POWER_RET : PWRDM_POWER_ON;
+        u8 new_pwrst;
+        bool found;
+
+        /* If it is already supported, nothing to search */
+        if (pwrdm_states & BIT(req_state))
+                return req_state;
+
+        if (!req_state)
+                goto up_search;
+
+        /*
+         * So, we dont have a exact match
+         * Can we get a deeper power state match?
+         */
+        new_pwrst = req_state - 1;
+        found = true;
+        while (!(pwrdm_states & BIT(new_pwrst))) {
+                /* No match even at OFF? Not available */
+                if (new_pwrst == PWRDM_POWER_OFF) {
+                        found = false;
+                        break;
+                }
+                new_pwrst--;
+        }
+
+        if (found)
+                goto done;
+
+up_search:
+        /* OK, no deeper ones, can we get a higher match? */
+        new_pwrst = req_state + 1;
+        while (!(pwrdm_states & BIT(new_pwrst))) {
+                if (new_pwrst > PWRDM_POWER_ON) {
+                        WARN(1, "powerdomain: %s: Fix max powerstate to ON\n",
+                             pwrdm->name);
+                        return PWRDM_POWER_ON;
+                }
+
+                if (new_pwrst == default_pwrst)
+                        break;
+                new_pwrst++;
+        }
+done:
+        return new_pwrst;
+}
+
+/**
  * omap_set_pwrdm_state - change a powerdomain's current power state
  * @pwrdm: struct powerdomain * to change the power state of
  * @pwrst: power state to change to
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index f4727117f6cc..11bd4dd7d8d6 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -39,6 +39,7 @@
 #define PWRSTS_OFF_RET          (PWRSTS_OFF | PWRSTS_RET)
 #define PWRSTS_RET_ON           (PWRSTS_RET | PWRSTS_ON)
 #define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | PWRSTS_ON)
+#define PWRSTS_INA_ON           (PWRSTS_INACTIVE | PWRSTS_ON)
 
 
 /*
@@ -219,6 +220,9 @@ struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
 
 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
 
+u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
+                            bool is_logic_state, u8 req_state);
+
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_pwrst(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
index ce1d752af991..60d7ed8ef8ca 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = {
         .prcm_offs        = OMAP54XX_PRM_CORE_INST,
         .prcm_partition   = OMAP54XX_PRM_PARTITION,
         .pwrsts           = PWRSTS_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 5,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
@@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = {
         .voltdm           = { .name = "mpu" },
         .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C0_INST,
         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
-        .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
@@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = {
         .voltdm           = { .name = "mpu" },
         .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C1_INST,
         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
-        .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
@@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = {
         .prcm_offs        = OMAP54XX_PRM_MPU_INST,
         .prcm_partition   = OMAP54XX_PRM_PARTITION,
         .pwrsts           = PWRSTS_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 2,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 48151d1cfde0..287a2037aa16 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -160,8 +160,8 @@ static struct powerdomain core_7xx_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = DRA7XX_PRM_CORE_INST,
         .prcm_partition   = DRA7XX_PRM_PARTITION,
-        .pwrsts           = PWRSTS_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts           = PWRSTS_INA_ON,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 5,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
@@ -193,8 +193,8 @@ static struct powerdomain cpu0_7xx_pwrdm = {
         .name             = "cpu0_pwrdm",
         .prcm_offs        = DRA7XX_MPU_PRCM_PRM_C0_INST,
         .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
-        .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
@@ -209,8 +209,8 @@ static struct powerdomain cpu1_7xx_pwrdm = {
         .name             = "cpu1_pwrdm",
         .prcm_offs        = DRA7XX_MPU_PRCM_PRM_C1_INST,
         .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
-        .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
@@ -243,7 +243,7 @@ static struct powerdomain mpu_7xx_pwrdm = {
         .prcm_offs        = DRA7XX_PRM_MPU_INST,
         .prcm_partition   = DRA7XX_PRM_PARTITION,
         .pwrsts           = PWRSTS_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 2,
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 2458be6fc67b..ff08da385a2d 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of_irq.h>
 
 #include "soc.h"
 #include "common.h"
@@ -45,7 +46,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
         .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
         .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
         .restore_irqen          = &omap3xxx_prm_restore_irqen,
-        .reconfigure_io_chain   = &omap3xxx_prm_reconfigure_io_chain,
+        .reconfigure_io_chain   = NULL,
 };
 
 /*
@@ -369,15 +370,30 @@ void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
 }
 
 /**
- * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ * omap3430_pre_es3_1_reconfigure_io_chain - restart wake-up daisy chain
+ *
+ * The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only
+ * thing we can do is toggle EN_IO bit for earlier omaps.
+ */
+void omap3430_pre_es3_1_reconfigure_io_chain(void)
+{
+        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                     PM_WKEN);
+        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                   PM_WKEN);
+        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+}
+
+/**
+ * omap3_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
  *
  * Clear any previously-latched I/O wakeup events and ensure that the
  * I/O wakeup gates are aligned with the current mux settings.  Works
  * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
  * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
- * return value.
+ * return value. These registers are only available in 3430 es3.1 and later.
  */
-void omap3xxx_prm_reconfigure_io_chain(void)
+void omap3_prm_reconfigure_io_chain(void)
 {
         int i = 0;
 
@@ -400,6 +416,15 @@ void omap3xxx_prm_reconfigure_io_chain(void)
 }
 
 /**
+ * omap3xxx_prm_reconfigure_io_chain - reconfigure I/O chain
+ */
+void omap3xxx_prm_reconfigure_io_chain(void)
+{
+        if (omap3_prcm_irq_setup.reconfigure_io_chain)
+                omap3_prcm_irq_setup.reconfigure_io_chain();
+}
+
+/**
  * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
  *
  * Activates the I/O wakeup event latches and allows events logged by
@@ -649,6 +674,11 @@ int __init omap3xxx_prm_init(void)
         return prm_register(&omap3xxx_prm_ll_data);
 }
 
+static struct of_device_id omap3_prm_dt_match_table[] = {
+        { .compatible = "ti,omap3-prm" },
+        { }
+};
+
 static int omap3xxx_prm_late_init(void)
 {
         int ret;
@@ -656,6 +686,25 @@ static int omap3xxx_prm_late_init(void)
         if (!(prm_features & PRM_HAS_IO_WAKEUP))
                 return 0;
 
+        if (omap3_has_io_chain_ctrl())
+                omap3_prcm_irq_setup.reconfigure_io_chain =
+                        omap3_prm_reconfigure_io_chain;
+        else
+                omap3_prcm_irq_setup.reconfigure_io_chain =
+                        omap3430_pre_es3_1_reconfigure_io_chain;
+
+        if (of_have_populated_dt()) {
+                struct device_node *np;
+                int irq_num;
+
+                np = of_find_matching_node(NULL, omap3_prm_dt_match_table);
+                if (np) {
+                        irq_num = of_irq_get(np, 0);
+                        if (irq_num >= 0)
+                                omap3_prcm_irq_setup.irq = irq_num;
+                }
+        }
+
         omap3xxx_prm_enable_io_wakeup();
         ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
         if (!ret)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a7f6ea27180a..0958d070d3db 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,6 +17,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of_irq.h>
 
 
 #include "soc.h"
@@ -32,7 +33,6 @@
 /* Static data */
 
 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
-        OMAP_PRCM_IRQ("wkup",   0,      0),
         OMAP_PRCM_IRQ("io",     9,      1),
 };
 
@@ -154,21 +154,36 @@ void omap4_prm_vp_clear_txdone(u8 vp_id)
 
 u32 omap4_prm_vcvp_read(u8 offset)
 {
+        s32 inst = omap4_prmst_get_prm_dev_inst();
+
+        if (inst == PRM_INSTANCE_UNKNOWN)
+                return 0;
+
         return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-                                           OMAP4430_PRM_DEVICE_INST, offset);
+                                           inst, offset);
 }
 
 void omap4_prm_vcvp_write(u32 val, u8 offset)
 {
+        s32 inst = omap4_prmst_get_prm_dev_inst();
+
+        if (inst == PRM_INSTANCE_UNKNOWN)
+                return;
+
         omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
-                                     OMAP4430_PRM_DEVICE_INST, offset);
+                                     inst, offset);
 }
 
 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 {
+        s32 inst = omap4_prmst_get_prm_dev_inst();
+
+        if (inst == PRM_INSTANCE_UNKNOWN)
+                return 0;
+
         return omap4_prminst_rmw_inst_reg_bits(mask, bits,
                                                OMAP4430_PRM_PARTITION,
-                                               OMAP4430_PRM_DEVICE_INST,
+                                               inst,
                                                offset);
 }
 
@@ -275,14 +290,18 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
 void omap44xx_prm_reconfigure_io_chain(void)
 {
         int i = 0;
+        s32 inst = omap4_prmst_get_prm_dev_inst();
+
+        if (inst == PRM_INSTANCE_UNKNOWN)
+                return;
 
         /* Trigger WUCLKIN enable */
         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
                                     OMAP4430_WUCLK_CTRL_MASK,
-                                    OMAP4430_PRM_DEVICE_INST,
+                                    inst,
                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
         omap_test_timeout(
-                (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                (((omap4_prm_read_inst_reg(inst,
                                            OMAP4_PRM_IO_PMCTRL_OFFSET) &
                    OMAP4430_WUCLK_STATUS_MASK) >>
                   OMAP4430_WUCLK_STATUS_SHIFT) == 1),
@@ -292,10 +311,10 @@ void omap44xx_prm_reconfigure_io_chain(void)
 
         /* Trigger WUCLKIN disable */
         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
-                                    OMAP4430_PRM_DEVICE_INST,
+                                    inst,
                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
         omap_test_timeout(
-                (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                (((omap4_prm_read_inst_reg(inst,
                                            OMAP4_PRM_IO_PMCTRL_OFFSET) &
                    OMAP4430_WUCLK_STATUS_MASK) >>
                   OMAP4430_WUCLK_STATUS_SHIFT) == 0),
@@ -316,9 +335,14 @@ void omap44xx_prm_reconfigure_io_chain(void)
  */
 static void __init omap44xx_prm_enable_io_wakeup(void)
 {
+        s32 inst = omap4_prmst_get_prm_dev_inst();
+
+        if (inst == PRM_INSTANCE_UNKNOWN)
+                return;
+
         omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
                                     OMAP4430_GLOBAL_WUEN_MASK,
-                                    OMAP4430_PRM_DEVICE_INST,
+                                    inst,
                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 }
 
@@ -333,8 +357,13 @@ static u32 omap44xx_prm_read_reset_sources(void)
         struct prm_reset_src_map *p;
         u32 r = 0;
         u32 v;
+        s32 inst = omap4_prmst_get_prm_dev_inst();
 
-        v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+        if (inst == PRM_INSTANCE_UNKNOWN)
+                return 0;
+
+
+        v = omap4_prm_read_inst_reg(inst,
                                     OMAP4_RM_RSTST);
 
         p = omap44xx_prm_reset_src_map;
@@ -664,17 +693,56 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(void)
 {
-        if (cpu_is_omap44xx())
+        if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
                 prm_features |= PRM_HAS_IO_WAKEUP;
 
         return prm_register(&omap44xx_prm_ll_data);
 }
 
+static struct of_device_id omap_prm_dt_match_table[] = {
+        { .compatible = "ti,omap4-prm" },
+        { .compatible = "ti,omap5-prm" },
+        { .compatible = "ti,dra7-prm" },
+        { }
+};
+
 static int omap44xx_prm_late_init(void)
 {
+        struct device_node *np;
+        int irq_num;
+
         if (!(prm_features & PRM_HAS_IO_WAKEUP))
                 return 0;
 
+        /* OMAP4+ is DT only now */
+        if (!of_have_populated_dt())
+                return 0;
+
+        np = of_find_matching_node(NULL, omap_prm_dt_match_table);
+
+        if (!np) {
+                /* Default loaded up with OMAP4 values */
+                if (!cpu_is_omap44xx())
+                        return 0;
+        } else {
+                irq_num = of_irq_get(np, 0);
+                /*
+                 * Already have OMAP4 IRQ num. For all other platforms, we need
+                 * IRQ numbers from DT
+                 */
+                if (irq_num < 0 && !cpu_is_omap44xx()) {
+                        if (irq_num == -EPROBE_DEFER)
+                                return irq_num;
+
+                        /* Have nothing to do */
+                        return 0;
+                }
+
+                /* Once OMAP4 DT is filled as well */
+                if (irq_num >= 0)
+                        omap4_prcm_irq_setup.irq = irq_num;
+        }
+
         omap44xx_prm_enable_io_wakeup();
 
         return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 76ca320f007c..74054b813600 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -467,7 +467,7 @@ int prm_unregister(struct prm_ll_data *pld)
         return 0;
 }
 
-static struct of_device_id omap_prcm_dt_match_table[] = {
+static const struct of_device_id omap_prcm_dt_match_table[] = {
         { .compatible = "ti,am3-prcm" },
         { .compatible = "ti,am3-scrm" },
         { .compatible = "ti,am4-prcm" },
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 69f0dd08629c..225e0258d76d 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -31,6 +31,8 @@
 
 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
 
+static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
+
 /**
  * omap_prm_base_init - Populates the prm partitions
  *
@@ -43,6 +45,24 @@ void omap_prm_base_init(void)
         _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
 }
 
+s32 omap4_prmst_get_prm_dev_inst(void)
+{
+        if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
+                return prm_dev_inst;
+
+        /* This cannot be done way early at boot.. as things are not setup */
+        if (cpu_is_omap44xx())
+                prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
+        else if (soc_is_omap54xx())
+                prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
+        else if (soc_is_dra7xx())
+                prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
+        else if (soc_is_am43xx())
+                prm_dev_inst = AM43XX_PRM_DEVICE_INST;
+
+        return prm_dev_inst;
+}
+
 /* Read a register in a PRM instance */
 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
 {
@@ -169,28 +189,18 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
 void omap4_prminst_global_warm_sw_reset(void)
 {
         u32 v;
-        s16 dev_inst;
+        s32 inst = omap4_prmst_get_prm_dev_inst();
 
-        if (cpu_is_omap44xx())
-                dev_inst = OMAP4430_PRM_DEVICE_INST;
-        else if (soc_is_omap54xx())
-                dev_inst = OMAP54XX_PRM_DEVICE_INST;
-        else if (soc_is_dra7xx())
-                dev_inst = DRA7XX_PRM_DEVICE_INST;
-        else if (soc_is_am43xx())
-                dev_inst = AM43XX_PRM_DEVICE_INST;
-        else
+        if (inst == PRM_INSTANCE_UNKNOWN)
                 return;
 
-        v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
+        v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
                                         OMAP4_PRM_RSTCTRL_OFFSET);
         v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
         omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
-                                 dev_inst,
-                                 OMAP4_PRM_RSTCTRL_OFFSET);
+                                 inst, OMAP4_PRM_RSTCTRL_OFFSET);
 
         /* OCP barrier */
         v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-                                    dev_inst,
-                                    OMAP4_PRM_RSTCTRL_OFFSET);
+                                    inst, OMAP4_PRM_RSTCTRL_OFFSET);
 }
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index a2ede2d65481..583aa3774571 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -12,6 +12,9 @@
 #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
 #define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
 
+#define PRM_INSTANCE_UNKNOWN    -1
+extern s32 omap4_prmst_get_prm_dev_inst(void);
+
 /*
  * In an ideal world, we would not export these low-level functions,
  * but this will probably take some time to fix properly
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 7a42e1960c3b..d3a588cf3a6e 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -20,8 +20,8 @@ static int sr_class3_enable(struct omap_sr *sr)
         unsigned long volt = voltdm_get_voltage(sr->voltdm);
 
         if (!volt) {
-                pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
-                                __func__, sr->name);
+                pr_warn("%s: Curr voltage unknown. Cannot enable %s\n",
+                        __func__, sr->name);
                 return -ENODATA;
         }
 
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 01ca8086fb6c..4376f59626d1 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -245,6 +245,8 @@ IS_AM_SUBCLASS(437x, 0x437)
 #define soc_is_omap54xx()               0
 #define soc_is_omap543x()               0
 #define soc_is_dra7xx()                 0
+#define soc_is_dra74x()                 0
+#define soc_is_dra72x()                 0
 
 #if defined(MULTI_OMAP2)
 # if defined(CONFIG_ARCH_OMAP2)
@@ -393,7 +395,11 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 #if defined(CONFIG_SOC_DRA7XX)
 #undef soc_is_dra7xx
+#undef soc_is_dra74x
+#undef soc_is_dra72x
 #define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
+#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
+#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
 #endif
 
 /* Various silicon revisions for omap2 */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 1b91ef0c182a..d7cff2632d1e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -154,7 +154,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
         pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
         if (IS_ERR(pdev))
-                pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
+                pr_warn("%s: Could not build omap_device for %s: %s\n",
                         __func__, name, oh->name);
 exit:
         i++;
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index ddf1818af228..cd488b80ba36 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -32,12 +32,6 @@
 
 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA           0x40300000
 
 #define SRAM_BOOTLOADER_SZ      0x00
 
@@ -105,32 +99,14 @@ static void __init omap_detect_sram(void)
                         } else {
                                 omap_sram_size = 0x8000; /* 32K */
                         }
-                } else if (cpu_is_omap44xx()) {
-                        omap_sram_start = OMAP4_SRAM_PUB_PA;
-                        omap_sram_size = 0xa000; /* 40K */
-                } else if (soc_is_omap54xx()) {
-                        omap_sram_start = OMAP5_SRAM_PA;
-                        omap_sram_size = SZ_128K; /* 128KB */
                 } else {
                         omap_sram_start = OMAP2_SRAM_PUB_PA;
                         omap_sram_size = 0x800; /* 2K */
                 }
         } else {
-                if (soc_is_am33xx()) {
-                        omap_sram_start = AM33XX_SRAM_PA;
-                        omap_sram_size = 0x10000; /* 64K */
-                } else if (soc_is_am43xx()) {
-                        omap_sram_start = AM33XX_SRAM_PA;
-                        omap_sram_size = SZ_256K;
-                } else if (cpu_is_omap34xx()) {
+                if (cpu_is_omap34xx()) {
                         omap_sram_start = OMAP3_SRAM_PA;
                         omap_sram_size = 0x10000; /* 64K */
-                } else if (cpu_is_omap44xx()) {
-                        omap_sram_start = OMAP4_SRAM_PA;
-                        omap_sram_size = 0xe000; /* 56K */
-                } else if (soc_is_omap54xx()) {
-                        omap_sram_start = OMAP5_SRAM_PA;
-                        omap_sram_size = SZ_128K; /* 128KB */
                 } else {
                         omap_sram_start = OMAP2_SRAM_PA;
                         if (cpu_is_omap242x())
@@ -148,12 +124,6 @@ static void __init omap2_map_sram(void)
 {
         int cached = 1;
 
-#ifdef CONFIG_OMAP4_ERRATA_I688
-        if (cpu_is_omap44xx()) {
-                omap_sram_start += PAGE_SIZE;
-                omap_sram_size -= SZ_16K;
-        }
-#endif
         if (cpu_is_omap34xx()) {
                 /*
                  * SRAM must be marked as non-cached on OMAP3 since the
@@ -285,11 +255,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif /* CONFIG_ARCH_OMAP3 */
 
-static inline int am33xx_sram_init(void)
-{
-        return 0;
-}
-
 int __init omap_sram_init(void)
 {
         omap_detect_sram();
@@ -299,8 +264,6 @@ int __init omap_sram_init(void)
                 omap242x_sram_init();
         else if (cpu_is_omap2430())
                 omap243x_sram_init();
-        else if (soc_is_am33xx())
-                am33xx_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
 
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
index ca7277c2a9ee..948d3edefc38 100644
--- a/arch/arm/mach-omap2/sram.h
+++ b/arch/arm/mach-omap2/sram.h
@@ -74,10 +74,3 @@ static inline void omap_push_sram_idle(void) {}
  */
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP3_SRAM_PA           0x40200000
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA           0x40304000
-#define OMAP4_SRAM_VA           0xfe404000
-#else
-#define OMAP4_SRAM_PA           0x40300000
-#endif
-#define AM33XX_SRAM_PA          0x40300000
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 43d03fbf4c0b..4f61148ec168 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -141,7 +141,7 @@ static struct property device_disabled = {
         .value = "disabled",
 };
 
-static struct of_device_id omap_timer_match[] __initdata = {
+static const struct of_device_id omap_timer_match[] __initconst = {
         { .compatible = "ti,omap2420-timer", },
         { .compatible = "ti,omap3430-timer", },
         { .compatible = "ti,omap4430-timer", },
@@ -162,7 +162,7 @@ static struct of_device_id omap_timer_match[] __initdata = {
  * the timer node in device-tree as disabled, to prevent the kernel from
  * registering this timer as a platform device and so no one else can use it.
  */
-static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
+static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
                                                      const char *property)
 {
         struct device_node *np;
@@ -388,7 +388,7 @@ static u64 notrace dmtimer_read_sched_clock(void)
         return 0;
 }
 
-static struct of_device_id omap_counter_match[] __initdata = {
+static const struct of_device_id omap_counter_match[] __initconst = {
         { .compatible = "ti,omap-counter32k", },
         { }
 };
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index a4628a9e760c..be9ef834fa81 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -198,7 +198,7 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
                 loop_cnt++;
 
                 if (retries_cnt > 10) {
-                        pr_warning("%s: Retry count exceeded\n", __func__);
+                        pr_warn("%s: Retry count exceeded\n", __func__);
                         return -ETIMEDOUT;
                 }
 
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3ac8fe1d8213..3783b8625f0f 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -55,7 +55,7 @@ static LIST_HEAD(voltdm_list);
 unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
 {
         if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                 return 0;
         }
 
@@ -77,7 +77,7 @@ int voltdm_scale(struct voltagedomain *voltdm,
         unsigned long volt = 0;
 
         if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                 return -EINVAL;
         }
 
@@ -96,8 +96,8 @@ int voltdm_scale(struct voltagedomain *voltdm,
         }
 
         if (!volt) {
-                pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n",
-                           __func__, target_volt);
+                pr_warn("%s: not scaling. OPP voltage for %lu, not found.\n",
+                        __func__, target_volt);
                 return -EINVAL;
         }
 
@@ -122,7 +122,7 @@ void voltdm_reset(struct voltagedomain *voltdm)
         unsigned long target_volt;
 
         if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                 return;
         }
 
@@ -152,7 +152,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
                                 struct omap_volt_data **volt_data)
 {
         if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                 return;
         }
 
@@ -180,12 +180,12 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
         int i;
 
         if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                 return ERR_PTR(-EINVAL);
         }
 
         if (!voltdm->volt_data) {
-                pr_warning("%s: voltage table does not exist for vdd_%s\n",
+                pr_warn("%s: voltage table does not exist for vdd_%s\n",
                         __func__, voltdm->name);
                 return ERR_PTR(-ENODATA);
         }
@@ -214,7 +214,7 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
                                struct omap_voltdm_pmic *pmic)
 {
         if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                 return -EINVAL;
         }
 
@@ -237,7 +237,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
                                   int voltscale_method)
 {
         if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                 return;
         }
 
@@ -279,7 +279,7 @@ int __init omap_voltage_late_init(void)
 
                 sys_ck = clk_get(NULL, voltdm->sys_clk.name);
                 if (IS_ERR(sys_ck)) {
-                        pr_warning("%s: Could not get sys clk.\n", __func__);
+                        pr_warn("%s: Could not get sys clk.\n", __func__);
                         return -EINVAL;
                 }
                 voltdm->sys_clk.rate = clk_get_rate(sys_ck);
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 97d6607d447a..ff0a68cf7439 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -93,8 +93,8 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh)
                 udelay(oh->class->sysc->srst_udelay);
 
         if (c == MAX_MODULE_SOFTRESET_WAIT)
-                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
-                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+                pr_warn("%s: %s: softreset failed (waited %d usec)\n",
+                        __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
         else
                 pr_debug("%s: %s: softreset in %d usec\n", __func__,
                          oh->name, c);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 56edeab17b68..09d2a26985da 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -550,7 +550,7 @@ static int __init dns323_identify_rev(void)
                         break;
         }
         if (i >= 1000) {
-                pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
+                pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n");
                 return DNS323_REV_B1;
         }
         writel((3 << 21)        /* phy ID reg */ |
@@ -562,7 +562,7 @@ static int __init dns323_identify_rev(void)
                         break;
         }
         if (i >= 1000) {
-                pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
+                pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n");
                 return DNS323_REV_B1;
         }
         pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
@@ -577,8 +577,8 @@ static int __init dns323_identify_rev(void)
         case 0x0e10: /* MV88E1118 */
                 return DNS323_REV_C1;
         default:
-                pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
-                           reg & 0xffff);
+                pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
+                        reg & 0xffff);
         }
         return DNS323_REV_B1;
 }
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 6208d125c1b9..12086745c9fd 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -349,7 +349,7 @@ static void __init tsp2_init(void)
                         gpio_free(TSP2_RTC_GPIO);
         }
         if (tsp2_i2c_rtc.irq == 0)
-                pr_warning("tsp2_init: failed to get RTC IRQ\n");
+                pr_warn("tsp2_init: failed to get RTC IRQ\n");
         i2c_register_board_info(0, &tsp2_i2c_rtc, 1);
 
         /* register Terastation Pro II specific power-off method */
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9136797addb2..c725b7cb9875 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -314,7 +314,7 @@ static void __init qnap_ts209_init(void)
                         gpio_free(TS209_RTC_GPIO);
         }
         if (qnap_ts209_i2c_rtc.irq == 0)
-                pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
+                pr_warn("qnap_ts209_init: failed to get RTC IRQ\n");
         i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
 
         /* register tsx09 specific power-off method */
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 5c079d312015..cf2ab531cabc 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -302,7 +302,7 @@ static void __init qnap_ts409_init(void)
                         gpio_free(TS409_RTC_GPIO);
         }
         if (qnap_ts409_i2c_rtc.irq == 0)
-                pr_warning("qnap_ts409_init: failed to get RTC IRQ\n");
+                pr_warn("qnap_ts409_init: failed to get RTC IRQ\n");
         i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
         platform_device_register(&ts409_leds);
 
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index db16dae441e2..1b704d35cf5b 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -403,8 +403,8 @@ static void ts78xx_fpga_supports(void)
                 /* enable devices if magic matches */
                 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
                 case TS7800_FPGA_MAGIC:
-                        pr_warning("unrecognised FPGA revision 0x%.2x\n",
-                                        ts78xx_fpga.id & 0xff);
+                        pr_warn("unrecognised FPGA revision 0x%.2x\n",
+                                ts78xx_fpga.id & 0xff);
                         ts78xx_fpga.supports.ts_rtc.present = 1;
                         ts78xx_fpga.supports.ts_nand.present = 1;
                         ts78xx_fpga.supports.ts_rng.present = 1;
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 666094315ab1..ac7b3eabbd85 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -1071,9 +1071,47 @@ static struct resource pxa3xx_resource_ssp4[] = {
         },
 };
 
+/*
+ * PXA3xx SSP is basically equivalent to PXA27x.
+ * However, we need to register the device by the correct name in order to
+ * make the driver set the correct internal type, hence we provide specific
+ * platform_devices for each of them.
+ */
+struct platform_device pxa3xx_device_ssp1 = {
+        .name           = "pxa3xx-ssp",
+        .id             = 0,
+        .dev            = {
+                .dma_mask = &pxa27x_ssp1_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource       = pxa27x_resource_ssp1,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp1),
+};
+
+struct platform_device pxa3xx_device_ssp2 = {
+        .name           = "pxa3xx-ssp",
+        .id             = 1,
+        .dev            = {
+                .dma_mask = &pxa27x_ssp2_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource       = pxa27x_resource_ssp2,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp2),
+};
+
+struct platform_device pxa3xx_device_ssp3 = {
+        .name           = "pxa3xx-ssp",
+        .id             = 2,
+        .dev            = {
+                .dma_mask = &pxa27x_ssp3_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource       = pxa27x_resource_ssp3,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
+};
+
 struct platform_device pxa3xx_device_ssp4 = {
-        /* PXA3xx SSP is basically equivalent to PXA27x */
-        .name           = "pxa27x-ssp",
+        .name           = "pxa3xx-ssp",
         .id             = 3,
         .dev            = {
                 .dma_mask = &pxa3xx_ssp4_dma_mask,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 0f3fd0d65b12..4a13c32fb705 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -27,6 +27,9 @@ extern struct platform_device pxa25x_device_assp;
 extern struct platform_device pxa27x_device_ssp1;
 extern struct platform_device pxa27x_device_ssp2;
 extern struct platform_device pxa27x_device_ssp3;
+extern struct platform_device pxa3xx_device_ssp1;
+extern struct platform_device pxa3xx_device_ssp2;
+extern struct platform_device pxa3xx_device_ssp3;
 extern struct platform_device pxa3xx_device_ssp4;
 
 extern struct platform_device pxa25x_device_pwm0;
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 630fa916bbc6..04b013fbc98f 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -61,7 +61,7 @@ EXPORT_SYMBOL(get_clock_tick_rate);
 /*
  * For non device-tree builds, keep legacy timer init
  */
-void pxa_timer_init(void)
+void __init pxa_timer_init(void)
 {
         pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000),
                             get_clock_tick_rate());
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 593ccd35ca97..edcbd9c0bcb2 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -84,10 +84,10 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
         INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
-        INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
-        INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
-        INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
-        INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa3xx-ssp.0", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa3xx-ssp.1", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa3xx-ssp.2", NULL),
+        INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa3xx-ssp.3", NULL),
         INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
@@ -452,9 +452,9 @@ static struct platform_device *devices[] __initdata = {
         &pxa_device_asoc_platform,
         &sa1100_device_rtc,
         &pxa_device_rtc,
-        &pxa27x_device_ssp1,
-        &pxa27x_device_ssp2,
-        &pxa27x_device_ssp3,
+        &pxa3xx_device_ssp1,
+        &pxa3xx_device_ssp2,
+        &pxa3xx_device_ssp3,
         &pxa3xx_device_ssp4,
         &pxa27x_device_pwm0,
         &pxa27x_device_pwm1,
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index c437a9941726..6d8bbf7d39d8 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,8 @@ static const char * const qcom_dt_match[] __initconst = {
         "qcom,apq8064",
         "qcom,apq8074-dragonboard",
         "qcom,apq8084",
+        "qcom,ipq8062",
+        "qcom,ipq8064",
         "qcom,msm8660-surf",
         "qcom,msm8960-cdp",
         NULL
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d1686696ca41..ac5803cac98d 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -4,6 +4,7 @@ config ARCH_ROCKCHIP
         select PINCTRL_ROCKCHIP
         select ARCH_HAS_RESET_CONTROLLER
         select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
         select ARM_GIC
         select CACHE_L2X0
         select HAVE_ARM_ARCH_TIMER
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index ad5316ae524e..9eb22297cbe1 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -32,7 +32,6 @@ config CPU_S3C2410
         select S3C2410_DMA if S3C24XX_DMA
         select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
         select S3C2410_PM if PM
-        select SAMSUNG_WDT_RESET
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
@@ -76,7 +75,6 @@ config CPU_S3C2442
 config CPU_S3C244X
         def_bool y
         depends on CPU_S3C2440 || CPU_S3C2442
-        select SAMSUNG_WDT_RESET
 
 config CPU_S3C2443
         bool "SAMSUNG S3C2443"
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 44fa95df9262..bf50328107bd 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -51,7 +51,6 @@
 #include <plat/devs.h>
 #include <plat/cpu-freq.h>
 #include <plat/pwm-core.h>
-#include <plat/watchdog-reset.h>
 
 #include "common.h"
 
@@ -513,7 +512,6 @@ struct platform_device s3c2443_device_dma = {
 void __init s3c2410_init_clocks(int xtal)
 {
         s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
-        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 #endif
 
@@ -535,7 +533,6 @@ void __init s3c2416_init_clocks(int xtal)
 void __init s3c2440_init_clocks(int xtal)
 {
         s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
-        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 #endif
 
@@ -543,7 +540,6 @@ void __init s3c2440_init_clocks(int xtal)
 void __init s3c2442_init_clocks(int xtal)
 {
         s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
-        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 #endif
 
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ac3ff12a0601..c7ac7e61a22e 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -22,7 +22,6 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -38,7 +37,6 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
@@ -53,7 +51,6 @@ extern void s3c2416_map_io(void);
 extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
-extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2416_init_irq(void);
 
 extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -67,7 +64,6 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c244x_init_uarts NULL
 #endif
@@ -98,7 +94,6 @@ extern void s3c2443_map_io(void);
 extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
-extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
index c3feff3c0488..ffe37bdb9f59 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
@@ -42,8 +42,6 @@
 #define S3C2443_URSTCON                 S3C2443_CLKREG(0x88)
 #define S3C2443_UCLKCON                 S3C2443_CLKREG(0x8C)
 
-#define S3C2443_SWRST_RESET             (0x533c2443)
-
 #define S3C2443_PLLCON_OFF              (1<<24)
 
 #define S3C2443_CLKSRC_EPLLREF_XTAL     (2<<7)
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 5157e250dd13..3e63777a109f 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -247,5 +247,4 @@ MACHINE_START(AML_M5900, "AML_M5900")
         .init_irq       = s3c2410_init_irq,
         .init_machine   = amlm5900_init,
         .init_time      = amlm5900_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index e053581cab0b..d03df0df01fa 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -430,5 +430,4 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .init_machine   = anubis_init,
         .init_irq       = s3c2440_init_irq,
         .init_time      = anubis_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 9db768f448a5..9ae170fef2a7 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -218,5 +218,4 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .init_machine   = at2440evb_init,
         .init_irq       = s3c2440_init_irq,
         .init_time      = at2440evb_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index f9112b801a33..ed07cf392d4b 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -591,5 +591,4 @@ MACHINE_START(BAST, "Simtec-BAST")
         .init_irq       = s3c2410_init_irq,
         .init_machine   = bast_init,
         .init_time      = bast_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index fc3a08d0cb3f..6d1e0b9c5b27 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -597,5 +597,4 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         .init_irq       = s3c2442_init_irq,
         .init_machine   = gta02_machine_init,
         .init_time      = gta02_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index c9a99bbad545..d35ddc1d9991 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -747,5 +747,4 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .init_irq       = s3c2410_init_irq,
         .init_machine   = h1940_init,
         .init_time      = h1940_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 7804d3c6991b..7d99fe8f6157 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -670,5 +670,4 @@ MACHINE_START(JIVE, "JIVE")
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
         .init_time      = jive_init_time,
-        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 5cc40ec1d254..a8521684a7f5 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -695,5 +695,4 @@ MACHINE_START(MINI2440, "MINI2440")
         .init_machine   = mini2440_init,
         .init_irq       = s3c2440_init_irq,
         .init_time      = mini2440_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 3ac2a54348d6..171c1f11fd22 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -599,7 +599,6 @@ MACHINE_START(N30, "Acer-N30")
         .init_machine   = n30_init,
         .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
-        .restart        = s3c2410_restart,
 MACHINE_END
 
 MACHINE_START(N35, "Acer-N35")
@@ -610,5 +609,4 @@ MACHINE_START(N35, "Acer-N35")
         .init_machine   = n30_init,
         .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index c82c281ce351..2a61d13dcd6c 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -159,5 +159,4 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .init_machine   = nexcoder_init,
         .init_irq       = s3c2440_init_irq,
         .init_time      = nexcoder_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 189147b80eca..2f6fdc326835 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -412,5 +412,4 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         .init_irq       = s3c2440_init_irq,
         .init_machine   = osiris_init,
         .init_time      = osiris_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 45833001186d..345a484b93cc 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -122,5 +122,4 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .init_machine   = otom11_init,
         .init_irq       = s3c2410_init_irq,
         .init_time      = otom11_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 228c9094519d..984516e8307a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -352,5 +352,4 @@ MACHINE_START(QT2410, "QT2410")
         .init_irq       = s3c2410_init_irq,
         .init_machine   = qt2410_machine_init,
         .init_time      = qt2410_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index e2c6541909c1..c3f2682d0c62 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -812,5 +812,4 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .init_irq       = s3c2442_init_irq,
         .init_machine = rx1950_init_machine,
         .init_time      = rx1950_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 6e749ec3a2ea..cf55196f89ca 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -215,5 +215,4 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .init_irq       = s3c2440_init_irq,
         .init_machine   = rx3715_init_machine,
         .init_time      = rx3715_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
index e4dcb9aa2ca2..f886478b88c5 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -51,5 +51,4 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
         .map_io         = s3c2416_dt_map_io,
         .init_irq       = irqchip_init,
         .init_machine   = s3c2416_dt_machine_init,
-        .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index 419fadd6e446..27dd6605e395 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -124,5 +124,4 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         .init_irq       = s3c2410_init_irq,
         .init_machine   = smdk2410_init,
         .init_time      = smdk2410_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 10726bf84920..586e4a3b8d5d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -138,7 +138,6 @@ MACHINE_START(S3C2413, "S3C2413")
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
         .init_time      = samsung_timer_init,
-        .restart        = s3c2412_restart,
 MACHINE_END
 
 MACHINE_START(SMDK2412, "SMDK2412")
@@ -150,7 +149,6 @@ MACHINE_START(SMDK2412, "SMDK2412")
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
         .init_time      = samsung_timer_init,
-        .restart        = s3c2412_restart,
 MACHINE_END
 
 MACHINE_START(SMDK2413, "SMDK2413")
@@ -162,5 +160,4 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
         .init_time      = smdk2413_init_time,
-        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 24189e8e8560..86394f72d29e 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -262,5 +262,4 @@ MACHINE_START(SMDK2416, "SMDK2416")
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
         .init_time      = smdk2416_init_time,
-        .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 5fb89c0ae17a..9bb96bfbb420 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -185,5 +185,4 @@ MACHINE_START(S3C2440, "SMDK2440")
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
         .init_time      = smdk2440_init_time,
-        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 0ed77614dcfe..87fe5c5b8073 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -150,5 +150,4 @@ MACHINE_START(SMDK2443, "SMDK2443")
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
         .init_time      = smdk2443_init_time,
-        .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index c616ca2d409e..2deb62f92fb2 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -157,5 +157,4 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .init_irq       = s3c2410_init_irq,
         .init_machine   = tct_hammer_init,
         .init_time      = tct_hammer_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index f88c584c3001..89f32bd3f01b 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -340,5 +340,4 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .init_machine   = vr1000_init,
         .init_irq       = s3c2410_init_irq,
         .init_time      = vr1000_init_time,
-        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 9d4f64750698..b4460d5f7011 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -165,5 +165,4 @@ MACHINE_START(VSTMS, "VSTMS")
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
         .init_time      = vstms_init_time,
-        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 5ffe828cd659..2a6985a4a0ff 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -42,7 +42,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/watchdog-reset.h>
 
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
@@ -135,15 +134,3 @@ int __init s3c2410a_init(void)
         s3c2410_dev.bus = &s3c2410a_subsys;
         return s3c2410_init();
 }
-
-void s3c2410_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (mode == REBOOT_SOFT) {
-                soft_restart(0);
-        }
-
-        samsung_wdt_reset();
-
-        /* we'll take a jump through zero as a poor second */
-        soft_restart(0);
-}
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 569f3f5a6c71..ecf2c77ab88b 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -48,9 +48,6 @@
 #include "regs-dsc.h"
 #include "s3c2412-power.h"
 
-#define S3C2412_SWRST                   (S3C24XX_VA_CLKPWR + 0x30)
-#define S3C2412_SWRST_RESET             (0x533C2412)
-
 #ifndef CONFIG_CPU_S3C2412_ONLY
 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
 
@@ -128,26 +125,6 @@ static void s3c2412_idle(void)
         cpu_do_idle();
 }
 
-void s3c2412_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (mode == REBOOT_SOFT)
-                soft_restart(0);
-
-        /* errata "Watch-dog/Software Reset Problem" specifies that
-         * this reset must be done with the SYSCLK sourced from
-         * EXTCLK instead of FOUT to avoid a glitch in the reset
-         * mechanism.
-         *
-         * See the watchdog section of the S3C2412 manual for more
-         * information on this fix.
-         */
-
-        __raw_writel(0x00, S3C2412_CLKSRC);
-        __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
-
-        mdelay(1);
-}
-
 /* s3c2412_map_io
  *
  * register the standard cpu IO areas, and any passed in from the
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 9fe260ae11e1..bfd4da86deb8 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -81,14 +81,6 @@ static struct device s3c2416_dev = {
         .bus            = &s3c2416_subsys,
 };
 
-void s3c2416_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (mode == REBOOT_SOFT)
-                soft_restart(0);
-
-        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
-}
-
 int __init s3c2416_init(void)
 {
         printk(KERN_INFO "S3C2416: Initializing architecture\n");
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index c7a804d0348e..87b6b89d8ee7 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -61,14 +61,6 @@ static struct device s3c2443_dev = {
         .bus            = &s3c2443_subsys,
 };
 
-void s3c2443_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (mode == REBOOT_SOFT)
-                soft_restart(0);
-
-        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
-}
-
 int __init s3c2443_init(void)
 {
         printk("S3C2443: Initialising architecture\n");
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index d1c3e65785a1..177f97802745 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -42,7 +42,6 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/nand-core.h>
-#include <plat/watchdog-reset.h>
 
 #include "common.h"
 #include "regs-dsc.h"
@@ -137,14 +136,3 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
         .suspend        = s3c244x_suspend,
         .resume         = s3c244x_resume,
 };
-
-void s3c244x_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (mode == REBOOT_SOFT)
-                soft_restart(0);
-
-        samsung_wdt_reset();
-
-        /* we'll take a jump through zero as a poor second */
-        soft_restart(0);
-}
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 5c45aae675b6..16547f2641a3 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -440,8 +440,3 @@ void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
         /* if all else fails, or mode was for soft, jump to 0 */
         soft_restart(0);
 }
-
-void __init s3c64xx_init_late(void)
-{
-        s3c64xx_pm_late_initcall();
-}
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 7043e7a3a67e..9eb864412911 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -23,7 +23,6 @@ void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
 void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
-void s3c64xx_init_late(void);
 
 void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
         unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
@@ -52,12 +51,6 @@ extern void s3c6410_map_io(void);
 #define s3c6410_init NULL
 #endif
 
-#ifdef CONFIG_PM
-int __init s3c64xx_pm_late_initcall(void);
-#else
-static inline int s3c64xx_pm_late_initcall(void) { return 0; }
-#endif
-
 #ifdef CONFIG_S3C64XX_PL080
 extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
 extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 60576dfbea8d..6224c67f5061 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -233,7 +233,6 @@ MACHINE_START(ANW6410, "A&W6410")
         .init_irq       = s3c6410_init_irq,
         .map_io         = anw6410_map_io,
         .init_machine   = anw6410_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index fe116334afda..10b913baab28 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -857,7 +857,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
         .init_irq       = s3c6410_init_irq,
         .map_io         = crag6410_map_io,
         .init_machine   = crag6410_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 19e8feb908fd..e4b087c58ee6 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -277,7 +277,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
         .init_irq       = s3c6410_init_irq,
         .map_io         = hmt_map_io,
         .init_machine   = hmt_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 9cbc07602ef3..ab61af50bfb9 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -366,7 +366,6 @@ MACHINE_START(MINI6410, "MINI6410")
         .init_irq       = s3c6410_init_irq,
         .map_io         = mini6410_map_io,
         .init_machine   = mini6410_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 4bae7dc49eea..80cb1446f69f 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -103,7 +103,6 @@ MACHINE_START(NCP, "NCP")
         .init_irq       = s3c6410_init_irq,
         .map_io         = ncp_map_io,
         .init_machine   = ncp_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index fbad2af1ef16..85fa9598b980 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -335,7 +335,6 @@ MACHINE_START(REAL6410, "REAL6410")
         .init_irq       = s3c6410_init_irq,
         .map_io         = real6410_map_io,
         .init_machine   = real6410_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index dec4c08e834f..33224ab36fac 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -156,7 +156,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
         .init_irq       = s3c6410_init_irq,
         .map_io         = smartq_map_io,
         .init_machine   = smartq5_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 27b322069c7d..fc7fece22fb0 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -172,7 +172,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
         .init_irq       = s3c6410_init_irq,
         .map_io         = smartq_map_io,
         .init_machine   = smartq7_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 910749768340..6f425126a735 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -92,7 +92,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
         .init_irq       = s3c6400_init_irq,
         .map_io         = smdk6400_map_io,
         .init_machine   = smdk6400_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 1dc86d76b530..661eb662d051 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -705,7 +705,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
         .init_irq       = s3c6410_init_irq,
         .map_io         = smdk6410_map_io,
         .init_machine   = smdk6410_machine_init,
-        .init_late      = s3c64xx_init_late,
         .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 6b37694fa335..aaf7bea4032f 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -347,10 +347,3 @@ static __init int s3c64xx_pm_initcall(void)
         return 0;
 }
 arch_initcall(s3c64xx_pm_initcall);
-
-int __init s3c64xx_pm_late_initcall(void)
-{
-        pm_genpd_poweroff_unused();
-
-        return 0;
-}
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 123163dd2ab0..21b4b13c5ab7 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -24,9 +24,8 @@
 
 #include <plat/pm-common.h>
 
-#include <mach/regs-clock.h>
-
 #include "common.h"
+#include "regs-clock.h"
 
 static struct sleep_save s5pv210_core_save[] = {
         /* Clock ETC */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h
index b14ffcd7f6cc..4640f0f03c12 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/regs-clock.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/regs-clock.h
- *
+/*
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c
index 53feff33d129..43eb1eaea0c9 100644
--- a/arch/arm/mach-s5pv210/s5pv210.c
+++ b/arch/arm/mach-s5pv210/s5pv210.c
@@ -18,9 +18,9 @@
 #include <asm/system_misc.h>
 
 #include <plat/map-base.h>
-#include <mach/regs-clock.h>
 
 #include "common.h"
+#include "regs-clock.h"
 
 static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
                                         int depth, void *data)
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 04f9784ff0ed..c6f6ed1cbed0 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -58,6 +58,7 @@ config SA1100_H3100
         bool "Compaq iPAQ H3100"
         select ARM_SA1110_CPUFREQ
         select HTC_EGPIO
+        select MFD_IPAQ_MICRO
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
           H3100 handheld computer.  Information about this machine and the
@@ -69,6 +70,7 @@ config SA1100_H3600
         bool "Compaq iPAQ H3600/H3700"
         select ARM_SA1110_CPUFREQ
         select HTC_EGPIO
+        select MFD_IPAQ_MICRO
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
           H3600 handheld computer.  Information about this machine and the
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index c79bf467fb7f..b1d4faa12f9a 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -25,6 +25,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/h3xxx.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
@@ -244,9 +245,23 @@ static struct platform_device h3xxx_keys = {
         },
 };
 
+static struct resource h3xxx_micro_resources[] = {
+        DEFINE_RES_MEM(0x80010000, SZ_4K),
+        DEFINE_RES_MEM(0x80020000, SZ_4K),
+        DEFINE_RES_IRQ(IRQ_Ser1UART),
+};
+
+struct platform_device h3xxx_micro_asic = {
+        .name = "ipaq-h3xxx-micro",
+        .id = -1,
+        .resource = h3xxx_micro_resources,
+        .num_resources = ARRAY_SIZE(h3xxx_micro_resources),
+};
+
 static struct platform_device *h3xxx_devices[] = {
         &h3xxx_egpio,
         &h3xxx_keys,
+        &h3xxx_micro_asic,
 };
 
 void __init h3xxx_mach_init(void)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index e15dff790dbb..21f457b56c01 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,30 @@
 config ARCH_SHMOBILE
         bool
 
+config PM_RCAR
+        bool
+
+config PM_RMOBILE
+        bool
+
+config ARCH_RCAR_GEN1
+        bool
+        select PM_RCAR if PM || SMP
+        select RENESAS_INTC_IRQPIN
+        select SYS_SUPPORTS_SH_TMU
+
+config ARCH_RCAR_GEN2
+        bool
+        select PM_RCAR if PM || SMP
+        select RENESAS_IRQC
+        select SYS_SUPPORTS_SH_CMT
+
+config ARCH_RMOBILE
+        bool
+        select PM_RMOBILE if PM && !ARCH_SHMOBILE_MULTI
+        select SYS_SUPPORTS_SH_CMT
+        select SYS_SUPPORTS_SH_TMU
+
 menuconfig ARCH_SHMOBILE_MULTI
         bool "Renesas ARM SoCs" if ARCH_MULTI_V7
         depends on MMU
@@ -26,26 +50,28 @@ config ARCH_R7S72100
         bool "RZ/A1H (R7S72100)"
         select SYS_SUPPORTS_SH_MTU2
 
+config ARCH_R8A7740
+        bool "R-Mobile A1 (R8A77400)"
+        select ARCH_RMOBILE
+        select RENESAS_INTC_IRQPIN
+
 config ARCH_R8A7779
         bool "R-Car H1 (R8A77790)"
-        select RENESAS_INTC_IRQPIN
-        select SYS_SUPPORTS_SH_TMU
+        select ARCH_RCAR_GEN1
 
 config ARCH_R8A7790
         bool "R-Car H2 (R8A77900)"
-        select RENESAS_IRQC
-        select SYS_SUPPORTS_SH_CMT
+        select ARCH_RCAR_GEN2
 
 config ARCH_R8A7791
-        bool "R-Car M2 (R8A77910)"
-        select RENESAS_IRQC
-        select SYS_SUPPORTS_SH_CMT
+        bool "R-Car M2-W (R8A77910)"
+        select ARCH_RCAR_GEN2
 
-comment "Renesas ARM SoCs Board Type"
+config ARCH_R8A7794
+        bool "R-Car E2 (R8A77940)"
+        select ARCH_RCAR_GEN2
 
-config MACH_GENMAI
-        bool "Genmai board"
-        depends on ARCH_R7S72100
+comment "Renesas ARM SoCs Board Type"
 
 config MACH_KOELSCH
         bool "Koelsch board"
@@ -71,92 +97,62 @@ comment "Renesas ARM SoCs System Type"
 
 config ARCH_SH7372
         bool "SH-Mobile AP4 (SH7372)"
+        select ARCH_RMOBILE
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_CPU_SUSPEND if PM || CPU_IDLE
-        select CPU_V7
-        select SH_CLK_CPG
-        select SYS_SUPPORTS_SH_CMT
-        select SYS_SUPPORTS_SH_TMU
+        select SH_INTC
 
 config ARCH_SH73A0
         bool "SH-Mobile AG5 (R8A73A00)"
+        select ARCH_RMOBILE
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select CPU_V7
         select I2C
-        select SH_CLK_CPG
+        select SH_INTC
         select RENESAS_INTC_IRQPIN
-        select SYS_SUPPORTS_SH_CMT
-        select SYS_SUPPORTS_SH_TMU
 
 config ARCH_R8A73A4
         bool "R-Mobile APE6 (R8A73A40)"
+        select ARCH_RMOBILE
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select CPU_V7
-        select SH_CLK_CPG
         select RENESAS_IRQC
-        select SYS_SUPPORTS_SH_CMT
-        select SYS_SUPPORTS_SH_TMU
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
+        select ARCH_RMOBILE
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select CPU_V7
-        select SH_CLK_CPG
         select RENESAS_INTC_IRQPIN
-        select SYS_SUPPORTS_SH_CMT
-        select SYS_SUPPORTS_SH_TMU
 
 config ARCH_R8A7778
         bool "R-Car M1A (R8A77781)"
+        select ARCH_RCAR_GEN1
         select ARCH_WANT_OPTIONAL_GPIOLIB
-        select CPU_V7
-        select SH_CLK_CPG
         select ARM_GIC
-        select SYS_SUPPORTS_SH_TMU
-        select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7779
         bool "R-Car H1 (R8A77790)"
+        select ARCH_RCAR_GEN1
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select CPU_V7
-        select SH_CLK_CPG
-        select RENESAS_INTC_IRQPIN
-        select SYS_SUPPORTS_SH_TMU
 
 config ARCH_R8A7790
         bool "R-Car H2 (R8A77900)"
+        select ARCH_RCAR_GEN2
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select CPU_V7
         select MIGHT_HAVE_PCI
-        select SH_CLK_CPG
-        select RENESAS_IRQC
-        select SYS_SUPPORTS_SH_CMT
         select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 
 config ARCH_R8A7791
-        bool "R-Car M2 (R8A77910)"
+        bool "R-Car M2-W (R8A77910)"
+        select ARCH_RCAR_GEN2
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select CPU_V7
         select MIGHT_HAVE_PCI
-        select SH_CLK_CPG
-        select RENESAS_IRQC
-        select SYS_SUPPORTS_SH_CMT
         select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 
-config ARCH_R7S72100
-        bool "RZ/A1H (R7S72100)"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_GIC
-        select CPU_V7
-        select SH_CLK_CPG
-        select SYS_SUPPORTS_SH_MTU2
-
 comment "Renesas ARM SoCs Board Type"
 
 config MACH_APE6EVM
@@ -195,21 +191,6 @@ config MACH_ARMADILLO800EVA
         select SND_SOC_WM8978 if SND_SIMPLE_CARD
         select USE_OF
 
-config MACH_ARMADILLO800EVA_REFERENCE
-        bool "Armadillo-800 EVA board - Reference Device Tree Implementation"
-        depends on ARCH_R8A7740
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select SMSC_PHY if SH_ETH
-        select SND_SOC_WM8978 if SND_SIMPLE_CARD
-        select USE_OF
-        ---help---
-           Use reference implementation of Armadillo800 EVA board support
-           which makes greater use of device tree at the expense
-           of not supporting a number of devices.
-
-           This is intended to aid developers
-
 config MACH_BOCKW
         bool "BOCK-W platform"
         depends on ARCH_R8A7778
@@ -232,11 +213,6 @@ config MACH_BOCKW_REFERENCE
 
            This is intended to aid developers
 
-config MACH_GENMAI
-        bool "Genmai board"
-        depends on ARCH_R7S72100
-        select USE_OF
-
 config MACH_MARZEN
         bool "MARZEN board"
         depends on ARCH_R8A7779
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe3878a1a69a..e20f2786ec72 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -2,21 +2,19 @@
 # Makefile for the linux kernel.
 #
 
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/mach-shmobile/include
-
 # Common objects
 obj-y                           := timer.o console.o
 
 # CPU objects
-obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o intc-sh7372.o
-obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o intc-sh73a0.o
+obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o intc-sh7372.o pm-sh7372.o
+obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o
 obj-$(CONFIG_ARCH_R8A73A4)      += setup-r8a73a4.o
-obj-$(CONFIG_ARCH_R8A7740)      += setup-r8a7740.o
+obj-$(CONFIG_ARCH_R8A7740)      += setup-r8a7740.o pm-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7778)      += setup-r8a7778.o
-obj-$(CONFIG_ARCH_R8A7779)      += setup-r8a7779.o
-obj-$(CONFIG_ARCH_R8A7790)      += setup-r8a7790.o
-obj-$(CONFIG_ARCH_R8A7790)      += setup-r8a7790.o setup-rcar-gen2.o
-obj-$(CONFIG_ARCH_R8A7791)      += setup-r8a7791.o setup-rcar-gen2.o
+obj-$(CONFIG_ARCH_R8A7779)      += setup-r8a7779.o pm-r8a7779.o
+obj-$(CONFIG_ARCH_R8A7790)      += setup-r8a7790.o pm-r8a7790.o
+obj-$(CONFIG_ARCH_R8A7791)      += setup-r8a7791.o pm-r8a7791.o
+obj-$(CONFIG_ARCH_R8A7794)      += setup-r8a7794.o
 obj-$(CONFIG_ARCH_EMEV2)        += setup-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)     += setup-r7s72100.o
 
@@ -31,13 +29,13 @@ obj-$(CONFIG_ARCH_R8A7778)	+= clock-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)      += clock-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)      += clock-r8a7790.o
 obj-$(CONFIG_ARCH_R8A7791)      += clock-r8a7791.o
-obj-$(CONFIG_ARCH_R7S72100)     += clock-r7s72100.o
 endif
 
 # CPU reset vector handling objects
 cpu-y                           := platsmp.o headsmp.o
-cpu-$(CONFIG_ARCH_R8A7790)      += platsmp-apmu.o
-cpu-$(CONFIG_ARCH_R8A7791)      += platsmp-apmu.o
+
+# Shared SoC family objects
+obj-$(CONFIG_ARCH_RCAR_GEN2)    += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
 
 # SMP objects
 smp-y                           := $(cpu-y)
@@ -51,19 +49,14 @@ smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o headsmp-scu.o platsmp-scu.o
 obj-$(CONFIG_SUSPEND)           += suspend.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
-obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o pm-rmobile.o
-obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
-obj-$(CONFIG_ARCH_R8A7740)      += pm-r8a7740.o pm-rmobile.o
-obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o pm-rcar.o
-obj-$(CONFIG_ARCH_R8A7790)      += pm-r8a7790.o pm-rcar.o $(cpu-y)
-obj-$(CONFIG_ARCH_R8A7791)      += pm-r8a7791.o pm-rcar.o $(cpu-y)
+obj-$(CONFIG_PM_RCAR)           += pm-rcar.o
+obj-$(CONFIG_PM_RMOBILE)        += pm-rmobile.o
 
-# IRQ objects
-obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
+# special sh7372 handling for IRQ objects and low level sleep code
+obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o sleep-sh7372.o
 
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
-obj-$(CONFIG_MACH_GENMAI)       += board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager-reference.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen-reference.o
@@ -73,11 +66,9 @@ obj-$(CONFIG_MACH_APE6EVM_REFERENCE)	+= board-ape6evm-reference.o
 obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
 obj-$(CONFIG_MACH_BOCKW)        += board-bockw.o
 obj-$(CONFIG_MACH_BOCKW_REFERENCE)      += board-bockw-reference.o
-obj-$(CONFIG_MACH_GENMAI)       += board-genmai.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
-obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
 obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index ebf97d4bcfd8..de9a23852fc8 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -3,10 +3,8 @@ loadaddr-y	:=
 loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
 loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
-loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
-loadaddr-$(CONFIG_MACH_GENMAI) += 0x08008000
 loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
 loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
index 2f7723e5fe91..a6503d8c77de 100644
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -50,7 +50,6 @@ static void __init ape6evm_add_standard_devices(void)
 
         r8a73a4_add_dt_devices();
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
 }
 
 static const char *ape6evm_boards_compat_dt[] __initdata = {
@@ -59,7 +58,8 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-        .init_early     = r8a73a4_init_early,
+        .init_early     = shmobile_init_delay,
         .init_machine   = ape6evm_add_standard_devices,
+        .init_late      = shmobile_init_late,
         .dt_compat      = ape6evm_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 1585b8830b13..b222f68d55b7 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -283,7 +283,8 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-        .init_early     = r8a73a4_init_early,
+        .init_early     = shmobile_init_delay,
         .init_machine   = ape6evm_add_standard_devices,
+        .init_late      = shmobile_init_late,
         .dt_compat      = ape6evm_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
deleted file mode 100644
index 84bc6cb6d5aa..000000000000
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * armadillo 800 eva board support
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-
-#include <asm/mach/arch.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include "common.h"
-#include "r8a7740.h"
-
-/*
- * CON1         Camera Module
- * CON2         Extension Bus
- * CON3         HDMI Output
- * CON4         Composite Video Output
- * CON5         H-UDI JTAG
- * CON6         ARM JTAG
- * CON7         SD1
- * CON8         SD2
- * CON9         RTC BackUp
- * CON10        Monaural Mic Input
- * CON11        Stereo Headphone Output
- * CON12        Audio Line Output(L)
- * CON13        Audio Line Output(R)
- * CON14        AWL13 Module
- * CON15        Extension
- * CON16        LCD1
- * CON17        LCD2
- * CON19        Power Input
- * CON20        USB1
- * CON21        USB2
- * CON22        Serial
- * CON23        LAN
- * CON24        USB3
- * LED1         Camera LED (Yellow)
- * LED2         Power LED (Green)
- * LED3-LED6    User LED (Yellow)
- * LED7         LAN link LED (Green)
- * LED8         LAN activity LED (Yellow)
- */
-
-/*
- * DipSwitch
- *
- *                    SW1
- *
- * -12345678-+---------------+----------------------------
- *  1        | boot          | hermit
- *  0        | boot          | OS auto boot
- * -12345678-+---------------+----------------------------
- *   00      | boot device   | eMMC
- *   10      | boot device   | SDHI0 (CON7)
- *   01      | boot device   | -
- *   11      | boot device   | Extension Buss (CS0)
- * -12345678-+---------------+----------------------------
- *     0     | Extension Bus | D8-D15 disable, eMMC enable
- *     1     | Extension Bus | D8-D15 enable,  eMMC disable
- * -12345678-+---------------+----------------------------
- *      0    | SDHI1         | COM8 disable, COM14 enable
- *      1    | SDHI1         | COM8 enable,  COM14 disable
- * -12345678-+---------------+----------------------------
- *       0   | USB0          | COM20 enable,  COM24 disable
- *       1   | USB0          | COM20 disable, COM24 enable
- * -12345678-+---------------+----------------------------
- *        00 | JTAG          | SH-X2
- *        10 | JTAG          | ARM
- *        01 | JTAG          | -
- *        11 | JTAG          | Boundary Scan
- *-----------+---------------+----------------------------
- */
-
-/*
- * FSI-WM8978
- *
- * this command is required when playback.
- *
- * # amixer set "Headphone" 50
- *
- * this command is required when capture.
- *
- * # amixer set "Input PGA" 15
- * # amixer set "Left Input Mixer MicP" on
- * # amixer set "Left Input Mixer MicN" on
- * # amixer set "Right Input Mixer MicN" on
- * # amixer set "Right Input Mixer MicP" on
- */
-
-/*
- * USB function
- *
- * When you use USB Function,
- * set SW1.6 ON, and connect cable to CN24.
- *
- * USBF needs workaround on R8A7740 chip.
- * These are a little bit complex.
- * see
- *      usbhsf_power_ctrl()
- */
-
-static void __init eva_clock_init(void)
-{
-        struct clk *system      = clk_get(NULL, "system_clk");
-        struct clk *xtal1       = clk_get(NULL, "extal1");
-        struct clk *usb24s      = clk_get(NULL, "usb24s");
-        struct clk *fsibck      = clk_get(NULL, "fsibck");
-
-        if (IS_ERR(system)      ||
-            IS_ERR(xtal1)       ||
-            IS_ERR(usb24s)      ||
-            IS_ERR(fsibck)) {
-                pr_err("armadillo800eva board clock init failed\n");
-                goto clock_error;
-        }
-
-        /* armadillo 800 eva extal1 is 24MHz */
-        clk_set_rate(xtal1, 24000000);
-
-        /* usb24s use extal1 (= system) clock (= 24MHz) */
-        clk_set_parent(usb24s, system);
-
-        /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
-        clk_set_rate(fsibck, 12288000);
-
-clock_error:
-        if (!IS_ERR(system))
-                clk_put(system);
-        if (!IS_ERR(xtal1))
-                clk_put(xtal1);
-        if (!IS_ERR(usb24s))
-                clk_put(usb24s);
-        if (!IS_ERR(fsibck))
-                clk_put(fsibck);
-}
-
-/*
- * board init
- */
-static void __init eva_init(void)
-{
-        r8a7740_clock_init(MD_CK0 | MD_CK2);
-        eva_clock_init();
-
-        r8a7740_meram_workaround();
-
-#ifdef CONFIG_CACHE_L2X0
-        /* Shared attribute override enable, 32K*8way */
-        l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
-
-        r8a7740_add_standard_devices_dt();
-
-        r8a7740_pm_init();
-}
-
-#define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(enum reboot_mode mode, const char *cmd)
-{
-        /* Do soft power on reset */
-        writel(1 << 31, RESCNT2);
-}
-
-static const char *eva_boards_compat_dt[] __initdata = {
-        "renesas,armadillo800eva-reference",
-        NULL,
-};
-
-DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
-        .map_io         = r8a7740_map_io,
-        .init_early     = shmobile_init_delay,
-        .init_irq       = r8a7740_init_irq_of,
-        .init_machine   = eva_init,
-        .init_late      = shmobile_init_late,
-        .dt_compat      = eva_boards_compat_dt,
-        .restart        = eva_restart,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 6dbaad611a92..e70983534403 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1231,6 +1231,10 @@ clock_error:
 #define GPIO_PORT8CR    IOMEM(0xe6050008)
 static void __init eva_init(void)
 {
+        static struct pm_domain_device domain_devices[] __initdata = {
+                { "A4LC", &lcdc0_device },
+                { "A4LC", &hdmi_lcdc_device },
+        };
         struct platform_device *usb = NULL;
 
         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -1316,8 +1320,8 @@ static void __init eva_init(void)
         platform_add_devices(eva_devices,
                              ARRAY_SIZE(eva_devices));
 
-        rmobile_add_device_to_domain("A4LC", &lcdc0_device);
-        rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device);
+        rmobile_add_devices_to_domains(domain_devices,
+                                       ARRAY_SIZE(domain_devices));
         if (usb)
                 rmobile_add_device_to_domain("A3SP", usb);
 
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index ba840cd333b9..79c47847f200 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -80,8 +80,9 @@ static const char *bockw_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(BOCKW_DT, "bockw")
-        .init_early     = r8a7778_init_delay,
+        .init_early     = shmobile_init_delay,
         .init_irq       = r8a7778_init_irq_dt,
         .init_machine   = bockw_init,
+        .init_late      = shmobile_init_late,
         .dt_compat      = bockw_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 8a83eb39d3f1..1cf2c75dacfb 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -733,7 +733,7 @@ static const char *bockw_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(BOCKW_DT, "bockw")
-        .init_early     = r8a7778_init_delay,
+        .init_early     = shmobile_init_delay,
         .init_irq       = r8a7778_init_irq_dt,
         .init_machine   = bockw_init,
         .dt_compat      = bockw_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c
deleted file mode 100644
index e5448f7b868a..000000000000
--- a/arch/arm/mach-shmobile/board-genmai-reference.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Genmai board support
- *
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "clock.h"
-#include "common.h"
-#include "r7s72100.h"
-
-/*
- * This is a really crude hack to provide clkdev support to platform
- * devices until they get moved to DT.
- */
-static const struct clk_name clk_names[] = {
-        { "mtu2", "fck", "sh-mtu2" },
-};
-
-static void __init genmai_add_standard_devices(void)
-{
-        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), true);
-        r7s72100_add_dt_devices();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char * const genmai_boards_compat_dt[] __initconst = {
-        "renesas,genmai",
-        NULL,
-};
-
-DT_MACHINE_START(GENMAI_DT, "genmai")
-        .init_early     = shmobile_init_delay,
-        .init_machine   = genmai_add_standard_devices,
-        .dt_compat      = genmai_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c
deleted file mode 100644
index 7bf2d8057535..000000000000
--- a/arch/arm/mach-shmobile/board-genmai.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Genmai board support
- *
- * Copyright (C) 2013-2014  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- * Copyright (C) 2014  Cogent Embedded, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_eth.h>
-#include <linux/spi/rspi.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "irqs.h"
-#include "r7s72100.h"
-
-/* Ether */
-static const struct sh_eth_plat_data ether_pdata __initconst = {
-        .phy                    = 0x00, /* PD60610 */
-        .edmac_endian           = EDMAC_LITTLE_ENDIAN,
-        .phy_interface          = PHY_INTERFACE_MODE_MII,
-        .no_ether_link          = 1
-};
-
-static const struct resource ether_resources[] __initconst = {
-        DEFINE_RES_MEM(0xe8203000, 0x800),
-        DEFINE_RES_MEM(0xe8204800, 0x200),
-        DEFINE_RES_IRQ(gic_iid(359)),
-};
-
-static const struct platform_device_info ether_info __initconst = {
-        .name           = "r7s72100-ether",
-        .id             = -1,
-        .res            = ether_resources,
-        .num_res        = ARRAY_SIZE(ether_resources),
-        .data           = &ether_pdata,
-        .size_data      = sizeof(ether_pdata),
-        .dma_mask       = DMA_BIT_MASK(32),
-};
-
-/* RSPI */
-#define RSPI_RESOURCE(idx, baseaddr, irq)                               \
-static const struct resource rspi##idx##_resources[] __initconst = {    \
-        DEFINE_RES_MEM(baseaddr, 0x24),                                 \
-        DEFINE_RES_IRQ_NAMED(irq, "error"),                             \
-        DEFINE_RES_IRQ_NAMED(irq + 1, "rx"),                            \
-        DEFINE_RES_IRQ_NAMED(irq + 2, "tx"),                            \
-}
-
-RSPI_RESOURCE(0, 0xe800c800, gic_iid(270));
-RSPI_RESOURCE(1, 0xe800d000, gic_iid(273));
-RSPI_RESOURCE(2, 0xe800d800, gic_iid(276));
-RSPI_RESOURCE(3, 0xe800e000, gic_iid(279));
-RSPI_RESOURCE(4, 0xe800e800, gic_iid(282));
-
-static const struct rspi_plat_data rspi_pdata __initconst = {
-        .num_chipselect = 1,
-};
-
-#define r7s72100_register_rspi(idx)                                        \
-        platform_device_register_resndata(NULL, "rspi-rz", idx,            \
-                                        rspi##idx##_resources,             \
-                                        ARRAY_SIZE(rspi##idx##_resources), \
-                                        &rspi_pdata, sizeof(rspi_pdata))
-
-static const struct spi_board_info spi_info[] __initconst = {
-        {
-                .modalias               = "wm8978",
-                .max_speed_hz           = 5000000,
-                .bus_num                = 4,
-                .chip_select            = 0,
-        },
-};
-
-/* SCIF */
-#define R7S72100_SCIF(index, baseaddr, irq)                             \
-static const struct plat_sci_port scif##index##_platform_data = {       \
-        .type           = PORT_SCIF,                                    \
-        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,               \
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
-        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
-                          SCSCR_REIE,                                   \
-};                                                                      \
-                                                                        \
-static struct resource scif##index##_resources[] = {                    \
-        DEFINE_RES_MEM(baseaddr, 0x100),                                \
-        DEFINE_RES_IRQ(irq + 1),                                        \
-        DEFINE_RES_IRQ(irq + 2),                                        \
-        DEFINE_RES_IRQ(irq + 3),                                        \
-        DEFINE_RES_IRQ(irq),                                            \
-}                                                                       \
-
-R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
-R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
-R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
-R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
-R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
-R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
-R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
-R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
-
-#define r7s72100_register_scif(index)                                          \
-        platform_device_register_resndata(NULL, "sh-sci", index,               \
-                                          scif##index##_resources,             \
-                                          ARRAY_SIZE(scif##index##_resources), \
-                                          &scif##index##_platform_data,        \
-                                          sizeof(scif##index##_platform_data))
-
-static void __init genmai_add_standard_devices(void)
-{
-        r7s72100_clock_init();
-        r7s72100_add_dt_devices();
-
-        platform_device_register_full(&ether_info);
-
-        r7s72100_register_rspi(0);
-        r7s72100_register_rspi(1);
-        r7s72100_register_rspi(2);
-        r7s72100_register_rspi(3);
-        r7s72100_register_rspi(4);
-        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
-
-        r7s72100_register_scif(0);
-        r7s72100_register_scif(1);
-        r7s72100_register_scif(2);
-        r7s72100_register_scif(3);
-        r7s72100_register_scif(4);
-        r7s72100_register_scif(5);
-        r7s72100_register_scif(6);
-        r7s72100_register_scif(7);
-}
-
-static const char * const genmai_boards_compat_dt[] __initconst = {
-        "renesas,genmai",
-        NULL,
-};
-
-DT_MACHINE_START(GENMAI_DT, "genmai")
-        .init_early     = shmobile_init_delay,
-        .init_machine   = genmai_add_standard_devices,
-        .dt_compat      = genmai_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index 3ff88c138896..9db5e6774fb7 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -88,7 +88,6 @@ static void __init koelsch_add_du_device(void)
  * devices until they get moved to DT.
  */
 static const struct clk_name clk_names[] __initconst = {
-        { "cmt0", "fck", "sh-cmt-48-gen2.0" },
         { "du0", "du.0", "rcar-du-r8a7791" },
         { "du1", "du.1", "rcar-du-r8a7791" },
         { "lvds0", "lvds.0", "rcar-du-r8a7791" },
@@ -97,7 +96,6 @@ static const struct clk_name clk_names[] __initconst = {
 static void __init koelsch_add_standard_devices(void)
 {
         shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
-        r8a7791_add_dt_devices();
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         koelsch_add_du_device();
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 5d2621f202d1..d9cdf9a97e23 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -51,8 +51,8 @@ static const char *kzm9g_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
         .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
-        .init_early     = sh73a0_init_delay,
-        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_early     = shmobile_init_delay,
         .init_machine   = kzm_init,
+        .init_late      = shmobile_init_late,
         .dt_compat      = kzm9g_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index f8bc7f8f86ad..77e36fa0b142 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -50,6 +50,7 @@
 #include <video/sh_mobile_lcdc.h>
 
 #include "common.h"
+#include "intc.h"
 #include "irqs.h"
 #include "sh73a0.h"
 
@@ -910,7 +911,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
         .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_add_early_devices,
-        .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = sh73a0_init_irq,
         .init_machine   = kzm_init,
         .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 41c808e56005..2a05c02bec39 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -92,7 +92,6 @@ static void __init lager_add_du_device(void)
  * devices until they get moved to DT.
  */
 static const struct clk_name clk_names[] __initconst = {
-        { "cmt0", "fck", "sh-cmt-48-gen2.0" },
         { "du0", "du.0", "rcar-du-r8a7790" },
         { "du1", "du.1", "rcar-du-r8a7790" },
         { "du2", "du.2", "rcar-du-r8a7790" },
@@ -103,7 +102,6 @@ static const struct clk_name clk_names[] __initconst = {
 static void __init lager_add_standard_devices(void)
 {
         shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
-        r8a7790_add_dt_devices();
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         lager_add_du_device();
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 79f448e93abb..ca5d34b92aa7 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -63,6 +63,7 @@
 #include <asm/mach-types.h>
 
 #include "common.h"
+#include "intc.h"
 #include "irqs.h"
 #include "pm-rmobile.h"
 #include "sh-gpio.h"
@@ -1420,7 +1421,7 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 #define USCCR1          IOMEM(0xE6058144)
 static void __init mackerel_init(void)
 {
-        struct pm_domain_device domain_devices[] = {
+        static struct pm_domain_device domain_devices[] __initdata = {
                 { "A4LC", &lcdc_device, },
                 { "A4LC", &hdmi_lcdc_device, },
                 { "A4LC", &meram_device, },
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 21b3e1ca2261..38d9cdd26587 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -37,18 +37,8 @@ static void __init marzen_init_timer(void)
         clocksource_of_init();
 }
 
-/*
- * This is a really crude hack to provide clkdev support to platform
- * devices until they get moved to DT.
- */
-static const struct clk_name clk_names[] __initconst = {
-        { "tmu0", "fck", "sh-tmu.0" },
-};
-
 static void __init marzen_init(void)
 {
-        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
-        r8a7779_add_standard_devices_dt();
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
 }
@@ -64,8 +54,8 @@ DT_MACHINE_START(MARZEN, "marzen")
         .map_io         = r8a7779_map_io,
         .init_early     = shmobile_init_delay,
         .init_time      = marzen_init_timer,
-        .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq_dt,
         .init_machine   = marzen_init,
+        .init_late      = shmobile_init_late,
         .dt_compat      = marzen_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
deleted file mode 100644
index 3eb2ec401e0c..000000000000
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * r7a72100 clock framework support
- *
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2012  Phil Edworthy
- * Copyright (C) 2011  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-
-#include "common.h"
-#include "r7s72100.h"
-
-/* Frequency Control Registers */
-#define FRQCR           0xfcfe0010
-#define FRQCR2          0xfcfe0014
-/* Standby Control Registers */
-#define STBCR3          0xfcfe0420
-#define STBCR4          0xfcfe0424
-#define STBCR7          0xfcfe0430
-#define STBCR9          0xfcfe0438
-#define STBCR10         0xfcfe043c
-
-#define PLL_RATE 30
-
-static struct clk_mapping cpg_mapping = {
-        .phys   = 0xfcfe0000,
-        .len    = 0x1000,
-};
-
-/* Fixed 32 KHz root clock for RTC */
-static struct clk r_clk = {
-        .rate           = 32768,
-};
-
-/*
- * Default rate for the root input clock, reset this with clk_set_rate()
- * from the platform code.
- */
-static struct clk extal_clk = {
-        .rate           = 13330000,
-        .mapping        = &cpg_mapping,
-};
-
-static unsigned long pll_recalc(struct clk *clk)
-{
-        return clk->parent->rate * PLL_RATE;
-}
-
-static struct sh_clk_ops pll_clk_ops = {
-        .recalc         = pll_recalc,
-};
-
-static struct clk pll_clk = {
-        .ops            = &pll_clk_ops,
-        .parent         = &extal_clk,
-        .flags          = CLK_ENABLE_ON_INIT,
-};
-
-static unsigned long bus_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 3;
-}
-
-static struct sh_clk_ops bus_clk_ops = {
-        .recalc         = bus_recalc,
-};
-
-static struct clk bus_clk = {
-        .ops            = &bus_clk_ops,
-        .parent         = &pll_clk,
-        .flags          = CLK_ENABLE_ON_INIT,
-};
-
-static unsigned long peripheral0_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 12;
-}
-
-static struct sh_clk_ops peripheral0_clk_ops = {
-        .recalc         = peripheral0_recalc,
-};
-
-static struct clk peripheral0_clk = {
-        .ops            = &peripheral0_clk_ops,
-        .parent         = &pll_clk,
-        .flags          = CLK_ENABLE_ON_INIT,
-};
-
-static unsigned long peripheral1_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 6;
-}
-
-static struct sh_clk_ops peripheral1_clk_ops = {
-        .recalc         = peripheral1_recalc,
-};
-
-static struct clk peripheral1_clk = {
-        .ops            = &peripheral1_clk_ops,
-        .parent         = &pll_clk,
-        .flags          = CLK_ENABLE_ON_INIT,
-};
-
-struct clk *main_clks[] = {
-        &r_clk,
-        &extal_clk,
-        &pll_clk,
-        &bus_clk,
-        &peripheral0_clk,
-        &peripheral1_clk,
-};
-
-static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
-static int multipliers[] = { 1, 2, 1, 1 };
-
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors = div2,
-        .nr_divisors = ARRAY_SIZE(div2),
-        .multipliers = multipliers,
-        .nr_multipliers = ARRAY_SIZE(multipliers),
-};
-
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-};
-
-enum { DIV4_I,
-        DIV4_NR };
-
-#define DIV4(_reg, _bit, _mask, _flags) \
-        SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
-
-/* The mask field specifies the div2 entries that are valid */
-struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I]  = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
-                                        | CLK_ENABLE_ON_INIT),
-};
-
-enum {
-        MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
-        MSTP97, MSTP96, MSTP95, MSTP94,
-        MSTP74,
-        MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
-        MSTP33, MSTP_NR
-};
-
-static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
-        [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
-        [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
-        [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
-        [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
-        [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
-        [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
-        [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
-        [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
-        [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
-        [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
-        [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
-        [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
-        [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
-        [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
-        [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
-        [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
-        [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
-        [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
-};
-
-static struct clk_lookup lookups[] = {
-        /* main clocks */
-        CLKDEV_CON_ID("rclk", &r_clk),
-        CLKDEV_CON_ID("extal", &extal_clk),
-        CLKDEV_CON_ID("pll_clk", &pll_clk),
-        CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
-
-        /* DIV4 clocks */
-        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
-
-        /* MSTP clocks */
-        CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
-        CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
-        CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
-        CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
-        CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
-        CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
-
-        /* ICK */
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
-        CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
-        CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
-};
-
-void __init r7s72100_clock_init(void)
-{
-        int k, ret = 0;
-
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup rza1 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 17435c1aa2fe..126ddafad526 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -183,8 +183,8 @@ enum {
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
-        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
-        [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
 };
 
 /* DIV6 clocks */
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 10e193d707f5..453b23129cfa 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -152,7 +152,7 @@ enum {
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
-        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
 };
 
 /* DIV6 clocks */
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index d8c4048b9e33..02a6f45a0b9e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
-        CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
         CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 98056081f0da..72087c79ad7b 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,8 +2,6 @@
 #define __ARCH_MACH_COMMON_H
 
 extern void shmobile_earlytimer_init(void);
-extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
-                         unsigned int mult, unsigned int div);
 extern void shmobile_init_delay(void);
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
diff --git a/arch/arm/mach-shmobile/cpufreq.c b/arch/arm/mach-shmobile/cpufreq.c
index 8a24b2be46ae..57fbff024dcd 100644
--- a/arch/arm/mach-shmobile/cpufreq.c
+++ b/arch/arm/mach-shmobile/cpufreq.c
@@ -12,6 +12,6 @@
 
 int __init shmobile_cpufreq_init(void)
 {
-        platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
+        platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
         return 0;
 }
diff --git a/arch/arm/mach-shmobile/dma-register.h b/arch/arm/mach-shmobile/dma-register.h
index 97c40bd9b94f..52a2f66e600f 100644
--- a/arch/arm/mach-shmobile/dma-register.h
+++ b/arch/arm/mach-shmobile/dma-register.h
@@ -52,8 +52,8 @@ static const unsigned int dma_ts_shift[] = {
         ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
          (((i) & TS_HI_BIT)  << TS_HI_SHIFT))
 
-#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
-#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
 
 
 /*
diff --git a/arch/arm/mach-shmobile/intc.h b/arch/arm/mach-shmobile/intc.h
index a5603c76cfe0..40b2ad4ca5b4 100644
--- a/arch/arm/mach-shmobile/intc.h
+++ b/arch/arm/mach-shmobile/intc.h
@@ -287,4 +287,9 @@ static struct intc_desc p ## _desc __initdata = {			\
                              p ## _sense_registers, NULL),              \
 }
 
+/* INTCS */
+#define INTCS_VECT_BASE         0x3400
+#define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
+
 #endif  /* __ASM_MACH_INTC_H */
diff --git a/arch/arm/mach-shmobile/irqs.h b/arch/arm/mach-shmobile/irqs.h
index 4ff2d2aa94f0..3070f6d887eb 100644
--- a/arch/arm/mach-shmobile/irqs.h
+++ b/arch/arm/mach-shmobile/irqs.h
@@ -1,18 +1,12 @@
 #ifndef __SHMOBILE_IRQS_H
 #define __SHMOBILE_IRQS_H
 
-#include <linux/sh_intc.h>
-#include <mach/irqs.h>
+#include "include/mach/irqs.h"
 
 /* GIC */
 #define gic_spi(nr)             ((nr) + 32)
 #define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
 
-/* INTCS */
-#define INTCS_VECT_BASE         0x3400
-#define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
-#define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
-
 /* GPIO IRQ */
 #define _GPIO_IRQ_BASE          2500
 #define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index a0d44d537fa0..e3f146448237 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -13,12 +13,12 @@
 #include "common.h"
 #include "pm-rmobile.h"
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 static int r8a7740_pd_a4s_suspend(void)
 {
         /*
          * The A4S domain contains the CPU core and therefore it should
-         * only be turned off if the CPU is in use.
+         * only be turned off if the CPU is not in use.
          */
         return -EBUSY;
 }
@@ -34,23 +34,21 @@ static int r8a7740_pd_a3sp_suspend(void)
 
 static struct rmobile_pm_domain r8a7740_pm_domains[] = {
         {
+                .genpd.name     = "A4LC",
+                .bit_shift      = 1,
+        }, {
                 .genpd.name     = "A4S",
                 .bit_shift      = 10,
                 .gov            = &pm_domain_always_on_gov,
                 .no_debug       = true,
                 .suspend        = r8a7740_pd_a4s_suspend,
-        },
-        {
+        }, {
                 .genpd.name     = "A3SP",
                 .bit_shift      = 11,
                 .gov            = &pm_domain_always_on_gov,
                 .no_debug       = true,
                 .suspend        = r8a7740_pd_a3sp_suspend,
         },
-        {
-                .genpd.name     = "A4LC",
-                .bit_shift      = 1,
-        },
 };
 
 void __init r8a7740_init_pm_domains(void)
@@ -58,8 +56,7 @@ void __init r8a7740_init_pm_domains(void)
         rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
         pm_genpd_add_subdomain_names("A4S", "A3SP");
 }
-
-#endif /* CONFIG_PM */
+#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
 
 #ifdef CONFIG_SUSPEND
 static int r8a7740_enter_suspend(suspend_state_t suspend_state)
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index 69f70b7f7fb2..82fe3d7f9662 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -87,7 +87,6 @@ static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
         genpd->dev_ops.stop = pm_clk_suspend;
         genpd->dev_ops.start = pm_clk_resume;
         genpd->dev_ops.active_wakeup = pd_active_wakeup;
-        genpd->dev_irq_safe = true;
         genpd->power_off = pd_power_down;
         genpd->power_on = pd_power_up;
 
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c
index 34b8a5674f85..00022ee56f80 100644
--- a/arch/arm/mach-shmobile/pm-rcar.c
+++ b/arch/arm/mach-shmobile/pm-rcar.c
@@ -31,8 +31,6 @@
 #define SYSCISR_RETRIES 1000
 #define SYSCISR_DELAY_US 1
 
-#if defined(CONFIG_PM) || defined(CONFIG_SMP)
-
 static void __iomem *rcar_sysc_base;
 static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
 
@@ -137,5 +135,3 @@ void __iomem *rcar_sysc_init(phys_addr_t base)
 
         return rcar_sysc_base;
 }
-
-#endif /* CONFIG_PM || CONFIG_SMP */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index ebdd16e94a84..717e6413d29c 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -27,7 +27,6 @@
 #define PSTR_RETRIES    100
 #define PSTR_DELAY_US   10
 
-#ifdef CONFIG_PM
 static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
 {
         struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);
@@ -111,7 +110,6 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
         genpd->dev_ops.stop             = pm_clk_suspend;
         genpd->dev_ops.start            = pm_clk_resume;
         genpd->dev_ops.active_wakeup    = rmobile_pd_active_wakeup;
-        genpd->dev_irq_safe             = true;
         genpd->power_off                = rmobile_pd_power_down;
         genpd->power_on                 = rmobile_pd_power_up;
         __rmobile_pd_power_up(rmobile_pd, false);
@@ -151,4 +149,3 @@ void rmobile_add_devices_to_domains(struct pm_domain_device data[],
                 rmobile_add_device_to_domain_td(data[j].domain_name,
                                                 data[j].pdev, &latencies);
 }
-#endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h
index 690553a06887..8f66b343162b 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.h
+++ b/arch/arm/mach-shmobile/pm-rmobile.h
@@ -36,7 +36,7 @@ struct pm_domain_device {
         struct platform_device *pdev;
 };
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_RMOBILE
 extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num);
 extern void rmobile_add_device_to_domain_td(const char *domain_name,
                                             struct platform_device *pdev,
@@ -58,6 +58,6 @@ extern void rmobile_add_devices_to_domains(struct pm_domain_device data[],
 
 static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[],
                                                   int size) {}
-#endif /* CONFIG_PM */
+#endif /* CONFIG_PM_RMOBILE */
 
 #endif /* PM_RMOBILE_H */
diff --git a/arch/arm/mach-shmobile/r7s72100.h b/arch/arm/mach-shmobile/r7s72100.h
deleted file mode 100644
index efb723c88dd0..000000000000
--- a/arch/arm/mach-shmobile/r7s72100.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_R7S72100_H__
-#define __ASM_R7S72100_H__
-
-void r7s72100_add_dt_devices(void);
-void r7s72100_clock_init(void);
-
-#endif /* __ASM_R7S72100_H__ */
diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
index ce8bdd1d8a8a..5fafd6fcedf7 100644
--- a/arch/arm/mach-shmobile/r8a73a4.h
+++ b/arch/arm/mach-shmobile/r8a73a4.h
@@ -14,6 +14,5 @@ void r8a73a4_add_standard_devices(void);
 void r8a73a4_add_dt_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
-void r8a73a4_init_early(void);
 
 #endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h
index 1d1a5fd78b6b..f369b4b0863d 100644
--- a/arch/arm/mach-shmobile/r8a7740.h
+++ b/arch/arm/mach-shmobile/r8a7740.h
@@ -49,15 +49,14 @@ extern void r8a7740_init_irq_of(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
-extern void r8a7740_add_standard_devices_dt(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 extern void __init r8a7740_init_pm_domains(void);
 #else
 static inline void r8a7740_init_pm_domains(void) {}
-#endif /* CONFIG_PM */
+#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
 
 #endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h
index 5415c719dc19..19f97046dd70 100644
--- a/arch/arm/mach-shmobile/r8a7779.h
+++ b/arch/arm/mach-shmobile/r8a7779.h
@@ -17,7 +17,6 @@ extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
-extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_init_late(void);
 extern u32 r8a7779_read_mode_pins(void);
 extern void r8a7779_clock_init(void);
diff --git a/arch/arm/mach-shmobile/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index 459827f1369b..388f0514d931 100644
--- a/arch/arm/mach-shmobile/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -27,7 +27,6 @@ enum {
 };
 
 void r8a7790_add_standard_devices(void);
-void r8a7790_add_dt_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_pm_init(void);
diff --git a/arch/arm/mach-shmobile/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h
index 86eae7bceb6f..c1bf7abefa5a 100644
--- a/arch/arm/mach-shmobile/r8a7791.h
+++ b/arch/arm/mach-shmobile/r8a7791.h
@@ -2,7 +2,6 @@
 #define __ASM_R8A7791_H__
 
 void r8a7791_add_standard_devices(void);
-void r8a7791_add_dt_devices(void);
 void r8a7791_clock_init(void);
 void r8a7791_pinmux_init(void);
 void r8a7791_pm_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index f3b3b14ba972..4122104359f9 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -18,34 +18,12 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/irq.h>
 #include <linux/kernel.h>
-#include <linux/of_platform.h>
-#include <linux/sh_timer.h>
 
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include "irqs.h"
-#include "r7s72100.h"
 
-static struct resource mtu2_resources[] __initdata = {
-        DEFINE_RES_MEM(0xfcff0000, 0x400),
-        DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"),
-};
-
-#define r7s72100_register_mtu2()                                        \
-        platform_device_register_resndata(NULL, "sh-mtu2",              \
-                                          -1, mtu2_resources,           \
-                                          ARRAY_SIZE(mtu2_resources),   \
-                                          NULL, 0)
-
-void __init r7s72100_add_dt_devices(void)
-{
-        r7s72100_register_mtu2();
-}
-
-#ifdef CONFIG_USE_OF
 static const char *r7s72100_boards_compat_dt[] __initdata = {
         "renesas,r7s72100",
         NULL,
@@ -53,6 +31,6 @@ static const char *r7s72100_boards_compat_dt[] __initdata = {
 
 DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
         .init_early     = shmobile_init_delay,
+        .init_late      = shmobile_init_late,
         .dt_compat      = r7s72100_boards_compat_dt,
 MACHINE_END
-#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 6683072a9d98..53f40b70680d 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -295,13 +295,6 @@ void __init r8a73a4_add_standard_devices(void)
         r8a73a4_register_dmac();
 }
 
-void __init r8a73a4_init_early(void)
-{
-#ifndef CONFIG_ARM_ARCH_TIMER
-        shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
-#endif
-}
-
 #ifdef CONFIG_USE_OF
 
 static const char *r8a73a4_boards_compat_dt[] __initdata = {
@@ -310,7 +303,8 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
-        .init_early     = r8a73a4_init_early,
+        .init_early     = shmobile_init_delay,
+        .init_late      = shmobile_init_late,
         .dt_compat      = r8a73a4_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 3d5eacaba3e6..8894e1b7ab0e 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -36,6 +36,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include "common.h"
 #include "dma-register.h"
@@ -311,10 +312,6 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *r8a7740_devices_dt[] __initdata = {
-        &cmt1_device,
-};
-
 static struct platform_device *r8a7740_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -331,6 +328,7 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
         &irqpin3_device,
         &tmu0_device,
         &ipmmu_device,
+        &cmt1_device,
 };
 
 /* DMA */
@@ -747,6 +745,19 @@ static void r8a7740_i2c_workaround(struct platform_device *pdev)
 
 void __init r8a7740_add_standard_devices(void)
 {
+        static struct pm_domain_device domain_devices[] __initdata = {
+                { "A3SP", &scif0_device },
+                { "A3SP", &scif1_device },
+                { "A3SP", &scif2_device },
+                { "A3SP", &scif3_device },
+                { "A3SP", &scif4_device },
+                { "A3SP", &scif5_device },
+                { "A3SP", &scif6_device },
+                { "A3SP", &scif7_device },
+                { "A3SP", &scif8_device },
+                { "A3SP", &i2c1_device },
+        };
+
         /* I2C work-around */
         r8a7740_i2c_workaround(&i2c0_device);
         r8a7740_i2c_workaround(&i2c1_device);
@@ -756,31 +767,18 @@ void __init r8a7740_add_standard_devices(void)
         /* add devices */
         platform_add_devices(r8a7740_early_devices,
                             ARRAY_SIZE(r8a7740_early_devices));
-        platform_add_devices(r8a7740_devices_dt,
-                            ARRAY_SIZE(r8a7740_devices_dt));
         platform_add_devices(r8a7740_late_devices,
                              ARRAY_SIZE(r8a7740_late_devices));
 
         /* add devices to PM domain  */
-
-        rmobile_add_device_to_domain("A3SP",    &scif0_device);
-        rmobile_add_device_to_domain("A3SP",    &scif1_device);
-        rmobile_add_device_to_domain("A3SP",    &scif2_device);
-        rmobile_add_device_to_domain("A3SP",    &scif3_device);
-        rmobile_add_device_to_domain("A3SP",    &scif4_device);
-        rmobile_add_device_to_domain("A3SP",    &scif5_device);
-        rmobile_add_device_to_domain("A3SP",    &scif6_device);
-        rmobile_add_device_to_domain("A3SP",    &scif7_device);
-        rmobile_add_device_to_domain("A3SP",    &scif8_device);
-        rmobile_add_device_to_domain("A3SP",    &i2c1_device);
+        rmobile_add_devices_to_domains(domain_devices,
+                                       ARRAY_SIZE(domain_devices));
 }
 
 void __init r8a7740_add_early_devices(void)
 {
         early_platform_add_devices(r8a7740_early_devices,
                                    ARRAY_SIZE(r8a7740_early_devices));
-        early_platform_add_devices(r8a7740_devices_dt,
-                                   ARRAY_SIZE(r8a7740_devices_dt));
 
         /* setup early console here as well */
         shmobile_setup_console();
@@ -788,13 +786,6 @@ void __init r8a7740_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init r8a7740_add_standard_devices_dt(void)
-{
-        platform_add_devices(r8a7740_devices_dt,
-                            ARRAY_SIZE(r8a7740_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 void __init r8a7740_init_irq_of(void)
 {
         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
@@ -827,8 +818,20 @@ void __init r8a7740_init_irq_of(void)
 
 static void __init r8a7740_generic_init(void)
 {
-        r8a7740_clock_init(0);
-        r8a7740_add_standard_devices_dt();
+        r8a7740_meram_workaround();
+
+#ifdef CONFIG_CACHE_L2X0
+        /* Shared attribute override enable, 32K*8way */
+        l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
+#endif
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+#define RESCNT2 IOMEM(0xe6188020)
+static void r8a7740_restart(enum reboot_mode mode, const char *cmd)
+{
+        /* Do soft power on reset */
+        writel(1 << 31, RESCNT2);
 }
 
 static const char *r8a7740_boards_compat_dt[] __initdata = {
@@ -843,6 +846,7 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
         .init_machine   = r8a7740_generic_init,
         .init_late      = shmobile_init_late,
         .dt_compat      = r8a7740_boards_compat_dt,
+        .restart        = r8a7740_restart,
 MACHINE_END
 
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index f00a488dcf43..85fe016d6a87 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -520,6 +520,7 @@ void __init r8a7778_add_standard_devices(void)
 
 void __init r8a7778_init_late(void)
 {
+        shmobile_init_late();
         platform_device_register_full(&ehci_info);
         platform_device_register_full(&ohci_info);
 }
@@ -573,7 +574,7 @@ void __init r8a7778_init_irq_extpin(int irlm)
 
 void __init r8a7778_init_delay(void)
 {
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+        shmobile_init_delay();
 }
 
 #ifdef CONFIG_USE_OF
@@ -609,8 +610,8 @@ static const char *r8a7778_compat_dt[] __initdata = {
 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
         .init_early     = r8a7778_init_delay,
         .init_irq       = r8a7778_init_irq_dt,
+        .init_late      = shmobile_init_late,
         .dt_compat      = r8a7778_compat_dt,
-        .init_late      = r8a7778_init_late,
 MACHINE_END
 
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 236c1befb9e3..136078ab9407 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -641,7 +641,7 @@ static void __init r8a7779_register_hpb_dmae(void)
                                           sizeof(dma_platform_data));
 }
 
-static struct platform_device *r8a7779_devices_dt[] __initdata = {
+static struct platform_device *r8a7779_early_devices[] __initdata = {
         &tmu0_device,
 };
 
@@ -669,8 +669,8 @@ void __init r8a7779_add_standard_devices(void)
 
         r8a7779_init_pm_domains();
 
-        platform_add_devices(r8a7779_devices_dt,
-                            ARRAY_SIZE(r8a7779_devices_dt));
+        platform_add_devices(r8a7779_early_devices,
+                            ARRAY_SIZE(r8a7779_early_devices));
         platform_add_devices(r8a7779_standard_devices,
                             ARRAY_SIZE(r8a7779_standard_devices));
         r8a7779_register_hpb_dmae();
@@ -678,8 +678,8 @@ void __init r8a7779_add_standard_devices(void)
 
 void __init r8a7779_add_early_devices(void)
 {
-        early_platform_add_devices(r8a7779_devices_dt,
-                                   ARRAY_SIZE(r8a7779_devices_dt));
+        early_platform_add_devices(r8a7779_early_devices,
+                                   ARRAY_SIZE(r8a7779_early_devices));
 
         /* Early serial console setup is not included here due to
          * memory map collisions. The SCIF serial ports in r8a7779
@@ -739,12 +739,6 @@ void __init r8a7779_init_irq_dt(void)
         __raw_writel(0x003fee3f, INT2SMSKCR4);
 }
 
-void __init r8a7779_add_standard_devices_dt(void)
-{
-        platform_add_devices(r8a7779_devices_dt,
-                             ARRAY_SIZE(r8a7779_devices_dt));
-}
-
 #define MODEMR          0xffcc0020
 
 u32 __init r8a7779_read_mode_pins(void)
@@ -771,10 +765,8 @@ static const char *r8a7779_compat_dt[] __initdata = {
 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
         .map_io         = r8a7779_map_io,
         .init_early     = shmobile_init_delay,
-        .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq_dt,
-        .init_machine   = r8a7779_add_standard_devices_dt,
-        .init_late      = r8a7779_init_late,
+        .init_late      = shmobile_init_late,
         .dt_compat      = r8a7779_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 0c12b01bb9e3..877fdeb985d0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -282,11 +282,6 @@ static struct resource cmt0_resources[] = {
                                           &cmt##idx##_platform_data,    \
                                           sizeof(struct sh_timer_config))
 
-void __init r8a7790_add_dt_devices(void)
-{
-        r8a7790_register_cmt(0);
-}
-
 void __init r8a7790_add_standard_devices(void)
 {
         r8a7790_register_scif(0);
@@ -299,7 +294,7 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_scif(7);
         r8a7790_register_scif(8);
         r8a7790_register_scif(9);
-        r8a7790_add_dt_devices();
+        r8a7790_register_cmt(0);
         r8a7790_register_irqc(0);
         r8a7790_register_thermal();
         r8a7790_register_i2c(0);
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index d47d8b16a43f..35d78639244f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -182,11 +182,6 @@ static const struct resource thermal_resources[] __initconst = {
                                         thermal_resources,              \
                                         ARRAY_SIZE(thermal_resources))
 
-void __init r8a7791_add_dt_devices(void)
-{
-        r8a7791_register_cmt(0);
-}
-
 void __init r8a7791_add_standard_devices(void)
 {
         r8a7791_register_scif(0);
@@ -204,7 +199,7 @@ void __init r8a7791_add_standard_devices(void)
         r8a7791_register_scif(12);
         r8a7791_register_scif(13);
         r8a7791_register_scif(14);
-        r8a7791_add_dt_devices();
+        r8a7791_register_cmt(0);
         r8a7791_register_irqc(0);
         r8a7791_register_thermal();
 }
diff --git a/arch/arm/mach-shmobile/setup-r8a7794.c b/arch/arm/mach-shmobile/setup-r8a7794.c
new file mode 100644
index 000000000000..d2b093033132
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7794.c
@@ -0,0 +1,33 @@
+/*
+ * r8a7794 processor support
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ * Copyright (C) 2014  Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of_platform.h>
+#include "common.h"
+#include "rcar-gen2.h"
+#include <asm/mach/arch.h>
+
+static const char * const r8a7794_boards_compat_dt[] __initconst = {
+        "renesas,r8a7794",
+        NULL,
+};
+
+DT_MACHINE_START(R8A7794_DT, "Generic R8A7794 (Flattened Device Tree)")
+        .init_early     = shmobile_init_delay,
+        .init_late      = shmobile_init_late,
+        .init_time      = rcar_gen2_timer_init,
+        .reserve        = rcar_gen2_reserve,
+        .dt_compat      = r8a7794_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 9cdfcdfd38fc..d646c8d12423 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -41,6 +41,7 @@
 
 #include "common.h"
 #include "dma-register.h"
+#include "intc.h"
 #include "irqs.h"
 #include "pm-rmobile.h"
 #include "sh7372.h"
@@ -927,7 +928,7 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
 
 void __init sh7372_add_standard_devices(void)
 {
-        struct pm_domain_device domain_devices[] = {
+        static struct pm_domain_device domain_devices[] __initdata = {
                 { "A3RV", &vpu_device, },
                 { "A4MP", &spu0_device, },
                 { "A4MP", &spu1_device, },
@@ -984,7 +985,7 @@ void __init sh7372_add_early_devices(void)
 
 void __init sh7372_add_early_devices_dt(void)
 {
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
+        shmobile_init_delay();
 
         sh7372_add_early_devices();
 }
@@ -1008,7 +1009,6 @@ static const char *sh7372_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
         .map_io         = sh7372_map_io,
         .init_early     = sh7372_add_early_devices_dt,
-        .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = sh7372_add_standard_devices_dt,
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 2c802ae9b241..b7bd8e509668 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -40,6 +40,7 @@
 
 #include "common.h"
 #include "dma-register.h"
+#include "intc.h"
 #include "irqs.h"
 #include "sh73a0.h"
 
@@ -696,10 +697,6 @@ static struct platform_device irqpin3_device = {
         },
 };
 
-static struct platform_device *sh73a0_devices_dt[] __initdata = {
-        &cmt1_device,
-};
-
 static struct platform_device *sh73a0_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -712,6 +709,7 @@ static struct platform_device *sh73a0_early_devices[] __initdata = {
         &scif8_device,
         &tmu0_device,
         &ipmmu_device,
+        &cmt1_device,
 };
 
 static struct platform_device *sh73a0_late_devices[] __initdata = {
@@ -736,8 +734,6 @@ void __init sh73a0_add_standard_devices(void)
         /* Clear software reset bit on SY-DMAC module */
         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 
-        platform_add_devices(sh73a0_devices_dt,
-                            ARRAY_SIZE(sh73a0_devices_dt));
         platform_add_devices(sh73a0_early_devices,
                             ARRAY_SIZE(sh73a0_early_devices));
         platform_add_devices(sh73a0_late_devices,
@@ -746,7 +742,7 @@ void __init sh73a0_add_standard_devices(void)
 
 void __init sh73a0_init_delay(void)
 {
-        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+        shmobile_init_delay();
 }
 
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
@@ -762,8 +758,6 @@ void __init sh73a0_earlytimer_init(void)
 
 void __init sh73a0_add_early_devices(void)
 {
-        early_platform_add_devices(sh73a0_devices_dt,
-                                   ARRAY_SIZE(sh73a0_devices_dt));
         early_platform_add_devices(sh73a0_early_devices,
                                    ARRAY_SIZE(sh73a0_early_devices));
 
@@ -775,17 +769,10 @@ void __init sh73a0_add_early_devices(void)
 
 void __init sh73a0_add_standard_devices_dt(void)
 {
-        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
-
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
-        platform_add_devices(sh73a0_devices_dt,
-                             ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-
-        /* Instantiate cpufreq-cpu0 */
-        platform_device_register_full(&devinfo);
 }
 
 static const char *sh73a0_boards_compat_dt[] __initdata = {
@@ -797,8 +784,8 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
         .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_init_delay,
-        .nr_irqs        = NR_IRQS_LEGACY,
         .init_machine   = sh73a0_add_standard_devices_dt,
+        .init_late      = shmobile_init_late,
         .dt_compat      = sh73a0_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 942efdc82a62..87c6be1e79bd 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -23,8 +23,8 @@
 #include <linux/delay.h>
 #include <linux/of_address.h>
 
-void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
-                                    unsigned int mult, unsigned int div)
+static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
+                                           unsigned int mult, unsigned int div)
 {
         /* calculate a worst-case loops-per-jiffy value
          * based on maximum cpu core hz setting and the
@@ -40,27 +40,10 @@ void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
                 preset_lpj = max_cpu_core_hz / value;
 }
 
-void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
-                                 unsigned int mult, unsigned int div)
-{
-        /* calculate a worst-case loops-per-jiffy value
-         * based on maximum cpu core mhz setting and the
-         * __delay() implementation in arch/arm/lib/delay.S
-         *
-         * this will result in a longer delay than expected
-         * when the cpu core runs on lower frequencies.
-         */
-
-        unsigned int value = (1000000 * mult) / (HZ * div);
-
-        if (!preset_lpj)
-                preset_lpj = max_cpu_core_mhz * value;
-}
-
 void __init shmobile_init_delay(void)
 {
         struct device_node *np, *cpus;
-        bool is_a8_a9 = false;
+        bool is_a7_a8_a9 = false;
         bool is_a15 = false;
         u32 max_freq = 0;
 
@@ -74,9 +57,10 @@ void __init shmobile_init_delay(void)
                 if (!of_property_read_u32(np, "clock-frequency", &freq))
                         max_freq = max(max_freq, freq);
 
-                if (of_device_is_compatible(np, "arm,cortex-a8") ||
+                if (of_device_is_compatible(np, "arm,cortex-a7") ||
+                    of_device_is_compatible(np, "arm,cortex-a8") ||
                     of_device_is_compatible(np, "arm,cortex-a9"))
-                        is_a8_a9 = true;
+                        is_a7_a8_a9 = true;
                 else if (of_device_is_compatible(np, "arm,cortex-a15"))
                         is_a15 = true;
         }
@@ -86,7 +70,7 @@ void __init shmobile_init_delay(void)
         if (!max_freq)
                 return;
 
-        if (is_a8_a9)
+        if (is_a7_a8_a9)
                 shmobile_setup_delay_hz(max_freq, 1, 3);
         else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
                 shmobile_setup_delay_hz(max_freq, 2, 4);
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 6fd4dc88160b..b6f4bda273b3 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -4,7 +4,6 @@
 
 menuconfig PLAT_SPEAR
         bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
-        default PLAT_SPEAR_SINGLE
         select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
         select CLKSRC_MMIO
@@ -13,7 +12,7 @@ if PLAT_SPEAR
 
 config ARCH_SPEAR13XX
         bool "ST SPEAr13xx"
-        depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
+        depends on ARCH_MULTI_V7
         select ARM_GIC
         select GPIO_SPEAR_SPICS
         select HAVE_ARM_SCU if SMP
@@ -44,7 +43,7 @@ endif #ARCH_SPEAR13XX
 
 config ARCH_SPEAR3XX
         bool "ST SPEAr3xx"
-        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on ARCH_MULTI_V5
         depends on !ARCH_SPEAR13XX
         select ARM_VIC
         select PINCTRL
@@ -75,7 +74,7 @@ endif
 
 config ARCH_SPEAR6XX
         bool "ST SPEAr6XX"
-        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on ARCH_MULTI_V5
         depends on !ARCH_SPEAR13XX
         select ARM_VIC
         help
@@ -88,7 +87,7 @@ config MACH_SPEAR600
           Supports ST SPEAr600 boards configured via the device-tree
 
 config ARCH_SPEAR_AUTO
-        def_bool PLAT_SPEAR_SINGLE
+        bool
         depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
         select ARCH_SPEAR3XX
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 42d4753683ce..d7598aeed803 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -12,81 +12,9 @@
 
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/io.h>
-#include <linux/reboot.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/system_misc.h>
-
-#define SUN4I_WATCHDOG_CTRL_REG         0x00
-#define SUN4I_WATCHDOG_CTRL_RESTART             BIT(0)
-#define SUN4I_WATCHDOG_MODE_REG         0x04
-#define SUN4I_WATCHDOG_MODE_ENABLE              BIT(0)
-#define SUN4I_WATCHDOG_MODE_RESET_ENABLE        BIT(1)
-
-#define SUN6I_WATCHDOG1_IRQ_REG         0x00
-#define SUN6I_WATCHDOG1_CTRL_REG        0x10
-#define SUN6I_WATCHDOG1_CTRL_RESTART            BIT(0)
-#define SUN6I_WATCHDOG1_CONFIG_REG      0x14
-#define SUN6I_WATCHDOG1_CONFIG_RESTART          BIT(0)
-#define SUN6I_WATCHDOG1_CONFIG_IRQ              BIT(1)
-#define SUN6I_WATCHDOG1_MODE_REG        0x18
-#define SUN6I_WATCHDOG1_MODE_ENABLE             BIT(0)
-
-static void __iomem *wdt_base;
-
-static void sun4i_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (!wdt_base)
-                return;
-
-        /* Enable timer and set reset bit in the watchdog */
-        writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
-               wdt_base + SUN4I_WATCHDOG_MODE_REG);
-
-        /*
-         * Restart the watchdog. The default (and lowest) interval
-         * value for the watchdog is 0.5s.
-         */
-        writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
-
-        while (1) {
-                mdelay(5);
-                writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
-                       wdt_base + SUN4I_WATCHDOG_MODE_REG);
-        }
-}
-
-static struct of_device_id sunxi_restart_ids[] = {
-        { .compatible = "allwinner,sun4i-a10-wdt" },
-        { /*sentinel*/ }
-};
-
-static void sunxi_setup_restart(void)
-{
-        struct device_node *np;
-
-        np = of_find_matching_node(NULL, sunxi_restart_ids);
-        if (WARN(!np, "unable to setup watchdog restart"))
-                return;
-
-        wdt_base = of_iomap(np, 0);
-        WARN(!wdt_base, "failed to map watchdog base address");
-}
-
-static void __init sunxi_dt_init(void)
-{
-        sunxi_setup_restart();
-
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 
 static const char * const sunxi_board_dt_compat[] = {
         "allwinner,sun4i-a10",
@@ -96,9 +24,7 @@ static const char * const sunxi_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
-        .init_machine   = sunxi_dt_init,
         .dt_compat      = sunxi_board_dt_compat,
-        .restart        = sun4i_restart,
 MACHINE_END
 
 static const char * const sun6i_board_dt_compat[] = {
@@ -126,9 +52,7 @@ static const char * const sun7i_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
-        .init_machine   = sunxi_dt_init,
         .dt_compat      = sun7i_board_dt_compat,
-        .restart        = sun4i_restart,
 MACHINE_END
 
 static const char * const sun8i_board_dt_compat[] = {
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index ec55d1de1b55..475e783992fd 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -22,11 +22,12 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <soc/tegra/fuse.h>
 
 #include "flowctrl.h"
-#include "iomap.h"
 
 static u8 flowctrl_offset_halt_cpu[] = {
         FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -42,23 +43,22 @@ static u8 flowctrl_offset_cpu_csr[] = {
         FLOW_CTRL_CPU1_CSR + 16,
 };
 
+static void __iomem *tegra_flowctrl_base;
+
 static void flowctrl_update(u8 offset, u32 value)
 {
-        void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
-
-        writel(value, addr);
+        writel(value, tegra_flowctrl_base + offset);
 
         /* ensure the update has reached the flow controller */
         wmb();
-        readl_relaxed(addr);
+        readl_relaxed(tegra_flowctrl_base + offset);
 }
 
 u32 flowctrl_read_cpu_csr(unsigned int cpuid)
 {
         u8 offset = flowctrl_offset_cpu_csr[cpuid];
-        void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
 
-        return readl(addr);
+        return readl(tegra_flowctrl_base + offset);
 }
 
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
@@ -139,3 +139,33 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
         reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event */
         flowctrl_write_cpu_csr(cpuid, reg);
 }
+
+static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra124-flowctrl" },
+        { .compatible = "nvidia,tegra114-flowctrl" },
+        { .compatible = "nvidia,tegra30-flowctrl" },
+        { .compatible = "nvidia,tegra20-flowctrl" },
+        { }
+};
+
+void __init tegra_flowctrl_init(void)
+{
+        /* hardcoded fallback if device tree node is missing */
+        unsigned long base = 0x60007000;
+        unsigned long size = SZ_4K;
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, matches);
+        if (np) {
+                struct resource res;
+
+                if (of_address_to_resource(np, 0, &res) == 0) {
+                        size = resource_size(&res);
+                        base = res.start;
+                }
+
+                of_node_put(np);
+        }
+
+        tegra_flowctrl_base = ioremap_nocache(base, size);
+}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index c89aac60a143..73a9c5016c1a 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
 
 void flowctrl_cpu_suspend_enter(unsigned int cpuid);
 void flowctrl_cpu_suspend_exit(unsigned int cpuid);
+
+void tegra_flowctrl_init(void);
 #endif
 
 #endif
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 5ef5173dec83..ef016af1c9e7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -48,6 +48,7 @@
 #include "board.h"
 #include "common.h"
 #include "cpuidle.h"
+#include "flowctrl.h"
 #include "iomap.h"
 #include "irq.h"
 #include "pm.h"
@@ -74,6 +75,7 @@ static void __init tegra_init_early(void)
 {
         of_register_trusted_foundations();
         tegra_cpu_reset_handler_init();
+        tegra_flowctrl_init();
 }
 
 static void __init tegra_dt_init_irq(void)
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 2c2754e79cb3..f61158c6ce71 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -426,9 +426,15 @@ static int ve_spc_populate_opps(uint32_t cluster)
 
 static int ve_init_opp_table(struct device *cpu_dev)
 {
-        int cluster = topology_physical_package_id(cpu_dev->id);
-        int idx, ret = 0, max_opp = info->num_opps[cluster];
-        struct ve_spc_opp *opps = info->opps[cluster];
+        int cluster;
+        int idx, ret = 0, max_opp;
+        struct ve_spc_opp *opps;
+
+        cluster = topology_physical_package_id(cpu_dev->id);
+        cluster = cluster < 0 ? 0 : cluster;
+
+        max_opp = info->num_opps[cluster];
+        opps = info->opps[cluster];
 
         for (idx = 0; idx < max_opp; idx++, opps++) {
                 ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
@@ -537,6 +543,8 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev)
         spc->hw.init = &init;
         spc->cluster = topology_physical_package_id(cpu_dev->id);
 
+        spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
+
         init.name = dev_name(cpu_dev);
         init.ops = &clk_spc_ops;
         init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 2da7be31e7e2..3bc0dc9a4d69 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -69,7 +69,7 @@ static void vt8500_power_off(void)
 {
         local_irq_disable();
         writew(5, pmc_base + VT8500_HCR_REG);
-        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+        asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (0));
 }
 
 static void __init vt8500_init(void)
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 1b25d92ebf22..c85fb3f7d5cd 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -3,8 +3,7 @@
 #
 
 # Common support
-obj-y                           := common.o slcr.o
+obj-y                           := common.o slcr.o pm.o
 CFLAGS_REMOVE_hotplug.o         =-march=armv6k
 CFLAGS_hotplug.o                =-Wa,-march=armv7-a -mcpu=cortex-a9
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 31a6fa40ba37..26f92c28d22b 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -98,13 +98,19 @@ static int __init zynq_get_revision(void)
         return revision;
 }
 
+static void __init zynq_init_late(void)
+{
+        zynq_core_pm_init();
+        zynq_pm_late_init();
+}
+
 /**
  * zynq_init_machine - System specific initialization, intended to be
  *                     called from board specific initialization.
  */
 static void __init zynq_init_machine(void)
 {
-        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+        struct platform_device_info devinfo = { .name = "cpufreq-dt", };
         struct soc_device_attribute *soc_dev_attr;
         struct soc_device *soc_dev;
         struct device *parent = NULL;
@@ -198,12 +204,13 @@ static const char * const zynq_dt_match[] = {
 
 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
         /* 64KB way size, 8-way associativity, parity disabled */
-        .l2c_aux_val    = 0x02000000,
-        .l2c_aux_mask   = 0xf0ffffff,
+        .l2c_aux_val    = 0x00000000,
+        .l2c_aux_mask   = 0xffffffff,
         .smp            = smp_ops(zynq_smp_ops),
         .map_io         = zynq_map_io,
         .init_irq       = zynq_irq_init,
         .init_machine   = zynq_init_machine,
+        .init_late      = zynq_init_late,
         .init_time      = zynq_timer_init,
         .dt_compat      = zynq_dt_match,
         .reserve        = zynq_memory_init,
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index f652f0a884a6..2bc71273c73c 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -24,6 +24,8 @@ extern int zynq_early_slcr_init(void);
 extern void zynq_slcr_system_reset(void);
 extern void zynq_slcr_cpu_stop(int cpu);
 extern void zynq_slcr_cpu_start(int cpu);
+extern bool zynq_slcr_cpu_state_read(int cpu);
+extern void zynq_slcr_cpu_state_write(int cpu, bool die);
 extern u32 zynq_slcr_get_device_id(void);
 
 #ifdef CONFIG_SMP
@@ -37,7 +39,17 @@ extern struct smp_operations zynq_smp_ops __initdata;
 
 extern void __iomem *zynq_scu_base;
 
-/* Hotplug */
-extern void zynq_platform_cpu_die(unsigned int cpu);
+void zynq_pm_late_init(void);
+
+static inline void zynq_core_pm_init(void)
+{
+        /* A9 clock gating */
+        asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"
+                      "orr  r12, r12, #1\n"
+                      "mcr  p15, 0, r12, c15, c0, 0\n"
+                      : /* no outputs */
+                      : /* no inputs */
+                      : "r12");
+}
 
 #endif
diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
index 5052c70326e4..b685c89f11e4 100644
--- a/arch/arm/mach-zynq/hotplug.c
+++ b/arch/arm/mach-zynq/hotplug.c
@@ -10,50 +10,5 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
+#include <asm/proc-fns.h>
 
-#include <asm/cacheflush.h>
-#include <asm/cp15.h>
-#include "common.h"
-
-static inline void zynq_cpu_enter_lowpower(void)
-{
-        unsigned int v;
-
-        flush_cache_all();
-        asm volatile(
-        "       mcr     p15, 0, %1, c7, c5, 0\n"
-        "       dsb\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x40\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C)
-          : "cc");
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void zynq_platform_cpu_die(unsigned int cpu)
-{
-        zynq_cpu_enter_lowpower();
-
-        /*
-         * there is no power-control hardware on this platform, so all
-         * we can do is put the core into WFI; this is safe as the calling
-         * code will have already disabled interrupts
-         */
-        for (;;)
-                cpu_do_idle();
-}
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index abc82ef085c1..52d768ff7857 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -112,20 +112,59 @@ static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
         scu_enable(zynq_scu_base);
 }
 
+/**
+ * zynq_secondary_init - Initialize secondary CPU cores
+ * @cpu:        CPU that is initialized
+ *
+ * This function is in the hotplug path. Don't move it into the
+ * init section!!
+ */
+static void zynq_secondary_init(unsigned int cpu)
+{
+        zynq_core_pm_init();
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static int zynq_cpu_kill(unsigned cpu)
 {
+        unsigned long timeout = jiffies + msecs_to_jiffies(50);
+
+        while (zynq_slcr_cpu_state_read(cpu))
+                if (time_after(jiffies, timeout))
+                        return 0;
+
         zynq_slcr_cpu_stop(cpu);
         return 1;
 }
+
+/**
+ * zynq_cpu_die - Let a CPU core die
+ * @cpu:        Dying CPU
+ *
+ * Platform-specific code to shutdown a CPU.
+ * Called with IRQs disabled on the dying CPU.
+ */
+static void zynq_cpu_die(unsigned int cpu)
+{
+        zynq_slcr_cpu_state_write(cpu, true);
+
+        /*
+         * there is no power-control hardware on this platform, so all
+         * we can do is put the core into WFI; this is safe as the calling
+         * code will have already disabled interrupts
+         */
+        for (;;)
+                cpu_do_idle();
+}
 #endif
 
 struct smp_operations zynq_smp_ops __initdata = {
         .smp_init_cpus          = zynq_smp_init_cpus,
         .smp_prepare_cpus       = zynq_smp_prepare_cpus,
         .smp_boot_secondary     = zynq_boot_secondary,
+        .smp_secondary_init     = zynq_secondary_init,
 #ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = zynq_platform_cpu_die,
+        .cpu_die                = zynq_cpu_die,
         .cpu_kill               = zynq_cpu_kill,
 #endif
 };
diff --git a/arch/arm/mach-zynq/pm.c b/arch/arm/mach-zynq/pm.c
new file mode 100644
index 000000000000..911fcf865be8
--- /dev/null
+++ b/arch/arm/mach-zynq/pm.c
@@ -0,0 +1,83 @@
+/*
+ * Zynq power management
+ *
+ *  Copyright (C) 2012 - 2014 Xilinx
+ *
+ *  Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include "common.h"
+
+/* register offsets */
+#define DDRC_CTRL_REG1_OFFS             0x60
+#define DDRC_DRAM_PARAM_REG3_OFFS       0x20
+
+/* bitfields */
+#define DDRC_CLOCKSTOP_MASK     BIT(23)
+#define DDRC_SELFREFRESH_MASK   BIT(12)
+
+static void __iomem *ddrc_base;
+
+/**
+ * zynq_pm_ioremap() - Create IO mappings
+ * @comp:       DT compatible string
+ * Return: Pointer to the mapped memory or NULL.
+ *
+ * Remap the memory region for a compatible DT node.
+ */
+static void __iomem *zynq_pm_ioremap(const char *comp)
+{
+        struct device_node *np;
+        void __iomem *base = NULL;
+
+        np = of_find_compatible_node(NULL, NULL, comp);
+        if (np) {
+                base = of_iomap(np, 0);
+                of_node_put(np);
+        } else {
+                pr_warn("%s: no compatible node found for '%s'\n", __func__,
+                                comp);
+        }
+
+        return base;
+}
+
+/**
+ * zynq_pm_late_init() - Power management init
+ *
+ * Initialization of power management related featurs and infrastructure.
+ */
+void __init zynq_pm_late_init(void)
+{
+        u32 reg;
+
+        ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05");
+        if (!ddrc_base) {
+                pr_warn("%s: Unable to map DDRC IO memory.\n", __func__);
+        } else {
+                /*
+                 * Enable DDRC clock stop feature. The HW takes care of
+                 * entering/exiting the correct mode depending
+                 * on activity state.
+                 */
+                reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
+                reg |= DDRC_CLOCKSTOP_MASK;
+                writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
+        }
+}
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index c43a2d16e223..d4cb50cf97c0 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -138,6 +138,8 @@ void zynq_slcr_cpu_start(int cpu)
         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
         reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
+
+        zynq_slcr_cpu_state_write(cpu, false);
 }
 
 /**
@@ -154,8 +156,47 @@ void zynq_slcr_cpu_stop(int cpu)
 }
 
 /**
- * zynq_slcr_init - Regular slcr driver init
+ * zynq_slcr_cpu_state - Read/write cpu state
+ * @cpu:        cpu number
  *
+ * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
+ * 0 means cpu is running, 1 cpu is going to die.
+ *
+ * Return: true if cpu is running, false if cpu is going to die
+ */
+bool zynq_slcr_cpu_state_read(int cpu)
+{
+        u32 state;
+
+        state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+        state &= 1 << (31 - cpu);
+
+        return !state;
+}
+
+/**
+ * zynq_slcr_cpu_state - Read/write cpu state
+ * @cpu:        cpu number
+ * @die:        cpu state - true if cpu is going to die
+ *
+ * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
+ * 0 means cpu is running, 1 cpu is going to die.
+ */
+void zynq_slcr_cpu_state_write(int cpu, bool die)
+{
+        u32 state, mask;
+
+        state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+        mask = 1 << (31 - cpu);
+        if (die)
+                state |= mask;
+        else
+                state &= ~mask;
+        writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+}
+
+/**
+ * zynq_slcr_init - Regular slcr driver init
  * Return:      0 on success, negative errno otherwise.
  *
  * Called early during boot from platform code to remap SLCR area.
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 3815a8262af0..8c48c5c22a33 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -17,12 +17,6 @@
  */
         .align  5
 ENTRY(v6_early_abort)
-#ifdef CONFIG_CPU_V6
-        sub     r1, sp, #4                      @ Get unused stack location
-        strex   r0, r1, [r1]                    @ Clear the exclusive monitor
-#elif defined(CONFIG_CPU_32v6K)
-        clrex
-#endif
         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
 /*
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index 703375277ba6..4812ad054214 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -13,12 +13,6 @@
  */
         .align  5
 ENTRY(v7_early_abort)
-        /*
-         * The effect of data aborts on on the exclusive access monitor are
-         * UNPREDICTABLE. Do a CLREX to clear the state
-         */
-        clrex
-
         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
 
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 0c1ab49e5f7b..83792f4324ea 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -41,6 +41,7 @@
  * This code is not portable to processors with late data abort handling.
  */
 #define CODING_BITS(i)  (i & 0x0e000000)
+#define COND_BITS(i)    (i & 0xf0000000)
 
 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
@@ -821,6 +822,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                 break;
 
         case 0x04000000:        /* ldr or str immediate */
+                if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
+                        goto bad;
                 offset.un = OFFSET_BITS(instr);
                 handler = do_alignment_ldrstr;
                 break;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5f2c988a06ac..55f9d6e0cc88 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
+#include <linux/log2.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -945,6 +946,98 @@ static int l2_wt_override;
  * pass it though the device tree */
 static u32 cache_id_part_number_from_dt;
 
+/**
+ * l2x0_cache_size_of_parse() - read cache size parameters from DT
+ * @np: the device tree node for the l2 cache
+ * @aux_val: pointer to machine-supplied auxilary register value, to
+ * be augmented by the call (bits to be set to 1)
+ * @aux_mask: pointer to machine-supplied auxilary register mask, to
+ * be augmented by the call (bits to be set to 0)
+ * @associativity: variable to return the calculated associativity in
+ * @max_way_size: the maximum size in bytes for the cache ways
+ */
+static void __init l2x0_cache_size_of_parse(const struct device_node *np,
+                                            u32 *aux_val, u32 *aux_mask,
+                                            u32 *associativity,
+                                            u32 max_way_size)
+{
+        u32 mask = 0, val = 0;
+        u32 cache_size = 0, sets = 0;
+        u32 way_size_bits = 1;
+        u32 way_size = 0;
+        u32 block_size = 0;
+        u32 line_size = 0;
+
+        of_property_read_u32(np, "cache-size", &cache_size);
+        of_property_read_u32(np, "cache-sets", &sets);
+        of_property_read_u32(np, "cache-block-size", &block_size);
+        of_property_read_u32(np, "cache-line-size", &line_size);
+
+        if (!cache_size || !sets)
+                return;
+
+        /* All these l2 caches have the same line = block size actually */
+        if (!line_size) {
+                if (block_size) {
+                        /* If linesize if not given, it is equal to blocksize */
+                        line_size = block_size;
+                } else {
+                        /* Fall back to known size */
+                        pr_warn("L2C OF: no cache block/line size given: "
+                                "falling back to default size %d bytes\n",
+                                CACHE_LINE_SIZE);
+                        line_size = CACHE_LINE_SIZE;
+                }
+        }
+
+        if (line_size != CACHE_LINE_SIZE)
+                pr_warn("L2C OF: DT supplied line size %d bytes does "
+                        "not match hardware line size of %d bytes\n",
+                        line_size,
+                        CACHE_LINE_SIZE);
+
+        /*
+         * Since:
+         * set size = cache size / sets
+         * ways = cache size / (sets * line size)
+         * way size = cache size / (cache size / (sets * line size))
+         * way size = sets * line size
+         * associativity = ways = cache size / way size
+         */
+        way_size = sets * line_size;
+        *associativity = cache_size / way_size;
+
+        if (way_size > max_way_size) {
+                pr_err("L2C OF: set size %dKB is too large\n", way_size);
+                return;
+        }
+
+        pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
+                cache_size, cache_size >> 10);
+        pr_info("L2C OF: override line size: %d bytes\n", line_size);
+        pr_info("L2C OF: override way size: %d bytes (%dKB)\n",
+                way_size, way_size >> 10);
+        pr_info("L2C OF: override associativity: %d\n", *associativity);
+
+        /*
+         * Calculates the bits 17:19 to set for way size:
+         * 512KB -> 6, 256KB -> 5, ... 16KB -> 1
+         */
+        way_size_bits = ilog2(way_size >> 10) - 3;
+        if (way_size_bits < 1 || way_size_bits > 6) {
+                pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
+                       way_size);
+                return;
+        }
+
+        mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
+        val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT);
+
+        *aux_val &= ~mask;
+        *aux_val |= val;
+        *aux_mask &= ~mask;
+}
+
 static void __init l2x0_of_parse(const struct device_node *np,
                                  u32 *aux_val, u32 *aux_mask)
 {
@@ -952,6 +1045,7 @@ static void __init l2x0_of_parse(const struct device_node *np,
         u32 tag = 0;
         u32 dirty = 0;
         u32 val = 0, mask = 0;
+        u32 assoc;
 
         of_property_read_u32(np, "arm,tag-latency", &tag);
         if (tag) {
@@ -974,6 +1068,15 @@ static void __init l2x0_of_parse(const struct device_node *np,
                 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
         }
 
+        l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
+        if (assoc > 8) {
+                pr_err("l2x0 of: cache setting yield too high associativity\n");
+                pr_err("l2x0 of: %d calculated, max 8\n", assoc);
+        } else {
+                mask |= L2X0_AUX_CTRL_ASSOC_MASK;
+                val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT);
+        }
+
         *aux_val &= ~mask;
         *aux_val |= val;
         *aux_mask &= ~mask;
@@ -1021,6 +1124,7 @@ static void __init l2c310_of_parse(const struct device_node *np,
         u32 data[3] = { 0, 0, 0 };
         u32 tag[3] = { 0, 0, 0 };
         u32 filter[2] = { 0, 0 };
+        u32 assoc;
 
         of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
         if (tag[0] && tag[1] && tag[2])
@@ -1047,6 +1151,23 @@ static void __init l2c310_of_parse(const struct device_node *np,
                 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
                                l2x0_base + L310_ADDR_FILTER_START);
         }
+
+        l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
+        switch (assoc) {
+        case 16:
+                *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
+                *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16;
+                *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
+                break;
+        case 8:
+                *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
+                *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
+                break;
+        default:
+                pr_err("PL310 OF: cache setting yield illegal associativity\n");
+                pr_err("PL310 OF: %d calculated, only 8 and 16 legal\n", assoc);
+                break;
+        }
 }
 
 static const struct l2c_init_data of_l2c310_data __initconst = {
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 7a996aaa061e..c245d903927f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -12,6 +12,7 @@
 #include <linux/bootmem.h>
 #include <linux/module.h>
 #include <linux/mm.h>
+#include <linux/genalloc.h>
 #include <linux/gfp.h>
 #include <linux/errno.h>
 #include <linux/list.h>
@@ -298,57 +299,29 @@ static void *
 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
         const void *caller)
 {
-        struct vm_struct *area;
-        unsigned long addr;
-
         /*
          * DMA allocation can be mapped to user space, so lets
          * set VM_USERMAP flags too.
          */
-        area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
-                                  caller);
-        if (!area)
-                return NULL;
-        addr = (unsigned long)area->addr;
-        area->phys_addr = __pfn_to_phys(page_to_pfn(page));
-
-        if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
-                vunmap((void *)addr);
-                return NULL;
-        }
-        return (void *)addr;
+        return dma_common_contiguous_remap(page, size,
+                        VM_ARM_DMA_CONSISTENT | VM_USERMAP,
+                        prot, caller);
 }
 
 static void __dma_free_remap(void *cpu_addr, size_t size)
 {
-        unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
-        struct vm_struct *area = find_vm_area(cpu_addr);
-        if (!area || (area->flags & flags) != flags) {
-                WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
-                return;
-        }
-        unmap_kernel_range((unsigned long)cpu_addr, size);
-        vunmap(cpu_addr);
+        dma_common_free_remap(cpu_addr, size,
+                        VM_ARM_DMA_CONSISTENT | VM_USERMAP);
 }
 
 #define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_256K
+static struct gen_pool *atomic_pool;
 
-struct dma_pool {
-        size_t size;
-        spinlock_t lock;
-        unsigned long *bitmap;
-        unsigned long nr_pages;
-        void *vaddr;
-        struct page **pages;
-};
-
-static struct dma_pool atomic_pool = {
-        .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
-};
+static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
 
 static int __init early_coherent_pool(char *p)
 {
-        atomic_pool.size = memparse(p, &p);
+        atomic_pool_size = memparse(p, &p);
         return 0;
 }
 early_param("coherent_pool", early_coherent_pool);
@@ -358,14 +331,14 @@ void __init init_dma_coherent_pool_size(unsigned long size)
         /*
          * Catch any attempt to set the pool size too late.
          */
-        BUG_ON(atomic_pool.vaddr);
+        BUG_ON(atomic_pool);
 
         /*
          * Set architecture specific coherent pool size only if
          * it has not been changed by kernel command line parameter.
          */
-        if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
-                atomic_pool.size = size;
+        if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
+                atomic_pool_size = size;
 }
 
 /*
@@ -373,52 +346,44 @@ void __init init_dma_coherent_pool_size(unsigned long size)
  */
 static int __init atomic_pool_init(void)
 {
-        struct dma_pool *pool = &atomic_pool;
         pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
         gfp_t gfp = GFP_KERNEL | GFP_DMA;
-        unsigned long nr_pages = pool->size >> PAGE_SHIFT;
-        unsigned long *bitmap;
         struct page *page;
-        struct page **pages;
         void *ptr;
-        int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
 
-        bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-        if (!bitmap)
-                goto no_bitmap;
-
-        pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
-        if (!pages)
-                goto no_pages;
+        atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
+        if (!atomic_pool)
+                goto out;
 
         if (dev_get_cma_area(NULL))
-                ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
-                                              atomic_pool_init);
+                ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
+                                              &page, atomic_pool_init);
         else
-                ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
-                                           atomic_pool_init);
+                ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
+                                           &page, atomic_pool_init);
         if (ptr) {
-                int i;
-
-                for (i = 0; i < nr_pages; i++)
-                        pages[i] = page + i;
-
-                spin_lock_init(&pool->lock);
-                pool->vaddr = ptr;
-                pool->pages = pages;
-                pool->bitmap = bitmap;
-                pool->nr_pages = nr_pages;
-                pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
-                       (unsigned)pool->size / 1024);
+                int ret;
+
+                ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
+                                        page_to_phys(page),
+                                        atomic_pool_size, -1);
+                if (ret)
+                        goto destroy_genpool;
+
+                gen_pool_set_algo(atomic_pool,
+                                gen_pool_first_fit_order_align,
+                                (void *)PAGE_SHIFT);
+                pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n",
+                       atomic_pool_size / 1024);
                 return 0;
         }
 
-        kfree(pages);
-no_pages:
-        kfree(bitmap);
-no_bitmap:
-        pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
-               (unsigned)pool->size / 1024);
+destroy_genpool:
+        gen_pool_destroy(atomic_pool);
+        atomic_pool = NULL;
+out:
+        pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n",
+               atomic_pool_size / 1024);
         return -ENOMEM;
 }
 /*
@@ -522,76 +487,36 @@ static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
 
 static void *__alloc_from_pool(size_t size, struct page **ret_page)
 {
-        struct dma_pool *pool = &atomic_pool;
-        unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
-        unsigned int pageno;
-        unsigned long flags;
+        unsigned long val;
         void *ptr = NULL;
-        unsigned long align_mask;
 
-        if (!pool->vaddr) {
+        if (!atomic_pool) {
                 WARN(1, "coherent pool not initialised!\n");
                 return NULL;
         }
 
-        /*
-         * Align the region allocation - allocations from pool are rather
-         * small, so align them to their order in pages, minimum is a page
-         * size. This helps reduce fragmentation of the DMA space.
-         */
-        align_mask = (1 << get_order(size)) - 1;
-
-        spin_lock_irqsave(&pool->lock, flags);
-        pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
-                                            0, count, align_mask);
-        if (pageno < pool->nr_pages) {
-                bitmap_set(pool->bitmap, pageno, count);
-                ptr = pool->vaddr + PAGE_SIZE * pageno;
-                *ret_page = pool->pages[pageno];
-        } else {
-                pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
-                            "Please increase it with coherent_pool= kernel parameter!\n",
-                            (unsigned)pool->size / 1024);
+        val = gen_pool_alloc(atomic_pool, size);
+        if (val) {
+                phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
+
+                *ret_page = phys_to_page(phys);
+                ptr = (void *)val;
         }
-        spin_unlock_irqrestore(&pool->lock, flags);
 
         return ptr;
 }
 
 static bool __in_atomic_pool(void *start, size_t size)
 {
-        struct dma_pool *pool = &atomic_pool;
-        void *end = start + size;
-        void *pool_start = pool->vaddr;
-        void *pool_end = pool->vaddr + pool->size;
-
-        if (start < pool_start || start >= pool_end)
-                return false;
-
-        if (end <= pool_end)
-                return true;
-
-        WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
-             start, end - 1, pool_start, pool_end - 1);
-
-        return false;
+        return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
 }
 
 static int __free_from_pool(void *start, size_t size)
 {
-        struct dma_pool *pool = &atomic_pool;
-        unsigned long pageno, count;
-        unsigned long flags;
-
         if (!__in_atomic_pool(start, size))
                 return 0;
 
-        pageno = (start - pool->vaddr) >> PAGE_SHIFT;
-        count = size >> PAGE_SHIFT;
-
-        spin_lock_irqsave(&pool->lock, flags);
-        bitmap_clear(pool->bitmap, pageno, count);
-        spin_unlock_irqrestore(&pool->lock, flags);
+        gen_pool_free(atomic_pool, (unsigned long)start, size);
 
         return 1;
 }
@@ -1271,29 +1196,8 @@ static void *
 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
                     const void *caller)
 {
-        unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
-        struct vm_struct *area;
-        unsigned long p;
-
-        area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
-                                  caller);
-        if (!area)
-                return NULL;
-
-        area->pages = pages;
-        area->nr_pages = nr_pages;
-        p = (unsigned long)area->addr;
-
-        for (i = 0; i < nr_pages; i++) {
-                phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
-                if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
-                        goto err;
-                p += PAGE_SIZE;
-        }
-        return area->addr;
-err:
-        unmap_kernel_range((unsigned long)area->addr, size);
-        vunmap(area->addr);
+        return dma_common_pages_remap(pages, size,
+                        VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
         return NULL;
 }
 
@@ -1355,11 +1259,13 @@ static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t si
 
 static struct page **__atomic_get_pages(void *addr)
 {
-        struct dma_pool *pool = &atomic_pool;
-        struct page **pages = pool->pages;
-        int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
+        struct page *page;
+        phys_addr_t phys;
+
+        phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
+        page = phys_to_page(phys);
 
-        return pages + offs;
+        return (struct page **)page;
 }
 
 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
@@ -1501,8 +1407,8 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
         }
 
         if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
-                unmap_kernel_range((unsigned long)cpu_addr, size);
-                vunmap(cpu_addr);
+                dma_common_free_remap(cpu_addr, size,
+                        VM_ARM_DMA_CONSISTENT | VM_USERMAP);
         }
 
         __iommu_remove_mapping(dev, handle, size);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 43d54f5b26b9..265b836b3bd1 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -400,3 +400,18 @@ void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned l
          */
         __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
+                          pmd_t *pmdp)
+{
+        pmd_t pmd = pmd_mksplitting(*pmdp);
+        VM_BUG_ON(address & ~PMD_MASK);
+        set_pmd_at(vma->vm_mm, address, pmdp, pmd);
+
+        /* dummy IPI to serialise against fast_gup */
+        kick_all_cpus_sync();
+}
+#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index c447ec70e868..e7a81cebbb2e 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -27,7 +27,7 @@ static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end,
         if (pud_none_or_clear_bad(pud) || (pud_val(*pud) & L_PGD_SWAPPER)) {
                 pmd = pmd_alloc_one(&init_mm, addr);
                 if (!pmd) {
-                        pr_warning("Failed to allocate identity pmd.\n");
+                        pr_warn("Failed to allocate identity pmd.\n");
                         return;
                 }
                 /*
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 659c75d808dc..92bba32d9230 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -322,7 +322,7 @@ void __init arm_memblock_init(const struct machine_desc *mdesc)
          * reserve memory for DMA contigouos allocations,
          * must come from DMA area inside low memory
          */
-        dma_contiguous_reserve(min(arm_dma_limit, arm_lowmem_limit));
+        dma_contiguous_reserve(arm_dma_limit);
 
         arm_memblock_steal_permitted = false;
         memblock_dump_all();
@@ -636,6 +636,11 @@ static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (!keep_initrd) {
+                if (start == initrd_start)
+                        start = round_down(start, PAGE_SIZE);
+                if (end == initrd_end)
+                        end = round_up(end, PAGE_SIZE);
+
                 poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
                 free_reserved_area((void *)start, (void *)end, -1, "initrd");
         }
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 8348ed6b2efe..9f98cec7fe1e 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -223,13 +223,13 @@ early_param("ecc", early_ecc);
 
 static int __init early_cachepolicy(char *p)
 {
-        pr_warning("cachepolicy kernel parameter not supported without cp15\n");
+        pr_warn("cachepolicy kernel parameter not supported without cp15\n");
 }
 early_param("cachepolicy", early_cachepolicy);
 
 static int __init noalign_setup(char *__unused)
 {
-        pr_warning("noalign kernel parameter not supported without cp15\n");
+        pr_warn("noalign kernel parameter not supported without cp15\n");
 }
 __setup("noalign", noalign_setup);
 
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 1a24e9232ec8..d3daed0ae0ad 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -146,7 +146,6 @@ ENDPROC(cpu_v7_set_pte_ext)
         mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
         mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
         addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
-        adcls   \tmp, \tmp, #0
         mcrr    p15, 1, \ttbr1, \tmp, c2                        @ load TTBR1
         mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
         mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
@@ -158,9 +157,9 @@ ENDPROC(cpu_v7_set_pte_ext)
          *  TFR   EV X F   IHD LR    S
          * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
          * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
-         *   11    0 110    1  0011 1100 .111 1101 < we want
+         *   11    0 110    0  0011 1100 .111 1101 < we want
          */
         .align  2
         .type   v7_crval, #object
 v7_crval:
-        crval   clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
+        crval   clear=0x0122c302, mmuset=0x30c03c7d, ucset=0x00c01c7c
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b5d67db20897..b3a947863ac7 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -570,7 +570,7 @@ __v7_ca15mp_proc_info:
 __v7_b15mp_proc_info:
         .long   0x420f00f0
         .long   0xff0ffff0
-        __v7_proc __v7_b15mp_setup, hwcaps = HWCAP_IDIV
+        __v7_proc __v7_b15mp_setup
         .size   __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
 
         /*
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index a37b989a2f91..e1268f905026 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -12,11 +12,11 @@
 #include <linux/compiler.h>
 #include <linux/errno.h>
 #include <linux/filter.h>
-#include <linux/moduleloader.h>
 #include <linux/netdevice.h>
 #include <linux/string.h>
 #include <linux/slab.h>
 #include <linux/if_vlan.h>
+
 #include <asm/cacheflush.h>
 #include <asm/hwcap.h>
 #include <asm/opcodes.h>
@@ -174,6 +174,14 @@ static inline bool is_load_to_a(u16 inst)
         }
 }
 
+static void jit_fill_hole(void *area, unsigned int size)
+{
+        u32 *ptr;
+        /* We are guaranteed to have aligned memory. */
+        for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
+                *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
+}
+
 static void build_prologue(struct jit_ctx *ctx)
 {
         u16 reg_set = saved_regs(ctx);
@@ -859,9 +867,11 @@ b_epilogue:
 
 void bpf_jit_compile(struct bpf_prog *fp)
 {
+        struct bpf_binary_header *header;
         struct jit_ctx ctx;
         unsigned tmp_idx;
         unsigned alloc_size;
+        u8 *target_ptr;
 
         if (!bpf_jit_enable)
                 return;
@@ -897,13 +907,15 @@ void bpf_jit_compile(struct bpf_prog *fp)
         /* there's nothing after the epilogue on ARMv7 */
         build_epilogue(&ctx);
 #endif
-
         alloc_size = 4 * ctx.idx;
-        ctx.target = module_alloc(alloc_size);
-        if (unlikely(ctx.target == NULL))
+        header = bpf_jit_binary_alloc(alloc_size, &target_ptr,
+                                      4, jit_fill_hole);
+        if (header == NULL)
                 goto out;
 
+        ctx.target = (u32 *) target_ptr;
         ctx.idx = 0;
+
         build_prologue(&ctx);
         build_body(&ctx);
         build_epilogue(&ctx);
@@ -919,8 +931,9 @@ void bpf_jit_compile(struct bpf_prog *fp)
                 /* there are 2 passes here */
                 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
 
+        set_memory_ro((unsigned long)header, header->pages);
         fp->bpf_func = (void *)ctx.target;
-        fp->jited = 1;
+        fp->jited = true;
 out:
         kfree(ctx.offsets);
         return;
@@ -928,7 +941,15 @@ out:
 
 void bpf_jit_free(struct bpf_prog *fp)
 {
-        if (fp->jited)
-                module_free(NULL, fp->bpf_func);
-        kfree(fp);
+        unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
+        struct bpf_binary_header *header = (void *)addr;
+
+        if (!fp->jited)
+                goto free_filter;
+
+        set_memory_rw(addr, header->pages);
+        bpf_jit_binary_free(header);
+
+free_filter:
+        bpf_prog_unlock_free(fp);
 }
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index afb84621ff6f..b2d7d92859d3 100644
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -114,6 +114,20 @@
 
 #define ARM_INST_UMULL          0x00800090
 
+/*
+ * Use a suitable undefined instruction to use for ARM/Thumb2 faulting.
+ * We need to be careful not to conflict with those used by other modules
+ * (BUG, kprobes, etc) and the register_undef_hook() system.
+ *
+ * The ARM architecture reference manual guarantees that the following
+ * instruction space will produce an undefined instruction exception on
+ * all CPUs:
+ *
+ * ARM:   xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx       ARMv7-AR, section A5.4
+ * Thumb: 1101 1110 xxxx xxxx                           ARMv7-M, section A5.2.6
+ */
+#define ARM_INST_UDF            0xe7fddef1
+
 /* register */
 #define _AL3_R(op, rd, rn, rm)  ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
 /* immediate */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 02fc10d2d63b..d055db32ffcb 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -1,3 +1,6 @@
+config ARCH_OMAP
+        bool
+
 if ARCH_OMAP
 
 menu "TI OMAP Common Features"
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c2baa8ede543..24770e5a5081 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -64,7 +64,9 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 
 static struct omap_system_dma_plat_info *p;
 static struct omap_dma_dev_attr *d;
-
+static void omap_clear_dma(int lch);
+static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
+                                 unsigned char write_prio);
 static int enable_1510_mode;
 static u32 errata;
 
@@ -284,66 +286,6 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 }
 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 
-void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
-{
-        BUG_ON(omap_dma_in_1510_mode());
-
-        if (dma_omap1()) {
-                u16 w;
-
-                w = p->dma_read(CCR2, lch);
-                w &= ~0x03;
-
-                switch (mode) {
-                case OMAP_DMA_CONSTANT_FILL:
-                        w |= 0x01;
-                        break;
-                case OMAP_DMA_TRANSPARENT_COPY:
-                        w |= 0x02;
-                        break;
-                case OMAP_DMA_COLOR_DIS:
-                        break;
-                default:
-                        BUG();
-                }
-                p->dma_write(w, CCR2, lch);
-
-                w = p->dma_read(LCH_CTRL, lch);
-                w &= ~0x0f;
-                /* Default is channel type 2D */
-                if (mode) {
-                        p->dma_write(color, COLOR, lch);
-                        w |= 1;         /* Channel type G */
-                }
-                p->dma_write(w, LCH_CTRL, lch);
-        }
-
-        if (dma_omap2plus()) {
-                u32 val;
-
-                val = p->dma_read(CCR, lch);
-                val &= ~((1 << 17) | (1 << 16));
-
-                switch (mode) {
-                case OMAP_DMA_CONSTANT_FILL:
-                        val |= 1 << 16;
-                        break;
-                case OMAP_DMA_TRANSPARENT_COPY:
-                        val |= 1 << 17;
-                        break;
-                case OMAP_DMA_COLOR_DIS:
-                        break;
-                default:
-                        BUG();
-                }
-                p->dma_write(val, CCR, lch);
-
-                color &= 0xffffff;
-                p->dma_write(color, COLOR, lch);
-        }
-}
-EXPORT_SYMBOL(omap_set_dma_color_mode);
-
 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 {
         if (dma_omap2plus()) {
@@ -417,16 +359,6 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 }
 EXPORT_SYMBOL(omap_set_dma_params);
 
-void omap_set_dma_src_index(int lch, int eidx, int fidx)
-{
-        if (dma_omap2plus())
-                return;
-
-        p->dma_write(eidx, CSEI, lch);
-        p->dma_write(fidx, CSFI, lch);
-}
-EXPORT_SYMBOL(omap_set_dma_src_index);
-
 void omap_set_dma_src_data_pack(int lch, int enable)
 {
         u32 l;
@@ -510,16 +442,6 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 }
 EXPORT_SYMBOL(omap_set_dma_dest_params);
 
-void omap_set_dma_dest_index(int lch, int eidx, int fidx)
-{
-        if (dma_omap2plus())
-                return;
-
-        p->dma_write(eidx, CDEI, lch);
-        p->dma_write(fidx, CDFI, lch);
-}
-EXPORT_SYMBOL(omap_set_dma_dest_index);
-
 void omap_set_dma_dest_data_pack(int lch, int enable)
 {
         u32 l;
@@ -843,7 +765,7 @@ EXPORT_SYMBOL(omap_dma_set_global_params);
  * Both of the above can be set with one of the following values :
  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
  */
-int
+static int
 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                       unsigned char write_prio)
 {
@@ -864,13 +786,13 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 
         return 0;
 }
-EXPORT_SYMBOL(omap_dma_set_prio_lch);
+
 
 /*
  * Clears any DMA state so the DMA engine is ready to restart with new buffers
  * through omap_start_dma(). Any buffers in flight are discarded.
  */
-void omap_clear_dma(int lch)
+static void omap_clear_dma(int lch)
 {
         unsigned long flags;
 
@@ -878,7 +800,6 @@ void omap_clear_dma(int lch)
         p->clear_dma(lch);
         local_irq_restore(flags);
 }
-EXPORT_SYMBOL(omap_clear_dma);
 
 void omap_start_dma(int lch)
 {
@@ -1167,652 +1088,6 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
 }
 EXPORT_SYMBOL(omap_dma_link_lch);
 
-/*
- * Once the DMA queue is stopped, we can destroy it.
- */
-void omap_dma_unlink_lch(int lch_head, int lch_queue)
-{
-        if (omap_dma_in_1510_mode()) {
-                if (lch_head == lch_queue) {
-                        p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
-                                                                CCR, lch_head);
-                        return;
-                }
-                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
-                BUG();
-                return;
-        }
-
-        if (dma_chan[lch_head].next_lch != lch_queue ||
-            dma_chan[lch_head].next_lch == -1) {
-                pr_err("omap_dma: trying to unlink non linked channels\n");
-                dump_stack();
-        }
-
-        if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
-            (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
-                pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
-                dump_stack();
-        }
-
-        dma_chan[lch_head].next_lch = -1;
-}
-EXPORT_SYMBOL(omap_dma_unlink_lch);
-
-#ifndef CONFIG_ARCH_OMAP1
-/* Create chain of DMA channesls */
-static void create_dma_lch_chain(int lch_head, int lch_queue)
-{
-        u32 l;
-
-        /* Check if this is the first link in chain */
-        if (dma_chan[lch_head].next_linked_ch == -1) {
-                dma_chan[lch_head].next_linked_ch = lch_queue;
-                dma_chan[lch_head].prev_linked_ch = lch_queue;
-                dma_chan[lch_queue].next_linked_ch = lch_head;
-                dma_chan[lch_queue].prev_linked_ch = lch_head;
-        }
-
-        /* a link exists, link the new channel in circular chain */
-        else {
-                dma_chan[lch_queue].next_linked_ch =
-                                        dma_chan[lch_head].next_linked_ch;
-                dma_chan[lch_queue].prev_linked_ch = lch_head;
-                dma_chan[lch_head].next_linked_ch = lch_queue;
-                dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
-                                        lch_queue;
-        }
-
-        l = p->dma_read(CLNK_CTRL, lch_head);
-        l &= ~(0x1f);
-        l |= lch_queue;
-        p->dma_write(l, CLNK_CTRL, lch_head);
-
-        l = p->dma_read(CLNK_CTRL, lch_queue);
-        l &= ~(0x1f);
-        l |= (dma_chan[lch_queue].next_linked_ch);
-        p->dma_write(l, CLNK_CTRL, lch_queue);
-}
-
-/**
- * @brief omap_request_dma_chain : Request a chain of DMA channels
- *
- * @param dev_id - Device id using the dma channel
- * @param dev_name - Device name
- * @param callback - Call back function
- * @chain_id -
- * @no_of_chans - Number of channels requested
- * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
- *                                            OMAP_DMA_DYNAMIC_CHAIN
- * @params - Channel parameters
- *
- * @return - Success : 0
- *           Failure: -EINVAL/-ENOMEM
- */
-int omap_request_dma_chain(int dev_id, const char *dev_name,
-                           void (*callback) (int lch, u16 ch_status,
-                                             void *data),
-                           int *chain_id, int no_of_chans, int chain_mode,
-                           struct omap_dma_channel_params params)
-{
-        int *channels;
-        int i, err;
-
-        /* Is the chain mode valid ? */
-        if (chain_mode != OMAP_DMA_STATIC_CHAIN
-                        && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
-                printk(KERN_ERR "Invalid chain mode requested\n");
-                return -EINVAL;
-        }
-
-        if (unlikely((no_of_chans < 1
-                        || no_of_chans > dma_lch_count))) {
-                printk(KERN_ERR "Invalid Number of channels requested\n");
-                return -EINVAL;
-        }
-
-        /*
-         * Allocate a queue to maintain the status of the channels
-         * in the chain
-         */
-        channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
-        if (channels == NULL) {
-                printk(KERN_ERR "omap_dma: No memory for channel queue\n");
-                return -ENOMEM;
-        }
-
-        /* request and reserve DMA channels for the chain */
-        for (i = 0; i < no_of_chans; i++) {
-                err = omap_request_dma(dev_id, dev_name,
-                                        callback, NULL, &channels[i]);
-                if (err < 0) {
-                        int j;
-                        for (j = 0; j < i; j++)
-                                omap_free_dma(channels[j]);
-                        kfree(channels);
-                        printk(KERN_ERR "omap_dma: Request failed %d\n", err);
-                        return err;
-                }
-                dma_chan[channels[i]].prev_linked_ch = -1;
-                dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
-
-                /*
-                 * Allowing client drivers to set common parameters now,
-                 * so that later only relevant (src_start, dest_start
-                 * and element count) can be set
-                 */
-                omap_set_dma_params(channels[i], &params);
-        }
-
-        *chain_id = channels[0];
-        dma_linked_lch[*chain_id].linked_dmach_q = channels;
-        dma_linked_lch[*chain_id].chain_mode = chain_mode;
-        dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
-        dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
-
-        for (i = 0; i < no_of_chans; i++)
-                dma_chan[channels[i]].chain_id = *chain_id;
-
-        /* Reset the Queue pointers */
-        OMAP_DMA_CHAIN_QINIT(*chain_id);
-
-        /* Set up the chain */
-        if (no_of_chans == 1)
-                create_dma_lch_chain(channels[0], channels[0]);
-        else {
-                for (i = 0; i < (no_of_chans - 1); i++)
-                        create_dma_lch_chain(channels[i], channels[i + 1]);
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_request_dma_chain);
-
-/**
- * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
- * params after setting it. Dont do this while dma is running!!
- *
- * @param chain_id - Chained logical channel id.
- * @param params
- *
- * @return - Success : 0
- *           Failure : -EINVAL
- */
-int omap_modify_dma_chain_params(int chain_id,
-                                struct omap_dma_channel_params params)
-{
-        int *channels;
-        u32 i;
-
-        /* Check for input params */
-        if (unlikely((chain_id < 0
-                        || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exists\n");
-                return -EINVAL;
-        }
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-
-        for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
-                /*
-                 * Allowing client drivers to set common parameters now,
-                 * so that later only relevant (src_start, dest_start
-                 * and element count) can be set
-                 */
-                omap_set_dma_params(channels[i], &params);
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_modify_dma_chain_params);
-
-/**
- * @brief omap_free_dma_chain - Free all the logical channels in a chain.
- *
- * @param chain_id
- *
- * @return - Success : 0
- *           Failure : -EINVAL
- */
-int omap_free_dma_chain(int chain_id)
-{
-        int *channels;
-        u32 i;
-
-        /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exists\n");
-                return -EINVAL;
-        }
-
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-        for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
-                dma_chan[channels[i]].next_linked_ch = -1;
-                dma_chan[channels[i]].prev_linked_ch = -1;
-                dma_chan[channels[i]].chain_id = -1;
-                dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
-                omap_free_dma(channels[i]);
-        }
-
-        kfree(channels);
-
-        dma_linked_lch[chain_id].linked_dmach_q = NULL;
-        dma_linked_lch[chain_id].chain_mode = -1;
-        dma_linked_lch[chain_id].chain_state = -1;
-
-        return (0);
-}
-EXPORT_SYMBOL(omap_free_dma_chain);
-
-/**
- * @brief omap_dma_chain_status - Check if the chain is in
- * active / inactive state.
- * @param chain_id
- *
- * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
- *           Failure : -EINVAL
- */
-int omap_dma_chain_status(int chain_id)
-{
-        /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exists\n");
-                return -EINVAL;
-        }
-        pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
-                        dma_linked_lch[chain_id].q_count);
-
-        if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
-                return OMAP_DMA_CHAIN_INACTIVE;
-
-        return OMAP_DMA_CHAIN_ACTIVE;
-}
-EXPORT_SYMBOL(omap_dma_chain_status);
-
-/**
- * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
- * set the params and start the transfer.
- *
- * @param chain_id
- * @param src_start - buffer start address
- * @param dest_start - Dest address
- * @param elem_count
- * @param frame_count
- * @param callbk_data - channel callback parameter data.
- *
- * @return  - Success : 0
- *            Failure: -EINVAL/-EBUSY
- */
-int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
-                        int elem_count, int frame_count, void *callbk_data)
-{
-        int *channels;
-        u32 l, lch;
-        int start_dma = 0;
-
-        /*
-         * if buffer size is less than 1 then there is
-         * no use of starting the chain
-         */
-        if (elem_count < 1) {
-                printk(KERN_ERR "Invalid buffer size\n");
-                return -EINVAL;
-        }
-
-        /* Check for input params */
-        if (unlikely((chain_id < 0
-                        || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exist\n");
-                return -EINVAL;
-        }
-
-        /* Check if all the channels in chain are in use */
-        if (OMAP_DMA_CHAIN_QFULL(chain_id))
-                return -EBUSY;
-
-        /* Frame count may be negative in case of indexed transfers */
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-
-        /* Get a free channel */
-        lch = channels[dma_linked_lch[chain_id].q_tail];
-
-        /* Store the callback data */
-        dma_chan[lch].data = callbk_data;
-
-        /* Increment the q_tail */
-        OMAP_DMA_CHAIN_INCQTAIL(chain_id);
-
-        /* Set the params to the free channel */
-        if (src_start != 0)
-                p->dma_write(src_start, CSSA, lch);
-        if (dest_start != 0)
-                p->dma_write(dest_start, CDSA, lch);
-
-        /* Write the buffer size */
-        p->dma_write(elem_count, CEN, lch);
-        p->dma_write(frame_count, CFN, lch);
-
-        /*
-         * If the chain is dynamically linked,
-         * then we may have to start the chain if its not active
-         */
-        if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
-
-                /*
-                 * In Dynamic chain, if the chain is not started,
-                 * queue the channel
-                 */
-                if (dma_linked_lch[chain_id].chain_state ==
-                                                DMA_CHAIN_NOTSTARTED) {
-                        /* Enable the link in previous channel */
-                        if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
-                                                                DMA_CH_QUEUED)
-                                enable_lnk(dma_chan[lch].prev_linked_ch);
-                        dma_chan[lch].state = DMA_CH_QUEUED;
-                }
-
-                /*
-                 * Chain is already started, make sure its active,
-                 * if not then start the chain
-                 */
-                else {
-                        start_dma = 1;
-
-                        if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
-                                                        DMA_CH_STARTED) {
-                                enable_lnk(dma_chan[lch].prev_linked_ch);
-                                dma_chan[lch].state = DMA_CH_QUEUED;
-                                start_dma = 0;
-                                if (0 == ((1 << 7) & p->dma_read(
-                                        CCR, dma_chan[lch].prev_linked_ch))) {
-                                        disable_lnk(dma_chan[lch].
-                                                    prev_linked_ch);
-                                        pr_debug("\n prev ch is stopped\n");
-                                        start_dma = 1;
-                                }
-                        }
-
-                        else if (dma_chan[dma_chan[lch].prev_linked_ch].state
-                                                        == DMA_CH_QUEUED) {
-                                enable_lnk(dma_chan[lch].prev_linked_ch);
-                                dma_chan[lch].state = DMA_CH_QUEUED;
-                                start_dma = 0;
-                        }
-                        omap_enable_channel_irq(lch);
-
-                        l = p->dma_read(CCR, lch);
-
-                        if ((0 == (l & (1 << 24))))
-                                l &= ~(1 << 25);
-                        else
-                                l |= (1 << 25);
-                        if (start_dma == 1) {
-                                if (0 == (l & (1 << 7))) {
-                                        l |= (1 << 7);
-                                        dma_chan[lch].state = DMA_CH_STARTED;
-                                        pr_debug("starting %d\n", lch);
-                                        p->dma_write(l, CCR, lch);
-                                } else
-                                        start_dma = 0;
-                        } else {
-                                if (0 == (l & (1 << 7)))
-                                        p->dma_write(l, CCR, lch);
-                        }
-                        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
-                }
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_dma_chain_a_transfer);
-
-/**
- * @brief omap_start_dma_chain_transfers - Start the chain
- *
- * @param chain_id
- *
- * @return - Success : 0
- *           Failure : -EINVAL/-EBUSY
- */
-int omap_start_dma_chain_transfers(int chain_id)
-{
-        int *channels;
-        u32 l, i;
-
-        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-
-        if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
-                printk(KERN_ERR "Chain is already started\n");
-                return -EBUSY;
-        }
-
-        if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
-                for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
-                                                                        i++) {
-                        enable_lnk(channels[i]);
-                        omap_enable_channel_irq(channels[i]);
-                }
-        } else {
-                omap_enable_channel_irq(channels[0]);
-        }
-
-        l = p->dma_read(CCR, channels[0]);
-        l |= (1 << 7);
-        dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
-        dma_chan[channels[0]].state = DMA_CH_STARTED;
-
-        if ((0 == (l & (1 << 24))))
-                l &= ~(1 << 25);
-        else
-                l |= (1 << 25);
-        p->dma_write(l, CCR, channels[0]);
-
-        dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_start_dma_chain_transfers);
-
-/**
- * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
- *
- * @param chain_id
- *
- * @return - Success : 0
- *           Failure : EINVAL
- */
-int omap_stop_dma_chain_transfers(int chain_id)
-{
-        int *channels;
-        u32 l, i;
-        u32 sys_cf = 0;
-
-        /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exists\n");
-                return -EINVAL;
-        }
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-
-        if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
-                sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
-                l = sys_cf;
-                /* Middle mode reg set no Standby */
-                l &= ~((1 << 12)|(1 << 13));
-                p->dma_write(l, OCP_SYSCONFIG, 0);
-        }
-
-        for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
-
-                /* Stop the Channel transmission */
-                l = p->dma_read(CCR, channels[i]);
-                l &= ~(1 << 7);
-                p->dma_write(l, CCR, channels[i]);
-
-                /* Disable the link in all the channels */
-                disable_lnk(channels[i]);
-                dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
-
-        }
-        dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
-
-        /* Reset the Queue pointers */
-        OMAP_DMA_CHAIN_QINIT(chain_id);
-
-        if (IS_DMA_ERRATA(DMA_ERRATA_i88))
-                p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
-
-/* Get the index of the ongoing DMA in chain */
-/**
- * @brief omap_get_dma_chain_index - Get the element and frame index
- * of the ongoing DMA in chain
- *
- * @param chain_id
- * @param ei - Element index
- * @param fi - Frame index
- *
- * @return - Success : 0
- *           Failure : -EINVAL
- */
-int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
-{
-        int lch;
-        int *channels;
-
-        /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exists\n");
-                return -EINVAL;
-        }
-        if ((!ei) || (!fi))
-                return -EINVAL;
-
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-
-        /* Get the current channel */
-        lch = channels[dma_linked_lch[chain_id].q_head];
-
-        *ei = p->dma_read(CCEN, lch);
-        *fi = p->dma_read(CCFN, lch);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_get_dma_chain_index);
-
-/**
- * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
- * ongoing DMA in chain
- *
- * @param chain_id
- *
- * @return - Success : Destination position
- *           Failure : -EINVAL
- */
-int omap_get_dma_chain_dst_pos(int chain_id)
-{
-        int lch;
-        int *channels;
-
-        /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exists\n");
-                return -EINVAL;
-        }
-
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-
-        /* Get the current channel */
-        lch = channels[dma_linked_lch[chain_id].q_head];
-
-        return p->dma_read(CDAC, lch);
-}
-EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
-
-/**
- * @brief omap_get_dma_chain_src_pos - Get the source position
- * of the ongoing DMA in chain
- * @param chain_id
- *
- * @return - Success : Destination position
- *           Failure : -EINVAL
- */
-int omap_get_dma_chain_src_pos(int chain_id)
-{
-        int lch;
-        int *channels;
-
-        /* Check for input params */
-        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
-                printk(KERN_ERR "Invalid chain id\n");
-                return -EINVAL;
-        }
-
-        /* Check if the chain exists */
-        if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
-                printk(KERN_ERR "Chain doesn't exists\n");
-                return -EINVAL;
-        }
-
-        channels = dma_linked_lch[chain_id].linked_dmach_q;
-
-        /* Get the current channel */
-        lch = channels[dma_linked_lch[chain_id].q_head];
-
-        return p->dma_read(CSAC, lch);
-}
-EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
-#endif  /* ifndef CONFIG_ARCH_OMAP1 */
-
 /*----------------------------------------------------------------------------*/
 
 #ifdef CONFIG_ARCH_OMAP1
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 3ec6e8e8d368..f5b00f41c4f6 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -499,7 +499,7 @@ void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
 
         d->netdev = &orion_ge00.dev;
         for (i = 0; i < d->nr_chips; i++)
-                d->chip[i].mii_bus = &orion_ge00_shared.dev;
+                d->chip[i].host_dev = &orion_ge00_shared.dev;
         orion_switch_device.dev.platform_data = d;
 
         platform_device_register(&orion_switch_device);
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
index 3ea02903d75a..1f5ee17a10e8 100644
--- a/arch/arm/plat-pxa/ssp.c
+++ b/arch/arm/plat-pxa/ssp.c
@@ -258,6 +258,7 @@ static const struct platform_device_id ssp_id_table[] = {
         { "pxa25x-ssp",         PXA25x_SSP },
         { "pxa25x-nssp",        PXA25x_NSSP },
         { "pxa27x-ssp",         PXA27x_SSP },
+        { "pxa3xx-ssp",         PXA3xx_SSP },
         { "pxa168-ssp",         PXA168_SSP },
         { "pxa910-ssp",         PXA910_SSP },
         { },
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
index 12969523414c..1f85bfe6b470 100644
--- a/arch/arm/xen/Makefile
+++ b/arch/arm/xen/Makefile
@@ -1 +1 @@
-obj-y           := enlighten.o hypercall.o grant-table.o p2m.o mm.o
+obj-y           := enlighten.o hypercall.o grant-table.o p2m.o mm.o mm32.o
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 98544c5f86e9..0e15f011f9c8 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -260,6 +260,12 @@ static int __init xen_guest_init(void)
         xen_domain_type = XEN_HVM_DOMAIN;
 
         xen_setup_features();
+
+        if (!xen_feature(XENFEAT_grant_map_identity)) {
+                pr_warn("Please upgrade your Xen.\n"
+                                "If your platform has any non-coherent DMA devices, they won't work properly.\n");
+        }
+
         if (xen_feature(XENFEAT_dom0))
                 xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
         else
diff --git a/arch/arm/xen/mm32.c b/arch/arm/xen/mm32.c
new file mode 100644
index 000000000000..3b99860fd7ae
--- /dev/null
+++ b/arch/arm/xen/mm32.c
@@ -0,0 +1,202 @@
+#include <linux/cpu.h>
+#include <linux/dma-mapping.h>
+#include <linux/gfp.h>
+#include <linux/highmem.h>
+
+#include <xen/features.h>
+
+static DEFINE_PER_CPU(unsigned long, xen_mm32_scratch_virt);
+static DEFINE_PER_CPU(pte_t *, xen_mm32_scratch_ptep);
+
+static int alloc_xen_mm32_scratch_page(int cpu)
+{
+        struct page *page;
+        unsigned long virt;
+        pmd_t *pmdp;
+        pte_t *ptep;
+
+        if (per_cpu(xen_mm32_scratch_ptep, cpu) != NULL)
+                return 0;
+
+        page = alloc_page(GFP_KERNEL);
+        if (page == NULL) {
+                pr_warn("Failed to allocate xen_mm32_scratch_page for cpu %d\n", cpu);
+                return -ENOMEM;
+        }
+
+        virt = (unsigned long)__va(page_to_phys(page));
+        pmdp = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
+        ptep = pte_offset_kernel(pmdp, virt);
+
+        per_cpu(xen_mm32_scratch_virt, cpu) = virt;
+        per_cpu(xen_mm32_scratch_ptep, cpu) = ptep;
+
+        return 0;
+}
+
+static int xen_mm32_cpu_notify(struct notifier_block *self,
+                                    unsigned long action, void *hcpu)
+{
+        int cpu = (long)hcpu;
+        switch (action) {
+        case CPU_UP_PREPARE:
+                if (alloc_xen_mm32_scratch_page(cpu))
+                        return NOTIFY_BAD;
+                break;
+        default:
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block xen_mm32_cpu_notifier = {
+        .notifier_call  = xen_mm32_cpu_notify,
+};
+
+static void* xen_mm32_remap_page(dma_addr_t handle)
+{
+        unsigned long virt = get_cpu_var(xen_mm32_scratch_virt);
+        pte_t *ptep = __get_cpu_var(xen_mm32_scratch_ptep);
+
+        *ptep = pfn_pte(handle >> PAGE_SHIFT, PAGE_KERNEL);
+        local_flush_tlb_kernel_page(virt);
+
+        return (void*)virt;
+}
+
+static void xen_mm32_unmap(void *vaddr)
+{
+        put_cpu_var(xen_mm32_scratch_virt);
+}
+
+
+/* functions called by SWIOTLB */
+
+static void dma_cache_maint(dma_addr_t handle, unsigned long offset,
+        size_t size, enum dma_data_direction dir,
+        void (*op)(const void *, size_t, int))
+{
+        unsigned long pfn;
+        size_t left = size;
+
+        pfn = (handle >> PAGE_SHIFT) + offset / PAGE_SIZE;
+        offset %= PAGE_SIZE;
+
+        do {
+                size_t len = left;
+                void *vaddr;
+        
+                if (!pfn_valid(pfn))
+                {
+                        /* Cannot map the page, we don't know its physical address.
+                         * Return and hope for the best */
+                        if (!xen_feature(XENFEAT_grant_map_identity))
+                                return;
+                        vaddr = xen_mm32_remap_page(handle) + offset;
+                        op(vaddr, len, dir);
+                        xen_mm32_unmap(vaddr - offset);
+                } else {
+                        struct page *page = pfn_to_page(pfn);
+
+                        if (PageHighMem(page)) {
+                                if (len + offset > PAGE_SIZE)
+                                        len = PAGE_SIZE - offset;
+
+                                if (cache_is_vipt_nonaliasing()) {
+                                        vaddr = kmap_atomic(page);
+                                        op(vaddr + offset, len, dir);
+                                        kunmap_atomic(vaddr);
+                                } else {
+                                        vaddr = kmap_high_get(page);
+                                        if (vaddr) {
+                                                op(vaddr + offset, len, dir);
+                                                kunmap_high(page);
+                                        }
+                                }
+                        } else {
+                                vaddr = page_address(page) + offset;
+                                op(vaddr, len, dir);
+                        }
+                }
+
+                offset = 0;
+                pfn++;
+                left -= len;
+        } while (left);
+}
+
+static void __xen_dma_page_dev_to_cpu(struct device *hwdev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir)
+{
+        /* Cannot use __dma_page_dev_to_cpu because we don't have a
+         * struct page for handle */
+
+        if (dir != DMA_TO_DEVICE)
+                outer_inv_range(handle, handle + size);
+
+        dma_cache_maint(handle & PAGE_MASK, handle & ~PAGE_MASK, size, dir, dmac_unmap_area);
+}
+
+static void __xen_dma_page_cpu_to_dev(struct device *hwdev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir)
+{
+
+        dma_cache_maint(handle & PAGE_MASK, handle & ~PAGE_MASK, size, dir, dmac_map_area);
+
+        if (dir == DMA_FROM_DEVICE) {
+                outer_inv_range(handle, handle + size);
+        } else {
+                outer_clean_range(handle, handle + size);
+        }
+}
+
+void xen_dma_unmap_page(struct device *hwdev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir,
+                struct dma_attrs *attrs)
+
+{
+        if (!__generic_dma_ops(hwdev)->unmap_page)
+                return;
+        if (dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+                return;
+
+        __xen_dma_page_dev_to_cpu(hwdev, handle, size, dir);
+}
+
+void xen_dma_sync_single_for_cpu(struct device *hwdev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir)
+{
+        if (!__generic_dma_ops(hwdev)->sync_single_for_cpu)
+                return;
+        __xen_dma_page_dev_to_cpu(hwdev, handle, size, dir);
+}
+
+void xen_dma_sync_single_for_device(struct device *hwdev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir)
+{
+        if (!__generic_dma_ops(hwdev)->sync_single_for_device)
+                return;
+        __xen_dma_page_cpu_to_dev(hwdev, handle, size, dir);
+}
+
+int __init xen_mm32_init(void)
+{
+        int cpu;
+
+        if (!xen_initial_domain())
+                return 0;
+
+        register_cpu_notifier(&xen_mm32_cpu_notifier);
+        get_online_cpus();
+        for_each_online_cpu(cpu) {
+                if (alloc_xen_mm32_scratch_page(cpu)) {
+                        put_online_cpus();
+                        unregister_cpu_notifier(&xen_mm32_cpu_notifier);
+                        return -ENOMEM;
+                }
+        }
+        put_online_cpus();
+
+        return 0;
+}
+arch_initcall(xen_mm32_init);
diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c
index 97baf4427817..054857776254 100644
--- a/arch/arm/xen/p2m.c
+++ b/arch/arm/xen/p2m.c
@@ -21,14 +21,12 @@ struct xen_p2m_entry {
         unsigned long pfn;
         unsigned long mfn;
         unsigned long nr_pages;
-        struct rb_node rbnode_mach;
         struct rb_node rbnode_phys;
 };
 
 static rwlock_t p2m_lock;
 struct rb_root phys_to_mach = RB_ROOT;
 EXPORT_SYMBOL_GPL(phys_to_mach);
-static struct rb_root mach_to_phys = RB_ROOT;
 
 static int xen_add_phys_to_mach_entry(struct xen_p2m_entry *new)
 {
@@ -41,8 +39,6 @@ static int xen_add_phys_to_mach_entry(struct xen_p2m_entry *new)
                 parent = *link;
                 entry = rb_entry(parent, struct xen_p2m_entry, rbnode_phys);
 
-                if (new->mfn == entry->mfn)
-                        goto err_out;
                 if (new->pfn == entry->pfn)
                         goto err_out;
 
@@ -88,64 +84,6 @@ unsigned long __pfn_to_mfn(unsigned long pfn)
 }
 EXPORT_SYMBOL_GPL(__pfn_to_mfn);
 
-static int xen_add_mach_to_phys_entry(struct xen_p2m_entry *new)
-{
-        struct rb_node **link = &mach_to_phys.rb_node;
-        struct rb_node *parent = NULL;
-        struct xen_p2m_entry *entry;
-        int rc = 0;
-
-        while (*link) {
-                parent = *link;
-                entry = rb_entry(parent, struct xen_p2m_entry, rbnode_mach);
-
-                if (new->mfn == entry->mfn)
-                        goto err_out;
-                if (new->pfn == entry->pfn)
-                        goto err_out;
-
-                if (new->mfn < entry->mfn)
-                        link = &(*link)->rb_left;
-                else
-                        link = &(*link)->rb_right;
-        }
-        rb_link_node(&new->rbnode_mach, parent, link);
-        rb_insert_color(&new->rbnode_mach, &mach_to_phys);
-        goto out;
-
-err_out:
-        rc = -EINVAL;
-        pr_warn("%s: cannot add pfn=%pa -> mfn=%pa: pfn=%pa -> mfn=%pa already exists\n",
-                        __func__, &new->pfn, &new->mfn, &entry->pfn, &entry->mfn);
-out:
-        return rc;
-}
-
-unsigned long __mfn_to_pfn(unsigned long mfn)
-{
-        struct rb_node *n = mach_to_phys.rb_node;
-        struct xen_p2m_entry *entry;
-        unsigned long irqflags;
-
-        read_lock_irqsave(&p2m_lock, irqflags);
-        while (n) {
-                entry = rb_entry(n, struct xen_p2m_entry, rbnode_mach);
-                if (entry->mfn <= mfn &&
-                                entry->mfn + entry->nr_pages > mfn) {
-                        read_unlock_irqrestore(&p2m_lock, irqflags);
-                        return entry->pfn + (mfn - entry->mfn);
-                }
-                if (mfn < entry->mfn)
-                        n = n->rb_left;
-                else
-                        n = n->rb_right;
-        }
-        read_unlock_irqrestore(&p2m_lock, irqflags);
-
-        return INVALID_P2M_ENTRY;
-}
-EXPORT_SYMBOL_GPL(__mfn_to_pfn);
-
 int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
                             struct gnttab_map_grant_ref *kmap_ops,
                             struct page **pages, unsigned int count)
@@ -192,7 +130,6 @@ bool __set_phys_to_machine_multi(unsigned long pfn,
                         p2m_entry = rb_entry(n, struct xen_p2m_entry, rbnode_phys);
                         if (p2m_entry->pfn <= pfn &&
                                         p2m_entry->pfn + p2m_entry->nr_pages > pfn) {
-                                rb_erase(&p2m_entry->rbnode_mach, &mach_to_phys);
                                 rb_erase(&p2m_entry->rbnode_phys, &phys_to_mach);
                                 write_unlock_irqrestore(&p2m_lock, irqflags);
                                 kfree(p2m_entry);
@@ -217,8 +154,7 @@ bool __set_phys_to_machine_multi(unsigned long pfn,
         p2m_entry->mfn = mfn;
 
         write_lock_irqsave(&p2m_lock, irqflags);
-        if ((rc = xen_add_phys_to_mach_entry(p2m_entry) < 0) ||
-                (rc = xen_add_mach_to_phys_entry(p2m_entry) < 0)) {
+        if ((rc = xen_add_phys_to_mach_entry(p2m_entry)) < 0) {
                 write_unlock_irqrestore(&p2m_lock, irqflags);
                 return false;
         }
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index fd4e81a4e1ce..c49ca4c738bb 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -18,6 +18,7 @@ config ARM64
         select COMMON_CLK
         select CPU_PM if (SUSPEND || CPU_IDLE)
         select DCACHE_WORD_ACCESS
+        select GENERIC_ALLOCATOR
         select GENERIC_CLOCKEVENTS
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
         select GENERIC_CPU_AUTOPROBE
@@ -30,11 +31,13 @@ config ARM64
         select GENERIC_STRNCPY_FROM_USER
         select GENERIC_STRNLEN_USER
         select GENERIC_TIME_VSYSCALL
+        select HANDLE_DOMAIN_IRQ
         select HARDIRQS_SW_RESEND
         select HAVE_ARCH_AUDITSYSCALL
         select HAVE_ARCH_JUMP_LABEL
         select HAVE_ARCH_KGDB
         select HAVE_ARCH_TRACEHOOK
+        select HAVE_BPF_JIT
         select HAVE_C_RECORDMCOUNT
         select HAVE_CC_STACKPROTECTOR
         select HAVE_DEBUG_BUGVERBOSE
@@ -54,6 +57,7 @@ config ARM64
         select HAVE_PERF_EVENTS
         select HAVE_PERF_REGS
         select HAVE_PERF_USER_STACK_DUMP
+        select HAVE_RCU_TABLE_FREE
         select HAVE_SYSCALL_TRACEPOINTS
         select IRQ_DOMAIN
         select MODULES_USE_ELF_RELA
@@ -81,7 +85,7 @@ config MMU
         def_bool y
 
 config NO_IOPORT_MAP
-        def_bool y
+        def_bool y if !PCI
 
 config STACKTRACE_SUPPORT
         def_bool y
@@ -107,6 +111,9 @@ config GENERIC_CALIBRATE_DELAY
 config ZONE_DMA
         def_bool y
 
+config HAVE_GENERIC_RCU_GUP
+        def_bool y
+
 config ARCH_DMA_ADDR_T_64BIT
         def_bool y
 
@@ -134,6 +141,11 @@ source "kernel/Kconfig.freezer"
 
 menu "Platform selection"
 
+config ARCH_THUNDER
+        bool "Cavium Inc. Thunder SoC Family"
+        help
+          This enables support for Cavium's Thunder Family of SoCs.
+
 config ARCH_VEXPRESS
         bool "ARMv8 software model (Versatile Express)"
         select ARCH_REQUIRE_GPIOLIB
@@ -156,6 +168,26 @@ menu "Bus support"
 config ARM_AMBA
         bool
 
+config PCI
+        bool "PCI support"
+        help
+          This feature enables support for PCI bus system. If you say Y
+          here, the kernel will include drivers and infrastructure code
+          to support PCI bus devices.
+
+config PCI_DOMAINS
+        def_bool PCI
+
+config PCI_DOMAINS_GENERIC
+        def_bool PCI
+
+config PCI_SYSCALL
+        def_bool PCI
+
+source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
+source "drivers/pci/hotplug/Kconfig"
+
 endmenu
 
 menu "Kernel Features"
@@ -252,11 +284,11 @@ config SCHED_SMT
           places. If unsure say N here.
 
 config NR_CPUS
-        int "Maximum number of CPUs (2-32)"
-        range 2 32
+        int "Maximum number of CPUs (2-64)"
+        range 2 64
         depends on SMP
         # These have to remain sorted largest to smallest
-        default "8"
+        default "64"
 
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
index 4ee8e90b7a45..0a12933e50ed 100644
--- a/arch/arm64/Kconfig.debug
+++ b/arch/arm64/Kconfig.debug
@@ -43,4 +43,15 @@ config ARM64_RANDOMIZE_TEXT_OFFSET
           of TEXT_OFFSET and platforms must not require a specific
           value.
 
+config DEBUG_SET_MODULE_RONX
+        bool "Set loadable kernel module data as NX and text as RO"
+        depends on MODULES
+        help
+          This option helps catch unintended modifications to loadable
+          kernel module's text and read-only data. It also prevents execution
+          of module data. Such protection may interfere with run-time code
+          patching and dynamic kernel tracing - and they might also protect
+          against certain classes of kernel exploits.
+          If in doubt, say "N".
+
 endmenu
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 57833546bf00..59c86b6b3052 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -39,7 +39,7 @@ head-y		:= arch/arm64/kernel/head.o
 
 # The byte offset of the kernel image in RAM from the start of RAM.
 ifeq ($(CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET), y)
-TEXT_OFFSET := $(shell awk 'BEGIN {srand(); printf "0x%04x0\n", int(65535 * rand())}')
+TEXT_OFFSET := $(shell awk 'BEGIN {srand(); printf "0x%03x000\n", int(512 * rand())}')
 else
 TEXT_OFFSET := 0x00080000
 endif
@@ -47,6 +47,7 @@ endif
 export  TEXT_OFFSET GZFLAGS
 
 core-y          += arch/arm64/kernel/ arch/arm64/mm/
+core-$(CONFIG_NET) += arch/arm64/net/
 core-$(CONFIG_KVM) += arch/arm64/kvm/
 core-$(CONFIG_XEN) += arch/arm64/xen/
 core-$(CONFIG_CRYPTO) += arch/arm64/crypto/
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb051f66..f8001a62029c 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
 dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
 
diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts
index b2f56229aa5e..f64900052f4e 100644
--- a/arch/arm64/boot/dts/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm-mustang.dts
@@ -25,6 +25,14 @@
         };
 };
 
+&pcie0clk {
+        status = "ok";
+};
+
+&pcie0 {
+        status = "ok";
+};
+
 &serial0 {
         status = "ok";
 };
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index c0aceef7f5b3..4f6d04d52cca 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -269,6 +269,184 @@
                                 enable-mask = <0x2>;
                                 clock-output-names = "rtcclk";
                         };
+
+                        rngpkaclk: rngpkaclk@17000000 {
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x17000000 0x0 0x2000>;
+                                reg-names = "csr-reg";
+                                csr-offset = <0xc>;
+                                csr-mask = <0x10>;
+                                enable-offset = <0x10>;
+                                enable-mask = <0x10>;
+                                clock-output-names = "rngpkaclk";
+                        };
+
+                        pcie0clk: pcie0clk@1f2bc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2bc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie0clk";
+                        };
+
+                        pcie1clk: pcie1clk@1f2cc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2cc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie1clk";
+                        };
+
+                        pcie2clk: pcie2clk@1f2dc000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f2dc000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie2clk";
+                        };
+
+                        pcie3clk: pcie3clk@1f50c000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f50c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie3clk";
+                        };
+
+                        pcie4clk: pcie4clk@1f51c000 {
+                                status = "disabled";
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f51c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "pcie4clk";
+                        };
+                };
+
+                pcie0: pcie@1f2b0000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
+                                0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
+                                  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie0clk 0>;
+                };
+
+                pcie1: pcie@1f2c0000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
+                                0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
+                                  0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie1clk 0>;
+                };
+
+                pcie2: pcie@1f2d0000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
+                                 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000   /* io  */
+                                  0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie2clk 0>;
+                };
+
+                pcie3: pcie@1f500000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
+                                0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000   /* io   */
+                                  0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem  */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie3clk 0>;
+                };
+
+                pcie4: pcie@1f510000 {
+                        status = "disabled";
+                        device_type = "pci";
+                        compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
+                                0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
+                        reg-names = "csr", "cfg";
+                        ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000   /* io  */
+                                  0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
+                        dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
+                                         0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
+                                         0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
+                                         0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
+                        dma-coherent;
+                        clocks = <&pcie4clk 0>;
                 };
 
                 serial0: serial@1c020000 {
@@ -421,5 +599,13 @@
 
                         };
                 };
+
+                rng: rng@10520000 {
+                        compatible = "apm,xgene-rng";
+                        reg = <0x0 0x10520000 0x0 0x100>;
+                        interrupts = <0x0 0x41 0x4>;
+                        clocks = <&rngpkaclk 0>;
+                };
+
         };
 };
diff --git a/arch/arm64/boot/dts/thunder-88xx.dts b/arch/arm64/boot/dts/thunder-88xx.dts
new file mode 100644
index 000000000000..800ba65991f7
--- /dev/null
+++ b/arch/arm64/boot/dts/thunder-88xx.dts
@@ -0,0 +1,67 @@
+/*
+ * Cavium Thunder DTS file - Thunder board description
+ *
+ * Copyright (C) 2014, Cavium Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/include/ "thunder-88xx.dtsi"
+
+/ {
+        model = "Cavium ThunderX CN88XX board";
+        compatible = "cavium,thunder-88xx";
+
+        aliases {
+                serial0 = &uaa0;
+                serial1 = &uaa1;
+        };
+
+        memory@00000000 {
+                device_type = "memory";
+                reg = <0x0 0x00000000 0x0 0x80000000>;
+        };
+};
diff --git a/arch/arm64/boot/dts/thunder-88xx.dtsi b/arch/arm64/boot/dts/thunder-88xx.dtsi
new file mode 100644
index 000000000000..d8c0bdc51882
--- /dev/null
+++ b/arch/arm64/boot/dts/thunder-88xx.dtsi
@@ -0,0 +1,401 @@
+/*
+ * Cavium Thunder DTS file - Thunder SoC description
+ *
+ * Copyright (C) 2014, Cavium Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+        compatible = "cavium,thunder-88xx";
+        interrupt-parent = <&gic0>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        psci {
+                compatible = "arm,psci-0.2";
+                method = "smc";
+        };
+
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                cpu@000 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x000>;
+                        enable-method = "psci";
+                };
+                cpu@001 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x001>;
+                        enable-method = "psci";
+                };
+                cpu@002 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x002>;
+                        enable-method = "psci";
+                };
+                cpu@003 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x003>;
+                        enable-method = "psci";
+                };
+                cpu@004 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x004>;
+                        enable-method = "psci";
+                };
+                cpu@005 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x005>;
+                        enable-method = "psci";
+                };
+                cpu@006 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x006>;
+                        enable-method = "psci";
+                };
+                cpu@007 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x007>;
+                        enable-method = "psci";
+                };
+                cpu@008 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x008>;
+                        enable-method = "psci";
+                };
+                cpu@009 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x009>;
+                        enable-method = "psci";
+                };
+                cpu@00a {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x00a>;
+                        enable-method = "psci";
+                };
+                cpu@00b {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x00b>;
+                        enable-method = "psci";
+                };
+                cpu@00c {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x00c>;
+                        enable-method = "psci";
+                };
+                cpu@00d {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x00d>;
+                        enable-method = "psci";
+                };
+                cpu@00e {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x00e>;
+                        enable-method = "psci";
+                };
+                cpu@00f {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x00f>;
+                        enable-method = "psci";
+                };
+                cpu@100 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x100>;
+                        enable-method = "psci";
+                };
+                cpu@101 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x101>;
+                        enable-method = "psci";
+                };
+                cpu@102 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x102>;
+                        enable-method = "psci";
+                };
+                cpu@103 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x103>;
+                        enable-method = "psci";
+                };
+                cpu@104 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x104>;
+                        enable-method = "psci";
+                };
+                cpu@105 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x105>;
+                        enable-method = "psci";
+                };
+                cpu@106 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x106>;
+                        enable-method = "psci";
+                };
+                cpu@107 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x107>;
+                        enable-method = "psci";
+                };
+                cpu@108 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x108>;
+                        enable-method = "psci";
+                };
+                cpu@109 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x109>;
+                        enable-method = "psci";
+                };
+                cpu@10a {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x10a>;
+                        enable-method = "psci";
+                };
+                cpu@10b {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x10b>;
+                        enable-method = "psci";
+                };
+                cpu@10c {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x10c>;
+                        enable-method = "psci";
+                };
+                cpu@10d {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x10d>;
+                        enable-method = "psci";
+                };
+                cpu@10e {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x10e>;
+                        enable-method = "psci";
+                };
+                cpu@10f {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x10f>;
+                        enable-method = "psci";
+                };
+                cpu@200 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x200>;
+                        enable-method = "psci";
+                };
+                cpu@201 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x201>;
+                        enable-method = "psci";
+                };
+                cpu@202 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x202>;
+                        enable-method = "psci";
+                };
+                cpu@203 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x203>;
+                        enable-method = "psci";
+                };
+                cpu@204 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x204>;
+                        enable-method = "psci";
+                };
+                cpu@205 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x205>;
+                        enable-method = "psci";
+                };
+                cpu@206 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x206>;
+                        enable-method = "psci";
+                };
+                cpu@207 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x207>;
+                        enable-method = "psci";
+                };
+                cpu@208 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x208>;
+                        enable-method = "psci";
+                };
+                cpu@209 {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x209>;
+                        enable-method = "psci";
+                };
+                cpu@20a {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x20a>;
+                        enable-method = "psci";
+                };
+                cpu@20b {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x20b>;
+                        enable-method = "psci";
+                };
+                cpu@20c {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x20c>;
+                        enable-method = "psci";
+                };
+                cpu@20d {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x20d>;
+                        enable-method = "psci";
+                };
+                cpu@20e {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x20e>;
+                        enable-method = "psci";
+                };
+                cpu@20f {
+                        device_type = "cpu";
+                        compatible = "cavium,thunder", "arm,armv8";
+                        reg = <0x0 0x20f>;
+                        enable-method = "psci";
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <1 13 0xff01>,
+                             <1 14 0xff01>,
+                             <1 11 0xff01>,
+                             <1 10 0xff01>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                refclk50mhz: refclk50mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                        clock-output-names = "refclk50mhz";
+                };
+
+                gic0: interrupt-controller@8010,00000000 {
+                        compatible = "arm,gic-v3";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
+                              <0x8010 0x80000000 0x0 0x600000>; /* GICR */
+                        interrupts = <1 9 0xf04>;
+                };
+
+                uaa0: serial@87e0,24000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x87e0 0x24000000 0x0 0x1000>;
+                        interrupts = <1 21 4>;
+                        clocks = <&refclk50mhz>;
+                        clock-names = "apb_pclk";
+                };
+
+                uaa1: serial@87e0,25000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x87e0 0x25000000 0x0 0x1000>;
+                        interrupts = <1 22 4>;
+                        clocks = <&refclk50mhz>;
+                        clock-names = "apb_pclk";
+                };
+        };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 1e52b741d806..9cd37de9aa8d 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -32,6 +32,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_THUNDER=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_XGENE=y
 CONFIG_SMP=y
@@ -64,6 +65,8 @@ CONFIG_VIRTIO_BLK=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
+CONFIG_AHCI_XGENE=y
+CONFIG_PHY_XGENE=y
 CONFIG_PATA_PLATFORM=y
 CONFIG_PATA_OF_PLATFORM=y
 CONFIG_NETDEVICES=y
@@ -71,6 +74,7 @@ CONFIG_TUN=y
 CONFIG_VIRTIO_NET=y
 CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
+CONFIG_NET_XGENE=y
 # CONFIG_WLAN is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_SERPORT is not set
diff --git a/arch/arm64/crypto/sha2-ce-glue.c b/arch/arm64/crypto/sha2-ce-glue.c
index c294e67d3925..ae67e88c28b9 100644
--- a/arch/arm64/crypto/sha2-ce-glue.c
+++ b/arch/arm64/crypto/sha2-ce-glue.c
@@ -150,7 +150,6 @@ static void sha2_finup(struct shash_desc *desc, const u8 *data,
         kernel_neon_begin_partial(28);
         sha2_ce_transform(blocks, data, sctx->state, NULL, len);
         kernel_neon_end();
-        data += blocks * SHA256_BLOCK_SIZE;
 }
 
 static int sha224_finup(struct shash_desc *desc, const u8 *data,
diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index 0b3fcf86e6ba..774a7c85e70f 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -9,8 +9,8 @@ generic-y += current.h
 generic-y += delay.h
 generic-y += div64.h
 generic-y += dma.h
-generic-y += emergency-restart.h
 generic-y += early_ioremap.h
+generic-y += emergency-restart.h
 generic-y += errno.h
 generic-y += ftrace.h
 generic-y += hash.h
@@ -29,6 +29,7 @@ generic-y += mman.h
 generic-y += msgbuf.h
 generic-y += mutex.h
 generic-y += pci.h
+generic-y += pci-bridge.h
 generic-y += poll.h
 generic-y += preempt.h
 generic-y += resource.h
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index 9400596a0f39..f19097134b02 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -104,37 +104,6 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl)
         asm volatile("msr       cntkctl_el1, %0" : : "r" (cntkctl));
 }
 
-static inline void arch_counter_set_user_access(void)
-{
-        u32 cntkctl = arch_timer_get_cntkctl();
-
-        /* Disable user access to the timers and the physical counter */
-        /* Also disable virtual event stream */
-        cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
-                        | ARCH_TIMER_USR_VT_ACCESS_EN
-                        | ARCH_TIMER_VIRT_EVT_EN
-                        | ARCH_TIMER_USR_PCT_ACCESS_EN);
-
-        /* Enable user access to the virtual counter */
-        cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
-
-        arch_timer_set_cntkctl(cntkctl);
-}
-
-static inline void arch_timer_evtstrm_enable(int divider)
-{
-        u32 cntkctl = arch_timer_get_cntkctl();
-        cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
-        /* Set the divider and enable virtual event stream */
-        cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
-                        | ARCH_TIMER_VIRT_EVT_EN;
-        arch_timer_set_cntkctl(cntkctl);
-        elf_hwcap |= HWCAP_EVTSTRM;
-#ifdef CONFIG_COMPAT
-        compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
-#endif
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
         u64 cval;
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index f2defe1c380c..689b6379188c 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -148,4 +148,8 @@ static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
 {
 }
 
+int set_memory_ro(unsigned long addr, int numpages);
+int set_memory_rw(unsigned long addr, int numpages);
+int set_memory_x(unsigned long addr, int numpages);
+int set_memory_nx(unsigned long addr, int numpages);
 #endif
diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h
index 7a2e0762cb40..4c631a0a3609 100644
--- a/arch/arm64/include/asm/cachetype.h
+++ b/arch/arm64/include/asm/cachetype.h
@@ -39,6 +39,26 @@
 
 extern unsigned long __icache_flags;
 
+#define CCSIDR_EL1_LINESIZE_MASK        0x7
+#define CCSIDR_EL1_LINESIZE(x)          ((x) & CCSIDR_EL1_LINESIZE_MASK)
+
+#define CCSIDR_EL1_NUMSETS_SHIFT        13
+#define CCSIDR_EL1_NUMSETS_MASK         (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT)
+#define CCSIDR_EL1_NUMSETS(x) \
+        (((x) & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT)
+
+extern u64 __attribute_const__ icache_get_ccsidr(void);
+
+static inline int icache_get_linesize(void)
+{
+        return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr());
+}
+
+static inline int icache_get_numsets(void)
+{
+        return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr());
+}
+
 /*
  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
  * permitted in the I-cache.
diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index d7b4b38a8e86..6f8e2ef9094a 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -28,6 +28,8 @@ struct device_node;
  *              enable-method property.
  * @cpu_init:   Reads any data necessary for a specific enable-method from the
  *              devicetree, for a given cpu node and proposed logical id.
+ * @cpu_init_idle: Reads any data necessary to initialize CPU idle states from
+ *              devicetree, for a given cpu node and proposed logical id.
  * @cpu_prepare: Early one-time preparation step for a cpu. If there is a
  *              mechanism for doing so, tests whether it is possible to boot
  *              the given CPU.
@@ -47,6 +49,7 @@ struct device_node;
 struct cpu_operations {
         const char      *name;
         int             (*cpu_init)(struct device_node *, unsigned int);
+        int             (*cpu_init_idle)(struct device_node *, unsigned int);
         int             (*cpu_prepare)(unsigned int);
         int             (*cpu_boot)(unsigned int);
         void            (*cpu_postboot)(void);
@@ -61,7 +64,7 @@ struct cpu_operations {
 };
 
 extern const struct cpu_operations *cpu_ops[NR_CPUS];
-extern int __init cpu_read_ops(struct device_node *dn, int cpu);
-extern void __init cpu_read_bootcpu_ops(void);
+int __init cpu_read_ops(struct device_node *dn, int cpu);
+void __init cpu_read_bootcpu_ops(void);
 
 #endif /* ifndef __ASM_CPU_OPS_H */
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
new file mode 100644
index 000000000000..b52a9932e2b1
--- /dev/null
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_CPUIDLE_H
+#define __ASM_CPUIDLE_H
+
+#ifdef CONFIG_CPU_IDLE
+extern int cpu_init_idle(unsigned int cpu);
+#else
+static inline int cpu_init_idle(unsigned int cpu)
+{
+        return -EOPNOTSUPP;
+}
+#endif
+
+#endif
diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h
index 7fb343779498..40ec68aa6870 100644
--- a/arch/arm64/include/asm/debug-monitors.h
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -48,11 +48,13 @@
 /*
  * #imm16 values used for BRK instruction generation
  * Allowed values for kgbd are 0x400 - 0x7ff
+ * 0x100: for triggering a fault on purpose (reserved)
  * 0x400: for dynamic BRK instruction
  * 0x401: for compile time BRK instruction
  */
-#define KGDB_DYN_DGB_BRK_IMM            0x400
-#define KDBG_COMPILED_DBG_BRK_IMM       0x401
+#define FAULT_BRK_IMM                   0x100
+#define KGDB_DYN_DBG_BRK_IMM            0x400
+#define KGDB_COMPILED_DBG_BRK_IMM       0x401
 
 /*
  * BRK instruction encoding
@@ -61,24 +63,30 @@
 #define AARCH64_BREAK_MON       0xd4200000
 
 /*
+ * BRK instruction for provoking a fault on purpose
+ * Unlike kgdb, #imm16 value with unallocated handler is used for faulting.
+ */
+#define AARCH64_BREAK_FAULT     (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5))
+
+/*
  * Extract byte from BRK instruction
  */
-#define KGDB_DYN_DGB_BRK_INS_BYTE(x) \
+#define KGDB_DYN_DBG_BRK_INS_BYTE(x) \
         ((((AARCH64_BREAK_MON) & 0xffe0001f) >> (x * 8)) & 0xff)
 
 /*
  * Extract byte from BRK #imm16
  */
-#define KGBD_DYN_DGB_BRK_IMM_BYTE(x) \
-        (((((KGDB_DYN_DGB_BRK_IMM) & 0xffff) << 5) >> (x * 8)) & 0xff)
+#define KGBD_DYN_DBG_BRK_IMM_BYTE(x) \
+        (((((KGDB_DYN_DBG_BRK_IMM) & 0xffff) << 5) >> (x * 8)) & 0xff)
 
-#define KGDB_DYN_DGB_BRK_BYTE(x) \
-        (KGDB_DYN_DGB_BRK_INS_BYTE(x) | KGBD_DYN_DGB_BRK_IMM_BYTE(x))
+#define KGDB_DYN_DBG_BRK_BYTE(x) \
+        (KGDB_DYN_DBG_BRK_INS_BYTE(x) | KGBD_DYN_DBG_BRK_IMM_BYTE(x))
 
-#define  KGDB_DYN_BRK_INS_BYTE0  KGDB_DYN_DGB_BRK_BYTE(0)
-#define  KGDB_DYN_BRK_INS_BYTE1  KGDB_DYN_DGB_BRK_BYTE(1)
-#define  KGDB_DYN_BRK_INS_BYTE2  KGDB_DYN_DGB_BRK_BYTE(2)
-#define  KGDB_DYN_BRK_INS_BYTE3  KGDB_DYN_DGB_BRK_BYTE(3)
+#define  KGDB_DYN_BRK_INS_BYTE0  KGDB_DYN_DBG_BRK_BYTE(0)
+#define  KGDB_DYN_BRK_INS_BYTE1  KGDB_DYN_DBG_BRK_BYTE(1)
+#define  KGDB_DYN_BRK_INS_BYTE2  KGDB_DYN_DBG_BRK_BYTE(2)
+#define  KGDB_DYN_BRK_INS_BYTE3  KGDB_DYN_DBG_BRK_BYTE(3)
 
 #define CACHE_FLUSH_IS_SAFE             1
 
diff --git a/arch/arm64/include/asm/dma-mapping.h b/arch/arm64/include/asm/dma-mapping.h
index dc82e52acdb3..adeae3f6f0fc 100644
--- a/arch/arm64/include/asm/dma-mapping.h
+++ b/arch/arm64/include/asm/dma-mapping.h
@@ -52,6 +52,13 @@ static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
         dev->archdata.dma_ops = ops;
 }
 
+static inline int set_arch_dma_coherent_ops(struct device *dev)
+{
+        set_dma_ops(dev, &coherent_swiotlb_dma_ops);
+        return 0;
+}
+#define set_arch_dma_coherent_ops       set_arch_dma_coherent_ops
+
 #include <asm-generic/dma-mapping-common.h>
 
 static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h
index 0be67821f9ce..e8a3268a891c 100644
--- a/arch/arm64/include/asm/hardirq.h
+++ b/arch/arm64/include/asm/hardirq.h
@@ -47,8 +47,6 @@ static inline void ack_bad_irq(unsigned int irq)
         irq_err_count++;
 }
 
-extern void handle_IRQ(unsigned int, struct pt_regs *);
-
 /*
  * No arch-specific IRQ flags.
  */
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index d064047612b1..52b484b6aa1a 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -79,7 +79,6 @@ static inline void decode_ctrl_reg(u32 reg,
  */
 #define ARM_MAX_BRP             16
 #define ARM_MAX_WRP             16
-#define ARM_MAX_HBP_SLOTS       (ARM_MAX_BRP + ARM_MAX_WRP)
 
 /* Virtual debug register bases. */
 #define AARCH64_DBG_REG_BVR     0
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index dc1f73b13e74..56a9e63b6c33 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -2,6 +2,8 @@
  * Copyright (C) 2013 Huawei Ltd.
  * Author: Jiang Liu <liuj97@gmail.com>
  *
+ * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -64,12 +66,155 @@ enum aarch64_insn_imm_type {
         AARCH64_INSN_IMM_14,
         AARCH64_INSN_IMM_12,
         AARCH64_INSN_IMM_9,
+        AARCH64_INSN_IMM_7,
+        AARCH64_INSN_IMM_6,
+        AARCH64_INSN_IMM_S,
+        AARCH64_INSN_IMM_R,
         AARCH64_INSN_IMM_MAX
 };
 
+enum aarch64_insn_register_type {
+        AARCH64_INSN_REGTYPE_RT,
+        AARCH64_INSN_REGTYPE_RN,
+        AARCH64_INSN_REGTYPE_RT2,
+        AARCH64_INSN_REGTYPE_RM,
+        AARCH64_INSN_REGTYPE_RD,
+        AARCH64_INSN_REGTYPE_RA,
+};
+
+enum aarch64_insn_register {
+        AARCH64_INSN_REG_0  = 0,
+        AARCH64_INSN_REG_1  = 1,
+        AARCH64_INSN_REG_2  = 2,
+        AARCH64_INSN_REG_3  = 3,
+        AARCH64_INSN_REG_4  = 4,
+        AARCH64_INSN_REG_5  = 5,
+        AARCH64_INSN_REG_6  = 6,
+        AARCH64_INSN_REG_7  = 7,
+        AARCH64_INSN_REG_8  = 8,
+        AARCH64_INSN_REG_9  = 9,
+        AARCH64_INSN_REG_10 = 10,
+        AARCH64_INSN_REG_11 = 11,
+        AARCH64_INSN_REG_12 = 12,
+        AARCH64_INSN_REG_13 = 13,
+        AARCH64_INSN_REG_14 = 14,
+        AARCH64_INSN_REG_15 = 15,
+        AARCH64_INSN_REG_16 = 16,
+        AARCH64_INSN_REG_17 = 17,
+        AARCH64_INSN_REG_18 = 18,
+        AARCH64_INSN_REG_19 = 19,
+        AARCH64_INSN_REG_20 = 20,
+        AARCH64_INSN_REG_21 = 21,
+        AARCH64_INSN_REG_22 = 22,
+        AARCH64_INSN_REG_23 = 23,
+        AARCH64_INSN_REG_24 = 24,
+        AARCH64_INSN_REG_25 = 25,
+        AARCH64_INSN_REG_26 = 26,
+        AARCH64_INSN_REG_27 = 27,
+        AARCH64_INSN_REG_28 = 28,
+        AARCH64_INSN_REG_29 = 29,
+        AARCH64_INSN_REG_FP = 29, /* Frame pointer */
+        AARCH64_INSN_REG_30 = 30,
+        AARCH64_INSN_REG_LR = 30, /* Link register */
+        AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
+        AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
+};
+
+enum aarch64_insn_variant {
+        AARCH64_INSN_VARIANT_32BIT,
+        AARCH64_INSN_VARIANT_64BIT
+};
+
+enum aarch64_insn_condition {
+        AARCH64_INSN_COND_EQ = 0x0, /* == */
+        AARCH64_INSN_COND_NE = 0x1, /* != */
+        AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
+        AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
+        AARCH64_INSN_COND_MI = 0x4, /* < 0 */
+        AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
+        AARCH64_INSN_COND_VS = 0x6, /* overflow */
+        AARCH64_INSN_COND_VC = 0x7, /* no overflow */
+        AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
+        AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
+        AARCH64_INSN_COND_GE = 0xa, /* signed >= */
+        AARCH64_INSN_COND_LT = 0xb, /* signed < */
+        AARCH64_INSN_COND_GT = 0xc, /* signed > */
+        AARCH64_INSN_COND_LE = 0xd, /* signed <= */
+        AARCH64_INSN_COND_AL = 0xe, /* always */
+};
+
 enum aarch64_insn_branch_type {
         AARCH64_INSN_BRANCH_NOLINK,
         AARCH64_INSN_BRANCH_LINK,
+        AARCH64_INSN_BRANCH_RETURN,
+        AARCH64_INSN_BRANCH_COMP_ZERO,
+        AARCH64_INSN_BRANCH_COMP_NONZERO,
+};
+
+enum aarch64_insn_size_type {
+        AARCH64_INSN_SIZE_8,
+        AARCH64_INSN_SIZE_16,
+        AARCH64_INSN_SIZE_32,
+        AARCH64_INSN_SIZE_64,
+};
+
+enum aarch64_insn_ldst_type {
+        AARCH64_INSN_LDST_LOAD_REG_OFFSET,
+        AARCH64_INSN_LDST_STORE_REG_OFFSET,
+        AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
+        AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
+        AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
+        AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
+};
+
+enum aarch64_insn_adsb_type {
+        AARCH64_INSN_ADSB_ADD,
+        AARCH64_INSN_ADSB_SUB,
+        AARCH64_INSN_ADSB_ADD_SETFLAGS,
+        AARCH64_INSN_ADSB_SUB_SETFLAGS
+};
+
+enum aarch64_insn_movewide_type {
+        AARCH64_INSN_MOVEWIDE_ZERO,
+        AARCH64_INSN_MOVEWIDE_KEEP,
+        AARCH64_INSN_MOVEWIDE_INVERSE
+};
+
+enum aarch64_insn_bitfield_type {
+        AARCH64_INSN_BITFIELD_MOVE,
+        AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
+        AARCH64_INSN_BITFIELD_MOVE_SIGNED
+};
+
+enum aarch64_insn_data1_type {
+        AARCH64_INSN_DATA1_REVERSE_16,
+        AARCH64_INSN_DATA1_REVERSE_32,
+        AARCH64_INSN_DATA1_REVERSE_64,
+};
+
+enum aarch64_insn_data2_type {
+        AARCH64_INSN_DATA2_UDIV,
+        AARCH64_INSN_DATA2_SDIV,
+        AARCH64_INSN_DATA2_LSLV,
+        AARCH64_INSN_DATA2_LSRV,
+        AARCH64_INSN_DATA2_ASRV,
+        AARCH64_INSN_DATA2_RORV,
+};
+
+enum aarch64_insn_data3_type {
+        AARCH64_INSN_DATA3_MADD,
+        AARCH64_INSN_DATA3_MSUB,
+};
+
+enum aarch64_insn_logic_type {
+        AARCH64_INSN_LOGIC_AND,
+        AARCH64_INSN_LOGIC_BIC,
+        AARCH64_INSN_LOGIC_ORR,
+        AARCH64_INSN_LOGIC_ORN,
+        AARCH64_INSN_LOGIC_EOR,
+        AARCH64_INSN_LOGIC_EON,
+        AARCH64_INSN_LOGIC_AND_SETFLAGS,
+        AARCH64_INSN_LOGIC_BIC_SETFLAGS
 };
 
 #define __AARCH64_INSN_FUNCS(abbr, mask, val)   \
@@ -78,13 +223,58 @@ static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
 { return (val); }
 
+__AARCH64_INSN_FUNCS(str_reg,   0x3FE0EC00, 0x38206800)
+__AARCH64_INSN_FUNCS(ldr_reg,   0x3FE0EC00, 0x38606800)
+__AARCH64_INSN_FUNCS(stp_post,  0x7FC00000, 0x28800000)
+__AARCH64_INSN_FUNCS(ldp_post,  0x7FC00000, 0x28C00000)
+__AARCH64_INSN_FUNCS(stp_pre,   0x7FC00000, 0x29800000)
+__AARCH64_INSN_FUNCS(ldp_pre,   0x7FC00000, 0x29C00000)
+__AARCH64_INSN_FUNCS(add_imm,   0x7F000000, 0x11000000)
+__AARCH64_INSN_FUNCS(adds_imm,  0x7F000000, 0x31000000)
+__AARCH64_INSN_FUNCS(sub_imm,   0x7F000000, 0x51000000)
+__AARCH64_INSN_FUNCS(subs_imm,  0x7F000000, 0x71000000)
+__AARCH64_INSN_FUNCS(movn,      0x7F800000, 0x12800000)
+__AARCH64_INSN_FUNCS(sbfm,      0x7F800000, 0x13000000)
+__AARCH64_INSN_FUNCS(bfm,       0x7F800000, 0x33000000)
+__AARCH64_INSN_FUNCS(movz,      0x7F800000, 0x52800000)
+__AARCH64_INSN_FUNCS(ubfm,      0x7F800000, 0x53000000)
+__AARCH64_INSN_FUNCS(movk,      0x7F800000, 0x72800000)
+__AARCH64_INSN_FUNCS(add,       0x7F200000, 0x0B000000)
+__AARCH64_INSN_FUNCS(adds,      0x7F200000, 0x2B000000)
+__AARCH64_INSN_FUNCS(sub,       0x7F200000, 0x4B000000)
+__AARCH64_INSN_FUNCS(subs,      0x7F200000, 0x6B000000)
+__AARCH64_INSN_FUNCS(madd,      0x7FE08000, 0x1B000000)
+__AARCH64_INSN_FUNCS(msub,      0x7FE08000, 0x1B008000)
+__AARCH64_INSN_FUNCS(udiv,      0x7FE0FC00, 0x1AC00800)
+__AARCH64_INSN_FUNCS(sdiv,      0x7FE0FC00, 0x1AC00C00)
+__AARCH64_INSN_FUNCS(lslv,      0x7FE0FC00, 0x1AC02000)
+__AARCH64_INSN_FUNCS(lsrv,      0x7FE0FC00, 0x1AC02400)
+__AARCH64_INSN_FUNCS(asrv,      0x7FE0FC00, 0x1AC02800)
+__AARCH64_INSN_FUNCS(rorv,      0x7FE0FC00, 0x1AC02C00)
+__AARCH64_INSN_FUNCS(rev16,     0x7FFFFC00, 0x5AC00400)
+__AARCH64_INSN_FUNCS(rev32,     0x7FFFFC00, 0x5AC00800)
+__AARCH64_INSN_FUNCS(rev64,     0x7FFFFC00, 0x5AC00C00)
+__AARCH64_INSN_FUNCS(and,       0x7F200000, 0x0A000000)
+__AARCH64_INSN_FUNCS(bic,       0x7F200000, 0x0A200000)
+__AARCH64_INSN_FUNCS(orr,       0x7F200000, 0x2A000000)
+__AARCH64_INSN_FUNCS(orn,       0x7F200000, 0x2A200000)
+__AARCH64_INSN_FUNCS(eor,       0x7F200000, 0x4A000000)
+__AARCH64_INSN_FUNCS(eon,       0x7F200000, 0x4A200000)
+__AARCH64_INSN_FUNCS(ands,      0x7F200000, 0x6A000000)
+__AARCH64_INSN_FUNCS(bics,      0x7F200000, 0x6A200000)
 __AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
 __AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
+__AARCH64_INSN_FUNCS(cbz,       0xFE000000, 0x34000000)
+__AARCH64_INSN_FUNCS(cbnz,      0xFE000000, 0x35000000)
+__AARCH64_INSN_FUNCS(bcond,     0xFF000010, 0x54000000)
 __AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
 __AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
 __AARCH64_INSN_FUNCS(smc,       0xFFE0001F, 0xD4000003)
 __AARCH64_INSN_FUNCS(brk,       0xFFE0001F, 0xD4200000)
 __AARCH64_INSN_FUNCS(hint,      0xFFFFF01F, 0xD503201F)
+__AARCH64_INSN_FUNCS(br,        0xFFFFFC1F, 0xD61F0000)
+__AARCH64_INSN_FUNCS(blr,       0xFFFFFC1F, 0xD63F0000)
+__AARCH64_INSN_FUNCS(ret,       0xFFFFFC1F, 0xD65F0000)
 
 #undef  __AARCH64_INSN_FUNCS
 
@@ -97,8 +287,67 @@ u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
                                   u32 insn, u64 imm);
 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
                                 enum aarch64_insn_branch_type type);
+u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
+                                     enum aarch64_insn_register reg,
+                                     enum aarch64_insn_variant variant,
+                                     enum aarch64_insn_branch_type type);
+u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
+                                     enum aarch64_insn_condition cond);
 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
 u32 aarch64_insn_gen_nop(void);
+u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
+                                enum aarch64_insn_branch_type type);
+u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
+                                    enum aarch64_insn_register base,
+                                    enum aarch64_insn_register offset,
+                                    enum aarch64_insn_size_type size,
+                                    enum aarch64_insn_ldst_type type);
+u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
+                                     enum aarch64_insn_register reg2,
+                                     enum aarch64_insn_register base,
+                                     int offset,
+                                     enum aarch64_insn_variant variant,
+                                     enum aarch64_insn_ldst_type type);
+u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
+                                 enum aarch64_insn_register src,
+                                 int imm, enum aarch64_insn_variant variant,
+                                 enum aarch64_insn_adsb_type type);
+u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
+                              enum aarch64_insn_register src,
+                              int immr, int imms,
+                              enum aarch64_insn_variant variant,
+                              enum aarch64_insn_bitfield_type type);
+u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
+                              int imm, int shift,
+                              enum aarch64_insn_variant variant,
+                              enum aarch64_insn_movewide_type type);
+u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
+                                         enum aarch64_insn_register src,
+                                         enum aarch64_insn_register reg,
+                                         int shift,
+                                         enum aarch64_insn_variant variant,
+                                         enum aarch64_insn_adsb_type type);
+u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
+                           enum aarch64_insn_register src,
+                           enum aarch64_insn_variant variant,
+                           enum aarch64_insn_data1_type type);
+u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
+                           enum aarch64_insn_register src,
+                           enum aarch64_insn_register reg,
+                           enum aarch64_insn_variant variant,
+                           enum aarch64_insn_data2_type type);
+u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
+                           enum aarch64_insn_register src,
+                           enum aarch64_insn_register reg1,
+                           enum aarch64_insn_register reg2,
+                           enum aarch64_insn_variant variant,
+                           enum aarch64_insn_data3_type type);
+u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
+                                         enum aarch64_insn_register src,
+                                         enum aarch64_insn_register reg,
+                                         int shift,
+                                         enum aarch64_insn_variant variant,
+                                         enum aarch64_insn_logic_type type);
 
 bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
 
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index e0ecdcf6632d..79f1d519221f 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -121,7 +121,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 /*
  *  I/O port access primitives.
  */
-#define IO_SPACE_LIMIT          0xffff
+#define arch_has_dev_port()     (1)
+#define IO_SPACE_LIMIT          (SZ_32M - 1)
 #define PCI_IOBASE              ((void __iomem *)(MODULES_VADDR - SZ_32M))
 
 static inline u8 inb(unsigned long addr)
@@ -243,7 +244,7 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
  * (PHYS_OFFSET and PHYS_MASK taken into account).
  */
 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
-extern int valid_phys_addr_range(unsigned long addr, size_t size);
+extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 
 extern int devmem_is_allowed(unsigned long pfn);
diff --git a/arch/arm64/include/asm/irq_work.h b/arch/arm64/include/asm/irq_work.h
new file mode 100644
index 000000000000..8e24ef3f7c82
--- /dev/null
+++ b/arch/arm64/include/asm/irq_work.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_IRQ_WORK_H
+#define __ASM_IRQ_WORK_H
+
+#include <asm/smp.h>
+
+static inline bool arch_irq_work_has_interrupt(void)
+{
+        return !!__smp_cross_call;
+}
+
+#endif /* __ASM_IRQ_WORK_H */
diff --git a/arch/arm64/include/asm/kgdb.h b/arch/arm64/include/asm/kgdb.h
index 3c8aafc1082f..f69f69c8120c 100644
--- a/arch/arm64/include/asm/kgdb.h
+++ b/arch/arm64/include/asm/kgdb.h
@@ -29,7 +29,7 @@
 
 static inline void arch_kgdb_breakpoint(void)
 {
-        asm ("brk %0" : : "I" (KDBG_COMPILED_DBG_BRK_IMM));
+        asm ("brk %0" : : "I" (KGDB_COMPILED_DBG_BRK_IMM));
 }
 
 extern void kgdb_handle_bus_error(void);
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index cc83520459ed..7fd3e27e3ccc 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -122,6 +122,17 @@
 #define VTCR_EL2_T0SZ_MASK      0x3f
 #define VTCR_EL2_T0SZ_40B       24
 
+/*
+ * We configure the Stage-2 page tables to always restrict the IPA space to be
+ * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
+ * not known to exist and will break with this configuration.
+ *
+ * Note that when using 4K pages, we concatenate two first level page tables
+ * together.
+ *
+ * The magic numbers used for VTTBR_X in this patch can be found in Tables
+ * D4-23 and D4-25 in ARM DDI 0487A.b.
+ */
 #ifdef CONFIG_ARM64_64K_PAGES
 /*
  * Stage2 translation configuration:
@@ -149,7 +160,7 @@
 #endif
 
 #define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
-#define VTTBR_BADDR_MASK  (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_BADDR_MASK  (((1LLU << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
 #define VTTBR_VMID_SHIFT  (48LLU)
 #define VTTBR_VMID_MASK   (0xffLLU << VTTBR_VMID_SHIFT)
 
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index fdc3e21abd8d..5674a55b5518 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -174,6 +174,11 @@ static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
 
 static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
 {
+        return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC;
+}
+
+static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
+{
         return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC_TYPE;
 }
 
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index e10c45a578e3..2012c4ba8d67 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -22,6 +22,8 @@
 #ifndef __ARM64_KVM_HOST_H__
 #define __ARM64_KVM_HOST_H__
 
+#include <linux/types.h>
+#include <linux/kvm_types.h>
 #include <asm/kvm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
@@ -41,8 +43,7 @@
 
 #define KVM_VCPU_MAX_FEATURES 3
 
-struct kvm_vcpu;
-int kvm_target_cpu(void);
+int __attribute_const__ kvm_target_cpu(void);
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
 int kvm_arch_dev_ioctl_check_extension(long ext);
 
@@ -164,25 +165,23 @@ struct kvm_vcpu_stat {
         u32 halt_wakeup;
 };
 
-struct kvm_vcpu_init;
 int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
                         const struct kvm_vcpu_init *init);
 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
-struct kvm_one_reg;
 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 
 #define KVM_ARCH_WANT_MMU_NOTIFIER
-struct kvm;
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 int kvm_unmap_hva_range(struct kvm *kvm,
                         unsigned long start, unsigned long end);
 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 
 /* We do not have shadow page tables, hence the empty hooks */
-static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+static inline int kvm_age_hva(struct kvm *kvm, unsigned long start,
+                              unsigned long end)
 {
         return 0;
 }
@@ -192,8 +191,13 @@ static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
         return 0;
 }
 
+static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
+                                                         unsigned long address)
+{
+}
+
 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
-struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
+struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
 
 u64 kvm_call_hyp(void *hypfn, ...);
 
@@ -244,4 +248,10 @@ static inline void vgic_arch_setup(const struct vgic_params *vgic)
         }
 }
 
+static inline void kvm_arch_hardware_disable(void) {}
+static inline void kvm_arch_hardware_unsetup(void) {}
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
+
 #endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 8e138c7c53ac..a030d163840b 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -59,10 +59,9 @@
 #define KERN_TO_HYP(kva)        ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
 
 /*
- * Align KVM with the kernel's view of physical memory. Should be
- * 40bit IPA, with PGD being 8kB aligned in the 4KB page configuration.
+ * We currently only support a 40bit IPA.
  */
-#define KVM_PHYS_SHIFT  PHYS_MASK_SHIFT
+#define KVM_PHYS_SHIFT  (40)
 #define KVM_PHYS_SIZE   (1UL << KVM_PHYS_SHIFT)
 #define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1UL)
 
@@ -93,19 +92,6 @@ void kvm_clear_hyp_idmap(void);
 #define kvm_set_pte(ptep, pte)          set_pte(ptep, pte)
 #define kvm_set_pmd(pmdp, pmd)          set_pmd(pmdp, pmd)
 
-static inline bool kvm_is_write_fault(unsigned long esr)
-{
-        unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
-
-        if (esr_ec == ESR_EL2_EC_IABT)
-                return false;
-
-        if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR))
-                return false;
-
-        return true;
-}
-
 static inline void kvm_clean_pgd(pgd_t *pgd) {}
 static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
 static inline void kvm_clean_pte(pte_t *pte) {}
diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
new file mode 100644
index 000000000000..872ba939fcb2
--- /dev/null
+++ b/arch/arm64/include/asm/pci.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_PCI_H
+#define __ASM_PCI_H
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+#include <asm-generic/pci-bridge.h>
+#include <asm-generic/pci-dma-compat.h>
+
+#define PCIBIOS_MIN_IO          0x1000
+#define PCIBIOS_MIN_MEM         0
+
+/*
+ * Set to 1 if the kernel should re-assign all PCI bus numbers
+ */
+#define pcibios_assign_all_busses() \
+        (pci_has_flag(PCI_REASSIGN_ALL_BUS))
+
+/*
+ * PCI address space differs from physical memory address space
+ */
+#define PCI_DMA_BUS_IS_PHYS     (0)
+
+extern int isa_dma_bridge_buggy;
+
+#ifdef CONFIG_PCI
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        return 1;
+}
+#endif  /* CONFIG_PCI */
+
+#endif  /* __KERNEL__ */
+#endif  /* __ASM_PCI_H */
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 453a179469a3..5279e5733386 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -26,13 +26,13 @@ static inline void set_my_cpu_offset(unsigned long off)
 static inline unsigned long __my_cpu_offset(void)
 {
         unsigned long off;
-        register unsigned long *sp asm ("sp");
 
         /*
          * We want to allow caching the value, so avoid using volatile and
          * instead use a fake stack read to hazard against barrier().
          */
-        asm("mrs %0, tpidr_el1" : "=r" (off) : "Q" (*sp));
+        asm("mrs %0, tpidr_el1" : "=r" (off) :
+                "Q" (*(const unsigned long *)current_stack_pointer));
 
         return off;
 }
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index ffe1ba0506d1..cefd3e825612 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -149,46 +149,51 @@ extern struct page *empty_zero_page;
 #define pte_valid_not_user(pte) \
         ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
 
-static inline pte_t pte_wrprotect(pte_t pte)
+static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
 {
-        pte_val(pte) &= ~PTE_WRITE;
+        pte_val(pte) &= ~pgprot_val(prot);
         return pte;
 }
 
-static inline pte_t pte_mkwrite(pte_t pte)
+static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
 {
-        pte_val(pte) |= PTE_WRITE;
+        pte_val(pte) |= pgprot_val(prot);
         return pte;
 }
 
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        return clear_pte_bit(pte, __pgprot(PTE_WRITE));
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        return set_pte_bit(pte, __pgprot(PTE_WRITE));
+}
+
 static inline pte_t pte_mkclean(pte_t pte)
 {
-        pte_val(pte) &= ~PTE_DIRTY;
-        return pte;
+        return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
 }
 
 static inline pte_t pte_mkdirty(pte_t pte)
 {
-        pte_val(pte) |= PTE_DIRTY;
-        return pte;
+        return set_pte_bit(pte, __pgprot(PTE_DIRTY));
 }
 
 static inline pte_t pte_mkold(pte_t pte)
 {
-        pte_val(pte) &= ~PTE_AF;
-        return pte;
+        return clear_pte_bit(pte, __pgprot(PTE_AF));
 }
 
 static inline pte_t pte_mkyoung(pte_t pte)
 {
-        pte_val(pte) |= PTE_AF;
-        return pte;
+        return set_pte_bit(pte, __pgprot(PTE_AF));
 }
 
 static inline pte_t pte_mkspecial(pte_t pte)
 {
-        pte_val(pte) |= PTE_SPECIAL;
-        return pte;
+        return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
 }
 
 static inline void set_pte(pte_t *ptep, pte_t pte)
@@ -239,6 +244,16 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 
 #define __HAVE_ARCH_PTE_SPECIAL
 
+static inline pte_t pud_pte(pud_t pud)
+{
+        return __pte(pud_val(pud));
+}
+
+static inline pmd_t pud_pmd(pud_t pud)
+{
+        return __pmd(pud_val(pud));
+}
+
 static inline pte_t pmd_pte(pmd_t pmd)
 {
         return __pte(pmd_val(pmd));
@@ -256,7 +271,13 @@ static inline pmd_t pte_pmd(pte_t pte)
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 #define pmd_trans_huge(pmd)     (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
 #define pmd_trans_splitting(pmd)        pte_special(pmd_pte(pmd))
-#endif
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
+struct vm_area_struct;
+void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
+                          pmd_t *pmdp);
+#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 
 #define pmd_young(pmd)          pte_young(pmd_pte(pmd))
 #define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
@@ -277,6 +298,7 @@ static inline pmd_t pte_pmd(pte_t pte)
 #define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
 
 #define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
+#define pud_write(pud)          pte_write(pud_pte(pud))
 #define pud_pfn(pud)            (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
 
 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
@@ -296,6 +318,8 @@ static inline int has_transparent_hugepage(void)
         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
 #define pgprot_writecombine(prot) \
         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
+#define pgprot_device(prot) \
+        __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
 #define __HAVE_PHYS_MEM_ACCESS_PROT
 struct file;
 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
@@ -376,6 +400,8 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
         return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
 }
 
+#define pud_page(pud)           pmd_page(pud_pmd(pud))
+
 #endif  /* CONFIG_ARM64_PGTABLE_LEVELS > 2 */
 
 #if CONFIG_ARM64_PGTABLE_LEVELS > 3
diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h
index 0c657bb54597..9a8fd84f8fb2 100644
--- a/arch/arm64/include/asm/proc-fns.h
+++ b/arch/arm64/include/asm/proc-fns.h
@@ -32,6 +32,8 @@ extern void cpu_cache_off(void);
 extern void cpu_do_idle(void);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+void cpu_soft_restart(phys_addr_t cpu_reset,
+                unsigned long addr) __attribute__((noreturn));
 extern void cpu_do_suspend(struct cpu_suspend_ctx *ptr);
 extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr);
 
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 3df21feeabdd..286b1bec547c 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -139,7 +139,7 @@ extern struct task_struct *cpu_switch_to(struct task_struct *prev,
         ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
 
 #define KSTK_EIP(tsk)   ((unsigned long)task_pt_regs(tsk)->pc)
-#define KSTK_ESP(tsk)   ((unsigned long)task_pt_regs(tsk)->sp)
+#define KSTK_ESP(tsk)   user_stack_pointer(task_pt_regs(tsk))
 
 /*
  * Prefetching support
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 501000fadb6f..41ed9e13795e 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -137,7 +137,7 @@ struct pt_regs {
         (!((regs)->pstate & PSR_F_BIT))
 
 #define user_stack_pointer(regs) \
-        (!compat_user_mode(regs)) ? ((regs)->sp) : ((regs)->compat_sp)
+        (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
 
 static inline unsigned long regs_return_value(struct pt_regs *regs)
 {
diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
index a498f2cd2c2a..780f82c827b6 100644
--- a/arch/arm64/include/asm/smp.h
+++ b/arch/arm64/include/asm/smp.h
@@ -48,6 +48,8 @@ extern void smp_init_cpus(void);
  */
 extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
 
+extern void (*__smp_cross_call)(const struct cpumask *, unsigned int);
+
 /*
  * Called from the secondary holding pen, this is the secondary CPU entry point.
  */
diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h
index 1be62bcb9d47..74a9d301819f 100644
--- a/arch/arm64/include/asm/sparsemem.h
+++ b/arch/arm64/include/asm/sparsemem.h
@@ -17,7 +17,7 @@
 #define __ASM_SPARSEMEM_H
 
 #ifdef CONFIG_SPARSEMEM
-#define MAX_PHYSMEM_BITS        40
+#define MAX_PHYSMEM_BITS        48
 #define SECTION_SIZE_BITS       30
 #endif
 
diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/suspend.h
index e9c149c042e0..456d67c1f0fa 100644
--- a/arch/arm64/include/asm/suspend.h
+++ b/arch/arm64/include/asm/suspend.h
@@ -21,6 +21,7 @@ struct sleep_save_sp {
         phys_addr_t save_ptr_stash_phys;
 };
 
+extern int __cpu_suspend(unsigned long arg, int (*fn)(unsigned long));
 extern void cpu_resume(void);
 extern int cpu_suspend(unsigned long);
 
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
index 45108d802f5e..459bf8e53208 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -69,14 +69,19 @@ struct thread_info {
 #define init_stack              (init_thread_union.stack)
 
 /*
+ * how to get the current stack pointer from C
+ */
+register unsigned long current_stack_pointer asm ("sp");
+
+/*
  * how to get the thread information struct from C
  */
 static inline struct thread_info *current_thread_info(void) __attribute_const__;
 
 static inline struct thread_info *current_thread_info(void)
 {
-        register unsigned long sp asm ("sp");
-        return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
+        return (struct thread_info *)
+                (current_stack_pointer & ~(THREAD_SIZE - 1));
 }
 
 #define thread_saved_pc(tsk)    \
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index 62731ef9749a..a82c0c5c8b52 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -23,6 +23,20 @@
 
 #include <asm-generic/tlb.h>
 
+#include <linux/pagemap.h>
+#include <linux/swap.h>
+
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+
+#define tlb_remove_entry(tlb, entry)    tlb_remove_table(tlb, entry)
+static inline void __tlb_remove_table(void *_table)
+{
+        free_page_and_swap_cache((struct page *)_table);
+}
+#else
+#define tlb_remove_entry(tlb, entry)    tlb_remove_page(tlb, entry)
+#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
+
 /*
  * There's three ways the TLB shootdown code is used:
  *  1. Unmapping a range of vmas.  See zap_page_range(), unmap_region().
@@ -88,7 +102,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 {
         pgtable_page_dtor(pte);
         tlb_add_flush(tlb, addr);
-        tlb_remove_page(tlb, pte);
+        tlb_remove_entry(tlb, pte);
 }
 
 #if CONFIG_ARM64_PGTABLE_LEVELS > 2
@@ -96,7 +110,7 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
                                   unsigned long addr)
 {
         tlb_add_flush(tlb, addr);
-        tlb_remove_page(tlb, virt_to_page(pmdp));
+        tlb_remove_entry(tlb, virt_to_page(pmdp));
 }
 #endif
 
@@ -105,7 +119,7 @@ static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,
                                   unsigned long addr)
 {
         tlb_add_flush(tlb, addr);
-        tlb_remove_page(tlb, virt_to_page(pudp));
+        tlb_remove_entry(tlb, virt_to_page(pudp));
 }
 #endif
 
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index 4bc95d27e063..6d2bf419431d 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -41,7 +41,7 @@
 #define __ARM_NR_compat_cacheflush      (__ARM_NR_COMPAT_BASE+2)
 #define __ARM_NR_compat_set_tls         (__ARM_NR_COMPAT_BASE+5)
 
-#define __NR_compat_syscalls            383
+#define __NR_compat_syscalls            386
 #endif
 
 #define __ARCH_WANT_SYS_CLONE
diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h
index e242600c4046..da1f06b535e3 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -787,3 +787,8 @@ __SYSCALL(__NR_sched_setattr, sys_sched_setattr)
 __SYSCALL(__NR_sched_getattr, sys_sched_getattr)
 #define __NR_renameat2 382
 __SYSCALL(__NR_renameat2, sys_renameat2)
+                        /* 383 for seccomp */
+#define __NR_getrandom 384
+__SYSCALL(__NR_getrandom, sys_getrandom)
+#define __NR_memfd_create 385
+__SYSCALL(__NR_memfd_create, sys_memfd_create)
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index e633ff8cdec8..8e38878c87c6 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -37,6 +37,7 @@
 
 #define __KVM_HAVE_GUEST_DEBUG
 #define __KVM_HAVE_IRQ_LINE
+#define __KVM_HAVE_READONLY_MEM
 
 #define KVM_REG_SIZE(id)                                                \
         (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
@@ -159,6 +160,7 @@ struct kvm_arch_memory_slot {
 #define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
 #define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
 #define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
+#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
 
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT          24
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index df7ef8768fc2..5bd029b43644 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -26,9 +26,11 @@ arm64-obj-$(CONFIG_PERF_EVENTS)		+= perf_regs.o
 arm64-obj-$(CONFIG_HW_PERF_EVENTS)      += perf_event.o
 arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)  += hw_breakpoint.o
 arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND)   += sleep.o suspend.o
+arm64-obj-$(CONFIG_CPU_IDLE)            += cpuidle.o
 arm64-obj-$(CONFIG_JUMP_LABEL)          += jump_label.o
 arm64-obj-$(CONFIG_KGDB)                += kgdb.o
 arm64-obj-$(CONFIG_EFI)                 += efi.o efi-stub.o efi-entry.o
+arm64-obj-$(CONFIG_PCI)                 += pci.o
 
 obj-y                                   += $(arm64-obj-y) vdso/
 obj-m                                   += $(arm64-obj-m)
diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
new file mode 100644
index 000000000000..19d17f51db37
--- /dev/null
+++ b/arch/arm64/kernel/cpuidle.c
@@ -0,0 +1,31 @@
+/*
+ * ARM64 CPU idle arch support
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+#include <asm/cpuidle.h>
+#include <asm/cpu_ops.h>
+
+int cpu_init_idle(unsigned int cpu)
+{
+        int ret = -EOPNOTSUPP;
+        struct device_node *cpu_node = of_cpu_device_node_get(cpu);
+
+        if (!cpu_node)
+                return -ENODEV;
+
+        if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_init_idle)
+                ret = cpu_ops[cpu]->cpu_init_idle(cpu_node, cpu);
+
+        of_node_put(cpu_node);
+        return ret;
+}
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index f798f66634af..504fdaa8367e 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -20,8 +20,10 @@
 #include <asm/cputype.h>
 
 #include <linux/bitops.h>
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/preempt.h>
 #include <linux/printk.h>
 #include <linux/smp.h>
 
@@ -47,9 +49,19 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
         unsigned int cpu = smp_processor_id();
         u32 l1ip = CTR_L1IP(info->reg_ctr);
 
-        if (l1ip != ICACHE_POLICY_PIPT)
-                set_bit(ICACHEF_ALIASING, &__icache_flags);
-        if (l1ip == ICACHE_POLICY_AIVIVT);
+        if (l1ip != ICACHE_POLICY_PIPT) {
+                /*
+                 * VIPT caches are non-aliasing if the VA always equals the PA
+                 * in all bit positions that are covered by the index. This is
+                 * the case if the size of a way (# of sets * line size) does
+                 * not exceed PAGE_SIZE.
+                 */
+                u32 waysize = icache_get_numsets() * icache_get_linesize();
+
+                if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
+                        set_bit(ICACHEF_ALIASING, &__icache_flags);
+        }
+        if (l1ip == ICACHE_POLICY_AIVIVT)
                 set_bit(ICACHEF_AIVIVT, &__icache_flags);
 
         pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
@@ -190,3 +202,15 @@ void __init cpuinfo_store_boot_cpu(void)
 
         boot_cpu_data = *info;
 }
+
+u64 __attribute_const__ icache_get_ccsidr(void)
+{
+        u64 ccsidr;
+
+        WARN_ON(preemptible());
+
+        /* Select L1 I-cache and read its size ID register */
+        asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1"
+            : "=r"(ccsidr) : "r"(1L));
+        return ccsidr;
+}
diff --git a/arch/arm64/kernel/efi-stub.c b/arch/arm64/kernel/efi-stub.c
index 1317fef8dde9..d27dd982ff26 100644
--- a/arch/arm64/kernel/efi-stub.c
+++ b/arch/arm64/kernel/efi-stub.c
@@ -28,20 +28,16 @@ efi_status_t handle_kernel_image(efi_system_table_t *sys_table,
         kernel_size = _edata - _text;
         if (*image_addr != (dram_base + TEXT_OFFSET)) {
                 kernel_memsize = kernel_size + (_end - _edata);
-                status = efi_relocate_kernel(sys_table, image_addr,
-                                             kernel_size, kernel_memsize,
-                                             dram_base + TEXT_OFFSET,
-                                             PAGE_SIZE);
+                status = efi_low_alloc(sys_table, kernel_memsize + TEXT_OFFSET,
+                                       SZ_2M, reserve_addr);
                 if (status != EFI_SUCCESS) {
                         pr_efi_err(sys_table, "Failed to relocate kernel\n");
                         return status;
                 }
-                if (*image_addr != (dram_base + TEXT_OFFSET)) {
-                        pr_efi_err(sys_table, "Failed to alloc kernel memory\n");
-                        efi_free(sys_table, kernel_memsize, *image_addr);
-                        return EFI_LOAD_ERROR;
-                }
-                *image_size = kernel_memsize;
+                memcpy((void *)*reserve_addr + TEXT_OFFSET, (void *)*image_addr,
+                       kernel_size);
+                *image_addr = *reserve_addr + TEXT_OFFSET;
+                *reserve_size = kernel_memsize + TEXT_OFFSET;
         }
 
 
diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c
index e72f3100958f..03aaa99e1ea0 100644
--- a/arch/arm64/kernel/efi.c
+++ b/arch/arm64/kernel/efi.c
@@ -188,6 +188,8 @@ static __init void reserve_regions(void)
                 if (uefi_debug)
                         pr_cont("\n");
         }
+
+        set_bit(EFI_MEMMAP, &efi.flags);
 }
 
 
@@ -463,6 +465,8 @@ static int __init arm64_enter_virtual_mode(void)
         efi_native_runtime_setup();
         set_bit(EFI_RUNTIME_SERVICES, &efi.flags);
 
+        efi.runtime_version = efi.systab->hdr.revision;
+
         return 0;
 
 err_unmap:
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index f0b5e5120a87..726b910fe6ec 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -324,7 +324,6 @@ el1_dbg:
         mrs     x0, far_el1
         mov     x2, sp                          // struct pt_regs
         bl      do_debug_exception
-        enable_dbg
         kernel_exit 1
 el1_inv:
         // TODO: add support for undefined instructions in kernel mode
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index ad8aebb1cdef..3dca15634e69 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -270,6 +270,7 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
         case CPU_PM_ENTER:
                 if (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))
                         fpsimd_save_state(&current->thread.fpsimd_state);
+                this_cpu_write(fpsimd_last_state, NULL);
                 break;
         case CPU_PM_EXIT:
                 if (current->mm)
diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index 7924d73b6476..cf8556ae09d0 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -58,7 +58,8 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
         u32 new;
 
         pc = (unsigned long)&ftrace_call;
-        new = aarch64_insn_gen_branch_imm(pc, (unsigned long)func, true);
+        new = aarch64_insn_gen_branch_imm(pc, (unsigned long)func,
+                                          AARCH64_INSN_BRANCH_LINK);
 
         return ftrace_modify_code(pc, 0, new, false);
 }
@@ -72,7 +73,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
         u32 old, new;
 
         old = aarch64_insn_gen_nop();
-        new = aarch64_insn_gen_branch_imm(pc, addr, true);
+        new = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
 
         return ftrace_modify_code(pc, old, new, true);
 }
@@ -86,7 +87,7 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
         unsigned long pc = rec->ip;
         u32 old, new;
 
-        old = aarch64_insn_gen_branch_imm(pc, addr, true);
+        old = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
         new = aarch64_insn_gen_nop();
 
         return ftrace_modify_code(pc, old, new, true);
@@ -154,7 +155,8 @@ static int ftrace_modify_graph_caller(bool enable)
         u32 branch, nop;
 
         branch = aarch64_insn_gen_branch_imm(pc,
-                        (unsigned long)ftrace_graph_caller, false);
+                                             (unsigned long)ftrace_graph_caller,
+                                             AARCH64_INSN_BRANCH_LINK);
         nop = aarch64_insn_gen_nop();
 
         if (enable)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 144f10567f82..0a6e4f924df8 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -38,11 +38,11 @@
 
 #define KERNEL_RAM_VADDR        (PAGE_OFFSET + TEXT_OFFSET)
 
-#if (TEXT_OFFSET & 0xf) != 0
-#error TEXT_OFFSET must be at least 16B aligned
-#elif (PAGE_OFFSET & 0xfffff) != 0
+#if (TEXT_OFFSET & 0xfff) != 0
+#error TEXT_OFFSET must be at least 4KB aligned
+#elif (PAGE_OFFSET & 0x1fffff) != 0
 #error PAGE_OFFSET must be at least 2MB aligned
-#elif TEXT_OFFSET > 0xfffff
+#elif TEXT_OFFSET > 0x1fffff
 #error TEXT_OFFSET must be less than 2MB
 #endif
 
@@ -151,7 +151,7 @@ optional_header:
         .short  0x20b                           // PE32+ format
         .byte   0x02                            // MajorLinkerVersion
         .byte   0x14                            // MinorLinkerVersion
-        .long   _edata - stext                  // SizeOfCode
+        .long   _end - stext                    // SizeOfCode
         .long   0                               // SizeOfInitializedData
         .long   0                               // SizeOfUninitializedData
         .long   efi_stub_entry - efi_head       // AddressOfEntryPoint
@@ -169,7 +169,7 @@ extra_header_fields:
         .short  0                               // MinorSubsystemVersion
         .long   0                               // Win32VersionValue
 
-        .long   _edata - efi_head               // SizeOfImage
+        .long   _end - efi_head                 // SizeOfImage
 
         // Everything before the kernel image is considered part of the header
         .long   stext - efi_head                // SizeOfHeaders
@@ -216,7 +216,7 @@ section_table:
         .byte   0
         .byte   0
         .byte   0                       // end of 0 padding of section name
-        .long   _edata - stext          // VirtualSize
+        .long   _end - stext            // VirtualSize
         .long   stext - efi_head        // VirtualAddress
         .long   _edata - stext          // SizeOfRawData
         .long   stext - efi_head        // PointerToRawData
@@ -373,10 +373,6 @@ ENTRY(__boot_cpu_mode)
         .long   0
         .popsection
 
-        .align  3
-2:      .quad   .
-        .quad   PAGE_OFFSET
-
 #ifdef CONFIG_SMP
         .align  3
 1:      .quad   .
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 92f36835486b..e007714ded04 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -2,6 +2,8 @@
  * Copyright (C) 2013 Huawei Ltd.
  * Author: Jiang Liu <liuj97@gmail.com>
  *
+ * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -20,9 +22,14 @@
 #include <linux/smp.h>
 #include <linux/stop_machine.h>
 #include <linux/uaccess.h>
+
 #include <asm/cacheflush.h>
+#include <asm/debug-monitors.h>
 #include <asm/insn.h>
 
+#define AARCH64_INSN_SF_BIT     BIT(31)
+#define AARCH64_INSN_N_BIT      BIT(22)
+
 static int aarch64_insn_encoding_class[] = {
         AARCH64_INSN_CLS_UNKNOWN,
         AARCH64_INSN_CLS_UNKNOWN,
@@ -251,6 +258,19 @@ u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
                 mask = BIT(9) - 1;
                 shift = 12;
                 break;
+        case AARCH64_INSN_IMM_7:
+                mask = BIT(7) - 1;
+                shift = 15;
+                break;
+        case AARCH64_INSN_IMM_6:
+        case AARCH64_INSN_IMM_S:
+                mask = BIT(6) - 1;
+                shift = 10;
+                break;
+        case AARCH64_INSN_IMM_R:
+                mask = BIT(6) - 1;
+                shift = 16;
+                break;
         default:
                 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
                         type);
@@ -264,10 +284,76 @@ u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
         return insn;
 }
 
-u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
-                                          enum aarch64_insn_branch_type type)
+static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
+                                        u32 insn,
+                                        enum aarch64_insn_register reg)
+{
+        int shift;
+
+        if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
+                pr_err("%s: unknown register encoding %d\n", __func__, reg);
+                return 0;
+        }
+
+        switch (type) {
+        case AARCH64_INSN_REGTYPE_RT:
+        case AARCH64_INSN_REGTYPE_RD:
+                shift = 0;
+                break;
+        case AARCH64_INSN_REGTYPE_RN:
+                shift = 5;
+                break;
+        case AARCH64_INSN_REGTYPE_RT2:
+        case AARCH64_INSN_REGTYPE_RA:
+                shift = 10;
+                break;
+        case AARCH64_INSN_REGTYPE_RM:
+                shift = 16;
+                break;
+        default:
+                pr_err("%s: unknown register type encoding %d\n", __func__,
+                       type);
+                return 0;
+        }
+
+        insn &= ~(GENMASK(4, 0) << shift);
+        insn |= reg << shift;
+
+        return insn;
+}
+
+static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
+                                         u32 insn)
+{
+        u32 size;
+
+        switch (type) {
+        case AARCH64_INSN_SIZE_8:
+                size = 0;
+                break;
+        case AARCH64_INSN_SIZE_16:
+                size = 1;
+                break;
+        case AARCH64_INSN_SIZE_32:
+                size = 2;
+                break;
+        case AARCH64_INSN_SIZE_64:
+                size = 3;
+                break;
+        default:
+                pr_err("%s: unknown size encoding %d\n", __func__, type);
+                return 0;
+        }
+
+        insn &= ~GENMASK(31, 30);
+        insn |= size << 30;
+
+        return insn;
+}
+
+static inline long branch_imm_common(unsigned long pc, unsigned long addr,
+                                     long range)
 {
-        u32 insn;
         long offset;
 
         /*
@@ -276,23 +362,97 @@ u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
          */
         BUG_ON((pc & 0x3) || (addr & 0x3));
 
+        offset = ((long)addr - (long)pc);
+        BUG_ON(offset < -range || offset >= range);
+
+        return offset;
+}
+
+u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
+                                          enum aarch64_insn_branch_type type)
+{
+        u32 insn;
+        long offset;
+
         /*
          * B/BL support [-128M, 128M) offset
          * ARM64 virtual address arrangement guarantees all kernel and module
          * texts are within +/-128M.
          */
-        offset = ((long)addr - (long)pc);
-        BUG_ON(offset < -SZ_128M || offset >= SZ_128M);
+        offset = branch_imm_common(pc, addr, SZ_128M);
 
-        if (type == AARCH64_INSN_BRANCH_LINK)
+        switch (type) {
+        case AARCH64_INSN_BRANCH_LINK:
                 insn = aarch64_insn_get_bl_value();
-        else
+                break;
+        case AARCH64_INSN_BRANCH_NOLINK:
                 insn = aarch64_insn_get_b_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
 
         return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
                                              offset >> 2);
 }
 
+u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
+                                     enum aarch64_insn_register reg,
+                                     enum aarch64_insn_variant variant,
+                                     enum aarch64_insn_branch_type type)
+{
+        u32 insn;
+        long offset;
+
+        offset = branch_imm_common(pc, addr, SZ_1M);
+
+        switch (type) {
+        case AARCH64_INSN_BRANCH_COMP_ZERO:
+                insn = aarch64_insn_get_cbz_value();
+                break;
+        case AARCH64_INSN_BRANCH_COMP_NONZERO:
+                insn = aarch64_insn_get_cbnz_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
+                                             offset >> 2);
+}
+
+u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
+                                     enum aarch64_insn_condition cond)
+{
+        u32 insn;
+        long offset;
+
+        offset = branch_imm_common(pc, addr, SZ_1M);
+
+        insn = aarch64_insn_get_bcond_value();
+
+        BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
+        insn |= cond;
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
+                                             offset >> 2);
+}
+
 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
 {
         return aarch64_insn_get_hint_value() | op;
@@ -302,3 +462,500 @@ u32 __kprobes aarch64_insn_gen_nop(void)
 {
         return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
 }
+
+u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
+                                enum aarch64_insn_branch_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_BRANCH_NOLINK:
+                insn = aarch64_insn_get_br_value();
+                break;
+        case AARCH64_INSN_BRANCH_LINK:
+                insn = aarch64_insn_get_blr_value();
+                break;
+        case AARCH64_INSN_BRANCH_RETURN:
+                insn = aarch64_insn_get_ret_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
+}
+
+u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
+                                    enum aarch64_insn_register base,
+                                    enum aarch64_insn_register offset,
+                                    enum aarch64_insn_size_type size,
+                                    enum aarch64_insn_ldst_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
+                insn = aarch64_insn_get_ldr_reg_value();
+                break;
+        case AARCH64_INSN_LDST_STORE_REG_OFFSET:
+                insn = aarch64_insn_get_str_reg_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        insn = aarch64_insn_encode_ldst_size(size, insn);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
+                                            base);
+
+        return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
+                                            offset);
+}
+
+u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
+                                     enum aarch64_insn_register reg2,
+                                     enum aarch64_insn_register base,
+                                     int offset,
+                                     enum aarch64_insn_variant variant,
+                                     enum aarch64_insn_ldst_type type)
+{
+        u32 insn;
+        int shift;
+
+        switch (type) {
+        case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
+                insn = aarch64_insn_get_ldp_pre_value();
+                break;
+        case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
+                insn = aarch64_insn_get_stp_pre_value();
+                break;
+        case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
+                insn = aarch64_insn_get_ldp_post_value();
+                break;
+        case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
+                insn = aarch64_insn_get_stp_post_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                /* offset must be multiples of 4 in the range [-256, 252] */
+                BUG_ON(offset & 0x3);
+                BUG_ON(offset < -256 || offset > 252);
+                shift = 2;
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                /* offset must be multiples of 8 in the range [-512, 504] */
+                BUG_ON(offset & 0x7);
+                BUG_ON(offset < -512 || offset > 504);
+                shift = 3;
+                insn |= AARCH64_INSN_SF_BIT;
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
+                                            reg1);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
+                                            reg2);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
+                                            base);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
+                                             offset >> shift);
+}
+
+u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
+                                 enum aarch64_insn_register src,
+                                 int imm, enum aarch64_insn_variant variant,
+                                 enum aarch64_insn_adsb_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_ADSB_ADD:
+                insn = aarch64_insn_get_add_imm_value();
+                break;
+        case AARCH64_INSN_ADSB_SUB:
+                insn = aarch64_insn_get_sub_imm_value();
+                break;
+        case AARCH64_INSN_ADSB_ADD_SETFLAGS:
+                insn = aarch64_insn_get_adds_imm_value();
+                break;
+        case AARCH64_INSN_ADSB_SUB_SETFLAGS:
+                insn = aarch64_insn_get_subs_imm_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        BUG_ON(imm & ~(SZ_4K - 1));
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
+}
+
+u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
+                              enum aarch64_insn_register src,
+                              int immr, int imms,
+                              enum aarch64_insn_variant variant,
+                              enum aarch64_insn_bitfield_type type)
+{
+        u32 insn;
+        u32 mask;
+
+        switch (type) {
+        case AARCH64_INSN_BITFIELD_MOVE:
+                insn = aarch64_insn_get_bfm_value();
+                break;
+        case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
+                insn = aarch64_insn_get_ubfm_value();
+                break;
+        case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
+                insn = aarch64_insn_get_sbfm_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                mask = GENMASK(4, 0);
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
+                mask = GENMASK(5, 0);
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        BUG_ON(immr & ~mask);
+        BUG_ON(imms & ~mask);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+
+        insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
+}
+
+u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
+                              int imm, int shift,
+                              enum aarch64_insn_variant variant,
+                              enum aarch64_insn_movewide_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_MOVEWIDE_ZERO:
+                insn = aarch64_insn_get_movz_value();
+                break;
+        case AARCH64_INSN_MOVEWIDE_KEEP:
+                insn = aarch64_insn_get_movk_value();
+                break;
+        case AARCH64_INSN_MOVEWIDE_INVERSE:
+                insn = aarch64_insn_get_movn_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        BUG_ON(imm & ~(SZ_64K - 1));
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                BUG_ON(shift != 0 && shift != 16);
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
+                       shift != 48);
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        insn |= (shift >> 4) << 21;
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
+}
+
+u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
+                                         enum aarch64_insn_register src,
+                                         enum aarch64_insn_register reg,
+                                         int shift,
+                                         enum aarch64_insn_variant variant,
+                                         enum aarch64_insn_adsb_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_ADSB_ADD:
+                insn = aarch64_insn_get_add_value();
+                break;
+        case AARCH64_INSN_ADSB_SUB:
+                insn = aarch64_insn_get_sub_value();
+                break;
+        case AARCH64_INSN_ADSB_ADD_SETFLAGS:
+                insn = aarch64_insn_get_adds_value();
+                break;
+        case AARCH64_INSN_ADSB_SUB_SETFLAGS:
+                insn = aarch64_insn_get_subs_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                BUG_ON(shift & ~(SZ_32 - 1));
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                BUG_ON(shift & ~(SZ_64 - 1));
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
+}
+
+u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
+                           enum aarch64_insn_register src,
+                           enum aarch64_insn_variant variant,
+                           enum aarch64_insn_data1_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_DATA1_REVERSE_16:
+                insn = aarch64_insn_get_rev16_value();
+                break;
+        case AARCH64_INSN_DATA1_REVERSE_32:
+                insn = aarch64_insn_get_rev32_value();
+                break;
+        case AARCH64_INSN_DATA1_REVERSE_64:
+                BUG_ON(variant != AARCH64_INSN_VARIANT_64BIT);
+                insn = aarch64_insn_get_rev64_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+}
+
+u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
+                           enum aarch64_insn_register src,
+                           enum aarch64_insn_register reg,
+                           enum aarch64_insn_variant variant,
+                           enum aarch64_insn_data2_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_DATA2_UDIV:
+                insn = aarch64_insn_get_udiv_value();
+                break;
+        case AARCH64_INSN_DATA2_SDIV:
+                insn = aarch64_insn_get_sdiv_value();
+                break;
+        case AARCH64_INSN_DATA2_LSLV:
+                insn = aarch64_insn_get_lslv_value();
+                break;
+        case AARCH64_INSN_DATA2_LSRV:
+                insn = aarch64_insn_get_lsrv_value();
+                break;
+        case AARCH64_INSN_DATA2_ASRV:
+                insn = aarch64_insn_get_asrv_value();
+                break;
+        case AARCH64_INSN_DATA2_RORV:
+                insn = aarch64_insn_get_rorv_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+
+        return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
+}
+
+u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
+                           enum aarch64_insn_register src,
+                           enum aarch64_insn_register reg1,
+                           enum aarch64_insn_register reg2,
+                           enum aarch64_insn_variant variant,
+                           enum aarch64_insn_data3_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_DATA3_MADD:
+                insn = aarch64_insn_get_madd_value();
+                break;
+        case AARCH64_INSN_DATA3_MSUB:
+                insn = aarch64_insn_get_msub_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
+                                            reg1);
+
+        return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
+                                            reg2);
+}
+
+u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
+                                         enum aarch64_insn_register src,
+                                         enum aarch64_insn_register reg,
+                                         int shift,
+                                         enum aarch64_insn_variant variant,
+                                         enum aarch64_insn_logic_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_LOGIC_AND:
+                insn = aarch64_insn_get_and_value();
+                break;
+        case AARCH64_INSN_LOGIC_BIC:
+                insn = aarch64_insn_get_bic_value();
+                break;
+        case AARCH64_INSN_LOGIC_ORR:
+                insn = aarch64_insn_get_orr_value();
+                break;
+        case AARCH64_INSN_LOGIC_ORN:
+                insn = aarch64_insn_get_orn_value();
+                break;
+        case AARCH64_INSN_LOGIC_EOR:
+                insn = aarch64_insn_get_eor_value();
+                break;
+        case AARCH64_INSN_LOGIC_EON:
+                insn = aarch64_insn_get_eon_value();
+                break;
+        case AARCH64_INSN_LOGIC_AND_SETFLAGS:
+                insn = aarch64_insn_get_ands_value();
+                break;
+        case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
+                insn = aarch64_insn_get_bics_value();
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                BUG_ON(shift & ~(SZ_32 - 1));
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                BUG_ON(shift & ~(SZ_64 - 1));
+                break;
+        default:
+                BUG_ON(1);
+                return AARCH64_BREAK_FAULT;
+        }
+
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
+}
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 0f08dfd69ebc..071a6ec13bd8 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -40,33 +40,6 @@ int arch_show_interrupts(struct seq_file *p, int prec)
         return 0;
 }
 
-/*
- * handle_IRQ handles all hardware IRQ's.  Decoded IRQs should
- * not come via this function.  Instead, they should provide their
- * own 'handler'.  Used by platform code implementing C-based 1st
- * level decoding.
- */
-void handle_IRQ(unsigned int irq, struct pt_regs *regs)
-{
-        struct pt_regs *old_regs = set_irq_regs(regs);
-
-        irq_enter();
-
-        /*
-         * Some hardware gives randomly wrong interrupts.  Rather
-         * than crashing, do something sensible.
-         */
-        if (unlikely(irq >= nr_irqs)) {
-                pr_warn_ratelimited("Bad IRQ%u\n", irq);
-                ack_bad_irq(irq);
-        } else {
-                generic_handle_irq(irq);
-        }
-
-        irq_exit();
-        set_irq_regs(old_regs);
-}
-
 void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
 {
         if (handle_arch_irq)
@@ -97,19 +70,15 @@ static bool migrate_one_irq(struct irq_desc *desc)
         if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
                 return false;
 
-        if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids)
+        if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
+                affinity = cpu_online_mask;
                 ret = true;
+        }
 
-        /*
-         * when using forced irq_set_affinity we must ensure that the cpu
-         * being offlined is not present in the affinity mask, it may be
-         * selected as the target CPU otherwise
-         */
-        affinity = cpu_online_mask;
         c = irq_data_get_irq_chip(d);
         if (!c->irq_set_affinity)
                 pr_debug("IRQ%u: unable to set affinity\n", d->irq);
-        else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
+        else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
                 cpumask_copy(d->affinity, affinity);
 
         return ret;
diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c
index 75c9cf1aafee..a0d10c55f307 100644
--- a/arch/arm64/kernel/kgdb.c
+++ b/arch/arm64/kernel/kgdb.c
@@ -235,13 +235,13 @@ static int kgdb_step_brk_fn(struct pt_regs *regs, unsigned int esr)
 
 static struct break_hook kgdb_brkpt_hook = {
         .esr_mask       = 0xffffffff,
-        .esr_val        = DBG_ESR_VAL_BRK(KGDB_DYN_DGB_BRK_IMM),
+        .esr_val        = DBG_ESR_VAL_BRK(KGDB_DYN_DBG_BRK_IMM),
         .fn             = kgdb_brk_fn
 };
 
 static struct break_hook kgdb_compiled_brkpt_hook = {
         .esr_mask       = 0xffffffff,
-        .esr_val        = DBG_ESR_VAL_BRK(KDBG_COMPILED_DBG_BRK_IMM),
+        .esr_val        = DBG_ESR_VAL_BRK(KGDB_COMPILED_DBG_BRK_IMM),
         .fn             = kgdb_compiled_brk_fn
 };
 
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
new file mode 100644
index 000000000000..ce5836c14ec1
--- /dev/null
+++ b/arch/arm64/kernel/pci.c
@@ -0,0 +1,70 @@
+/*
+ * Code borrowed from powerpc/kernel/pci-common.c
+ *
+ * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+
+#include <asm/pci-bridge.h>
+
+/*
+ * Called after each bus is probed, but before its children are examined
+ */
+void pcibios_fixup_bus(struct pci_bus *bus)
+{
+        /* nothing to do, expected to be removed in the future */
+}
+
+/*
+ * We don't have to worry about legacy ISA devices, so nothing to do here
+ */
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
+{
+        return res->start;
+}
+
+/*
+ * Try to assign the IRQ number from DT when adding a new device
+ */
+int pcibios_add_device(struct pci_dev *dev)
+{
+        dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+
+        return 0;
+}
+
+
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+static bool dt_domain_found = false;
+
+void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
+{
+        int domain = of_get_pci_domain_nr(parent->of_node);
+
+        if (domain >= 0) {
+                dt_domain_found = true;
+        } else if (dt_domain_found == true) {
+                dev_err(parent, "Node %s is missing \"linux,pci-domain\" property in DT\n",
+                        parent->of_node->full_name);
+                return;
+        } else {
+                domain = pci_get_new_domain_nr();
+        }
+
+        bus->domain_nr = domain;
+}
+#endif
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index baf5afb7e6a0..aa29ecb4f800 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1276,7 +1276,7 @@ arch_initcall(cpu_pmu_reset);
 /*
  * PMU platform driver and devicetree bindings.
  */
-static struct of_device_id armpmu_of_device_ids[] = {
+static const struct of_device_id armpmu_of_device_ids[] = {
         {.compatible = "arm,armv8-pmuv3"},
         {},
 };
diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c
index 422ebd63b619..6762ad705587 100644
--- a/arch/arm64/kernel/perf_regs.c
+++ b/arch/arm64/kernel/perf_regs.c
@@ -24,6 +24,12 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
                         return regs->compat_lr;
         }
 
+        if ((u32)idx == PERF_REG_ARM64_SP)
+                return regs->sp;
+
+        if ((u32)idx == PERF_REG_ARM64_PC)
+                return regs->pc;
+
         return regs->regs[idx];
 }
 
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 1309d64aa926..89f41f7d27dd 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -57,36 +57,10 @@ unsigned long __stack_chk_guard __read_mostly;
 EXPORT_SYMBOL(__stack_chk_guard);
 #endif
 
-static void setup_restart(void)
-{
-        /*
-         * Tell the mm system that we are going to reboot -
-         * we may need it to insert some 1:1 mappings so that
-         * soft boot works.
-         */
-        setup_mm_for_reboot();
-
-        /* Clean and invalidate caches */
-        flush_cache_all();
-
-        /* Turn D-cache off */
-        cpu_cache_off();
-
-        /* Push out any further dirty data, and ensure cache is empty */
-        flush_cache_all();
-}
-
 void soft_restart(unsigned long addr)
 {
-        typedef void (*phys_reset_t)(unsigned long);
-        phys_reset_t phys_reset;
-
-        setup_restart();
-
-        /* Switch to the identity mapping */
-        phys_reset = (phys_reset_t)virt_to_phys(cpu_reset);
-        phys_reset(addr);
-
+        setup_mm_for_reboot();
+        cpu_soft_restart(virt_to_phys(cpu_reset), addr);
         /* Should never get here */
         BUG();
 }
@@ -230,9 +204,27 @@ void exit_thread(void)
 {
 }
 
+static void tls_thread_flush(void)
+{
+        asm ("msr tpidr_el0, xzr");
+
+        if (is_compat_task()) {
+                current->thread.tp_value = 0;
+
+                /*
+                 * We need to ensure ordering between the shadow state and the
+                 * hardware state, so that we don't corrupt the hardware state
+                 * with a stale shadow state during context switch.
+                 */
+                barrier();
+                asm ("msr tpidrro_el0, xzr");
+        }
+}
+
 void flush_thread(void)
 {
         fpsimd_flush_thread();
+        tls_thread_flush();
         flush_ptrace_hw_breakpoint(current);
 }
 
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index 553954771a67..866c1c821860 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -21,6 +21,7 @@
 #include <linux/reboot.h>
 #include <linux/pm.h>
 #include <linux/delay.h>
+#include <linux/slab.h>
 #include <uapi/linux/psci.h>
 
 #include <asm/compiler.h>
@@ -28,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/psci.h>
 #include <asm/smp_plat.h>
+#include <asm/suspend.h>
 #include <asm/system_misc.h>
 
 #define PSCI_POWER_STATE_TYPE_STANDBY           0
@@ -65,6 +67,8 @@ enum psci_function {
         PSCI_FN_MAX,
 };
 
+static DEFINE_PER_CPU_READ_MOSTLY(struct psci_power_state *, psci_power_state);
+
 static u32 psci_function_id[PSCI_FN_MAX];
 
 static int psci_to_linux_errno(int errno)
@@ -93,6 +97,18 @@ static u32 psci_power_state_pack(struct psci_power_state state)
                  & PSCI_0_2_POWER_STATE_AFFL_MASK);
 }
 
+static void psci_power_state_unpack(u32 power_state,
+                                    struct psci_power_state *state)
+{
+        state->id = (power_state & PSCI_0_2_POWER_STATE_ID_MASK) >>
+                        PSCI_0_2_POWER_STATE_ID_SHIFT;
+        state->type = (power_state & PSCI_0_2_POWER_STATE_TYPE_MASK) >>
+                        PSCI_0_2_POWER_STATE_TYPE_SHIFT;
+        state->affinity_level =
+                        (power_state & PSCI_0_2_POWER_STATE_AFFL_MASK) >>
+                        PSCI_0_2_POWER_STATE_AFFL_SHIFT;
+}
+
 /*
  * The following two functions are invoked via the invoke_psci_fn pointer
  * and will not be inlined, allowing us to piggyback on the AAPCS.
@@ -199,6 +215,63 @@ static int psci_migrate_info_type(void)
         return err;
 }
 
+static int __maybe_unused cpu_psci_cpu_init_idle(struct device_node *cpu_node,
+                                                 unsigned int cpu)
+{
+        int i, ret, count = 0;
+        struct psci_power_state *psci_states;
+        struct device_node *state_node;
+
+        /*
+         * If the PSCI cpu_suspend function hook has not been initialized
+         * idle states must not be enabled, so bail out
+         */
+        if (!psci_ops.cpu_suspend)
+                return -EOPNOTSUPP;
+
+        /* Count idle states */
+        while ((state_node = of_parse_phandle(cpu_node, "cpu-idle-states",
+                                              count))) {
+                count++;
+                of_node_put(state_node);
+        }
+
+        if (!count)
+                return -ENODEV;
+
+        psci_states = kcalloc(count, sizeof(*psci_states), GFP_KERNEL);
+        if (!psci_states)
+                return -ENOMEM;
+
+        for (i = 0; i < count; i++) {
+                u32 psci_power_state;
+
+                state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+
+                ret = of_property_read_u32(state_node,
+                                           "arm,psci-suspend-param",
+                                           &psci_power_state);
+                if (ret) {
+                        pr_warn(" * %s missing arm,psci-suspend-param property\n",
+                                state_node->full_name);
+                        of_node_put(state_node);
+                        goto free_mem;
+                }
+
+                of_node_put(state_node);
+                pr_debug("psci-power-state %#x index %d\n", psci_power_state,
+                                                            i);
+                psci_power_state_unpack(psci_power_state, &psci_states[i]);
+        }
+        /* Idle states parsed correctly, initialize per-cpu pointer */
+        per_cpu(psci_power_state, cpu) = psci_states;
+        return 0;
+
+free_mem:
+        kfree(psci_states);
+        return ret;
+}
+
 static int get_set_conduit_method(struct device_node *np)
 {
         const char *method;
@@ -436,8 +509,39 @@ static int cpu_psci_cpu_kill(unsigned int cpu)
 #endif
 #endif
 
+static int psci_suspend_finisher(unsigned long index)
+{
+        struct psci_power_state *state = __get_cpu_var(psci_power_state);
+
+        return psci_ops.cpu_suspend(state[index - 1],
+                                    virt_to_phys(cpu_resume));
+}
+
+static int __maybe_unused cpu_psci_cpu_suspend(unsigned long index)
+{
+        int ret;
+        struct psci_power_state *state = __get_cpu_var(psci_power_state);
+        /*
+         * idle state index 0 corresponds to wfi, should never be called
+         * from the cpu_suspend operations
+         */
+        if (WARN_ON_ONCE(!index))
+                return -EINVAL;
+
+        if (state->type == PSCI_POWER_STATE_TYPE_STANDBY)
+                ret = psci_ops.cpu_suspend(state[index - 1], 0);
+        else
+                ret = __cpu_suspend(index, psci_suspend_finisher);
+
+        return ret;
+}
+
 const struct cpu_operations cpu_psci_ops = {
         .name           = "psci",
+#ifdef CONFIG_CPU_IDLE
+        .cpu_init_idle  = cpu_psci_cpu_init_idle,
+        .cpu_suspend    = cpu_psci_cpu_suspend,
+#endif
 #ifdef CONFIG_SMP
         .cpu_init       = cpu_psci_cpu_init,
         .cpu_prepare    = cpu_psci_cpu_prepare,
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 0310811bd77d..fe63ac5e9bf5 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -87,7 +87,8 @@ static void ptrace_hbptriggered(struct perf_event *bp,
                         break;
                 }
         }
-        for (i = ARM_MAX_BRP; i < ARM_MAX_HBP_SLOTS && !bp; ++i) {
+
+        for (i = 0; i < ARM_MAX_WRP; ++i) {
                 if (current->thread.debug.hbp_watch[i] == bp) {
                         info.si_errno = -((i << 1) + 1);
                         break;
@@ -662,8 +663,10 @@ static int compat_gpr_get(struct task_struct *target,
                         kbuf += sizeof(reg);
                 } else {
                         ret = copy_to_user(ubuf, &reg, sizeof(reg));
-                        if (ret)
+                        if (ret) {
+                                ret = -EFAULT;
                                 break;
+                        }
 
                         ubuf += sizeof(reg);
                 }
@@ -701,8 +704,10 @@ static int compat_gpr_set(struct task_struct *target,
                         kbuf += sizeof(reg);
                 } else {
                         ret = copy_from_user(&reg, ubuf, sizeof(reg));
-                        if (ret)
-                                return ret;
+                        if (ret) {
+                                ret = -EFAULT;
+                                break;
+                        }
 
                         ubuf += sizeof(reg);
                 }
@@ -1115,19 +1120,15 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs)
         if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
                 trace_sys_enter(regs, regs->syscallno);
 
-#ifdef CONFIG_AUDITSYSCALL
         audit_syscall_entry(syscall_get_arch(), regs->syscallno,
                 regs->orig_x0, regs->regs[1], regs->regs[2], regs->regs[3]);
-#endif
 
         return regs->syscallno;
 }
 
 asmlinkage void syscall_trace_exit(struct pt_regs *regs)
 {
-#ifdef CONFIG_AUDITSYSCALL
         audit_syscall_exit(regs);
-#endif
 
         if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
                 trace_sys_exit(regs, regs_return_value(regs));
diff --git a/arch/arm64/kernel/return_address.c b/arch/arm64/kernel/return_address.c
index 89102a6ffad5..6c4fd2810ecb 100644
--- a/arch/arm64/kernel/return_address.c
+++ b/arch/arm64/kernel/return_address.c
@@ -36,13 +36,12 @@ void *return_address(unsigned int level)
 {
         struct return_address_data data;
         struct stackframe frame;
-        register unsigned long current_sp asm ("sp");
 
         data.level = level + 2;
         data.addr = NULL;
 
         frame.fp = (unsigned long)__builtin_frame_address(0);
-        frame.sp = current_sp;
+        frame.sp = current_stack_pointer;
         frame.pc = (unsigned long)return_address; /* dummy */
 
         walk_stackframe(&frame, save_return_addr, &data);
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index f6f0ccf35ae6..2437196cc5d4 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -78,6 +78,7 @@ unsigned int compat_elf_hwcap2 __read_mostly;
 #endif
 
 static const char *cpu_name;
+static const char *machine_name;
 phys_addr_t __fdt_pointer __initdata;
 
 /*
@@ -309,6 +310,8 @@ static void __init setup_machine_fdt(phys_addr_t dt_phys)
                 while (true)
                         cpu_relax();
         }
+
+        machine_name = of_flat_dt_get_machine_name();
 }
 
 /*
@@ -362,11 +365,6 @@ u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 
 void __init setup_arch(char **cmdline_p)
 {
-        /*
-         * Unmask asynchronous aborts early to catch possible system errors.
-         */
-        local_async_enable();
-
         setup_processor();
 
         setup_machine_fdt(__fdt_pointer);
@@ -382,6 +380,12 @@ void __init setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+        /*
+         *  Unmask asynchronous aborts after bringing up possible earlycon.
+         * (Report possible System Errors once we can report this occurred)
+         */
+        local_async_enable();
+
         efi_init();
         arm64_memblock_init();
 
@@ -447,21 +451,10 @@ static int c_show(struct seq_file *m, void *v)
 {
         int i;
 
-        /*
-         * Dump out the common processor features in a single line. Userspace
-         * should read the hwcaps with getauxval(AT_HWCAP) rather than
-         * attempting to parse this.
-         */
-        seq_puts(m, "features\t:");
-        for (i = 0; hwcap_str[i]; i++)
-                if (elf_hwcap & (1 << i))
-                        seq_printf(m, " %s", hwcap_str[i]);
-        seq_puts(m, "\n\n");
+        seq_printf(m, "Processor\t: %s rev %d (%s)\n",
+                   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
 
         for_each_online_cpu(i) {
-                struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
-                u32 midr = cpuinfo->reg_midr;
-
                 /*
                  * glibc reads /proc/cpuinfo to determine the number of
                  * online processors, looking for lines beginning with
@@ -470,13 +463,25 @@ static int c_show(struct seq_file *m, void *v)
 #ifdef CONFIG_SMP
                 seq_printf(m, "processor\t: %d\n", i);
 #endif
-                seq_printf(m, "implementer\t: 0x%02x\n",
-                           MIDR_IMPLEMENTOR(midr));
-                seq_printf(m, "variant\t\t: 0x%x\n", MIDR_VARIANT(midr));
-                seq_printf(m, "partnum\t\t: 0x%03x\n", MIDR_PARTNUM(midr));
-                seq_printf(m, "revision\t: 0x%x\n\n", MIDR_REVISION(midr));
         }
 
+        /* dump out the processor features */
+        seq_puts(m, "Features\t: ");
+
+        for (i = 0; hwcap_str[i]; i++)
+                if (elf_hwcap & (1 << i))
+                        seq_printf(m, "%s ", hwcap_str[i]);
+
+        seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
+        seq_printf(m, "CPU architecture: AArch64\n");
+        seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
+        seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
+        seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
+
+        seq_puts(m, "\n");
+
+        seq_printf(m, "Hardware\t: %s\n", machine_name);
+
         return 0;
 }
 
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S
index b1925729c692..a564b440416a 100644
--- a/arch/arm64/kernel/sleep.S
+++ b/arch/arm64/kernel/sleep.S
@@ -49,28 +49,39 @@
         orr     \dst, \dst, \mask               // dst|=(aff3>>rs3)
         .endm
 /*
- * Save CPU state for a suspend.  This saves callee registers, and allocates
- * space on the kernel stack to save the CPU specific registers + some
- * other data for resume.
+ * Save CPU state for a suspend and execute the suspend finisher.
+ * On success it will return 0 through cpu_resume - ie through a CPU
+ * soft/hard reboot from the reset vector.
+ * On failure it returns the suspend finisher return value or force
+ * -EOPNOTSUPP if the finisher erroneously returns 0 (the suspend finisher
+ * is not allowed to return, if it does this must be considered failure).
+ * It saves callee registers, and allocates space on the kernel stack
+ * to save the CPU specific registers + some other data for resume.
  *
  *  x0 = suspend finisher argument
+ *  x1 = suspend finisher function pointer
  */
-ENTRY(__cpu_suspend)
+ENTRY(__cpu_suspend_enter)
         stp     x29, lr, [sp, #-96]!
         stp     x19, x20, [sp,#16]
         stp     x21, x22, [sp,#32]
         stp     x23, x24, [sp,#48]
         stp     x25, x26, [sp,#64]
         stp     x27, x28, [sp,#80]
+        /*
+         * Stash suspend finisher and its argument in x20 and x19
+         */
+        mov     x19, x0
+        mov     x20, x1
         mov     x2, sp
         sub     sp, sp, #CPU_SUSPEND_SZ // allocate cpu_suspend_ctx
-        mov     x1, sp
+        mov     x0, sp
         /*
-         * x1 now points to struct cpu_suspend_ctx allocated on the stack
+         * x0 now points to struct cpu_suspend_ctx allocated on the stack
          */
-        str     x2, [x1, #CPU_CTX_SP]
-        ldr     x2, =sleep_save_sp
-        ldr     x2, [x2, #SLEEP_SAVE_SP_VIRT]
+        str     x2, [x0, #CPU_CTX_SP]
+        ldr     x1, =sleep_save_sp
+        ldr     x1, [x1, #SLEEP_SAVE_SP_VIRT]
 #ifdef CONFIG_SMP
         mrs     x7, mpidr_el1
         ldr     x9, =mpidr_hash
@@ -82,11 +93,21 @@ ENTRY(__cpu_suspend)
         ldp     w3, w4, [x9, #MPIDR_HASH_SHIFTS]
         ldp     w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)]
         compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10
-        add     x2, x2, x8, lsl #3
+        add     x1, x1, x8, lsl #3
 #endif
-        bl      __cpu_suspend_finisher
+        bl      __cpu_suspend_save
+        /*
+         * Grab suspend finisher in x20 and its argument in x19
+         */
+        mov     x0, x19
+        mov     x1, x20
+        /*
+         * We are ready for power down, fire off the suspend finisher
+         * in x1, with argument in x0
+         */
+        blr     x1
         /*
-         * Never gets here, unless suspend fails.
+         * Never gets here, unless suspend finisher fails.
          * Successful cpu_suspend should return from cpu_resume, returning
          * through this code path is considered an error
          * If the return value is set to 0 force x0 = -EOPNOTSUPP
@@ -103,7 +124,7 @@ ENTRY(__cpu_suspend)
         ldp     x27, x28, [sp, #80]
         ldp     x29, lr, [sp], #96
         ret
-ENDPROC(__cpu_suspend)
+ENDPROC(__cpu_suspend_enter)
         .ltorg
 
 /*
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 474339718105..b06d1d90ee8c 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -470,7 +470,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         }
 }
 
-static void (*__smp_cross_call)(const struct cpumask *, unsigned int);
+void (*__smp_cross_call)(const struct cpumask *, unsigned int);
 
 void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
 {
diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c
index 0347d38eea29..4f93c67e63de 100644
--- a/arch/arm64/kernel/smp_spin_table.c
+++ b/arch/arm64/kernel/smp_spin_table.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/smp.h>
+#include <linux/types.h>
 
 #include <asm/cacheflush.h>
 #include <asm/cpu_ops.h>
@@ -65,12 +66,21 @@ static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu)
 
 static int smp_spin_table_cpu_prepare(unsigned int cpu)
 {
-        void **release_addr;
+        __le64 __iomem *release_addr;
 
         if (!cpu_release_addr[cpu])
                 return -ENODEV;
 
-        release_addr = __va(cpu_release_addr[cpu]);
+        /*
+         * The cpu-release-addr may or may not be inside the linear mapping.
+         * As ioremap_cache will either give us a new mapping or reuse the
+         * existing linear mapping, we can use it to cover both cases. In
+         * either case the memory will be MT_NORMAL.
+         */
+        release_addr = ioremap_cache(cpu_release_addr[cpu],
+                                     sizeof(*release_addr));
+        if (!release_addr)
+                return -ENOMEM;
 
         /*
          * We write the release address as LE regardless of the native
@@ -79,15 +89,17 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu)
          * boot-loader's endianess before jumping. This is mandated by
          * the boot protocol.
          */
-        release_addr[0] = (void *) cpu_to_le64(__pa(secondary_holding_pen));
-
-        __flush_dcache_area(release_addr, sizeof(release_addr[0]));
+        writeq_relaxed(__pa(secondary_holding_pen), release_addr);
+        __flush_dcache_area((__force void *)release_addr,
+                            sizeof(*release_addr));
 
         /*
          * Send an event to wake up the secondary CPU.
          */
         sev();
 
+        iounmap(release_addr);
+
         return 0;
 }
 
diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c
index 55437ba1f5a4..407991bf79f5 100644
--- a/arch/arm64/kernel/stacktrace.c
+++ b/arch/arm64/kernel/stacktrace.c
@@ -111,10 +111,9 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
                 frame.sp = thread_saved_sp(tsk);
                 frame.pc = thread_saved_pc(tsk);
         } else {
-                register unsigned long current_sp asm("sp");
                 data.no_sched_functions = 0;
                 frame.fp = (unsigned long)__builtin_frame_address(0);
-                frame.sp = current_sp;
+                frame.sp = current_stack_pointer;
                 frame.pc = (unsigned long)save_stack_trace_tsk;
         }
 
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
index 55a99b9a97e0..13ad4dbb1615 100644
--- a/arch/arm64/kernel/suspend.c
+++ b/arch/arm64/kernel/suspend.c
@@ -9,22 +9,19 @@
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 
-extern int __cpu_suspend(unsigned long);
+extern int __cpu_suspend_enter(unsigned long arg, int (*fn)(unsigned long));
 /*
- * This is called by __cpu_suspend() to save the state, and do whatever
+ * This is called by __cpu_suspend_enter() to save the state, and do whatever
  * flushing is required to ensure that when the CPU goes to sleep we have
  * the necessary data available when the caches are not searched.
  *
- * @arg: Argument to pass to suspend operations
- * @ptr: CPU context virtual address
- * @save_ptr: address of the location where the context physical address
- *            must be saved
+ * ptr: CPU context virtual address
+ * save_ptr: address of the location where the context physical address
+ *           must be saved
  */
-int __cpu_suspend_finisher(unsigned long arg, struct cpu_suspend_ctx *ptr,
-                           phys_addr_t *save_ptr)
+void notrace __cpu_suspend_save(struct cpu_suspend_ctx *ptr,
+                                phys_addr_t *save_ptr)
 {
-        int cpu = smp_processor_id();
-
         *save_ptr = virt_to_phys(ptr);
 
         cpu_do_suspend(ptr);
@@ -35,8 +32,6 @@ int __cpu_suspend_finisher(unsigned long arg, struct cpu_suspend_ctx *ptr,
          */
         __flush_dcache_area(ptr, sizeof(*ptr));
         __flush_dcache_area(save_ptr, sizeof(*save_ptr));
-
-        return cpu_ops[cpu]->cpu_suspend(arg);
 }
 
 /*
@@ -56,15 +51,15 @@ void __init cpu_suspend_set_dbg_restorer(void (*hw_bp_restore)(void *))
 }
 
 /**
- * cpu_suspend
+ * cpu_suspend() - function to enter a low-power state
+ * @arg: argument to pass to CPU suspend operations
  *
- * @arg: argument to pass to the finisher function
+ * Return: 0 on success, -EOPNOTSUPP if CPU suspend hook not initialized, CPU
+ * operations back-end error code otherwise.
  */
 int cpu_suspend(unsigned long arg)
 {
-        struct mm_struct *mm = current->active_mm;
-        int ret, cpu = smp_processor_id();
-        unsigned long flags;
+        int cpu = smp_processor_id();
 
         /*
          * If cpu_ops have not been registered or suspend
@@ -72,6 +67,21 @@ int cpu_suspend(unsigned long arg)
          */
         if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_suspend)
                 return -EOPNOTSUPP;
+        return cpu_ops[cpu]->cpu_suspend(arg);
+}
+
+/*
+ * __cpu_suspend
+ *
+ * arg: argument to pass to the finisher function
+ * fn: finisher function pointer
+ *
+ */
+int __cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        struct mm_struct *mm = current->active_mm;
+        int ret;
+        unsigned long flags;
 
         /*
          * From this point debug exceptions are disabled to prevent
@@ -86,7 +96,7 @@ int cpu_suspend(unsigned long arg)
          * page tables, so that the thread address space is properly
          * set-up on function return.
          */
-        ret = __cpu_suspend(arg);
+        ret = __cpu_suspend_enter(arg, fn);
         if (ret == 0) {
                 cpu_switch_mm(mm->pgd, mm);
                 flush_tlb_all();
@@ -95,7 +105,7 @@ int cpu_suspend(unsigned long arg)
                  * Restore per-cpu offset before any kernel
                  * subsystem relying on it has a chance to run.
                  */
-                set_my_cpu_offset(per_cpu_offset(cpu));
+                set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
 
                 /*
                  * Restore HW breakpoint registers to sane values
diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
index de2b0226e06d..dc47e53e9e28 100644
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -79,6 +79,12 @@ long compat_arm_syscall(struct pt_regs *regs)
 
         case __ARM_NR_compat_set_tls:
                 current->thread.tp_value = regs->regs[0];
+
+                /*
+                 * Protect against register corruption from context switch.
+                 * See comment in tls_thread_flush.
+                 */
+                barrier();
                 asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
                 return 0;
 
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 02cd3f023e9a..de1b085e7963 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -132,7 +132,6 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
 static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
 {
         struct stackframe frame;
-        const register unsigned long current_sp asm ("sp");
 
         pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
 
@@ -145,7 +144,7 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
                 frame.pc = regs->pc;
         } else if (tsk == current) {
                 frame.fp = (unsigned long)__builtin_frame_address(0);
-                frame.sp = current_sp;
+                frame.sp = current_stack_pointer;
                 frame.pc = (unsigned long)dump_backtrace;
         } else {
                 /*
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 97f0c0429dfa..edf8715ba39b 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -97,9 +97,9 @@ SECTIONS
 
         PERCPU_SECTION(64)
 
+        . = ALIGN(PAGE_SIZE);
         __init_end = .;
 
-        . = ALIGN(PAGE_SIZE);
         _data = .;
         _sdata = .;
         RW_DATA_SECTION(64, PAGE_SIZE, THREAD_SIZE)
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index 8d1ec2887a26..76794692c20b 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -174,7 +174,7 @@ static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 
         ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
         if (ret != 0)
-                return ret;
+                return -EFAULT;
 
         return kvm_arm_timer_set_reg(vcpu, reg->id, val);
 }
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index e28be510380c..34b8bd0711e9 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -66,6 +66,8 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
         else
                 kvm_vcpu_block(vcpu);
 
+        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+
         return 1;
 }
 
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index d968796f4b2d..c3191168a994 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -80,6 +80,10 @@ __do_hyp_init:
         msr     mair_el2, x4
         isb
 
+        /* Invalidate the stale TLBs from Bootloader */
+        tlbi    alle2
+        dsb     sy
+
         mrs     x4, sctlr_el2
         and     x4, x4, #SCTLR_EL2_EE   // preserve endianness of EL2
         ldr     x5, =SCTLR_EL2_FLAGS
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 5805e7c4a4dd..4cc3b719208e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1218,7 +1218,7 @@ static bool is_valid_cache(u32 val)
         u32 level, ctype;
 
         if (val >= CSSELR_MAX)
-                return -ENOENT;
+                return false;
 
         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
         level = (val >> 1);
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
index 3ecb56c624d3..c56179ed2c09 100644
--- a/arch/arm64/mm/Makefile
+++ b/arch/arm64/mm/Makefile
@@ -1,5 +1,5 @@
 obj-y                           := dma-mapping.o extable.o fault.o init.o \
                                    cache.o copypage.o flush.o \
                                    ioremap.o mmap.o pgd.o mmu.o \
-                                   context.o proc.o
+                                   context.o proc.o pageattr.o
 obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 4164c5ace9f8..d92094203913 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -20,13 +20,11 @@
 #include <linux/gfp.h>
 #include <linux/export.h>
 #include <linux/slab.h>
+#include <linux/genalloc.h>
 #include <linux/dma-mapping.h>
 #include <linux/dma-contiguous.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
 #include <linux/vmalloc.h>
 #include <linux/swiotlb.h>
-#include <linux/amba/bus.h>
 
 #include <asm/cacheflush.h>
 
@@ -41,6 +39,54 @@ static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot,
         return prot;
 }
 
+static struct gen_pool *atomic_pool;
+
+#define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_256K
+static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
+
+static int __init early_coherent_pool(char *p)
+{
+        atomic_pool_size = memparse(p, &p);
+        return 0;
+}
+early_param("coherent_pool", early_coherent_pool);
+
+static void *__alloc_from_pool(size_t size, struct page **ret_page)
+{
+        unsigned long val;
+        void *ptr = NULL;
+
+        if (!atomic_pool) {
+                WARN(1, "coherent pool not initialised!\n");
+                return NULL;
+        }
+
+        val = gen_pool_alloc(atomic_pool, size);
+        if (val) {
+                phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
+
+                *ret_page = phys_to_page(phys);
+                ptr = (void *)val;
+        }
+
+        return ptr;
+}
+
+static bool __in_atomic_pool(void *start, size_t size)
+{
+        return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
+}
+
+static int __free_from_pool(void *start, size_t size)
+{
+        if (!__in_atomic_pool(start, size))
+                return 0;
+
+        gen_pool_free(atomic_pool, (unsigned long)start, size);
+
+        return 1;
+}
+
 static void *__dma_alloc_coherent(struct device *dev, size_t size,
                                   dma_addr_t *dma_handle, gfp_t flags,
                                   struct dma_attrs *attrs)
@@ -53,7 +99,7 @@ static void *__dma_alloc_coherent(struct device *dev, size_t size,
         if (IS_ENABLED(CONFIG_ZONE_DMA) &&
             dev->coherent_dma_mask <= DMA_BIT_MASK(32))
                 flags |= GFP_DMA;
-        if (IS_ENABLED(CONFIG_DMA_CMA)) {
+        if (IS_ENABLED(CONFIG_DMA_CMA) && (flags & __GFP_WAIT)) {
                 struct page *page;
 
                 size = PAGE_ALIGN(size);
@@ -73,50 +119,54 @@ static void __dma_free_coherent(struct device *dev, size_t size,
                                 void *vaddr, dma_addr_t dma_handle,
                                 struct dma_attrs *attrs)
 {
+        bool freed;
+        phys_addr_t paddr = dma_to_phys(dev, dma_handle);
+
         if (dev == NULL) {
                 WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
                 return;
         }
 
-        if (IS_ENABLED(CONFIG_DMA_CMA)) {
-                phys_addr_t paddr = dma_to_phys(dev, dma_handle);
-
-                dma_release_from_contiguous(dev,
+        freed = dma_release_from_contiguous(dev,
                                         phys_to_page(paddr),
                                         size >> PAGE_SHIFT);
-        } else {
+        if (!freed)
                 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
-        }
 }
 
 static void *__dma_alloc_noncoherent(struct device *dev, size_t size,
                                      dma_addr_t *dma_handle, gfp_t flags,
                                      struct dma_attrs *attrs)
 {
-        struct page *page, **map;
+        struct page *page;
         void *ptr, *coherent_ptr;
-        int order, i;
 
         size = PAGE_ALIGN(size);
-        order = get_order(size);
+
+        if (!(flags & __GFP_WAIT)) {
+                struct page *page = NULL;
+                void *addr = __alloc_from_pool(size, &page);
+
+                if (addr)
+                        *dma_handle = phys_to_dma(dev, page_to_phys(page));
+
+                return addr;
+
+        }
 
         ptr = __dma_alloc_coherent(dev, size, dma_handle, flags, attrs);
         if (!ptr)
                 goto no_mem;
-        map = kmalloc(sizeof(struct page *) << order, flags & ~GFP_DMA);
-        if (!map)
-                goto no_map;
 
         /* remove any dirty cache lines on the kernel alias */
         __dma_flush_range(ptr, ptr + size);
 
         /* create a coherent mapping */
         page = virt_to_page(ptr);
-        for (i = 0; i < (size >> PAGE_SHIFT); i++)
-                map[i] = page + i;
-        coherent_ptr = vmap(map, size >> PAGE_SHIFT, VM_MAP,
-                            __get_dma_pgprot(attrs, __pgprot(PROT_NORMAL_NC), false));
-        kfree(map);
+        coherent_ptr = dma_common_contiguous_remap(page, size, VM_USERMAP,
+                                __get_dma_pgprot(attrs,
+                                        __pgprot(PROT_NORMAL_NC), false),
+                                        NULL);
         if (!coherent_ptr)
                 goto no_map;
 
@@ -125,7 +175,7 @@ static void *__dma_alloc_noncoherent(struct device *dev, size_t size,
 no_map:
         __dma_free_coherent(dev, size, ptr, *dma_handle, attrs);
 no_mem:
-        *dma_handle = ~0;
+        *dma_handle = DMA_ERROR_CODE;
         return NULL;
 }
 
@@ -135,6 +185,8 @@ static void __dma_free_noncoherent(struct device *dev, size_t size,
 {
         void *swiotlb_addr = phys_to_virt(dma_to_phys(dev, dma_handle));
 
+        if (__free_from_pool(vaddr, size))
+                return;
         vunmap(vaddr);
         __dma_free_coherent(dev, size, swiotlb_addr, dma_handle, attrs);
 }
@@ -308,45 +360,88 @@ struct dma_map_ops coherent_swiotlb_dma_ops = {
 };
 EXPORT_SYMBOL(coherent_swiotlb_dma_ops);
 
-static int dma_bus_notifier(struct notifier_block *nb,
-                            unsigned long event, void *_dev)
-{
-        struct device *dev = _dev;
-
-        if (event != BUS_NOTIFY_ADD_DEVICE)
-                return NOTIFY_DONE;
-
-        if (of_property_read_bool(dev->of_node, "dma-coherent"))
-                set_dma_ops(dev, &coherent_swiotlb_dma_ops);
+extern int swiotlb_late_init_with_default_size(size_t default_size);
 
-        return NOTIFY_OK;
+static int __init atomic_pool_init(void)
+{
+        pgprot_t prot = __pgprot(PROT_NORMAL_NC);
+        unsigned long nr_pages = atomic_pool_size >> PAGE_SHIFT;
+        struct page *page;
+        void *addr;
+        unsigned int pool_size_order = get_order(atomic_pool_size);
+
+        if (dev_get_cma_area(NULL))
+                page = dma_alloc_from_contiguous(NULL, nr_pages,
+                                                        pool_size_order);
+        else
+                page = alloc_pages(GFP_DMA, pool_size_order);
+
+        if (page) {
+                int ret;
+                void *page_addr = page_address(page);
+
+                memset(page_addr, 0, atomic_pool_size);
+                __dma_flush_range(page_addr, page_addr + atomic_pool_size);
+
+                atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
+                if (!atomic_pool)
+                        goto free_page;
+
+                addr = dma_common_contiguous_remap(page, atomic_pool_size,
+                                        VM_USERMAP, prot, atomic_pool_init);
+
+                if (!addr)
+                        goto destroy_genpool;
+
+                ret = gen_pool_add_virt(atomic_pool, (unsigned long)addr,
+                                        page_to_phys(page),
+                                        atomic_pool_size, -1);
+                if (ret)
+                        goto remove_mapping;
+
+                gen_pool_set_algo(atomic_pool,
+                                  gen_pool_first_fit_order_align,
+                                  (void *)PAGE_SHIFT);
+
+                pr_info("DMA: preallocated %zu KiB pool for atomic allocations\n",
+                        atomic_pool_size / 1024);
+                return 0;
+        }
+        goto out;
+
+remove_mapping:
+        dma_common_free_remap(addr, atomic_pool_size, VM_USERMAP);
+destroy_genpool:
+        gen_pool_destroy(atomic_pool);
+        atomic_pool = NULL;
+free_page:
+        if (!dma_release_from_contiguous(NULL, page, nr_pages))
+                __free_pages(page, pool_size_order);
+out:
+        pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
+                atomic_pool_size / 1024);
+        return -ENOMEM;
 }
 
-static struct notifier_block platform_bus_nb = {
-        .notifier_call = dma_bus_notifier,
-};
-
-static struct notifier_block amba_bus_nb = {
-        .notifier_call = dma_bus_notifier,
-};
-
-extern int swiotlb_late_init_with_default_size(size_t default_size);
-
 static int __init swiotlb_late_init(void)
 {
         size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT);
 
-        /*
-         * These must be registered before of_platform_populate().
-         */
-        bus_register_notifier(&platform_bus_type, &platform_bus_nb);
-        bus_register_notifier(&amba_bustype, &amba_bus_nb);
-
         dma_ops = &noncoherent_swiotlb_dma_ops;
 
         return swiotlb_late_init_with_default_size(swiotlb_size);
 }
-arch_initcall(swiotlb_late_init);
+
+static int __init arm64_dma_init(void)
+{
+        int ret = 0;
+
+        ret |= swiotlb_late_init();
+        ret |= atomic_pool_init();
+
+        return ret;
+}
+arch_initcall(arm64_dma_init);
 
 #define PREALLOC_DMA_DEBUG_ENTRIES      4096
 
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index 0d64089d28b5..b6f14e8d2121 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -104,3 +104,19 @@ EXPORT_SYMBOL(flush_dcache_page);
  */
 EXPORT_SYMBOL(flush_cache_all);
 EXPORT_SYMBOL(flush_icache_range);
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
+                          pmd_t *pmdp)
+{
+        pmd_t pmd = pmd_mksplitting(*pmdp);
+
+        VM_BUG_ON(address & ~PMD_MASK);
+        set_pmd_at(vma->vm_mm, address, pmdp, pmd);
+
+        /* dummy IPI to serialise against fast_gup */
+        kick_all_cpus_sync();
+}
+#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 5b4526ee3a01..494297c698ca 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -32,6 +32,7 @@
 #include <linux/of_fdt.h>
 #include <linux/dma-mapping.h>
 #include <linux/dma-contiguous.h>
+#include <linux/efi.h>
 
 #include <asm/fixmap.h>
 #include <asm/sections.h>
@@ -254,7 +255,7 @@ static void __init free_unused_memmap(void)
  */
 void __init mem_init(void)
 {
-        max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
+        set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
 
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
         free_unused_memmap();
@@ -332,8 +333,14 @@ static int keep_initrd;
 
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        if (!keep_initrd)
+        if (!keep_initrd) {
+                if (start == initrd_start)
+                        start = round_down(start, PAGE_SIZE);
+                if (end == initrd_end)
+                        end = round_up(end, PAGE_SIZE);
+
                 free_reserved_area((void *)start, (void *)end, 0, "initrd");
+        }
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/arm64/mm/mmap.c b/arch/arm64/mm/mmap.c
index 8ed6cb1a900f..1d73662f00ff 100644
--- a/arch/arm64/mm/mmap.c
+++ b/arch/arm64/mm/mmap.c
@@ -102,7 +102,7 @@ EXPORT_SYMBOL_GPL(arch_pick_mmap_layout);
  * You really shouldn't be using read() or write() on /dev/mem.  This might go
  * away in the future.
  */
-int valid_phys_addr_range(unsigned long addr, size_t size)
+int valid_phys_addr_range(phys_addr_t addr, size_t size)
 {
         if (addr < PHYS_OFFSET)
                 return 0;
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index c55567283cde..6894ef3e6234 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -94,7 +94,7 @@ static int __init early_cachepolicy(char *p)
          */
         asm volatile(
         "       mrs     %0, mair_el1\n"
-        "       bfi     %0, %1, #%2, #8\n"
+        "       bfi     %0, %1, %2, #8\n"
         "       msr     mair_el1, %0\n"
         "       isb\n"
         : "=&r" (tmp)
diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c
new file mode 100644
index 000000000000..bb0ea94c4ba1
--- /dev/null
+++ b/arch/arm64/mm/pageattr.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+
+struct page_change_data {
+        pgprot_t set_mask;
+        pgprot_t clear_mask;
+};
+
+static int change_page_range(pte_t *ptep, pgtable_t token, unsigned long addr,
+                        void *data)
+{
+        struct page_change_data *cdata = data;
+        pte_t pte = *ptep;
+
+        pte = clear_pte_bit(pte, cdata->clear_mask);
+        pte = set_pte_bit(pte, cdata->set_mask);
+
+        set_pte(ptep, pte);
+        return 0;
+}
+
+static int change_memory_common(unsigned long addr, int numpages,
+                                pgprot_t set_mask, pgprot_t clear_mask)
+{
+        unsigned long start = addr;
+        unsigned long size = PAGE_SIZE*numpages;
+        unsigned long end = start + size;
+        int ret;
+        struct page_change_data data;
+
+        if (!IS_ALIGNED(addr, PAGE_SIZE)) {
+                start &= PAGE_MASK;
+                end = start + size;
+                WARN_ON_ONCE(1);
+        }
+
+        if (!is_module_address(start) || !is_module_address(end - 1))
+                return -EINVAL;
+
+        data.set_mask = set_mask;
+        data.clear_mask = clear_mask;
+
+        ret = apply_to_page_range(&init_mm, start, size, change_page_range,
+                                        &data);
+
+        flush_tlb_kernel_range(start, end);
+        return ret;
+}
+
+int set_memory_ro(unsigned long addr, int numpages)
+{
+        return change_memory_common(addr, numpages,
+                                        __pgprot(PTE_RDONLY),
+                                        __pgprot(PTE_WRITE));
+}
+EXPORT_SYMBOL_GPL(set_memory_ro);
+
+int set_memory_rw(unsigned long addr, int numpages)
+{
+        return change_memory_common(addr, numpages,
+                                        __pgprot(PTE_WRITE),
+                                        __pgprot(PTE_RDONLY));
+}
+EXPORT_SYMBOL_GPL(set_memory_rw);
+
+int set_memory_nx(unsigned long addr, int numpages)
+{
+        return change_memory_common(addr, numpages,
+                                        __pgprot(PTE_PXN),
+                                        __pgprot(0));
+}
+EXPORT_SYMBOL_GPL(set_memory_nx);
+
+int set_memory_x(unsigned long addr, int numpages)
+{
+        return change_memory_common(addr, numpages,
+                                        __pgprot(0),
+                                        __pgprot(PTE_PXN));
+}
+EXPORT_SYMBOL_GPL(set_memory_x);
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 7736779c9809..4e778b13291b 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -76,6 +76,21 @@ ENTRY(cpu_reset)
         ret     x0
 ENDPROC(cpu_reset)
 
+ENTRY(cpu_soft_restart)
+        /* Save address of cpu_reset() and reset address */
+        mov     x19, x0
+        mov     x20, x1
+
+        /* Turn D-cache off */
+        bl      cpu_cache_off
+
+        /* Push out all dirty data, and ensure cache is empty */
+        bl      flush_cache_all
+
+        mov     x0, x20
+        ret     x19
+ENDPROC(cpu_soft_restart)
+
 /*
  *      cpu_do_idle()
  *
diff --git a/arch/arm64/net/Makefile b/arch/arm64/net/Makefile
new file mode 100644
index 000000000000..da9763378284
--- /dev/null
+++ b/arch/arm64/net/Makefile
@@ -0,0 +1,4 @@
+#
+# ARM64 networking code
+#
+obj-$(CONFIG_BPF_JIT) += bpf_jit_comp.o
diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
new file mode 100644
index 000000000000..2134f7e6c288
--- /dev/null
+++ b/arch/arm64/net/bpf_jit.h
@@ -0,0 +1,169 @@
+/*
+ * BPF JIT compiler for ARM64
+ *
+ * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _BPF_JIT_H
+#define _BPF_JIT_H
+
+#include <asm/insn.h>
+
+/* 5-bit Register Operand */
+#define A64_R(x)        AARCH64_INSN_REG_##x
+#define A64_FP          AARCH64_INSN_REG_FP
+#define A64_LR          AARCH64_INSN_REG_LR
+#define A64_ZR          AARCH64_INSN_REG_ZR
+#define A64_SP          AARCH64_INSN_REG_SP
+
+#define A64_VARIANT(sf) \
+        ((sf) ? AARCH64_INSN_VARIANT_64BIT : AARCH64_INSN_VARIANT_32BIT)
+
+/* Compare & branch (immediate) */
+#define A64_COMP_BRANCH(sf, Rt, offset, type) \
+        aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
+                AARCH64_INSN_BRANCH_COMP_##type)
+#define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO)
+
+/* Conditional branch (immediate) */
+#define A64_COND_BRANCH(cond, offset) \
+        aarch64_insn_gen_cond_branch_imm(0, offset, cond)
+#define A64_COND_EQ     AARCH64_INSN_COND_EQ /* == */
+#define A64_COND_NE     AARCH64_INSN_COND_NE /* != */
+#define A64_COND_CS     AARCH64_INSN_COND_CS /* unsigned >= */
+#define A64_COND_HI     AARCH64_INSN_COND_HI /* unsigned > */
+#define A64_COND_GE     AARCH64_INSN_COND_GE /* signed >= */
+#define A64_COND_GT     AARCH64_INSN_COND_GT /* signed > */
+#define A64_B_(cond, imm19) A64_COND_BRANCH(cond, (imm19) << 2)
+
+/* Unconditional branch (immediate) */
+#define A64_BRANCH(offset, type) aarch64_insn_gen_branch_imm(0, offset, \
+        AARCH64_INSN_BRANCH_##type)
+#define A64_B(imm26)  A64_BRANCH((imm26) << 2, NOLINK)
+#define A64_BL(imm26) A64_BRANCH((imm26) << 2, LINK)
+
+/* Unconditional branch (register) */
+#define A64_BLR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_LINK)
+#define A64_RET(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_RETURN)
+
+/* Load/store register (register offset) */
+#define A64_LS_REG(Rt, Rn, Rm, size, type) \
+        aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
+                AARCH64_INSN_SIZE_##size, \
+                AARCH64_INSN_LDST_##type##_REG_OFFSET)
+#define A64_STRB(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 8, STORE)
+#define A64_LDRB(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 8, LOAD)
+#define A64_STRH(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 16, STORE)
+#define A64_LDRH(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 16, LOAD)
+#define A64_STR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, STORE)
+#define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD)
+#define A64_STR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, STORE)
+#define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD)
+
+/* Load/store register pair */
+#define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \
+        aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
+                AARCH64_INSN_VARIANT_64BIT, \
+                AARCH64_INSN_LDST_##ls##_PAIR_##type)
+/* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
+#define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)
+/* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */
+#define A64_POP(Rt, Rt2, Rn)  A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)
+
+/* Add/subtract (immediate) */
+#define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \
+        aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
+                A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
+/* Rd = Rn OP imm12 */
+#define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
+#define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)
+/* Rd = Rn */
+#define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)
+
+/* Bitfield move */
+#define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \
+        aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
+                A64_VARIANT(sf), AARCH64_INSN_BITFIELD_MOVE_##type)
+/* Signed, with sign replication to left and zeros to right */
+#define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED)
+/* Unsigned, with zeros to left and right */
+#define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED)
+
+/* Rd = Rn << shift */
+#define A64_LSL(sf, Rd, Rn, shift) ({   \
+        int sz = (sf) ? 64 : 32;        \
+        A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
+})
+/* Rd = Rn >> shift */
+#define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
+/* Rd = Rn >> shift; signed */
+#define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
+
+/* Move wide (immediate) */
+#define A64_MOVEW(sf, Rd, imm16, shift, type) \
+        aarch64_insn_gen_movewide(Rd, imm16, shift, \
+                A64_VARIANT(sf), AARCH64_INSN_MOVEWIDE_##type)
+/* Rd = Zeros (for MOVZ);
+ * Rd |= imm16 << shift (where shift is {0, 16, 32, 48});
+ * Rd = ~Rd; (for MOVN); */
+#define A64_MOVN(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, INVERSE)
+#define A64_MOVZ(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, ZERO)
+#define A64_MOVK(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, KEEP)
+
+/* Add/subtract (shifted register) */
+#define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \
+        aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
+                A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
+/* Rd = Rn OP Rm */
+#define A64_ADD(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
+#define A64_SUB(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)
+#define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)
+/* Rd = -Rm */
+#define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)
+/* Rn - Rm; set condition flags */
+#define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)
+
+/* Data-processing (1 source) */
+#define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \
+        A64_VARIANT(sf), AARCH64_INSN_DATA1_##type)
+/* Rd = BSWAPx(Rn) */
+#define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16)
+#define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32)
+#define A64_REV64(Rd, Rn)     A64_DATA1(1, Rd, Rn, REVERSE_64)
+
+/* Data-processing (2 source) */
+/* Rd = Rn OP Rm */
+#define A64_UDIV(sf, Rd, Rn, Rm) aarch64_insn_gen_data2(Rd, Rn, Rm, \
+        A64_VARIANT(sf), AARCH64_INSN_DATA2_UDIV)
+
+/* Data-processing (3 source) */
+/* Rd = Ra + Rn * Rm */
+#define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
+        A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)
+/* Rd = Rn * Rm */
+#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
+
+/* Logical (shifted register) */
+#define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
+        aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
+                A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
+/* Rd = Rn OP Rm */
+#define A64_AND(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
+#define A64_ORR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
+#define A64_EOR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
+#define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)
+/* Rn & Rm; set condition flags */
+#define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
+
+#endif /* _BPF_JIT_H */
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
new file mode 100644
index 000000000000..7ae33545535b
--- /dev/null
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -0,0 +1,679 @@
+/*
+ * BPF JIT compiler for ARM64
+ *
+ * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt) "bpf_jit: " fmt
+
+#include <linux/filter.h>
+#include <linux/moduleloader.h>
+#include <linux/printk.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <asm/byteorder.h>
+#include <asm/cacheflush.h>
+
+#include "bpf_jit.h"
+
+int bpf_jit_enable __read_mostly;
+
+#define TMP_REG_1 (MAX_BPF_REG + 0)
+#define TMP_REG_2 (MAX_BPF_REG + 1)
+
+/* Map BPF registers to A64 registers */
+static const int bpf2a64[] = {
+        /* return value from in-kernel function, and exit value from eBPF */
+        [BPF_REG_0] = A64_R(7),
+        /* arguments from eBPF program to in-kernel function */
+        [BPF_REG_1] = A64_R(0),
+        [BPF_REG_2] = A64_R(1),
+        [BPF_REG_3] = A64_R(2),
+        [BPF_REG_4] = A64_R(3),
+        [BPF_REG_5] = A64_R(4),
+        /* callee saved registers that in-kernel function will preserve */
+        [BPF_REG_6] = A64_R(19),
+        [BPF_REG_7] = A64_R(20),
+        [BPF_REG_8] = A64_R(21),
+        [BPF_REG_9] = A64_R(22),
+        /* read-only frame pointer to access stack */
+        [BPF_REG_FP] = A64_FP,
+        /* temporary register for internal BPF JIT */
+        [TMP_REG_1] = A64_R(23),
+        [TMP_REG_2] = A64_R(24),
+};
+
+struct jit_ctx {
+        const struct bpf_prog *prog;
+        int idx;
+        int tmp_used;
+        int body_offset;
+        int *offset;
+        u32 *image;
+};
+
+static inline void emit(const u32 insn, struct jit_ctx *ctx)
+{
+        if (ctx->image != NULL)
+                ctx->image[ctx->idx] = cpu_to_le32(insn);
+
+        ctx->idx++;
+}
+
+static inline void emit_a64_mov_i64(const int reg, const u64 val,
+                                    struct jit_ctx *ctx)
+{
+        u64 tmp = val;
+        int shift = 0;
+
+        emit(A64_MOVZ(1, reg, tmp & 0xffff, shift), ctx);
+        tmp >>= 16;
+        shift += 16;
+        while (tmp) {
+                if (tmp & 0xffff)
+                        emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx);
+                tmp >>= 16;
+                shift += 16;
+        }
+}
+
+static inline void emit_a64_mov_i(const int is64, const int reg,
+                                  const s32 val, struct jit_ctx *ctx)
+{
+        u16 hi = val >> 16;
+        u16 lo = val & 0xffff;
+
+        if (hi & 0x8000) {
+                if (hi == 0xffff) {
+                        emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx);
+                } else {
+                        emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx);
+                        emit(A64_MOVK(is64, reg, lo, 0), ctx);
+                }
+        } else {
+                emit(A64_MOVZ(is64, reg, lo, 0), ctx);
+                if (hi)
+                        emit(A64_MOVK(is64, reg, hi, 16), ctx);
+        }
+}
+
+static inline int bpf2a64_offset(int bpf_to, int bpf_from,
+                                 const struct jit_ctx *ctx)
+{
+        int to = ctx->offset[bpf_to + 1];
+        /* -1 to account for the Branch instruction */
+        int from = ctx->offset[bpf_from + 1] - 1;
+
+        return to - from;
+}
+
+static inline int epilogue_offset(const struct jit_ctx *ctx)
+{
+        int to = ctx->offset[ctx->prog->len - 1];
+        int from = ctx->idx - ctx->body_offset;
+
+        return to - from;
+}
+
+/* Stack must be multiples of 16B */
+#define STACK_ALIGN(sz) (((sz) + 15) & ~15)
+
+static void build_prologue(struct jit_ctx *ctx)
+{
+        const u8 r6 = bpf2a64[BPF_REG_6];
+        const u8 r7 = bpf2a64[BPF_REG_7];
+        const u8 r8 = bpf2a64[BPF_REG_8];
+        const u8 r9 = bpf2a64[BPF_REG_9];
+        const u8 fp = bpf2a64[BPF_REG_FP];
+        const u8 ra = bpf2a64[BPF_REG_A];
+        const u8 rx = bpf2a64[BPF_REG_X];
+        const u8 tmp1 = bpf2a64[TMP_REG_1];
+        const u8 tmp2 = bpf2a64[TMP_REG_2];
+        int stack_size = MAX_BPF_STACK;
+
+        stack_size += 4; /* extra for skb_copy_bits buffer */
+        stack_size = STACK_ALIGN(stack_size);
+
+        /* Save callee-saved register */
+        emit(A64_PUSH(r6, r7, A64_SP), ctx);
+        emit(A64_PUSH(r8, r9, A64_SP), ctx);
+        if (ctx->tmp_used)
+                emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx);
+
+        /* Set up BPF stack */
+        emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx);
+
+        /* Set up frame pointer */
+        emit(A64_MOV(1, fp, A64_SP), ctx);
+
+        /* Clear registers A and X */
+        emit_a64_mov_i64(ra, 0, ctx);
+        emit_a64_mov_i64(rx, 0, ctx);
+}
+
+static void build_epilogue(struct jit_ctx *ctx)
+{
+        const u8 r0 = bpf2a64[BPF_REG_0];
+        const u8 r6 = bpf2a64[BPF_REG_6];
+        const u8 r7 = bpf2a64[BPF_REG_7];
+        const u8 r8 = bpf2a64[BPF_REG_8];
+        const u8 r9 = bpf2a64[BPF_REG_9];
+        const u8 fp = bpf2a64[BPF_REG_FP];
+        const u8 tmp1 = bpf2a64[TMP_REG_1];
+        const u8 tmp2 = bpf2a64[TMP_REG_2];
+        int stack_size = MAX_BPF_STACK;
+
+        stack_size += 4; /* extra for skb_copy_bits buffer */
+        stack_size = STACK_ALIGN(stack_size);
+
+        /* We're done with BPF stack */
+        emit(A64_ADD_I(1, A64_SP, A64_SP, stack_size), ctx);
+
+        /* Restore callee-saved register */
+        if (ctx->tmp_used)
+                emit(A64_POP(tmp1, tmp2, A64_SP), ctx);
+        emit(A64_POP(r8, r9, A64_SP), ctx);
+        emit(A64_POP(r6, r7, A64_SP), ctx);
+
+        /* Restore frame pointer */
+        emit(A64_MOV(1, fp, A64_SP), ctx);
+
+        /* Set return value */
+        emit(A64_MOV(1, A64_R(0), r0), ctx);
+
+        emit(A64_RET(A64_LR), ctx);
+}
+
+static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
+{
+        const u8 code = insn->code;
+        const u8 dst = bpf2a64[insn->dst_reg];
+        const u8 src = bpf2a64[insn->src_reg];
+        const u8 tmp = bpf2a64[TMP_REG_1];
+        const u8 tmp2 = bpf2a64[TMP_REG_2];
+        const s16 off = insn->off;
+        const s32 imm = insn->imm;
+        const int i = insn - ctx->prog->insnsi;
+        const bool is64 = BPF_CLASS(code) == BPF_ALU64;
+        u8 jmp_cond;
+        s32 jmp_offset;
+
+        switch (code) {
+        /* dst = src */
+        case BPF_ALU | BPF_MOV | BPF_X:
+        case BPF_ALU64 | BPF_MOV | BPF_X:
+                emit(A64_MOV(is64, dst, src), ctx);
+                break;
+        /* dst = dst OP src */
+        case BPF_ALU | BPF_ADD | BPF_X:
+        case BPF_ALU64 | BPF_ADD | BPF_X:
+                emit(A64_ADD(is64, dst, dst, src), ctx);
+                break;
+        case BPF_ALU | BPF_SUB | BPF_X:
+        case BPF_ALU64 | BPF_SUB | BPF_X:
+                emit(A64_SUB(is64, dst, dst, src), ctx);
+                break;
+        case BPF_ALU | BPF_AND | BPF_X:
+        case BPF_ALU64 | BPF_AND | BPF_X:
+                emit(A64_AND(is64, dst, dst, src), ctx);
+                break;
+        case BPF_ALU | BPF_OR | BPF_X:
+        case BPF_ALU64 | BPF_OR | BPF_X:
+                emit(A64_ORR(is64, dst, dst, src), ctx);
+                break;
+        case BPF_ALU | BPF_XOR | BPF_X:
+        case BPF_ALU64 | BPF_XOR | BPF_X:
+                emit(A64_EOR(is64, dst, dst, src), ctx);
+                break;
+        case BPF_ALU | BPF_MUL | BPF_X:
+        case BPF_ALU64 | BPF_MUL | BPF_X:
+                emit(A64_MUL(is64, dst, dst, src), ctx);
+                break;
+        case BPF_ALU | BPF_DIV | BPF_X:
+        case BPF_ALU64 | BPF_DIV | BPF_X:
+                emit(A64_UDIV(is64, dst, dst, src), ctx);
+                break;
+        case BPF_ALU | BPF_MOD | BPF_X:
+        case BPF_ALU64 | BPF_MOD | BPF_X:
+                ctx->tmp_used = 1;
+                emit(A64_UDIV(is64, tmp, dst, src), ctx);
+                emit(A64_MUL(is64, tmp, tmp, src), ctx);
+                emit(A64_SUB(is64, dst, dst, tmp), ctx);
+                break;
+        /* dst = -dst */
+        case BPF_ALU | BPF_NEG:
+        case BPF_ALU64 | BPF_NEG:
+                emit(A64_NEG(is64, dst, dst), ctx);
+                break;
+        /* dst = BSWAP##imm(dst) */
+        case BPF_ALU | BPF_END | BPF_FROM_LE:
+        case BPF_ALU | BPF_END | BPF_FROM_BE:
+#ifdef CONFIG_CPU_BIG_ENDIAN
+                if (BPF_SRC(code) == BPF_FROM_BE)
+                        break;
+#else /* !CONFIG_CPU_BIG_ENDIAN */
+                if (BPF_SRC(code) == BPF_FROM_LE)
+                        break;
+#endif
+                switch (imm) {
+                case 16:
+                        emit(A64_REV16(is64, dst, dst), ctx);
+                        break;
+                case 32:
+                        emit(A64_REV32(is64, dst, dst), ctx);
+                        break;
+                case 64:
+                        emit(A64_REV64(dst, dst), ctx);
+                        break;
+                }
+                break;
+        /* dst = imm */
+        case BPF_ALU | BPF_MOV | BPF_K:
+        case BPF_ALU64 | BPF_MOV | BPF_K:
+                emit_a64_mov_i(is64, dst, imm, ctx);
+                break;
+        /* dst = dst OP imm */
+        case BPF_ALU | BPF_ADD | BPF_K:
+        case BPF_ALU64 | BPF_ADD | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp, imm, ctx);
+                emit(A64_ADD(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_SUB | BPF_K:
+        case BPF_ALU64 | BPF_SUB | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp, imm, ctx);
+                emit(A64_SUB(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_AND | BPF_K:
+        case BPF_ALU64 | BPF_AND | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp, imm, ctx);
+                emit(A64_AND(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_OR | BPF_K:
+        case BPF_ALU64 | BPF_OR | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp, imm, ctx);
+                emit(A64_ORR(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_XOR | BPF_K:
+        case BPF_ALU64 | BPF_XOR | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp, imm, ctx);
+                emit(A64_EOR(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_MUL | BPF_K:
+        case BPF_ALU64 | BPF_MUL | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp, imm, ctx);
+                emit(A64_MUL(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_DIV | BPF_K:
+        case BPF_ALU64 | BPF_DIV | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp, imm, ctx);
+                emit(A64_UDIV(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_MOD | BPF_K:
+        case BPF_ALU64 | BPF_MOD | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(is64, tmp2, imm, ctx);
+                emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);
+                emit(A64_MUL(is64, tmp, tmp, tmp2), ctx);
+                emit(A64_SUB(is64, dst, dst, tmp), ctx);
+                break;
+        case BPF_ALU | BPF_LSH | BPF_K:
+        case BPF_ALU64 | BPF_LSH | BPF_K:
+                emit(A64_LSL(is64, dst, dst, imm), ctx);
+                break;
+        case BPF_ALU | BPF_RSH | BPF_K:
+        case BPF_ALU64 | BPF_RSH | BPF_K:
+                emit(A64_LSR(is64, dst, dst, imm), ctx);
+                break;
+        case BPF_ALU | BPF_ARSH | BPF_K:
+        case BPF_ALU64 | BPF_ARSH | BPF_K:
+                emit(A64_ASR(is64, dst, dst, imm), ctx);
+                break;
+
+#define check_imm(bits, imm) do {                               \
+        if ((((imm) > 0) && ((imm) >> (bits))) ||               \
+            (((imm) < 0) && (~(imm) >> (bits)))) {              \
+                pr_info("[%2d] imm=%d(0x%x) out of range\n",    \
+                        i, imm, imm);                           \
+                return -EINVAL;                                 \
+        }                                                       \
+} while (0)
+#define check_imm19(imm) check_imm(19, imm)
+#define check_imm26(imm) check_imm(26, imm)
+
+        /* JUMP off */
+        case BPF_JMP | BPF_JA:
+                jmp_offset = bpf2a64_offset(i + off, i, ctx);
+                check_imm26(jmp_offset);
+                emit(A64_B(jmp_offset), ctx);
+                break;
+        /* IF (dst COND src) JUMP off */
+        case BPF_JMP | BPF_JEQ | BPF_X:
+        case BPF_JMP | BPF_JGT | BPF_X:
+        case BPF_JMP | BPF_JGE | BPF_X:
+        case BPF_JMP | BPF_JNE | BPF_X:
+        case BPF_JMP | BPF_JSGT | BPF_X:
+        case BPF_JMP | BPF_JSGE | BPF_X:
+                emit(A64_CMP(1, dst, src), ctx);
+emit_cond_jmp:
+                jmp_offset = bpf2a64_offset(i + off, i, ctx);
+                check_imm19(jmp_offset);
+                switch (BPF_OP(code)) {
+                case BPF_JEQ:
+                        jmp_cond = A64_COND_EQ;
+                        break;
+                case BPF_JGT:
+                        jmp_cond = A64_COND_HI;
+                        break;
+                case BPF_JGE:
+                        jmp_cond = A64_COND_CS;
+                        break;
+                case BPF_JNE:
+                        jmp_cond = A64_COND_NE;
+                        break;
+                case BPF_JSGT:
+                        jmp_cond = A64_COND_GT;
+                        break;
+                case BPF_JSGE:
+                        jmp_cond = A64_COND_GE;
+                        break;
+                default:
+                        return -EFAULT;
+                }
+                emit(A64_B_(jmp_cond, jmp_offset), ctx);
+                break;
+        case BPF_JMP | BPF_JSET | BPF_X:
+                emit(A64_TST(1, dst, src), ctx);
+                goto emit_cond_jmp;
+        /* IF (dst COND imm) JUMP off */
+        case BPF_JMP | BPF_JEQ | BPF_K:
+        case BPF_JMP | BPF_JGT | BPF_K:
+        case BPF_JMP | BPF_JGE | BPF_K:
+        case BPF_JMP | BPF_JNE | BPF_K:
+        case BPF_JMP | BPF_JSGT | BPF_K:
+        case BPF_JMP | BPF_JSGE | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(1, tmp, imm, ctx);
+                emit(A64_CMP(1, dst, tmp), ctx);
+                goto emit_cond_jmp;
+        case BPF_JMP | BPF_JSET | BPF_K:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(1, tmp, imm, ctx);
+                emit(A64_TST(1, dst, tmp), ctx);
+                goto emit_cond_jmp;
+        /* function call */
+        case BPF_JMP | BPF_CALL:
+        {
+                const u8 r0 = bpf2a64[BPF_REG_0];
+                const u64 func = (u64)__bpf_call_base + imm;
+
+                ctx->tmp_used = 1;
+                emit_a64_mov_i64(tmp, func, ctx);
+                emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx);
+                emit(A64_MOV(1, A64_FP, A64_SP), ctx);
+                emit(A64_BLR(tmp), ctx);
+                emit(A64_MOV(1, r0, A64_R(0)), ctx);
+                emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx);
+                break;
+        }
+        /* function return */
+        case BPF_JMP | BPF_EXIT:
+                if (i == ctx->prog->len - 1)
+                        break;
+                jmp_offset = epilogue_offset(ctx);
+                check_imm26(jmp_offset);
+                emit(A64_B(jmp_offset), ctx);
+                break;
+
+        /* LDX: dst = *(size *)(src + off) */
+        case BPF_LDX | BPF_MEM | BPF_W:
+        case BPF_LDX | BPF_MEM | BPF_H:
+        case BPF_LDX | BPF_MEM | BPF_B:
+        case BPF_LDX | BPF_MEM | BPF_DW:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(1, tmp, off, ctx);
+                switch (BPF_SIZE(code)) {
+                case BPF_W:
+                        emit(A64_LDR32(dst, src, tmp), ctx);
+                        break;
+                case BPF_H:
+                        emit(A64_LDRH(dst, src, tmp), ctx);
+                        break;
+                case BPF_B:
+                        emit(A64_LDRB(dst, src, tmp), ctx);
+                        break;
+                case BPF_DW:
+                        emit(A64_LDR64(dst, src, tmp), ctx);
+                        break;
+                }
+                break;
+
+        /* ST: *(size *)(dst + off) = imm */
+        case BPF_ST | BPF_MEM | BPF_W:
+        case BPF_ST | BPF_MEM | BPF_H:
+        case BPF_ST | BPF_MEM | BPF_B:
+        case BPF_ST | BPF_MEM | BPF_DW:
+                goto notyet;
+
+        /* STX: *(size *)(dst + off) = src */
+        case BPF_STX | BPF_MEM | BPF_W:
+        case BPF_STX | BPF_MEM | BPF_H:
+        case BPF_STX | BPF_MEM | BPF_B:
+        case BPF_STX | BPF_MEM | BPF_DW:
+                ctx->tmp_used = 1;
+                emit_a64_mov_i(1, tmp, off, ctx);
+                switch (BPF_SIZE(code)) {
+                case BPF_W:
+                        emit(A64_STR32(src, dst, tmp), ctx);
+                        break;
+                case BPF_H:
+                        emit(A64_STRH(src, dst, tmp), ctx);
+                        break;
+                case BPF_B:
+                        emit(A64_STRB(src, dst, tmp), ctx);
+                        break;
+                case BPF_DW:
+                        emit(A64_STR64(src, dst, tmp), ctx);
+                        break;
+                }
+                break;
+        /* STX XADD: lock *(u32 *)(dst + off) += src */
+        case BPF_STX | BPF_XADD | BPF_W:
+        /* STX XADD: lock *(u64 *)(dst + off) += src */
+        case BPF_STX | BPF_XADD | BPF_DW:
+                goto notyet;
+
+        /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */
+        case BPF_LD | BPF_ABS | BPF_W:
+        case BPF_LD | BPF_ABS | BPF_H:
+        case BPF_LD | BPF_ABS | BPF_B:
+        /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + src + imm)) */
+        case BPF_LD | BPF_IND | BPF_W:
+        case BPF_LD | BPF_IND | BPF_H:
+        case BPF_LD | BPF_IND | BPF_B:
+        {
+                const u8 r0 = bpf2a64[BPF_REG_0]; /* r0 = return value */
+                const u8 r6 = bpf2a64[BPF_REG_6]; /* r6 = pointer to sk_buff */
+                const u8 fp = bpf2a64[BPF_REG_FP];
+                const u8 r1 = bpf2a64[BPF_REG_1]; /* r1: struct sk_buff *skb */
+                const u8 r2 = bpf2a64[BPF_REG_2]; /* r2: int k */
+                const u8 r3 = bpf2a64[BPF_REG_3]; /* r3: unsigned int size */
+                const u8 r4 = bpf2a64[BPF_REG_4]; /* r4: void *buffer */
+                const u8 r5 = bpf2a64[BPF_REG_5]; /* r5: void *(*func)(...) */
+                int size;
+
+                emit(A64_MOV(1, r1, r6), ctx);
+                emit_a64_mov_i(0, r2, imm, ctx);
+                if (BPF_MODE(code) == BPF_IND)
+                        emit(A64_ADD(0, r2, r2, src), ctx);
+                switch (BPF_SIZE(code)) {
+                case BPF_W:
+                        size = 4;
+                        break;
+                case BPF_H:
+                        size = 2;
+                        break;
+                case BPF_B:
+                        size = 1;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+                emit_a64_mov_i64(r3, size, ctx);
+                emit(A64_ADD_I(1, r4, fp, MAX_BPF_STACK), ctx);
+                emit_a64_mov_i64(r5, (unsigned long)bpf_load_pointer, ctx);
+                emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx);
+                emit(A64_MOV(1, A64_FP, A64_SP), ctx);
+                emit(A64_BLR(r5), ctx);
+                emit(A64_MOV(1, r0, A64_R(0)), ctx);
+                emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx);
+
+                jmp_offset = epilogue_offset(ctx);
+                check_imm19(jmp_offset);
+                emit(A64_CBZ(1, r0, jmp_offset), ctx);
+                emit(A64_MOV(1, r5, r0), ctx);
+                switch (BPF_SIZE(code)) {
+                case BPF_W:
+                        emit(A64_LDR32(r0, r5, A64_ZR), ctx);
+#ifndef CONFIG_CPU_BIG_ENDIAN
+                        emit(A64_REV32(0, r0, r0), ctx);
+#endif
+                        break;
+                case BPF_H:
+                        emit(A64_LDRH(r0, r5, A64_ZR), ctx);
+#ifndef CONFIG_CPU_BIG_ENDIAN
+                        emit(A64_REV16(0, r0, r0), ctx);
+#endif
+                        break;
+                case BPF_B:
+                        emit(A64_LDRB(r0, r5, A64_ZR), ctx);
+                        break;
+                }
+                break;
+        }
+notyet:
+                pr_info_once("*** NOT YET: opcode %02x ***\n", code);
+                return -EFAULT;
+
+        default:
+                pr_err_once("unknown opcode %02x\n", code);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int build_body(struct jit_ctx *ctx)
+{
+        const struct bpf_prog *prog = ctx->prog;
+        int i;
+
+        for (i = 0; i < prog->len; i++) {
+                const struct bpf_insn *insn = &prog->insnsi[i];
+                int ret;
+
+                if (ctx->image == NULL)
+                        ctx->offset[i] = ctx->idx;
+
+                ret = build_insn(insn, ctx);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static inline void bpf_flush_icache(void *start, void *end)
+{
+        flush_icache_range((unsigned long)start, (unsigned long)end);
+}
+
+void bpf_jit_compile(struct bpf_prog *prog)
+{
+        /* Nothing to do here. We support Internal BPF. */
+}
+
+void bpf_int_jit_compile(struct bpf_prog *prog)
+{
+        struct jit_ctx ctx;
+        int image_size;
+
+        if (!bpf_jit_enable)
+                return;
+
+        if (!prog || !prog->len)
+                return;
+
+        memset(&ctx, 0, sizeof(ctx));
+        ctx.prog = prog;
+
+        ctx.offset = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
+        if (ctx.offset == NULL)
+                return;
+
+        /* 1. Initial fake pass to compute ctx->idx. */
+
+        /* Fake pass to fill in ctx->offset. */
+        if (build_body(&ctx))
+                goto out;
+
+        build_prologue(&ctx);
+
+        build_epilogue(&ctx);
+
+        /* Now we know the actual image size. */
+        image_size = sizeof(u32) * ctx.idx;
+        ctx.image = module_alloc(image_size);
+        if (unlikely(ctx.image == NULL))
+                goto out;
+
+        /* 2. Now, the actual pass. */
+
+        ctx.idx = 0;
+        build_prologue(&ctx);
+
+        ctx.body_offset = ctx.idx;
+        if (build_body(&ctx)) {
+                module_free(NULL, ctx.image);
+                goto out;
+        }
+
+        build_epilogue(&ctx);
+
+        /* And we're done. */
+        if (bpf_jit_enable > 1)
+                bpf_jit_dump(prog->len, image_size, 2, ctx.image);
+
+        bpf_flush_icache(ctx.image, ctx.image + ctx.idx);
+        prog->bpf_func = (void *)ctx.image;
+        prog->jited = 1;
+
+out:
+        kfree(ctx.offset);
+}
+
+void bpf_jit_free(struct bpf_prog *prog)
+{
+        if (prog->jited)
+                module_free(NULL, prog->bpf_func);
+
+        kfree(prog);
+}
diff --git a/arch/avr32/include/asm/Kbuild b/arch/avr32/include/asm/Kbuild
index 00a0f3ccd6eb..2a71b1cb9848 100644
--- a/arch/avr32/include/asm/Kbuild
+++ b/arch/avr32/include/asm/Kbuild
@@ -9,6 +9,7 @@ generic-y += exec.h
 generic-y += futex.h
 generic-y += hash.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += local.h
 generic-y += local64.h
 generic-y += mcs_spinlock.h
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index ed30699cc635..af76634f8d98 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -671,7 +671,7 @@ config TICKSOURCE_CORETMR
         default y
 endmenu
 
-menu "Clock souce"
+menu "Clock source"
         depends on GENERIC_CLOCKEVENTS
 config CYCLES_CLOCKSOURCE
         bool "CYCLES"
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 0d93b9a79ca9..46ed6bb9c679 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -15,6 +15,7 @@ generic-y += hw_irq.h
 generic-y += ioctl.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += kvm_para.h
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 1e7290ef3525..1e1014df5e9e 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -733,7 +733,6 @@ static struct platform_device bfin_mac_device = {
 
 static struct pata_platform_info bfin_pata_platform_data = {
         .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH,
 };
 
 static struct resource bfin_pata_resources[] = {
@@ -750,7 +749,7 @@ static struct resource bfin_pata_resources[] = {
         {
                 .start = PATA_INT,
                 .end = PATA_INT,
-                .flags = IORESOURCE_IRQ,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         },
 };
 
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index c7495dc74690..d056db9e5592 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -587,7 +587,6 @@ static struct platform_device bfin_mac_device = {
 
 static struct pata_platform_info bfin_pata_platform_data = {
         .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH,
 };
 
 static struct resource bfin_pata_resources[] = {
@@ -604,7 +603,7 @@ static struct resource bfin_pata_resources[] = {
         {
                 .start = PATA_INT,
                 .end = PATA_INT,
-                .flags = IORESOURCE_IRQ,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         },
 };
 
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index de19b8a56007..88a19fc9844d 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -2462,7 +2462,6 @@ static struct platform_device bfin_sport0_device = {
 #define PATA_INT        IRQ_PF5
 static struct pata_platform_info bfin_pata_platform_data = {
         .ioport_shift = 1,
-        .irq_flags = IRQF_TRIGGER_HIGH,
 };
 
 static struct resource bfin_pata_resources[] = {
@@ -2479,7 +2478,7 @@ static struct resource bfin_pata_resources[] = {
         {
                 .start = PATA_INT,
                 .end = PATA_INT,
-                .flags = IORESOURCE_IRQ,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         },
 };
 #elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 6b988ad653d8..ed309c9a62b6 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -589,7 +589,6 @@ static struct platform_device bfin_mac_device = {
 
 static struct pata_platform_info bfin_pata_platform_data = {
         .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH,
 };
 
 static struct resource bfin_pata_resources[] = {
@@ -606,7 +605,7 @@ static struct resource bfin_pata_resources[] = {
         {
                 .start = PATA_INT,
                 .end = PATA_INT,
-                .flags = IORESOURCE_IRQ,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         },
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index e862f7823e68..c6db52ba3a06 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -354,7 +354,6 @@ static struct platform_device bfin_sir0_device = {
 
 static struct pata_platform_info bfin_pata_platform_data = {
         .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH,
 };
 
 static struct resource bfin_pata_resources[] = {
@@ -371,7 +370,7 @@ static struct resource bfin_pata_resources[] = {
         {
                 .start = PATA_INT,
                 .end = PATA_INT,
-                .flags = IORESOURCE_IRQ,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
         },
 };
 
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 1f94784eab6d..694619365265 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -455,7 +455,7 @@ void handle_sec_sci_fault(uint32_t gstat)
                         printk(KERN_DEBUG "sec ack err\n");
                         break;
                 default:
-                        printk(KERN_DEBUG "sec sci unknow err\n");
+                        printk(KERN_DEBUG "sec sci unknown err\n");
                 }
         }
 
diff --git a/arch/c6x/include/asm/Kbuild b/arch/c6x/include/asm/Kbuild
index 8dbdce8421b0..e77e0c1dbe75 100644
--- a/arch/c6x/include/asm/Kbuild
+++ b/arch/c6x/include/asm/Kbuild
@@ -22,6 +22,7 @@ generic-y += ioctl.h
 generic-y += ioctls.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += local.h
diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild
index 31742dfadff9..2ca489eaadd3 100644
--- a/arch/cris/include/asm/Kbuild
+++ b/arch/cris/include/asm/Kbuild
@@ -8,12 +8,14 @@ generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += exec.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += kvm_para.h
 generic-y += linkage.h
 generic-y += mcs_spinlock.h
 generic-y += module.h
 generic-y += preempt.h
 generic-y += scatterlist.h
+generic-y += sections.h
 generic-y += trace_clock.h
 generic-y += vga.h
 generic-y += xor.h
diff --git a/arch/cris/include/asm/sections.h b/arch/cris/include/asm/sections.h
deleted file mode 100644
index 2c998ce8967b..000000000000
--- a/arch/cris/include/asm/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _CRIS_SECTIONS_H
-#define _CRIS_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/frv/include/asm/Kbuild b/arch/frv/include/asm/Kbuild
index 5b73921b6e9d..3caf05cabfc5 100644
--- a/arch/frv/include/asm/Kbuild
+++ b/arch/frv/include/asm/Kbuild
@@ -3,6 +3,7 @@ generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += exec.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
 generic-y += scatterlist.h
diff --git a/arch/frv/include/asm/processor.h b/arch/frv/include/asm/processor.h
index a34f309e5801..ae8d423e79d9 100644
--- a/arch/frv/include/asm/processor.h
+++ b/arch/frv/include/asm/processor.h
@@ -35,22 +35,6 @@
 struct task_struct;
 
 /*
- *  CPU type and hardware bug flags. Kept separately for each CPU.
- */
-struct cpuinfo_frv {
-#ifdef CONFIG_MMU
-        unsigned long   *pgd_quick;
-        unsigned long   *pte_quick;
-        unsigned long   pgtable_cache_sz;
-#endif
-} __cacheline_aligned;
-
-extern struct cpuinfo_frv __nongprelbss boot_cpu_data;
-
-#define cpu_data                (&boot_cpu_data)
-#define current_cpu_data        boot_cpu_data
-
-/*
  * Bus types
  */
 #define EISA_bus 0
@@ -129,7 +113,8 @@ unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)   ((tsk)->thread.frame0->pc)
 #define KSTK_ESP(tsk)   ((tsk)->thread.frame0->sp)
 
-#define cpu_relax()    barrier()
+#define cpu_relax() barrier()
+#define cpu_relax_lowlatency() cpu_relax()
 
 /* data cache prefetch */
 #define ARCH_HAS_PREFETCH
diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c
index 2cc327a1ca44..091b2839be90 100644
--- a/arch/frv/kernel/irq-mb93091.c
+++ b/arch/frv/kernel/irq-mb93091.c
@@ -107,25 +107,25 @@ static irqreturn_t fpga_interrupt(int irq, void *_mask)
 static struct irqaction fpga_irq[4]  = {
         [0] = {
                 .handler        = fpga_interrupt,
-                .flags          = IRQF_DISABLED | IRQF_SHARED,
+                .flags          = IRQF_SHARED,
                 .name           = "fpga.0",
                 .dev_id         = (void *) 0x0028UL,
         },
         [1] = {
                 .handler        = fpga_interrupt,
-                .flags          = IRQF_DISABLED | IRQF_SHARED,
+                .flags          = IRQF_SHARED,
                 .name           = "fpga.1",
                 .dev_id         = (void *) 0x0050UL,
         },
         [2] = {
                 .handler        = fpga_interrupt,
-                .flags          = IRQF_DISABLED | IRQF_SHARED,
+                .flags          = IRQF_SHARED,
                 .name           = "fpga.2",
                 .dev_id         = (void *) 0x1c00UL,
         },
         [3] = {
                 .handler        = fpga_interrupt,
-                .flags          = IRQF_DISABLED | IRQF_SHARED,
+                .flags          = IRQF_SHARED,
                 .name           = "fpga.3",
                 .dev_id         = (void *) 0x6386UL,
         }
diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c
index 95e4eb4f1f38..1f3015cf80f5 100644
--- a/arch/frv/kernel/irq-mb93093.c
+++ b/arch/frv/kernel/irq-mb93093.c
@@ -105,7 +105,6 @@ static irqreturn_t fpga_interrupt(int irq, void *_mask)
 static struct irqaction fpga_irq[1]  = {
         [0] = {
                 .handler        = fpga_interrupt,
-                .flags          = IRQF_DISABLED,
                 .name           = "fpga.0",
                 .dev_id         = (void *) 0x0700UL,
         }
diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c
index ba648da0932d..8ca5aa4ff595 100644
--- a/arch/frv/kernel/irq-mb93493.c
+++ b/arch/frv/kernel/irq-mb93493.c
@@ -118,13 +118,13 @@ static irqreturn_t mb93493_interrupt(int irq, void *_piqsr)
 static struct irqaction mb93493_irq[2]  = {
         [0] = {
                 .handler        = mb93493_interrupt,
-                .flags          = IRQF_DISABLED | IRQF_SHARED,
+                .flags          = IRQF_SHARED,
                 .name           = "mb93493.0",
                 .dev_id         = (void *) __addr_MB93493_IQSR(0),
         },
         [1] = {
                 .handler        = mb93493_interrupt,
-                .flags          = IRQF_DISABLED | IRQF_SHARED,
+                .flags          = IRQF_SHARED,
                 .name           = "mb93493.1",
                 .dev_id         = (void *) __addr_MB93493_IQSR(1),
         }
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
index 9f3a7a62d787..9f4a9a607dbe 100644
--- a/arch/frv/kernel/setup.c
+++ b/arch/frv/kernel/setup.c
@@ -104,8 +104,6 @@ unsigned long __nongprelbss dma_coherent_mem_end;
 unsigned long __initdata __sdram_old_base;
 unsigned long __initdata num_mappedpages;
 
-struct cpuinfo_frv __nongprelbss boot_cpu_data;
-
 char __initdata command_line[COMMAND_LINE_SIZE];
 char __initdata redboot_command_line[COMMAND_LINE_SIZE];
 
diff --git a/arch/frv/kernel/time.c b/arch/frv/kernel/time.c
index b457de496b70..332e00bf9d06 100644
--- a/arch/frv/kernel/time.c
+++ b/arch/frv/kernel/time.c
@@ -44,7 +44,6 @@ static irqreturn_t timer_interrupt(int irq, void *dummy);
 
 static struct irqaction timer_irq  = {
         .handler = timer_interrupt,
-        .flags = IRQF_DISABLED,
         .name = "timer",
 };
 
diff --git a/arch/hexagon/include/asm/Kbuild b/arch/hexagon/include/asm/Kbuild
index 0e69796b58c7..5f234a5a2320 100644
--- a/arch/hexagon/include/asm/Kbuild
+++ b/arch/hexagon/include/asm/Kbuild
@@ -23,6 +23,7 @@ generic-y += ioctls.h
 generic-y += iomap.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += local.h
diff --git a/arch/hexagon/mm/cache.c b/arch/hexagon/mm/cache.c
index fe14ccf28561..0c76c802e31c 100644
--- a/arch/hexagon/mm/cache.c
+++ b/arch/hexagon/mm/cache.c
@@ -68,6 +68,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
         );
         local_irq_restore(flags);
 }
+EXPORT_SYMBOL(flush_icache_range);
 
 void hexagon_clean_dcache_range(unsigned long start, unsigned long end)
 {
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 64aefb76bd69..c84c88bbbbd7 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -549,8 +549,6 @@ source "drivers/sn/Kconfig"
 config KEXEC
         bool "kexec system call"
         depends on !IA64_HP_SIM && (!SMP || HOTPLUG_CPU)
-        select CRYPTO
-        select CRYPTO_SHA256
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/ia64/configs/bigsur_defconfig b/arch/ia64/configs/bigsur_defconfig
index 4c4ac163c600..b6bda1838629 100644
--- a/arch/ia64/configs/bigsur_defconfig
+++ b/arch/ia64/configs/bigsur_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_LOG_BUF_SHIFT=16
@@ -6,6 +5,8 @@ CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_SGI_PARTITION=y
 CONFIG_IA64_DIG=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
@@ -51,9 +52,6 @@ CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_NET_PCI=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
@@ -85,7 +83,6 @@ CONFIG_EXT3_FS=y
 CONFIG_XFS_FS=y
 CONFIG_XFS_QUOTA=y
 CONFIG_XFS_POSIX_ACL=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
@@ -95,17 +92,13 @@ CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
+CONFIG_NFS_V4=m
 CONFIG_NFSD=m
 CONFIG_NFSD_V4=y
 CONFIG_CIFS=m
 CONFIG_CIFS_STATS=y
 CONFIG_CIFS_XATTR=y
 CONFIG_CIFS_POSIX=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_SGI_PARTITION=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=m
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig
index e8ed3ae70aae..81f686dee53c 100644
--- a/arch/ia64/configs/generic_defconfig
+++ b/arch/ia64/configs/generic_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
@@ -6,13 +5,13 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=20
 CONFIG_CGROUPS=y
 CONFIG_CPUSETS=y
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_SGI_PARTITION=y
 CONFIG_MCKINLEY=y
 CONFIG_IA64_PAGE_SIZE_64KB=y
 CONFIG_IA64_CYCLONE=y
@@ -29,14 +28,13 @@ CONFIG_ACPI_BUTTON=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_DOCK=y
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_CONTAINER=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
-CONFIG_ARPD=y
 CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -82,16 +80,13 @@ CONFIG_FUSION_FC=m
 CONFIG_FUSION_SAS=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_NET_ETHERNET=y
+CONFIG_NETCONSOLE=y
+CONFIG_TIGON3=y
 CONFIG_NET_TULIP=y
 CONFIG_TULIP=m
-CONFIG_NET_PCI=y
-CONFIG_NET_VENDOR_INTEL=y
 CONFIG_E100=m
 CONFIG_E1000=y
 CONFIG_IGB=y
-CONFIG_TIGON3=y
-CONFIG_NETCONSOLE=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_GAMEPORT=m
 CONFIG_SERIAL_NONSTANDARD=y
@@ -151,6 +146,7 @@ CONFIG_USB_STORAGE=m
 CONFIG_INFINIBAND=m
 CONFIG_INFINIBAND_MTHCA=m
 CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INTEL_IOMMU=y
 CONFIG_MSPEC=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
@@ -164,7 +160,6 @@ CONFIG_REISERFS_FS_XATTR=y
 CONFIG_REISERFS_FS_POSIX_ACL=y
 CONFIG_REISERFS_FS_SECURITY=y
 CONFIG_XFS_FS=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
@@ -175,16 +170,10 @@ CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
+CONFIG_NFS_V4=m
 CONFIG_NFSD=m
 CONFIG_NFSD_V4=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_SGI_PARTITION=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -225,11 +214,7 @@ CONFIG_NLS_UTF8=m
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MUTEXES=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRC_T10DIF=y
-CONFIG_INTEL_IOMMU=y
diff --git a/arch/ia64/configs/gensparse_defconfig b/arch/ia64/configs/gensparse_defconfig
index d663efd1e4db..5b4fcdd51457 100644
--- a/arch/ia64/configs/gensparse_defconfig
+++ b/arch/ia64/configs/gensparse_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
@@ -9,6 +8,8 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_SGI_PARTITION=y
 CONFIG_MCKINLEY=y
 CONFIG_IA64_CYCLONE=y
 CONFIG_SMP=y
@@ -24,14 +25,12 @@ CONFIG_BINFMT_MISC=m
 CONFIG_ACPI_BUTTON=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_CONTAINER=m
 CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
-CONFIG_ARPD=y
 CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_BLK_DEV_LOOP=m
@@ -71,15 +70,12 @@ CONFIG_FUSION_SPI=y
 CONFIG_FUSION_FC=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_NET_ETHERNET=y
+CONFIG_NETCONSOLE=y
+CONFIG_TIGON3=y
 CONFIG_NET_TULIP=y
 CONFIG_TULIP=m
-CONFIG_NET_PCI=y
-CONFIG_NET_VENDOR_INTEL=y
 CONFIG_E100=m
 CONFIG_E1000=y
-CONFIG_TIGON3=y
-CONFIG_NETCONSOLE=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_GAMEPORT=m
 CONFIG_SERIAL_NONSTANDARD=y
@@ -146,7 +142,6 @@ CONFIG_REISERFS_FS_XATTR=y
 CONFIG_REISERFS_FS_POSIX_ACL=y
 CONFIG_REISERFS_FS_SECURITY=y
 CONFIG_XFS_FS=y
-CONFIG_AUTOFS_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
@@ -157,16 +152,10 @@ CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
+CONFIG_NFS_V4=m
 CONFIG_NFSD=m
 CONFIG_NFSD_V4=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_SGI_PARTITION=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
diff --git a/arch/ia64/configs/sim_defconfig b/arch/ia64/configs/sim_defconfig
index b4548a3e82d5..f0f69fdbddae 100644
--- a/arch/ia64/configs/sim_defconfig
+++ b/arch/ia64/configs/sim_defconfig
@@ -1,13 +1,12 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_IA64_HP_SIM=y
 CONFIG_MCKINLEY=y
 CONFIG_IA64_PAGE_SIZE_64KB=y
@@ -27,7 +26,6 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SPI_ATTRS=y
@@ -49,8 +47,6 @@ CONFIG_HUGETLBFS=y
 CONFIG_NFS_FS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
+CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_INFO=y
diff --git a/arch/ia64/configs/tiger_defconfig b/arch/ia64/configs/tiger_defconfig
index c8a3f40e77f6..192ed157c9ce 100644
--- a/arch/ia64/configs/tiger_defconfig
+++ b/arch/ia64/configs/tiger_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
@@ -11,6 +10,8 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_SGI_PARTITION=y
 CONFIG_IA64_DIG=y
 CONFIG_MCKINLEY=y
 CONFIG_IA64_PAGE_SIZE_64KB=y
@@ -29,14 +30,12 @@ CONFIG_BINFMT_MISC=m
 CONFIG_ACPI_BUTTON=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_CONTAINER=m
 CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
-CONFIG_ARPD=y
 CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_BLK_DEV_LOOP=m
@@ -53,6 +52,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=m
 CONFIG_BLK_DEV_SR=m
 CONFIG_CHR_DEV_SG=m
+CONFIG_SCSI_FC_ATTRS=y
 CONFIG_SCSI_SYM53C8XX_2=y
 CONFIG_SCSI_QLOGIC_1280=y
 CONFIG_MD=y
@@ -72,15 +72,12 @@ CONFIG_FUSION_FC=y
 CONFIG_FUSION_CTL=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_NET_ETHERNET=y
+CONFIG_NETCONSOLE=y
+CONFIG_TIGON3=y
 CONFIG_NET_TULIP=y
 CONFIG_TULIP=m
-CONFIG_NET_PCI=y
-CONFIG_NET_VENDOR_INTEL=y
 CONFIG_E100=m
 CONFIG_E1000=y
-CONFIG_TIGON3=y
-CONFIG_NETCONSOLE=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_GAMEPORT=m
 CONFIG_SERIAL_NONSTANDARD=y
@@ -118,7 +115,6 @@ CONFIG_REISERFS_FS_XATTR=y
 CONFIG_REISERFS_FS_POSIX_ACL=y
 CONFIG_REISERFS_FS_SECURITY=y
 CONFIG_XFS_FS=y
-CONFIG_AUTOFS_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
@@ -129,16 +125,10 @@ CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
+CONFIG_NFS_V4=m
 CONFIG_NFSD=m
 CONFIG_NFSD_V4=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_SGI_PARTITION=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -180,6 +170,5 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_IA64_GRANULE_16MB=y
-CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_MD5=y
diff --git a/arch/ia64/configs/zx1_defconfig b/arch/ia64/configs/zx1_defconfig
index 54bc72eda30d..b504c8e2fd52 100644
--- a/arch/ia64/configs/zx1_defconfig
+++ b/arch/ia64/configs/zx1_defconfig
@@ -1,9 +1,9 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KPROBES=y
 CONFIG_MODULES=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_IA64_HP_ZX1=y
 CONFIG_MCKINLEY=y
 CONFIG_SMP=y
@@ -18,6 +18,7 @@ CONFIG_EFI_VARS=y
 CONFIG_BINFMT_MISC=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -37,9 +38,9 @@ CONFIG_CHR_DEV_OSST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_FC_ATTRS=y
 CONFIG_SCSI_SYM53C8XX_2=y
 CONFIG_SCSI_QLOGIC_1280=y
 CONFIG_FUSION=y
@@ -48,18 +49,15 @@ CONFIG_FUSION_FC=y
 CONFIG_FUSION_CTL=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
+CONFIG_TIGON3=y
 CONFIG_NET_TULIP=y
 CONFIG_TULIP=y
 CONFIG_TULIP_MWI=y
 CONFIG_TULIP_MMIO=y
 CONFIG_TULIP_NAPI=y
 CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_NET_PCI=y
-CONFIG_NET_VENDOR_INTEL=y
 CONFIG_E100=y
 CONFIG_E1000=y
-CONFIG_TIGON3=y
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
@@ -100,7 +98,6 @@ CONFIG_USB_STORAGE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT3_FS=y
-CONFIG_AUTOFS_FS=y
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=y
@@ -110,12 +107,9 @@ CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=y
 CONFIG_NLS_CODEPAGE_775=y
diff --git a/arch/ia64/include/asm/Kbuild b/arch/ia64/include/asm/Kbuild
index e8317d2d6c8d..747320be9d0e 100644
--- a/arch/ia64/include/asm/Kbuild
+++ b/arch/ia64/include/asm/Kbuild
@@ -2,6 +2,7 @@
 generic-y += clkdev.h
 generic-y += exec.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += kvm_para.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h
index db95f570705f..4729752b7256 100644
--- a/arch/ia64/include/asm/kvm_host.h
+++ b/arch/ia64/include/asm/kvm_host.h
@@ -234,9 +234,6 @@ struct kvm_vm_data {
 #define KVM_REQ_PTC_G           32
 #define KVM_REQ_RESUME          33
 
-struct kvm;
-struct kvm_vcpu;
-
 struct kvm_mmio_req {
         uint64_t addr;          /*  physical address            */
         uint64_t size;          /*  size in bytes               */
@@ -595,6 +592,18 @@ void kvm_sal_emul(struct kvm_vcpu *vcpu);
 struct kvm *kvm_arch_alloc_vm(void);
 void kvm_arch_free_vm(struct kvm *kvm);
 
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_free_memslot(struct kvm *kvm,
+                struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
+static inline void kvm_arch_memslots_updated(struct kvm *kvm) {}
+static inline void kvm_arch_commit_memory_region(struct kvm *kvm,
+                struct kvm_userspace_memory_region *mem,
+                const struct kvm_memory_slot *old,
+                enum kvm_mr_change change) {}
+static inline void kvm_arch_hardware_unsetup(void) {}
+
 #endif /* __ASSEMBLY__*/
 
 #endif
diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h
index 4254f5d3218c..10a14ead70b9 100644
--- a/arch/ia64/include/asm/unistd.h
+++ b/arch/ia64/include/asm/unistd.h
@@ -11,7 +11,7 @@
 
 
 
-#define NR_syscalls                     316 /* length of syscall table */
+#define NR_syscalls                     317 /* length of syscall table */
 
 /*
  * The following defines stop scripts/checksyscalls.sh from complaining about
diff --git a/arch/ia64/include/uapi/asm/unistd.h b/arch/ia64/include/uapi/asm/unistd.h
index 99801c3be914..18026b2eb582 100644
--- a/arch/ia64/include/uapi/asm/unistd.h
+++ b/arch/ia64/include/uapi/asm/unistd.h
@@ -329,5 +329,6 @@
 #define __NR_sched_getattr              1337
 #define __NR_renameat2                  1338
 #define __NR_getrandom                  1339
+#define __NR_memfd_create               1340
 
 #endif /* _UAPI_ASM_IA64_UNISTD_H */
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index 4c13837a9269..01edf242eb29 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -1777,6 +1777,7 @@ sys_call_table:
         data8 sys_sched_getattr
         data8 sys_renameat2
         data8 sys_getrandom
+        data8 sys_memfd_create                  // 1340
 
         .org sys_call_table + 8*NR_syscalls     // guard against failures to increase NR_syscalls
 #endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c
index c430f9198d1b..8c3730c3c63d 100644
--- a/arch/ia64/kernel/msi_ia64.c
+++ b/arch/ia64/kernel/msi_ia64.c
@@ -23,7 +23,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata,
         if (irq_prepare_move(irq, cpu))
                 return -1;
 
-        get_cached_msi_msg(irq, &msg);
+        __get_cached_msi_msg(idata->msi_desc, &msg);
 
         addr = msg.address_lo;
         addr &= MSI_ADDR_DEST_ID_MASK;
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 0729ba6acddf..ec6b9acb6bea 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -125,7 +125,7 @@ long ia64_pal_vp_create(u64 *vpd, u64 *host_iva, u64 *opt_handler)
 
 static  DEFINE_SPINLOCK(vp_lock);
 
-int kvm_arch_hardware_enable(void *garbage)
+int kvm_arch_hardware_enable(void)
 {
         long  status;
         long  tmp_base;
@@ -160,7 +160,7 @@ int kvm_arch_hardware_enable(void *garbage)
         return 0;
 }
 
-void kvm_arch_hardware_disable(void *garbage)
+void kvm_arch_hardware_disable(void)
 {
 
         long status;
@@ -1364,10 +1364,6 @@ static void kvm_release_vm_pages(struct kvm *kvm)
         }
 }
 
-void kvm_arch_sync_events(struct kvm *kvm)
-{
-}
-
 void kvm_arch_destroy_vm(struct kvm *kvm)
 {
         kvm_iommu_unmap_guest(kvm);
@@ -1376,10 +1372,6 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
         kvm_release_vm_pages(kvm);
 }
 
-void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
-{
-}
-
 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
         if (cpu != vcpu->cpu) {
@@ -1468,7 +1460,6 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
         kfree(vcpu->arch.apic);
 }
 
-
 long kvm_arch_vcpu_ioctl(struct file *filp,
                          unsigned int ioctl, unsigned long arg)
 {
@@ -1551,21 +1542,12 @@ int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
         return VM_FAULT_SIGBUS;
 }
 
-void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
-                           struct kvm_memory_slot *dont)
-{
-}
-
 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
                             unsigned long npages)
 {
         return 0;
 }
 
-void kvm_arch_memslots_updated(struct kvm *kvm)
-{
-}
-
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                 struct kvm_memory_slot *memslot,
                 struct kvm_userspace_memory_region *mem,
@@ -1597,14 +1579,6 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
         return 0;
 }
 
-void kvm_arch_commit_memory_region(struct kvm *kvm,
-                struct kvm_userspace_memory_region *mem,
-                const struct kvm_memory_slot *old,
-                enum kvm_mr_change change)
-{
-        return;
-}
-
 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 {
         kvm_flush_remote_tlbs(kvm);
@@ -1853,10 +1827,6 @@ int kvm_arch_hardware_setup(void)
         return 0;
 }
 
-void kvm_arch_hardware_unsetup(void)
-{
-}
-
 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 {
         return __apic_accept_irq(vcpu, irq->vector);
diff --git a/arch/ia64/pci/fixup.c b/arch/ia64/pci/fixup.c
index ec73b2cf912a..fc505d58f078 100644
--- a/arch/ia64/pci/fixup.c
+++ b/arch/ia64/pci/fixup.c
@@ -38,27 +38,6 @@ static void pci_fixup_video(struct pci_dev *pdev)
                 return;
         /* Maybe, this machine supports legacy memory map. */
 
-        if (!vga_default_device()) {
-                resource_size_t start, end;
-                int i;
-
-                /* Does firmware framebuffer belong to us? */
-                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
-                        if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
-                                continue;
-
-                        start = pci_resource_start(pdev, i);
-                        end  = pci_resource_end(pdev, i);
-
-                        if (!start || !end)
-                                continue;
-
-                        if (screen_info.lfb_base >= start &&
-                            (screen_info.lfb_base + screen_info.lfb_size) < end)
-                                vga_set_default_device(pdev);
-                }
-        }
-
         /* Is VGA routed to us? */
         bus = pdev->bus;
         while (bus) {
@@ -83,8 +62,7 @@ static void pci_fixup_video(struct pci_dev *pdev)
                 pci_read_config_word(pdev, PCI_COMMAND, &config);
                 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
                         pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
-                        dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
-                        vga_set_default_device(pdev);
+                        dev_printk(KERN_DEBUG, &pdev->dev, "Video device with shadowed ROM\n");
                 }
         }
 }
diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c
index afc58d2799ad..446e7799928c 100644
--- a/arch/ia64/sn/kernel/msi_sn.c
+++ b/arch/ia64/sn/kernel/msi_sn.c
@@ -175,8 +175,8 @@ static int sn_set_msi_irq_affinity(struct irq_data *data,
          * Release XIO resources for the old MSI PCI address
          */
 
-        get_cached_msi_msg(irq, &msg);
-        sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
+        __get_cached_msi_msg(data->msi_desc, &msg);
+        sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
         pdev = sn_pdev->pdi_linux_pcidev;
         provider = SN_PCIDEV_BUSPROVIDER(pdev);
 
diff --git a/arch/m32r/include/asm/Kbuild b/arch/m32r/include/asm/Kbuild
index accc10a3dc78..3796801d6e0c 100644
--- a/arch/m32r/include/asm/Kbuild
+++ b/arch/m32r/include/asm/Kbuild
@@ -3,8 +3,10 @@ generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += exec.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += module.h
 generic-y += preempt.h
 generic-y += scatterlist.h
+generic-y += sections.h
 generic-y += trace_clock.h
diff --git a/arch/m32r/include/asm/sections.h b/arch/m32r/include/asm/sections.h
deleted file mode 100644
index 5e5d21c4908a..000000000000
--- a/arch/m32r/include/asm/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _M32R_SECTIONS_H
-#define _M32R_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif  /* _M32R_SECTIONS_H */
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index 1a15f81ea1bd..093f2761aa51 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -134,7 +134,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction irq0 = {
         .handler = timer_interrupt,
-        .flags = IRQF_DISABLED,
         .name = "MFT2",
 };
 
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 3ff8c9a25335..87b7c7581b1d 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -91,8 +91,6 @@ config MMU_SUN3
 config KEXEC
         bool "kexec system call"
         depends on M68KCLASSIC
-        select CRYPTO
-        select CRYPTO_SHA256
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/m68k/Kconfig.devices b/arch/m68k/Kconfig.devices
index d163991c5717..42b6fcfc30ef 100644
--- a/arch/m68k/Kconfig.devices
+++ b/arch/m68k/Kconfig.devices
@@ -73,7 +73,7 @@ config ATARI_ETHERNEC
           ROM port. The driver works by polling instead of interrupts, so it
           is quite slow.
 
-          This driver also suppports the ethernet part of the NetUSBee ROM
+          This driver also supports the ethernet part of the NetUSBee ROM
           port combined Ethernet/USB adapter.
 
           To compile the actual ethernet driver, choose Y or M in for the NE2000
@@ -95,7 +95,7 @@ config ATARI_DSP56K
 
 config AMIGA_BUILTIN_SERIAL
         tristate "Amiga builtin serial support"
-        depends on AMIGA
+        depends on AMIGA && TTY
         help
           If you want to use your Amiga's built-in serial port in Linux,
           answer Y.
diff --git a/arch/m68k/atari/stram.c b/arch/m68k/atari/stram.c
index 5f8cb5a234d9..c83d66442612 100644
--- a/arch/m68k/atari/stram.c
+++ b/arch/m68k/atari/stram.c
@@ -21,6 +21,7 @@
 #include <linux/mount.h>
 #include <linux/blkdev.h>
 #include <linux/module.h>
+#include <linux/ioport.h>
 
 #include <asm/setup.h>
 #include <asm/machdep.h>
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
index c67c94a2d672..dbaf9f3065e8 100644
--- a/arch/m68k/include/asm/Kbuild
+++ b/arch/m68k/include/asm/Kbuild
@@ -11,6 +11,7 @@ generic-y += hw_irq.h
 generic-y += ioctl.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += kvm_para.h
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index ffdf54f44bc6..8955b40a5dc4 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -510,6 +510,13 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
  */
 #define xlate_dev_kmem_ptr(p)   p
 
-#define ioport_map(port, nr)    ((void __iomem *)(port))
+static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+        return (void __iomem *) port;
+}
+
+static inline void ioport_unmap(void __iomem *p)
+{
+}
 
 #endif /* _IO_H */
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 1fcdd344c7ad..4ef7a54813e6 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -4,7 +4,7 @@
 #include <uapi/asm/unistd.h>
 
 
-#define NR_syscalls             352
+#define NR_syscalls             354
 
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_OLD_STAT
diff --git a/arch/m68k/include/uapi/asm/unistd.h b/arch/m68k/include/uapi/asm/unistd.h
index 9cd82fbc7817..b419c6b7ac37 100644
--- a/arch/m68k/include/uapi/asm/unistd.h
+++ b/arch/m68k/include/uapi/asm/unistd.h
@@ -357,5 +357,7 @@
 #define __NR_sched_setattr      349
 #define __NR_sched_getattr      350
 #define __NR_renameat2          351
+#define __NR_getrandom          352
+#define __NR_memfd_create       353
 
 #endif /* _UAPI_ASM_M68K_UNISTD_H_ */
diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c
index 3a480b3df0d6..9aa01adb407f 100644
--- a/arch/m68k/kernel/sys_m68k.c
+++ b/arch/m68k/kernel/sys_m68k.c
@@ -376,7 +376,6 @@ cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len)
 asmlinkage int
 sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
 {
-        struct vm_area_struct *vma;
         int ret = -EINVAL;
 
         if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL ||
@@ -389,17 +388,21 @@ sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
                 if (!capable(CAP_SYS_ADMIN))
                         goto out;
         } else {
+                struct vm_area_struct *vma;
+
+                /* Check for overflow.  */
+                if (addr + len < addr)
+                        goto out;
+
                 /*
                  * Verify that the specified address region actually belongs
                  * to this process.
                  */
-                vma = find_vma (current->mm, addr);
                 ret = -EINVAL;
-                /* Check for overflow.  */
-                if (addr + len < addr)
-                        goto out;
-                if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end)
-                        goto out;
+                down_read(&current->mm->mmap_sem);
+                vma = find_vma(current->mm, addr);
+                if (!vma || addr < vma->vm_start || addr + len > vma->vm_end)
+                        goto out_unlock;
         }
 
         if (CPU_IS_020_OR_030) {
@@ -429,7 +432,7 @@ sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
                         __asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr));
                 }
                 ret = 0;
-                goto out;
+                goto out_unlock;
         } else {
             /*
              * 040 or 060: don't blindly trust 'scope', someone could
@@ -446,6 +449,8 @@ sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
                 ret = cache_flush_060 (addr, scope, cache, len);
             }
         }
+out_unlock:
+        up_read(&current->mm->mmap_sem);
 out:
         return ret;
 }
diff --git a/arch/m68k/kernel/syscalltable.S b/arch/m68k/kernel/syscalltable.S
index 501e10212789..05b46c2b08b8 100644
--- a/arch/m68k/kernel/syscalltable.S
+++ b/arch/m68k/kernel/syscalltable.S
@@ -372,4 +372,6 @@ ENTRY(sys_call_table)
         .long sys_sched_setattr
         .long sys_sched_getattr         /* 350 */
         .long sys_renameat2
+        .long sys_getrandom
+        .long sys_memfd_create
 
diff --git a/arch/m68k/mm/hwtest.c b/arch/m68k/mm/hwtest.c
index 2c7dde3c6430..fb8be4dd38c4 100644
--- a/arch/m68k/mm/hwtest.c
+++ b/arch/m68k/mm/hwtest.c
@@ -25,29 +25,32 @@
 
 #include <linux/module.h>
 
-int hwreg_present( volatile void *regp )
+int hwreg_present(volatile void *regp)
 {
-    int ret = 0;
-    long        save_sp, save_vbr;
-    long        tmp_vectors[3];
+        int ret = 0;
+        unsigned long flags;
+        long save_sp, save_vbr;
+        long tmp_vectors[3];
 
-    __asm__ __volatile__
-        (       "movec  %/vbr,%2\n\t"
-                "movel  #Lberr1,%4@(8)\n\t"
-                "movec  %4,%/vbr\n\t"
-                "movel  %/sp,%1\n\t"
-                "moveq  #0,%0\n\t"
-                "tstb   %3@\n\t"
+        local_irq_save(flags);
+        __asm__ __volatile__ (
+                "movec %/vbr,%2\n\t"
+                "movel #Lberr1,%4@(8)\n\t"
+                "movec %4,%/vbr\n\t"
+                "movel %/sp,%1\n\t"
+                "moveq #0,%0\n\t"
+                "tstb %3@\n\t"
                 "nop\n\t"
-                "moveq  #1,%0\n"
-                "Lberr1:\n\t"
-                "movel  %1,%/sp\n\t"
-                "movec  %2,%/vbr"
+                "moveq #1,%0\n"
+        "Lberr1:\n\t"
+                "movel %1,%/sp\n\t"
+                "movec %2,%/vbr"
                 : "=&d" (ret), "=&r" (save_sp), "=&r" (save_vbr)
                 : "a" (regp), "a" (tmp_vectors)
-                );
+        );
+        local_irq_restore(flags);
 
-    return( ret );
+        return ret;
 }
 EXPORT_SYMBOL(hwreg_present);
 
@@ -55,31 +58,36 @@ EXPORT_SYMBOL(hwreg_present);
  * by a bus error handler. Returns 1 if successful, 0 otherwise.
  */
 
-int hwreg_write( volatile void *regp, unsigned short val )
+int hwreg_write(volatile void *regp, unsigned short val)
 {
-        int             ret;
-        long    save_sp, save_vbr;
-        long    tmp_vectors[3];
+        int ret;
+        unsigned long flags;
+        long save_sp, save_vbr;
+        long tmp_vectors[3];
 
-        __asm__ __volatile__
-        (       "movec  %/vbr,%2\n\t"
-                "movel  #Lberr2,%4@(8)\n\t"
-                "movec  %4,%/vbr\n\t"
-                "movel  %/sp,%1\n\t"
-                "moveq  #0,%0\n\t"
-                "movew  %5,%3@\n\t"
-                "nop    \n\t"   /* If this nop isn't present, 'ret' may already be
-                                 * loaded with 1 at the time the bus error
-                                 * happens! */
-                "moveq  #1,%0\n"
+        local_irq_save(flags);
+        __asm__ __volatile__ (
+                "movec %/vbr,%2\n\t"
+                "movel #Lberr2,%4@(8)\n\t"
+                "movec %4,%/vbr\n\t"
+                "movel %/sp,%1\n\t"
+                "moveq #0,%0\n\t"
+                "movew %5,%3@\n\t"
+                "nop\n\t"
+                /*
+                 * If this nop isn't present, 'ret' may already be loaded
+                 * with 1 at the time the bus error happens!
+                 */
+                "moveq #1,%0\n"
         "Lberr2:\n\t"
-                "movel  %1,%/sp\n\t"
-                "movec  %2,%/vbr"
+                "movel %1,%/sp\n\t"
+                "movec %2,%/vbr"
                 : "=&d" (ret), "=&r" (save_sp), "=&r" (save_vbr)
                 : "a" (regp), "a" (tmp_vectors), "g" (val)
         );
+        local_irq_restore(flags);
 
-        return( ret );
+        return ret;
 }
 EXPORT_SYMBOL(hwreg_write);
 
diff --git a/arch/metag/include/asm/Kbuild b/arch/metag/include/asm/Kbuild
index c29ead89a317..7b8111c8f937 100644
--- a/arch/metag/include/asm/Kbuild
+++ b/arch/metag/include/asm/Kbuild
@@ -19,6 +19,7 @@ generic-y += ioctl.h
 generic-y += ioctls.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += kvm_para.h
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 40e1c1dd0e24..6feded3b0c4c 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -127,7 +127,7 @@ config SECCOMP
 
 endmenu
 
-menu "Advanced setup"
+menu "Kernel features"
 
 config ADVANCED_OPTIONS
         bool "Prompt for advanced kernel configuration options"
@@ -248,10 +248,10 @@ config MICROBLAZE_64K_PAGES
 
 endchoice
 
-endmenu
-
 source "mm/Kconfig"
 
+endmenu
+
 menu "Executable file formats"
 
 source "fs/Kconfig.binfmt"
diff --git a/arch/microblaze/include/asm/Kbuild b/arch/microblaze/include/asm/Kbuild
index 27a3acda6c19..448143b8cabd 100644
--- a/arch/microblaze/include/asm/Kbuild
+++ b/arch/microblaze/include/asm/Kbuild
@@ -5,6 +5,7 @@ generic-y += cputime.h
 generic-y += device.h
 generic-y += exec.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
 generic-y += scatterlist.h
diff --git a/arch/microblaze/include/asm/entry.h b/arch/microblaze/include/asm/entry.h
index b4a4cb150aa9..596e485ae707 100644
--- a/arch/microblaze/include/asm/entry.h
+++ b/arch/microblaze/include/asm/entry.h
@@ -15,6 +15,7 @@
 
 #include <asm/percpu.h>
 #include <asm/ptrace.h>
+#include <linux/linkage.h>
 
 /*
  * These are per-cpu variables required in entry.S, among other
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 0aa005703a0b..59a89a64a865 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -98,13 +98,13 @@ static inline int access_ok(int type, const void __user *addr,
 
         if ((get_fs().seg < ((unsigned long)addr)) ||
                         (get_fs().seg < ((unsigned long)addr + size - 1))) {
-                pr_debug("ACCESS fail: %s at 0x%08x (size 0x%x), seg 0x%08x\n",
+                pr_devel("ACCESS fail: %s at 0x%08x (size 0x%x), seg 0x%08x\n",
                         type ? "WRITE" : "READ ", (__force u32)addr, (u32)size,
                         (u32)get_fs().seg);
                 return 0;
         }
 ok:
-        pr_debug("ACCESS OK: %s at 0x%08x (size 0x%x), seg 0x%08x\n",
+        pr_devel("ACCESS OK: %s at 0x%08x (size 0x%x), seg 0x%08x\n",
                         type ? "WRITE" : "READ ", (__force u32)addr, (u32)size,
                         (u32)get_fs().seg);
         return 1;
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index fd56a8f66489..ea4b233647c1 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -38,6 +38,6 @@
 
 #endif /* __ASSEMBLY__ */
 
-#define __NR_syscalls         381
+#define __NR_syscalls         387
 
 #endif /* _ASM_MICROBLAZE_UNISTD_H */
diff --git a/arch/microblaze/include/uapi/asm/unistd.h b/arch/microblaze/include/uapi/asm/unistd.h
index 4e1ddc930a68..1c2380bf8fe6 100644
--- a/arch/microblaze/include/uapi/asm/unistd.h
+++ b/arch/microblaze/include/uapi/asm/unistd.h
@@ -399,5 +399,8 @@
 #define __NR_sched_setattr      381
 #define __NR_sched_getattr      382
 #define __NR_renameat2          383
+#define __NR_seccomp            384
+#define __NR_getrandom          385
+#define __NR_memfd_create       386
 
 #endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index 1a23d5d5480c..de59ee1d7010 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -384,3 +384,6 @@ ENTRY(sys_call_table)
         .long sys_sched_setattr
         .long sys_sched_getattr
         .long sys_renameat2
+        .long sys_seccomp
+        .long sys_getrandom             /* 385 */
+        .long sys_memfd_create
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index df51e78a72cc..574c43000699 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -546,6 +546,7 @@ config SGI_IP28
         # select SYS_HAS_EARLY_PRINTK
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
+        select MIPS_L1_CACHE_SHIFT_7
       help
         This is the SGI Indigo2 with R10000 processor.  To compile a Linux
         kernel that runs on these, say Y here.
@@ -2029,7 +2030,9 @@ config MIPS_CMP
         bool "MIPS CMP framework support (DEPRECATED)"
         depends on SYS_SUPPORTS_MIPS_CMP
         select MIPS_GIC_IPI
+        select SMP
         select SYNC_R4K
+        select SYS_SUPPORTS_SMP
         select WEAK_ORDERING
         default n
         help
@@ -2396,8 +2399,6 @@ source "kernel/Kconfig.preempt"
 
 config KEXEC
         bool "Kexec system call"
-        select CRYPTO
-        select CRYPTO_SHA256
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9336509f47ad..bbac51e11179 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -113,7 +113,16 @@ predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
 cflags-$(CONFIG_CPU_BIG_ENDIAN)         += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
 cflags-$(CONFIG_CPU_LITTLE_ENDIAN)      += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
 
-cflags-$(CONFIG_CPU_HAS_SMARTMIPS)      += $(call cc-option,-msmartmips)
+# For smartmips configurations, there are hundreds of warnings due to ISA overrides
+# in assembly and header files. smartmips is only supported for MIPS32r1 onwards
+# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
+# similar directives in the kernel will spam the build logs with the following warnings:
+# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
+# or
+# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
+# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
+# been fixed properly.
+cflags-$(CONFIG_CPU_HAS_SMARTMIPS)      += $(call cc-option,-msmartmips) -Wa,--no-warn
 cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
 
 cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index 776188908dfc..8c13675a12e7 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -847,6 +847,7 @@ int __init db1200_dev_setup(void)
                         pr_warn("DB1200: cant get I2C close to 50MHz\n");
                 else
                         clk_set_rate(c, pfc);
+                clk_prepare_enable(c);
                 clk_put(c);
         }
 
@@ -922,11 +923,6 @@ int __init db1200_dev_setup(void)
         }
 
         /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
-        c = clk_get(NULL, "psc1_intclk");
-        if (!IS_ERR(c)) {
-                clk_prepare_enable(c);
-                clk_put(c);
-        }
         __raw_writel(PSC_SEL_CLK_SERCLK,
             (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
         wmb();
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 2b63e7e7d3d3..c00585d915bc 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -59,12 +59,21 @@ static void bcm47xx_machine_restart(char *command)
         switch (bcm47xx_bus_type) {
 #ifdef CONFIG_BCM47XX_SSB
         case BCM47XX_BUS_TYPE_SSB:
-                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 3);
+                if (bcm47xx_bus.ssb.chip_id == 0x4785)
+                        write_c0_diag4(1 << 22);
+                ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
+                if (bcm47xx_bus.ssb.chip_id == 0x4785) {
+                        __asm__ __volatile__(
+                                ".set\tmips3\n\t"
+                                "sync\n\t"
+                                "wait\n\t"
+                                ".set\tmips0");
+                }
                 break;
 #endif
 #ifdef CONFIG_BCM47XX_BCMA
         case BCM47XX_BUS_TYPE_BCMA:
-                bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 3);
+                bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
                 break;
 #endif
         }
@@ -202,6 +211,10 @@ static void __init bcm47xx_register_bcma(void)
 
         err = bcma_host_soc_register(&bcm47xx_bus.bcma);
         if (err)
+                panic("Failed to register BCMA bus (err %d)", err);
+
+        err = bcma_host_soc_init(&bcm47xx_bus.bcma);
+        if (err)
                 panic("Failed to initialize BCMA bus (err %d)", err);
 
         bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 37eb2d1fa69a..b94bf44d8d8e 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -434,7 +434,7 @@ static void bcm63xx_init_irq(void)
                 irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
                 irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
                 irq_stat_addr[1] = 0;
-                irq_stat_addr[1] = 0;
+                irq_mask_addr[1] = 0;
                 irq_bits = 32;
                 ext_irq_count = 4;
                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
@@ -443,7 +443,7 @@ static void bcm63xx_init_irq(void)
                 irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
                 irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
                 irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
-                irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1);
+                irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1);
                 irq_bits = 64;
                 ext_irq_count = 4;
                 is_ext_irq_cascaded = 1;
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index b49c7adbfa89..31903cf9709d 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -13,6 +13,7 @@
 
 #include <linux/types.h>
 #include <linux/kernel.h>
+#include <linux/string.h>
 
 #include <asm/addrspace.h>
 
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 602866657938..c370426a7322 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -1,7 +1,7 @@
 if CPU_CAVIUM_OCTEON
 
 config CAVIUM_CN63XXP1
-        bool "Enable CN63XXP1 errata worarounds"
+        bool "Enable CN63XXP1 errata workarounds"
         default "n"
         help
           The CN63XXP1 chip requires build time workarounds to
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 008e9c8b8eac..38f4c32e2816 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -263,7 +263,6 @@ static uint64_t crashk_size, crashk_base;
 static int octeon_uart;
 
 extern asmlinkage void handle_int(void);
-extern asmlinkage void plat_irq_dispatch(void);
 
 /**
  * Return non zero if we are currently running in the Octeon simulator
@@ -458,6 +457,18 @@ static void octeon_halt(void)
         octeon_kill_core(NULL);
 }
 
+static char __read_mostly octeon_system_type[80];
+
+static int __init init_octeon_system_type(void)
+{
+        snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
+                cvmx_board_type_to_string(octeon_bootinfo->board_type),
+                octeon_model_get_string(read_c0_prid()));
+
+        return 0;
+}
+early_initcall(init_octeon_system_type);
+
 /**
  * Return a string representing the system type
  *
@@ -465,11 +476,7 @@ static void octeon_halt(void)
  */
 const char *octeon_board_type_string(void)
 {
-        static char name[80];
-        sprintf(name, "%s (%s)",
-                cvmx_board_type_to_string(octeon_bootinfo->board_type),
-                octeon_model_get_string(read_c0_prid()));
-        return name;
+        return octeon_system_type;
 }
 
 const char *get_system_type(void)
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
index 8f219dac9598..e24feb0633aa 100644
--- a/arch/mips/configs/gpr_defconfig
+++ b/arch/mips/configs/gpr_defconfig
@@ -19,6 +19,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PCI=y
 CONFIG_BINFMT_MISC=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index cc0756021398..48e16d98b2cc 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -28,6 +28,7 @@ CONFIG_MIPS32_COMPAT=y
 CONFIG_MIPS32_O32=y
 CONFIG_MIPS32_N32=y
 CONFIG_PM=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index 2575302aa2be..4f37a5985459 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -18,6 +18,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_BINFMT_MISC=m
 CONFIG_PM=y
+CONFIG_NET=y
 CONFIG_PACKET=m
 CONFIG_UNIX=y
 CONFIG_NET_KEY=m
diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig
index 4cb787ff273e..1c6191ebd583 100644
--- a/arch/mips/configs/loongson3_defconfig
+++ b/arch/mips/configs/loongson3_defconfig
@@ -59,6 +59,7 @@ CONFIG_MIPS32_COMPAT=y
 CONFIG_MIPS32_O32=y
 CONFIG_MIPS32_N32=y
 CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index e18741ea1771..f57b96dcf7df 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -19,6 +19,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_PCI=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig
index cf0e01f814e1..d41742dd26c8 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -20,6 +20,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_PCI=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig b/arch/mips/configs/malta_kvm_guest_defconfig
index edd9ec9cb678..a7806e83ea0f 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -19,6 +19,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_PCI=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index d269a5326a30..9b6926d6bb32 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -27,6 +27,7 @@ CONFIG_PD6729=m
 CONFIG_I82092=m
 CONFIG_BINFMT_MISC=m
 CONFIG_PM=y
+CONFIG_NET=y
 CONFIG_PACKET=m
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
index 2f660e9a0da6..70509a48df82 100644
--- a/arch/mips/configs/nlm_xlp_defconfig
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -63,6 +63,7 @@ CONFIG_MIPS32_O32=y
 CONFIG_MIPS32_N32=y
 CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index c6f84655c98a..82207e8079f3 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -43,6 +43,7 @@ CONFIG_PCI_DEBUG=y
 CONFIG_BINFMT_MISC=m
 CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index 29d79ae8a823..db029f4ff759 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -20,6 +20,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_PCI=y
 CONFIG_BINFMT_MISC=m
 CONFIG_PM=y
+CONFIG_NET=y
 CONFIG_PACKET=m
 CONFIG_UNIX=y
 CONFIG_NET_KEY=m
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 335e5290ec75..57012ef1f51e 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -3,6 +3,7 @@ generic-y += cputime.h
 generic-y += current.h
 generic-y += emergency-restart.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += local64.h
 generic-y += mcs_spinlock.h
 generic-y += mutex.h
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index d0352983b94d..51f80bd36fcc 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -16,8 +16,8 @@
 extern void octeon_cop2_save(struct octeon_cop2_state *);
 extern void octeon_cop2_restore(struct octeon_cop2_state *);
 
-#define cop2_save(r)            octeon_cop2_save(r)
-#define cop2_restore(r)         octeon_cop2_restore(r)
+#define cop2_save(r)            octeon_cop2_save(&(r)->thread.cp2)
+#define cop2_restore(r)         octeon_cop2_restore(&(r)->thread.cp2)
 
 #define cop2_present            1
 #define cop2_lazy_restore       1
@@ -26,26 +26,26 @@ extern void octeon_cop2_restore(struct octeon_cop2_state *);
 
 extern void nlm_cop2_save(struct nlm_cop2_state *);
 extern void nlm_cop2_restore(struct nlm_cop2_state *);
-#define cop2_save(r)            nlm_cop2_save(r)
-#define cop2_restore(r)         nlm_cop2_restore(r)
+
+#define cop2_save(r)            nlm_cop2_save(&(r)->thread.cp2)
+#define cop2_restore(r)         nlm_cop2_restore(&(r)->thread.cp2)
 
 #define cop2_present            1
 #define cop2_lazy_restore       0
 
 #elif defined(CONFIG_CPU_LOONGSON3)
 
-#define cop2_save(r)
-#define cop2_restore(r)
-
 #define cop2_present            1
 #define cop2_lazy_restore       1
+#define cop2_save(r)            do { (r); } while (0)
+#define cop2_restore(r)         do { (r); } while (0)
 
 #else
 
 #define cop2_present            0
 #define cop2_lazy_restore       0
-#define cop2_save(r)
-#define cop2_restore(r)
+#define cop2_save(r)            do { (r); } while (0)
+#define cop2_restore(r)         do { (r); } while (0)
 #endif
 
 enum cu2_ops {
diff --git a/arch/mips/include/asm/eva.h b/arch/mips/include/asm/eva.h
new file mode 100644
index 000000000000..a3d1807f227c
--- /dev/null
+++ b/arch/mips/include/asm/eva.h
@@ -0,0 +1,43 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014, Imagination Technologies Ltd.
+ *
+ * EVA functions for generic code
+ */
+
+#ifndef _ASM_EVA_H
+#define _ASM_EVA_H
+
+#include <kernel-entry-init.h>
+
+#ifdef __ASSEMBLY__
+
+#ifdef CONFIG_EVA
+
+/*
+ * EVA early init code
+ *
+ * Platforms must define their own 'platform_eva_init' macro in
+ * their kernel-entry-init.h header. This macro usually does the
+ * platform specific configuration of the segmentation registers,
+ * and it is normally called from assembly code.
+ *
+ */
+
+.macro eva_init
+platform_eva_init
+.endm
+
+#else
+
+.macro eva_init
+.endm
+
+#endif /* CONFIG_EVA */
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 3f20b2111d56..d7699cf7e135 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -49,7 +49,7 @@
 #endif
 #define GICBIS(reg, mask, bits)                 \
         do { u32 data;                          \
-                GICREAD((reg), data);           \
+                GICREAD(reg, data);             \
                 data &= ~(mask);                \
                 data |= ((bits) & (mask));      \
                 GICWRITE((reg), data);          \
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index ae1f7b24dd1a..39f07aec640c 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -26,6 +26,8 @@ static inline int irq_canonicalize(int irq)
 #define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
 #endif
 
+asmlinkage void plat_irq_dispatch(void);
+
 extern void do_IRQ(unsigned int irq);
 
 extern void arch_init_irq(void);
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 7a3fc67bd7f9..f2c249796ea8 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -96,11 +96,6 @@
 #define CAUSEB_DC                       27
 #define CAUSEF_DC                       (_ULCAST_(1) << 27)
 
-struct kvm;
-struct kvm_run;
-struct kvm_vcpu;
-struct kvm_interrupt;
-
 extern atomic_t kvm_mips_instance;
 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
@@ -767,5 +762,16 @@ extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
 
+static inline void kvm_arch_hardware_disable(void) {}
+static inline void kvm_arch_hardware_unsetup(void) {}
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_free_memslot(struct kvm *kvm,
+                struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
+static inline void kvm_arch_memslots_updated(struct kvm *kvm) {}
+static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
+static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
+                struct kvm_memory_slot *slot) {}
+static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
 
 #endif /* __MIPS_KVM_HOST_H__ */
diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
index 5d6a76434d00..c4a912733b65 100644
--- a/arch/mips/include/asm/mach-ip28/spaces.h
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -11,15 +11,8 @@
 #ifndef _ASM_MACH_IP28_SPACES_H
 #define _ASM_MACH_IP28_SPACES_H
 
-#define CAC_BASE        _AC(0xa800000000000000, UL)
-
-#define HIGHMEM_START   (~0UL)
-
 #define PHYS_OFFSET     _AC(0x20000000, UL)
 
-#define UNCAC_BASE      _AC(0xc0000000, UL)     /* 0xa0000000 + PHYS_OFFSET */
-#define IO_BASE         UNCAC_BASE
-
 #include <asm/mach-generic/spaces.h>
 
 #endif /* _ASM_MACH_IP28_SPACES_H */
diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
index 77eeda77e73c..0cf8622db27f 100644
--- a/arch/mips/include/asm/mach-malta/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -10,14 +10,15 @@
 #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
 #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
 
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
         /*
          * Prepare segments for EVA boot:
          *
          * This is in case the processor boots in legacy configuration
          * (SI_EVAReset is de-asserted and CONFIG5.K == 0)
          *
-         * On entry, t1 is loaded with CP0_CONFIG
-         *
          * ========================= Mappings =============================
          * Virtual memory           Physical memory           Mapping
          * 0x00000000 - 0x7fffffff  0x80000000 - 0xfffffffff   MUSUK (kuseg)
@@ -30,12 +31,20 @@
          *
          *
          * Lowmem is expanded to 2GB
+         *
+         * The following code uses the t0, t1, t2 and ra registers without
+         * previously preserving them.
+         *
          */
-        .macro  eva_entry
+        .macro  platform_eva_init
+
+        .set    push
+        .set    reorder
         /*
          * Get Config.K0 value and use it to program
          * the segmentation registers
          */
+        mfc0    t1, CP0_CONFIG
         andi    t1, 0x7 /* CCA */
         move    t2, t1
         ins     t2, t1, 16, 3
@@ -77,6 +86,8 @@
         mtc0    t0, $16, 5
         sync
         jal     mips_ihb
+
+        .set    pop
         .endm
 
         .macro  kernel_entry_setup
@@ -95,7 +106,7 @@
         sll     t0, t0, 6   /* SC bit */
         bgez    t0, 9f
 
-        eva_entry
+        platform_eva_init
         b       0f
 9:
         /* Assume we came from YAMON... */
@@ -127,8 +138,7 @@ nonsc_processor:
 #ifdef CONFIG_EVA
         sync
         ehb
-        mfc0    t1, CP0_CONFIG
-        eva_entry
+        platform_eva_init
 #endif
         .endm
 
diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
index ceeb1f5e7129..0eb43c832b25 100644
--- a/arch/mips/include/asm/mach-netlogic/topology.h
+++ b/arch/mips/include/asm/mach-netlogic/topology.h
@@ -10,13 +10,6 @@
 
 #include <asm/mach-netlogic/multi-node.h>
 
-#ifdef CONFIG_SMP
-#define topology_physical_package_id(cpu)       cpu_to_node(cpu)
-#define topology_core_id(cpu)   (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
-#define topology_thread_cpumask(cpu)            (&cpu_sibling_map[cpu])
-#define topology_core_cpumask(cpu)      cpumask_of_node(cpu_to_node(cpu))
-#endif
-
 #include <asm-generic/topology.h>
 
 #endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 5699ec3a71af..3be81803595d 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -37,7 +37,7 @@
 
 /*
  * This is used for calculating the real page sizes
- * for FTLB or VTLB + FTLB confugrations.
+ * for FTLB or VTLB + FTLB configurations.
  */
 static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
 {
@@ -223,7 +223,8 @@ static inline int pfn_valid(unsigned long pfn)
 
 #endif
 
-#define virt_to_page(kaddr)     pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
+#define virt_to_page(kaddr)     pfn_to_page(PFN_DOWN(virt_to_phys((void *)     \
+                                                                  (kaddr))))
 
 extern int __virt_addr_valid(const volatile void *kaddr);
 #define virt_addr_valid(kaddr)                                          \
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 027c74db13f9..df49a308085c 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -122,6 +122,9 @@ do {									\
         }                                                               \
 } while(0)
 
+extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
+        pte_t pteval);
+
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 
 #define pte_none(pte)           (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
@@ -145,7 +148,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
                 }
         }
 }
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
 
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
@@ -183,7 +185,6 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
         }
 #endif
 }
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
 
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
@@ -390,15 +391,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 
 extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
         pte_t pte);
-extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
-        pte_t pte);
 
 static inline void update_mmu_cache(struct vm_area_struct *vma,
         unsigned long address, pte_t *ptep)
 {
         pte_t pte = *ptep;
         __update_tlb(vma, address, pte);
-        __update_cache(vma, address, pte);
 }
 
 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 1e0f20a9cdda..eacf865d21c2 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,11 +37,6 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define NO_PROC_ID      (-1)
 
-#define topology_physical_package_id(cpu)       (cpu_data[cpu].package)
-#define topology_core_id(cpu)                   (cpu_data[cpu].core)
-#define topology_core_cpumask(cpu)              (&cpu_core_map[cpu])
-#define topology_thread_cpumask(cpu)            (&cpu_sibling_map[cpu])
-
 #define SMP_RESCHEDULE_YOURSELF 0x1     /* XXX braindead */
 #define SMP_CALL_FUNCTION       0x2
 /* Octeon - Tell another core to flush its icache */
diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
deleted file mode 100644
index 3adac3b53d19..000000000000
--- a/arch/mips/include/asm/suspend.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_SUSPEND_H
-#define __ASM_SUSPEND_H
-
-/* References to section boundaries */
-extern const void __nosave_begin, __nosave_end;
-
-#endif /* __ASM_SUSPEND_H */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index 495c1041a2cc..b928b6f898cd 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -92,7 +92,7 @@ do {									\
                         KSTK_STATUS(prev) &= ~ST0_CU2;                  \
                 __c0_stat = read_c0_status();                           \
                 write_c0_status(__c0_stat | ST0_CU2);                   \
-                cop2_save(&prev->thread.cp2);                           \
+                cop2_save(prev);                                        \
                 write_c0_status(__c0_stat & ~ST0_CU2);                  \
         }                                                               \
         __clear_software_ll_bit();                                      \
@@ -111,7 +111,7 @@ do {									\
                         (KSTK_STATUS(current) & ST0_CU2)) {             \
                 __c0_stat = read_c0_status();                           \
                 write_c0_status(__c0_stat | ST0_CU2);                   \
-                cop2_restore(&current->thread.cp2);                     \
+                cop2_restore(current);                                  \
                 write_c0_status(__c0_stat & ~ST0_CU2);                  \
         }                                                               \
         if (cpu_has_dsp)                                                \
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 17960fe7a8ce..cdf68b33bd65 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -131,10 +131,12 @@ static inline int syscall_get_arch(void)
 {
         int arch = EM_MIPS;
 #ifdef CONFIG_64BIT
-        if (!test_thread_flag(TIF_32BIT_REGS))
+        if (!test_thread_flag(TIF_32BIT_REGS)) {
                 arch |= __AUDIT_ARCH_64BIT;
-        if (test_thread_flag(TIF_32BIT_ADDR))
-                arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
+                /* N32 sets only TIF_32BIT_ADDR */
+                if (test_thread_flag(TIF_32BIT_ADDR))
+                        arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
+        }
 #endif
 #if defined(__LITTLE_ENDIAN)
         arch |=  __AUDIT_ARCH_LE;
diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h
index 20ea4859c822..3e307ec2afba 100644
--- a/arch/mips/include/asm/topology.h
+++ b/arch/mips/include/asm/topology.h
@@ -9,5 +9,13 @@
 #define __ASM_TOPOLOGY_H
 
 #include <topology.h>
+#include <linux/smp.h>
+
+#ifdef CONFIG_SMP
+#define topology_physical_package_id(cpu)       (cpu_data[cpu].package)
+#define topology_core_id(cpu)                   (cpu_data[cpu].core)
+#define topology_core_cpumask(cpu)              (&cpu_core_map[cpu])
+#define topology_thread_cpumask(cpu)            (&cpu_sibling_map[cpu])
+#endif
 
 #endif /* __ASM_TOPOLOGY_H */
diff --git a/arch/mips/include/uapi/asm/ioctls.h b/arch/mips/include/uapi/asm/ioctls.h
index b1e637757fe3..740219c2c894 100644
--- a/arch/mips/include/uapi/asm/ioctls.h
+++ b/arch/mips/include/uapi/asm/ioctls.h
@@ -81,6 +81,8 @@
 #define TCSETS2         _IOW('T', 0x2B, struct termios2)
 #define TCSETSW2        _IOW('T', 0x2C, struct termios2)
 #define TCSETSF2        _IOW('T', 0x2D, struct termios2)
+#define TIOCGRS485      _IOR('T', 0x2E, struct serial_rs485)
+#define TIOCSRS485      _IOWR('T', 0x2F, struct serial_rs485)
 #define TIOCGPTN        _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
 #define TIOCGDEV        _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index 9bc13eaf9d67..fdb4923777d1 100644
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -373,16 +373,18 @@
 #define __NR_sched_getattr              (__NR_Linux + 350)
 #define __NR_renameat2                  (__NR_Linux + 351)
 #define __NR_seccomp                    (__NR_Linux + 352)
+#define __NR_getrandom                  (__NR_Linux + 353)
+#define __NR_memfd_create               (__NR_Linux + 354)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             352
+#define __NR_Linux_syscalls             354
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         352
+#define __NR_O32_Linux_syscalls         354
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -703,16 +705,18 @@
 #define __NR_sched_getattr              (__NR_Linux + 310)
 #define __NR_renameat2                  (__NR_Linux + 311)
 #define __NR_seccomp                    (__NR_Linux + 312)
+#define __NR_getrandom                  (__NR_Linux + 313)
+#define __NR_memfd_create               (__NR_Linux + 314)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             312
+#define __NR_Linux_syscalls             314
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          312
+#define __NR_64_Linux_syscalls          314
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -1037,15 +1041,17 @@
 #define __NR_sched_getattr              (__NR_Linux + 314)
 #define __NR_renameat2                  (__NR_Linux + 315)
 #define __NR_seccomp                    (__NR_Linux + 316)
+#define __NR_getrandom                  (__NR_Linux + 317)
+#define __NR_memfd_create               (__NR_Linux + 318)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             316
+#define __NR_Linux_syscalls             318
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         316
+#define __NR_N32_Linux_syscalls         318
 
 #endif /* _UAPI_ASM_UNISTD_H */
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 6f4f739dad96..e6e97d2a5c9e 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -13,6 +13,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/asmmacro.h>
 #include <asm/cacheops.h>
+#include <asm/eva.h>
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/pm.h>
@@ -166,6 +167,9 @@ dcache_done:
 1:      jal     mips_cps_core_init
          nop
 
+        /* Do any EVA initialization if necessary */
+        eva_init
+
         /*
          * Boot any other VPEs within this core that should be online, and
          * deactivate this VPE if it should be offline.
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c
index 992e18474da5..50980bf3983e 100644
--- a/arch/mips/kernel/machine_kexec.c
+++ b/arch/mips/kernel/machine_kexec.c
@@ -71,8 +71,12 @@ machine_kexec(struct kimage *image)
         kexec_start_address =
                 (unsigned long) phys_to_virt(image->start);
 
-        kexec_indirection_page =
-                (unsigned long) phys_to_virt(image->head & PAGE_MASK);
+        if (image->type == KEXEC_TYPE_DEFAULT) {
+                kexec_indirection_page =
+                        (unsigned long) phys_to_virt(image->head & PAGE_MASK);
+        } else {
+                kexec_indirection_page = (unsigned long)&image->head;
+        }
 
         memcpy((void*)reboot_code_buffer, relocate_new_kernel,
                relocate_new_kernel_size);
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 5d25462de8a6..2f7c734771f4 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -129,7 +129,11 @@ NESTED(_mcount, PT_SIZE, ra)
          nop
 #endif
         b       ftrace_stub
+#ifdef CONFIG_32BIT
+         addiu sp, sp, 8
+#else
          nop
+#endif
 
 static_trace:
         MCOUNT_SAVE_REGS
@@ -139,6 +143,9 @@ static_trace:
          move   a1, AT          /* arg2: parent's return address */
 
         MCOUNT_RESTORE_REGS
+#ifdef CONFIG_32BIT
+        addiu sp, sp, 8
+#endif
         .globl ftrace_stub
 ftrace_stub:
         RETURN_BACK
@@ -183,6 +190,11 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra)
         jal     prepare_ftrace_return
          nop
         MCOUNT_RESTORE_REGS
+#ifndef CONFIG_DYNAMIC_FTRACE
+#ifdef CONFIG_32BIT
+        addiu sp, sp, 8
+#endif
+#endif
         RETURN_BACK
         END(ftrace_graph_caller)
 
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 14bf74b0f51c..b63f2482f288 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -558,7 +558,7 @@ static int mipspmu_get_irq(void)
         if (mipspmu.irq >= 0) {
                 /* Request my own irq handler. */
                 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
-                        IRQF_PERCPU | IRQF_NOBALANCING,
+                        IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD,
                         "mips_perf_pmu", NULL);
                 if (err) {
                         pr_warning("Unable to request IRQ%d for MIPS "
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index f93b4cbec739..744cd10ba599 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -577,3 +577,5 @@ EXPORT(sys_call_table)
         PTR     sys_sched_getattr               /* 4350 */
         PTR     sys_renameat2
         PTR     sys_seccomp
+        PTR     sys_getrandom
+        PTR     sys_memfd_create
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 03ebd9979ad2..002b1bc09c38 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -432,4 +432,6 @@ EXPORT(sys_call_table)
         PTR     sys_sched_getattr               /* 5310 */
         PTR     sys_renameat2
         PTR     sys_seccomp
+        PTR     sys_getrandom
+        PTR     sys_memfd_create
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index ebc9228e2e15..ca6cbbe9805b 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -425,4 +425,6 @@ EXPORT(sysn32_call_table)
         PTR     sys_sched_getattr
         PTR     sys_renameat2                   /* 6315 */
         PTR     sys_seccomp
+        PTR     sys_getrandom
+        PTR     sys_memfd_create
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 13b964fddc4a..9e10d11fbb84 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -113,15 +113,19 @@ trace_a_syscall:
         move    s0, t2                  # Save syscall pointer
         move    a0, sp
         /*
-         * syscall number is in v0 unless we called syscall(__NR_###)
+         * absolute syscall number is in v0 unless we called syscall(__NR_###)
          * where the real syscall number is in a0
          * note: NR_syscall is the first O32 syscall but the macro is
          * only defined when compiling with -mabi=32 (CONFIG_32BIT)
          * therefore __NR_O32_Linux is used (4000)
          */
-        addiu   a1, v0,  __NR_O32_Linux
-        bnez    v0, 1f /* __NR_syscall at offset 0 */
-        lw      a1, PT_R4(sp)
+        .set    push
+        .set    reorder
+        subu    t1, v0,  __NR_O32_Linux
+        move    a1, v0
+        bnez    t1, 1f /* __NR_syscall at offset 0 */
+        lw      a1, PT_R4(sp) /* Arg1 for __NR_syscall case */
+        .set    pop
 
 1:      jal     syscall_trace_enter
 
@@ -558,4 +562,6 @@ EXPORT(sys32_call_table)
         PTR     sys_sched_getattr               /* 4350 */
         PTR     sys_renameat2
         PTR     sys_seccomp
+        PTR     sys_getrandom
+        PTR     sys_memfd_create
         .size   sys32_call_table,.-sys32_call_table
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
index cd7114147ae7..e3b21e51ff7e 100644
--- a/arch/mips/kvm/mips.c
+++ b/arch/mips/kvm/mips.c
@@ -77,24 +77,16 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
         return 1;
 }
 
-int kvm_arch_hardware_enable(void *garbage)
+int kvm_arch_hardware_enable(void)
 {
         return 0;
 }
 
-void kvm_arch_hardware_disable(void *garbage)
-{
-}
-
 int kvm_arch_hardware_setup(void)
 {
         return 0;
 }
 
-void kvm_arch_hardware_unsetup(void)
-{
-}
-
 void kvm_arch_check_processor_compat(void *rtn)
 {
         *(int *)rtn = 0;
@@ -163,10 +155,6 @@ void kvm_mips_free_vcpus(struct kvm *kvm)
         mutex_unlock(&kvm->lock);
 }
 
-void kvm_arch_sync_events(struct kvm *kvm)
-{
-}
-
 static void kvm_mips_uninit_tlbs(void *arg)
 {
         /* Restore wired count */
@@ -194,21 +182,12 @@ long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
         return -ENOIOCTLCMD;
 }
 
-void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
-                           struct kvm_memory_slot *dont)
-{
-}
-
 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
                             unsigned long npages)
 {
         return 0;
 }
 
-void kvm_arch_memslots_updated(struct kvm *kvm)
-{
-}
-
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                    struct kvm_memory_slot *memslot,
                                    struct kvm_userspace_memory_region *mem,
@@ -254,19 +233,6 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
         }
 }
 
-void kvm_arch_flush_shadow_all(struct kvm *kvm)
-{
-}
-
-void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
-                                   struct kvm_memory_slot *slot)
-{
-}
-
-void kvm_arch_flush_shadow(struct kvm *kvm)
-{
-}
-
 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 {
         int err, size, offset;
@@ -998,10 +964,6 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         return 0;
 }
 
-void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
-{
-}
-
 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
                                   struct kvm_translation *tr)
 {
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 8f1866d8124d..468ffa043607 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -221,7 +221,7 @@ void __init ltq_soc_init(void)
                 (request_mem_region(res_sys[2].start,
                                 resource_size(&res_sys[2]),
                                 res_sys[2].name) < 0))
-                pr_err("Failed to request core reources");
+                pr_err("Failed to request core resources");
 
         status_membase = ioremap_nocache(res_status.start,
                                         resource_size(&res_status));
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 51804b10a036..2b15491de494 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -318,7 +318,7 @@ void __init ltq_soc_init(void)
                                 res_cgu.name) < 0) ||
                 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
                                 res_ebu.name) < 0))
-                pr_err("Failed to request core reources");
+                pr_err("Failed to request core resources");
 
         pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
         ltq_cgu_membase = ioremap_nocache(res_cgu.start,
diff --git a/arch/mips/loongson/loongson-3/cop2-ex.c b/arch/mips/loongson/loongson-3/cop2-ex.c
index 9182e8d2967c..b03e37d2071a 100644
--- a/arch/mips/loongson/loongson-3/cop2-ex.c
+++ b/arch/mips/loongson/loongson-3/cop2-ex.c
@@ -22,13 +22,13 @@
 static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
         void *data)
 {
-        int fpu_enabled;
+        int fpu_owned;
         int fr = !test_thread_flag(TIF_32BIT_FPREGS);
 
         switch (action) {
         case CU2_EXCEPTION:
                 preempt_disable();
-                fpu_enabled = read_c0_status() & ST0_CU1;
+                fpu_owned = __is_fpu_owner();
                 if (!fr)
                         set_c0_status(ST0_CU1 | ST0_CU2);
                 else
@@ -39,8 +39,8 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
                         KSTK_STATUS(current) |= ST0_FR;
                 else
                         KSTK_STATUS(current) &= ~ST0_FR;
-                /* If FPU is enabled, we needn't init or restore fp */
-                if(!fpu_enabled) {
+                /* If FPU is owned, we needn't init or restore fp */
+                if (!fpu_owned) {
                         set_thread_flag(TIF_USEDFPU);
                         if (!used_math()) {
                                 _init_fpu();
diff --git a/arch/mips/loongson/loongson-3/numa.c b/arch/mips/loongson/loongson-3/numa.c
index ca025a6ba559..37ed184398c6 100644
--- a/arch/mips/loongson/loongson-3/numa.c
+++ b/arch/mips/loongson/loongson-3/numa.c
@@ -24,8 +24,6 @@
 #include <asm/page.h>
 #include <asm/pgalloc.h>
 #include <asm/sections.h>
-#include <linux/bootmem.h>
-#include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/bootinfo.h>
 #include <asm/mc146818-time.h>
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index bf0fc6b16ad9..7a4727795a70 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -650,9 +650,9 @@ static inline int cop1_64bit(struct pt_regs *xcp)
 #define SIFROMREG(si, x)                                                \
 do {                                                                    \
         if (cop1_64bit(xcp))                                            \
-                (si) = get_fpr32(&ctx->fpr[x], 0);                      \
+                (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
         else                                                            \
-                (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);         \
+                (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 } while (0)
 
 #define SITOREG(si, x)                                                  \
@@ -667,7 +667,7 @@ do {									\
         }                                                               \
 } while (0)
 
-#define SIFROMHREG(si, x)       ((si) = get_fpr32(&ctx->fpr[x], 1))
+#define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 
 #define SITOHREG(si, x)                                                 \
 do {                                                                    \
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index f7b91d3a371d..7e3ea7766822 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -119,25 +119,36 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
 
 EXPORT_SYMBOL(__flush_anon_page);
 
-void __update_cache(struct vm_area_struct *vma, unsigned long address,
-        pte_t pte)
+static void mips_flush_dcache_from_pte(pte_t pteval, unsigned long address)
 {
         struct page *page;
-        unsigned long pfn, addr;
-        int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
+        unsigned long pfn = pte_pfn(pteval);
 
-        pfn = pte_pfn(pte);
         if (unlikely(!pfn_valid(pfn)))
                 return;
+
         page = pfn_to_page(pfn);
         if (page_mapping(page) && Page_dcache_dirty(page)) {
-                addr = (unsigned long) page_address(page);
-                if (exec || pages_do_alias(addr, address & PAGE_MASK))
-                        flush_data_cache_page(addr);
+                unsigned long page_addr = (unsigned long) page_address(page);
+
+                if (!cpu_has_ic_fills_f_dc ||
+                    pages_do_alias(page_addr, address & PAGE_MASK))
+                        flush_data_cache_page(page_addr);
                 ClearPageDcacheDirty(page);
         }
 }
 
+void set_pte_at(struct mm_struct *mm, unsigned long addr,
+        pte_t *ptep, pte_t pteval)
+{
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
+                if (pte_present(pteval))
+                        mips_flush_dcache_from_pte(pteval, addr);
+        }
+
+        set_pte(ptep, pteval);
+}
+
 unsigned long _page_cachable_default;
 EXPORT_SYMBOL(_page_cachable_default);
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 571aab064936..f42e35e42790 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -53,6 +53,7 @@
  */
 unsigned long empty_zero_page, zero_page_mask;
 EXPORT_SYMBOL_GPL(empty_zero_page);
+EXPORT_SYMBOL(zero_page_mask);
 
 /*
  * Not static inline because used by IP27 special magic initialization code
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 0c35dee0a215..8fddd2cdbff7 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -35,13 +35,19 @@ fw_memblock_t * __init fw_getmdesc(int eva)
         /* otherwise look in the environment */
 
         memsize_str = fw_getenv("memsize");
-        if (memsize_str)
-                tmp = kstrtol(memsize_str, 0, &memsize);
+        if (memsize_str) {
+                tmp = kstrtoul(memsize_str, 0, &memsize);
+                if (tmp)
+                        pr_warn("Failed to read the 'memsize' env variable.\n");
+        }
         if (eva) {
         /* Look for ememsize for EVA */
                 ememsize_str = fw_getenv("ememsize");
-                if (ememsize_str)
-                        tmp = kstrtol(ememsize_str, 0, &ememsize);
+                if (ememsize_str) {
+                        tmp = kstrtoul(ememsize_str, 0, &ememsize);
+                        if (tmp)
+                                pr_warn("Failed to read the 'ememsize' env variable.\n");
+                }
         }
         if (!memsize && !ememsize) {
                 pr_warn("memsize not set in YAMON, set to default (32Mb)\n");
diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 05a56619ece2..7edc08398c4a 100644
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -765,27 +765,6 @@ static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
         return (u64)err << 32 | ntohl(ret);
 }
 
-#ifdef __BIG_ENDIAN_BITFIELD
-#define PKT_TYPE_MAX    (7 << 5)
-#else
-#define PKT_TYPE_MAX    7
-#endif
-static int pkt_type_offset(void)
-{
-        struct sk_buff skb_probe = {
-                .pkt_type = ~0,
-        };
-        u8 *ct = (u8 *)&skb_probe;
-        unsigned int off;
-
-        for (off = 0; off < sizeof(struct sk_buff); off++) {
-                if (ct[off] == PKT_TYPE_MAX)
-                        return off;
-        }
-        pr_err_once("Please fix pkt_type_offset(), as pkt_type couldn't be found\n");
-        return -1;
-}
-
 static int build_body(struct jit_ctx *ctx)
 {
         void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
@@ -1332,11 +1311,7 @@ jmp_cmp:
                 case BPF_ANC | SKF_AD_PKTTYPE:
                         ctx->flags |= SEEN_SKB;
 
-                        off = pkt_type_offset();
-
-                        if (off < 0)
-                                return -1;
-                        emit_load_byte(r_tmp, r_skb, off, ctx);
+                        emit_load_byte(r_tmp, r_skb, PKT_TYPE_OFFSET(), ctx);
                         /* Keep only the last 3 bits */
                         emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx);
 #ifdef __BIG_ENDIAN_BITFIELD
@@ -1417,7 +1392,7 @@ void bpf_jit_compile(struct bpf_prog *fp)
                 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
 
         fp->bpf_func = (void *)ctx.target;
-        fp->jited = 1;
+        fp->jited = true;
 
 out:
         kfree(ctx.offsets);
@@ -1427,5 +1402,6 @@ void bpf_jit_free(struct bpf_prog *fp)
 {
         if (fp->jited)
                 module_free(NULL, fp->bpf_func);
-        kfree(fp);
+
+        bpf_prog_unlock_free(fp);
 }
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index ab0c5d14c6f7..63bbe07a1ccd 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -73,8 +73,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
          * wants.  Most devices only want 1, which will give
          * configured_private_bits and request_private_bits equal 0.
          */
-        pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
-                             &control);
+        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 
         /*
          * If the number of private bits has been configured then use
@@ -176,8 +175,7 @@ msi_irq_allocated:
         /* Update the number of IRQs the device has available to it */
         control &= ~PCI_MSI_FLAGS_QSIZE;
         control |= request_private_bits << 4;
-        pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
-                              control);
+        pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 
         irq_set_msi_desc(irq, desc);
         write_msi_msg(irq, &msg);
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index cb1ef9984069..37fe8e7887e2 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -218,7 +218,7 @@ static int ltq_pci_probe(struct platform_device *pdev)
         res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
         if (!res_cfg || !res_bridge) {
-                dev_err(&pdev->dev, "missing memory reources\n");
+                dev_err(&pdev->dev, "missing memory resources\n");
                 return -EINVAL;
         }
 
diff --git a/arch/mips/pmcs-msp71xx/msp_irq.c b/arch/mips/pmcs-msp71xx/msp_irq.c
index 941744aabb51..f914c753de21 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq.c
@@ -51,7 +51,7 @@ static inline void sec_int_dispatch(void)  { do_IRQ(MSP_INT_SEC);  }
  * the range 40-71.
  */
 
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
 {
         u32 pending;
 
diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
index 521e5963df05..2129e67723ff 100644
--- a/arch/mips/power/cpu.c
+++ b/arch/mips/power/cpu.c
@@ -7,7 +7,7 @@
  * Author: Hu Hongbing <huhb@lemote.com>
  *         Wu Zhangjin <wuzhangjin@gmail.com>
  */
-#include <asm/suspend.h>
+#include <asm/sections.h>
 #include <asm/fpu.h>
 #include <asm/dsp.h>
 
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 9ff200ae1c9a..2791b8641df6 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -789,11 +789,11 @@ void __init txx9_iocled_init(unsigned long baseaddr,
         if (platform_device_add(pdev))
                 goto out_pdev;
         return;
+
 out_pdev:
         platform_device_put(pdev);
 out_gpio:
-        if (gpiochip_remove(&iocled->chip))
-                return;
+        gpiochip_remove(&iocled->chip);
 out_unmap:
         iounmap(iocled->mmioaddr);
 out_free:
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index a648de1b1096..4434b54e1d87 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -181,7 +181,7 @@ endmenu
 config SMP
         bool "Symmetric multi-processing support"
         default y
-        depends on MN10300_PROC_MN2WS0038 || MN10300_PROC_MN2WS0050
+        depends on MN10300_PROC_MN2WS0050
         ---help---
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, say N. If you have a system with more
diff --git a/arch/mn10300/include/asm/Kbuild b/arch/mn10300/include/asm/Kbuild
index ecbd6676bd33..54a062cb9f2c 100644
--- a/arch/mn10300/include/asm/Kbuild
+++ b/arch/mn10300/include/asm/Kbuild
@@ -4,7 +4,9 @@ generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += exec.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
 generic-y += scatterlist.h
+generic-y += sections.h
 generic-y += trace_clock.h
diff --git a/arch/mn10300/include/asm/sections.h b/arch/mn10300/include/asm/sections.h
deleted file mode 100644
index 2b8c5160388f..000000000000
--- a/arch/mn10300/include/asm/sections.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sections.h>
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 88e83368bbf5..e5a693b16da2 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -8,6 +8,7 @@ config OPENRISC
         select OF
         select OF_EARLY_FLATTREE
         select IRQ_DOMAIN
+        select HANDLE_DOMAIN_IRQ
         select HAVE_MEMBLOCK
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_ARCH_TRACEHOOK
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 480af0d9c2f5..89b61d7dc790 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -31,6 +31,7 @@ generic-y += ioctl.h
 generic-y += ioctls.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += kvm_para.h
diff --git a/arch/openrisc/include/asm/irq.h b/arch/openrisc/include/asm/irq.h
index b84634cc95eb..d9eee0a2b7b4 100644
--- a/arch/openrisc/include/asm/irq.h
+++ b/arch/openrisc/include/asm/irq.h
@@ -24,7 +24,6 @@
 
 #define NO_IRQ          (-1)
 
-void handle_IRQ(unsigned int, struct pt_regs *);
 extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
 
 #endif /* __ASM_OPENRISC_IRQ_H__ */
diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c
index 967eb1430203..35e478a93116 100644
--- a/arch/openrisc/kernel/irq.c
+++ b/arch/openrisc/kernel/irq.c
@@ -48,18 +48,6 @@ void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
         handle_arch_irq = handle_irq;
 }
 
-void handle_IRQ(unsigned int irq, struct pt_regs *regs)
-{
-        struct pt_regs *old_regs = set_irq_regs(regs);
-
-        irq_enter();
-
-        generic_handle_irq(irq);
-
-        irq_exit();
-        set_irq_regs(old_regs);
-}
-
 void __irq_entry do_IRQ(struct pt_regs *regs)
 {
         handle_arch_irq(regs);
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 6e75e2030927..1554a6f2a5bb 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -321,6 +321,22 @@ source "fs/Kconfig"
 
 source "arch/parisc/Kconfig.debug"
 
+config SECCOMP
+        def_bool y
+        prompt "Enable seccomp to safely compute untrusted bytecode"
+        ---help---
+          This kernel feature is useful for number crunching applications
+          that may need to compute untrusted bytecode during their
+          execution. By using pipes or other transports made available to
+          the process as file descriptors supporting the read/write
+          syscalls, it's possible to isolate those applications in
+          their own address space using seccomp. Once seccomp is
+          enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+          and the task is only allowed to execute a few safe syscalls
+          defined by each seccomp mode.
+
+          If unsure, say Y. Only embedded should say N here.
+
 source "security/Kconfig"
 
 source "crypto/Kconfig"
diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile
index 7187664034c3..5db8882f732c 100644
--- a/arch/parisc/Makefile
+++ b/arch/parisc/Makefile
@@ -48,7 +48,12 @@ cflags-y	:= -pipe
 
 # These flags should be implied by an hppa-linux configuration, but they
 # are not in gcc 3.2.
-cflags-y        += -mno-space-regs -mfast-indirect-calls
+cflags-y        += -mno-space-regs
+
+# -mfast-indirect-calls is only relevant for 32-bit kernels.
+ifndef CONFIG_64BIT
+cflags-y        += -mfast-indirect-calls
+endif
 
 # Currently we save and restore fpregs on all kernel entry/interruption paths.
 # If that gets optimized, we might need to disable the use of fpregs in the
diff --git a/arch/parisc/configs/a500_defconfig b/arch/parisc/configs/a500_defconfig
index 90025322b75e..0490199d7b15 100644
--- a/arch/parisc/configs/a500_defconfig
+++ b/arch/parisc/configs/a500_defconfig
@@ -31,6 +31,7 @@ CONFIG_PD6729=m
 CONFIG_I82092=m
 # CONFIG_SUPERIO is not set
 # CONFIG_CHASSIS_LCD_LED is not set
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/parisc/configs/c8000_defconfig b/arch/parisc/configs/c8000_defconfig
index 8249ac9d9cfc..269c23d23fcb 100644
--- a/arch/parisc/configs/c8000_defconfig
+++ b/arch/parisc/configs/c8000_defconfig
@@ -33,6 +33,7 @@ CONFIG_PCI_LBA=y
 # CONFIG_PDC_CHASSIS_WARN is not set
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/parisc/hpux/sys_hpux.c b/arch/parisc/hpux/sys_hpux.c
index d9dc6cd3b7d2..e5c4da035810 100644
--- a/arch/parisc/hpux/sys_hpux.c
+++ b/arch/parisc/hpux/sys_hpux.c
@@ -456,7 +456,7 @@ int hpux_sysfs(int opcode, unsigned long arg1, unsigned long arg2)
                 }
 
                 /* String could be altered by userspace after strlen_user() */
-                fsname[len] = '\0';
+                fsname[len - 1] = '\0';
 
                 printk(KERN_DEBUG "that is '%s' as (char *)\n", fsname);
                 if ( !strcmp(fsname, "hfs") ) {
diff --git a/arch/parisc/include/asm/Kbuild b/arch/parisc/include/asm/Kbuild
index ecf25e6678ad..ffb024b8423f 100644
--- a/arch/parisc/include/asm/Kbuild
+++ b/arch/parisc/include/asm/Kbuild
@@ -10,6 +10,7 @@ generic-y += exec.h
 generic-y += hash.h
 generic-y += hw_irq.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kvm_para.h
 generic-y += local.h
diff --git a/arch/parisc/include/asm/seccomp.h b/arch/parisc/include/asm/seccomp.h
new file mode 100644
index 000000000000..015f7887aa29
--- /dev/null
+++ b/arch/parisc/include/asm/seccomp.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_PARISC_SECCOMP_H
+#define _ASM_PARISC_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#define __NR_seccomp_read_32 __NR_read
+#define __NR_seccomp_write_32 __NR_write
+#define __NR_seccomp_exit_32 __NR_exit
+#define __NR_seccomp_sigreturn_32 __NR_rt_sigreturn
+
+#endif  /* _ASM_PARISC_SECCOMP_H */
diff --git a/arch/parisc/include/asm/thread_info.h b/arch/parisc/include/asm/thread_info.h
index 4b9b10ce1f9d..a84611835549 100644
--- a/arch/parisc/include/asm/thread_info.h
+++ b/arch/parisc/include/asm/thread_info.h
@@ -60,6 +60,7 @@ struct thread_info {
 #define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
 #define TIF_SINGLESTEP          9       /* single stepping? */
 #define TIF_BLOCKSTEP           10      /* branch stepping? */
+#define TIF_SECCOMP             11      /* secure computing */
 
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
@@ -70,11 +71,13 @@ struct thread_info {
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SINGLESTEP         (1 << TIF_SINGLESTEP)
 #define _TIF_BLOCKSTEP          (1 << TIF_BLOCKSTEP)
+#define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 
 #define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | \
                                  _TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_TRACE_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
-                                 _TIF_BLOCKSTEP | _TIF_SYSCALL_AUDIT)
+                                 _TIF_BLOCKSTEP | _TIF_SYSCALL_AUDIT | \
+                                 _TIF_SECCOMP)
 
 #ifdef CONFIG_64BIT
 # ifdef CONFIG_COMPAT
diff --git a/arch/parisc/include/uapi/asm/ioctls.h b/arch/parisc/include/uapi/asm/ioctls.h
index 66719c38a36b..b6572f051b67 100644
--- a/arch/parisc/include/uapi/asm/ioctls.h
+++ b/arch/parisc/include/uapi/asm/ioctls.h
@@ -50,6 +50,8 @@
 #define TCSETS2         _IOW('T',0x2B, struct termios2)
 #define TCSETSW2        _IOW('T',0x2C, struct termios2)
 #define TCSETSF2        _IOW('T',0x2D, struct termios2)
+#define TIOCGRS485      _IOR('T', 0x2E, struct serial_rs485)
+#define TIOCSRS485      _IOWR('T', 0x2F, struct serial_rs485)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
 #define TIOCGDEV        _IOR('T',0x32, int)  /* Get primary device node of /dev/console */
diff --git a/arch/parisc/include/uapi/asm/unistd.h b/arch/parisc/include/uapi/asm/unistd.h
index 47e0e21d2272..8667f18be238 100644
--- a/arch/parisc/include/uapi/asm/unistd.h
+++ b/arch/parisc/include/uapi/asm/unistd.h
@@ -830,8 +830,11 @@
 #define __NR_sched_getattr      (__NR_Linux + 335)
 #define __NR_utimes             (__NR_Linux + 336)
 #define __NR_renameat2          (__NR_Linux + 337)
+#define __NR_seccomp            (__NR_Linux + 338)
+#define __NR_getrandom          (__NR_Linux + 339)
+#define __NR_memfd_create       (__NR_Linux + 340)
 
-#define __NR_Linux_syscalls     (__NR_renameat2 + 1)
+#define __NR_Linux_syscalls     (__NR_memfd_create + 1)
 
 
 #define __IGNORE_select         /* newselect */
diff --git a/arch/parisc/kernel/ptrace.c b/arch/parisc/kernel/ptrace.c
index e842ee233db4..92438c21d453 100644
--- a/arch/parisc/kernel/ptrace.c
+++ b/arch/parisc/kernel/ptrace.c
@@ -17,6 +17,7 @@
 #include <linux/user.h>
 #include <linux/personality.h>
 #include <linux/security.h>
+#include <linux/seccomp.h>
 #include <linux/compat.h>
 #include <linux/signal.h>
 #include <linux/audit.h>
@@ -270,6 +271,9 @@ long do_syscall_trace_enter(struct pt_regs *regs)
 {
         long ret = 0;
 
+        /* Do the secure computing check first. */
+        secure_computing_strict(regs->gr[20]);
+
         if (test_thread_flag(TIF_SYSCALL_TRACE) &&
             tracehook_report_syscall_entry(regs))
                 ret = -1L;
diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index 838786011037..7ef22e3387e0 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -74,7 +74,7 @@ ENTRY(linux_gateway_page)
         /* ADDRESS 0xb0 to 0xb8, lws uses two insns for entry */
         /* Light-weight-syscall entry must always be located at 0xb0 */
         /* WARNING: Keep this number updated with table size changes */
-#define __NR_lws_entries (2)
+#define __NR_lws_entries (3)
 
 lws_entry:
         gate    lws_start, %r0          /* increase privilege */
@@ -502,7 +502,7 @@ lws_exit:
 
         
         /***************************************************
-                Implementing CAS as an atomic operation:
+                Implementing 32bit CAS as an atomic operation:
 
                 %r26 - Address to examine
                 %r25 - Old value to check (old)
@@ -659,6 +659,230 @@ cas_action:
         ASM_EXCEPTIONTABLE_ENTRY(2b-linux_gateway_page, 3b-linux_gateway_page)
 
 
+        /***************************************************
+                New CAS implementation which uses pointers and variable size
+                information. The value pointed by old and new MUST NOT change
+                while performing CAS. The lock only protect the value at %r26.
+
+                %r26 - Address to examine
+                %r25 - Pointer to the value to check (old)
+                %r24 - Pointer to the value to set (new)
+                %r23 - Size of the variable (0/1/2/3 for 8/16/32/64 bit)
+                %r28 - Return non-zero on failure
+                %r21 - Kernel error code
+
+                %r21 has the following meanings:
+
+                EAGAIN - CAS is busy, ldcw failed, try again.
+                EFAULT - Read or write failed.
+
+                Scratch: r20, r22, r28, r29, r1, fr4 (32bit for 64bit CAS only)
+
+        ****************************************************/
+
+        /* ELF32 Process entry path */
+lws_compare_and_swap_2:
+#ifdef CONFIG_64BIT
+        /* Clip the input registers */
+        depdi   0, 31, 32, %r26
+        depdi   0, 31, 32, %r25
+        depdi   0, 31, 32, %r24
+        depdi   0, 31, 32, %r23
+#endif
+
+        /* Check the validity of the size pointer */
+        subi,>>= 4, %r23, %r0
+        b,n     lws_exit_nosys
+
+        /* Jump to the functions which will load the old and new values into
+           registers depending on the their size */
+        shlw    %r23, 2, %r29
+        blr     %r29, %r0
+        nop
+
+        /* 8bit load */
+4:      ldb     0(%sr3,%r25), %r25
+        b       cas2_lock_start
+5:      ldb     0(%sr3,%r24), %r24
+        nop
+        nop
+        nop
+        nop
+        nop
+
+        /* 16bit load */
+6:      ldh     0(%sr3,%r25), %r25
+        b       cas2_lock_start
+7:      ldh     0(%sr3,%r24), %r24
+        nop
+        nop
+        nop
+        nop
+        nop
+
+        /* 32bit load */
+8:      ldw     0(%sr3,%r25), %r25
+        b       cas2_lock_start
+9:      ldw     0(%sr3,%r24), %r24
+        nop
+        nop
+        nop
+        nop
+        nop
+
+        /* 64bit load */
+#ifdef CONFIG_64BIT
+10:     ldd     0(%sr3,%r25), %r25
+11:     ldd     0(%sr3,%r24), %r24
+#else
+        /* Load new value into r22/r23 - high/low */
+10:     ldw     0(%sr3,%r25), %r22
+11:     ldw     4(%sr3,%r25), %r23
+        /* Load new value into fr4 for atomic store later */
+12:     flddx   0(%sr3,%r24), %fr4
+#endif
+
+cas2_lock_start:
+        /* Load start of lock table */
+        ldil    L%lws_lock_start, %r20
+        ldo     R%lws_lock_start(%r20), %r28
+
+        /* Extract four bits from r26 and hash lock (Bits 4-7) */
+        extru  %r26, 27, 4, %r20
+
+        /* Find lock to use, the hash is either one of 0 to
+           15, multiplied by 16 (keep it 16-byte aligned)
+           and add to the lock table offset. */
+        shlw    %r20, 4, %r20
+        add     %r20, %r28, %r20
+
+        rsm     PSW_SM_I, %r0                   /* Disable interrupts */
+        /* COW breaks can cause contention on UP systems */
+        LDCW    0(%sr2,%r20), %r28              /* Try to acquire the lock */
+        cmpb,<>,n       %r0, %r28, cas2_action  /* Did we get it? */
+cas2_wouldblock:
+        ldo     2(%r0), %r28                    /* 2nd case */
+        ssm     PSW_SM_I, %r0
+        b       lws_exit                        /* Contended... */
+        ldo     -EAGAIN(%r0), %r21              /* Spin in userspace */
+
+        /*
+                prev = *addr;
+                if ( prev == old )
+                  *addr = new;
+                return prev;
+        */
+
+        /* NOTES:
+                This all works becuse intr_do_signal
+                and schedule both check the return iasq
+                and see that we are on the kernel page
+                so this process is never scheduled off
+                or is ever sent any signal of any sort,
+                thus it is wholly atomic from usrspaces
+                perspective
+        */
+cas2_action:
+        /* Jump to the correct function */
+        blr     %r29, %r0
+        /* Set %r28 as non-zero for now */
+        ldo     1(%r0),%r28
+
+        /* 8bit CAS */
+13:     ldb,ma  0(%sr3,%r26), %r29
+        sub,=   %r29, %r25, %r0
+        b,n     cas2_end
+14:     stb,ma  %r24, 0(%sr3,%r26)
+        b       cas2_end
+        copy    %r0, %r28
+        nop
+        nop
+
+        /* 16bit CAS */
+15:     ldh,ma  0(%sr3,%r26), %r29
+        sub,=   %r29, %r25, %r0
+        b,n     cas2_end
+16:     sth,ma  %r24, 0(%sr3,%r26)
+        b       cas2_end
+        copy    %r0, %r28
+        nop
+        nop
+
+        /* 32bit CAS */
+17:     ldw,ma  0(%sr3,%r26), %r29
+        sub,=   %r29, %r25, %r0
+        b,n     cas2_end
+18:     stw,ma  %r24, 0(%sr3,%r26)
+        b       cas2_end
+        copy    %r0, %r28
+        nop
+        nop
+
+        /* 64bit CAS */
+#ifdef CONFIG_64BIT
+19:     ldd,ma  0(%sr3,%r26), %r29
+        sub,=   %r29, %r25, %r0
+        b,n     cas2_end
+20:     std,ma  %r24, 0(%sr3,%r26)
+        copy    %r0, %r28
+#else
+        /* Compare first word */
+19:     ldw,ma  0(%sr3,%r26), %r29
+        sub,=   %r29, %r22, %r0
+        b,n     cas2_end
+        /* Compare second word */
+20:     ldw,ma  4(%sr3,%r26), %r29
+        sub,=   %r29, %r23, %r0
+        b,n     cas2_end
+        /* Perform the store */
+21:     fstdx   %fr4, 0(%sr3,%r26)
+        copy    %r0, %r28
+#endif
+
+cas2_end:
+        /* Free lock */
+        stw,ma  %r20, 0(%sr2,%r20)
+        /* Enable interrupts */
+        ssm     PSW_SM_I, %r0
+        /* Return to userspace, set no error */
+        b       lws_exit
+        copy    %r0, %r21
+
+22:
+        /* Error occurred on load or store */
+        /* Free lock */
+        stw     %r20, 0(%sr2,%r20)
+        ssm     PSW_SM_I, %r0
+        ldo     1(%r0),%r28
+        b       lws_exit
+        ldo     -EFAULT(%r0),%r21       /* set errno */
+        nop
+        nop
+        nop
+
+        /* Exception table entries, for the load and store, return EFAULT.
+           Each of the entries must be relocated. */
+        ASM_EXCEPTIONTABLE_ENTRY(4b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(5b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(6b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(7b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(8b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(9b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(10b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(11b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(13b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(14b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(15b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(16b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(17b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(18b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(19b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(20b-linux_gateway_page, 22b-linux_gateway_page)
+#ifndef CONFIG_64BIT
+        ASM_EXCEPTIONTABLE_ENTRY(12b-linux_gateway_page, 22b-linux_gateway_page)
+        ASM_EXCEPTIONTABLE_ENTRY(21b-linux_gateway_page, 22b-linux_gateway_page)
+#endif
+
         /* Make sure nothing else is placed on this page */
         .align PAGE_SIZE
 END(linux_gateway_page)
@@ -675,8 +899,9 @@ ENTRY(end_linux_gateway_page)
         /* Light-weight-syscall table */
         /* Start of lws table. */
 ENTRY(lws_table)
-        LWS_ENTRY(compare_and_swap32)   /* 0 - ELF32 Atomic compare and swap */
-        LWS_ENTRY(compare_and_swap64)   /* 1 - ELF64 Atomic compare and swap */
+        LWS_ENTRY(compare_and_swap32)           /* 0 - ELF32 Atomic 32bit CAS */
+        LWS_ENTRY(compare_and_swap64)           /* 1 - ELF64 Atomic 32bit CAS */
+        LWS_ENTRY(compare_and_swap_2)           /* 2 - ELF32 Atomic 64bit CAS */
 END(lws_table)
         /* End of lws table */
 
diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S
index 84c5d3a58fa1..b563d9c8268b 100644
--- a/arch/parisc/kernel/syscall_table.S
+++ b/arch/parisc/kernel/syscall_table.S
@@ -433,6 +433,9 @@
         ENTRY_SAME(sched_getattr)       /* 335 */
         ENTRY_COMP(utimes)
         ENTRY_SAME(renameat2)
+        ENTRY_SAME(seccomp)
+        ENTRY_SAME(getrandom)
+        ENTRY_SAME(memfd_create)        /* 340 */
 
         /* Nothing yet */
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a577609f8ed6..4bc7b62fb4b6 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -399,8 +399,6 @@ config PPC64_SUPPORTS_MEMORY_FAILURE
 config KEXEC
         bool "kexec system call"
         depends on (PPC_BOOK3S || FSL_BOOKE || (44x && !SMP))
-        select CRYPTO
-        select CRYPTO_SHA256
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/powerpc/boot/simpleboot.c b/arch/powerpc/boot/simpleboot.c
index 21cd48074ec8..9f8c678f0d9a 100644
--- a/arch/powerpc/boot/simpleboot.c
+++ b/arch/powerpc/boot/simpleboot.c
@@ -61,7 +61,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
                 if (*reg++ != 0)
                         fatal("Memory range is not based at address 0\n");
 
-        /* get the memsize and trucate it to under 4G on 32 bit machines */
+        /* get the memsize and truncate it to under 4G on 32 bit machines */
         memsize64 = 0;
         for (i = 0; i < *ns; i++)
                 memsize64 = (memsize64 << 32) | *reg++;
diff --git a/arch/powerpc/configs/c2k_defconfig b/arch/powerpc/configs/c2k_defconfig
index 5e2aa43562b5..59734916986a 100644
--- a/arch/powerpc/configs/c2k_defconfig
+++ b/arch/powerpc/configs/c2k_defconfig
@@ -29,6 +29,7 @@ CONFIG_PM=y
 CONFIG_PCI_MSI=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_SHPC=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=y
diff --git a/arch/powerpc/configs/cell_defconfig b/arch/powerpc/configs/cell_defconfig
index 4bee1a6d41d0..45fd06cdc3e8 100644
--- a/arch/powerpc/configs/cell_defconfig
+++ b/arch/powerpc/configs/cell_defconfig
@@ -5,6 +5,7 @@ CONFIG_SMP=y
 CONFIG_NR_CPUS=4
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=15
diff --git a/arch/powerpc/configs/celleb_defconfig b/arch/powerpc/configs/celleb_defconfig
index 6d7b22f41b50..77d7bf3ca2ac 100644
--- a/arch/powerpc/configs/celleb_defconfig
+++ b/arch/powerpc/configs/celleb_defconfig
@@ -5,6 +5,7 @@ CONFIG_SMP=y
 CONFIG_NR_CPUS=4
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=15
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 4b07bade1ba9..269d6e47c67d 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -4,6 +4,7 @@ CONFIG_ALTIVEC=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=24
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig
index 3c72fa615bd9..7594c5ac6481 100644
--- a/arch/powerpc/configs/g5_defconfig
+++ b/arch/powerpc/configs/g5_defconfig
@@ -5,6 +5,7 @@ CONFIG_NR_CPUS=4
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_BLK_DEV_INITRD=y
diff --git a/arch/powerpc/configs/maple_defconfig b/arch/powerpc/configs/maple_defconfig
index 95e545d9f25c..c8b6a9ddb21b 100644
--- a/arch/powerpc/configs/maple_defconfig
+++ b/arch/powerpc/configs/maple_defconfig
@@ -4,6 +4,7 @@ CONFIG_NR_CPUS=4
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 # CONFIG_COMPAT_BRK is not set
diff --git a/arch/powerpc/configs/pasemi_defconfig b/arch/powerpc/configs/pasemi_defconfig
index cec044a3ff69..e5e7838af008 100644
--- a/arch/powerpc/configs/pasemi_defconfig
+++ b/arch/powerpc/configs/pasemi_defconfig
@@ -3,6 +3,7 @@ CONFIG_ALTIVEC=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig
index 553e66278010..0351b5ffdfef 100644
--- a/arch/powerpc/configs/pmac32_defconfig
+++ b/arch/powerpc/configs/pmac32_defconfig
@@ -31,6 +31,7 @@ CONFIG_HIBERNATION=y
 CONFIG_APM_EMULATION=y
 CONFIG_PCCARD=m
 CONFIG_YENTA=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=y
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index f26b267eb71f..36518870e6b2 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -4,6 +4,7 @@ CONFIG_VSX=y
 CONFIG_SMP=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -57,6 +58,7 @@ CONFIG_ELECTRA_CF=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_RPA=m
 CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig
index 438e813dc9cb..c3a3269b0865 100644
--- a/arch/powerpc/configs/ppc64e_defconfig
+++ b/arch/powerpc/configs/ppc64e_defconfig
@@ -3,6 +3,7 @@ CONFIG_PPC_BOOK3E_64=y
 CONFIG_SMP=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_TASKSTATS=y
@@ -32,6 +33,7 @@ CONFIG_SPARSEMEM_MANUAL=y
 CONFIG_PCI_MSI=y
 CONFIG_PCCARD=y
 CONFIG_HOTPLUG_PCI=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index fdee37fab81c..2e637c881d2b 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -5,6 +5,7 @@ CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_RD_LZMA=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index a905063281cc..dd2a9cab4b50 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -5,6 +5,7 @@ CONFIG_SMP=y
 CONFIG_NR_CPUS=2048
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_AUDIT=y
 CONFIG_AUDITSYSCALL=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
@@ -52,6 +53,7 @@ CONFIG_SCHED_SMT=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_RPA=m
 CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/powerpc/configs/pseries_le_defconfig b/arch/powerpc/configs/pseries_le_defconfig
index 58e3dbf43ca4..63392f4b29a4 100644
--- a/arch/powerpc/configs/pseries_le_defconfig
+++ b/arch/powerpc/configs/pseries_le_defconfig
@@ -6,6 +6,7 @@ CONFIG_NR_CPUS=2048
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_AUDIT=y
 CONFIG_AUDITSYSCALL=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
@@ -54,6 +55,7 @@ CONFIG_SCHED_SMT=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_RPA=m
 CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index 7f23f162ce9c..31e8f59aff38 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -1,6 +1,7 @@
 
 generic-y += clkdev.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
 generic-y += rwsem.h
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 465dfcb82c92..5bca220bbb60 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -53,17 +53,17 @@
 #define BOOKE_INTERRUPT_DEBUG 15
 
 /* E500 */
-#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32
-#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33
-/*
- * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines
- */
-#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
-#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
-#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
-#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \
-                                BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
+#ifdef CONFIG_SPE_POSSIBLE
+#define BOOKE_INTERRUPT_SPE_UNAVAIL 32
+#define BOOKE_INTERRUPT_SPE_FP_DATA 33
 #define BOOKE_INTERRUPT_SPE_FP_ROUND 34
+#endif
+
+#ifdef CONFIG_PPC_E500MC
+#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 32
+#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 33
+#endif
+
 #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
 #define BOOKE_INTERRUPT_DOORBELL 36
 #define BOOKE_INTERRUPT_DOORBELL_CRITICAL 37
diff --git a/arch/powerpc/include/asm/kvm_booke.h b/arch/powerpc/include/asm/kvm_booke.h
index f7aa5cc395c4..3286f0d6a86c 100644
--- a/arch/powerpc/include/asm/kvm_booke.h
+++ b/arch/powerpc/include/asm/kvm_booke.h
@@ -23,15 +23,16 @@
 #include <linux/types.h>
 #include <linux/kvm_host.h>
 
-/* LPIDs we support with this build -- runtime limit may be lower */
+/*
+ * Number of available lpids. Only the low-order 6 bits of LPID rgister are
+ * implemented on e500mc+ cores.
+ */
 #define KVMPPC_NR_LPIDS                        64
 
 #define KVMPPC_INST_EHPRIV              0x7c00021c
 #define EHPRIV_OC_SHIFT                 11
 /* "ehpriv 1" : ehpriv with OC = 1 is used for debug emulation */
 #define EHPRIV_OC_DEBUG                 1
-#define KVMPPC_INST_EHPRIV_DEBUG        (KVMPPC_INST_EHPRIV | \
-                                         (EHPRIV_OC_DEBUG << EHPRIV_OC_SHIFT))
 
 static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
 {
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 98d9dd50d063..047855619cc4 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -53,14 +53,18 @@
 
 #define KVM_ARCH_WANT_MMU_NOTIFIER
 
-struct kvm;
 extern int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 extern int kvm_unmap_hva_range(struct kvm *kvm,
                                unsigned long start, unsigned long end);
-extern int kvm_age_hva(struct kvm *kvm, unsigned long hva);
+extern int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
 extern int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 extern void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 
+static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
+                                                         unsigned long address)
+{
+}
+
 #define HPTEG_CACHE_NUM                 (1 << 15)
 #define HPTEG_HASH_BITS_PTE             13
 #define HPTEG_HASH_BITS_PTE_LONG        12
@@ -76,10 +80,6 @@ extern void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 /* Physical Address Mask - allowed range of real mode RAM access */
 #define KVM_PAM                 0x0fffffffffffffffULL
 
-struct kvm;
-struct kvm_run;
-struct kvm_vcpu;
-
 struct lppaca;
 struct slb_shadow;
 struct dtl_entry;
@@ -144,6 +144,7 @@ enum kvm_exit_types {
         EMULATED_TLBWE_EXITS,
         EMULATED_RFI_EXITS,
         EMULATED_RFCI_EXITS,
+        EMULATED_RFDI_EXITS,
         DEC_EXITS,
         EXT_INTR_EXITS,
         HALT_WAKEUP,
@@ -589,8 +590,6 @@ struct kvm_vcpu_arch {
         u32 crit_save;
         /* guest debug registers*/
         struct debug_reg dbg_reg;
-        /* hardware visible debug registers when in guest state */
-        struct debug_reg shadow_dbg_reg;
 #endif
         gpa_t paddr_accessed;
         gva_t vaddr_accessed;
@@ -612,7 +611,6 @@ struct kvm_vcpu_arch {
         u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
 
         struct hrtimer dec_timer;
-        struct tasklet_struct tasklet;
         u64 dec_jiffies;
         u64 dec_expires;
         unsigned long pending_exceptions;
@@ -687,4 +685,12 @@ struct kvm_vcpu_arch {
 #define __KVM_HAVE_ARCH_WQP
 #define __KVM_HAVE_CREATE_DEVICE
 
+static inline void kvm_arch_hardware_disable(void) {}
+static inline void kvm_arch_hardware_unsetup(void) {}
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_memslots_updated(struct kvm *kvm) {}
+static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
+static inline void kvm_arch_exit(void) {}
+
 #endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index fb86a2299d8a..a6dcdb6d13c1 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -38,6 +38,12 @@
 #include <asm/paca.h>
 #endif
 
+/*
+ * KVMPPC_INST_SW_BREAKPOINT is debug Instruction
+ * for supporting software breakpoint.
+ */
+#define KVMPPC_INST_SW_BREAKPOINT       0x00dddd00
+
 enum emulation_result {
         EMULATE_DONE,         /* no further processing */
         EMULATE_DO_MMIO,      /* kvm_run filled with MMIO request */
@@ -89,7 +95,7 @@ extern int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu);
 extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
 extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
 extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
-extern void kvmppc_decrementer_func(unsigned long data);
+extern void kvmppc_decrementer_func(struct kvm_vcpu *vcpu);
 extern int kvmppc_sanity_check(struct kvm_vcpu *vcpu);
 extern int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu);
 extern void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu);
@@ -206,6 +212,9 @@ extern int kvmppc_xics_get_xive(struct kvm *kvm, u32 irq, u32 *server,
 extern int kvmppc_xics_int_on(struct kvm *kvm, u32 irq);
 extern int kvmppc_xics_int_off(struct kvm *kvm, u32 irq);
 
+void kvmppc_core_dequeue_debug(struct kvm_vcpu *vcpu);
+void kvmppc_core_queue_debug(struct kvm_vcpu *vcpu);
+
 union kvmppc_one_reg {
         u32     wval;
         u64     dval;
@@ -243,7 +252,7 @@ struct kvmppc_ops {
         int (*unmap_hva)(struct kvm *kvm, unsigned long hva);
         int (*unmap_hva_range)(struct kvm *kvm, unsigned long start,
                            unsigned long end);
-        int (*age_hva)(struct kvm *kvm, unsigned long hva);
+        int (*age_hva)(struct kvm *kvm, unsigned long start, unsigned long end);
         int (*test_age_hva)(struct kvm *kvm, unsigned long hva);
         void (*set_spte_hva)(struct kvm *kvm, unsigned long hva, pte_t pte);
         void (*mmu_destroy)(struct kvm_vcpu *vcpu);
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index b125ceab149c..3af721633618 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -136,8 +136,6 @@ struct machdep_calls {
         int             (*pci_setup_phb)(struct pci_controller *host);
 
 #ifdef CONFIG_PCI_MSI
-        int             (*msi_check_device)(struct pci_dev* dev,
-                                            int nvec, int type);
         int             (*setup_msi_irqs)(struct pci_dev *dev,
                                           int nvec, int type);
         void            (*teardown_msi_irqs)(struct pci_dev *dev);
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index d98c1ecc3266..f60d4ea8b50c 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -38,10 +38,9 @@ static inline int pte_none(pte_t pte)		{ return (pte_val(pte) & ~_PTE_NONE_MASK)
 static inline pgprot_t pte_pgprot(pte_t pte)    { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
 
 #ifdef CONFIG_NUMA_BALANCING
-
 static inline int pte_present(pte_t pte)
 {
-        return pte_val(pte) & (_PAGE_PRESENT | _PAGE_NUMA);
+        return pte_val(pte) & _PAGE_NUMA_MASK;
 }
 
 #define pte_present_nonuma pte_present_nonuma
@@ -50,37 +49,6 @@ static inline int pte_present_nonuma(pte_t pte)
         return pte_val(pte) & (_PAGE_PRESENT);
 }
 
-#define pte_numa pte_numa
-static inline int pte_numa(pte_t pte)
-{
-        return (pte_val(pte) &
-                (_PAGE_NUMA|_PAGE_PRESENT)) == _PAGE_NUMA;
-}
-
-#define pte_mknonnuma pte_mknonnuma
-static inline pte_t pte_mknonnuma(pte_t pte)
-{
-        pte_val(pte) &= ~_PAGE_NUMA;
-        pte_val(pte) |=  _PAGE_PRESENT | _PAGE_ACCESSED;
-        return pte;
-}
-
-#define pte_mknuma pte_mknuma
-static inline pte_t pte_mknuma(pte_t pte)
-{
-        /*
-         * We should not set _PAGE_NUMA on non present ptes. Also clear the
-         * present bit so that hash_page will return 1 and we collect this
-         * as numa fault.
-         */
-        if (pte_present(pte)) {
-                pte_val(pte) |= _PAGE_NUMA;
-                pte_val(pte) &= ~_PAGE_PRESENT;
-        } else
-                VM_BUG_ON(1);
-        return pte;
-}
-
 #define ptep_set_numa ptep_set_numa
 static inline void ptep_set_numa(struct mm_struct *mm, unsigned long addr,
                                  pte_t *ptep)
@@ -92,12 +60,6 @@ static inline void ptep_set_numa(struct mm_struct *mm, unsigned long addr,
         return;
 }
 
-#define pmd_numa pmd_numa
-static inline int pmd_numa(pmd_t pmd)
-{
-        return pte_numa(pmd_pte(pmd));
-}
-
 #define pmdp_set_numa pmdp_set_numa
 static inline void pmdp_set_numa(struct mm_struct *mm, unsigned long addr,
                                  pmd_t *pmdp)
@@ -109,16 +71,21 @@ static inline void pmdp_set_numa(struct mm_struct *mm, unsigned long addr,
         return;
 }
 
-#define pmd_mknonnuma pmd_mknonnuma
-static inline pmd_t pmd_mknonnuma(pmd_t pmd)
+/*
+ * Generic NUMA pte helpers expect pteval_t and pmdval_t types to exist
+ * which was inherited from x86. For the purposes of powerpc pte_basic_t and
+ * pmd_t are equivalent
+ */
+#define pteval_t pte_basic_t
+#define pmdval_t pmd_t
+static inline pteval_t ptenuma_flags(pte_t pte)
 {
-        return pte_pmd(pte_mknonnuma(pmd_pte(pmd)));
+        return pte_val(pte) & _PAGE_NUMA_MASK;
 }
 
-#define pmd_mknuma pmd_mknuma
-static inline pmd_t pmd_mknuma(pmd_t pmd)
+static inline pmdval_t pmdnuma_flags(pmd_t pmd)
 {
-        return pte_pmd(pte_mknuma(pmd_pte(pmd)));
+        return pmd_val(pmd) & _PAGE_NUMA_MASK;
 }
 
 # else
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index 8d1569c29042..e040c3595129 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -98,6 +98,11 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
                          _PAGE_USER | _PAGE_ACCESSED | \
                          _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | _PAGE_EXEC)
 
+#ifdef CONFIG_NUMA_BALANCING
+/* Mask of bits that distinguish present and numa ptes */
+#define _PAGE_NUMA_MASK (_PAGE_NUMA|_PAGE_PRESENT)
+#endif
+
 /*
  * We define 2 sets of base prot bits, one for basic pages (ie,
  * cacheable kernel and user pages) and one for non cacheable
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 279b80f3bb29..c0c61fa9cd9e 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -47,6 +47,12 @@
                                  STACK_FRAME_OVERHEAD + KERNEL_REDZONE_SIZE)
 #define STACK_FRAME_MARKER      12
 
+#if defined(_CALL_ELF) && _CALL_ELF == 2
+#define STACK_FRAME_MIN_SIZE    32
+#else
+#define STACK_FRAME_MIN_SIZE    STACK_FRAME_OVERHEAD
+#endif
+
 /* Size of dummy stack frame allocated when calling signal handler. */
 #define __SIGNAL_FRAMESIZE      128
 #define __SIGNAL_FRAMESIZE32    64
@@ -60,6 +66,7 @@
 #define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
 #define STACK_INT_FRAME_SIZE    (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
 #define STACK_FRAME_MARKER      2
+#define STACK_FRAME_MIN_SIZE    STACK_FRAME_OVERHEAD
 
 /* Size of stack frame allocated when calling signal handler. */
 #define __SIGNAL_FRAMESIZE      64
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 1d653308a33c..16547efa2d5a 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -319,6 +319,8 @@
  * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
  */
 #ifdef CONFIG_BOOKE
+#define DBSR_IDE        0x80000000      /* Imprecise Debug Event */
+#define DBSR_MRR        0x30000000      /* Most Recent Reset */
 #define DBSR_IC         0x08000000      /* Instruction Completion */
 #define DBSR_BT         0x04000000      /* Branch Taken */
 #define DBSR_IRPT       0x02000000      /* Exception Debug Event */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 542bc0f0673f..7d8a60068805 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -362,3 +362,6 @@ SYSCALL(ni_syscall) /* sys_kcmp */
 SYSCALL_SPU(sched_setattr)
 SYSCALL_SPU(sched_getattr)
 SYSCALL_SPU(renameat2)
+SYSCALL_SPU(seccomp)
+SYSCALL_SPU(getrandom)
+SYSCALL_SPU(memfd_create)
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 5ce5552ab9f5..4e9af3fd43e7 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -12,7 +12,7 @@
 #include <uapi/asm/unistd.h>
 
 
-#define __NR_syscalls           358
+#define __NR_syscalls           361
 
 #define __NR__exit __NR_exit
 #define NR_syscalls     __NR_syscalls
diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
index e0e49dbb145d..ab4d4732c492 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -476,6 +476,11 @@ struct kvm_get_htab_header {
 
 /* FP and vector status/control registers */
 #define KVM_REG_PPC_FPSCR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
+/*
+ * VSCR register is documented as a 32-bit register in the ISA, but it can
+ * only be accesses via a vector register. Expose VSCR as a 32-bit register
+ * even though the kernel represents it as a 128-bit vector.
+ */
 #define KVM_REG_PPC_VSCR        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
 
 /* Virtual processor areas */
@@ -557,6 +562,7 @@ struct kvm_get_htab_header {
 #define KVM_REG_PPC_DABRX       (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
 #define KVM_REG_PPC_WORT        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9)
 #define KVM_REG_PPC_SPRG9       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
+#define KVM_REG_PPC_DBSR        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
 
 /* Transactional Memory checkpointed state:
  * This is all GPRs, all VSX regs and a subset of SPRs
diff --git a/arch/powerpc/include/uapi/asm/unistd.h b/arch/powerpc/include/uapi/asm/unistd.h
index 2d526f7b48da..0688fc06e183 100644
--- a/arch/powerpc/include/uapi/asm/unistd.h
+++ b/arch/powerpc/include/uapi/asm/unistd.h
@@ -380,5 +380,8 @@
 #define __NR_sched_setattr      355
 #define __NR_sched_getattr      356
 #define __NR_renameat2          357
+#define __NR_seccomp            358
+#define __NR_getrandom          359
+#define __NR_memfd_create       360
 
 #endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 4f1393d20079..dddba3e94260 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -91,6 +91,7 @@ _GLOBAL(setup_altivec_idle)
 
         blr
 
+#ifdef CONFIG_PPC_E500MC
 _GLOBAL(__setup_cpu_e6500)
         mflr    r6
 #ifdef CONFIG_PPC64
@@ -107,14 +108,20 @@ _GLOBAL(__setup_cpu_e6500)
         bl      __setup_cpu_e5500
         mtlr    r6
         blr
+#endif /* CONFIG_PPC_E500MC */
 
 #ifdef CONFIG_PPC32
+#ifdef CONFIG_E200
 _GLOBAL(__setup_cpu_e200)
         /* enable dedicated debug exception handling resources (Debug APU) */
         mfspr   r3,SPRN_HID0
         ori     r3,r3,HID0_DAPUEN@l
         mtspr   SPRN_HID0,r3
         b       __setup_e200_ivors
+#endif /* CONFIG_E200 */
+
+#ifdef CONFIG_E500
+#ifndef CONFIG_PPC_E500MC
 _GLOBAL(__setup_cpu_e500v1)
 _GLOBAL(__setup_cpu_e500v2)
         mflr    r4
@@ -129,6 +136,7 @@ _GLOBAL(__setup_cpu_e500v2)
 #endif
         mtlr    r4
         blr
+#else /* CONFIG_PPC_E500MC */
 _GLOBAL(__setup_cpu_e500mc)
 _GLOBAL(__setup_cpu_e5500)
         mflr    r5
@@ -159,7 +167,9 @@ _GLOBAL(__setup_cpu_e5500)
 2:
         mtlr    r5
         blr
-#endif
+#endif /* CONFIG_PPC_E500MC */
+#endif /* CONFIG_E500 */
+#endif /* CONFIG_PPC32 */
 
 #ifdef CONFIG_PPC_BOOK3E_64
 _GLOBAL(__restore_cpu_e6500)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 9b6dcaaec1a3..808405906336 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1961,6 +1961,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
 #endif /* CONFIG_PPC32 */
 #ifdef CONFIG_E500
 #ifdef CONFIG_PPC32
+#ifndef CONFIG_PPC_E500MC
         {       /* e500 */
                 .pvr_mask               = 0xffff0000,
                 .pvr_value              = 0x80200000,
@@ -2000,6 +2001,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_e500,
                 .platform               = "ppc8548",
         },
+#else
         {       /* e500mc */
                 .pvr_mask               = 0xffff0000,
                 .pvr_value              = 0x80230000,
@@ -2018,7 +2020,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_e500mc,
                 .platform               = "ppce500mc",
         },
+#endif /* CONFIG_PPC_E500MC */
 #endif /* CONFIG_PPC32 */
+#ifdef CONFIG_PPC_E500MC
         {       /* e5500 */
                 .pvr_mask               = 0xffff0000,
                 .pvr_value              = 0x80240000,
@@ -2062,6 +2066,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_e500mc,
                 .platform               = "ppce6500",
         },
+#endif /* CONFIG_PPC_E500MC */
 #ifdef CONFIG_PPC32
         {       /* default match */
                 .pvr_mask               = 0x00000000,
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index bb9cac6c8051..3e68d1c69718 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -635,7 +635,7 @@ interrupt_end_book3e:
 
 /* Altivec Unavailable Interrupt */
         START_EXCEPTION(altivec_unavailable);
-        NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL,
+        NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
                                 PROLOG_ADDITION_NONE)
         /* we can probably do a shorter exception entry for that one... */
         EXCEPTION_COMMON(0x200)
@@ -658,7 +658,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 /* AltiVec Assist */
         START_EXCEPTION(altivec_assist);
         NORMAL_EXCEPTION_PROLOG(0x220,
-                                BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST,
+                                BOOKE_INTERRUPT_ALTIVEC_ASSIST,
                                 PROLOG_ADDITION_NONE)
         EXCEPTION_COMMON(0x220)
         INTS_DISABLE
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index b497188a94a1..fffd1f96bb1d 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -613,34 +613,36 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
         mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       InstructionStorage
 
+/* Define SPE handlers for e200 and e500v2 */
 #ifdef CONFIG_SPE
         /* SPE Unavailable */
         START_EXCEPTION(SPEUnavailable)
-        NORMAL_EXCEPTION_PROLOG(SPE_ALTIVEC_UNAVAIL)
+        NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
         beq     1f
         bl      load_up_spe
         b       fast_exception_return
 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
         EXC_XFER_EE_LITE(0x2010, KernelSPE)
-#else
-        EXCEPTION(0x2020, SPE_ALTIVEC_UNAVAIL, SPEUnavailable, \
+#elif defined(CONFIG_SPE_POSSIBLE)
+        EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
                   unknown_exception, EXC_XFER_EE)
-#endif /* CONFIG_SPE */
+#endif /* CONFIG_SPE_POSSIBLE */
 
         /* SPE Floating Point Data */
 #ifdef CONFIG_SPE
-        EXCEPTION(0x2030, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
+        EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
                   SPEFloatingPointException, EXC_XFER_EE)
 
         /* SPE Floating Point Round */
         EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
                   SPEFloatingPointRoundException, EXC_XFER_EE)
-#else
-        EXCEPTION(0x2040, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
+#elif defined(CONFIG_SPE_POSSIBLE)
+        EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
                   unknown_exception, EXC_XFER_EE)
         EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
                   unknown_exception, EXC_XFER_EE)
-#endif /* CONFIG_SPE */
+#endif /* CONFIG_SPE_POSSIBLE */
+
 
         /* Performance Monitor */
         EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
@@ -947,6 +949,7 @@ get_phys_addr:
  * Global functions
  */
 
+#ifdef CONFIG_E200
 /* Adjust or setup IVORs for e200 */
 _GLOBAL(__setup_e200_ivors)
         li      r3,DebugDebug@l
@@ -959,7 +962,10 @@ _GLOBAL(__setup_e200_ivors)
         mtspr   SPRN_IVOR34,r3
         sync
         blr
+#endif
 
+#ifdef CONFIG_E500
+#ifndef CONFIG_PPC_E500MC
 /* Adjust or setup IVORs for e500v1/v2 */
 _GLOBAL(__setup_e500_ivors)
         li      r3,DebugCrit@l
@@ -974,7 +980,7 @@ _GLOBAL(__setup_e500_ivors)
         mtspr   SPRN_IVOR35,r3
         sync
         blr
-
+#else
 /* Adjust or setup IVORs for e500mc */
 _GLOBAL(__setup_e500mc_ivors)
         li      r3,DebugDebug@l
@@ -1000,6 +1006,8 @@ _GLOBAL(__setup_ehv_ivors)
         mtspr   SPRN_IVOR41,r3
         sync
         blr
+#endif /* CONFIG_PPC_E500MC */
+#endif /* CONFIG_E500 */
 
 #ifdef CONFIG_SPE
 /*
diff --git a/arch/powerpc/kernel/msi.c b/arch/powerpc/kernel/msi.c
index 8bbc12d20f5c..71bd161640cf 100644
--- a/arch/powerpc/kernel/msi.c
+++ b/arch/powerpc/kernel/msi.c
@@ -13,7 +13,7 @@
 
 #include <asm/machdep.h>
 
-int arch_msi_check_device(struct pci_dev* dev, int nvec, int type)
+int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 {
         if (!ppc_md.setup_msi_irqs || !ppc_md.teardown_msi_irqs) {
                 pr_debug("msi: Platform doesn't provide MSI callbacks.\n");
@@ -24,16 +24,6 @@ int arch_msi_check_device(struct pci_dev* dev, int nvec, int type)
         if (type == PCI_CAP_ID_MSI && nvec > 1)
                 return 1;
 
-        if (ppc_md.msi_check_device) {
-                pr_debug("msi: Using platform check routine.\n");
-                return ppc_md.msi_check_device(dev, nvec, type);
-        }
-
-        return 0;
-}
-
-int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
-{
         return ppc_md.setup_msi_irqs(dev, nvec, type);
 }
 
diff --git a/arch/powerpc/kernel/suspend.c b/arch/powerpc/kernel/suspend.c
index 0167d53da30c..a531154cc0f3 100644
--- a/arch/powerpc/kernel/suspend.c
+++ b/arch/powerpc/kernel/suspend.c
@@ -9,9 +9,7 @@
 
 #include <linux/mm.h>
 #include <asm/page.h>
-
-/* References to section boundaries */
-extern const void __nosave_begin, __nosave_end;
+#include <asm/sections.h>
 
 /*
  *      pfn_is_nosave - check if given pfn is in the 'nosave' section
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index dd03f6b299ba..b32db4b95361 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -535,174 +535,111 @@ int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
         return -ENOTSUPP;
 }
 
-int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                        union kvmppc_one_reg *val)
 {
-        int r;
-        union kvmppc_one_reg val;
-        int size;
+        int r = 0;
         long int i;
 
-        size = one_reg_size(reg->id);
-        if (size > sizeof(val))
-                return -EINVAL;
-
-        r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, reg->id, &val);
+        r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val);
         if (r == -EINVAL) {
                 r = 0;
-                switch (reg->id) {
+                switch (id) {
                 case KVM_REG_PPC_DAR:
-                        val = get_reg_val(reg->id, kvmppc_get_dar(vcpu));
+                        *val = get_reg_val(id, kvmppc_get_dar(vcpu));
                         break;
                 case KVM_REG_PPC_DSISR:
-                        val = get_reg_val(reg->id, kvmppc_get_dsisr(vcpu));
+                        *val = get_reg_val(id, kvmppc_get_dsisr(vcpu));
                         break;
                 case KVM_REG_PPC_FPR0 ... KVM_REG_PPC_FPR31:
-                        i = reg->id - KVM_REG_PPC_FPR0;
-                        val = get_reg_val(reg->id, VCPU_FPR(vcpu, i));
+                        i = id - KVM_REG_PPC_FPR0;
+                        *val = get_reg_val(id, VCPU_FPR(vcpu, i));
                         break;
                 case KVM_REG_PPC_FPSCR:
-                        val = get_reg_val(reg->id, vcpu->arch.fp.fpscr);
-                        break;
-#ifdef CONFIG_ALTIVEC
-                case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
-                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
-                                r = -ENXIO;
-                                break;
-                        }
-                        val.vval = vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0];
-                        break;
-                case KVM_REG_PPC_VSCR:
-                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
-                                r = -ENXIO;
-                                break;
-                        }
-                        val = get_reg_val(reg->id, vcpu->arch.vr.vscr.u[3]);
+                        *val = get_reg_val(id, vcpu->arch.fp.fpscr);
                         break;
-                case KVM_REG_PPC_VRSAVE:
-                        val = get_reg_val(reg->id, vcpu->arch.vrsave);
-                        break;
-#endif /* CONFIG_ALTIVEC */
 #ifdef CONFIG_VSX
                 case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
                         if (cpu_has_feature(CPU_FTR_VSX)) {
-                                long int i = reg->id - KVM_REG_PPC_VSR0;
-                                val.vsxval[0] = vcpu->arch.fp.fpr[i][0];
-                                val.vsxval[1] = vcpu->arch.fp.fpr[i][1];
+                                i = id - KVM_REG_PPC_VSR0;
+                                val->vsxval[0] = vcpu->arch.fp.fpr[i][0];
+                                val->vsxval[1] = vcpu->arch.fp.fpr[i][1];
                         } else {
                                 r = -ENXIO;
                         }
                         break;
 #endif /* CONFIG_VSX */
-                case KVM_REG_PPC_DEBUG_INST: {
-                        u32 opcode = INS_TW;
-                        r = copy_to_user((u32 __user *)(long)reg->addr,
-                                         &opcode, sizeof(u32));
+                case KVM_REG_PPC_DEBUG_INST:
+                        *val = get_reg_val(id, INS_TW);
                         break;
-                }
 #ifdef CONFIG_KVM_XICS
                 case KVM_REG_PPC_ICP_STATE:
                         if (!vcpu->arch.icp) {
                                 r = -ENXIO;
                                 break;
                         }
-                        val = get_reg_val(reg->id, kvmppc_xics_get_icp(vcpu));
+                        *val = get_reg_val(id, kvmppc_xics_get_icp(vcpu));
                         break;
 #endif /* CONFIG_KVM_XICS */
                 case KVM_REG_PPC_FSCR:
-                        val = get_reg_val(reg->id, vcpu->arch.fscr);
+                        *val = get_reg_val(id, vcpu->arch.fscr);
                         break;
                 case KVM_REG_PPC_TAR:
-                        val = get_reg_val(reg->id, vcpu->arch.tar);
+                        *val = get_reg_val(id, vcpu->arch.tar);
                         break;
                 case KVM_REG_PPC_EBBHR:
-                        val = get_reg_val(reg->id, vcpu->arch.ebbhr);
+                        *val = get_reg_val(id, vcpu->arch.ebbhr);
                         break;
                 case KVM_REG_PPC_EBBRR:
-                        val = get_reg_val(reg->id, vcpu->arch.ebbrr);
+                        *val = get_reg_val(id, vcpu->arch.ebbrr);
                         break;
                 case KVM_REG_PPC_BESCR:
-                        val = get_reg_val(reg->id, vcpu->arch.bescr);
+                        *val = get_reg_val(id, vcpu->arch.bescr);
                         break;
                 case KVM_REG_PPC_VTB:
-                        val = get_reg_val(reg->id, vcpu->arch.vtb);
+                        *val = get_reg_val(id, vcpu->arch.vtb);
                         break;
                 case KVM_REG_PPC_IC:
-                        val = get_reg_val(reg->id, vcpu->arch.ic);
+                        *val = get_reg_val(id, vcpu->arch.ic);
                         break;
                 default:
                         r = -EINVAL;
                         break;
                 }
         }
-        if (r)
-                return r;
-
-        if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size))
-                r = -EFAULT;
 
         return r;
 }
 
-int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                        union kvmppc_one_reg *val)
 {
-        int r;
-        union kvmppc_one_reg val;
-        int size;
+        int r = 0;
         long int i;
 
-        size = one_reg_size(reg->id);
-        if (size > sizeof(val))
-                return -EINVAL;
-
-        if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size))
-                return -EFAULT;
-
-        r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, reg->id, &val);
+        r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val);
         if (r == -EINVAL) {
                 r = 0;
-                switch (reg->id) {
+                switch (id) {
                 case KVM_REG_PPC_DAR:
-                        kvmppc_set_dar(vcpu, set_reg_val(reg->id, val));
+                        kvmppc_set_dar(vcpu, set_reg_val(id, *val));
                         break;
                 case KVM_REG_PPC_DSISR:
-                        kvmppc_set_dsisr(vcpu, set_reg_val(reg->id, val));
+                        kvmppc_set_dsisr(vcpu, set_reg_val(id, *val));
                         break;
                 case KVM_REG_PPC_FPR0 ... KVM_REG_PPC_FPR31:
-                        i = reg->id - KVM_REG_PPC_FPR0;
-                        VCPU_FPR(vcpu, i) = set_reg_val(reg->id, val);
+                        i = id - KVM_REG_PPC_FPR0;
+                        VCPU_FPR(vcpu, i) = set_reg_val(id, *val);
                         break;
                 case KVM_REG_PPC_FPSCR:
-                        vcpu->arch.fp.fpscr = set_reg_val(reg->id, val);
-                        break;
-#ifdef CONFIG_ALTIVEC
-                case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
-                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
-                                r = -ENXIO;
-                                break;
-                        }
-                        vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0] = val.vval;
-                        break;
-                case KVM_REG_PPC_VSCR:
-                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
-                                r = -ENXIO;
-                                break;
-                        }
-                        vcpu->arch.vr.vscr.u[3] = set_reg_val(reg->id, val);
-                        break;
-                case KVM_REG_PPC_VRSAVE:
-                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
-                                r = -ENXIO;
-                                break;
-                        }
-                        vcpu->arch.vrsave = set_reg_val(reg->id, val);
+                        vcpu->arch.fp.fpscr = set_reg_val(id, *val);
                         break;
-#endif /* CONFIG_ALTIVEC */
 #ifdef CONFIG_VSX
                 case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
                         if (cpu_has_feature(CPU_FTR_VSX)) {
-                                long int i = reg->id - KVM_REG_PPC_VSR0;
-                                vcpu->arch.fp.fpr[i][0] = val.vsxval[0];
-                                vcpu->arch.fp.fpr[i][1] = val.vsxval[1];
+                                i = id - KVM_REG_PPC_VSR0;
+                                vcpu->arch.fp.fpr[i][0] = val->vsxval[0];
+                                vcpu->arch.fp.fpr[i][1] = val->vsxval[1];
                         } else {
                                 r = -ENXIO;
                         }
@@ -715,29 +652,29 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                                 break;
                         }
                         r = kvmppc_xics_set_icp(vcpu,
-                                                set_reg_val(reg->id, val));
+                                                set_reg_val(id, *val));
                         break;
 #endif /* CONFIG_KVM_XICS */
                 case KVM_REG_PPC_FSCR:
-                        vcpu->arch.fscr = set_reg_val(reg->id, val);
+                        vcpu->arch.fscr = set_reg_val(id, *val);
                         break;
                 case KVM_REG_PPC_TAR:
-                        vcpu->arch.tar = set_reg_val(reg->id, val);
+                        vcpu->arch.tar = set_reg_val(id, *val);
                         break;
                 case KVM_REG_PPC_EBBHR:
-                        vcpu->arch.ebbhr = set_reg_val(reg->id, val);
+                        vcpu->arch.ebbhr = set_reg_val(id, *val);
                         break;
                 case KVM_REG_PPC_EBBRR:
-                        vcpu->arch.ebbrr = set_reg_val(reg->id, val);
+                        vcpu->arch.ebbrr = set_reg_val(id, *val);
                         break;
                 case KVM_REG_PPC_BESCR:
-                        vcpu->arch.bescr = set_reg_val(reg->id, val);
+                        vcpu->arch.bescr = set_reg_val(id, *val);
                         break;
                 case KVM_REG_PPC_VTB:
-                        vcpu->arch.vtb = set_reg_val(reg->id, val);
+                        vcpu->arch.vtb = set_reg_val(id, *val);
                         break;
                 case KVM_REG_PPC_IC:
-                        vcpu->arch.ic = set_reg_val(reg->id, val);
+                        vcpu->arch.ic = set_reg_val(id, *val);
                         break;
                 default:
                         r = -EINVAL;
@@ -778,13 +715,12 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
                                         struct kvm_guest_debug *dbg)
 {
-        return -EINVAL;
+        vcpu->guest_debug = dbg->control;
+        return 0;
 }
 
-void kvmppc_decrementer_func(unsigned long data)
+void kvmppc_decrementer_func(struct kvm_vcpu *vcpu)
 {
-        struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
-
         kvmppc_core_queue_dec(vcpu);
         kvm_vcpu_kick(vcpu);
 }
@@ -851,9 +787,9 @@ int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
         return kvm->arch.kvm_ops->unmap_hva_range(kvm, start, end);
 }
 
-int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
 {
-        return kvm->arch.kvm_ops->age_hva(kvm, hva);
+        return kvm->arch.kvm_ops->age_hva(kvm, start, end);
 }
 
 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
diff --git a/arch/powerpc/kvm/book3s.h b/arch/powerpc/kvm/book3s.h
index 4bf956cf94d6..d2b3ec088b8c 100644
--- a/arch/powerpc/kvm/book3s.h
+++ b/arch/powerpc/kvm/book3s.h
@@ -17,7 +17,8 @@ extern void kvmppc_core_flush_memslot_hv(struct kvm *kvm,
 extern int kvm_unmap_hva_hv(struct kvm *kvm, unsigned long hva);
 extern int kvm_unmap_hva_range_hv(struct kvm *kvm, unsigned long start,
                                   unsigned long end);
-extern int kvm_age_hva_hv(struct kvm *kvm, unsigned long hva);
+extern int kvm_age_hva_hv(struct kvm *kvm, unsigned long start,
+                          unsigned long end);
 extern int kvm_test_age_hva_hv(struct kvm *kvm, unsigned long hva);
 extern void kvm_set_spte_hva_hv(struct kvm *kvm, unsigned long hva, pte_t pte);
 
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 72c20bb16d26..d40770248b6a 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -62,10 +62,10 @@ long kvmppc_alloc_hpt(struct kvm *kvm, u32 *htab_orderp)
         }
 
         kvm->arch.hpt_cma_alloc = 0;
-        page = kvm_alloc_hpt(1 << (order - PAGE_SHIFT));
+        page = kvm_alloc_hpt(1ul << (order - PAGE_SHIFT));
         if (page) {
                 hpt = (unsigned long)pfn_to_kaddr(page_to_pfn(page));
-                memset((void *)hpt, 0, (1 << order));
+                memset((void *)hpt, 0, (1ul << order));
                 kvm->arch.hpt_cma_alloc = 1;
         }
 
@@ -1002,11 +1002,11 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
         return ret;
 }
 
-int kvm_age_hva_hv(struct kvm *kvm, unsigned long hva)
+int kvm_age_hva_hv(struct kvm *kvm, unsigned long start, unsigned long end)
 {
         if (!kvm->arch.using_mmu_notifiers)
                 return 0;
-        return kvm_handle_hva(kvm, hva, kvm_age_rmapp);
+        return kvm_handle_hva_range(kvm, start, end, kvm_age_rmapp);
 }
 
 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 27cced9c7249..e63587d30b70 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -725,6 +725,30 @@ static int kvmppc_hcall_impl_hv(unsigned long cmd)
         return kvmppc_hcall_impl_hv_realmode(cmd);
 }
 
+static int kvmppc_emulate_debug_inst(struct kvm_run *run,
+                                        struct kvm_vcpu *vcpu)
+{
+        u32 last_inst;
+
+        if (kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst) !=
+                                        EMULATE_DONE) {
+                /*
+                 * Fetch failed, so return to guest and
+                 * try executing it again.
+                 */
+                return RESUME_GUEST;
+        }
+
+        if (last_inst == KVMPPC_INST_SW_BREAKPOINT) {
+                run->exit_reason = KVM_EXIT_DEBUG;
+                run->debug.arch.address = kvmppc_get_pc(vcpu);
+                return RESUME_HOST;
+        } else {
+                kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
+                return RESUME_GUEST;
+        }
+}
+
 static int kvmppc_handle_exit_hv(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                  struct task_struct *tsk)
 {
@@ -807,12 +831,18 @@ static int kvmppc_handle_exit_hv(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 break;
         /*
          * This occurs if the guest executes an illegal instruction.
-         * We just generate a program interrupt to the guest, since
-         * we don't emulate any guest instructions at this stage.
+         * If the guest debug is disabled, generate a program interrupt
+         * to the guest. If guest debug is enabled, we need to check
+         * whether the instruction is a software breakpoint instruction.
+         * Accordingly return to Guest or Host.
          */
         case BOOK3S_INTERRUPT_H_EMUL_ASSIST:
-                kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
-                r = RESUME_GUEST;
+                if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) {
+                        r = kvmppc_emulate_debug_inst(run, vcpu);
+                } else {
+                        kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
+                        r = RESUME_GUEST;
+                }
                 break;
         /*
          * This occurs if the guest (kernel or userspace), does something that
@@ -856,7 +886,9 @@ static int kvm_arch_vcpu_ioctl_set_sregs_hv(struct kvm_vcpu *vcpu,
 {
         int i, j;
 
-        kvmppc_set_pvr_hv(vcpu, sregs->pvr);
+        /* Only accept the same PVR as the host's, since we can't spoof it */
+        if (sregs->pvr != vcpu->arch.pvr)
+                return -EINVAL;
 
         j = 0;
         for (i = 0; i < vcpu->arch.slb_nr; i++) {
@@ -922,6 +954,9 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
         long int i;
 
         switch (id) {
+        case KVM_REG_PPC_DEBUG_INST:
+                *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT);
+                break;
         case KVM_REG_PPC_HIOR:
                 *val = get_reg_val(id, 0);
                 break;
@@ -1489,7 +1524,7 @@ static void kvmppc_remove_runnable(struct kvmppc_vcore *vc,
 static int kvmppc_grab_hwthread(int cpu)
 {
         struct paca_struct *tpaca;
-        long timeout = 1000;
+        long timeout = 10000;
 
         tpaca = &paca[cpu];
 
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index 329d7fdd0a6a..4fdc27c80f4c 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -101,7 +101,7 @@ struct kvm_rma_info *kvm_alloc_rma()
         ri = kmalloc(sizeof(struct kvm_rma_info), GFP_KERNEL);
         if (!ri)
                 return NULL;
-        page = cma_alloc(kvm_cma, kvm_rma_pages, get_order(kvm_rma_pages));
+        page = cma_alloc(kvm_cma, kvm_rma_pages, order_base_2(kvm_rma_pages));
         if (!page)
                 goto err_out;
         atomic_set(&ri->use_count, 1);
@@ -135,12 +135,12 @@ struct page *kvm_alloc_hpt(unsigned long nr_pages)
 {
         unsigned long align_pages = HPT_ALIGN_PAGES;
 
-        VM_BUG_ON(get_order(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT);
+        VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT);
 
         /* Old CPUs require HPT aligned on a multiple of its size */
         if (!cpu_has_feature(CPU_FTR_ARCH_206))
                 align_pages = nr_pages;
-        return cma_alloc(kvm_cma, nr_pages, get_order(align_pages));
+        return cma_alloc(kvm_cma, nr_pages, order_base_2(align_pages));
 }
 EXPORT_SYMBOL_GPL(kvm_alloc_hpt);
 
@@ -163,6 +163,12 @@ void __init kvm_cma_reserve(void)
         unsigned long align_size;
         struct memblock_region *reg;
         phys_addr_t selected_size = 0;
+
+        /*
+         * We need CMA reservation only when we are in HV mode
+         */
+        if (!cpu_has_feature(CPU_FTR_HVMODE))
+                return;
         /*
          * We cannot use memblock_phys_mem_size() here, because
          * memblock_analyze() has not been called yet.
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index f0c4db7704c3..edb2ccdbb2ba 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -355,6 +355,7 @@ kvmppc_hv_entry:
          * MSR = ~IR|DR
          * R13 = PACA
          * R1 = host R1
+         * R2 = TOC
          * all other volatile GPRS = free
          */
         mflr    r0
@@ -503,7 +504,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 toc_tlbie_lock:
         .tc     native_tlbie_lock[TC],native_tlbie_lock
         .previous
-        ld      r3,toc_tlbie_lock@toc(2)
+        ld      r3,toc_tlbie_lock@toc(r2)
 #ifdef __BIG_ENDIAN__
         lwz     r8,PACA_LOCK_TOKEN(r13)
 #else
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index faffb27badd9..cf2eb16846d1 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -295,7 +295,8 @@ static int kvm_unmap_hva_range_pr(struct kvm *kvm, unsigned long start,
         return 0;
 }
 
-static int kvm_age_hva_pr(struct kvm *kvm, unsigned long hva)
+static int kvm_age_hva_pr(struct kvm *kvm, unsigned long start,
+                          unsigned long end)
 {
         /* XXX could be more clever ;) */
         return 0;
@@ -1319,6 +1320,9 @@ static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id,
         int r = 0;
 
         switch (id) {
+        case KVM_REG_PPC_DEBUG_INST:
+                *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT);
+                break;
         case KVM_REG_PPC_HIOR:
                 *val = get_reg_val(id, to_book3s(vcpu)->hior);
                 break;
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index b4c89fa6f109..9b55dec2d6cc 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -124,6 +124,40 @@ static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
 }
 #endif
 
+/*
+ * Load up guest vcpu FP state if it's needed.
+ * It also set the MSR_FP in thread so that host know
+ * we're holding FPU, and then host can help to save
+ * guest vcpu FP state if other threads require to use FPU.
+ * This simulates an FP unavailable fault.
+ *
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_PPC_FPU
+        if (!(current->thread.regs->msr & MSR_FP)) {
+                enable_kernel_fp();
+                load_fp_state(&vcpu->arch.fp);
+                current->thread.fp_save_area = &vcpu->arch.fp;
+                current->thread.regs->msr |= MSR_FP;
+        }
+#endif
+}
+
+/*
+ * Save guest vcpu FP state into thread.
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_PPC_FPU
+        if (current->thread.regs->msr & MSR_FP)
+                giveup_fpu(current);
+        current->thread.fp_save_area = NULL;
+#endif
+}
+
 static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
 {
 #if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
@@ -134,6 +168,40 @@ static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
 #endif
 }
 
+/*
+ * Simulate AltiVec unavailable fault to load guest state
+ * from thread to AltiVec unit.
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_ALTIVEC
+        if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
+                if (!(current->thread.regs->msr & MSR_VEC)) {
+                        enable_kernel_altivec();
+                        load_vr_state(&vcpu->arch.vr);
+                        current->thread.vr_save_area = &vcpu->arch.vr;
+                        current->thread.regs->msr |= MSR_VEC;
+                }
+        }
+#endif
+}
+
+/*
+ * Save guest vcpu AltiVec state into thread.
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_ALTIVEC
+        if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
+                if (current->thread.regs->msr & MSR_VEC)
+                        giveup_altivec(current);
+                current->thread.vr_save_area = NULL;
+        }
+#endif
+}
+
 static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
 {
         /* Synchronize guest's desire to get debug interrupts into shadow MSR */
@@ -267,6 +335,16 @@ static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
         clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
 }
 
+void kvmppc_core_queue_debug(struct kvm_vcpu *vcpu)
+{
+        kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DEBUG);
+}
+
+void kvmppc_core_dequeue_debug(struct kvm_vcpu *vcpu)
+{
+        clear_bit(BOOKE_IRQPRIO_DEBUG, &vcpu->arch.pending_exceptions);
+}
+
 static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
 {
         kvmppc_set_srr0(vcpu, srr0);
@@ -341,9 +419,15 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
         case BOOKE_IRQPRIO_ITLB_MISS:
         case BOOKE_IRQPRIO_SYSCALL:
         case BOOKE_IRQPRIO_FP_UNAVAIL:
+#ifdef CONFIG_SPE_POSSIBLE
         case BOOKE_IRQPRIO_SPE_UNAVAIL:
         case BOOKE_IRQPRIO_SPE_FP_DATA:
         case BOOKE_IRQPRIO_SPE_FP_ROUND:
+#endif
+#ifdef CONFIG_ALTIVEC
+        case BOOKE_IRQPRIO_ALTIVEC_UNAVAIL:
+        case BOOKE_IRQPRIO_ALTIVEC_ASSIST:
+#endif
         case BOOKE_IRQPRIO_AP_UNAVAIL:
                 allowed = 1;
                 msr_mask = MSR_CE | MSR_ME | MSR_DE;
@@ -377,7 +461,11 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
                 allowed = vcpu->arch.shared->msr & MSR_DE;
                 allowed = allowed && !crit;
                 msr_mask = MSR_ME;
-                int_class = INT_CLASS_CRIT;
+                if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
+                        int_class = INT_CLASS_DBG;
+                else
+                        int_class = INT_CLASS_CRIT;
+
                 break;
         }
 
@@ -654,20 +742,27 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 
         /*
          * Since we can't trap on MSR_FP in GS-mode, we consider the guest
-         * as always using the FPU.  Kernel usage of FP (via
-         * enable_kernel_fp()) in this thread must not occur while
-         * vcpu->fpu_active is set.
+         * as always using the FPU.
          */
-        vcpu->fpu_active = 1;
-
         kvmppc_load_guest_fp(vcpu);
 #endif
 
+#ifdef CONFIG_ALTIVEC
+        /* Save userspace AltiVec state in stack */
+        if (cpu_has_feature(CPU_FTR_ALTIVEC))
+                enable_kernel_altivec();
+        /*
+         * Since we can't trap on MSR_VEC in GS-mode, we consider the guest
+         * as always using the AltiVec.
+         */
+        kvmppc_load_guest_altivec(vcpu);
+#endif
+
         /* Switch to guest debug context */
-        debug = vcpu->arch.shadow_dbg_reg;
+        debug = vcpu->arch.dbg_reg;
         switch_booke_debug_regs(&debug);
         debug = current->thread.debug;
-        current->thread.debug = vcpu->arch.shadow_dbg_reg;
+        current->thread.debug = vcpu->arch.dbg_reg;
 
         vcpu->arch.pgdir = current->mm->pgd;
         kvmppc_fix_ee_before_entry();
@@ -683,8 +778,10 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 
 #ifdef CONFIG_PPC_FPU
         kvmppc_save_guest_fp(vcpu);
+#endif
 
-        vcpu->fpu_active = 0;
+#ifdef CONFIG_ALTIVEC
+        kvmppc_save_guest_altivec(vcpu);
 #endif
 
 out:
@@ -728,9 +825,36 @@ static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
 
 static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu)
 {
-        struct debug_reg *dbg_reg = &(vcpu->arch.shadow_dbg_reg);
+        struct debug_reg *dbg_reg = &(vcpu->arch.dbg_reg);
         u32 dbsr = vcpu->arch.dbsr;
 
+        if (vcpu->guest_debug == 0) {
+                /*
+                 * Debug resources belong to Guest.
+                 * Imprecise debug event is not injected
+                 */
+                if (dbsr & DBSR_IDE) {
+                        dbsr &= ~DBSR_IDE;
+                        if (!dbsr)
+                                return RESUME_GUEST;
+                }
+
+                if (dbsr && (vcpu->arch.shared->msr & MSR_DE) &&
+                            (vcpu->arch.dbg_reg.dbcr0 & DBCR0_IDM))
+                        kvmppc_core_queue_debug(vcpu);
+
+                /* Inject a program interrupt if trap debug is not allowed */
+                if ((dbsr & DBSR_TIE) && !(vcpu->arch.shared->msr & MSR_DE))
+                        kvmppc_core_queue_program(vcpu, ESR_PTR);
+
+                return RESUME_GUEST;
+        }
+
+        /*
+         * Debug resource owned by userspace.
+         * Clear guest dbsr (vcpu->arch.dbsr)
+         */
+        vcpu->arch.dbsr = 0;
         run->debug.arch.status = 0;
         run->debug.arch.address = vcpu->arch.pc;
 
@@ -868,7 +992,12 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
         case BOOKE_INTERRUPT_DATA_STORAGE:
         case BOOKE_INTERRUPT_DTLB_MISS:
         case BOOKE_INTERRUPT_HV_PRIV:
-                emulated = kvmppc_get_last_inst(vcpu, false, &last_inst);
+                emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
+                break;
+        case BOOKE_INTERRUPT_PROGRAM:
+                /* SW breakpoints arrive as illegal instructions on HV */
+                if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
+                        emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
                 break;
         default:
                 break;
@@ -947,6 +1076,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 break;
 
         case BOOKE_INTERRUPT_PROGRAM:
+                if ((vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) &&
+                        (last_inst == KVMPPC_INST_SW_BREAKPOINT)) {
+                        /*
+                         * We are here because of an SW breakpoint instr,
+                         * so lets return to host to handle.
+                         */
+                        r = kvmppc_handle_debug(run, vcpu);
+                        run->exit_reason = KVM_EXIT_DEBUG;
+                        kvmppc_account_exit(vcpu, DEBUG_EXITS);
+                        break;
+                }
+
                 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
                         /*
                          * Program traps generated by user-level software must
@@ -991,7 +1132,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
                 r = RESUME_GUEST;
                 break;
-#else
+#elif defined(CONFIG_SPE_POSSIBLE)
         case BOOKE_INTERRUPT_SPE_UNAVAIL:
                 /*
                  * Guest wants SPE, but host kernel doesn't support it.  Send
@@ -1012,6 +1153,22 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 run->hw.hardware_exit_reason = exit_nr;
                 r = RESUME_HOST;
                 break;
+#endif /* CONFIG_SPE_POSSIBLE */
+
+/*
+ * On cores with Vector category, KVM is loaded only if CONFIG_ALTIVEC,
+ * see kvmppc_core_check_processor_compat().
+ */
+#ifdef CONFIG_ALTIVEC
+        case BOOKE_INTERRUPT_ALTIVEC_UNAVAIL:
+                kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
+                r = RESUME_GUEST;
+                break;
+
+        case BOOKE_INTERRUPT_ALTIVEC_ASSIST:
+                kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_ASSIST);
+                r = RESUME_GUEST;
+                break;
 #endif
 
         case BOOKE_INTERRUPT_DATA_STORAGE:
@@ -1188,6 +1345,8 @@ out:
                 else {
                         /* interrupts now hard-disabled */
                         kvmppc_fix_ee_before_entry();
+                        kvmppc_load_guest_fp(vcpu);
+                        kvmppc_load_guest_altivec(vcpu);
                 }
         }
 
@@ -1243,6 +1402,11 @@ int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
         setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
                     (unsigned long)vcpu);
 
+        /*
+         * Clear DBSR.MRR to avoid guest debug interrupt as
+         * this is of host interest
+         */
+        mtspr(SPRN_DBSR, DBSR_MRR);
         return 0;
 }
 
@@ -1457,144 +1621,125 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs);
 }
 
-int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                        union kvmppc_one_reg *val)
 {
         int r = 0;
-        union kvmppc_one_reg val;
-        int size;
-
-        size = one_reg_size(reg->id);
-        if (size > sizeof(val))
-                return -EINVAL;
 
-        switch (reg->id) {
+        switch (id) {
         case KVM_REG_PPC_IAC1:
-                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac1);
+                *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1);
                 break;
         case KVM_REG_PPC_IAC2:
-                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac2);
+                *val = get_reg_val(id, vcpu->arch.dbg_reg.iac2);
                 break;
 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
         case KVM_REG_PPC_IAC3:
-                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac3);
+                *val = get_reg_val(id, vcpu->arch.dbg_reg.iac3);
                 break;
         case KVM_REG_PPC_IAC4:
-                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac4);
+                *val = get_reg_val(id, vcpu->arch.dbg_reg.iac4);
                 break;
 #endif
         case KVM_REG_PPC_DAC1:
-                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac1);
+                *val = get_reg_val(id, vcpu->arch.dbg_reg.dac1);
                 break;
         case KVM_REG_PPC_DAC2:
-                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac2);
+                *val = get_reg_val(id, vcpu->arch.dbg_reg.dac2);
                 break;
         case KVM_REG_PPC_EPR: {
                 u32 epr = kvmppc_get_epr(vcpu);
-                val = get_reg_val(reg->id, epr);
+                *val = get_reg_val(id, epr);
                 break;
         }
 #if defined(CONFIG_64BIT)
         case KVM_REG_PPC_EPCR:
-                val = get_reg_val(reg->id, vcpu->arch.epcr);
+                *val = get_reg_val(id, vcpu->arch.epcr);
                 break;
 #endif
         case KVM_REG_PPC_TCR:
-                val = get_reg_val(reg->id, vcpu->arch.tcr);
+                *val = get_reg_val(id, vcpu->arch.tcr);
                 break;
         case KVM_REG_PPC_TSR:
-                val = get_reg_val(reg->id, vcpu->arch.tsr);
+                *val = get_reg_val(id, vcpu->arch.tsr);
                 break;
         case KVM_REG_PPC_DEBUG_INST:
-                val = get_reg_val(reg->id, KVMPPC_INST_EHPRIV_DEBUG);
+                *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT);
                 break;
         case KVM_REG_PPC_VRSAVE:
-                val = get_reg_val(reg->id, vcpu->arch.vrsave);
+                *val = get_reg_val(id, vcpu->arch.vrsave);
                 break;
         default:
-                r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, reg->id, &val);
+                r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val);
                 break;
         }
 
-        if (r)
-                return r;
-
-        if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size))
-                r = -EFAULT;
-
         return r;
 }
 
-int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                        union kvmppc_one_reg *val)
 {
         int r = 0;
-        union kvmppc_one_reg val;
-        int size;
 
-        size = one_reg_size(reg->id);
-        if (size > sizeof(val))
-                return -EINVAL;
-
-        if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size))
-                return -EFAULT;
-
-        switch (reg->id) {
+        switch (id) {
         case KVM_REG_PPC_IAC1:
-                vcpu->arch.dbg_reg.iac1 = set_reg_val(reg->id, val);
+                vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val);
                 break;
         case KVM_REG_PPC_IAC2:
-                vcpu->arch.dbg_reg.iac2 = set_reg_val(reg->id, val);
+                vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val);
                 break;
 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
         case KVM_REG_PPC_IAC3:
-                vcpu->arch.dbg_reg.iac3 = set_reg_val(reg->id, val);
+                vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val);
                 break;
         case KVM_REG_PPC_IAC4:
-                vcpu->arch.dbg_reg.iac4 = set_reg_val(reg->id, val);
+                vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val);
                 break;
 #endif
         case KVM_REG_PPC_DAC1:
-                vcpu->arch.dbg_reg.dac1 = set_reg_val(reg->id, val);
+                vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val);
                 break;
         case KVM_REG_PPC_DAC2:
-                vcpu->arch.dbg_reg.dac2 = set_reg_val(reg->id, val);
+                vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val);
                 break;
         case KVM_REG_PPC_EPR: {
-                u32 new_epr = set_reg_val(reg->id, val);
+                u32 new_epr = set_reg_val(id, *val);
                 kvmppc_set_epr(vcpu, new_epr);
                 break;
         }
 #if defined(CONFIG_64BIT)
         case KVM_REG_PPC_EPCR: {
-                u32 new_epcr = set_reg_val(reg->id, val);
+                u32 new_epcr = set_reg_val(id, *val);
                 kvmppc_set_epcr(vcpu, new_epcr);
                 break;
         }
 #endif
         case KVM_REG_PPC_OR_TSR: {
-                u32 tsr_bits = set_reg_val(reg->id, val);
+                u32 tsr_bits = set_reg_val(id, *val);
                 kvmppc_set_tsr_bits(vcpu, tsr_bits);
                 break;
         }
         case KVM_REG_PPC_CLEAR_TSR: {
-                u32 tsr_bits = set_reg_val(reg->id, val);
+                u32 tsr_bits = set_reg_val(id, *val);
                 kvmppc_clr_tsr_bits(vcpu, tsr_bits);
                 break;
         }
         case KVM_REG_PPC_TSR: {
-                u32 tsr = set_reg_val(reg->id, val);
+                u32 tsr = set_reg_val(id, *val);
                 kvmppc_set_tsr(vcpu, tsr);
                 break;
         }
         case KVM_REG_PPC_TCR: {
-                u32 tcr = set_reg_val(reg->id, val);
+                u32 tcr = set_reg_val(id, *val);
                 kvmppc_set_tcr(vcpu, tcr);
                 break;
         }
         case KVM_REG_PPC_VRSAVE:
-                vcpu->arch.vrsave = set_reg_val(reg->id, val);
+                vcpu->arch.vrsave = set_reg_val(id, *val);
                 break;
         default:
-                r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, reg->id, &val);
+                r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val);
                 break;
         }
 
@@ -1694,10 +1839,8 @@ void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
         update_timer_ints(vcpu);
 }
 
-void kvmppc_decrementer_func(unsigned long data)
+void kvmppc_decrementer_func(struct kvm_vcpu *vcpu)
 {
-        struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
-
         if (vcpu->arch.tcr & TCR_ARE) {
                 vcpu->arch.dec = vcpu->arch.decar;
                 kvmppc_emulate_dec(vcpu);
@@ -1842,7 +1985,7 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
         int n, b = 0, w = 0;
 
         if (!(dbg->control & KVM_GUESTDBG_ENABLE)) {
-                vcpu->arch.shadow_dbg_reg.dbcr0 = 0;
+                vcpu->arch.dbg_reg.dbcr0 = 0;
                 vcpu->guest_debug = 0;
                 kvm_guest_protect_msr(vcpu, MSR_DE, false);
                 return 0;
@@ -1850,15 +1993,13 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 
         kvm_guest_protect_msr(vcpu, MSR_DE, true);
         vcpu->guest_debug = dbg->control;
-        vcpu->arch.shadow_dbg_reg.dbcr0 = 0;
-        /* Set DBCR0_EDM in guest visible DBCR0 register. */
-        vcpu->arch.dbg_reg.dbcr0 = DBCR0_EDM;
+        vcpu->arch.dbg_reg.dbcr0 = 0;
 
         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
-                vcpu->arch.shadow_dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
+                vcpu->arch.dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
 
         /* Code below handles only HW breakpoints */
-        dbg_reg = &(vcpu->arch.shadow_dbg_reg);
+        dbg_reg = &(vcpu->arch.dbg_reg);
 
 #ifdef CONFIG_KVM_BOOKE_HV
         /*
diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
index f753543c56fa..22ba08ea68e9 100644
--- a/arch/powerpc/kvm/booke.h
+++ b/arch/powerpc/kvm/booke.h
@@ -32,9 +32,15 @@
 #define BOOKE_IRQPRIO_ALIGNMENT 2
 #define BOOKE_IRQPRIO_PROGRAM 3
 #define BOOKE_IRQPRIO_FP_UNAVAIL 4
+#ifdef CONFIG_SPE_POSSIBLE
 #define BOOKE_IRQPRIO_SPE_UNAVAIL 5
 #define BOOKE_IRQPRIO_SPE_FP_DATA 6
 #define BOOKE_IRQPRIO_SPE_FP_ROUND 7
+#endif
+#ifdef CONFIG_PPC_E500MC
+#define BOOKE_IRQPRIO_ALTIVEC_UNAVAIL 5
+#define BOOKE_IRQPRIO_ALTIVEC_ASSIST 6
+#endif
 #define BOOKE_IRQPRIO_SYSCALL 8
 #define BOOKE_IRQPRIO_AP_UNAVAIL 9
 #define BOOKE_IRQPRIO_DTLB_MISS 10
@@ -116,40 +122,6 @@ extern int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn,
 extern int kvmppc_core_emulate_mfspr_e500(struct kvm_vcpu *vcpu, int sprn,
                                           ulong *spr_val);
 
-/*
- * Load up guest vcpu FP state if it's needed.
- * It also set the MSR_FP in thread so that host know
- * we're holding FPU, and then host can help to save
- * guest vcpu FP state if other threads require to use FPU.
- * This simulates an FP unavailable fault.
- *
- * It requires to be called with preemption disabled.
- */
-static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
-{
-#ifdef CONFIG_PPC_FPU
-        if (vcpu->fpu_active && !(current->thread.regs->msr & MSR_FP)) {
-                enable_kernel_fp();
-                load_fp_state(&vcpu->arch.fp);
-                current->thread.fp_save_area = &vcpu->arch.fp;
-                current->thread.regs->msr |= MSR_FP;
-        }
-#endif
-}
-
-/*
- * Save guest vcpu FP state into thread.
- * It requires to be called with preemption disabled.
- */
-static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
-{
-#ifdef CONFIG_PPC_FPU
-        if (vcpu->fpu_active && (current->thread.regs->msr & MSR_FP))
-                giveup_fpu(current);
-        current->thread.fp_save_area = NULL;
-#endif
-}
-
 static inline void kvmppc_clear_dbsr(void)
 {
         mtspr(SPRN_DBSR, mfspr(SPRN_DBSR));
diff --git a/arch/powerpc/kvm/booke_emulate.c b/arch/powerpc/kvm/booke_emulate.c
index 28c158881d23..a82f64502de1 100644
--- a/arch/powerpc/kvm/booke_emulate.c
+++ b/arch/powerpc/kvm/booke_emulate.c
@@ -25,6 +25,7 @@
 
 #define OP_19_XOP_RFI     50
 #define OP_19_XOP_RFCI    51
+#define OP_19_XOP_RFDI    39
 
 #define OP_31_XOP_MFMSR   83
 #define OP_31_XOP_WRTEE   131
@@ -37,6 +38,12 @@ static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
         kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
 }
 
+static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
+{
+        vcpu->arch.pc = vcpu->arch.dsrr0;
+        kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
+}
+
 static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
 {
         vcpu->arch.pc = vcpu->arch.csrr0;
@@ -65,6 +72,12 @@ int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         *advance = 0;
                         break;
 
+                case OP_19_XOP_RFDI:
+                        kvmppc_emul_rfdi(vcpu);
+                        kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
+                        *advance = 0;
+                        break;
+
                 default:
                         emulated = EMULATE_FAIL;
                         break;
@@ -118,6 +131,7 @@ int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
 int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
 {
         int emulated = EMULATE_DONE;
+        bool debug_inst = false;
 
         switch (sprn) {
         case SPRN_DEAR:
@@ -132,14 +146,128 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
         case SPRN_CSRR1:
                 vcpu->arch.csrr1 = spr_val;
                 break;
+        case SPRN_DSRR0:
+                vcpu->arch.dsrr0 = spr_val;
+                break;
+        case SPRN_DSRR1:
+                vcpu->arch.dsrr1 = spr_val;
+                break;
+        case SPRN_IAC1:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                vcpu->arch.dbg_reg.iac1 = spr_val;
+                break;
+        case SPRN_IAC2:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                vcpu->arch.dbg_reg.iac2 = spr_val;
+                break;
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+        case SPRN_IAC3:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                vcpu->arch.dbg_reg.iac3 = spr_val;
+                break;
+        case SPRN_IAC4:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                vcpu->arch.dbg_reg.iac4 = spr_val;
+                break;
+#endif
+        case SPRN_DAC1:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                vcpu->arch.dbg_reg.dac1 = spr_val;
+                break;
+        case SPRN_DAC2:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                vcpu->arch.dbg_reg.dac2 = spr_val;
+                break;
         case SPRN_DBCR0:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                spr_val &= (DBCR0_IDM | DBCR0_IC | DBCR0_BT | DBCR0_TIE |
+                        DBCR0_IAC1 | DBCR0_IAC2 | DBCR0_IAC3 | DBCR0_IAC4  |
+                        DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W);
+
                 vcpu->arch.dbg_reg.dbcr0 = spr_val;
                 break;
         case SPRN_DBCR1:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
                 vcpu->arch.dbg_reg.dbcr1 = spr_val;
                 break;
+        case SPRN_DBCR2:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
+                debug_inst = true;
+                vcpu->arch.dbg_reg.dbcr2 = spr_val;
+                break;
         case SPRN_DBSR:
+                /*
+                 * If userspace is debugging guest then guest
+                 * can not access debug registers.
+                 */
+                if (vcpu->guest_debug)
+                        break;
+
                 vcpu->arch.dbsr &= ~spr_val;
+                if (!(vcpu->arch.dbsr & ~DBSR_IDE))
+                        kvmppc_core_dequeue_debug(vcpu);
                 break;
         case SPRN_TSR:
                 kvmppc_clr_tsr_bits(vcpu, spr_val);
@@ -252,6 +380,10 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
                 emulated = EMULATE_FAIL;
         }
 
+        if (debug_inst) {
+                current->thread.debug = vcpu->arch.dbg_reg;
+                switch_booke_debug_regs(&vcpu->arch.dbg_reg);
+        }
         return emulated;
 }
 
@@ -278,12 +410,43 @@ int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
         case SPRN_CSRR1:
                 *spr_val = vcpu->arch.csrr1;
                 break;
+        case SPRN_DSRR0:
+                *spr_val = vcpu->arch.dsrr0;
+                break;
+        case SPRN_DSRR1:
+                *spr_val = vcpu->arch.dsrr1;
+                break;
+        case SPRN_IAC1:
+                *spr_val = vcpu->arch.dbg_reg.iac1;
+                break;
+        case SPRN_IAC2:
+                *spr_val = vcpu->arch.dbg_reg.iac2;
+                break;
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+        case SPRN_IAC3:
+                *spr_val = vcpu->arch.dbg_reg.iac3;
+                break;
+        case SPRN_IAC4:
+                *spr_val = vcpu->arch.dbg_reg.iac4;
+                break;
+#endif
+        case SPRN_DAC1:
+                *spr_val = vcpu->arch.dbg_reg.dac1;
+                break;
+        case SPRN_DAC2:
+                *spr_val = vcpu->arch.dbg_reg.dac2;
+                break;
         case SPRN_DBCR0:
                 *spr_val = vcpu->arch.dbg_reg.dbcr0;
+                if (vcpu->guest_debug)
+                        *spr_val = *spr_val | DBCR0_EDM;
                 break;
         case SPRN_DBCR1:
                 *spr_val = vcpu->arch.dbg_reg.dbcr1;
                 break;
+        case SPRN_DBCR2:
+                *spr_val = vcpu->arch.dbg_reg.dbcr2;
+                break;
         case SPRN_DBSR:
                 *spr_val = vcpu->arch.dbsr;
                 break;
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index e9fa56a911fd..81bd8a07aa51 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -238,7 +238,7 @@ kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
         SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
 kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
-        SPRN_SRR0, SPRN_SRR1,NEED_ESR
+        SPRN_SRR0, SPRN_SRR1, (NEED_ESR | NEED_EMU)
 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
         SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
@@ -256,11 +256,9 @@ kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \
         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \
         SPRN_SRR0, SPRN_SRR1, 0
-kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, EX_PARAMS(GEN), \
+kvm_handler BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, EX_PARAMS(GEN), \
         SPRN_SRR0, SPRN_SRR1, 0
-kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, EX_PARAMS(GEN), \
-        SPRN_SRR0, SPRN_SRR1, 0
-kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, EX_PARAMS(GEN), \
+kvm_handler BOOKE_INTERRUPT_ALTIVEC_ASSIST, EX_PARAMS(GEN), \
         SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
         SPRN_SRR0, SPRN_SRR1, 0
@@ -350,7 +348,7 @@ kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
         SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
-kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
+kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, (NEED_ESR | NEED_EMU)
 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
@@ -361,9 +359,6 @@ kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
-kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
-kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
-kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
 kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index a326178bdea5..72920bed3ac6 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -22,6 +22,7 @@
 #include <linux/kvm_host.h>
 #include <asm/mmu-book3e.h>
 #include <asm/tlb.h>
+#include <asm/cputhreads.h>
 
 enum vcpu_ftr {
         VCPU_FTR_MMU_V2
@@ -289,6 +290,25 @@ void kvmppc_e500_tlbil_all(struct kvmppc_vcpu_e500 *vcpu_e500);
 #define kvmppc_e500_get_tlb_stid(vcpu, gtlbe)       get_tlb_tid(gtlbe)
 #define get_tlbmiss_tid(vcpu)           get_cur_pid(vcpu)
 #define get_tlb_sts(gtlbe)              (gtlbe->mas1 & MAS1_TS)
+
+/*
+ * These functions should be called with preemption disabled
+ * and the returned value is valid only in that context
+ */
+static inline int get_thread_specific_lpid(int vm_lpid)
+{
+        int vcpu_lpid = vm_lpid;
+
+        if (threads_per_core == 2)
+                vcpu_lpid |= smp_processor_id() & 1;
+
+        return vcpu_lpid;
+}
+
+static inline int get_lpid(struct kvm_vcpu *vcpu)
+{
+        return get_thread_specific_lpid(vcpu->kvm->arch.lpid);
+}
 #else
 unsigned int kvmppc_e500_get_tlb_stid(struct kvm_vcpu *vcpu,
                                       struct kvm_book3e_206_tlb_entry *gtlbe);
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index c99c40e9182a..ce7291c79f6c 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -259,6 +259,7 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va
                 break;
 
         /* extra exceptions */
+#ifdef CONFIG_SPE_POSSIBLE
         case SPRN_IVOR32:
                 vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL] = spr_val;
                 break;
@@ -268,6 +269,15 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va
         case SPRN_IVOR34:
                 vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND] = spr_val;
                 break;
+#endif
+#ifdef CONFIG_ALTIVEC
+        case SPRN_IVOR32:
+                vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_UNAVAIL] = spr_val;
+                break;
+        case SPRN_IVOR33:
+                vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_ASSIST] = spr_val;
+                break;
+#endif
         case SPRN_IVOR35:
                 vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR] = spr_val;
                 break;
@@ -381,6 +391,7 @@ int kvmppc_core_emulate_mfspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong *spr_v
                 break;
 
         /* extra exceptions */
+#ifdef CONFIG_SPE_POSSIBLE
         case SPRN_IVOR32:
                 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL];
                 break;
@@ -390,6 +401,15 @@ int kvmppc_core_emulate_mfspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong *spr_v
         case SPRN_IVOR34:
                 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND];
                 break;
+#endif
+#ifdef CONFIG_ALTIVEC
+        case SPRN_IVOR32:
+                *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_UNAVAIL];
+                break;
+        case SPRN_IVOR33:
+                *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_ASSIST];
+                break;
+#endif
         case SPRN_IVOR35:
                 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR];
                 break;
diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
index 08f14bb57897..769778f855b0 100644
--- a/arch/powerpc/kvm/e500_mmu_host.c
+++ b/arch/powerpc/kvm/e500_mmu_host.c
@@ -69,7 +69,8 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode)
  * writing shadow tlb entry to host TLB
  */
 static inline void __write_host_tlbe(struct kvm_book3e_206_tlb_entry *stlbe,
-                                     uint32_t mas0)
+                                     uint32_t mas0,
+                                     uint32_t lpid)
 {
         unsigned long flags;
 
@@ -80,7 +81,7 @@ static inline void __write_host_tlbe(struct kvm_book3e_206_tlb_entry *stlbe,
         mtspr(SPRN_MAS3, (u32)stlbe->mas7_3);
         mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32));
 #ifdef CONFIG_KVM_BOOKE_HV
-        mtspr(SPRN_MAS8, stlbe->mas8);
+        mtspr(SPRN_MAS8, MAS8_TGS | get_thread_specific_lpid(lpid));
 #endif
         asm volatile("isync; tlbwe" : : : "memory");
 
@@ -129,11 +130,12 @@ static inline void write_host_tlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
 
         if (tlbsel == 0) {
                 mas0 = get_host_mas0(stlbe->mas2);
-                __write_host_tlbe(stlbe, mas0);
+                __write_host_tlbe(stlbe, mas0, vcpu_e500->vcpu.kvm->arch.lpid);
         } else {
                 __write_host_tlbe(stlbe,
                                   MAS0_TLBSEL(1) |
-                                  MAS0_ESEL(to_htlb1_esel(sesel)));
+                                  MAS0_ESEL(to_htlb1_esel(sesel)),
+                                  vcpu_e500->vcpu.kvm->arch.lpid);
         }
 }
 
@@ -176,7 +178,7 @@ void kvmppc_map_magic(struct kvm_vcpu *vcpu)
                        MAS3_SW | MAS3_SR | MAS3_UW | MAS3_UR;
         magic.mas8 = 0;
 
-        __write_host_tlbe(&magic, MAS0_TLBSEL(1) | MAS0_ESEL(tlbcam_index));
+        __write_host_tlbe(&magic, MAS0_TLBSEL(1) | MAS0_ESEL(tlbcam_index), 0);
         preempt_enable();
 }
 #endif
@@ -317,10 +319,6 @@ static void kvmppc_e500_setup_stlbe(
         stlbe->mas2 = (gvaddr & MAS2_EPN) | (ref->flags & E500_TLB_MAS2_ATTR);
         stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) |
                         e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
-
-#ifdef CONFIG_KVM_BOOKE_HV
-        stlbe->mas8 = MAS8_TGS | vcpu->kvm->arch.lpid;
-#endif
 }
 
 static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
@@ -633,7 +631,7 @@ int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, enum instruction_type type,
 
         local_irq_save(flags);
         mtspr(SPRN_MAS6, (vcpu->arch.pid << MAS6_SPID_SHIFT) | addr_space);
-        mtspr(SPRN_MAS5, MAS5_SGS | vcpu->kvm->arch.lpid);
+        mtspr(SPRN_MAS5, MAS5_SGS | get_lpid(vcpu));
         asm volatile("tlbsx 0, %[geaddr]\n" : :
                      [geaddr] "r" (geaddr));
         mtspr(SPRN_MAS5, 0);
@@ -732,7 +730,7 @@ int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
         return 0;
 }
 
-int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
 {
         /* XXX could be more clever ;) */
         return 0;
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 164bad2a19bf..2fdc8722e324 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -48,10 +48,11 @@ void kvmppc_set_pending_interrupt(struct kvm_vcpu *vcpu, enum int_class type)
                 return;
         }
 
-
-        tag = PPC_DBELL_LPID(vcpu->kvm->arch.lpid) | vcpu->vcpu_id;
+        preempt_disable();
+        tag = PPC_DBELL_LPID(get_lpid(vcpu)) | vcpu->vcpu_id;
         mb();
         ppc_msgsnd(dbell_type, 0, tag);
+        preempt_enable();
 }
 
 /* gtlbe must not be mapped by more than one host tlb entry */
@@ -60,12 +61,11 @@ void kvmppc_e500_tlbil_one(struct kvmppc_vcpu_e500 *vcpu_e500,
 {
         unsigned int tid, ts;
         gva_t eaddr;
-        u32 val, lpid;
+        u32 val;
         unsigned long flags;
 
         ts = get_tlb_ts(gtlbe);
         tid = get_tlb_tid(gtlbe);
-        lpid = vcpu_e500->vcpu.kvm->arch.lpid;
 
         /* We search the host TLB to invalidate its shadow TLB entry */
         val = (tid << 16) | ts;
@@ -74,7 +74,7 @@ void kvmppc_e500_tlbil_one(struct kvmppc_vcpu_e500 *vcpu_e500,
         local_irq_save(flags);
 
         mtspr(SPRN_MAS6, val);
-        mtspr(SPRN_MAS5, MAS5_SGS | lpid);
+        mtspr(SPRN_MAS5, MAS5_SGS | get_lpid(&vcpu_e500->vcpu));
 
         asm volatile("tlbsx 0, %[eaddr]\n" : : [eaddr] "r" (eaddr));
         val = mfspr(SPRN_MAS1);
@@ -95,7 +95,7 @@ void kvmppc_e500_tlbil_all(struct kvmppc_vcpu_e500 *vcpu_e500)
         unsigned long flags;
 
         local_irq_save(flags);
-        mtspr(SPRN_MAS5, MAS5_SGS | vcpu_e500->vcpu.kvm->arch.lpid);
+        mtspr(SPRN_MAS5, MAS5_SGS | get_lpid(&vcpu_e500->vcpu));
         asm volatile("tlbilxlpid");
         mtspr(SPRN_MAS5, 0);
         local_irq_restore(flags);
@@ -110,6 +110,7 @@ void kvmppc_mmu_msr_notify(struct kvm_vcpu *vcpu, u32 old_msr)
 {
 }
 
+/* We use two lpids per VM */
 static DEFINE_PER_CPU(struct kvm_vcpu *[KVMPPC_NR_LPIDS], last_vcpu_of_lpid);
 
 static void kvmppc_core_vcpu_load_e500mc(struct kvm_vcpu *vcpu, int cpu)
@@ -118,10 +119,12 @@ static void kvmppc_core_vcpu_load_e500mc(struct kvm_vcpu *vcpu, int cpu)
 
         kvmppc_booke_vcpu_load(vcpu, cpu);
 
-        mtspr(SPRN_LPID, vcpu->kvm->arch.lpid);
+        mtspr(SPRN_LPID, get_lpid(vcpu));
         mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
         mtspr(SPRN_GPIR, vcpu->vcpu_id);
         mtspr(SPRN_MSRP, vcpu->arch.shadow_msrp);
+        vcpu->arch.eplc = EPC_EGS | (get_lpid(vcpu) << EPC_ELPID_SHIFT);
+        vcpu->arch.epsc = vcpu->arch.eplc;
         mtspr(SPRN_EPLC, vcpu->arch.eplc);
         mtspr(SPRN_EPSC, vcpu->arch.epsc);
 
@@ -141,12 +144,10 @@ static void kvmppc_core_vcpu_load_e500mc(struct kvm_vcpu *vcpu, int cpu)
         mtspr(SPRN_GESR, vcpu->arch.shared->esr);
 
         if (vcpu->arch.oldpir != mfspr(SPRN_PIR) ||
-            __get_cpu_var(last_vcpu_of_lpid)[vcpu->kvm->arch.lpid] != vcpu) {
+            __get_cpu_var(last_vcpu_of_lpid)[get_lpid(vcpu)] != vcpu) {
                 kvmppc_e500_tlbil_all(vcpu_e500);
-                __get_cpu_var(last_vcpu_of_lpid)[vcpu->kvm->arch.lpid] = vcpu;
+                __get_cpu_var(last_vcpu_of_lpid)[get_lpid(vcpu)] = vcpu;
         }
-
-        kvmppc_load_guest_fp(vcpu);
 }
 
 static void kvmppc_core_vcpu_put_e500mc(struct kvm_vcpu *vcpu)
@@ -179,6 +180,16 @@ int kvmppc_core_check_processor_compat(void)
                 r = 0;
         else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
                 r = 0;
+#ifdef CONFIG_ALTIVEC
+        /*
+         * Since guests have the priviledge to enable AltiVec, we need AltiVec
+         * support in the host to save/restore their context.
+         * Don't use CPU_FTR_ALTIVEC to identify cores with AltiVec unit
+         * because it's cleared in the absence of CONFIG_ALTIVEC!
+         */
+        else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
+                r = 0;
+#endif
         else
                 r = -ENOTSUPP;
 
@@ -194,9 +205,7 @@ int kvmppc_core_vcpu_setup(struct kvm_vcpu *vcpu)
 #ifdef CONFIG_64BIT
         vcpu->arch.shadow_epcr |= SPRN_EPCR_ICM;
 #endif
-        vcpu->arch.shadow_msrp = MSRP_UCLEP | MSRP_DEP | MSRP_PMMP;
-        vcpu->arch.eplc = EPC_EGS | (vcpu->kvm->arch.lpid << EPC_ELPID_SHIFT);
-        vcpu->arch.epsc = vcpu->arch.eplc;
+        vcpu->arch.shadow_msrp = MSRP_UCLEP | MSRP_PMMP;
 
         vcpu->arch.pvr = mfspr(SPRN_PVR);
         vcpu_e500->svr = mfspr(SPRN_SVR);
@@ -356,13 +365,26 @@ static int kvmppc_core_init_vm_e500mc(struct kvm *kvm)
         if (lpid < 0)
                 return lpid;
 
+        /*
+         * Use two lpids per VM on cores with two threads like e6500. Use
+         * even numbers to speedup vcpu lpid computation with consecutive lpids
+         * per VM. vm1 will use lpids 2 and 3, vm2 lpids 4 and 5, and so on.
+         */
+        if (threads_per_core == 2)
+                lpid <<= 1;
+
         kvm->arch.lpid = lpid;
         return 0;
 }
 
 static void kvmppc_core_destroy_vm_e500mc(struct kvm *kvm)
 {
-        kvmppc_free_lpid(kvm->arch.lpid);
+        int lpid = kvm->arch.lpid;
+
+        if (threads_per_core == 2)
+                lpid >>= 1;
+
+        kvmppc_free_lpid(lpid);
 }
 
 static struct kvmppc_ops kvm_ops_e500mc = {
@@ -390,7 +412,13 @@ static int __init kvmppc_e500mc_init(void)
         if (r)
                 goto err_out;
 
-        kvmppc_init_lpid(64);
+        /*
+         * Use two lpids per VM on dual threaded processors like e6500
+         * to workarround the lack of tlb write conditional instruction.
+         * Expose half the number of available hardware lpids to the lpid
+         * allocator.
+         */
+        kvmppc_init_lpid(KVMPPC_NR_LPIDS/threads_per_core);
         kvmppc_claim_lpid(0); /* host */
 
         r = kvm_init(NULL, sizeof(struct kvmppc_vcpu_e500), 0, THIS_MODULE);
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index e96b50d0bdab..5cc2e7af3a7b 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -219,7 +219,7 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
         /* this default type might be overwritten by subcategories */
         kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
 
-        emulated = kvmppc_get_last_inst(vcpu, false, &inst);
+        emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
         if (emulated != EMULATE_DONE)
                 return emulated;
 
@@ -274,6 +274,21 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 }
                 break;
 
+        case 0:
+                /*
+                 * Instruction with primary opcode 0. Based on PowerISA
+                 * these are illegal instructions.
+                 */
+                if (inst == KVMPPC_INST_SW_BREAKPOINT) {
+                        run->exit_reason = KVM_EXIT_DEBUG;
+                        run->debug.arch.address = kvmppc_get_pc(vcpu);
+                        emulated = EMULATE_EXIT_USER;
+                        advance = 0;
+                } else
+                        emulated = EMULATE_FAIL;
+
+                break;
+
         default:
                 emulated = EMULATE_FAIL;
         }
diff --git a/arch/powerpc/kvm/emulate_loadstore.c b/arch/powerpc/kvm/emulate_loadstore.c
index 0de4ffa175a9..6d3c0ee1d744 100644
--- a/arch/powerpc/kvm/emulate_loadstore.c
+++ b/arch/powerpc/kvm/emulate_loadstore.c
@@ -58,7 +58,7 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)
         /* this default type might be overwritten by subcategories */
         kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
 
-        emulated = kvmppc_get_last_inst(vcpu, false, &inst);
+        emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
         if (emulated != EMULATE_DONE)
                 return emulated;
 
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 4c79284b58be..c1f8f53cd312 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -294,7 +294,7 @@ int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu)
         {
                 u32 last_inst;
 
-                kvmppc_get_last_inst(vcpu, false, &last_inst);
+                kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
                 /* XXX Deliver Program interrupt to guest. */
                 pr_emerg("%s: emulation failed (%08x)\n", __func__, last_inst);
                 r = RESUME_HOST;
@@ -384,24 +384,16 @@ int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr,
 }
 EXPORT_SYMBOL_GPL(kvmppc_ld);
 
-int kvm_arch_hardware_enable(void *garbage)
+int kvm_arch_hardware_enable(void)
 {
         return 0;
 }
 
-void kvm_arch_hardware_disable(void *garbage)
-{
-}
-
 int kvm_arch_hardware_setup(void)
 {
         return 0;
 }
 
-void kvm_arch_hardware_unsetup(void)
-{
-}
-
 void kvm_arch_check_processor_compat(void *rtn)
 {
         *(int *)rtn = kvmppc_core_check_processor_compat();
@@ -462,10 +454,6 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
         module_put(kvm->arch.kvm_ops->owner);
 }
 
-void kvm_arch_sync_events(struct kvm *kvm)
-{
-}
-
 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 {
         int r;
@@ -608,10 +596,6 @@ int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
         return kvmppc_core_create_memslot(kvm, slot, npages);
 }
 
-void kvm_arch_memslots_updated(struct kvm *kvm)
-{
-}
-
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                    struct kvm_memory_slot *memslot,
                                    struct kvm_userspace_memory_region *mem,
@@ -628,10 +612,6 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
         kvmppc_core_commit_memory_region(kvm, mem, old);
 }
 
-void kvm_arch_flush_shadow_all(struct kvm *kvm)
-{
-}
-
 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
                                    struct kvm_memory_slot *slot)
 {
@@ -658,7 +638,6 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 {
         /* Make sure we're not using the vcpu anymore */
         hrtimer_cancel(&vcpu->arch.dec_timer);
-        tasklet_kill(&vcpu->arch.tasklet);
 
         kvmppc_remove_vcpu_debugfs(vcpu);
 
@@ -684,16 +663,12 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
         return kvmppc_core_pending_dec(vcpu);
 }
 
-/*
- * low level hrtimer wake routine. Because this runs in hardirq context
- * we schedule a tasklet to do the real work.
- */
 enum hrtimer_restart kvmppc_decrementer_wakeup(struct hrtimer *timer)
 {
         struct kvm_vcpu *vcpu;
 
         vcpu = container_of(timer, struct kvm_vcpu, arch.dec_timer);
-        tasklet_schedule(&vcpu->arch.tasklet);
+        kvmppc_decrementer_func(vcpu);
 
         return HRTIMER_NORESTART;
 }
@@ -703,7 +678,6 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         int ret;
 
         hrtimer_init(&vcpu->arch.dec_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS);
-        tasklet_init(&vcpu->arch.tasklet, kvmppc_decrementer_func, (ulong)vcpu);
         vcpu->arch.dec_timer.function = kvmppc_decrementer_wakeup;
         vcpu->arch.dec_expires = ~(u64)0;
 
@@ -927,6 +901,103 @@ int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
 }
 EXPORT_SYMBOL_GPL(kvmppc_handle_store);
 
+int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        int r = 0;
+        union kvmppc_one_reg val;
+        int size;
+
+        size = one_reg_size(reg->id);
+        if (size > sizeof(val))
+                return -EINVAL;
+
+        r = kvmppc_get_one_reg(vcpu, reg->id, &val);
+        if (r == -EINVAL) {
+                r = 0;
+                switch (reg->id) {
+#ifdef CONFIG_ALTIVEC
+                case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
+                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
+                                r = -ENXIO;
+                                break;
+                        }
+                        vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0] = val.vval;
+                        break;
+                case KVM_REG_PPC_VSCR:
+                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
+                                r = -ENXIO;
+                                break;
+                        }
+                        vcpu->arch.vr.vscr.u[3] = set_reg_val(reg->id, val);
+                        break;
+                case KVM_REG_PPC_VRSAVE:
+                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
+                                r = -ENXIO;
+                                break;
+                        }
+                        vcpu->arch.vrsave = set_reg_val(reg->id, val);
+                        break;
+#endif /* CONFIG_ALTIVEC */
+                default:
+                        r = -EINVAL;
+                        break;
+                }
+        }
+
+        if (r)
+                return r;
+
+        if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size))
+                r = -EFAULT;
+
+        return r;
+}
+
+int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        int r;
+        union kvmppc_one_reg val;
+        int size;
+
+        size = one_reg_size(reg->id);
+        if (size > sizeof(val))
+                return -EINVAL;
+
+        if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size))
+                return -EFAULT;
+
+        r = kvmppc_set_one_reg(vcpu, reg->id, &val);
+        if (r == -EINVAL) {
+                r = 0;
+                switch (reg->id) {
+#ifdef CONFIG_ALTIVEC
+                case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
+                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
+                                r = -ENXIO;
+                                break;
+                        }
+                        val.vval = vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0];
+                        break;
+                case KVM_REG_PPC_VSCR:
+                        if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
+                                r = -ENXIO;
+                                break;
+                        }
+                        val = get_reg_val(reg->id, vcpu->arch.vr.vscr.u[3]);
+                        break;
+                case KVM_REG_PPC_VRSAVE:
+                        val = get_reg_val(reg->id, vcpu->arch.vrsave);
+                        break;
+#endif /* CONFIG_ALTIVEC */
+                default:
+                        r = -EINVAL;
+                        break;
+                }
+        }
+
+        return r;
+}
+
 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
         int r;
@@ -1343,9 +1414,4 @@ int kvm_arch_init(void *opaque)
         return 0;
 }
 
-void kvm_arch_exit(void)
-{
-
-}
-
 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ppc_instr);
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 3afa6f4c1957..cbae2dfd053c 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -686,7 +686,7 @@ void bpf_jit_compile(struct bpf_prog *fp)
                 ((u64 *)image)[0] = (u64)code_base;
                 ((u64 *)image)[1] = local_paca->kernel_toc;
                 fp->bpf_func = (void *)image;
-                fp->jited = 1;
+                fp->jited = true;
         }
 out:
         kfree(addrs);
@@ -697,5 +697,6 @@ void bpf_jit_free(struct bpf_prog *fp)
 {
         if (fp->jited)
                 module_free(NULL, fp->bpf_func);
-        kfree(fp);
+
+        bpf_prog_unlock_free(fp);
 }
diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c
index 74d1e780748b..2396dda282cd 100644
--- a/arch/powerpc/perf/callchain.c
+++ b/arch/powerpc/perf/callchain.c
@@ -35,7 +35,7 @@ static int valid_next_sp(unsigned long sp, unsigned long prev_sp)
                 return 0;               /* must be 16-byte aligned */
         if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD))
                 return 0;
-        if (sp >= prev_sp + STACK_FRAME_OVERHEAD)
+        if (sp >= prev_sp + STACK_FRAME_MIN_SIZE)
                 return 1;
         /*
          * sp could decrease when we jump off an interrupt stack
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index e238b6a55b15..73997027b085 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -141,7 +141,8 @@ static int mcu_gpiochip_add(struct mcu *mcu)
 
 static int mcu_gpiochip_remove(struct mcu *mcu)
 {
-        return gpiochip_remove(&mcu->gc);
+        gpiochip_remove(&mcu->gc);
+        return 0;
 }
 
 static int mcu_probe(struct i2c_client *client, const struct i2c_device_id *id)
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index e8bc40869cbd..7d9ee3d8c618 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -303,9 +303,13 @@ config PPC_ICSWX_USE_SIGILL
 
           If in doubt, say N here.
 
+config SPE_POSSIBLE
+        def_bool y
+        depends on E200 || (E500 && !PPC_E500MC)
+
 config SPE
         bool "SPE Support"
-        depends on E200 || (E500 && !PPC_E500MC)
+        depends on SPE_POSSIBLE
         default y
         ---help---
           This option enables kernel support for the Signal Processing
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index 85825b5401e5..862b32702d29 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -199,14 +199,6 @@ out_error:
         return msic;
 }
 
-static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
-{
-        if (!find_msi_translator(dev))
-                return -ENODEV;
-
-        return 0;
-}
-
 static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
 {
         struct device_node *dn;
@@ -416,7 +408,6 @@ static int axon_msi_probe(struct platform_device *device)
 
         ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
         ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
-        ppc_md.msi_check_device = axon_msi_check_device;
 
         axon_msi_debug_setup(dn, msic);
 
diff --git a/arch/powerpc/platforms/powernv/opal-hmi.c b/arch/powerpc/platforms/powernv/opal-hmi.c
index 97ac8dc33667..5e1ed1575aab 100644
--- a/arch/powerpc/platforms/powernv/opal-hmi.c
+++ b/arch/powerpc/platforms/powernv/opal-hmi.c
@@ -28,6 +28,7 @@
 
 #include <asm/opal.h>
 #include <asm/cputable.h>
+#include <asm/machdep.h>
 
 static int opal_hmi_handler_nb_init;
 struct OpalHmiEvtNode {
@@ -185,4 +186,4 @@ static int __init opal_hmi_handler_init(void)
         }
         return 0;
 }
-subsys_initcall(opal_hmi_handler_init);
+machine_subsys_initcall(powernv, opal_hmi_handler_init);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index b44eec3e8dbd..4b005ae5dc4b 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -322,7 +322,7 @@ static void opal_handle_message(void)
 
         /* check for errors. */
         if (ret) {
-                pr_warning("%s: Failed to retrive opal message, err=%lld\n",
+                pr_warning("%s: Failed to retrieve opal message, err=%lld\n",
                                 __func__, ret);
                 return;
         }
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index b854b57ed5e1..b45c49249a5d 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -46,29 +46,21 @@
 //#define cfg_dbg(fmt...)       printk(fmt)
 
 #ifdef CONFIG_PCI_MSI
-static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
-{
-        struct pci_controller *hose = pci_bus_to_host(pdev->bus);
-        struct pnv_phb *phb = hose->private_data;
-        struct pci_dn *pdn = pci_get_pdn(pdev);
-
-        if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
-                return -ENODEV;
-
-        return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
-}
-
 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 {
         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
         struct pnv_phb *phb = hose->private_data;
+        struct pci_dn *pdn = pci_get_pdn(pdev);
         struct msi_desc *entry;
         struct msi_msg msg;
         int hwirq;
         unsigned int virq;
         int rc;
 
-        if (WARN_ON(!phb))
+        if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
+                return -ENODEV;
+
+        if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
                 return -ENODEV;
 
         list_for_each_entry(entry, &pdev->msi_list, list) {
@@ -860,7 +852,6 @@ void __init pnv_pci_init(void)
 
         /* Configure MSIs */
 #ifdef CONFIG_PCI_MSI
-        ppc_md.msi_check_device = pnv_msi_check_device;
         ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
         ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
 #endif
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index c904583baf4b..34064f50945e 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -113,7 +113,7 @@ out:
 static int pseries_remove_mem_node(struct device_node *np)
 {
         const char *type;
-        const unsigned int *regs;
+        const __be32 *regs;
         unsigned long base;
         unsigned int lmb_size;
         int ret = -EINVAL;
@@ -126,14 +126,14 @@ static int pseries_remove_mem_node(struct device_node *np)
                 return 0;
 
         /*
-         * Find the bae address and size of the memblock
+         * Find the base address and size of the memblock
          */
         regs = of_get_property(np, "reg", NULL);
         if (!regs)
                 return ret;
 
-        base = *(unsigned long *)regs;
-        lmb_size = regs[3];
+        base = be64_to_cpu(*(unsigned long *)regs);
+        lmb_size = be32_to_cpu(regs[3]);
 
         pseries_remove_memblock(base, lmb_size);
         return 0;
@@ -153,7 +153,7 @@ static inline int pseries_remove_mem_node(struct device_node *np)
 static int pseries_add_mem_node(struct device_node *np)
 {
         const char *type;
-        const unsigned int *regs;
+        const __be32 *regs;
         unsigned long base;
         unsigned int lmb_size;
         int ret = -EINVAL;
@@ -172,8 +172,8 @@ static int pseries_add_mem_node(struct device_node *np)
         if (!regs)
                 return ret;
 
-        base = *(unsigned long *)regs;
-        lmb_size = regs[3];
+        base = be64_to_cpu(*(unsigned long *)regs);
+        lmb_size = be32_to_cpu(regs[3]);
 
         /*
          * Update memory region to represent the memory add
@@ -187,44 +187,46 @@ static int pseries_update_drconf_memory(struct of_prop_reconfig *pr)
         struct of_drconf_cell *new_drmem, *old_drmem;
         unsigned long memblock_size;
         u32 entries;
-        u32 *p;
+        __be32 *p;
         int i, rc = -EINVAL;
 
         memblock_size = pseries_memory_block_size();
         if (!memblock_size)
                 return -EINVAL;
 
-        p = (u32 *) pr->old_prop->value;
+        p = (__be32 *) pr->old_prop->value;
         if (!p)
                 return -EINVAL;
 
         /* The first int of the property is the number of lmb's described
          * by the property. This is followed by an array of of_drconf_cell
-         * entries. Get the niumber of entries and skip to the array of
+         * entries. Get the number of entries and skip to the array of
          * of_drconf_cell's.
          */
-        entries = *p++;
+        entries = be32_to_cpu(*p++);
         old_drmem = (struct of_drconf_cell *)p;
 
-        p = (u32 *)pr->prop->value;
+        p = (__be32 *)pr->prop->value;
         p++;
         new_drmem = (struct of_drconf_cell *)p;
 
         for (i = 0; i < entries; i++) {
-                if ((old_drmem[i].flags & DRCONF_MEM_ASSIGNED) &&
-                    (!(new_drmem[i].flags & DRCONF_MEM_ASSIGNED))) {
-                        rc = pseries_remove_memblock(old_drmem[i].base_addr,
+                if ((be32_to_cpu(old_drmem[i].flags) & DRCONF_MEM_ASSIGNED) &&
+                    (!(be32_to_cpu(new_drmem[i].flags) & DRCONF_MEM_ASSIGNED))) {
+                        rc = pseries_remove_memblock(
+                                be64_to_cpu(old_drmem[i].base_addr),
                                                      memblock_size);
                         break;
-                } else if ((!(old_drmem[i].flags & DRCONF_MEM_ASSIGNED)) &&
-                           (new_drmem[i].flags & DRCONF_MEM_ASSIGNED)) {
-                        rc = memblock_add(old_drmem[i].base_addr,
+                } else if ((!(be32_to_cpu(old_drmem[i].flags) &
+                            DRCONF_MEM_ASSIGNED)) &&
+                            (be32_to_cpu(new_drmem[i].flags) &
+                            DRCONF_MEM_ASSIGNED)) {
+                        rc = memblock_add(be64_to_cpu(old_drmem[i].base_addr),
                                           memblock_size);
                         rc = (rc < 0) ? -EINVAL : 0;
                         break;
                 }
         }
-
         return rc;
 }
 
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 18ff4626d74e..8ab5add4ac82 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -336,26 +336,6 @@ out:
         return request;
 }
 
-static int rtas_msi_check_device(struct pci_dev *pdev, int nvec, int type)
-{
-        int quota, rc;
-
-        if (type == PCI_CAP_ID_MSIX)
-                rc = check_req_msix(pdev, nvec);
-        else
-                rc = check_req_msi(pdev, nvec);
-
-        if (rc)
-                return rc;
-
-        quota = msi_quota_for_device(pdev, nvec);
-
-        if (quota && quota < nvec)
-                return quota;
-
-        return 0;
-}
-
 static int check_msix_entries(struct pci_dev *pdev)
 {
         struct msi_desc *entry;
@@ -397,15 +377,24 @@ static void rtas_hack_32bit_msi_gen2(struct pci_dev *pdev)
 static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type)
 {
         struct pci_dn *pdn;
-        int hwirq, virq, i, rc;
+        int hwirq, virq, i, quota, rc;
         struct msi_desc *entry;
         struct msi_msg msg;
         int nvec = nvec_in;
         int use_32bit_msi_hack = 0;
 
-        pdn = pci_get_pdn(pdev);
-        if (!pdn)
-                return -ENODEV;
+        if (type == PCI_CAP_ID_MSIX)
+                rc = check_req_msix(pdev, nvec);
+        else
+                rc = check_req_msi(pdev, nvec);
+
+        if (rc)
+                return rc;
+
+        quota = msi_quota_for_device(pdev, nvec);
+
+        if (quota && quota < nvec)
+                return quota;
 
         if (type == PCI_CAP_ID_MSIX && check_msix_entries(pdev))
                 return -EINVAL;
@@ -416,12 +405,14 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type)
          */
         if (type == PCI_CAP_ID_MSIX) {
                 int m = roundup_pow_of_two(nvec);
-                int quota = msi_quota_for_device(pdev, m);
+                quota = msi_quota_for_device(pdev, m);
 
                 if (quota >= m)
                         nvec = m;
         }
 
+        pdn = pci_get_pdn(pdev);
+
         /*
          * Try the new more explicit firmware interface, if that fails fall
          * back to the old interface. The old interface is known to never
@@ -485,7 +476,7 @@ again:
                 irq_set_msi_desc(virq, entry);
 
                 /* Read config space back so we can restore after reset */
-                read_msi_msg(virq, &msg);
+                __read_msi_msg(entry, &msg);
                 entry->msg = msg;
         }
 
@@ -526,7 +517,6 @@ static int rtas_msi_init(void)
         WARN_ON(ppc_md.setup_msi_irqs);
         ppc_md.setup_msi_irqs = rtas_setup_msi_irqs;
         ppc_md.teardown_msi_irqs = rtas_teardown_msi_irqs;
-        ppc_md.msi_check_device = rtas_msi_check_device;
 
         WARN_ON(ppc_md.pci_irq_fixup);
         ppc_md.pci_irq_fixup = rtas_msi_pci_irq_fixup;
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 77efbaec7b9c..b32e79dbef4f 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -109,14 +109,6 @@ static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
         return 0;
 }
 
-static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
-{
-        if (type == PCI_CAP_ID_MSIX)
-                pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
-
-        return 0;
-}
-
 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
 {
         struct msi_desc *entry;
@@ -173,6 +165,9 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
         struct msi_msg msg;
         struct fsl_msi *msi_data;
 
+        if (type == PCI_CAP_ID_MSIX)
+                pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
+
         /*
          * If the PCI node has an fsl,msi property, then we need to use it
          * to find the specific MSI.
@@ -527,7 +522,6 @@ static int fsl_of_msi_probe(struct platform_device *dev)
         if (!ppc_md.setup_msi_irqs) {
                 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
                 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
-                ppc_md.msi_check_device = fsl_msi_check_device;
         } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
                 dev_err(&dev->dev, "Different MSI driver already installed!\n");
                 err = -ENODEV;
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 38e62382070c..15dccd35fa11 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -63,14 +63,6 @@ static struct irq_chip mpic_pasemi_msi_chip = {
         .name                   = "PASEMI-MSI",
 };
 
-static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
-{
-        if (type == PCI_CAP_ID_MSIX)
-                pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
-
-        return 0;
-}
-
 static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
 {
         struct msi_desc *entry;
@@ -97,6 +89,8 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
         struct msi_msg msg;
         int hwirq;
 
+        if (type == PCI_CAP_ID_MSIX)
+                pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
         pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
                  pdev, nvec, type);
 
@@ -169,7 +163,6 @@ int mpic_pasemi_msi_init(struct mpic *mpic)
         WARN_ON(ppc_md.setup_msi_irqs);
         ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
         ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
-        ppc_md.msi_check_device = pasemi_msi_check_device;
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index 9a7aa0ed9c1c..623d7fba15b4 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -105,22 +105,6 @@ static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
         return 0;
 }
 
-static int u3msi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
-{
-        if (type == PCI_CAP_ID_MSIX)
-                pr_debug("u3msi: MSI-X untested, trying anyway.\n");
-
-        /* If we can't find a magic address then MSI ain't gonna work */
-        if (find_ht_magic_addr(pdev, 0) == 0 &&
-            find_u4_magic_addr(pdev, 0) == 0) {
-                pr_debug("u3msi: no magic address found for %s\n",
-                         pci_name(pdev));
-                return -ENXIO;
-        }
-
-        return 0;
-}
-
 static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
 {
         struct msi_desc *entry;
@@ -146,6 +130,17 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
         u64 addr;
         int hwirq;
 
+        if (type == PCI_CAP_ID_MSIX)
+                pr_debug("u3msi: MSI-X untested, trying anyway.\n");
+
+        /* If we can't find a magic address then MSI ain't gonna work */
+        if (find_ht_magic_addr(pdev, 0) == 0 &&
+            find_u4_magic_addr(pdev, 0) == 0) {
+                pr_debug("u3msi: no magic address found for %s\n",
+                         pci_name(pdev));
+                return -ENXIO;
+        }
+
         list_for_each_entry(entry, &pdev->msi_list, list) {
                 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1);
                 if (hwirq < 0) {
@@ -202,7 +197,6 @@ int mpic_u3msi_init(struct mpic *mpic)
         WARN_ON(ppc_md.setup_msi_irqs);
         ppc_md.setup_msi_irqs = u3msi_setup_msi_irqs;
         ppc_md.teardown_msi_irqs = u3msi_teardown_msi_irqs;
-        ppc_md.msi_check_device = u3msi_msi_check_device;
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/ppc4xx_hsta_msi.c b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
index 11c888416f0a..a6a4dbda9078 100644
--- a/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
+++ b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
@@ -44,6 +44,12 @@ static int hsta_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
         int irq, hwirq;
         u64 addr;
 
+        /* We don't support MSI-X */
+        if (type == PCI_CAP_ID_MSIX) {
+                pr_debug("%s: MSI-X not supported.\n", __func__);
+                return -EINVAL;
+        }
+
         list_for_each_entry(entry, &dev->msi_list, list) {
                 irq = msi_bitmap_alloc_hwirqs(&ppc4xx_hsta_msi.bmp, 1);
                 if (irq < 0) {
@@ -117,17 +123,6 @@ static void hsta_teardown_msi_irqs(struct pci_dev *dev)
         }
 }
 
-static int hsta_msi_check_device(struct pci_dev *pdev, int nvec, int type)
-{
-        /* We don't support MSI-X */
-        if (type == PCI_CAP_ID_MSIX) {
-                pr_debug("%s: MSI-X not supported.\n", __func__);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
 static int hsta_msi_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
@@ -178,7 +173,6 @@ static int hsta_msi_probe(struct platform_device *pdev)
 
         ppc_md.setup_msi_irqs = hsta_setup_msi_irqs;
         ppc_md.teardown_msi_irqs = hsta_teardown_msi_irqs;
-        ppc_md.msi_check_device = hsta_msi_check_device;
         return 0;
 
 out2:
diff --git a/arch/powerpc/sysdev/ppc4xx_msi.c b/arch/powerpc/sysdev/ppc4xx_msi.c
index 43948da837a7..22b5200636e7 100644
--- a/arch/powerpc/sysdev/ppc4xx_msi.c
+++ b/arch/powerpc/sysdev/ppc4xx_msi.c
@@ -85,8 +85,12 @@ static int ppc4xx_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
         struct msi_desc *entry;
         struct ppc4xx_msi *msi_data = &ppc4xx_msi;
 
-        msi_data->msi_virqs = kmalloc((msi_irqs) * sizeof(int),
-                                            GFP_KERNEL);
+        dev_dbg(&dev->dev, "PCIE-MSI:%s called. vec %x type %d\n",
+                __func__, nvec, type);
+        if (type == PCI_CAP_ID_MSIX)
+                pr_debug("ppc4xx msi: MSI-X untested, trying anyway.\n");
+
+        msi_data->msi_virqs = kmalloc((msi_irqs) * sizeof(int), GFP_KERNEL);
         if (!msi_data->msi_virqs)
                 return -ENOMEM;
 
@@ -134,16 +138,6 @@ void ppc4xx_teardown_msi_irqs(struct pci_dev *dev)
         }
 }
 
-static int ppc4xx_msi_check_device(struct pci_dev *pdev, int nvec, int type)
-{
-        dev_dbg(&pdev->dev, "PCIE-MSI:%s called. vec %x type %d\n",
-                __func__, nvec, type);
-        if (type == PCI_CAP_ID_MSIX)
-                pr_debug("ppc4xx msi: MSI-X untested, trying anyway.\n");
-
-        return 0;
-}
-
 static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
                                  struct resource res, struct ppc4xx_msi *msi)
 {
@@ -259,7 +253,6 @@ static int ppc4xx_msi_probe(struct platform_device *dev)
 
         ppc_md.setup_msi_irqs = ppc4xx_setup_msi_irqs;
         ppc_md.teardown_msi_irqs = ppc4xx_teardown_msi_irqs;
-        ppc_md.msi_check_device = ppc4xx_msi_check_device;
         return err;
 
 error_out:
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index ab39ceb89ecf..05c78bb5f570 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -48,8 +48,6 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 
 config KEXEC
         def_bool y
-        select CRYPTO
-        select CRYPTO_SHA256
 
 config AUDIT_ARCH
         def_bool y
diff --git a/arch/s390/configs/default_defconfig b/arch/s390/configs/default_defconfig
index 3ca1894ade09..9d94fdd9f525 100644
--- a/arch/s390/configs/default_defconfig
+++ b/arch/s390/configs/default_defconfig
@@ -63,6 +63,7 @@ CONFIG_CRASH_DUMP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_HIBERNATION=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
diff --git a/arch/s390/configs/gcov_defconfig b/arch/s390/configs/gcov_defconfig
index 4830aa6e6f53..90f514baa37d 100644
--- a/arch/s390/configs/gcov_defconfig
+++ b/arch/s390/configs/gcov_defconfig
@@ -61,6 +61,7 @@ CONFIG_CRASH_DUMP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_HIBERNATION=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
diff --git a/arch/s390/configs/performance_defconfig b/arch/s390/configs/performance_defconfig
index 61db449bf309..13559d32af69 100644
--- a/arch/s390/configs/performance_defconfig
+++ b/arch/s390/configs/performance_defconfig
@@ -59,6 +59,7 @@ CONFIG_CRASH_DUMP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_HIBERNATION=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
diff --git a/arch/s390/configs/zfcpdump_defconfig b/arch/s390/configs/zfcpdump_defconfig
index 948e0e057a23..e376789f2d8d 100644
--- a/arch/s390/configs/zfcpdump_defconfig
+++ b/arch/s390/configs/zfcpdump_defconfig
@@ -23,6 +23,7 @@ CONFIG_CRASH_DUMP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SECCOMP is not set
 # CONFIG_IUCV is not set
+CONFIG_NET=y
 CONFIG_ATM=y
 CONFIG_ATM_LANE=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
diff --git a/arch/s390/defconfig b/arch/s390/defconfig
index 2e56498a40df..fab35a8efa4f 100644
--- a/arch/s390/defconfig
+++ b/arch/s390/defconfig
@@ -50,6 +50,7 @@ CONFIG_CMA=y
 CONFIG_CRASH_DUMP=y
 CONFIG_BINFMT_MISC=m
 CONFIG_HIBERNATION=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_NET_KEY=y
diff --git a/arch/s390/include/asm/Kbuild b/arch/s390/include/asm/Kbuild
index b3fea0722ff1..773f86676588 100644
--- a/arch/s390/include/asm/Kbuild
+++ b/arch/s390/include/asm/Kbuild
@@ -2,6 +2,7 @@
 
 generic-y += clkdev.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
 generic-y += scatterlist.h
diff --git a/arch/s390/include/asm/ipl.h b/arch/s390/include/asm/ipl.h
index 2fcccc0c997c..c81661e756a0 100644
--- a/arch/s390/include/asm/ipl.h
+++ b/arch/s390/include/asm/ipl.h
@@ -17,12 +17,12 @@
 #define IPL_PARM_BLK_FCP_LEN (sizeof(struct ipl_list_hdr) + \
                               sizeof(struct ipl_block_fcp))
 
-#define IPL_PARM_BLK0_FCP_LEN (sizeof(struct ipl_block_fcp) + 8)
+#define IPL_PARM_BLK0_FCP_LEN (sizeof(struct ipl_block_fcp) + 16)
 
 #define IPL_PARM_BLK_CCW_LEN (sizeof(struct ipl_list_hdr) + \
                               sizeof(struct ipl_block_ccw))
 
-#define IPL_PARM_BLK0_CCW_LEN (sizeof(struct ipl_block_ccw) + 8)
+#define IPL_PARM_BLK0_CCW_LEN (sizeof(struct ipl_block_ccw) + 16)
 
 #define IPL_MAX_SUPPORTED_VERSION (0)
 
@@ -38,10 +38,11 @@ struct ipl_list_hdr {
         u8  pbt;
         u8  flags;
         u16 reserved2;
+        u8  loadparm[8];
 } __attribute__((packed));
 
 struct ipl_block_fcp {
-        u8  reserved1[313-1];
+        u8  reserved1[305-1];
         u8  opt;
         u8  reserved2[3];
         u16 reserved3;
@@ -62,7 +63,6 @@ struct ipl_block_fcp {
                                  offsetof(struct ipl_block_fcp, scp_data)))
 
 struct ipl_block_ccw {
-        u8  load_parm[8];
         u8  reserved1[84];
         u8  reserved2[2];
         u16 devno;
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index 773bef7614d8..2175f911a73a 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -13,8 +13,11 @@
 
 #ifndef ASM_KVM_HOST_H
 #define ASM_KVM_HOST_H
+
+#include <linux/types.h>
 #include <linux/hrtimer.h>
 #include <linux/interrupt.h>
+#include <linux/kvm_types.h>
 #include <linux/kvm_host.h>
 #include <linux/kvm.h>
 #include <asm/debug.h>
@@ -154,7 +157,9 @@ struct kvm_s390_sie_block {
         __u8    armid;                  /* 0x00e3 */
         __u8    reservede4[4];          /* 0x00e4 */
         __u64   tecmc;                  /* 0x00e8 */
-        __u8    reservedf0[16];         /* 0x00f0 */
+        __u8    reservedf0[12];         /* 0x00f0 */
+#define CRYCB_FORMAT1 0x00000001
+        __u32   crycbd;                 /* 0x00fc */
         __u64   gcr[16];                /* 0x0100 */
         __u64   gbea;                   /* 0x0180 */
         __u8    reserved188[24];        /* 0x0188 */
@@ -187,6 +192,7 @@ struct kvm_vcpu_stat {
         u32 exit_stop_request;
         u32 exit_validity;
         u32 exit_instruction;
+        u32 halt_wakeup;
         u32 instruction_lctl;
         u32 instruction_lctlg;
         u32 instruction_stctl;
@@ -407,6 +413,15 @@ struct s390_io_adapter {
 #define MAX_S390_IO_ADAPTERS ((MAX_ISC + 1) * 8)
 #define MAX_S390_ADAPTER_MAPS 256
 
+struct kvm_s390_crypto {
+        struct kvm_s390_crypto_cb *crycb;
+        __u32 crycbd;
+};
+
+struct kvm_s390_crypto_cb {
+        __u8    reserved00[128];                /* 0x0000 */
+};
+
 struct kvm_arch{
         struct sca_block *sca;
         debug_info_t *dbf;
@@ -420,6 +435,7 @@ struct kvm_arch{
         struct s390_io_adapter *adapters[MAX_S390_IO_ADAPTERS];
         wait_queue_head_t ipte_wq;
         spinlock_t start_stop_lock;
+        struct kvm_s390_crypto crypto;
 };
 
 #define KVM_HVA_ERR_BAD         (-1UL)
@@ -431,8 +447,6 @@ static inline bool kvm_is_error_hva(unsigned long addr)
 }
 
 #define ASYNC_PF_PER_VCPU       64
-struct kvm_vcpu;
-struct kvm_async_pf;
 struct kvm_arch_async_pf {
         unsigned long pfault_token;
 };
@@ -450,4 +464,18 @@ void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
 
 extern int sie64a(struct kvm_s390_sie_block *, u64 *);
 extern char sie_exit;
+
+static inline void kvm_arch_hardware_disable(void) {}
+static inline void kvm_arch_check_processor_compat(void *rtn) {}
+static inline void kvm_arch_exit(void) {}
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
+static inline void kvm_arch_free_memslot(struct kvm *kvm,
+                struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
+static inline void kvm_arch_memslots_updated(struct kvm *kvm) {}
+static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
+static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
+                struct kvm_memory_slot *slot) {}
+
 #endif
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
index 9e18a61d3df3..d39a31c3cdf2 100644
--- a/arch/s390/include/asm/pgalloc.h
+++ b/arch/s390/include/asm/pgalloc.h
@@ -18,9 +18,9 @@
 unsigned long *crst_table_alloc(struct mm_struct *);
 void crst_table_free(struct mm_struct *, unsigned long *);
 
-unsigned long *page_table_alloc(struct mm_struct *, unsigned long);
+unsigned long *page_table_alloc(struct mm_struct *);
 void page_table_free(struct mm_struct *, unsigned long *);
-void page_table_free_rcu(struct mmu_gather *, unsigned long *);
+void page_table_free_rcu(struct mmu_gather *, unsigned long *, unsigned long);
 
 void page_table_reset_pgste(struct mm_struct *, unsigned long, unsigned long,
                             bool init_skey);
@@ -145,8 +145,8 @@ static inline void pmd_populate(struct mm_struct *mm,
 /*
  * page table entry allocation/free routines.
  */
-#define pte_alloc_one_kernel(mm, vmaddr) ((pte_t *) page_table_alloc(mm, vmaddr))
-#define pte_alloc_one(mm, vmaddr) ((pte_t *) page_table_alloc(mm, vmaddr))
+#define pte_alloc_one_kernel(mm, vmaddr) ((pte_t *) page_table_alloc(mm))
+#define pte_alloc_one(mm, vmaddr) ((pte_t *) page_table_alloc(mm))
 
 #define pte_free_kernel(mm, pte) page_table_free(mm, (unsigned long *) pte)
 #define pte_free(mm, pte) page_table_free(mm, (unsigned long *) pte)
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index b76317c1f3eb..b7054356cc98 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -30,6 +30,7 @@
 #include <linux/sched.h>
 #include <linux/mm_types.h>
 #include <linux/page-flags.h>
+#include <linux/radix-tree.h>
 #include <asm/bug.h>
 #include <asm/page.h>
 
@@ -789,82 +790,67 @@ static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry)
 
 /**
  * struct gmap_struct - guest address space
+ * @crst_list: list of all crst tables used in the guest address space
  * @mm: pointer to the parent mm_struct
+ * @guest_to_host: radix tree with guest to host address translation
+ * @host_to_guest: radix tree with pointer to segment table entries
+ * @guest_table_lock: spinlock to protect all entries in the guest page table
  * @table: pointer to the page directory
  * @asce: address space control element for gmap page table
- * @crst_list: list of all crst tables used in the guest address space
  * @pfault_enabled: defines if pfaults are applicable for the guest
  */
 struct gmap {
         struct list_head list;
+        struct list_head crst_list;
         struct mm_struct *mm;
+        struct radix_tree_root guest_to_host;
+        struct radix_tree_root host_to_guest;
+        spinlock_t guest_table_lock;
         unsigned long *table;
         unsigned long asce;
+        unsigned long asce_end;
         void *private;
-        struct list_head crst_list;
         bool pfault_enabled;
 };
 
 /**
- * struct gmap_rmap - reverse mapping for segment table entries
- * @gmap: pointer to the gmap_struct
- * @entry: pointer to a segment table entry
- * @vmaddr: virtual address in the guest address space
- */
-struct gmap_rmap {
-        struct list_head list;
-        struct gmap *gmap;
-        unsigned long *entry;
-        unsigned long vmaddr;
-};
-
-/**
- * struct gmap_pgtable - gmap information attached to a page table
- * @vmaddr: address of the 1MB segment in the process virtual memory
- * @mapper: list of segment table entries mapping a page table
- */
-struct gmap_pgtable {
-        unsigned long vmaddr;
-        struct list_head mapper;
-};
-
-/**
  * struct gmap_notifier - notify function block for page invalidation
  * @notifier_call: address of callback function
  */
 struct gmap_notifier {
         struct list_head list;
-        void (*notifier_call)(struct gmap *gmap, unsigned long address);
+        void (*notifier_call)(struct gmap *gmap, unsigned long gaddr);
 };
 
-struct gmap *gmap_alloc(struct mm_struct *mm);
+struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit);
 void gmap_free(struct gmap *gmap);
 void gmap_enable(struct gmap *gmap);
 void gmap_disable(struct gmap *gmap);
 int gmap_map_segment(struct gmap *gmap, unsigned long from,
                      unsigned long to, unsigned long len);
 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
-unsigned long __gmap_translate(unsigned long address, struct gmap *);
-unsigned long gmap_translate(unsigned long address, struct gmap *);
-unsigned long __gmap_fault(unsigned long address, struct gmap *);
-unsigned long gmap_fault(unsigned long address, struct gmap *);
-void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
-void __gmap_zap(unsigned long address, struct gmap *);
+unsigned long __gmap_translate(struct gmap *, unsigned long gaddr);
+unsigned long gmap_translate(struct gmap *, unsigned long gaddr);
+int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr);
+int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags);
+void gmap_discard(struct gmap *, unsigned long from, unsigned long to);
+void __gmap_zap(struct gmap *, unsigned long gaddr);
 bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *);
 
 
 void gmap_register_ipte_notifier(struct gmap_notifier *);
 void gmap_unregister_ipte_notifier(struct gmap_notifier *);
 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
-void gmap_do_ipte_notify(struct mm_struct *, pte_t *);
+void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
 
 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
+                                        unsigned long addr,
                                         pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
         if (pgste_val(pgste) & PGSTE_IN_BIT) {
                 pgste_val(pgste) &= ~PGSTE_IN_BIT;
-                gmap_do_ipte_notify(mm, ptep);
+                gmap_do_ipte_notify(mm, addr, ptep);
         }
 #endif
         return pgste;
@@ -1110,7 +1096,7 @@ static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
         pgste_val(pgste) &= ~PGSTE_UC_BIT;
         pte = *ptep;
         if (dirty && (pte_val(pte) & _PAGE_PRESENT)) {
-                pgste = pgste_ipte_notify(mm, ptep, pgste);
+                pgste = pgste_ipte_notify(mm, addr, ptep, pgste);
                 __ptep_ipte(addr, ptep);
                 if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE))
                         pte_val(pte) |= _PAGE_PROTECT;
@@ -1127,20 +1113,21 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
                                             unsigned long addr, pte_t *ptep)
 {
         pgste_t pgste;
-        pte_t pte;
+        pte_t pte, oldpte;
         int young;
 
         if (mm_has_pgste(vma->vm_mm)) {
                 pgste = pgste_get_lock(ptep);
-                pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
+                pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste);
         }
 
-        pte = *ptep;
+        oldpte = pte = *ptep;
         ptep_flush_direct(vma->vm_mm, addr, ptep);
         young = pte_young(pte);
         pte = pte_mkold(pte);
 
         if (mm_has_pgste(vma->vm_mm)) {
+                pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm);
                 pgste = pgste_set_pte(ptep, pgste, pte);
                 pgste_set_unlock(ptep, pgste);
         } else
@@ -1178,7 +1165,7 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 
         if (mm_has_pgste(mm)) {
                 pgste = pgste_get_lock(ptep);
-                pgste = pgste_ipte_notify(mm, ptep, pgste);
+                pgste = pgste_ipte_notify(mm, address, ptep, pgste);
         }
 
         pte = *ptep;
@@ -1202,7 +1189,7 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
 
         if (mm_has_pgste(mm)) {
                 pgste = pgste_get_lock(ptep);
-                pgste_ipte_notify(mm, ptep, pgste);
+                pgste_ipte_notify(mm, address, ptep, pgste);
         }
 
         pte = *ptep;
@@ -1239,7 +1226,7 @@ static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
 
         if (mm_has_pgste(vma->vm_mm)) {
                 pgste = pgste_get_lock(ptep);
-                pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
+                pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
         }
 
         pte = *ptep;
@@ -1273,7 +1260,7 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
 
         if (!full && mm_has_pgste(mm)) {
                 pgste = pgste_get_lock(ptep);
-                pgste = pgste_ipte_notify(mm, ptep, pgste);
+                pgste = pgste_ipte_notify(mm, address, ptep, pgste);
         }
 
         pte = *ptep;
@@ -1298,7 +1285,7 @@ static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
         if (pte_write(pte)) {
                 if (mm_has_pgste(mm)) {
                         pgste = pgste_get_lock(ptep);
-                        pgste = pgste_ipte_notify(mm, ptep, pgste);
+                        pgste = pgste_ipte_notify(mm, address, ptep, pgste);
                 }
 
                 ptep_flush_lazy(mm, address, ptep);
@@ -1324,12 +1311,13 @@ static inline int ptep_set_access_flags(struct vm_area_struct *vma,
                 return 0;
         if (mm_has_pgste(vma->vm_mm)) {
                 pgste = pgste_get_lock(ptep);
-                pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
+                pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
         }
 
         ptep_flush_direct(vma->vm_mm, address, ptep);
 
         if (mm_has_pgste(vma->vm_mm)) {
+                pgste_set_key(ptep, pgste, entry, vma->vm_mm);
                 pgste = pgste_set_pte(ptep, pgste, entry);
                 pgste_set_unlock(ptep, pgste);
         } else
diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h
index a25f09fbaf36..572c59949004 100644
--- a/arch/s390/include/asm/tlb.h
+++ b/arch/s390/include/asm/tlb.h
@@ -105,7 +105,7 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
                                 unsigned long address)
 {
-        page_table_free_rcu(tlb, (unsigned long *) pte);
+        page_table_free_rcu(tlb, (unsigned long *) pte, address);
 }
 
 /*
diff --git a/arch/s390/include/uapi/asm/kvm.h b/arch/s390/include/uapi/asm/kvm.h
index 0fc26430a1e5..48eda3ab4944 100644
--- a/arch/s390/include/uapi/asm/kvm.h
+++ b/arch/s390/include/uapi/asm/kvm.h
@@ -111,12 +111,22 @@ struct kvm_guest_debug_arch {
 #define KVM_SYNC_GPRS   (1UL << 1)
 #define KVM_SYNC_ACRS   (1UL << 2)
 #define KVM_SYNC_CRS    (1UL << 3)
+#define KVM_SYNC_ARCH0  (1UL << 4)
+#define KVM_SYNC_PFAULT (1UL << 5)
 /* definition of registers in kvm_run */
 struct kvm_sync_regs {
         __u64 prefix;   /* prefix register */
         __u64 gprs[16]; /* general purpose registers */
         __u32 acrs[16]; /* access registers */
         __u64 crs[16];  /* control registers */
+        __u64 todpr;    /* tod programmable register [ARCH0] */
+        __u64 cputm;    /* cpu timer [ARCH0] */
+        __u64 ckc;      /* clock comparator [ARCH0] */
+        __u64 pp;       /* program parameter [ARCH0] */
+        __u64 gbea;     /* guest breaking-event address [ARCH0] */
+        __u64 pft;      /* pfault token [PFAULT] */
+        __u64 pfs;      /* pfault select [PFAULT] */
+        __u64 pfc;      /* pfault compare [PFAULT] */
 };
 
 #define KVM_REG_S390_TODPR      (KVM_REG_S390 | KVM_REG_SIZE_U32 | 0x1)
diff --git a/arch/s390/include/uapi/asm/unistd.h b/arch/s390/include/uapi/asm/unistd.h
index 3802d2d3a18d..940ac49198db 100644
--- a/arch/s390/include/uapi/asm/unistd.h
+++ b/arch/s390/include/uapi/asm/unistd.h
@@ -283,7 +283,10 @@
 #define __NR_sched_setattr      345
 #define __NR_sched_getattr      346
 #define __NR_renameat2          347
-#define NR_syscalls 348
+#define __NR_seccomp            348
+#define __NR_getrandom          349
+#define __NR_memfd_create       350
+#define NR_syscalls 351
 
 /* 
  * There are some system calls that are not present on 64 bit, some
diff --git a/arch/s390/kernel/compat_wrapper.c b/arch/s390/kernel/compat_wrapper.c
index 45cdb37aa6f8..faf6caa510dc 100644
--- a/arch/s390/kernel/compat_wrapper.c
+++ b/arch/s390/kernel/compat_wrapper.c
@@ -214,3 +214,6 @@ COMPAT_SYSCALL_WRAP3(finit_module, int, fd, const char __user *, uargs, int, fla
 COMPAT_SYSCALL_WRAP3(sched_setattr, pid_t, pid, struct sched_attr __user *, attr, unsigned int, flags);
 COMPAT_SYSCALL_WRAP4(sched_getattr, pid_t, pid, struct sched_attr __user *, attr, unsigned int, size, unsigned int, flags);
 COMPAT_SYSCALL_WRAP5(renameat2, int, olddfd, const char __user *, oldname, int, newdfd, const char __user *, newname, unsigned int, flags);
+COMPAT_SYSCALL_WRAP3(seccomp, unsigned int, op, unsigned int, flags, const char __user *, uargs)
+COMPAT_SYSCALL_WRAP3(getrandom, char __user *, buf, size_t, count, unsigned int, flags)
+COMPAT_SYSCALL_WRAP2(memfd_create, const char __user *, uname, unsigned int, flags)
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index 633ca7504536..39badb9ca0b3 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -455,22 +455,6 @@ DEFINE_IPL_ATTR_RO(ipl_fcp, bootprog, "%lld\n", (unsigned long long)
 DEFINE_IPL_ATTR_RO(ipl_fcp, br_lba, "%lld\n", (unsigned long long)
                    IPL_PARMBLOCK_START->ipl_info.fcp.br_lba);
 
-static struct attribute *ipl_fcp_attrs[] = {
-        &sys_ipl_type_attr.attr,
-        &sys_ipl_device_attr.attr,
-        &sys_ipl_fcp_wwpn_attr.attr,
-        &sys_ipl_fcp_lun_attr.attr,
-        &sys_ipl_fcp_bootprog_attr.attr,
-        &sys_ipl_fcp_br_lba_attr.attr,
-        NULL,
-};
-
-static struct attribute_group ipl_fcp_attr_group = {
-        .attrs = ipl_fcp_attrs,
-};
-
-/* CCW ipl device attributes */
-
 static ssize_t ipl_ccw_loadparm_show(struct kobject *kobj,
                                      struct kobj_attribute *attr, char *page)
 {
@@ -487,6 +471,23 @@ static ssize_t ipl_ccw_loadparm_show(struct kobject *kobj,
 static struct kobj_attribute sys_ipl_ccw_loadparm_attr =
         __ATTR(loadparm, 0444, ipl_ccw_loadparm_show, NULL);
 
+static struct attribute *ipl_fcp_attrs[] = {
+        &sys_ipl_type_attr.attr,
+        &sys_ipl_device_attr.attr,
+        &sys_ipl_fcp_wwpn_attr.attr,
+        &sys_ipl_fcp_lun_attr.attr,
+        &sys_ipl_fcp_bootprog_attr.attr,
+        &sys_ipl_fcp_br_lba_attr.attr,
+        &sys_ipl_ccw_loadparm_attr.attr,
+        NULL,
+};
+
+static struct attribute_group ipl_fcp_attr_group = {
+        .attrs = ipl_fcp_attrs,
+};
+
+/* CCW ipl device attributes */
+
 static struct attribute *ipl_ccw_attrs_vm[] = {
         &sys_ipl_type_attr.attr,
         &sys_ipl_device_attr.attr,
@@ -765,28 +766,10 @@ DEFINE_IPL_ATTR_RW(reipl_fcp, br_lba, "%lld\n", "%lld\n",
 DEFINE_IPL_ATTR_RW(reipl_fcp, device, "0.0.%04llx\n", "0.0.%llx\n",
                    reipl_block_fcp->ipl_info.fcp.devno);
 
-static struct attribute *reipl_fcp_attrs[] = {
-        &sys_reipl_fcp_device_attr.attr,
-        &sys_reipl_fcp_wwpn_attr.attr,
-        &sys_reipl_fcp_lun_attr.attr,
-        &sys_reipl_fcp_bootprog_attr.attr,
-        &sys_reipl_fcp_br_lba_attr.attr,
-        NULL,
-};
-
-static struct attribute_group reipl_fcp_attr_group = {
-        .attrs = reipl_fcp_attrs,
-};
-
-/* CCW reipl device attributes */
-
-DEFINE_IPL_ATTR_RW(reipl_ccw, device, "0.0.%04llx\n", "0.0.%llx\n",
-        reipl_block_ccw->ipl_info.ccw.devno);
-
 static void reipl_get_ascii_loadparm(char *loadparm,
                                      struct ipl_parameter_block *ibp)
 {
-        memcpy(loadparm, ibp->ipl_info.ccw.load_parm, LOADPARM_LEN);
+        memcpy(loadparm, ibp->hdr.loadparm, LOADPARM_LEN);
         EBCASC(loadparm, LOADPARM_LEN);
         loadparm[LOADPARM_LEN] = 0;
         strim(loadparm);
@@ -821,13 +804,50 @@ static ssize_t reipl_generic_loadparm_store(struct ipl_parameter_block *ipb,
                 return -EINVAL;
         }
         /* initialize loadparm with blanks */
-        memset(ipb->ipl_info.ccw.load_parm, ' ', LOADPARM_LEN);
+        memset(ipb->hdr.loadparm, ' ', LOADPARM_LEN);
         /* copy and convert to ebcdic */
-        memcpy(ipb->ipl_info.ccw.load_parm, buf, lp_len);
-        ASCEBC(ipb->ipl_info.ccw.load_parm, LOADPARM_LEN);
+        memcpy(ipb->hdr.loadparm, buf, lp_len);
+        ASCEBC(ipb->hdr.loadparm, LOADPARM_LEN);
         return len;
 }
 
+/* FCP wrapper */
+static ssize_t reipl_fcp_loadparm_show(struct kobject *kobj,
+                                       struct kobj_attribute *attr, char *page)
+{
+        return reipl_generic_loadparm_show(reipl_block_fcp, page);
+}
+
+static ssize_t reipl_fcp_loadparm_store(struct kobject *kobj,
+                                        struct kobj_attribute *attr,
+                                        const char *buf, size_t len)
+{
+        return reipl_generic_loadparm_store(reipl_block_fcp, buf, len);
+}
+
+static struct kobj_attribute sys_reipl_fcp_loadparm_attr =
+        __ATTR(loadparm, S_IRUGO | S_IWUSR, reipl_fcp_loadparm_show,
+                                            reipl_fcp_loadparm_store);
+
+static struct attribute *reipl_fcp_attrs[] = {
+        &sys_reipl_fcp_device_attr.attr,
+        &sys_reipl_fcp_wwpn_attr.attr,
+        &sys_reipl_fcp_lun_attr.attr,
+        &sys_reipl_fcp_bootprog_attr.attr,
+        &sys_reipl_fcp_br_lba_attr.attr,
+        &sys_reipl_fcp_loadparm_attr.attr,
+        NULL,
+};
+
+static struct attribute_group reipl_fcp_attr_group = {
+        .attrs = reipl_fcp_attrs,
+};
+
+/* CCW reipl device attributes */
+
+DEFINE_IPL_ATTR_RW(reipl_ccw, device, "0.0.%04llx\n", "0.0.%llx\n",
+        reipl_block_ccw->ipl_info.ccw.devno);
+
 /* NSS wrapper */
 static ssize_t reipl_nss_loadparm_show(struct kobject *kobj,
                                        struct kobj_attribute *attr, char *page)
@@ -1125,11 +1145,10 @@ static void reipl_block_ccw_fill_parms(struct ipl_parameter_block *ipb)
         /* LOADPARM */
         /* check if read scp info worked and set loadparm */
         if (sclp_ipl_info.is_valid)
-                memcpy(ipb->ipl_info.ccw.load_parm,
-                                &sclp_ipl_info.loadparm, LOADPARM_LEN);
+                memcpy(ipb->hdr.loadparm, &sclp_ipl_info.loadparm, LOADPARM_LEN);
         else
                 /* read scp info failed: set empty loadparm (EBCDIC blanks) */
-                memset(ipb->ipl_info.ccw.load_parm, 0x40, LOADPARM_LEN);
+                memset(ipb->hdr.loadparm, 0x40, LOADPARM_LEN);
         ipb->hdr.flags = DIAG308_FLAGS_LP_VALID;
 
         /* VM PARM */
@@ -1251,9 +1270,16 @@ static int __init reipl_fcp_init(void)
                 return rc;
         }
 
-        if (ipl_info.type == IPL_TYPE_FCP)
+        if (ipl_info.type == IPL_TYPE_FCP) {
                 memcpy(reipl_block_fcp, IPL_PARMBLOCK_START, PAGE_SIZE);
-        else {
+                /*
+                 * Fix loadparm: There are systems where the (SCSI) LOADPARM
+                 * is invalid in the SCSI IPL parameter block, so take it
+                 * always from sclp_ipl_info.
+                 */
+                memcpy(reipl_block_fcp->hdr.loadparm, sclp_ipl_info.loadparm,
+                       LOADPARM_LEN);
+        } else {
                 reipl_block_fcp->hdr.len = IPL_PARM_BLK_FCP_LEN;
                 reipl_block_fcp->hdr.version = IPL_PARM_BLOCK_VERSION;
                 reipl_block_fcp->hdr.blk0_len = IPL_PARM_BLK0_FCP_LEN;
@@ -1864,7 +1890,23 @@ static void __init shutdown_actions_init(void)
 
 static int __init s390_ipl_init(void)
 {
+        char str[8] = {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
+
         sclp_get_ipl_info(&sclp_ipl_info);
+        /*
+         * Fix loadparm: There are systems where the (SCSI) LOADPARM
+         * returned by read SCP info is invalid (contains EBCDIC blanks)
+         * when the system has been booted via diag308. In that case we use
+         * the value from diag308, if available.
+         *
+         * There are also systems where diag308 store does not work in
+         * case the system is booted from HMC. Fortunately in this case
+         * READ SCP info provides the correct value.
+         */
+        if (memcmp(sclp_ipl_info.loadparm, str, sizeof(str)) == 0 &&
+            diag308_set_works)
+                memcpy(sclp_ipl_info.loadparm, ipl_block.hdr.loadparm,
+                       LOADPARM_LEN);
         shutdown_actions_init();
         shutdown_triggers_init();
         return 0;
@@ -2060,6 +2102,13 @@ void s390_reset_system(void (*func)(void *), void *data)
         S390_lowcore.program_new_psw.addr =
                 PSW_ADDR_AMODE | (unsigned long) s390_base_pgm_handler;
 
+        /*
+         * Clear subchannel ID and number to signal new kernel that no CCW or
+         * SCSI IPL has been done (for kexec and kdump)
+         */
+        S390_lowcore.subchannel_id = 0;
+        S390_lowcore.subchannel_nr = 0;
+
         /* Store status at absolute zero */
         store_status();
 
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index ae1d5be7dd88..82bc113e8c1d 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -24,6 +24,7 @@
 #include <linux/stddef.h>
 #include <linux/unistd.h>
 #include <linux/ptrace.h>
+#include <linux/random.h>
 #include <linux/user.h>
 #include <linux/tty.h>
 #include <linux/ioport.h>
@@ -61,6 +62,7 @@
 #include <asm/diag.h>
 #include <asm/os_info.h>
 #include <asm/sclp.h>
+#include <asm/sysinfo.h>
 #include "entry.h"
 
 /*
@@ -766,6 +768,7 @@ static void __init setup_hwcaps(void)
 #endif
 
         get_cpu_id(&cpu_id);
+        add_device_randomness(&cpu_id, sizeof(cpu_id));
         switch (cpu_id.machine) {
         case 0x9672:
 #if !defined(CONFIG_64BIT)
@@ -804,6 +807,19 @@ static void __init setup_hwcaps(void)
 }
 
 /*
+ * Add system information as device randomness
+ */
+static void __init setup_randomness(void)
+{
+        struct sysinfo_3_2_2 *vmms;
+
+        vmms = (struct sysinfo_3_2_2 *) alloc_page(GFP_KERNEL);
+        if (vmms && stsi(vmms, 3, 2, 2) == 0 && vmms->count)
+                add_device_randomness(&vmms, vmms->count);
+        free_page((unsigned long) vmms);
+}
+
+/*
  * Setup function called from init/main.c just after the banner
  * was printed.
  */
@@ -901,6 +917,9 @@ void __init setup_arch(char **cmdline_p)
 
         /* Setup zfcpdump support */
         setup_zfcpdump();
+
+        /* Add system specific data to the random pool */
+        setup_randomness();
 }
 
 #ifdef CONFIG_32BIT
diff --git a/arch/s390/kernel/suspend.c b/arch/s390/kernel/suspend.c
index a7a7537ce1e7..1c4c5accd220 100644
--- a/arch/s390/kernel/suspend.c
+++ b/arch/s390/kernel/suspend.c
@@ -13,14 +13,10 @@
 #include <asm/ipl.h>
 #include <asm/cio.h>
 #include <asm/pci.h>
+#include <asm/sections.h>
 #include "entry.h"
 
 /*
- * References to section boundaries
- */
-extern const void __nosave_begin, __nosave_end;
-
-/*
  * The restore of the saved pages in an hibernation image will set
  * the change and referenced bits in the storage key for each page.
  * Overindication of the referenced bits after an hibernation cycle
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index fe5cdf29a001..6fe886ac2db5 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -356,3 +356,6 @@ SYSCALL(sys_finit_module,sys_finit_module,compat_sys_finit_module)
 SYSCALL(sys_sched_setattr,sys_sched_setattr,compat_sys_sched_setattr) /* 345 */
 SYSCALL(sys_sched_getattr,sys_sched_getattr,compat_sys_sched_getattr)
 SYSCALL(sys_renameat2,sys_renameat2,compat_sys_renameat2)
+SYSCALL(sys_seccomp,sys_seccomp,compat_sys_seccomp)
+SYSCALL(sys_getrandom,sys_getrandom,compat_sys_getrandom)
+SYSCALL(sys_memfd_create,sys_memfd_create,compat_sys_memfd_create) /* 350 */
diff --git a/arch/s390/kernel/vdso32/clock_gettime.S b/arch/s390/kernel/vdso32/clock_gettime.S
index 65fc3979c2f1..7cf18f8d4cb4 100644
--- a/arch/s390/kernel/vdso32/clock_gettime.S
+++ b/arch/s390/kernel/vdso32/clock_gettime.S
@@ -22,13 +22,11 @@ __kernel_clock_gettime:
         basr    %r5,0
 0:      al      %r5,21f-0b(%r5)                 /* get &_vdso_data */
         chi     %r2,__CLOCK_REALTIME
-        je      10f
+        je      11f
         chi     %r2,__CLOCK_MONOTONIC
         jne     19f
 
         /* CLOCK_MONOTONIC */
-        ltr     %r3,%r3
-        jz      9f                              /* tp == NULL */
 1:      l       %r4,__VDSO_UPD_COUNT+4(%r5)     /* load update counter */
         tml     %r4,0x0001                      /* pending update ? loop */
         jnz     1b
@@ -67,12 +65,10 @@ __kernel_clock_gettime:
         j       6b
 8:      st      %r2,0(%r3)                      /* store tp->tv_sec */
         st      %r1,4(%r3)                      /* store tp->tv_nsec */
-9:      lhi     %r2,0
+        lhi     %r2,0
         br      %r14
 
         /* CLOCK_REALTIME */
-10:     ltr     %r3,%r3                         /* tp == NULL */
-        jz      18f
 11:     l       %r4,__VDSO_UPD_COUNT+4(%r5)     /* load update counter */
         tml     %r4,0x0001                      /* pending update ? loop */
         jnz     11b
@@ -111,7 +107,7 @@ __kernel_clock_gettime:
         j       15b
 17:     st      %r2,0(%r3)                      /* store tp->tv_sec */
         st      %r1,4(%r3)                      /* store tp->tv_nsec */
-18:     lhi     %r2,0
+        lhi     %r2,0
         br      %r14
 
         /* Fallback to system call */
diff --git a/arch/s390/kernel/vdso64/clock_gettime.S b/arch/s390/kernel/vdso64/clock_gettime.S
index 91940ed33a4a..3f34e09db5f4 100644
--- a/arch/s390/kernel/vdso64/clock_gettime.S
+++ b/arch/s390/kernel/vdso64/clock_gettime.S
@@ -21,7 +21,7 @@ __kernel_clock_gettime:
         .cfi_startproc
         larl    %r5,_vdso_data
         cghi    %r2,__CLOCK_REALTIME
-        je      4f
+        je      5f
         cghi    %r2,__CLOCK_THREAD_CPUTIME_ID
         je      9f
         cghi    %r2,-2          /* Per-thread CPUCLOCK with PID=0, VIRT=1 */
@@ -30,8 +30,6 @@ __kernel_clock_gettime:
         jne     12f
 
         /* CLOCK_MONOTONIC */
-        ltgr    %r3,%r3
-        jz      3f                              /* tp == NULL */
 0:      lg      %r4,__VDSO_UPD_COUNT(%r5)       /* load update counter */
         tmll    %r4,0x0001                      /* pending update ? loop */
         jnz     0b
@@ -53,12 +51,10 @@ __kernel_clock_gettime:
         j       1b
 2:      stg     %r0,0(%r3)                      /* store tp->tv_sec */
         stg     %r1,8(%r3)                      /* store tp->tv_nsec */
-3:      lghi    %r2,0
+        lghi    %r2,0
         br      %r14
 
         /* CLOCK_REALTIME */
-4:      ltr     %r3,%r3                         /* tp == NULL */
-        jz      8f
 5:      lg      %r4,__VDSO_UPD_COUNT(%r5)       /* load update counter */
         tmll    %r4,0x0001                      /* pending update ? loop */
         jnz     5b
@@ -80,7 +76,7 @@ __kernel_clock_gettime:
         j       6b
 7:      stg     %r0,0(%r3)                      /* store tp->tv_sec */
         stg     %r1,8(%r3)                      /* store tp->tv_nsec */
-8:      lghi    %r2,0
+        lghi    %r2,0
         br      %r14
 
         /* CLOCK_THREAD_CPUTIME_ID for this thread */
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index 59bd8f991b98..9254afff250c 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -28,22 +28,32 @@ static int diag_release_pages(struct kvm_vcpu *vcpu)
         start = vcpu->run->s.regs.gprs[(vcpu->arch.sie_block->ipa & 0xf0) >> 4];
         end = vcpu->run->s.regs.gprs[vcpu->arch.sie_block->ipa & 0xf] + 4096;
 
-        if (start & ~PAGE_MASK || end & ~PAGE_MASK || start > end
+        if (start & ~PAGE_MASK || end & ~PAGE_MASK || start >= end
             || start < 2 * PAGE_SIZE)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
         VCPU_EVENT(vcpu, 5, "diag release pages %lX %lX", start, end);
         vcpu->stat.diagnose_10++;
 
-        /* we checked for start > end above */
-        if (end < prefix || start >= prefix + 2 * PAGE_SIZE) {
-                gmap_discard(start, end, vcpu->arch.gmap);
+        /*
+         * We checked for start >= end above, so lets check for the
+         * fast path (no prefix swap page involved)
+         */
+        if (end <= prefix || start >= prefix + 2 * PAGE_SIZE) {
+                gmap_discard(vcpu->arch.gmap, start, end);
         } else {
-                if (start < prefix)
-                        gmap_discard(start, prefix, vcpu->arch.gmap);
-                if (end >= prefix)
-                        gmap_discard(prefix + 2 * PAGE_SIZE,
-                                     end, vcpu->arch.gmap);
+                /*
+                 * This is slow path.  gmap_discard will check for start
+                 * so lets split this into before prefix, prefix, after
+                 * prefix and let gmap_discard make some of these calls
+                 * NOPs.
+                 */
+                gmap_discard(vcpu->arch.gmap, start, prefix);
+                if (start <= prefix)
+                        gmap_discard(vcpu->arch.gmap, 0, 4096);
+                if (end > prefix + 4096)
+                        gmap_discard(vcpu->arch.gmap, 4096, 8192);
+                gmap_discard(vcpu->arch.gmap, prefix + 2 * PAGE_SIZE, end);
         }
         return 0;
 }
diff --git a/arch/s390/kvm/gaccess.c b/arch/s390/kvm/gaccess.c
index 4653ac6e182b..0f961a1c64b3 100644
--- a/arch/s390/kvm/gaccess.c
+++ b/arch/s390/kvm/gaccess.c
@@ -254,8 +254,7 @@ static void ipte_unlock_simple(struct kvm_vcpu *vcpu)
                 new = old = ACCESS_ONCE(*ic);
                 new.k = 0;
         } while (cmpxchg(&ic->val, old.val, new.val) != old.val);
-        if (!ipte_lock_count)
-                wake_up(&vcpu->kvm->arch.ipte_wq);
+        wake_up(&vcpu->kvm->arch.ipte_wq);
 out:
         mutex_unlock(&ipte_mutex);
 }
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index f4c819bfc193..a39838457f01 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -26,8 +26,9 @@
 #define IOINT_SSID_MASK 0x00030000
 #define IOINT_CSSID_MASK 0x03fc0000
 #define IOINT_AI_MASK 0x04000000
+#define PFAULT_INIT 0x0600
 
-static void deliver_ckc_interrupt(struct kvm_vcpu *vcpu);
+static int __must_check deliver_ckc_interrupt(struct kvm_vcpu *vcpu);
 
 static int is_ioint(u64 type)
 {
@@ -76,7 +77,7 @@ static u64 int_word_to_isc_bits(u32 int_word)
         return (0x80 >> isc) << 24;
 }
 
-static int __interrupt_is_deliverable(struct kvm_vcpu *vcpu,
+static int __must_check __interrupt_is_deliverable(struct kvm_vcpu *vcpu,
                                       struct kvm_s390_interrupt_info *inti)
 {
         switch (inti->type) {
@@ -85,6 +86,7 @@ static int __interrupt_is_deliverable(struct kvm_vcpu *vcpu,
                         return 0;
                 if (vcpu->arch.sie_block->gcr[0] & 0x2000ul)
                         return 1;
+                return 0;
         case KVM_S390_INT_EMERGENCY:
                 if (psw_extint_disabled(vcpu))
                         return 0;
@@ -205,11 +207,30 @@ static void __set_intercept_indicator(struct kvm_vcpu *vcpu,
         }
 }
 
-static int __deliver_prog_irq(struct kvm_vcpu *vcpu,
-                              struct kvm_s390_pgm_info *pgm_info)
+static u16 get_ilc(struct kvm_vcpu *vcpu)
 {
         const unsigned short table[] = { 2, 4, 4, 6 };
+
+        switch (vcpu->arch.sie_block->icptcode) {
+        case ICPT_INST:
+        case ICPT_INSTPROGI:
+        case ICPT_OPEREXC:
+        case ICPT_PARTEXEC:
+        case ICPT_IOINST:
+                /* last instruction only stored for these icptcodes */
+                return table[vcpu->arch.sie_block->ipa >> 14];
+        case ICPT_PROGI:
+                return vcpu->arch.sie_block->pgmilc;
+        default:
+                return 0;
+        }
+}
+
+static int __must_check __deliver_prog_irq(struct kvm_vcpu *vcpu,
+                              struct kvm_s390_pgm_info *pgm_info)
+{
         int rc = 0;
+        u16 ilc = get_ilc(vcpu);
 
         switch (pgm_info->code & ~PGM_PER) {
         case PGM_AFX_TRANSLATION:
@@ -276,25 +297,7 @@ static int __deliver_prog_irq(struct kvm_vcpu *vcpu,
                                    (u8 *) __LC_PER_ACCESS_ID);
         }
 
-        switch (vcpu->arch.sie_block->icptcode) {
-        case ICPT_INST:
-        case ICPT_INSTPROGI:
-        case ICPT_OPEREXC:
-        case ICPT_PARTEXEC:
-        case ICPT_IOINST:
-                /* last instruction only stored for these icptcodes */
-                rc |= put_guest_lc(vcpu, table[vcpu->arch.sie_block->ipa >> 14],
-                                   (u16 *) __LC_PGM_ILC);
-                break;
-        case ICPT_PROGI:
-                rc |= put_guest_lc(vcpu, vcpu->arch.sie_block->pgmilc,
-                                   (u16 *) __LC_PGM_ILC);
-                break;
-        default:
-                rc |= put_guest_lc(vcpu, 0,
-                                   (u16 *) __LC_PGM_ILC);
-        }
-
+        rc |= put_guest_lc(vcpu, ilc, (u16 *) __LC_PGM_ILC);
         rc |= put_guest_lc(vcpu, pgm_info->code,
                            (u16 *)__LC_PGM_INT_CODE);
         rc |= write_guest_lc(vcpu, __LC_PGM_OLD_PSW,
@@ -305,7 +308,7 @@ static int __deliver_prog_irq(struct kvm_vcpu *vcpu,
         return rc;
 }
 
-static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
+static int __must_check __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                                    struct kvm_s390_interrupt_info *inti)
 {
         const unsigned short table[] = { 2, 4, 4, 6 };
@@ -343,7 +346,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
         case KVM_S390_INT_CLOCK_COMP:
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  inti->ext.ext_params, 0);
-                deliver_ckc_interrupt(vcpu);
+                rc = deliver_ckc_interrupt(vcpu);
                 break;
         case KVM_S390_INT_CPU_TIMER:
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
@@ -376,8 +379,9 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
         case KVM_S390_INT_PFAULT_INIT:
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0,
                                                  inti->ext.ext_params2);
-                rc  = put_guest_lc(vcpu, 0x2603, (u16 *) __LC_EXT_INT_CODE);
-                rc |= put_guest_lc(vcpu, 0x0600, (u16 *) __LC_EXT_CPU_ADDR);
+                rc  = put_guest_lc(vcpu, EXT_IRQ_CP_SERVICE,
+                                   (u16 *) __LC_EXT_INT_CODE);
+                rc |= put_guest_lc(vcpu, PFAULT_INIT, (u16 *) __LC_EXT_CPU_ADDR);
                 rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW,
                                      &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
                 rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW,
@@ -501,14 +505,11 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
         default:
                 BUG();
         }
-        if (rc) {
-                printk("kvm: The guest lowcore is not mapped during interrupt "
-                       "delivery, killing userspace\n");
-                do_exit(SIGKILL);
-        }
+
+        return rc;
 }
 
-static void deliver_ckc_interrupt(struct kvm_vcpu *vcpu)
+static int __must_check deliver_ckc_interrupt(struct kvm_vcpu *vcpu)
 {
         int rc;
 
@@ -518,11 +519,7 @@ static void deliver_ckc_interrupt(struct kvm_vcpu *vcpu)
         rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW,
                             &vcpu->arch.sie_block->gpsw,
                             sizeof(psw_t));
-        if (rc) {
-                printk("kvm: The guest lowcore is not mapped during interrupt "
-                        "delivery, killing userspace\n");
-                do_exit(SIGKILL);
-        }
+        return rc;
 }
 
 /* Check whether SIGP interpretation facility has an external call pending */
@@ -629,6 +626,7 @@ void kvm_s390_vcpu_wakeup(struct kvm_vcpu *vcpu)
                  */
                 vcpu->preempted = true;
                 wake_up_interruptible(&vcpu->wq);
+                vcpu->stat.halt_wakeup++;
         }
 }
 
@@ -661,12 +659,13 @@ void kvm_s390_clear_local_irqs(struct kvm_vcpu *vcpu)
                           &vcpu->kvm->arch.sca->cpu[vcpu->vcpu_id].ctrl);
 }
 
-void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
+int __must_check kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
 {
         struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
         struct kvm_s390_float_interrupt *fi = vcpu->arch.local_int.float_int;
         struct kvm_s390_interrupt_info  *n, *inti = NULL;
         int deliver;
+        int rc = 0;
 
         __reset_intercept_indicators(vcpu);
         if (atomic_read(&li->active)) {
@@ -685,16 +684,16 @@ void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
                                 atomic_set(&li->active, 0);
                         spin_unlock(&li->lock);
                         if (deliver) {
-                                __do_deliver_interrupt(vcpu, inti);
+                                rc = __do_deliver_interrupt(vcpu, inti);
                                 kfree(inti);
                         }
-                } while (deliver);
+                } while (!rc && deliver);
         }
 
-        if (kvm_cpu_has_pending_timer(vcpu))
-                deliver_ckc_interrupt(vcpu);
+        if (!rc && kvm_cpu_has_pending_timer(vcpu))
+                rc = deliver_ckc_interrupt(vcpu);
 
-        if (atomic_read(&fi->active)) {
+        if (!rc && atomic_read(&fi->active)) {
                 do {
                         deliver = 0;
                         spin_lock(&fi->lock);
@@ -711,67 +710,13 @@ void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
                                 atomic_set(&fi->active, 0);
                         spin_unlock(&fi->lock);
                         if (deliver) {
-                                __do_deliver_interrupt(vcpu, inti);
-                                kfree(inti);
-                        }
-                } while (deliver);
-        }
-}
-
-void kvm_s390_deliver_pending_machine_checks(struct kvm_vcpu *vcpu)
-{
-        struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
-        struct kvm_s390_float_interrupt *fi = vcpu->arch.local_int.float_int;
-        struct kvm_s390_interrupt_info  *n, *inti = NULL;
-        int deliver;
-
-        __reset_intercept_indicators(vcpu);
-        if (atomic_read(&li->active)) {
-                do {
-                        deliver = 0;
-                        spin_lock(&li->lock);
-                        list_for_each_entry_safe(inti, n, &li->list, list) {
-                                if ((inti->type == KVM_S390_MCHK) &&
-                                    __interrupt_is_deliverable(vcpu, inti)) {
-                                        list_del(&inti->list);
-                                        deliver = 1;
-                                        break;
-                                }
-                                __set_intercept_indicator(vcpu, inti);
-                        }
-                        if (list_empty(&li->list))
-                                atomic_set(&li->active, 0);
-                        spin_unlock(&li->lock);
-                        if (deliver) {
-                                __do_deliver_interrupt(vcpu, inti);
+                                rc = __do_deliver_interrupt(vcpu, inti);
                                 kfree(inti);
                         }
-                } while (deliver);
+                } while (!rc && deliver);
         }
 
-        if (atomic_read(&fi->active)) {
-                do {
-                        deliver = 0;
-                        spin_lock(&fi->lock);
-                        list_for_each_entry_safe(inti, n, &fi->list, list) {
-                                if ((inti->type == KVM_S390_MCHK) &&
-                                    __interrupt_is_deliverable(vcpu, inti)) {
-                                        list_del(&inti->list);
-                                        fi->irq_count--;
-                                        deliver = 1;
-                                        break;
-                                }
-                                __set_intercept_indicator(vcpu, inti);
-                        }
-                        if (list_empty(&fi->list))
-                                atomic_set(&fi->active, 0);
-                        spin_unlock(&fi->lock);
-                        if (deliver) {
-                                __do_deliver_interrupt(vcpu, inti);
-                                kfree(inti);
-                        }
-                } while (deliver);
-        }
+        return rc;
 }
 
 int kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code)
@@ -1048,7 +993,6 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
         trace_kvm_s390_inject_vcpu(vcpu->vcpu_id, s390int->type, s390int->parm,
                                    s390int->parm64, 2);
 
-        mutex_lock(&vcpu->kvm->lock);
         li = &vcpu->arch.local_int;
         spin_lock(&li->lock);
         if (inti->type == KVM_S390_PROGRAM_INT)
@@ -1060,7 +1004,6 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
                 li->action_bits |= ACTION_STOP_ON_STOP;
         atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
         spin_unlock(&li->lock);
-        mutex_unlock(&vcpu->kvm->lock);
         kvm_s390_vcpu_wakeup(vcpu);
         return 0;
 }
@@ -1300,7 +1243,7 @@ static int kvm_s390_adapter_map(struct kvm *kvm, unsigned int id, __u64 addr)
         }
         INIT_LIST_HEAD(&map->list);
         map->guest_addr = addr;
-        map->addr = gmap_translate(addr, kvm->arch.gmap);
+        map->addr = gmap_translate(kvm->arch.gmap, addr);
         if (map->addr == -EFAULT) {
                 ret = -EFAULT;
                 goto out;
@@ -1410,7 +1353,6 @@ static int flic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
                 r = enqueue_floating_irq(dev, attr);
                 break;
         case KVM_DEV_FLIC_CLEAR_IRQS:
-                r = 0;
                 kvm_s390_clear_float_irqs(dev->kvm);
                 break;
         case KVM_DEV_FLIC_APF_ENABLE:
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index ce81eb2ab76a..55aade49b6d1 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -50,6 +50,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
         { "exit_instruction", VCPU_STAT(exit_instruction) },
         { "exit_program_interruption", VCPU_STAT(exit_program_interruption) },
         { "exit_instr_and_program_int", VCPU_STAT(exit_instr_and_program) },
+        { "halt_wakeup", VCPU_STAT(halt_wakeup) },
         { "instruction_lctlg", VCPU_STAT(instruction_lctlg) },
         { "instruction_lctl", VCPU_STAT(instruction_lctl) },
         { "instruction_stctl", VCPU_STAT(instruction_stctl) },
@@ -100,16 +101,12 @@ int test_vfacility(unsigned long nr)
 }
 
 /* Section: not file related */
-int kvm_arch_hardware_enable(void *garbage)
+int kvm_arch_hardware_enable(void)
 {
         /* every s390 is virtualization enabled ;-) */
         return 0;
 }
 
-void kvm_arch_hardware_disable(void *garbage)
-{
-}
-
 static void kvm_gmap_notifier(struct gmap *gmap, unsigned long address);
 
 int kvm_arch_hardware_setup(void)
@@ -124,17 +121,10 @@ void kvm_arch_hardware_unsetup(void)
         gmap_unregister_ipte_notifier(&gmap_notifier);
 }
 
-void kvm_arch_check_processor_compat(void *rtn)
-{
-}
-
 int kvm_arch_init(void *opaque)
 {
-        return 0;
-}
-
-void kvm_arch_exit(void)
-{
+        /* Register floating interrupt controller interface. */
+        return kvm_register_device_ops(&kvm_flic_ops, KVM_DEV_TYPE_FLIC);
 }
 
 /* Section: device related */
@@ -404,6 +394,22 @@ long kvm_arch_vm_ioctl(struct file *filp,
         return r;
 }
 
+static int kvm_s390_crypto_init(struct kvm *kvm)
+{
+        if (!test_vfacility(76))
+                return 0;
+
+        kvm->arch.crypto.crycb = kzalloc(sizeof(*kvm->arch.crypto.crycb),
+                                         GFP_KERNEL | GFP_DMA);
+        if (!kvm->arch.crypto.crycb)
+                return -ENOMEM;
+
+        kvm->arch.crypto.crycbd = (__u32) (unsigned long) kvm->arch.crypto.crycb |
+                                  CRYCB_FORMAT1;
+
+        return 0;
+}
+
 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 {
         int rc;
@@ -441,6 +447,9 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
         if (!kvm->arch.dbf)
                 goto out_nodbf;
 
+        if (kvm_s390_crypto_init(kvm) < 0)
+                goto out_crypto;
+
         spin_lock_init(&kvm->arch.float_int.lock);
         INIT_LIST_HEAD(&kvm->arch.float_int.list);
         init_waitqueue_head(&kvm->arch.ipte_wq);
@@ -451,7 +460,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
         if (type & KVM_VM_S390_UCONTROL) {
                 kvm->arch.gmap = NULL;
         } else {
-                kvm->arch.gmap = gmap_alloc(current->mm);
+                kvm->arch.gmap = gmap_alloc(current->mm, (1UL << 44) - 1);
                 if (!kvm->arch.gmap)
                         goto out_nogmap;
                 kvm->arch.gmap->private = kvm;
@@ -465,6 +474,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 
         return 0;
 out_nogmap:
+        kfree(kvm->arch.crypto.crycb);
+out_crypto:
         debug_unregister(kvm->arch.dbf);
 out_nodbf:
         free_page((unsigned long)(kvm->arch.sca));
@@ -514,15 +525,12 @@ static void kvm_free_vcpus(struct kvm *kvm)
         mutex_unlock(&kvm->lock);
 }
 
-void kvm_arch_sync_events(struct kvm *kvm)
-{
-}
-
 void kvm_arch_destroy_vm(struct kvm *kvm)
 {
         kvm_free_vcpus(kvm);
         free_page((unsigned long)(kvm->arch.sca));
         debug_unregister(kvm->arch.dbf);
+        kfree(kvm->arch.crypto.crycb);
         if (!kvm_is_ucontrol(kvm))
                 gmap_free(kvm->arch.gmap);
         kvm_s390_destroy_adapters(kvm);
@@ -535,7 +543,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         vcpu->arch.pfault_token = KVM_S390_PFAULT_TOKEN_INVALID;
         kvm_clear_async_pf_completion_queue(vcpu);
         if (kvm_is_ucontrol(vcpu->kvm)) {
-                vcpu->arch.gmap = gmap_alloc(current->mm);
+                vcpu->arch.gmap = gmap_alloc(current->mm, -1UL);
                 if (!vcpu->arch.gmap)
                         return -ENOMEM;
                 vcpu->arch.gmap->private = vcpu->kvm;
@@ -546,15 +554,12 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         vcpu->run->kvm_valid_regs = KVM_SYNC_PREFIX |
                                     KVM_SYNC_GPRS |
                                     KVM_SYNC_ACRS |
-                                    KVM_SYNC_CRS;
+                                    KVM_SYNC_CRS |
+                                    KVM_SYNC_ARCH0 |
+                                    KVM_SYNC_PFAULT;
         return 0;
 }
 
-void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
-{
-        /* Nothing todo */
-}
-
 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
         save_fp_ctl(&vcpu->arch.host_fpregs.fpc);
@@ -607,6 +612,14 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
         return 0;
 }
 
+static void kvm_s390_vcpu_crypto_setup(struct kvm_vcpu *vcpu)
+{
+        if (!test_vfacility(76))
+                return;
+
+        vcpu->arch.sie_block->crycbd = vcpu->kvm->arch.crypto.crycbd;
+}
+
 void kvm_s390_vcpu_unsetup_cmma(struct kvm_vcpu *vcpu)
 {
         free_page(vcpu->arch.sie_block->cbrlo);
@@ -653,6 +666,9 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
         vcpu->arch.ckc_timer.function = kvm_s390_idle_wakeup;
         get_cpu_id(&vcpu->arch.cpu_id);
         vcpu->arch.cpu_id.version = 0xff;
+
+        kvm_s390_vcpu_crypto_setup(vcpu);
+
         return rc;
 }
 
@@ -1049,6 +1065,11 @@ retry:
                 goto retry;
         }
 
+        if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
+                vcpu->arch.sie_block->ihcpu = 0xffff;
+                goto retry;
+        }
+
         if (kvm_check_request(KVM_REQ_ENABLE_IBS, vcpu)) {
                 if (!ibs_enabled(vcpu)) {
                         trace_kvm_s390_enable_disable_ibs(vcpu->vcpu_id, 1);
@@ -1085,18 +1106,8 @@ retry:
  */
 long kvm_arch_fault_in_page(struct kvm_vcpu *vcpu, gpa_t gpa, int writable)
 {
-        struct mm_struct *mm = current->mm;
-        hva_t hva;
-        long rc;
-
-        hva = gmap_fault(gpa, vcpu->arch.gmap);
-        if (IS_ERR_VALUE(hva))
-                return (long)hva;
-        down_read(&mm->mmap_sem);
-        rc = get_user_pages(current, mm, hva, 1, writable, 0, NULL, NULL);
-        up_read(&mm->mmap_sem);
-
-        return rc < 0 ? rc : 0;
+        return gmap_fault(vcpu->arch.gmap, gpa,
+                          writable ? FAULT_FLAG_WRITE : 0);
 }
 
 static void __kvm_inject_pfault_token(struct kvm_vcpu *vcpu, bool start_token,
@@ -1191,8 +1202,11 @@ static int vcpu_pre_run(struct kvm_vcpu *vcpu)
         if (test_cpu_flag(CIF_MCCK_PENDING))
                 s390_handle_mcck();
 
-        if (!kvm_is_ucontrol(vcpu->kvm))
-                kvm_s390_deliver_pending_interrupts(vcpu);
+        if (!kvm_is_ucontrol(vcpu->kvm)) {
+                rc = kvm_s390_deliver_pending_interrupts(vcpu);
+                if (rc)
+                        return rc;
+        }
 
         rc = kvm_s390_handle_requests(vcpu);
         if (rc)
@@ -1296,6 +1310,48 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
         return rc;
 }
 
+static void sync_regs(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
+{
+        vcpu->arch.sie_block->gpsw.mask = kvm_run->psw_mask;
+        vcpu->arch.sie_block->gpsw.addr = kvm_run->psw_addr;
+        if (kvm_run->kvm_dirty_regs & KVM_SYNC_PREFIX)
+                kvm_s390_set_prefix(vcpu, kvm_run->s.regs.prefix);
+        if (kvm_run->kvm_dirty_regs & KVM_SYNC_CRS) {
+                memcpy(&vcpu->arch.sie_block->gcr, &kvm_run->s.regs.crs, 128);
+                /* some control register changes require a tlb flush */
+                kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
+        }
+        if (kvm_run->kvm_dirty_regs & KVM_SYNC_ARCH0) {
+                vcpu->arch.sie_block->cputm = kvm_run->s.regs.cputm;
+                vcpu->arch.sie_block->ckc = kvm_run->s.regs.ckc;
+                vcpu->arch.sie_block->todpr = kvm_run->s.regs.todpr;
+                vcpu->arch.sie_block->pp = kvm_run->s.regs.pp;
+                vcpu->arch.sie_block->gbea = kvm_run->s.regs.gbea;
+        }
+        if (kvm_run->kvm_dirty_regs & KVM_SYNC_PFAULT) {
+                vcpu->arch.pfault_token = kvm_run->s.regs.pft;
+                vcpu->arch.pfault_select = kvm_run->s.regs.pfs;
+                vcpu->arch.pfault_compare = kvm_run->s.regs.pfc;
+        }
+        kvm_run->kvm_dirty_regs = 0;
+}
+
+static void store_regs(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
+{
+        kvm_run->psw_mask = vcpu->arch.sie_block->gpsw.mask;
+        kvm_run->psw_addr = vcpu->arch.sie_block->gpsw.addr;
+        kvm_run->s.regs.prefix = kvm_s390_get_prefix(vcpu);
+        memcpy(&kvm_run->s.regs.crs, &vcpu->arch.sie_block->gcr, 128);
+        kvm_run->s.regs.cputm = vcpu->arch.sie_block->cputm;
+        kvm_run->s.regs.ckc = vcpu->arch.sie_block->ckc;
+        kvm_run->s.regs.todpr = vcpu->arch.sie_block->todpr;
+        kvm_run->s.regs.pp = vcpu->arch.sie_block->pp;
+        kvm_run->s.regs.gbea = vcpu->arch.sie_block->gbea;
+        kvm_run->s.regs.pft = vcpu->arch.pfault_token;
+        kvm_run->s.regs.pfs = vcpu->arch.pfault_select;
+        kvm_run->s.regs.pfc = vcpu->arch.pfault_compare;
+}
+
 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 {
         int rc;
@@ -1317,30 +1373,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                 return -EINVAL;
         }
 
-        switch (kvm_run->exit_reason) {
-        case KVM_EXIT_S390_SIEIC:
-        case KVM_EXIT_UNKNOWN:
-        case KVM_EXIT_INTR:
-        case KVM_EXIT_S390_RESET:
-        case KVM_EXIT_S390_UCONTROL:
-        case KVM_EXIT_S390_TSCH:
-        case KVM_EXIT_DEBUG:
-                break;
-        default:
-                BUG();
-        }
-
-        vcpu->arch.sie_block->gpsw.mask = kvm_run->psw_mask;
-        vcpu->arch.sie_block->gpsw.addr = kvm_run->psw_addr;
-        if (kvm_run->kvm_dirty_regs & KVM_SYNC_PREFIX) {
-                kvm_run->kvm_dirty_regs &= ~KVM_SYNC_PREFIX;
-                kvm_s390_set_prefix(vcpu, kvm_run->s.regs.prefix);
-        }
-        if (kvm_run->kvm_dirty_regs & KVM_SYNC_CRS) {
-                kvm_run->kvm_dirty_regs &= ~KVM_SYNC_CRS;
-                memcpy(&vcpu->arch.sie_block->gcr, &kvm_run->s.regs.crs, 128);
-                kvm_s390_set_prefix(vcpu, kvm_run->s.regs.prefix);
-        }
+        sync_regs(vcpu, kvm_run);
 
         might_fault();
         rc = __vcpu_run(vcpu);
@@ -1370,10 +1403,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                 rc = 0;
         }
 
-        kvm_run->psw_mask     = vcpu->arch.sie_block->gpsw.mask;
-        kvm_run->psw_addr     = vcpu->arch.sie_block->gpsw.addr;
-        kvm_run->s.regs.prefix = kvm_s390_get_prefix(vcpu);
-        memcpy(&kvm_run->s.regs.crs, &vcpu->arch.sie_block->gcr, 128);
+        store_regs(vcpu, kvm_run);
 
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
@@ -1502,7 +1532,7 @@ void kvm_s390_vcpu_start(struct kvm_vcpu *vcpu)
          * Another VCPU might have used IBS while we were offline.
          * Let's play safe and flush the VCPU at startup.
          */
-        vcpu->arch.sie_block->ihcpu  = 0xffff;
+        kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
         spin_unlock(&vcpu->kvm->arch.start_stop_lock);
         return;
 }
@@ -1657,9 +1687,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
         }
 #endif
         case KVM_S390_VCPU_FAULT: {
-                r = gmap_fault(arg, vcpu->arch.gmap);
-                if (!IS_ERR_VALUE(r))
-                        r = 0;
+                r = gmap_fault(vcpu->arch.gmap, arg, 0);
                 break;
         }
         case KVM_ENABLE_CAP:
@@ -1690,21 +1718,12 @@ int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
         return VM_FAULT_SIGBUS;
 }
 
-void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
-                           struct kvm_memory_slot *dont)
-{
-}
-
 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
                             unsigned long npages)
 {
         return 0;
 }
 
-void kvm_arch_memslots_updated(struct kvm *kvm)
-{
-}
-
 /* Section: memory related */
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                    struct kvm_memory_slot *memslot,
@@ -1750,15 +1769,6 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
         return;
 }
 
-void kvm_arch_flush_shadow_all(struct kvm *kvm)
-{
-}
-
-void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
-                                   struct kvm_memory_slot *slot)
-{
-}
-
 static int __init kvm_s390_init(void)
 {
         int ret;
@@ -1777,7 +1787,7 @@ static int __init kvm_s390_init(void)
                 return -ENOMEM;
         }
         memcpy(vfacilities, S390_lowcore.stfle_fac_list, 16);
-        vfacilities[0] &= 0xff82fff3f4fc2000UL;
+        vfacilities[0] &= 0xff82fffbf47c2000UL;
         vfacilities[1] &= 0x005c000000000000UL;
         return 0;
 }
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index 3862fa2cefe0..244d02303182 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -70,7 +70,7 @@ static inline u32 kvm_s390_get_prefix(struct kvm_vcpu *vcpu)
 static inline void kvm_s390_set_prefix(struct kvm_vcpu *vcpu, u32 prefix)
 {
         vcpu->arch.sie_block->prefix = prefix >> GUEST_PREFIX_SHIFT;
-        vcpu->arch.sie_block->ihcpu  = 0xffff;
+        kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
         kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu);
 }
 
@@ -138,8 +138,7 @@ static inline int kvm_s390_user_cpu_state_ctrl(struct kvm *kvm)
 int kvm_s390_handle_wait(struct kvm_vcpu *vcpu);
 void kvm_s390_vcpu_wakeup(struct kvm_vcpu *vcpu);
 enum hrtimer_restart kvm_s390_idle_wakeup(struct hrtimer *timer);
-void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu);
-void kvm_s390_deliver_pending_machine_checks(struct kvm_vcpu *vcpu);
+int __must_check kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu);
 void kvm_s390_clear_local_irqs(struct kvm_vcpu *vcpu);
 void kvm_s390_clear_float_irqs(struct kvm *kvm);
 int __must_check kvm_s390_inject_vm(struct kvm *kvm,
@@ -228,6 +227,7 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
 int psw_extint_disabled(struct kvm_vcpu *vcpu);
 void kvm_s390_destroy_adapters(struct kvm *kvm);
 int kvm_s390_si_ext_call_pending(struct kvm_vcpu *vcpu);
+extern struct kvm_device_ops kvm_flic_ops;
 
 /* implemented in guestdbg.c */
 void kvm_s390_backup_guest_per_regs(struct kvm_vcpu *vcpu);
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index f89c1cd67751..72bb2dd8b9cd 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -352,13 +352,6 @@ static int handle_stfl(struct kvm_vcpu *vcpu)
         return 0;
 }
 
-static void handle_new_psw(struct kvm_vcpu *vcpu)
-{
-        /* Check whether the new psw is enabled for machine checks. */
-        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_MCHECK)
-                kvm_s390_deliver_pending_machine_checks(vcpu);
-}
-
 #define PSW_MASK_ADDR_MODE (PSW_MASK_EA | PSW_MASK_BA)
 #define PSW_MASK_UNASSIGNED 0xb80800fe7fffffffUL
 #define PSW_ADDR_24 0x0000000000ffffffUL
@@ -405,7 +398,6 @@ int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu)
         gpsw->addr = new_psw.addr & ~PSW32_ADDR_AMODE;
         if (!is_valid_psw(gpsw))
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-        handle_new_psw(vcpu);
         return 0;
 }
 
@@ -427,7 +419,6 @@ static int handle_lpswe(struct kvm_vcpu *vcpu)
         vcpu->arch.sie_block->gpsw = new_psw;
         if (!is_valid_psw(&vcpu->arch.sie_block->gpsw))
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-        handle_new_psw(vcpu);
         return 0;
 }
 
@@ -738,7 +729,7 @@ static int handle_essa(struct kvm_vcpu *vcpu)
                         /* invalid entry */
                         break;
                 /* try to free backing */
-                __gmap_zap(cbrle, gmap);
+                __gmap_zap(gmap, cbrle);
         }
         up_read(&gmap->mm->mmap_sem);
         if (i < entries)
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index 3f3b35403d0a..a2b81d6ce8a5 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -442,18 +442,15 @@ static inline int do_exception(struct pt_regs *regs, int access)
         down_read(&mm->mmap_sem);
 
 #ifdef CONFIG_PGSTE
-        gmap = (struct gmap *)
-                ((current->flags & PF_VCPU) ? S390_lowcore.gmap : 0);
+        gmap = (current->flags & PF_VCPU) ?
+                (struct gmap *) S390_lowcore.gmap : NULL;
         if (gmap) {
-                address = __gmap_fault(address, gmap);
+                current->thread.gmap_addr = address;
+                address = __gmap_translate(gmap, address);
                 if (address == -EFAULT) {
                         fault = VM_FAULT_BADMAP;
                         goto out_up;
                 }
-                if (address == -ENOMEM) {
-                        fault = VM_FAULT_OOM;
-                        goto out_up;
-                }
                 if (gmap->pfault_enabled)
                         flags |= FAULT_FLAG_RETRY_NOWAIT;
         }
@@ -530,6 +527,20 @@ retry:
                         goto retry;
                 }
         }
+#ifdef CONFIG_PGSTE
+        if (gmap) {
+                address =  __gmap_link(gmap, current->thread.gmap_addr,
+                                       address);
+                if (address == -EFAULT) {
+                        fault = VM_FAULT_BADMAP;
+                        goto out_up;
+                }
+                if (address == -ENOMEM) {
+                        fault = VM_FAULT_OOM;
+                        goto out_up;
+                }
+        }
+#endif
         fault = 0;
 out_up:
         up_read(&mm->mmap_sem);
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 0c1073ed1e84..c7235e01fd67 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -43,6 +43,7 @@ pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__((__aligned__(PAGE_SIZE)));
 
 unsigned long empty_zero_page, zero_page_mask;
 EXPORT_SYMBOL(empty_zero_page);
+EXPORT_SYMBOL(zero_page_mask);
 
 static void __init setup_zero_pages(void)
 {
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 19daa53a3da4..296b61a4af59 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -145,30 +145,56 @@ void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)
 /**
  * gmap_alloc - allocate a guest address space
  * @mm: pointer to the parent mm_struct
+ * @limit: maximum size of the gmap address space
  *
  * Returns a guest address space structure.
  */
-struct gmap *gmap_alloc(struct mm_struct *mm)
+struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit)
 {
         struct gmap *gmap;
         struct page *page;
         unsigned long *table;
-
+        unsigned long etype, atype;
+
+        if (limit < (1UL << 31)) {
+                limit = (1UL << 31) - 1;
+                atype = _ASCE_TYPE_SEGMENT;
+                etype = _SEGMENT_ENTRY_EMPTY;
+        } else if (limit < (1UL << 42)) {
+                limit = (1UL << 42) - 1;
+                atype = _ASCE_TYPE_REGION3;
+                etype = _REGION3_ENTRY_EMPTY;
+        } else if (limit < (1UL << 53)) {
+                limit = (1UL << 53) - 1;
+                atype = _ASCE_TYPE_REGION2;
+                etype = _REGION2_ENTRY_EMPTY;
+        } else {
+                limit = -1UL;
+                atype = _ASCE_TYPE_REGION1;
+                etype = _REGION1_ENTRY_EMPTY;
+        }
         gmap = kzalloc(sizeof(struct gmap), GFP_KERNEL);
         if (!gmap)
                 goto out;
         INIT_LIST_HEAD(&gmap->crst_list);
+        INIT_RADIX_TREE(&gmap->guest_to_host, GFP_KERNEL);
+        INIT_RADIX_TREE(&gmap->host_to_guest, GFP_ATOMIC);
+        spin_lock_init(&gmap->guest_table_lock);
         gmap->mm = mm;
         page = alloc_pages(GFP_KERNEL, ALLOC_ORDER);
         if (!page)
                 goto out_free;
+        page->index = 0;
         list_add(&page->lru, &gmap->crst_list);
         table = (unsigned long *) page_to_phys(page);
-        crst_table_init(table, _REGION1_ENTRY_EMPTY);
+        crst_table_init(table, etype);
         gmap->table = table;
-        gmap->asce = _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH |
-                     _ASCE_USER_BITS | __pa(table);
+        gmap->asce = atype | _ASCE_TABLE_LENGTH |
+                _ASCE_USER_BITS | __pa(table);
+        gmap->asce_end = limit;
+        down_write(&mm->mmap_sem);
         list_add(&gmap->list, &mm->context.gmap_list);
+        up_write(&mm->mmap_sem);
         return gmap;
 
 out_free:
@@ -178,36 +204,38 @@ out:
 }
 EXPORT_SYMBOL_GPL(gmap_alloc);
 
-static int gmap_unlink_segment(struct gmap *gmap, unsigned long *table)
-{
-        struct gmap_pgtable *mp;
-        struct gmap_rmap *rmap;
-        struct page *page;
-
-        if (*table & _SEGMENT_ENTRY_INVALID)
-                return 0;
-        page = pfn_to_page(*table >> PAGE_SHIFT);
-        mp = (struct gmap_pgtable *) page->index;
-        list_for_each_entry(rmap, &mp->mapper, list) {
-                if (rmap->entry != table)
-                        continue;
-                list_del(&rmap->list);
-                kfree(rmap);
-                break;
-        }
-        *table = mp->vmaddr | _SEGMENT_ENTRY_INVALID | _SEGMENT_ENTRY_PROTECT;
-        return 1;
-}
-
 static void gmap_flush_tlb(struct gmap *gmap)
 {
         if (MACHINE_HAS_IDTE)
-                __tlb_flush_asce(gmap->mm, (unsigned long) gmap->table |
-                                 _ASCE_TYPE_REGION1);
+                __tlb_flush_asce(gmap->mm, gmap->asce);
         else
                 __tlb_flush_global();
 }
 
+static void gmap_radix_tree_free(struct radix_tree_root *root)
+{
+        struct radix_tree_iter iter;
+        unsigned long indices[16];
+        unsigned long index;
+        void **slot;
+        int i, nr;
+
+        /* A radix tree is freed by deleting all of its entries */
+        index = 0;
+        do {
+                nr = 0;
+                radix_tree_for_each_slot(slot, root, &iter, index) {
+                        indices[nr] = iter.index;
+                        if (++nr == 16)
+                                break;
+                }
+                for (i = 0; i < nr; i++) {
+                        index = indices[i];
+                        radix_tree_delete(root, index);
+                }
+        } while (nr > 0);
+}
+
 /**
  * gmap_free - free a guest address space
  * @gmap: pointer to the guest address space structure
@@ -215,31 +243,21 @@ static void gmap_flush_tlb(struct gmap *gmap)
 void gmap_free(struct gmap *gmap)
 {
         struct page *page, *next;
-        unsigned long *table;
-        int i;
-
 
         /* Flush tlb. */
         if (MACHINE_HAS_IDTE)
-                __tlb_flush_asce(gmap->mm, (unsigned long) gmap->table |
-                                 _ASCE_TYPE_REGION1);
+                __tlb_flush_asce(gmap->mm, gmap->asce);
         else
                 __tlb_flush_global();
 
         /* Free all segment & region tables. */
-        down_read(&gmap->mm->mmap_sem);
-        spin_lock(&gmap->mm->page_table_lock);
-        list_for_each_entry_safe(page, next, &gmap->crst_list, lru) {
-                table = (unsigned long *) page_to_phys(page);
-                if ((*table & _REGION_ENTRY_TYPE_MASK) == 0)
-                        /* Remove gmap rmap structures for segment table. */
-                        for (i = 0; i < PTRS_PER_PMD; i++, table++)
-                                gmap_unlink_segment(gmap, table);
+        list_for_each_entry_safe(page, next, &gmap->crst_list, lru)
                 __free_pages(page, ALLOC_ORDER);
-        }
-        spin_unlock(&gmap->mm->page_table_lock);
-        up_read(&gmap->mm->mmap_sem);
+        gmap_radix_tree_free(&gmap->guest_to_host);
+        gmap_radix_tree_free(&gmap->host_to_guest);
+        down_write(&gmap->mm->mmap_sem);
         list_del(&gmap->list);
+        up_write(&gmap->mm->mmap_sem);
         kfree(gmap);
 }
 EXPORT_SYMBOL_GPL(gmap_free);
@@ -267,42 +285,97 @@ EXPORT_SYMBOL_GPL(gmap_disable);
 /*
  * gmap_alloc_table is assumed to be called with mmap_sem held
  */
-static int gmap_alloc_table(struct gmap *gmap,
-                            unsigned long *table, unsigned long init)
-        __releases(&gmap->mm->page_table_lock)
-        __acquires(&gmap->mm->page_table_lock)
+static int gmap_alloc_table(struct gmap *gmap, unsigned long *table,
+                            unsigned long init, unsigned long gaddr)
 {
         struct page *page;
         unsigned long *new;
 
         /* since we dont free the gmap table until gmap_free we can unlock */
-        spin_unlock(&gmap->mm->page_table_lock);
         page = alloc_pages(GFP_KERNEL, ALLOC_ORDER);
-        spin_lock(&gmap->mm->page_table_lock);
         if (!page)
                 return -ENOMEM;
         new = (unsigned long *) page_to_phys(page);
         crst_table_init(new, init);
+        spin_lock(&gmap->mm->page_table_lock);
         if (*table & _REGION_ENTRY_INVALID) {
                 list_add(&page->lru, &gmap->crst_list);
                 *table = (unsigned long) new | _REGION_ENTRY_LENGTH |
                         (*table & _REGION_ENTRY_TYPE_MASK);
-        } else
+                page->index = gaddr;
+                page = NULL;
+        }
+        spin_unlock(&gmap->mm->page_table_lock);
+        if (page)
                 __free_pages(page, ALLOC_ORDER);
         return 0;
 }
 
 /**
+ * __gmap_segment_gaddr - find virtual address from segment pointer
+ * @entry: pointer to a segment table entry in the guest address space
+ *
+ * Returns the virtual address in the guest address space for the segment
+ */
+static unsigned long __gmap_segment_gaddr(unsigned long *entry)
+{
+        struct page *page;
+        unsigned long offset;
+
+        offset = (unsigned long) entry / sizeof(unsigned long);
+        offset = (offset & (PTRS_PER_PMD - 1)) * PMD_SIZE;
+        page = pmd_to_page((pmd_t *) entry);
+        return page->index + offset;
+}
+
+/**
+ * __gmap_unlink_by_vmaddr - unlink a single segment via a host address
+ * @gmap: pointer to the guest address space structure
+ * @vmaddr: address in the host process address space
+ *
+ * Returns 1 if a TLB flush is required
+ */
+static int __gmap_unlink_by_vmaddr(struct gmap *gmap, unsigned long vmaddr)
+{
+        unsigned long *entry;
+        int flush = 0;
+
+        spin_lock(&gmap->guest_table_lock);
+        entry = radix_tree_delete(&gmap->host_to_guest, vmaddr >> PMD_SHIFT);
+        if (entry) {
+                flush = (*entry != _SEGMENT_ENTRY_INVALID);
+                *entry = _SEGMENT_ENTRY_INVALID;
+        }
+        spin_unlock(&gmap->guest_table_lock);
+        return flush;
+}
+
+/**
+ * __gmap_unmap_by_gaddr - unmap a single segment via a guest address
+ * @gmap: pointer to the guest address space structure
+ * @gaddr: address in the guest address space
+ *
+ * Returns 1 if a TLB flush is required
+ */
+static int __gmap_unmap_by_gaddr(struct gmap *gmap, unsigned long gaddr)
+{
+        unsigned long vmaddr;
+
+        vmaddr = (unsigned long) radix_tree_delete(&gmap->guest_to_host,
+                                                   gaddr >> PMD_SHIFT);
+        return vmaddr ? __gmap_unlink_by_vmaddr(gmap, vmaddr) : 0;
+}
+
+/**
  * gmap_unmap_segment - unmap segment from the guest address space
  * @gmap: pointer to the guest address space structure
- * @addr: address in the guest address space
+ * @to: address in the guest address space
  * @len: length of the memory area to unmap
  *
  * Returns 0 if the unmap succeeded, -EINVAL if not.
  */
 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
 {
-        unsigned long *table;
         unsigned long off;
         int flush;
 
@@ -312,31 +385,10 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
                 return -EINVAL;
 
         flush = 0;
-        down_read(&gmap->mm->mmap_sem);
-        spin_lock(&gmap->mm->page_table_lock);
-        for (off = 0; off < len; off += PMD_SIZE) {
-                /* Walk the guest addr space page table */
-                table = gmap->table + (((to + off) >> 53) & 0x7ff);
-                if (*table & _REGION_ENTRY_INVALID)
-                        goto out;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + (((to + off) >> 42) & 0x7ff);
-                if (*table & _REGION_ENTRY_INVALID)
-                        goto out;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + (((to + off) >> 31) & 0x7ff);
-                if (*table & _REGION_ENTRY_INVALID)
-                        goto out;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + (((to + off) >> 20) & 0x7ff);
-
-                /* Clear segment table entry in guest address space. */
-                flush |= gmap_unlink_segment(gmap, table);
-                *table = _SEGMENT_ENTRY_INVALID;
-        }
-out:
-        spin_unlock(&gmap->mm->page_table_lock);
-        up_read(&gmap->mm->mmap_sem);
+        down_write(&gmap->mm->mmap_sem);
+        for (off = 0; off < len; off += PMD_SIZE)
+                flush |= __gmap_unmap_by_gaddr(gmap, to + off);
+        up_write(&gmap->mm->mmap_sem);
         if (flush)
                 gmap_flush_tlb(gmap);
         return 0;
@@ -348,87 +400,47 @@ EXPORT_SYMBOL_GPL(gmap_unmap_segment);
  * @gmap: pointer to the guest address space structure
  * @from: source address in the parent address space
  * @to: target address in the guest address space
+ * @len: length of the memory area to map
  *
  * Returns 0 if the mmap succeeded, -EINVAL or -ENOMEM if not.
  */
 int gmap_map_segment(struct gmap *gmap, unsigned long from,
                      unsigned long to, unsigned long len)
 {
-        unsigned long *table;
         unsigned long off;
         int flush;
 
         if ((from | to | len) & (PMD_SIZE - 1))
                 return -EINVAL;
-        if (len == 0 || from + len > TASK_MAX_SIZE ||
-            from + len < from || to + len < to)
+        if (len == 0 || from + len < from || to + len < to ||
+            from + len > TASK_MAX_SIZE || to + len > gmap->asce_end)
                 return -EINVAL;
 
         flush = 0;
-        down_read(&gmap->mm->mmap_sem);
-        spin_lock(&gmap->mm->page_table_lock);
+        down_write(&gmap->mm->mmap_sem);
         for (off = 0; off < len; off += PMD_SIZE) {
-                /* Walk the gmap address space page table */
-                table = gmap->table + (((to + off) >> 53) & 0x7ff);
-                if ((*table & _REGION_ENTRY_INVALID) &&
-                    gmap_alloc_table(gmap, table, _REGION2_ENTRY_EMPTY))
-                        goto out_unmap;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + (((to + off) >> 42) & 0x7ff);
-                if ((*table & _REGION_ENTRY_INVALID) &&
-                    gmap_alloc_table(gmap, table, _REGION3_ENTRY_EMPTY))
-                        goto out_unmap;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + (((to + off) >> 31) & 0x7ff);
-                if ((*table & _REGION_ENTRY_INVALID) &&
-                    gmap_alloc_table(gmap, table, _SEGMENT_ENTRY_EMPTY))
-                        goto out_unmap;
-                table = (unsigned long *) (*table & _REGION_ENTRY_ORIGIN);
-                table = table + (((to + off) >> 20) & 0x7ff);
-
-                /* Store 'from' address in an invalid segment table entry. */
-                flush |= gmap_unlink_segment(gmap, table);
-                *table =  (from + off) | (_SEGMENT_ENTRY_INVALID |
-                                          _SEGMENT_ENTRY_PROTECT);
+                /* Remove old translation */
+                flush |= __gmap_unmap_by_gaddr(gmap, to + off);
+                /* Store new translation */
+                if (radix_tree_insert(&gmap->guest_to_host,
+                                      (to + off) >> PMD_SHIFT,
+                                      (void *) from + off))
+                        break;
         }
-        spin_unlock(&gmap->mm->page_table_lock);
-        up_read(&gmap->mm->mmap_sem);
+        up_write(&gmap->mm->mmap_sem);
         if (flush)
                 gmap_flush_tlb(gmap);
-        return 0;
-
-out_unmap:
-        spin_unlock(&gmap->mm->page_table_lock);
-        up_read(&gmap->mm->mmap_sem);
+        if (off >= len)
+                return 0;
         gmap_unmap_segment(gmap, to, len);
         return -ENOMEM;
 }
 EXPORT_SYMBOL_GPL(gmap_map_segment);
 
-static unsigned long *gmap_table_walk(unsigned long address, struct gmap *gmap)
-{
-        unsigned long *table;
-
-        table = gmap->table + ((address >> 53) & 0x7ff);
-        if (unlikely(*table & _REGION_ENTRY_INVALID))
-                return ERR_PTR(-EFAULT);
-        table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-        table = table + ((address >> 42) & 0x7ff);
-        if (unlikely(*table & _REGION_ENTRY_INVALID))
-                return ERR_PTR(-EFAULT);
-        table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-        table = table + ((address >> 31) & 0x7ff);
-        if (unlikely(*table & _REGION_ENTRY_INVALID))
-                return ERR_PTR(-EFAULT);
-        table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-        table = table + ((address >> 20) & 0x7ff);
-        return table;
-}
-
 /**
  * __gmap_translate - translate a guest address to a user space address
- * @address: guest address
  * @gmap: pointer to guest mapping meta data structure
+ * @gaddr: guest address
  *
  * Returns user space address which corresponds to the guest address or
  * -EFAULT if no such mapping exists.
@@ -436,168 +448,161 @@ static unsigned long *gmap_table_walk(unsigned long address, struct gmap *gmap)
  * The mmap_sem of the mm that belongs to the address space must be held
  * when this function gets called.
  */
-unsigned long __gmap_translate(unsigned long address, struct gmap *gmap)
+unsigned long __gmap_translate(struct gmap *gmap, unsigned long gaddr)
 {
-        unsigned long *segment_ptr, vmaddr, segment;
-        struct gmap_pgtable *mp;
-        struct page *page;
+        unsigned long vmaddr;
 
-        current->thread.gmap_addr = address;
-        segment_ptr = gmap_table_walk(address, gmap);
-        if (IS_ERR(segment_ptr))
-                return PTR_ERR(segment_ptr);
-        /* Convert the gmap address to an mm address. */
-        segment = *segment_ptr;
-        if (!(segment & _SEGMENT_ENTRY_INVALID)) {
-                page = pfn_to_page(segment >> PAGE_SHIFT);
-                mp = (struct gmap_pgtable *) page->index;
-                return mp->vmaddr | (address & ~PMD_MASK);
-        } else if (segment & _SEGMENT_ENTRY_PROTECT) {
-                vmaddr = segment & _SEGMENT_ENTRY_ORIGIN;
-                return vmaddr | (address & ~PMD_MASK);
-        }
-        return -EFAULT;
+        vmaddr = (unsigned long)
+                radix_tree_lookup(&gmap->guest_to_host, gaddr >> PMD_SHIFT);
+        return vmaddr ? (vmaddr | (gaddr & ~PMD_MASK)) : -EFAULT;
 }
 EXPORT_SYMBOL_GPL(__gmap_translate);
 
 /**
  * gmap_translate - translate a guest address to a user space address
- * @address: guest address
  * @gmap: pointer to guest mapping meta data structure
+ * @gaddr: guest address
  *
  * Returns user space address which corresponds to the guest address or
  * -EFAULT if no such mapping exists.
  * This function does not establish potentially missing page table entries.
  */
-unsigned long gmap_translate(unsigned long address, struct gmap *gmap)
+unsigned long gmap_translate(struct gmap *gmap, unsigned long gaddr)
 {
         unsigned long rc;
 
         down_read(&gmap->mm->mmap_sem);
-        rc = __gmap_translate(address, gmap);
+        rc = __gmap_translate(gmap, gaddr);
         up_read(&gmap->mm->mmap_sem);
         return rc;
 }
 EXPORT_SYMBOL_GPL(gmap_translate);
 
-static int gmap_connect_pgtable(unsigned long address, unsigned long segment,
-                                unsigned long *segment_ptr, struct gmap *gmap)
+/**
+ * gmap_unlink - disconnect a page table from the gmap shadow tables
+ * @gmap: pointer to guest mapping meta data structure
+ * @table: pointer to the host page table
+ * @vmaddr: vm address associated with the host page table
+ */
+static void gmap_unlink(struct mm_struct *mm, unsigned long *table,
+                        unsigned long vmaddr)
+{
+        struct gmap *gmap;
+        int flush;
+
+        list_for_each_entry(gmap, &mm->context.gmap_list, list) {
+                flush = __gmap_unlink_by_vmaddr(gmap, vmaddr);
+                if (flush)
+                        gmap_flush_tlb(gmap);
+        }
+}
+
+/**
+ * gmap_link - set up shadow page tables to connect a host to a guest address
+ * @gmap: pointer to guest mapping meta data structure
+ * @gaddr: guest address
+ * @vmaddr: vm address
+ *
+ * Returns 0 on success, -ENOMEM for out of memory conditions, and -EFAULT
+ * if the vm address is already mapped to a different guest segment.
+ * The mmap_sem of the mm that belongs to the address space must be held
+ * when this function gets called.
+ */
+int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr)
 {
-        unsigned long vmaddr;
-        struct vm_area_struct *vma;
-        struct gmap_pgtable *mp;
-        struct gmap_rmap *rmap;
         struct mm_struct *mm;
-        struct page *page;
+        unsigned long *table;
+        spinlock_t *ptl;
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
+        int rc;
 
-        mm = gmap->mm;
-        vmaddr = segment & _SEGMENT_ENTRY_ORIGIN;
-        vma = find_vma(mm, vmaddr);
-        if (!vma || vma->vm_start > vmaddr)
-                return -EFAULT;
+        /* Create higher level tables in the gmap page table */
+        table = gmap->table;
+        if ((gmap->asce & _ASCE_TYPE_MASK) >= _ASCE_TYPE_REGION1) {
+                table += (gaddr >> 53) & 0x7ff;
+                if ((*table & _REGION_ENTRY_INVALID) &&
+                    gmap_alloc_table(gmap, table, _REGION2_ENTRY_EMPTY,
+                                     gaddr & 0xffe0000000000000))
+                        return -ENOMEM;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        }
+        if ((gmap->asce & _ASCE_TYPE_MASK) >= _ASCE_TYPE_REGION2) {
+                table += (gaddr >> 42) & 0x7ff;
+                if ((*table & _REGION_ENTRY_INVALID) &&
+                    gmap_alloc_table(gmap, table, _REGION3_ENTRY_EMPTY,
+                                     gaddr & 0xfffffc0000000000))
+                        return -ENOMEM;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        }
+        if ((gmap->asce & _ASCE_TYPE_MASK) >= _ASCE_TYPE_REGION3) {
+                table += (gaddr >> 31) & 0x7ff;
+                if ((*table & _REGION_ENTRY_INVALID) &&
+                    gmap_alloc_table(gmap, table, _SEGMENT_ENTRY_EMPTY,
+                                     gaddr & 0xffffffff80000000))
+                        return -ENOMEM;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        }
+        table += (gaddr >> 20) & 0x7ff;
         /* Walk the parent mm page table */
+        mm = gmap->mm;
         pgd = pgd_offset(mm, vmaddr);
-        pud = pud_alloc(mm, pgd, vmaddr);
-        if (!pud)
-                return -ENOMEM;
-        pmd = pmd_alloc(mm, pud, vmaddr);
-        if (!pmd)
-                return -ENOMEM;
-        if (!pmd_present(*pmd) &&
-            __pte_alloc(mm, vma, pmd, vmaddr))
-                return -ENOMEM;
+        VM_BUG_ON(pgd_none(*pgd));
+        pud = pud_offset(pgd, vmaddr);
+        VM_BUG_ON(pud_none(*pud));
+        pmd = pmd_offset(pud, vmaddr);
+        VM_BUG_ON(pmd_none(*pmd));
         /* large pmds cannot yet be handled */
         if (pmd_large(*pmd))
                 return -EFAULT;
-        /* pmd now points to a valid segment table entry. */
-        rmap = kmalloc(sizeof(*rmap), GFP_KERNEL|__GFP_REPEAT);
-        if (!rmap)
-                return -ENOMEM;
         /* Link gmap segment table entry location to page table. */
-        page = pmd_page(*pmd);
-        mp = (struct gmap_pgtable *) page->index;
-        rmap->gmap = gmap;
-        rmap->entry = segment_ptr;
-        rmap->vmaddr = address & PMD_MASK;
-        spin_lock(&mm->page_table_lock);
-        if (*segment_ptr == segment) {
-                list_add(&rmap->list, &mp->mapper);
-                /* Set gmap segment table entry to page table. */
-                *segment_ptr = pmd_val(*pmd) & PAGE_MASK;
-                rmap = NULL;
-        }
-        spin_unlock(&mm->page_table_lock);
-        kfree(rmap);
-        return 0;
-}
-
-static void gmap_disconnect_pgtable(struct mm_struct *mm, unsigned long *table)
-{
-        struct gmap_rmap *rmap, *next;
-        struct gmap_pgtable *mp;
-        struct page *page;
-        int flush;
-
-        flush = 0;
-        spin_lock(&mm->page_table_lock);
-        page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
-        mp = (struct gmap_pgtable *) page->index;
-        list_for_each_entry_safe(rmap, next, &mp->mapper, list) {
-                *rmap->entry = mp->vmaddr | (_SEGMENT_ENTRY_INVALID |
-                                             _SEGMENT_ENTRY_PROTECT);
-                list_del(&rmap->list);
-                kfree(rmap);
-                flush = 1;
-        }
-        spin_unlock(&mm->page_table_lock);
-        if (flush)
-                __tlb_flush_global();
+        rc = radix_tree_preload(GFP_KERNEL);
+        if (rc)
+                return rc;
+        ptl = pmd_lock(mm, pmd);
+        spin_lock(&gmap->guest_table_lock);
+        if (*table == _SEGMENT_ENTRY_INVALID) {
+                rc = radix_tree_insert(&gmap->host_to_guest,
+                                       vmaddr >> PMD_SHIFT, table);
+                if (!rc)
+                        *table = pmd_val(*pmd);
+        } else
+                rc = 0;
+        spin_unlock(&gmap->guest_table_lock);
+        spin_unlock(ptl);
+        radix_tree_preload_end();
+        return rc;
 }
 
-/*
- * this function is assumed to be called with mmap_sem held
+/**
+ * gmap_fault - resolve a fault on a guest address
+ * @gmap: pointer to guest mapping meta data structure
+ * @gaddr: guest address
+ * @fault_flags: flags to pass down to handle_mm_fault()
+ *
+ * Returns 0 on success, -ENOMEM for out of memory conditions, and -EFAULT
+ * if the vm address is already mapped to a different guest segment.
  */
-unsigned long __gmap_fault(unsigned long address, struct gmap *gmap)
+int gmap_fault(struct gmap *gmap, unsigned long gaddr,
+               unsigned int fault_flags)
 {
-        unsigned long *segment_ptr, segment;
-        struct gmap_pgtable *mp;
-        struct page *page;
+        unsigned long vmaddr;
         int rc;
 
-        current->thread.gmap_addr = address;
-        segment_ptr = gmap_table_walk(address, gmap);
-        if (IS_ERR(segment_ptr))
-                return -EFAULT;
-        /* Convert the gmap address to an mm address. */
-        while (1) {
-                segment = *segment_ptr;
-                if (!(segment & _SEGMENT_ENTRY_INVALID)) {
-                        /* Page table is present */
-                        page = pfn_to_page(segment >> PAGE_SHIFT);
-                        mp = (struct gmap_pgtable *) page->index;
-                        return mp->vmaddr | (address & ~PMD_MASK);
-                }
-                if (!(segment & _SEGMENT_ENTRY_PROTECT))
-                        /* Nothing mapped in the gmap address space. */
-                        break;
-                rc = gmap_connect_pgtable(address, segment, segment_ptr, gmap);
-                if (rc)
-                        return rc;
-        }
-        return -EFAULT;
-}
-
-unsigned long gmap_fault(unsigned long address, struct gmap *gmap)
-{
-        unsigned long rc;
-
         down_read(&gmap->mm->mmap_sem);
-        rc = __gmap_fault(address, gmap);
+        vmaddr = __gmap_translate(gmap, gaddr);
+        if (IS_ERR_VALUE(vmaddr)) {
+                rc = vmaddr;
+                goto out_up;
+        }
+        if (fixup_user_fault(current, gmap->mm, vmaddr, fault_flags)) {
+                rc = -EFAULT;
+                goto out_up;
+        }
+        rc = __gmap_link(gmap, gaddr, vmaddr);
+out_up:
         up_read(&gmap->mm->mmap_sem);
-
         return rc;
 }
 EXPORT_SYMBOL_GPL(gmap_fault);
@@ -617,17 +622,24 @@ static void gmap_zap_swap_entry(swp_entry_t entry, struct mm_struct *mm)
         free_swap_and_cache(entry);
 }
 
-/**
- * The mm->mmap_sem lock must be held
+/*
+ * this function is assumed to be called with mmap_sem held
  */
-static void gmap_zap_unused(struct mm_struct *mm, unsigned long address)
+void __gmap_zap(struct gmap *gmap, unsigned long gaddr)
 {
-        unsigned long ptev, pgstev;
+        unsigned long vmaddr, ptev, pgstev;
+        pte_t *ptep, pte;
         spinlock_t *ptl;
         pgste_t pgste;
-        pte_t *ptep, pte;
 
-        ptep = get_locked_pte(mm, address, &ptl);
+        /* Find the vm address for the guest address */
+        vmaddr = (unsigned long) radix_tree_lookup(&gmap->guest_to_host,
+                                                   gaddr >> PMD_SHIFT);
+        if (!vmaddr)
+                return;
+        vmaddr |= gaddr & ~PMD_MASK;
+        /* Get pointer to the page table entry */
+        ptep = get_locked_pte(gmap->mm, vmaddr, &ptl);
         if (unlikely(!ptep))
                 return;
         pte = *ptep;
@@ -639,87 +651,34 @@ static void gmap_zap_unused(struct mm_struct *mm, unsigned long address)
         ptev = pte_val(pte);
         if (((pgstev & _PGSTE_GPS_USAGE_MASK) == _PGSTE_GPS_USAGE_UNUSED) ||
             ((pgstev & _PGSTE_GPS_ZERO) && (ptev & _PAGE_INVALID))) {
-                gmap_zap_swap_entry(pte_to_swp_entry(pte), mm);
-                pte_clear(mm, address, ptep);
+                gmap_zap_swap_entry(pte_to_swp_entry(pte), gmap->mm);
+                pte_clear(gmap->mm, vmaddr, ptep);
         }
         pgste_set_unlock(ptep, pgste);
 out_pte:
         pte_unmap_unlock(*ptep, ptl);
 }
-
-/*
- * this function is assumed to be called with mmap_sem held
- */
-void __gmap_zap(unsigned long address, struct gmap *gmap)
-{
-        unsigned long *table, *segment_ptr;
-        unsigned long segment, pgstev, ptev;
-        struct gmap_pgtable *mp;
-        struct page *page;
-
-        segment_ptr = gmap_table_walk(address, gmap);
-        if (IS_ERR(segment_ptr))
-                return;
-        segment = *segment_ptr;
-        if (segment & _SEGMENT_ENTRY_INVALID)
-                return;
-        page = pfn_to_page(segment >> PAGE_SHIFT);
-        mp = (struct gmap_pgtable *) page->index;
-        address = mp->vmaddr | (address & ~PMD_MASK);
-        /* Page table is present */
-        table = (unsigned long *)(segment & _SEGMENT_ENTRY_ORIGIN);
-        table = table + ((address >> 12) & 0xff);
-        pgstev = table[PTRS_PER_PTE];
-        ptev = table[0];
-        /* quick check, checked again with locks held */
-        if (((pgstev & _PGSTE_GPS_USAGE_MASK) == _PGSTE_GPS_USAGE_UNUSED) ||
-            ((pgstev & _PGSTE_GPS_ZERO) && (ptev & _PAGE_INVALID)))
-                gmap_zap_unused(gmap->mm, address);
-}
 EXPORT_SYMBOL_GPL(__gmap_zap);
 
-void gmap_discard(unsigned long from, unsigned long to, struct gmap *gmap)
+void gmap_discard(struct gmap *gmap, unsigned long from, unsigned long to)
 {
-
-        unsigned long *table, address, size;
+        unsigned long gaddr, vmaddr, size;
         struct vm_area_struct *vma;
-        struct gmap_pgtable *mp;
-        struct page *page;
 
         down_read(&gmap->mm->mmap_sem);
-        address = from;
-        while (address < to) {
-                /* Walk the gmap address space page table */
-                table = gmap->table + ((address >> 53) & 0x7ff);
-                if (unlikely(*table & _REGION_ENTRY_INVALID)) {
-                        address = (address + PMD_SIZE) & PMD_MASK;
-                        continue;
-                }
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + ((address >> 42) & 0x7ff);
-                if (unlikely(*table & _REGION_ENTRY_INVALID)) {
-                        address = (address + PMD_SIZE) & PMD_MASK;
+        for (gaddr = from; gaddr < to;
+             gaddr = (gaddr + PMD_SIZE) & PMD_MASK) {
+                /* Find the vm address for the guest address */
+                vmaddr = (unsigned long)
+                        radix_tree_lookup(&gmap->guest_to_host,
+                                          gaddr >> PMD_SHIFT);
+                if (!vmaddr)
                         continue;
-                }
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + ((address >> 31) & 0x7ff);
-                if (unlikely(*table & _REGION_ENTRY_INVALID)) {
-                        address = (address + PMD_SIZE) & PMD_MASK;
-                        continue;
-                }
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                table = table + ((address >> 20) & 0x7ff);
-                if (unlikely(*table & _SEGMENT_ENTRY_INVALID)) {
-                        address = (address + PMD_SIZE) & PMD_MASK;
-                        continue;
-                }
-                page = pfn_to_page(*table >> PAGE_SHIFT);
-                mp = (struct gmap_pgtable *) page->index;
-                vma = find_vma(gmap->mm, mp->vmaddr);
-                size = min(to - address, PMD_SIZE - (address & ~PMD_MASK));
-                zap_page_range(vma, mp->vmaddr | (address & ~PMD_MASK),
-                               size, NULL);
-                address = (address + PMD_SIZE) & PMD_MASK;
+                vmaddr |= gaddr & ~PMD_MASK;
+                /* Find vma in the parent mm */
+                vma = find_vma(gmap->mm, vmaddr);
+                size = min(to - gaddr, PMD_SIZE - (gaddr & ~PMD_MASK));
+                zap_page_range(vma, vmaddr, size, NULL);
         }
         up_read(&gmap->mm->mmap_sem);
 }
@@ -755,7 +714,7 @@ EXPORT_SYMBOL_GPL(gmap_unregister_ipte_notifier);
 /**
  * gmap_ipte_notify - mark a range of ptes for invalidation notification
  * @gmap: pointer to guest mapping meta data structure
- * @start: virtual address in the guest address space
+ * @gaddr: virtual address in the guest address space
  * @len: size of area
  *
  * Returns 0 if for each page in the given range a gmap mapping exists and
@@ -763,7 +722,7 @@ EXPORT_SYMBOL_GPL(gmap_unregister_ipte_notifier);
  * for one or more pages -EFAULT is returned. If no memory could be allocated
  * -ENOMEM is returned. This function establishes missing page table entries.
  */
-int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len)
+int gmap_ipte_notify(struct gmap *gmap, unsigned long gaddr, unsigned long len)
 {
         unsigned long addr;
         spinlock_t *ptl;
@@ -771,12 +730,12 @@ int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len)
         pgste_t pgste;
         int rc = 0;
 
-        if ((start & ~PAGE_MASK) || (len & ~PAGE_MASK))
+        if ((gaddr & ~PAGE_MASK) || (len & ~PAGE_MASK))
                 return -EINVAL;
         down_read(&gmap->mm->mmap_sem);
         while (len) {
                 /* Convert gmap address and connect the page tables */
-                addr = __gmap_fault(start, gmap);
+                addr = __gmap_translate(gmap, gaddr);
                 if (IS_ERR_VALUE(addr)) {
                         rc = addr;
                         break;
@@ -786,6 +745,9 @@ int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len)
                         rc = -EFAULT;
                         break;
                 }
+                rc = __gmap_link(gmap, gaddr, addr);
+                if (rc)
+                        break;
                 /* Walk the process page table, lock and get pte pointer */
                 ptep = get_locked_pte(gmap->mm, addr, &ptl);
                 if (unlikely(!ptep))
@@ -796,7 +758,7 @@ int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len)
                         pgste = pgste_get_lock(ptep);
                         pgste_val(pgste) |= PGSTE_IN_BIT;
                         pgste_set_unlock(ptep, pgste);
-                        start += PAGE_SIZE;
+                        gaddr += PAGE_SIZE;
                         len -= PAGE_SIZE;
                 }
                 spin_unlock(ptl);
@@ -809,28 +771,30 @@ EXPORT_SYMBOL_GPL(gmap_ipte_notify);
 /**
  * gmap_do_ipte_notify - call all invalidation callbacks for a specific pte.
  * @mm: pointer to the process mm_struct
+ * @addr: virtual address in the process address space
  * @pte: pointer to the page table entry
  *
  * This function is assumed to be called with the page table lock held
  * for the pte to notify.
  */
-void gmap_do_ipte_notify(struct mm_struct *mm, pte_t *pte)
+void gmap_do_ipte_notify(struct mm_struct *mm, unsigned long vmaddr, pte_t *pte)
 {
-        unsigned long segment_offset;
+        unsigned long offset, gaddr;
+        unsigned long *table;
         struct gmap_notifier *nb;
-        struct gmap_pgtable *mp;
-        struct gmap_rmap *rmap;
-        struct page *page;
+        struct gmap *gmap;
 
-        segment_offset = ((unsigned long) pte) & (255 * sizeof(pte_t));
-        segment_offset = segment_offset * (4096 / sizeof(pte_t));
-        page = pfn_to_page(__pa(pte) >> PAGE_SHIFT);
-        mp = (struct gmap_pgtable *) page->index;
+        offset = ((unsigned long) pte) & (255 * sizeof(pte_t));
+        offset = offset * (4096 / sizeof(pte_t));
         spin_lock(&gmap_notifier_lock);
-        list_for_each_entry(rmap, &mp->mapper, list) {
+        list_for_each_entry(gmap, &mm->context.gmap_list, list) {
+                table = radix_tree_lookup(&gmap->host_to_guest,
+                                          vmaddr >> PMD_SHIFT);
+                if (!table)
+                        continue;
+                gaddr = __gmap_segment_gaddr(table) + offset;
                 list_for_each_entry(nb, &gmap_notifier_list, list)
-                        nb->notifier_call(rmap->gmap,
-                                          rmap->vmaddr + segment_offset);
+                        nb->notifier_call(gmap, gaddr);
         }
         spin_unlock(&gmap_notifier_lock);
 }
@@ -841,29 +805,18 @@ static inline int page_table_with_pgste(struct page *page)
         return atomic_read(&page->_mapcount) == 0;
 }
 
-static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm,
-                                                    unsigned long vmaddr)
+static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm)
 {
         struct page *page;
         unsigned long *table;
-        struct gmap_pgtable *mp;
 
         page = alloc_page(GFP_KERNEL|__GFP_REPEAT);
         if (!page)
                 return NULL;
-        mp = kmalloc(sizeof(*mp), GFP_KERNEL|__GFP_REPEAT);
-        if (!mp) {
-                __free_page(page);
-                return NULL;
-        }
         if (!pgtable_page_ctor(page)) {
-                kfree(mp);
                 __free_page(page);
                 return NULL;
         }
-        mp->vmaddr = vmaddr & PMD_MASK;
-        INIT_LIST_HEAD(&mp->mapper);
-        page->index = (unsigned long) mp;
         atomic_set(&page->_mapcount, 0);
         table = (unsigned long *) page_to_phys(page);
         clear_table(table, _PAGE_INVALID, PAGE_SIZE/2);
@@ -874,14 +827,10 @@ static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm,
 static inline void page_table_free_pgste(unsigned long *table)
 {
         struct page *page;
-        struct gmap_pgtable *mp;
 
         page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
-        mp = (struct gmap_pgtable *) page->index;
-        BUG_ON(!list_empty(&mp->mapper));
         pgtable_page_dtor(page);
         atomic_set(&page->_mapcount, -1);
-        kfree(mp);
         __free_page(page);
 }
 
@@ -986,11 +935,21 @@ int set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
         pte_t *ptep;
 
         down_read(&mm->mmap_sem);
+retry:
         ptep = get_locked_pte(current->mm, addr, &ptl);
         if (unlikely(!ptep)) {
                 up_read(&mm->mmap_sem);
                 return -EFAULT;
         }
+        if (!(pte_val(*ptep) & _PAGE_INVALID) &&
+             (pte_val(*ptep) & _PAGE_PROTECT)) {
+                pte_unmap_unlock(*ptep, ptl);
+                if (fixup_user_fault(current, mm, addr, FAULT_FLAG_WRITE)) {
+                        up_read(&mm->mmap_sem);
+                        return -EFAULT;
+                }
+                goto retry;
+        }
 
         new = old = pgste_get_lock(ptep);
         pgste_val(new) &= ~(PGSTE_GR_BIT | PGSTE_GC_BIT |
@@ -1028,8 +987,7 @@ static inline int page_table_with_pgste(struct page *page)
         return 0;
 }
 
-static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm,
-                                                    unsigned long vmaddr)
+static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm)
 {
         return NULL;
 }
@@ -1043,8 +1001,8 @@ static inline void page_table_free_pgste(unsigned long *table)
 {
 }
 
-static inline void gmap_disconnect_pgtable(struct mm_struct *mm,
-                                           unsigned long *table)
+static inline void gmap_unlink(struct mm_struct *mm, unsigned long *table,
+                        unsigned long vmaddr)
 {
 }
 
@@ -1064,14 +1022,14 @@ static inline unsigned int atomic_xor_bits(atomic_t *v, unsigned int bits)
 /*
  * page table entry allocation/free routines.
  */
-unsigned long *page_table_alloc(struct mm_struct *mm, unsigned long vmaddr)
+unsigned long *page_table_alloc(struct mm_struct *mm)
 {
         unsigned long *uninitialized_var(table);
         struct page *uninitialized_var(page);
         unsigned int mask, bit;
 
         if (mm_has_pgste(mm))
-                return page_table_alloc_pgste(mm, vmaddr);
+                return page_table_alloc_pgste(mm);
         /* Allocate fragments of a 4K page as 1K/2K page table */
         spin_lock_bh(&mm->context.list_lock);
         mask = FRAG_MASK;
@@ -1113,10 +1071,8 @@ void page_table_free(struct mm_struct *mm, unsigned long *table)
         unsigned int bit, mask;
 
         page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
-        if (page_table_with_pgste(page)) {
-                gmap_disconnect_pgtable(mm, table);
+        if (page_table_with_pgste(page))
                 return page_table_free_pgste(table);
-        }
         /* Free 1K/2K page table fragment of a 4K page */
         bit = 1 << ((__pa(table) & ~PAGE_MASK)/(PTRS_PER_PTE*sizeof(pte_t)));
         spin_lock_bh(&mm->context.list_lock);
@@ -1148,7 +1104,8 @@ static void __page_table_free_rcu(void *table, unsigned bit)
         }
 }
 
-void page_table_free_rcu(struct mmu_gather *tlb, unsigned long *table)
+void page_table_free_rcu(struct mmu_gather *tlb, unsigned long *table,
+                         unsigned long vmaddr)
 {
         struct mm_struct *mm;
         struct page *page;
@@ -1157,7 +1114,7 @@ void page_table_free_rcu(struct mmu_gather *tlb, unsigned long *table)
         mm = tlb->mm;
         page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
         if (page_table_with_pgste(page)) {
-                gmap_disconnect_pgtable(mm, table);
+                gmap_unlink(mm, table, vmaddr);
                 table = (unsigned long *) (__pa(table) | FRAG_MASK);
                 tlb_remove_table(tlb, table);
                 return;
@@ -1293,7 +1250,7 @@ again:
                 if (page_table_with_pgste(page))
                         continue;
                 /* Allocate new page table with pgstes */
-                new = page_table_alloc_pgste(mm, addr);
+                new = page_table_alloc_pgste(mm);
                 if (!new)
                         return -ENOMEM;
 
@@ -1308,7 +1265,7 @@ again:
                         /* Establish new table */
                         pmd_populate(mm, pmd, (pte_t *) new);
                         /* Free old table with rcu, there might be a walker! */
-                        page_table_free_rcu(tlb, table);
+                        page_table_free_rcu(tlb, table, addr);
                         new = NULL;
                 }
                 spin_unlock(ptl);
diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
index fe9012a49aa5..fdbd7888cb07 100644
--- a/arch/s390/mm/vmem.c
+++ b/arch/s390/mm/vmem.c
@@ -65,7 +65,7 @@ static pte_t __ref *vmem_pte_alloc(unsigned long address)
         pte_t *pte;
 
         if (slab_is_available())
-                pte = (pte_t *) page_table_alloc(&init_mm, address);
+                pte = (pte_t *) page_table_alloc(&init_mm);
         else
                 pte = alloc_bootmem_align(PTRS_PER_PTE * sizeof(pte_t),
                                           PTRS_PER_PTE * sizeof(pte_t));
diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c
index 61e45b7c04d7..c52ac77408ca 100644
--- a/arch/s390/net/bpf_jit_comp.c
+++ b/arch/s390/net/bpf_jit_comp.c
@@ -5,11 +5,9 @@
  *
  * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
  */
-#include <linux/moduleloader.h>
 #include <linux/netdevice.h>
 #include <linux/if_vlan.h>
 #include <linux/filter.h>
-#include <linux/random.h>
 #include <linux/init.h>
 #include <asm/cacheflush.h>
 #include <asm/facility.h>
@@ -148,6 +146,12 @@ struct bpf_jit {
         ret;                                            \
 })
 
+static void bpf_jit_fill_hole(void *area, unsigned int size)
+{
+        /* Fill whole space with illegal instructions */
+        memset(area, 0, size);
+}
+
 static void bpf_jit_prologue(struct bpf_jit *jit)
 {
         /* Save registers and create stack frame if necessary */
@@ -223,37 +227,6 @@ static void bpf_jit_epilogue(struct bpf_jit *jit)
         EMIT2(0x07fe);
 }
 
-/* Helper to find the offset of pkt_type in sk_buff
- * Make sure its still a 3bit field starting at the MSBs within a byte.
- */
-#define PKT_TYPE_MAX 0xe0
-static int pkt_type_offset;
-
-static int __init bpf_pkt_type_offset_init(void)
-{
-        struct sk_buff skb_probe = {
-                .pkt_type = ~0,
-        };
-        char *ct = (char *)&skb_probe;
-        int off;
-
-        pkt_type_offset = -1;
-        for (off = 0; off < sizeof(struct sk_buff); off++) {
-                if (!ct[off])
-                        continue;
-                if (ct[off] == PKT_TYPE_MAX)
-                        pkt_type_offset = off;
-                else {
-                        /* Found non matching bit pattern, fix needed. */
-                        WARN_ON_ONCE(1);
-                        pkt_type_offset = -1;
-                        return -1;
-                }
-        }
-        return 0;
-}
-device_initcall(bpf_pkt_type_offset_init);
-
 /*
  * make sure we dont leak kernel information to user
  */
@@ -753,12 +726,10 @@ call_fn:	/* lg %r1,<d(function)>(%r13) */
                 }
                 break;
         case BPF_ANC | SKF_AD_PKTTYPE:
-                if (pkt_type_offset < 0)
-                        goto out;
                 /* lhi %r5,0 */
                 EMIT4(0xa7580000);
                 /* ic %r5,<d(pkt_type_offset)>(%r2) */
-                EMIT4_DISP(0x43502000, pkt_type_offset);
+                EMIT4_DISP(0x43502000, PKT_TYPE_OFFSET());
                 /* srl %r5,5 */
                 EMIT4_DISP(0x88500000, 5);
                 break;
@@ -780,38 +751,6 @@ out:
         return -1;
 }
 
-/*
- * Note: for security reasons, bpf code will follow a randomly
- *       sized amount of illegal instructions.
- */
-struct bpf_binary_header {
-        unsigned int pages;
-        u8 image[];
-};
-
-static struct bpf_binary_header *bpf_alloc_binary(unsigned int bpfsize,
-                                                  u8 **image_ptr)
-{
-        struct bpf_binary_header *header;
-        unsigned int sz, hole;
-
-        /* Most BPF filters are really small, but if some of them fill a page,
-         * allow at least 128 extra bytes for illegal instructions.
-         */
-        sz = round_up(bpfsize + sizeof(*header) + 128, PAGE_SIZE);
-        header = module_alloc(sz);
-        if (!header)
-                return NULL;
-        memset(header, 0, sz);
-        header->pages = sz / PAGE_SIZE;
-        hole = min(sz - (bpfsize + sizeof(*header)), PAGE_SIZE - sizeof(*header));
-        /* Insert random number of illegal instructions before BPF code
-         * and make sure the first instruction starts at an even address.
-         */
-        *image_ptr = &header->image[(prandom_u32() % hole) & -2];
-        return header;
-}
-
 void bpf_jit_compile(struct bpf_prog *fp)
 {
         struct bpf_binary_header *header = NULL;
@@ -850,7 +789,8 @@ void bpf_jit_compile(struct bpf_prog *fp)
                         size = prg_len + lit_len;
                         if (size >= BPF_SIZE_MAX)
                                 goto out;
-                        header = bpf_alloc_binary(size, &jit.start);
+                        header = bpf_jit_binary_alloc(size, &jit.start,
+                                                      2, bpf_jit_fill_hole);
                         if (!header)
                                 goto out;
                         jit.prg = jit.mid = jit.start + prg_len;
@@ -869,7 +809,7 @@ void bpf_jit_compile(struct bpf_prog *fp)
         if (jit.start) {
                 set_memory_ro((unsigned long)header, header->pages);
                 fp->bpf_func = (void *) jit.start;
-                fp->jited = 1;
+                fp->jited = true;
         }
 out:
         kfree(addrs);
@@ -884,8 +824,8 @@ void bpf_jit_free(struct bpf_prog *fp)
                 goto free_filter;
 
         set_memory_rw(addr, header->pages);
-        module_free(NULL, header);
+        bpf_jit_binary_free(header);
 
 free_filter:
-        kfree(fp);
+        bpf_prog_unlock_free(fp);
 }
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 4ac8cae5727c..366e1b599a7b 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -22,17 +22,14 @@ choice
 config ARCH_SCORE7
         bool "SCORE7 processor"
         select SYS_SUPPORTS_32BIT_KERNEL
-        select GENERIC_HAS_IOMAP
 
 config MACH_SPCT6600
         bool "SPCT6600 series based machines"
         select SYS_SUPPORTS_32BIT_KERNEL
-        select GENERIC_HAS_IOMAP
 
 config SCORE_SIM
         bool "Score simulator"
         select SYS_SUPPORTS_32BIT_KERNEL
-        select GENERIC_HAS_IOMAP
 endchoice
 
 endmenu
diff --git a/arch/score/include/asm/Kbuild b/arch/score/include/asm/Kbuild
index aad209199f7e..46461c19f284 100644
--- a/arch/score/include/asm/Kbuild
+++ b/arch/score/include/asm/Kbuild
@@ -6,8 +6,11 @@ generic-y += barrier.h
 generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += hash.h
+generic-y += irq_work.h
 generic-y += mcs_spinlock.h
 generic-y += preempt.h
 generic-y += scatterlist.h
+generic-y += sections.h
 generic-y += trace_clock.h
 generic-y += xor.h
+generic-y += serial.h
diff --git a/arch/score/include/asm/sections.h b/arch/score/include/asm/sections.h
deleted file mode 100644
index 9441d23af005..000000000000
--- a/arch/score/include/asm/sections.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_SCORE_SECTIONS_H
-#define _ASM_SCORE_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif /* _ASM_SCORE_SECTIONS_H */
diff --git a/arch/score/kernel/time.c b/arch/score/kernel/time.c
index f0a43affb201..24770cd9b473 100644
--- a/arch/score/kernel/time.c
+++ b/arch/score/kernel/time.c
@@ -41,7 +41,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction timer_irq = {
         .handler = timer_interrupt,
-        .flags = IRQF_DISABLED | IRQF_TIMER,
+        .flags = IRQF_TIMER,
         .name = "timer",
 };
 
diff --git a/arch/score/lib/checksum_copy.c b/arch/score/lib/checksum_copy.c
index 04565dd3ded8..9b770b30e8a5 100644
--- a/arch/score/lib/checksum_copy.c
+++ b/arch/score/lib/checksum_copy.c
@@ -50,3 +50,4 @@ unsigned int csum_partial_copy_from_user(const char *src, char *dst,
 
         return csum_partial(dst, len, sum);
 }
+EXPORT_SYMBOL(csum_partial_copy_from_user);
diff --git a/arch/score/mm/cache.c b/arch/score/mm/cache.c
index f85ec1a7c88e..b4bcfd3e8393 100644
--- a/arch/score/mm/cache.c
+++ b/arch/score/mm/cache.c
@@ -72,6 +72,7 @@ void flush_dcache_page(struct page *page)
         addr = (unsigned long) page_address(page);
         flush_data_cache_page(addr);
 }
+EXPORT_SYMBOL(flush_dcache_page);
 
 /* called by update_mmu_cache. */
 void __update_cache(struct vm_area_struct *vma, unsigned long address,
@@ -277,3 +278,4 @@ void flush_icache_range(unsigned long start, unsigned long end)
                 start += L1_CACHE_BYTES;
         }
 }
+EXPORT_SYMBOL(flush_icache_range);
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 453fa5c09550..244fb4c81e25 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -172,6 +172,7 @@ menu "System type"
 #
 config CPU_SH2
         bool
+        select SH_INTC
 
 config CPU_SH2A
         bool
@@ -182,6 +183,7 @@ config CPU_SH3
         bool
         select CPU_HAS_INTEVT
         select CPU_HAS_SR_RB
+        select SH_INTC
         select SYS_SUPPORTS_SH_TMU
 
 config CPU_SH4
@@ -189,6 +191,7 @@ config CPU_SH4
         select CPU_HAS_INTEVT
         select CPU_HAS_SR_RB
         select CPU_HAS_FPU if !CPU_SH4AL_DSP
+        select SH_INTC
         select SYS_SUPPORTS_SH_TMU
         select SYS_SUPPORTS_HUGETLBFS if MMU
 
@@ -595,8 +598,6 @@ source kernel/Kconfig.hz
 config KEXEC
         bool "kexec system call (EXPERIMENTAL)"
         depends on SUPERH32 && MMU
-        select CRYPTO
-        select CRYPTO_SHA256
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c
index 3ea65e9b56e8..f035a7ac6456 100644
--- a/arch/sh/boards/mach-x3proto/gpio.c
+++ b/arch/sh/boards/mach-x3proto/gpio.c
@@ -128,10 +128,8 @@ int __init x3proto_gpio_setup(void)
         return 0;
 
 err_irq:
-        ret = gpiochip_remove(&x3proto_gpio_chip);
-        if (unlikely(ret))
-                pr_err("Failed deregistering GPIO\n");
-
+        gpiochip_remove(&x3proto_gpio_chip);
+        ret = 0;
 err_gpio:
         synchronize_irq(ilsel);
 
diff --git a/arch/sh/configs/sdk7780_defconfig b/arch/sh/configs/sdk7780_defconfig
index 6a96b9a2f7a5..bbd4c2298708 100644
--- a/arch/sh/configs/sdk7780_defconfig
+++ b/arch/sh/configs/sdk7780_defconfig
@@ -30,6 +30,7 @@ CONFIG_PCI_DEBUG=y
 CONFIG_PCCARD=y
 CONFIG_YENTA=y
 CONFIG_HOTPLUG_PCI=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig
index e741b1e36acd..df25ae774ee0 100644
--- a/arch/sh/configs/sh2007_defconfig
+++ b/arch/sh/configs/sh2007_defconfig
@@ -25,6 +25,7 @@ CONFIG_CMDLINE_OVERWRITE=y
 CONFIG_CMDLINE="console=ttySC1,115200 ip=dhcp root=/dev/nfs rw nfsroot=/nfs/rootfs,rsize=1024,wsize=1024 earlyprintk=sh-sci.1"
 CONFIG_PCCARD=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=y
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
index c19e47dacb31..5a6c9acff0d2 100644
--- a/arch/sh/include/asm/Kbuild
+++ b/arch/sh/include/asm/Kbuild
@@ -12,6 +12,7 @@ generic-y += hash.h
 generic-y += ioctl.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kvm_para.h
 generic-y += local.h
 generic-y += local64.h
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index 1b6199740e98..7a99e6af6372 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -3,7 +3,6 @@
 
 #include <asm-generic/sections.h>
 
-extern long __nosave_begin, __nosave_end;
 extern long __machvec_start, __machvec_end;
 extern char __uncached_start, __uncached_end;
 extern char __start_eh_frame[], __stop_eh_frame[];
diff --git a/arch/sh/include/uapi/asm/ioctls.h b/arch/sh/include/uapi/asm/ioctls.h
index 342241079760..c9903e56ccf4 100644
--- a/arch/sh/include/uapi/asm/ioctls.h
+++ b/arch/sh/include/uapi/asm/ioctls.h
@@ -83,6 +83,8 @@
 #define TCSETS2         _IOW('T', 43, struct termios2)
 #define TCSETSW2        _IOW('T', 44, struct termios2)
 #define TCSETSF2        _IOW('T', 45, struct termios2)
+#define TIOCGRS485      _IOR('T', 46, struct serial_rs485)
+#define TIOCSRS485      _IOWR('T', 47, struct serial_rs485)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
 #define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 097c2cdd117f..f770e3992620 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -229,6 +229,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
 
         cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
 }
+EXPORT_SYMBOL(flush_icache_range);
 
 void flush_icache_page(struct vm_area_struct *vma, struct page *page)
 {
diff --git a/arch/sh/mm/gup.c b/arch/sh/mm/gup.c
index bf8daf9d9c9b..37458f38b220 100644
--- a/arch/sh/mm/gup.c
+++ b/arch/sh/mm/gup.c
@@ -105,6 +105,8 @@ static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
                 VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
                 page = pte_page(pte);
                 get_page(page);
+                __flush_anon_page(page, addr);
+                flush_dcache_page(page);
                 pages[*nr] = page;
                 (*nr)++;
 
diff --git a/arch/sparc/configs/sparc64_defconfig b/arch/sparc/configs/sparc64_defconfig
index 9d8521b8c854..6b68f12f29db 100644
--- a/arch/sparc/configs/sparc64_defconfig
+++ b/arch/sparc/configs/sparc64_defconfig
@@ -29,6 +29,7 @@ CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_SUN_OPENPROMFS=m
 CONFIG_BINFMT_MISC=m
+CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_XFRM_USER=m
diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild
index cdd1b447bb6c..f5f94ce1692c 100644
--- a/arch/sparc/include/asm/Kbuild
+++ b/arch/sparc/include/asm/Kbuild
@@ -8,6 +8,7 @@ generic-y += emergency-restart.h
 generic-y += exec.h
 generic-y += hash.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += linkage.h
 generic-y += local.h
 generic-y += local64.h
diff --git a/arch/sparc/include/asm/vio.h b/arch/sparc/include/asm/vio.h
index e0f6c399f1d0..6b135a8ab07b 100644
--- a/arch/sparc/include/asm/vio.h
+++ b/arch/sparc/include/asm/vio.h
@@ -65,6 +65,7 @@ struct vio_dring_register {
         u16                     options;
 #define VIO_TX_DRING            0x0001
 #define VIO_RX_DRING            0x0002
+#define VIO_RX_DRING_DATA       0x0004
         u16                     resv;
         u32                     num_cookies;
         struct ldc_trans_cookie cookies[0];
@@ -80,6 +81,8 @@ struct vio_dring_unregister {
 #define VIO_PKT_MODE            0x01 /* Packet based transfer   */
 #define VIO_DESC_MODE           0x02 /* In-band descriptors     */
 #define VIO_DRING_MODE          0x03 /* Descriptor rings        */
+/* in vers >= 1.2, VIO_DRING_MODE is 0x04 and transfer mode is a bitmask */
+#define VIO_NEW_DRING_MODE      0x04
 
 struct vio_dring_data {
         struct vio_msg_tag      tag;
@@ -205,10 +208,20 @@ struct vio_net_attr_info {
         u8                      addr_type;
 #define VNET_ADDR_ETHERMAC      0x01
         u16                     ack_freq;
-        u32                     resv1;
+        u8                      plnk_updt;
+#define PHYSLINK_UPDATE_NONE            0x00
+#define PHYSLINK_UPDATE_STATE           0x01
+#define PHYSLINK_UPDATE_STATE_ACK       0x02
+#define PHYSLINK_UPDATE_STATE_NACK      0x03
+        u8                      options;
+        u16                     resv1;
         u64                     addr;
         u64                     mtu;
-        u64                     resv2[3];
+        u16                     cflags;
+#define VNET_LSO_IPV4_CAPAB             0x0001
+        u16                     ipv4_lso_maxlen;
+        u32                     resv2;
+        u64                     resv3[2];
 };
 
 #define VNET_NUM_MCAST          7
@@ -366,6 +379,33 @@ struct vio_driver_state {
         struct vio_driver_ops   *ops;
 };
 
+static inline bool vio_version_before(struct vio_driver_state *vio,
+                                      u16 major, u16 minor)
+{
+        u32 have = (u32)vio->ver.major << 16 | vio->ver.minor;
+        u32 want = (u32)major << 16 | minor;
+
+        return have < want;
+}
+
+static inline bool vio_version_after(struct vio_driver_state *vio,
+                                      u16 major, u16 minor)
+{
+        u32 have = (u32)vio->ver.major << 16 | vio->ver.minor;
+        u32 want = (u32)major << 16 | minor;
+
+        return have > want;
+}
+
+static inline bool vio_version_after_eq(struct vio_driver_state *vio,
+                                        u16 major, u16 minor)
+{
+        u32 have = (u32)vio->ver.major << 16 | vio->ver.minor;
+        u32 want = (u32)major << 16 | minor;
+
+        return have >= want;
+}
+
 #define viodbg(TYPE, f, a...) \
 do {    if (vio->debug & VIO_DEBUG_##TYPE) \
                 printk(KERN_INFO "vio: ID[%lu] " f, \
diff --git a/arch/sparc/include/uapi/asm/ioctls.h b/arch/sparc/include/uapi/asm/ioctls.h
index 897d1723fa14..06b3f6c3bb9a 100644
--- a/arch/sparc/include/uapi/asm/ioctls.h
+++ b/arch/sparc/include/uapi/asm/ioctls.h
@@ -24,6 +24,8 @@
 #define TIOCGPKT        _IOR('T', 0x38, int) /* Get packet mode state */
 #define TIOCGPTLCK      _IOR('T', 0x39, int) /* Get Pty lock state */
 #define TIOCGEXCL       _IOR('T', 0x40, int) /* Get exclusive mode state */
+#define TIOCGRS485      _IOR('T', 0x41, struct serial_rs485)
+#define TIOCSRS485      _IOWR('T', 0x42, struct serial_rs485)
 
 /* Note that all the ioctls that are not available in Linux have a 
  * double underscore on the front to: a) avoid some programs to
diff --git a/arch/sparc/kernel/ldc.c b/arch/sparc/kernel/ldc.c
index 66dacd56bb10..0af28b984695 100644
--- a/arch/sparc/kernel/ldc.c
+++ b/arch/sparc/kernel/ldc.c
@@ -2159,7 +2159,7 @@ int ldc_map_single(struct ldc_channel *lp,
         state.pte_idx = (base - iommu->page_table);
         state.nc = 0;
         fill_cookies(&state, (pa & PAGE_MASK), (pa & ~PAGE_MASK), len);
-        BUG_ON(state.nc != 1);
+        BUG_ON(state.nc > ncookies);
 
         return state.nc;
 }
diff --git a/arch/sparc/kernel/viohs.c b/arch/sparc/kernel/viohs.c
index f8e7dd53e1c7..7ef081a185b1 100644
--- a/arch/sparc/kernel/viohs.c
+++ b/arch/sparc/kernel/viohs.c
@@ -426,6 +426,13 @@ static int process_dreg_info(struct vio_driver_state *vio,
         if (vio->dr_state & VIO_DR_STATE_RXREG)
                 goto send_nack;
 
+        /* v1.6 and higher, ACK with desired, supported mode, or NACK */
+        if (vio_version_after_eq(vio, 1, 6)) {
+                if (!(pkt->options & VIO_TX_DRING))
+                        goto send_nack;
+                pkt->options = VIO_TX_DRING;
+        }
+
         BUG_ON(vio->desc_buf);
 
         vio->desc_buf = kzalloc(pkt->descr_size, GFP_ATOMIC);
@@ -453,8 +460,11 @@ static int process_dreg_info(struct vio_driver_state *vio,
         pkt->tag.stype = VIO_SUBTYPE_ACK;
         pkt->dring_ident = ++dr->ident;
 
-        viodbg(HS, "SEND DRING_REG ACK ident[%llx]\n",
-               (unsigned long long) pkt->dring_ident);
+        viodbg(HS, "SEND DRING_REG ACK ident[%llx] "
+               "ndesc[%u] dsz[%u] opt[0x%x] ncookies[%u]\n",
+               (unsigned long long) pkt->dring_ident,
+               pkt->num_descr, pkt->descr_size, pkt->options,
+               pkt->num_cookies);
 
         len = (sizeof(*pkt) +
                (dr->ncookies * sizeof(struct ldc_trans_cookie)));
diff --git a/arch/sparc/net/bpf_jit_asm.S b/arch/sparc/net/bpf_jit_asm.S
index 9d016c7017f7..8c83f4b8eb15 100644
--- a/arch/sparc/net/bpf_jit_asm.S
+++ b/arch/sparc/net/bpf_jit_asm.S
@@ -6,10 +6,12 @@
 #define SAVE_SZ         176
 #define SCRATCH_OFF     STACK_BIAS + 128
 #define BE_PTR(label)   be,pn %xcc, label
+#define SIGN_EXTEND(reg)        sra reg, 0, reg
 #else
 #define SAVE_SZ         96
 #define SCRATCH_OFF     72
 #define BE_PTR(label)   be label
+#define SIGN_EXTEND(reg)
 #endif
 
 #define SKF_MAX_NEG_OFF (-0x200000) /* SKF_LL_OFF from filter.h */
@@ -135,6 +137,7 @@ bpf_slow_path_byte_msh:
         save    %sp, -SAVE_SZ, %sp;                     \
         mov     %i0, %o0;                               \
         mov     r_OFF, %o1;                             \
+        SIGN_EXTEND(%o1);                               \
         call    bpf_internal_load_pointer_neg_helper;   \
          mov    (LEN), %o2;                             \
         mov     %o0, r_TMP;                             \
diff --git a/arch/sparc/net/bpf_jit_comp.c b/arch/sparc/net/bpf_jit_comp.c
index 1f76c22a6a75..f33e7c7a3bf7 100644
--- a/arch/sparc/net/bpf_jit_comp.c
+++ b/arch/sparc/net/bpf_jit_comp.c
@@ -184,7 +184,7 @@ do {								\
          */
 #define emit_alu_K(OPCODE, K)                                   \
 do {                                                            \
-        if (K) {                                                \
+        if (K || OPCODE == AND || OPCODE == MUL) {              \
                 unsigned int _insn = OPCODE;                    \
                 _insn |= RS1(r_A) | RD(r_A);                    \
                 if (is_simm13(K)) {                             \
@@ -234,12 +234,18 @@ do {	BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u8));	\
         __emit_load8(BASE, STRUCT, FIELD, DEST);                        \
 } while (0)
 
-#define emit_ldmem(OFF, DEST)                                   \
-do {    *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(DEST);     \
+#ifdef CONFIG_SPARC64
+#define BIAS (STACK_BIAS - 4)
+#else
+#define BIAS (-4)
+#endif
+
+#define emit_ldmem(OFF, DEST)                                           \
+do {    *prog++ = LD32I | RS1(SP) | S13(BIAS - (OFF)) | RD(DEST);       \
 } while (0)
 
-#define emit_stmem(OFF, SRC)                                    \
-do {    *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(SRC);      \
+#define emit_stmem(OFF, SRC)                                            \
+do {    *prog++ = ST32I | RS1(SP) | S13(BIAS - (OFF)) | RD(SRC);        \
 } while (0)
 
 #ifdef CONFIG_SMP
@@ -579,16 +585,11 @@ void bpf_jit_compile(struct bpf_prog *fp)
                         case BPF_ANC | SKF_AD_PROTOCOL:
                                 emit_skb_load16(protocol, r_A);
                                 break;
-#if 0
-                                /* GCC won't let us take the address of
-                                 * a bit field even though we very much
-                                 * know what we are doing here.
-                                 */
                         case BPF_ANC | SKF_AD_PKTTYPE:
-                                __emit_skb_load8(pkt_type, r_A);
+                                __emit_skb_load8(__pkt_type_offset, r_A);
+                                emit_andi(r_A, PKT_TYPE_MAX, r_A);
                                 emit_alu_K(SRL, 5);
                                 break;
-#endif
                         case BPF_ANC | SKF_AD_IFINDEX:
                                 emit_skb_loadptr(dev, r_A);
                                 emit_cmpi(r_A, 0);
@@ -615,14 +616,20 @@ void bpf_jit_compile(struct bpf_prog *fp)
                         case BPF_ANC | SKF_AD_VLAN_TAG:
                         case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
                                 emit_skb_load16(vlan_tci, r_A);
-                                if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) {
-                                        emit_andi(r_A, VLAN_VID_MASK, r_A);
+                                if (code != (BPF_ANC | SKF_AD_VLAN_TAG)) {
+                                        emit_alu_K(SRL, 12);
+                                        emit_andi(r_A, 1, r_A);
                                 } else {
-                                        emit_loadimm(VLAN_TAG_PRESENT, r_TMP);
+                                        emit_loadimm(~VLAN_TAG_PRESENT, r_TMP);
                                         emit_and(r_A, r_TMP, r_A);
                                 }
                                 break;
-
+                        case BPF_LD | BPF_W | BPF_LEN:
+                                emit_skb_load32(len, r_A);
+                                break;
+                        case BPF_LDX | BPF_W | BPF_LEN:
+                                emit_skb_load32(len, r_X);
+                                break;
                         case BPF_LD | BPF_IMM:
                                 emit_loadimm(K, r_A);
                                 break;
@@ -630,15 +637,19 @@ void bpf_jit_compile(struct bpf_prog *fp)
                                 emit_loadimm(K, r_X);
                                 break;
                         case BPF_LD | BPF_MEM:
+                                seen |= SEEN_MEM;
                                 emit_ldmem(K * 4, r_A);
                                 break;
                         case BPF_LDX | BPF_MEM:
+                                seen |= SEEN_MEM | SEEN_XREG;
                                 emit_ldmem(K * 4, r_X);
                                 break;
                         case BPF_ST:
+                                seen |= SEEN_MEM;
                                 emit_stmem(K * 4, r_A);
                                 break;
                         case BPF_STX:
+                                seen |= SEEN_MEM | SEEN_XREG;
                                 emit_stmem(K * 4, r_X);
                                 break;
 
@@ -801,7 +812,7 @@ cond_branch:			f_offset = addrs[i + filter[i].jf];
         if (image) {
                 bpf_flush_icache(image, image + proglen);
                 fp->bpf_func = (void *)image;
-                fp->jited = 1;
+                fp->jited = true;
         }
 out:
         kfree(addrs);
@@ -812,5 +823,6 @@ void bpf_jit_free(struct bpf_prog *fp)
 {
         if (fp->jited)
                 module_free(NULL, fp->bpf_func);
-        kfree(fp);
+
+        bpf_prog_unlock_free(fp);
 }
diff --git a/arch/sparc/power/hibernate.c b/arch/sparc/power/hibernate.c
index 42b0b8ce699a..17bd2e167e07 100644
--- a/arch/sparc/power/hibernate.c
+++ b/arch/sparc/power/hibernate.c
@@ -9,11 +9,9 @@
 #include <asm/hibernate.h>
 #include <asm/visasm.h>
 #include <asm/page.h>
+#include <asm/sections.h>
 #include <asm/tlb.h>
 
-/* References to section boundaries */
-extern const void __nosave_begin, __nosave_end;
-
 struct saved_context saved_context;
 
 /*
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index a3ffe2dd4832..7cca41842a9e 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -134,6 +134,7 @@ config TILEGX
         select HAVE_KPROBES
         select HAVE_KRETPROBES
         select HAVE_ARCH_KGDB
+        select ARCH_SUPPORTS_ATOMIC_RMW
 
 config TILEPRO
         def_bool !TILEGX
@@ -191,8 +192,6 @@ source "kernel/Kconfig.hz"
 
 config KEXEC
         bool "kexec system call"
-        select CRYPTO
-        select CRYPTO_SHA256
         ---help---
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/tile/gxio/mpipe.c b/arch/tile/gxio/mpipe.c
index 5301a9ffbae1..320ff5e6e61e 100644
--- a/arch/tile/gxio/mpipe.c
+++ b/arch/tile/gxio/mpipe.c
@@ -29,6 +29,32 @@
 /* HACK: Avoid pointless "shadow" warnings. */
 #define link link_shadow
 
+/**
+ * strscpy - Copy a C-string into a sized buffer, but only if it fits
+ * @dest: Where to copy the string to
+ * @src: Where to copy the string from
+ * @size: size of destination buffer
+ *
+ * Use this routine to avoid copying too-long strings.
+ * The routine returns the total number of bytes copied
+ * (including the trailing NUL) or zero if the buffer wasn't
+ * big enough.  To ensure that programmers pay attention
+ * to the return code, the destination has a single NUL
+ * written at the front (if size is non-zero) when the
+ * buffer is not big enough.
+ */
+static size_t strscpy(char *dest, const char *src, size_t size)
+{
+        size_t len = strnlen(src, size) + 1;
+        if (len > size) {
+                if (size)
+                        dest[0] = '\0';
+                return 0;
+        }
+        memcpy(dest, src, len);
+        return len;
+}
+
 int gxio_mpipe_init(gxio_mpipe_context_t *context, unsigned int mpipe_index)
 {
         char file[32];
@@ -511,8 +537,8 @@ int gxio_mpipe_link_instance(const char *link_name)
         if (!context)
                 return GXIO_ERR_NO_DEVICE;
 
-        strncpy(name.name, link_name, sizeof(name.name));
-        name.name[GXIO_MPIPE_LINK_NAME_LEN - 1] = '\0';
+        if (strscpy(name.name, link_name, sizeof(name.name)) == 0)
+                return GXIO_ERR_NO_DEVICE;
 
         return gxio_mpipe_info_instance_aux(context, name);
 }
@@ -529,7 +555,8 @@ int gxio_mpipe_link_enumerate_mac(int idx, char *link_name, uint8_t *link_mac)
 
         rv = gxio_mpipe_info_enumerate_aux(context, idx, &name, &mac);
         if (rv >= 0) {
-                strncpy(link_name, name.name, sizeof(name.name));
+                if (strscpy(link_name, name.name, sizeof(name.name)) == 0)
+                        return GXIO_ERR_INVAL_MEMORY_SIZE;
                 memcpy(link_mac, mac.mac, sizeof(mac.mac));
         }
 
@@ -545,8 +572,8 @@ int gxio_mpipe_link_open(gxio_mpipe_link_t *link,
         _gxio_mpipe_link_name_t name;
         int rv;
 
-        strncpy(name.name, link_name, sizeof(name.name));
-        name.name[GXIO_MPIPE_LINK_NAME_LEN - 1] = '\0';
+        if (strscpy(name.name, link_name, sizeof(name.name)) == 0)
+                return GXIO_ERR_NO_DEVICE;
 
         rv = gxio_mpipe_link_open_aux(context, name, flags);
         if (rv < 0)
diff --git a/arch/tile/include/asm/Kbuild b/arch/tile/include/asm/Kbuild
index 0aa5675e7025..e6462b8a6284 100644
--- a/arch/tile/include/asm/Kbuild
+++ b/arch/tile/include/asm/Kbuild
@@ -17,6 +17,7 @@ generic-y += ioctl.h
 generic-y += ioctls.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += local.h
 generic-y += local64.h
 generic-y += mcs_spinlock.h
diff --git a/arch/tile/include/asm/sections.h b/arch/tile/include/asm/sections.h
index 5d5d3b739a6b..86a746243dc8 100644
--- a/arch/tile/include/asm/sections.h
+++ b/arch/tile/include/asm/sections.h
@@ -19,9 +19,6 @@
 
 #include <asm-generic/sections.h>
 
-/* Text and data are at different areas in the kernel VA space. */
-extern char _sinitdata[], _einitdata[];
-
 /* Write-once data is writable only till the end of initialization. */
 extern char __w1data_begin[], __w1data_end[];
 
diff --git a/arch/tile/include/asm/vdso.h b/arch/tile/include/asm/vdso.h
index 9f6a78d665fa..9b069692153f 100644
--- a/arch/tile/include/asm/vdso.h
+++ b/arch/tile/include/asm/vdso.h
@@ -15,6 +15,7 @@
 #ifndef __TILE_VDSO_H__
 #define __TILE_VDSO_H__
 
+#include <linux/seqlock.h>
 #include <linux/types.h>
 
 /*
@@ -26,15 +27,20 @@
  */
 
 struct vdso_data {
-        __u64 tz_update_count;  /* Timezone atomicity ctr             */
-        __u64 tb_update_count;  /* Timebase atomicity ctr             */
-        __u64 xtime_tod_stamp;  /* TOD clock for xtime                */
-        __u64 xtime_clock_sec;  /* Kernel time second                 */
-        __u64 xtime_clock_nsec; /* Kernel time nanosecond             */
-        __u64 wtom_clock_sec;   /* Wall to monotonic clock second     */
-        __u64 wtom_clock_nsec;  /* Wall to monotonic clock nanosecond */
+        seqcount_t tz_seq;      /* Timezone seqlock                   */
+        seqcount_t tb_seq;      /* Timebase seqlock                   */
+        __u64 cycle_last;       /* TOD clock for xtime                */
+        __u64 mask;             /* Cycle mask                         */
         __u32 mult;             /* Cycle to nanosecond multiplier     */
         __u32 shift;            /* Cycle to nanosecond divisor (power of two) */
+        __u64 wall_time_sec;
+        __u64 wall_time_snsec;
+        __u64 monotonic_time_sec;
+        __u64 monotonic_time_snsec;
+        __u64 wall_time_coarse_sec;
+        __u64 wall_time_coarse_nsec;
+        __u64 monotonic_time_coarse_sec;
+        __u64 monotonic_time_coarse_nsec;
         __u32 tz_minuteswest;   /* Minutes west of Greenwich          */
         __u32 tz_dsttime;       /* Type of dst correction             */
 };
diff --git a/arch/tile/include/uapi/arch/sim_def.h b/arch/tile/include/uapi/arch/sim_def.h
index 4b44a2b6a09a..1c069537ae41 100644
--- a/arch/tile/include/uapi/arch/sim_def.h
+++ b/arch/tile/include/uapi/arch/sim_def.h
@@ -360,19 +360,19 @@
  * @{
  */
 
-/** Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
+/** Use with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
 #define SIM_CHIP_MEMCTL        0x001
 
-/** Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
+/** Use with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
 #define SIM_CHIP_XAUI          0x002
 
-/** Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
+/** Use with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
 #define SIM_CHIP_PCIE          0x004
 
-/** Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
+/** Use with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
 #define SIM_CHIP_MPIPE         0x008
 
-/** Use with with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
+/** Use with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
 #define SIM_CHIP_TRIO          0x010
 
 /** Reference all chip devices. */
diff --git a/arch/tile/kernel/smp.c b/arch/tile/kernel/smp.c
index 01e8ab29f43a..19eaa62d456a 100644
--- a/arch/tile/kernel/smp.c
+++ b/arch/tile/kernel/smp.c
@@ -183,6 +183,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
                 preempt_enable();
         }
 }
+EXPORT_SYMBOL(flush_icache_range);
 
 
 /* Called when smp_send_reschedule() triggers IRQ_RESCHEDULE. */
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
index d8fbc289e680..c1b362277fb7 100644
--- a/arch/tile/kernel/time.c
+++ b/arch/tile/kernel/time.c
@@ -249,33 +249,52 @@ cycles_t ns2cycles(unsigned long nsecs)
 
 void update_vsyscall_tz(void)
 {
-        /* Userspace gettimeofday will spin while this value is odd. */
-        ++vdso_data->tz_update_count;
-        smp_wmb();
+        write_seqcount_begin(&vdso_data->tz_seq);
         vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
         vdso_data->tz_dsttime = sys_tz.tz_dsttime;
-        smp_wmb();
-        ++vdso_data->tz_update_count;
+        write_seqcount_end(&vdso_data->tz_seq);
 }
 
 void update_vsyscall(struct timekeeper *tk)
 {
-        struct timespec *wtm = &tk->wall_to_monotonic;
-        struct clocksource *clock = tk->tkr.clock;
-
-        if (clock != &cycle_counter_cs)
+        if (tk->tkr.clock != &cycle_counter_cs)
                 return;
 
-        /* Userspace gettimeofday will spin while this value is odd. */
-        ++vdso_data->tb_update_count;
-        smp_wmb();
-        vdso_data->xtime_tod_stamp = tk->tkr.cycle_last;
-        vdso_data->xtime_clock_sec = tk->xtime_sec;
-        vdso_data->xtime_clock_nsec = tk->tkr.xtime_nsec;
-        vdso_data->wtom_clock_sec = wtm->tv_sec;
-        vdso_data->wtom_clock_nsec = wtm->tv_nsec;
-        vdso_data->mult = tk->tkr.mult;
-        vdso_data->shift = tk->tkr.shift;
-        smp_wmb();
-        ++vdso_data->tb_update_count;
+        write_seqcount_begin(&vdso_data->tb_seq);
+
+        vdso_data->cycle_last           = tk->tkr.cycle_last;
+        vdso_data->mask                 = tk->tkr.mask;
+        vdso_data->mult                 = tk->tkr.mult;
+        vdso_data->shift                = tk->tkr.shift;
+
+        vdso_data->wall_time_sec        = tk->xtime_sec;
+        vdso_data->wall_time_snsec      = tk->tkr.xtime_nsec;
+
+        vdso_data->monotonic_time_sec   = tk->xtime_sec
+                                        + tk->wall_to_monotonic.tv_sec;
+        vdso_data->monotonic_time_snsec = tk->tkr.xtime_nsec
+                                        + ((u64)tk->wall_to_monotonic.tv_nsec
+                                                << tk->tkr.shift);
+        while (vdso_data->monotonic_time_snsec >=
+                                        (((u64)NSEC_PER_SEC) << tk->tkr.shift)) {
+                vdso_data->monotonic_time_snsec -=
+                                        ((u64)NSEC_PER_SEC) << tk->tkr.shift;
+                vdso_data->monotonic_time_sec++;
+        }
+
+        vdso_data->wall_time_coarse_sec = tk->xtime_sec;
+        vdso_data->wall_time_coarse_nsec = (long)(tk->tkr.xtime_nsec >>
+                                                 tk->tkr.shift);
+
+        vdso_data->monotonic_time_coarse_sec =
+                vdso_data->wall_time_coarse_sec + tk->wall_to_monotonic.tv_sec;
+        vdso_data->monotonic_time_coarse_nsec =
+                vdso_data->wall_time_coarse_nsec + tk->wall_to_monotonic.tv_nsec;
+
+        while (vdso_data->monotonic_time_coarse_nsec >= NSEC_PER_SEC) {
+                vdso_data->monotonic_time_coarse_nsec -= NSEC_PER_SEC;
+                vdso_data->monotonic_time_coarse_sec++;
+        }
+
+        write_seqcount_end(&vdso_data->tb_seq);
 }
diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c
index f3ceb6308e42..86900ccd4977 100644
--- a/arch/tile/kernel/traps.c
+++ b/arch/tile/kernel/traps.c
@@ -277,7 +277,7 @@ void __kprobes do_trap(struct pt_regs *regs, int fault_num,
                 if (fixup_exception(regs))  /* ILL_TRANS or UNALIGN_DATA */
                         return;
                 if (fault_num >= 0 &&
-                    fault_num < sizeof(int_name)/sizeof(int_name[0]) &&
+                    fault_num < ARRAY_SIZE(int_name) &&
                     int_name[fault_num] != NULL)
                         name = int_name[fault_num];
                 else
diff --git a/arch/tile/kernel/vdso/vdso.lds.S b/arch/tile/kernel/vdso/vdso.lds.S
index 041cd6c39c83..731529f3f06f 100644
--- a/arch/tile/kernel/vdso/vdso.lds.S
+++ b/arch/tile/kernel/vdso/vdso.lds.S
@@ -82,6 +82,8 @@ VERSION
                 __vdso_rt_sigreturn;
                 __vdso_gettimeofday;
                 gettimeofday;
+                __vdso_clock_gettime;
+                clock_gettime;
         local:*;
         };
 }
diff --git a/arch/tile/kernel/vdso/vgettimeofday.c b/arch/tile/kernel/vdso/vgettimeofday.c
index e933fb9fbf5c..8bb21eda07d8 100644
--- a/arch/tile/kernel/vdso/vgettimeofday.c
+++ b/arch/tile/kernel/vdso/vgettimeofday.c
@@ -15,6 +15,7 @@
 #define VDSO_BUILD  /* avoid some shift warnings for -m32 in <asm/page.h> */
 #include <linux/time.h>
 #include <asm/timex.h>
+#include <asm/unistd.h>
 #include <asm/vdso.h>
 
 #if CHIP_HAS_SPLIT_CYCLE()
@@ -35,6 +36,11 @@ static inline cycles_t get_cycles_inline(void)
 #define get_cycles get_cycles_inline
 #endif
 
+struct syscall_return_value {
+        long value;
+        long error;
+};
+
 /*
  * Find out the vDSO data page address in the process address space.
  */
@@ -50,59 +56,143 @@ inline unsigned long get_datapage(void)
         return ret;
 }
 
-int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
+static inline u64 vgetsns(struct vdso_data *vdso)
+{
+        return ((get_cycles() - vdso->cycle_last) & vdso->mask) * vdso->mult;
+}
+
+static inline int do_realtime(struct vdso_data *vdso, struct timespec *ts)
+{
+        unsigned count;
+        u64 ns;
+
+        do {
+                count = read_seqcount_begin(&vdso->tb_seq);
+                ts->tv_sec = vdso->wall_time_sec;
+                ns = vdso->wall_time_snsec;
+                ns += vgetsns(vdso);
+                ns >>= vdso->shift;
+        } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
+
+        ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
+        ts->tv_nsec = ns;
+
+        return 0;
+}
+
+static inline int do_monotonic(struct vdso_data *vdso, struct timespec *ts)
+{
+        unsigned count;
+        u64 ns;
+
+        do {
+                count = read_seqcount_begin(&vdso->tb_seq);
+                ts->tv_sec = vdso->monotonic_time_sec;
+                ns = vdso->monotonic_time_snsec;
+                ns += vgetsns(vdso);
+                ns >>= vdso->shift;
+        } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
+
+        ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
+        ts->tv_nsec = ns;
+
+        return 0;
+}
+
+static inline int do_realtime_coarse(struct vdso_data *vdso,
+                                     struct timespec *ts)
+{
+        unsigned count;
+
+        do {
+                count = read_seqcount_begin(&vdso->tb_seq);
+                ts->tv_sec = vdso->wall_time_coarse_sec;
+                ts->tv_nsec = vdso->wall_time_coarse_nsec;
+        } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
+
+        return 0;
+}
+
+static inline int do_monotonic_coarse(struct vdso_data *vdso,
+                                      struct timespec *ts)
 {
-        cycles_t cycles;
-        unsigned long count, sec, ns;
-        volatile struct vdso_data *vdso_data;
+        unsigned count;
+
+        do {
+                count = read_seqcount_begin(&vdso->tb_seq);
+                ts->tv_sec = vdso->monotonic_time_coarse_sec;
+                ts->tv_nsec = vdso->monotonic_time_coarse_nsec;
+        } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
+
+        return 0;
+}
+
+struct syscall_return_value __vdso_gettimeofday(struct timeval *tv,
+                                                struct timezone *tz)
+{
+        struct syscall_return_value ret = { 0, 0 };
+        unsigned count;
+        struct vdso_data *vdso = (struct vdso_data *)get_datapage();
 
-        vdso_data = (struct vdso_data *)get_datapage();
         /* The use of the timezone is obsolete, normally tz is NULL. */
         if (unlikely(tz != NULL)) {
-                while (1) {
-                        /* Spin until the update finish. */
-                        count = vdso_data->tz_update_count;
-                        if (count & 1)
-                                continue;
-
-                        tz->tz_minuteswest = vdso_data->tz_minuteswest;
-                        tz->tz_dsttime = vdso_data->tz_dsttime;
-
-                        /* Check whether updated, read again if so. */
-                        if (count == vdso_data->tz_update_count)
-                                break;
-                }
+                do {
+                        count = read_seqcount_begin(&vdso->tz_seq);
+                        tz->tz_minuteswest = vdso->tz_minuteswest;
+                        tz->tz_dsttime = vdso->tz_dsttime;
+                } while (unlikely(read_seqcount_retry(&vdso->tz_seq, count)));
         }
 
         if (unlikely(tv == NULL))
-                return 0;
-
-        while (1) {
-                /* Spin until the update finish. */
-                count = vdso_data->tb_update_count;
-                if (count & 1)
-                        continue;
-
-                sec = vdso_data->xtime_clock_sec;
-                cycles = get_cycles() - vdso_data->xtime_tod_stamp;
-                ns = (cycles * vdso_data->mult) + vdso_data->xtime_clock_nsec;
-                ns >>= vdso_data->shift;
-
-                if (ns >= NSEC_PER_SEC) {
-                        ns -= NSEC_PER_SEC;
-                        sec += 1;
-                }
-
-                /* Check whether updated, read again if so. */
-                if (count == vdso_data->tb_update_count)
-                        break;
-        }
+                return ret;
 
-        tv->tv_sec = sec;
-        tv->tv_usec = ns / 1000;
+        do_realtime(vdso, (struct timespec *)tv);
+        tv->tv_usec /= 1000;
 
-        return 0;
+        return ret;
 }
 
 int gettimeofday(struct timeval *tv, struct timezone *tz)
         __attribute__((weak, alias("__vdso_gettimeofday")));
+
+static struct syscall_return_value vdso_fallback_gettime(long clock,
+                                                         struct timespec *ts)
+{
+        struct syscall_return_value ret;
+        __asm__ __volatile__ (
+                "swint1"
+                : "=R00" (ret.value), "=R01" (ret.error)
+                : "R10" (__NR_clock_gettime), "R00" (clock), "R01" (ts)
+                : "r2", "r3", "r4", "r5", "r6", "r7",
+                "r8",  "r9", "r11", "r12", "r13", "r14", "r15",
+                "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+                "r24", "r25", "r26", "r27", "r28", "r29", "memory");
+        return ret;
+}
+
+struct syscall_return_value __vdso_clock_gettime(clockid_t clock,
+                                                 struct timespec *ts)
+{
+        struct vdso_data *vdso = (struct vdso_data *)get_datapage();
+        struct syscall_return_value ret = { 0, 0 };
+
+        switch (clock) {
+        case CLOCK_REALTIME:
+                do_realtime(vdso, ts);
+                return ret;
+        case CLOCK_MONOTONIC:
+                do_monotonic(vdso, ts);
+                return ret;
+        case CLOCK_REALTIME_COARSE:
+                do_realtime_coarse(vdso, ts);
+                return ret;
+        case CLOCK_MONOTONIC_COARSE:
+                do_monotonic_coarse(vdso, ts);
+                return ret;
+        default:
+                return vdso_fallback_gettime(clock, ts);
+        }
+}
+
+int clock_gettime(clockid_t clock, struct timespec *ts)
+        __attribute__((weak, alias("__vdso_clock_gettime")));
diff --git a/arch/tile/kernel/vmlinux.lds.S b/arch/tile/kernel/vmlinux.lds.S
index f1819423ffc9..0e059a0101ea 100644
--- a/arch/tile/kernel/vmlinux.lds.S
+++ b/arch/tile/kernel/vmlinux.lds.S
@@ -66,11 +66,9 @@ SECTIONS
 
   . = ALIGN(PAGE_SIZE);
   __init_begin = .;
-  VMLINUX_SYMBOL(_sinitdata) = .;
   INIT_DATA_SECTION(16) :data =0
   PERCPU_SECTION(L2_CACHE_BYTES)
   . = ALIGN(PAGE_SIZE);
-  VMLINUX_SYMBOL(_einitdata) = .;
   __init_end = .;
 
   _sdata = .;                   /* Start of data section */
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index bfb3127b4df9..a092e393bd20 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -254,8 +254,8 @@ static pgprot_t __init init_pgprot(ulong address)
          * Everything else that isn't data or bss is heap, so mark it
          * with the initial heap home (hash-for-home, or this cpu).  This
          * includes any addresses after the loaded image and any address before
-         * _einitdata, since we already captured the case of text before
-         * _sinittext, and __pa(einittext) is approximately __pa(sinitdata).
+         * __init_end, since we already captured the case of text before
+         * _sinittext, and __pa(einittext) is approximately __pa(__init_begin).
          *
          * All the LOWMEM pages that we mark this way will get their
          * struct page homecache properly marked later, in set_page_homes().
@@ -263,7 +263,7 @@ static pgprot_t __init init_pgprot(ulong address)
          * homes, but with a zero free_time we don't have to actually
          * do a flush action the first time we use them, either.
          */
-        if (address >= (ulong) _end || address < (ulong) _einitdata)
+        if (address >= (ulong) _end || address < (ulong) __init_end)
                 return construct_pgprot(PAGE_KERNEL, initial_heap_home());
 
         /* Use hash-for-home if requested for data/bss. */
@@ -632,7 +632,7 @@ int devmem_is_allowed(unsigned long pagenr)
 {
         return pagenr < kaddr_to_pfn(_end) &&
                 !(pagenr >= kaddr_to_pfn(&init_thread_union) ||
-                  pagenr < kaddr_to_pfn(_einitdata)) &&
+                  pagenr < kaddr_to_pfn(__init_end)) &&
                 !(pagenr >= kaddr_to_pfn(_sinittext) ||
                   pagenr <= kaddr_to_pfn(_einittext-1));
 }
@@ -975,8 +975,8 @@ void free_initmem(void)
 
         /* Free the data pages that we won't use again after init. */
         free_init_pages("unused kernel data",
-                        (unsigned long)_sinitdata,
-                        (unsigned long)_einitdata);
+                        (unsigned long)__init_begin,
+                        (unsigned long)__init_end);
 
         /*
          * Free the pages mapped from 0xc0000000 that correspond to code
diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild
index 7bd64aa2e94a..244b12c8cb39 100644
--- a/arch/um/include/asm/Kbuild
+++ b/arch/um/include/asm/Kbuild
@@ -14,6 +14,7 @@ generic-y += hash.h
 generic-y += hw_irq.h
 generic-y += io.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += mcs_spinlock.h
 generic-y += mutex.h
diff --git a/arch/unicore32/include/asm/Kbuild b/arch/unicore32/include/asm/Kbuild
index 1e5fb872a4aa..5a2bb53faa42 100644
--- a/arch/unicore32/include/asm/Kbuild
+++ b/arch/unicore32/include/asm/Kbuild
@@ -22,6 +22,7 @@ generic-y += ioctl.h
 generic-y += ioctls.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += local.h
diff --git a/arch/unicore32/include/mach/pm.h b/arch/unicore32/include/mach/pm.h
index 4dcd34ae194c..77b522694e74 100644
--- a/arch/unicore32/include/mach/pm.h
+++ b/arch/unicore32/include/mach/pm.h
@@ -36,8 +36,5 @@ extern int puv3_pm_enter(suspend_state_t state);
 /* Defined in hibernate_asm.S */
 extern int restore_image(pgd_t *resume_pg_dir, struct pbe *restore_pblist);
 
-/* References to section boundaries */
-extern const void __nosave_begin, __nosave_end;
-
 extern struct pbe *restore_pblist;
 #endif
diff --git a/arch/unicore32/kernel/hibernate.c b/arch/unicore32/kernel/hibernate.c
index d75ef8b6cb56..9969ec374abb 100644
--- a/arch/unicore32/kernel/hibernate.c
+++ b/arch/unicore32/kernel/hibernate.c
@@ -18,6 +18,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
+#include <asm/sections.h>
 #include <asm/suspend.h>
 
 #include "mach/pm.h"
diff --git a/arch/unicore32/kernel/signal.c b/arch/unicore32/kernel/signal.c
index 780d77388dec..7c8fb7018dc6 100644
--- a/arch/unicore32/kernel/signal.c
+++ b/arch/unicore32/kernel/signal.c
@@ -254,7 +254,8 @@ static int setup_frame(struct ksignal *ksig, sigset_t *set,
 
         err |= setup_sigframe(frame, regs, set);
         if (err == 0)
-                err |= setup_return(regs, &ksig->ka, frame->retcode, frame, usig);
+                err |= setup_return(regs, &ksig->ka, frame->retcode, frame,
+                                    ksig->sig);
 
         return err;
 }
@@ -276,7 +277,8 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
         err |= __save_altstack(&frame->sig.uc.uc_stack, regs->UCreg_sp);
         err |= setup_sigframe(&frame->sig, regs, set);
         if (err == 0)
-                err |= setup_return(regs, &ksig->ka, frame->sig.retcode, frame, usig);
+                err |= setup_return(regs, &ksig->ka, frame->sig.retcode, frame,
+                                    ksig->sig);
 
         if (err == 0) {
                 /*
@@ -303,7 +305,6 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs,
                           int syscall)
 {
         struct thread_info *thread = current_thread_info();
-        struct task_struct *tsk = current;
         sigset_t *oldset = sigmask_to_save();
         int usig = ksig->sig;
         int ret;
@@ -373,7 +374,7 @@ static void do_signal(struct pt_regs *regs, int syscall)
         if (!user_mode(regs))
                 return;
 
-        if (get_signsl(&ksig)) {
+        if (get_signal(&ksig)) {
                 handle_signal(&ksig, regs, syscall);
                 return;
         }
diff --git a/arch/x86/Kbuild b/arch/x86/Kbuild
index 61b6d51866f8..3942f74c92d7 100644
--- a/arch/x86/Kbuild
+++ b/arch/x86/Kbuild
@@ -17,6 +17,4 @@ obj-$(CONFIG_IA32_EMULATION) += ia32/
 obj-y += platform/
 obj-y += net/
 
-ifeq ($(CONFIG_X86_64),y)
-obj-$(CONFIG_KEXEC) += purgatory/
-endif
+obj-$(CONFIG_KEXEC_FILE) += purgatory/
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5d0bf1aa9dcb..3eb8a41509b3 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -23,13 +23,13 @@ config X86
         def_bool y
         select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI
         select ARCH_HAS_DEBUG_STRICT_USER_COPY_CHECKS
+        select ARCH_HAS_FAST_MULTIPLIER
         select ARCH_MIGHT_HAVE_PC_PARPORT
         select ARCH_MIGHT_HAVE_PC_SERIO
         select HAVE_AOUT if X86_32
         select HAVE_UNSTABLE_SCHED_CLOCK
         select ARCH_SUPPORTS_NUMA_BALANCING if X86_64
         select ARCH_SUPPORTS_INT128 if X86_64
-        select ARCH_WANTS_PROT_NUMA_PROT_NONE
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_PCSPKR_PLATFORM
@@ -136,6 +136,7 @@ config X86
         select HAVE_ACPI_APEI if ACPI
         select HAVE_ACPI_APEI_NMI if ACPI
         select ACPI_LEGACY_TABLES_LOOKUP if ACPI
+        select X86_FEATURE_NAMES if PROC_FS
 
 config INSTRUCTION_DECODER
         def_bool y
@@ -313,6 +314,17 @@ config SMP
 
           If you don't know what to do here, say N.
 
+config X86_FEATURE_NAMES
+        bool "Processor feature human-readable names" if EMBEDDED
+        default y
+        ---help---
+          This option compiles in a table of x86 feature bits and corresponding
+          names.  This is required to support /proc/cpuinfo and a few kernel
+          messages.  You can disable this to save space, at the expense of
+          making those few kernel messages show numeric feature bits instead.
+
+          If in doubt, say Y.
+
 config X86_X2APIC
         bool "Support x2apic"
         depends on X86_LOCAL_APIC && X86_64 && IRQ_REMAP
@@ -1585,9 +1597,6 @@ source kernel/Kconfig.hz
 
 config KEXEC
         bool "kexec system call"
-        select BUILD_BIN2C
-        select CRYPTO
-        select CRYPTO_SHA256
         ---help---
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
@@ -1602,9 +1611,22 @@ config KEXEC
           interface is strongly in flux, so no good recommendation can be
           made.
 
+config KEXEC_FILE
+        bool "kexec file based system call"
+        select BUILD_BIN2C
+        depends on KEXEC
+        depends on X86_64
+        depends on CRYPTO=y
+        depends on CRYPTO_SHA256=y
+        ---help---
+          This is new version of kexec system call. This system call is
+          file based and takes file descriptors as system call argument
+          for kernel and initramfs as opposed to list of segments as
+          accepted by previous system call.
+
 config KEXEC_VERIFY_SIG
         bool "Verify kernel signature during kexec_file_load() syscall"
-        depends on KEXEC
+        depends on KEXEC_FILE
         ---help---
           This option makes kernel signature verification mandatory for
           kexec_file_load() syscall. If kernel is signature can not be
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index c1aa36887843..5692d6ac0f18 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -184,11 +184,8 @@ archheaders:
         $(Q)$(MAKE) $(build)=arch/x86/syscalls all
 
 archprepare:
-ifeq ($(CONFIG_KEXEC),y)
-# Build only for 64bit. No loaders for 32bit yet.
- ifeq ($(CONFIG_X86_64),y)
+ifeq ($(CONFIG_KEXEC_FILE),y)
         $(Q)$(MAKE) $(build)=arch/x86/purgatory arch/x86/purgatory/kexec-purgatory.c
- endif
 endif
 
 ###
@@ -254,12 +251,7 @@ archclean:
         $(Q)rm -rf $(objtree)/arch/x86_64
         $(Q)$(MAKE) $(clean)=$(boot)
         $(Q)$(MAKE) $(clean)=arch/x86/tools
-
-PHONY += kvmconfig
-kvmconfig:
-        $(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target))
-        $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(srctree)/arch/x86/configs/kvm_guest.config
-        $(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig
+        $(Q)$(MAKE) $(clean)=arch/x86/purgatory
 
 define archhelp
   echo  '* bzImage      - Compressed kernel image (arch/x86/boot/bzImage)'
@@ -274,5 +266,4 @@ define archhelp
   echo  '                  bzdisk/fdimage*/isoimage also accept:'
   echo  '                  FDARGS="..."  arguments for the booted kernel'
   echo  '                  FDINITRD=file initrd for the booted kernel'
-  echo  '  kvmconfig    - Enable additional options for guest kernel support'
 endef
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index dbe8dd2fe247..5b016e2498f3 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -35,19 +35,22 @@ setup-y		+= video-vesa.o
 setup-y         += video-bios.o
 
 targets         += $(setup-y)
-hostprogs-y     := mkcpustr tools/build
+hostprogs-y     := tools/build
+hostprogs-$(CONFIG_X86_FEATURE_NAMES) += mkcpustr
 
 HOST_EXTRACFLAGS += -I$(srctree)/tools/include \
                     -include include/generated/autoconf.h \
                     -D__EXPORTED_HEADERS__
 
+ifdef CONFIG_X86_FEATURE_NAMES
 $(obj)/cpu.o: $(obj)/cpustr.h
 
 quiet_cmd_cpustr = CPUSTR  $@
       cmd_cpustr = $(obj)/mkcpustr > $@
-targets         += cpustr.h
+targets += cpustr.h
 $(obj)/cpustr.h: $(obj)/mkcpustr FORCE
         $(call if_changed,cpustr)
+endif
 
 # ---------------------------------------------------------------------------
 
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index 7a801a310e37..704f58aa79cd 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -26,18 +26,18 @@ LDFLAGS_vmlinux := -T
 hostprogs-y     := mkpiggy
 HOST_EXTRACFLAGS += -I$(srctree)/tools/include
 
-VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
-        $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o \
-        $(obj)/piggy.o $(obj)/cpuflags.o $(obj)/aslr.o
+vmlinux-objs-y := $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
+        $(obj)/string.o $(obj)/cmdline.o \
+        $(obj)/piggy.o $(obj)/cpuflags.o
+
+vmlinux-objs-$(CONFIG_EARLY_PRINTK) += $(obj)/early_serial_console.o
+vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/aslr.o
 
 $(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone
 
-ifeq ($(CONFIG_EFI_STUB), y)
-        VMLINUX_OBJS += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o \
-                                $(objtree)/drivers/firmware/efi/libstub/lib.a
-endif
+vmlinux-objs-$(CONFIG_EFI_STUB) += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
 
-$(obj)/vmlinux: $(VMLINUX_OBJS) FORCE
+$(obj)/vmlinux: $(vmlinux-objs-y) FORCE
         $(call if_changed,ld)
         @:
 
@@ -45,7 +45,7 @@ OBJCOPYFLAGS_vmlinux.bin :=  -R .comment -S
 $(obj)/vmlinux.bin: vmlinux FORCE
         $(call if_changed,objcopy)
 
-targets += $(patsubst $(obj)/%,%,$(VMLINUX_OBJS)) vmlinux.bin.all vmlinux.relocs
+targets += $(patsubst $(obj)/%,%,$(vmlinux-objs-y)) vmlinux.bin.all vmlinux.relocs
 
 CMD_RELOCS = arch/x86/tools/relocs
 quiet_cmd_relocs = RELOCS  $@
diff --git a/arch/x86/boot/compressed/aslr.c b/arch/x86/boot/compressed/aslr.c
index fc6091abedb7..7c68808edeb7 100644
--- a/arch/x86/boot/compressed/aslr.c
+++ b/arch/x86/boot/compressed/aslr.c
@@ -1,6 +1,5 @@
 #include "misc.h"
 
-#ifdef CONFIG_RANDOMIZE_BASE
 #include <asm/msr.h>
 #include <asm/archrandom.h>
 #include <asm/e820.h>
@@ -183,12 +182,27 @@ static void mem_avoid_init(unsigned long input, unsigned long input_size,
 static bool mem_avoid_overlap(struct mem_vector *img)
 {
         int i;
+        struct setup_data *ptr;
 
         for (i = 0; i < MEM_AVOID_MAX; i++) {
                 if (mem_overlaps(img, &mem_avoid[i]))
                         return true;
         }
 
+        /* Avoid all entries in the setup_data linked list. */
+        ptr = (struct setup_data *)(unsigned long)real_mode->hdr.setup_data;
+        while (ptr) {
+                struct mem_vector avoid;
+
+                avoid.start = (u64)ptr;
+                avoid.size = sizeof(*ptr) + ptr->len;
+
+                if (mem_overlaps(img, &avoid))
+                        return true;
+
+                ptr = (struct setup_data *)(unsigned long)ptr->next;
+        }
+
         return false;
 }
 
@@ -320,5 +334,3 @@ unsigned char *choose_kernel_location(unsigned char *input,
 out:
         return (unsigned char *)choice;
 }
-
-#endif /* CONFIG_RANDOMIZE_BASE */
diff --git a/arch/x86/boot/compressed/early_serial_console.c b/arch/x86/boot/compressed/early_serial_console.c
index d3d003cb5481..261e81fb9582 100644
--- a/arch/x86/boot/compressed/early_serial_console.c
+++ b/arch/x86/boot/compressed/early_serial_console.c
@@ -1,9 +1,5 @@
 #include "misc.h"
 
-#ifdef CONFIG_EARLY_PRINTK
-
 int early_serial_base;
 
 #include "../early_serial_console.c"
-
-#endif
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index f277184e2ac1..de8eebd6f67c 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -19,7 +19,10 @@
 
 static efi_system_table_t *sys_table;
 
-struct efi_config *efi_early;
+static struct efi_config *efi_early;
+
+#define efi_call_early(f, ...)                                          \
+        efi_early->call(efi_early->f, __VA_ARGS__);
 
 #define BOOT_SERVICES(bits)                                             \
 static void setup_boot_services##bits(struct efi_config *c)             \
@@ -265,21 +268,25 @@ void efi_char16_printk(efi_system_table_t *table, efi_char16_t *str)
 
                 offset = offsetof(typeof(*out), output_string);
                 output_string = efi_early->text_output + offset;
+                out = (typeof(out))(unsigned long)efi_early->text_output;
                 func = (u64 *)output_string;
 
-                efi_early->call(*func, efi_early->text_output, str);
+                efi_early->call(*func, out, str);
         } else {
                 struct efi_simple_text_output_protocol_32 *out;
                 u32 *func;
 
                 offset = offsetof(typeof(*out), output_string);
                 output_string = efi_early->text_output + offset;
+                out = (typeof(out))(unsigned long)efi_early->text_output;
                 func = (u32 *)output_string;
 
-                efi_early->call(*func, efi_early->text_output, str);
+                efi_early->call(*func, out, str);
         }
 }
 
+#include "../../../../drivers/firmware/efi/libstub/efi-stub-helper.c"
+
 static void find_bits(unsigned long mask, u8 *pos, u8 *size)
 {
         u8 first, len;
@@ -360,7 +367,7 @@ free_struct:
         return status;
 }
 
-static efi_status_t
+static void
 setup_efi_pci32(struct boot_params *params, void **pci_handle,
                 unsigned long size)
 {
@@ -403,8 +410,6 @@ setup_efi_pci32(struct boot_params *params, void **pci_handle,
                 data = (struct setup_data *)rom;
 
         }
-
-        return status;
 }
 
 static efi_status_t
@@ -463,7 +468,7 @@ free_struct:
 
 }
 
-static efi_status_t
+static void
 setup_efi_pci64(struct boot_params *params, void **pci_handle,
                 unsigned long size)
 {
@@ -506,11 +511,18 @@ setup_efi_pci64(struct boot_params *params, void **pci_handle,
                 data = (struct setup_data *)rom;
 
         }
-
-        return status;
 }
 
-static efi_status_t setup_efi_pci(struct boot_params *params)
+/*
+ * There's no way to return an informative status from this function,
+ * because any analysis (and printing of error messages) needs to be
+ * done directly at the EFI function call-site.
+ *
+ * For example, EFI_INVALID_PARAMETER could indicate a bug or maybe we
+ * just didn't find any PCI devices, but there's no way to tell outside
+ * the context of the call.
+ */
+static void setup_efi_pci(struct boot_params *params)
 {
         efi_status_t status;
         void **pci_handle = NULL;
@@ -527,7 +539,7 @@ static efi_status_t setup_efi_pci(struct boot_params *params)
                                         size, (void **)&pci_handle);
 
                 if (status != EFI_SUCCESS)
-                        return status;
+                        return;
 
                 status = efi_call_early(locate_handle,
                                         EFI_LOCATE_BY_PROTOCOL, &pci_proto,
@@ -538,13 +550,12 @@ static efi_status_t setup_efi_pci(struct boot_params *params)
                 goto free_handle;
 
         if (efi_early->is64)
-                status = setup_efi_pci64(params, pci_handle, size);
+                setup_efi_pci64(params, pci_handle, size);
         else
-                status = setup_efi_pci32(params, pci_handle, size);
+                setup_efi_pci32(params, pci_handle, size);
 
 free_handle:
         efi_call_early(free_pool, pci_handle);
-        return status;
 }
 
 static void
@@ -1032,7 +1043,6 @@ struct boot_params *make_boot_params(struct efi_config *c)
         int i;
         unsigned long ramdisk_addr;
         unsigned long ramdisk_size;
-        unsigned long initrd_addr_max;
 
         efi_early = c;
         sys_table = (efi_system_table_t *)(unsigned long)efi_early->table;
@@ -1095,15 +1105,20 @@ struct boot_params *make_boot_params(struct efi_config *c)
 
         memset(sdt, 0, sizeof(*sdt));
 
-        if (hdr->xloadflags & XLF_CAN_BE_LOADED_ABOVE_4G)
-                initrd_addr_max = -1UL;
-        else
-                initrd_addr_max = hdr->initrd_addr_max;
-
         status = handle_cmdline_files(sys_table, image,
                                       (char *)(unsigned long)hdr->cmd_line_ptr,
-                                      "initrd=", initrd_addr_max,
+                                      "initrd=", hdr->initrd_addr_max,
                                       &ramdisk_addr, &ramdisk_size);
+
+        if (status != EFI_SUCCESS &&
+            hdr->xloadflags & XLF_CAN_BE_LOADED_ABOVE_4G) {
+                efi_printk(sys_table, "Trying to load files to higher address\n");
+                status = handle_cmdline_files(sys_table, image,
+                                      (char *)(unsigned long)hdr->cmd_line_ptr,
+                                      "initrd=", -1UL,
+                                      &ramdisk_addr, &ramdisk_size);
+        }
+
         if (status != EFI_SUCCESS)
                 goto fail2;
         hdr->ramdisk_image = ramdisk_addr & 0xffffffff;
@@ -1376,10 +1391,7 @@ struct boot_params *efi_main(struct efi_config *c,
 
         setup_graphics(boot_params);
 
-        status = setup_efi_pci(boot_params);
-        if (status != EFI_SUCCESS) {
-                efi_printk(sys_table, "setup_efi_pci() failed!\n");
-        }
+        setup_efi_pci(boot_params);
 
         status = efi_call_early(allocate_pool, EFI_LOADER_DATA,
                                 sizeof(*gdt), (void **)&gdt);
diff --git a/arch/x86/boot/compressed/eboot.h b/arch/x86/boot/compressed/eboot.h
index d487e727f1ec..c88c31ecad12 100644
--- a/arch/x86/boot/compressed/eboot.h
+++ b/arch/x86/boot/compressed/eboot.h
@@ -103,4 +103,20 @@ struct efi_uga_draw_protocol {
         void *blt;
 };
 
+struct efi_config {
+        u64 image_handle;
+        u64 table;
+        u64 allocate_pool;
+        u64 allocate_pages;
+        u64 get_memory_map;
+        u64 free_pool;
+        u64 free_pages;
+        u64 locate_handle;
+        u64 handle_protocol;
+        u64 exit_boot_services;
+        u64 text_output;
+        efi_status_t (*call)(unsigned long, ...);
+        bool is64;
+} __packed;
+
 #endif /* BOOT_COMPRESSED_EBOOT_H */
diff --git a/arch/x86/boot/cpu.c b/arch/x86/boot/cpu.c
index 6ec6bb6e9957..29207f69ae8c 100644
--- a/arch/x86/boot/cpu.c
+++ b/arch/x86/boot/cpu.c
@@ -16,7 +16,9 @@
  */
 
 #include "boot.h"
+#ifdef CONFIG_X86_FEATURE_NAMES
 #include "cpustr.h"
+#endif
 
 static char *cpu_name(int level)
 {
@@ -32,11 +34,48 @@ static char *cpu_name(int level)
         }
 }
 
+static void show_cap_strs(u32 *err_flags)
+{
+        int i, j;
+#ifdef CONFIG_X86_FEATURE_NAMES
+        const unsigned char *msg_strs = (const unsigned char *)x86_cap_strs;
+        for (i = 0; i < NCAPINTS; i++) {
+                u32 e = err_flags[i];
+                for (j = 0; j < 32; j++) {
+                        if (msg_strs[0] < i ||
+                            (msg_strs[0] == i && msg_strs[1] < j)) {
+                                /* Skip to the next string */
+                                msg_strs += 2;
+                                while (*msg_strs++)
+                                        ;
+                        }
+                        if (e & 1) {
+                                if (msg_strs[0] == i &&
+                                    msg_strs[1] == j &&
+                                    msg_strs[2])
+                                        printf("%s ", msg_strs+2);
+                                else
+                                        printf("%d:%d ", i, j);
+                        }
+                        e >>= 1;
+                }
+        }
+#else
+        for (i = 0; i < NCAPINTS; i++) {
+                u32 e = err_flags[i];
+                for (j = 0; j < 32; j++) {
+                        if (e & 1)
+                                printf("%d:%d ", i, j);
+                        e >>= 1;
+                }
+        }
+#endif
+}
+
 int validate_cpu(void)
 {
         u32 *err_flags;
         int cpu_level, req_level;
-        const unsigned char *msg_strs;
 
         check_cpu(&cpu_level, &req_level, &err_flags);
 
@@ -49,34 +88,9 @@ int validate_cpu(void)
         }
 
         if (err_flags) {
-                int i, j;
                 puts("This kernel requires the following features "
                      "not present on the CPU:\n");
-
-                msg_strs = (const unsigned char *)x86_cap_strs;
-
-                for (i = 0; i < NCAPINTS; i++) {
-                        u32 e = err_flags[i];
-
-                        for (j = 0; j < 32; j++) {
-                                if (msg_strs[0] < i ||
-                                    (msg_strs[0] == i && msg_strs[1] < j)) {
-                                        /* Skip to the next string */
-                                        msg_strs += 2;
-                                        while (*msg_strs++)
-                                                ;
-                                }
-                                if (e & 1) {
-                                        if (msg_strs[0] == i &&
-                                            msg_strs[1] == j &&
-                                            msg_strs[2])
-                                                printf("%s ", msg_strs+2);
-                                        else
-                                                printf("%d:%d ", i, j);
-                                }
-                                e >>= 1;
-                        }
-                }
+                show_cap_strs(err_flags);
                 putchar('\n');
                 return -1;
         } else {
diff --git a/arch/x86/configs/tiny.config b/arch/x86/configs/tiny.config
new file mode 100644
index 000000000000..4e2ecfa23c15
--- /dev/null
+++ b/arch/x86/configs/tiny.config
@@ -0,0 +1 @@
+CONFIG_NOHIGHMEM=y
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index d551165a3159..fd0f848938cc 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
 
 obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o
 obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o
+obj-$(CONFIG_CRYPTO_SHA1_MB) += sha-mb/
 obj-$(CONFIG_CRYPTO_CRC32_PCLMUL) += crc32-pclmul.o
 obj-$(CONFIG_CRYPTO_SHA256_SSSE3) += sha256-ssse3.o
 obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o
diff --git a/arch/x86/crypto/aes_ctrby8_avx-x86_64.S b/arch/x86/crypto/aes_ctrby8_avx-x86_64.S
index f091f122ed24..2df2a0298f5a 100644
--- a/arch/x86/crypto/aes_ctrby8_avx-x86_64.S
+++ b/arch/x86/crypto/aes_ctrby8_avx-x86_64.S
@@ -79,9 +79,6 @@
 #define xcounter        %xmm8
 #define xbyteswap       %xmm9
 #define xkey0           %xmm10
-#define xkey3           %xmm11
-#define xkey6           %xmm12
-#define xkey9           %xmm13
 #define xkey4           %xmm11
 #define xkey8           %xmm12
 #define xkey12          %xmm13
@@ -108,6 +105,10 @@
 
 byteswap_const:
         .octa 0x000102030405060708090A0B0C0D0E0F
+ddq_low_msk:
+        .octa 0x0000000000000000FFFFFFFFFFFFFFFF
+ddq_high_add_1:
+        .octa 0x00000000000000010000000000000000
 ddq_add_1:
         .octa 0x00000000000000000000000000000001
 ddq_add_2:
@@ -169,7 +170,12 @@ ddq_add_8:
         .rept (by - 1)
                 club DDQ_DATA, i
                 club XDATA, i
-                vpaddd  var_ddq_add(%rip), xcounter, var_xdata
+                vpaddq  var_ddq_add(%rip), xcounter, var_xdata
+                vptest  ddq_low_msk(%rip), var_xdata
+                jnz 1f
+                vpaddq  ddq_high_add_1(%rip), var_xdata, var_xdata
+                vpaddq  ddq_high_add_1(%rip), xcounter, xcounter
+                1:
                 vpshufb xbyteswap, var_xdata, var_xdata
                 .set i, (i +1)
         .endr
@@ -178,7 +184,11 @@ ddq_add_8:
 
         vpxor   xkey0, xdata0, xdata0
         club DDQ_DATA, by
-        vpaddd  var_ddq_add(%rip), xcounter, xcounter
+        vpaddq  var_ddq_add(%rip), xcounter, xcounter
+        vptest  ddq_low_msk(%rip), xcounter
+        jnz     1f
+        vpaddq  ddq_high_add_1(%rip), xcounter, xcounter
+        1:
 
         .set i, 1
         .rept (by - 1)
diff --git a/arch/x86/crypto/sha-mb/Makefile b/arch/x86/crypto/sha-mb/Makefile
new file mode 100644
index 000000000000..2f8756375df5
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/Makefile
@@ -0,0 +1,11 @@
+#
+# Arch-specific CryptoAPI modules.
+#
+
+avx2_supported := $(call as-instr,vpgatherdd %ymm0$(comma)(%eax$(comma)%ymm1\
+                                $(comma)4)$(comma)%ymm2,yes,no)
+ifeq ($(avx2_supported),yes)
+        obj-$(CONFIG_CRYPTO_SHA1_MB) += sha1-mb.o
+        sha1-mb-y := sha1_mb.o sha1_mb_mgr_flush_avx2.o \
+             sha1_mb_mgr_init_avx2.o sha1_mb_mgr_submit_avx2.o sha1_x8_avx2.o
+endif
diff --git a/arch/x86/crypto/sha-mb/sha1_mb.c b/arch/x86/crypto/sha-mb/sha1_mb.c
new file mode 100644
index 000000000000..99eefd812958
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha1_mb.c
@@ -0,0 +1,935 @@
+/*
+ * Multi buffer SHA1 algorithm Glue Code
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+
+#include <crypto/internal/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/cryptohash.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <crypto/scatterwalk.h>
+#include <crypto/sha.h>
+#include <crypto/mcryptd.h>
+#include <crypto/crypto_wq.h>
+#include <asm/byteorder.h>
+#include <asm/i387.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <linux/hardirq.h>
+#include <asm/fpu-internal.h>
+#include "sha_mb_ctx.h"
+
+#define FLUSH_INTERVAL 1000 /* in usec */
+
+static struct mcryptd_alg_state sha1_mb_alg_state;
+
+struct sha1_mb_ctx {
+        struct mcryptd_ahash *mcryptd_tfm;
+};
+
+static inline struct mcryptd_hash_request_ctx *cast_hash_to_mcryptd_ctx(struct sha1_hash_ctx *hash_ctx)
+{
+        struct shash_desc *desc;
+
+        desc = container_of((void *) hash_ctx, struct shash_desc, __ctx);
+        return container_of(desc, struct mcryptd_hash_request_ctx, desc);
+}
+
+static inline struct ahash_request *cast_mcryptd_ctx_to_req(struct mcryptd_hash_request_ctx *ctx)
+{
+        return container_of((void *) ctx, struct ahash_request, __ctx);
+}
+
+static void req_ctx_init(struct mcryptd_hash_request_ctx *rctx,
+                                struct shash_desc *desc)
+{
+        rctx->flag = HASH_UPDATE;
+}
+
+static asmlinkage void (*sha1_job_mgr_init)(struct sha1_mb_mgr *state);
+static asmlinkage struct job_sha1* (*sha1_job_mgr_submit)(struct sha1_mb_mgr *state,
+                                                          struct job_sha1 *job);
+static asmlinkage struct job_sha1* (*sha1_job_mgr_flush)(struct sha1_mb_mgr *state);
+static asmlinkage struct job_sha1* (*sha1_job_mgr_get_comp_job)(struct sha1_mb_mgr *state);
+
+inline void sha1_init_digest(uint32_t *digest)
+{
+        static const uint32_t initial_digest[SHA1_DIGEST_LENGTH] = {SHA1_H0,
+                                        SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 };
+        memcpy(digest, initial_digest, sizeof(initial_digest));
+}
+
+inline uint32_t sha1_pad(uint8_t padblock[SHA1_BLOCK_SIZE * 2],
+                         uint32_t total_len)
+{
+        uint32_t i = total_len & (SHA1_BLOCK_SIZE - 1);
+
+        memset(&padblock[i], 0, SHA1_BLOCK_SIZE);
+        padblock[i] = 0x80;
+
+        i += ((SHA1_BLOCK_SIZE - 1) &
+              (0 - (total_len + SHA1_PADLENGTHFIELD_SIZE + 1)))
+             + 1 + SHA1_PADLENGTHFIELD_SIZE;
+
+#if SHA1_PADLENGTHFIELD_SIZE == 16
+        *((uint64_t *) &padblock[i - 16]) = 0;
+#endif
+
+        *((uint64_t *) &padblock[i - 8]) = cpu_to_be64(total_len << 3);
+
+        /* Number of extra blocks to hash */
+        return i >> SHA1_LOG2_BLOCK_SIZE;
+}
+
+static struct sha1_hash_ctx *sha1_ctx_mgr_resubmit(struct sha1_ctx_mgr *mgr, struct sha1_hash_ctx *ctx)
+{
+        while (ctx) {
+                if (ctx->status & HASH_CTX_STS_COMPLETE) {
+                        /* Clear PROCESSING bit */
+                        ctx->status = HASH_CTX_STS_COMPLETE;
+                        return ctx;
+                }
+
+                /*
+                 * If the extra blocks are empty, begin hashing what remains
+                 * in the user's buffer.
+                 */
+                if (ctx->partial_block_buffer_length == 0 &&
+                    ctx->incoming_buffer_length) {
+
+                        const void *buffer = ctx->incoming_buffer;
+                        uint32_t len = ctx->incoming_buffer_length;
+                        uint32_t copy_len;
+
+                        /*
+                         * Only entire blocks can be hashed.
+                         * Copy remainder to extra blocks buffer.
+                         */
+                        copy_len = len & (SHA1_BLOCK_SIZE-1);
+
+                        if (copy_len) {
+                                len -= copy_len;
+                                memcpy(ctx->partial_block_buffer,
+                                       ((const char *) buffer + len),
+                                       copy_len);
+                                ctx->partial_block_buffer_length = copy_len;
+                        }
+
+                        ctx->incoming_buffer_length = 0;
+
+                        /* len should be a multiple of the block size now */
+                        assert((len % SHA1_BLOCK_SIZE) == 0);
+
+                        /* Set len to the number of blocks to be hashed */
+                        len >>= SHA1_LOG2_BLOCK_SIZE;
+
+                        if (len) {
+
+                                ctx->job.buffer = (uint8_t *) buffer;
+                                ctx->job.len = len;
+                                ctx = (struct sha1_hash_ctx *) sha1_job_mgr_submit(&mgr->mgr,
+                                                                                  &ctx->job);
+                                continue;
+                        }
+                }
+
+                /*
+                 * If the extra blocks are not empty, then we are
+                 * either on the last block(s) or we need more
+                 * user input before continuing.
+                 */
+                if (ctx->status & HASH_CTX_STS_LAST) {
+
+                        uint8_t *buf = ctx->partial_block_buffer;
+                        uint32_t n_extra_blocks = sha1_pad(buf, ctx->total_length);
+
+                        ctx->status = (HASH_CTX_STS_PROCESSING |
+                                       HASH_CTX_STS_COMPLETE);
+                        ctx->job.buffer = buf;
+                        ctx->job.len = (uint32_t) n_extra_blocks;
+                        ctx = (struct sha1_hash_ctx *) sha1_job_mgr_submit(&mgr->mgr, &ctx->job);
+                        continue;
+                }
+
+                if (ctx)
+                        ctx->status = HASH_CTX_STS_IDLE;
+                return ctx;
+        }
+
+        return NULL;
+}
+
+static struct sha1_hash_ctx *sha1_ctx_mgr_get_comp_ctx(struct sha1_ctx_mgr *mgr)
+{
+        /*
+         * If get_comp_job returns NULL, there are no jobs complete.
+         * If get_comp_job returns a job, verify that it is safe to return to the user.
+         * If it is not ready, resubmit the job to finish processing.
+         * If sha1_ctx_mgr_resubmit returned a job, it is ready to be returned.
+         * Otherwise, all jobs currently being managed by the hash_ctx_mgr still need processing.
+         */
+        struct sha1_hash_ctx *ctx;
+
+        ctx = (struct sha1_hash_ctx *) sha1_job_mgr_get_comp_job(&mgr->mgr);
+        return sha1_ctx_mgr_resubmit(mgr, ctx);
+}
+
+static void sha1_ctx_mgr_init(struct sha1_ctx_mgr *mgr)
+{
+        sha1_job_mgr_init(&mgr->mgr);
+}
+
+static struct sha1_hash_ctx *sha1_ctx_mgr_submit(struct sha1_ctx_mgr *mgr,
+                                          struct sha1_hash_ctx *ctx,
+                                          const void *buffer,
+                                          uint32_t len,
+                                          int flags)
+{
+        if (flags & (~HASH_ENTIRE)) {
+                /* User should not pass anything other than FIRST, UPDATE, or LAST */
+                ctx->error = HASH_CTX_ERROR_INVALID_FLAGS;
+                return ctx;
+        }
+
+        if (ctx->status & HASH_CTX_STS_PROCESSING) {
+                /* Cannot submit to a currently processing job. */
+                ctx->error = HASH_CTX_ERROR_ALREADY_PROCESSING;
+                return ctx;
+        }
+
+        if ((ctx->status & HASH_CTX_STS_COMPLETE) && !(flags & HASH_FIRST)) {
+                /* Cannot update a finished job. */
+                ctx->error = HASH_CTX_ERROR_ALREADY_COMPLETED;
+                return ctx;
+        }
+
+
+        if (flags & HASH_FIRST) {
+                /* Init digest */
+                sha1_init_digest(ctx->job.result_digest);
+
+                /* Reset byte counter */
+                ctx->total_length = 0;
+
+                /* Clear extra blocks */
+                ctx->partial_block_buffer_length = 0;
+        }
+
+        /* If we made it here, there were no errors during this call to submit */
+        ctx->error = HASH_CTX_ERROR_NONE;
+
+        /* Store buffer ptr info from user */
+        ctx->incoming_buffer = buffer;
+        ctx->incoming_buffer_length = len;
+
+        /* Store the user's request flags and mark this ctx as currently being processed. */
+        ctx->status = (flags & HASH_LAST) ?
+                        (HASH_CTX_STS_PROCESSING | HASH_CTX_STS_LAST) :
+                        HASH_CTX_STS_PROCESSING;
+
+        /* Advance byte counter */
+        ctx->total_length += len;
+
+        /*
+         * If there is anything currently buffered in the extra blocks,
+         * append to it until it contains a whole block.
+         * Or if the user's buffer contains less than a whole block,
+         * append as much as possible to the extra block.
+         */
+        if ((ctx->partial_block_buffer_length) | (len < SHA1_BLOCK_SIZE)) {
+                /* Compute how many bytes to copy from user buffer into extra block */
+                uint32_t copy_len = SHA1_BLOCK_SIZE - ctx->partial_block_buffer_length;
+                if (len < copy_len)
+                        copy_len = len;
+
+                if (copy_len) {
+                        /* Copy and update relevant pointers and counters */
+                        memcpy(&ctx->partial_block_buffer[ctx->partial_block_buffer_length],
+                                buffer, copy_len);
+
+                        ctx->partial_block_buffer_length += copy_len;
+                        ctx->incoming_buffer = (const void *)((const char *)buffer + copy_len);
+                        ctx->incoming_buffer_length = len - copy_len;
+                }
+
+                /* The extra block should never contain more than 1 block here */
+                assert(ctx->partial_block_buffer_length <= SHA1_BLOCK_SIZE);
+
+                /* If the extra block buffer contains exactly 1 block, it can be hashed. */
+                if (ctx->partial_block_buffer_length >= SHA1_BLOCK_SIZE) {
+                        ctx->partial_block_buffer_length = 0;
+
+                        ctx->job.buffer = ctx->partial_block_buffer;
+                        ctx->job.len = 1;
+                        ctx = (struct sha1_hash_ctx *) sha1_job_mgr_submit(&mgr->mgr, &ctx->job);
+                }
+        }
+
+        return sha1_ctx_mgr_resubmit(mgr, ctx);
+}
+
+static struct sha1_hash_ctx *sha1_ctx_mgr_flush(struct sha1_ctx_mgr *mgr)
+{
+        struct sha1_hash_ctx *ctx;
+
+        while (1) {
+                ctx = (struct sha1_hash_ctx *) sha1_job_mgr_flush(&mgr->mgr);
+
+                /* If flush returned 0, there are no more jobs in flight. */
+                if (!ctx)
+                        return NULL;
+
+                /*
+                 * If flush returned a job, resubmit the job to finish processing.
+                 */
+                ctx = sha1_ctx_mgr_resubmit(mgr, ctx);
+
+                /*
+                 * If sha1_ctx_mgr_resubmit returned a job, it is ready to be returned.
+                 * Otherwise, all jobs currently being managed by the sha1_ctx_mgr
+                 * still need processing. Loop.
+                 */
+                if (ctx)
+                        return ctx;
+        }
+}
+
+static int sha1_mb_init(struct shash_desc *desc)
+{
+        struct sha1_hash_ctx *sctx = shash_desc_ctx(desc);
+
+        hash_ctx_init(sctx);
+        sctx->job.result_digest[0] = SHA1_H0;
+        sctx->job.result_digest[1] = SHA1_H1;
+        sctx->job.result_digest[2] = SHA1_H2;
+        sctx->job.result_digest[3] = SHA1_H3;
+        sctx->job.result_digest[4] = SHA1_H4;
+        sctx->total_length = 0;
+        sctx->partial_block_buffer_length = 0;
+        sctx->status = HASH_CTX_STS_IDLE;
+
+        return 0;
+}
+
+static int sha1_mb_set_results(struct mcryptd_hash_request_ctx *rctx)
+{
+        int     i;
+        struct  sha1_hash_ctx *sctx = shash_desc_ctx(&rctx->desc);
+        __be32  *dst = (__be32 *) rctx->out;
+
+        for (i = 0; i < 5; ++i)
+                dst[i] = cpu_to_be32(sctx->job.result_digest[i]);
+
+        return 0;
+}
+
+static int sha_finish_walk(struct mcryptd_hash_request_ctx **ret_rctx,
+                        struct mcryptd_alg_cstate *cstate, bool flush)
+{
+        int     flag = HASH_UPDATE;
+        int     nbytes, err = 0;
+        struct mcryptd_hash_request_ctx *rctx = *ret_rctx;
+        struct sha1_hash_ctx *sha_ctx;
+
+        /* more work ? */
+        while (!(rctx->flag & HASH_DONE)) {
+                nbytes = crypto_ahash_walk_done(&rctx->walk, 0);
+                if (nbytes < 0) {
+                        err = nbytes;
+                        goto out;
+                }
+                /* check if the walk is done */
+                if (crypto_ahash_walk_last(&rctx->walk)) {
+                        rctx->flag |= HASH_DONE;
+                        if (rctx->flag & HASH_FINAL)
+                                flag |= HASH_LAST;
+
+                }
+                sha_ctx = (struct sha1_hash_ctx *) shash_desc_ctx(&rctx->desc);
+                kernel_fpu_begin();
+                sha_ctx = sha1_ctx_mgr_submit(cstate->mgr, sha_ctx, rctx->walk.data, nbytes, flag);
+                if (!sha_ctx) {
+                        if (flush)
+                                sha_ctx = sha1_ctx_mgr_flush(cstate->mgr);
+                }
+                kernel_fpu_end();
+                if (sha_ctx)
+                        rctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+                else {
+                        rctx = NULL;
+                        goto out;
+                }
+        }
+
+        /* copy the results */
+        if (rctx->flag & HASH_FINAL)
+                sha1_mb_set_results(rctx);
+
+out:
+        *ret_rctx = rctx;
+        return err;
+}
+
+static int sha_complete_job(struct mcryptd_hash_request_ctx *rctx,
+                            struct mcryptd_alg_cstate *cstate,
+                            int err)
+{
+        struct ahash_request *req = cast_mcryptd_ctx_to_req(rctx);
+        struct sha1_hash_ctx *sha_ctx;
+        struct mcryptd_hash_request_ctx *req_ctx;
+        int ret;
+
+        /* remove from work list */
+        spin_lock(&cstate->work_lock);
+        list_del(&rctx->waiter);
+        spin_unlock(&cstate->work_lock);
+
+        if (irqs_disabled())
+                rctx->complete(&req->base, err);
+        else {
+                local_bh_disable();
+                rctx->complete(&req->base, err);
+                local_bh_enable();
+        }
+
+        /* check to see if there are other jobs that are done */
+        sha_ctx = sha1_ctx_mgr_get_comp_ctx(cstate->mgr);
+        while (sha_ctx) {
+                req_ctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+                ret = sha_finish_walk(&req_ctx, cstate, false);
+                if (req_ctx) {
+                        spin_lock(&cstate->work_lock);
+                        list_del(&req_ctx->waiter);
+                        spin_unlock(&cstate->work_lock);
+
+                        req = cast_mcryptd_ctx_to_req(req_ctx);
+                        if (irqs_disabled())
+                                rctx->complete(&req->base, ret);
+                        else {
+                                local_bh_disable();
+                                rctx->complete(&req->base, ret);
+                                local_bh_enable();
+                        }
+                }
+                sha_ctx = sha1_ctx_mgr_get_comp_ctx(cstate->mgr);
+        }
+
+        return 0;
+}
+
+static void sha1_mb_add_list(struct mcryptd_hash_request_ctx *rctx,
+                             struct mcryptd_alg_cstate *cstate)
+{
+        unsigned long next_flush;
+        unsigned long delay = usecs_to_jiffies(FLUSH_INTERVAL);
+
+        /* initialize tag */
+        rctx->tag.arrival = jiffies;    /* tag the arrival time */
+        rctx->tag.seq_num = cstate->next_seq_num++;
+        next_flush = rctx->tag.arrival + delay;
+        rctx->tag.expire = next_flush;
+
+        spin_lock(&cstate->work_lock);
+        list_add_tail(&rctx->waiter, &cstate->work_list);
+        spin_unlock(&cstate->work_lock);
+
+        mcryptd_arm_flusher(cstate, delay);
+}
+
+static int sha1_mb_update(struct shash_desc *desc, const u8 *data,
+                          unsigned int len)
+{
+        struct mcryptd_hash_request_ctx *rctx =
+                        container_of(desc, struct mcryptd_hash_request_ctx, desc);
+        struct mcryptd_alg_cstate *cstate =
+                                this_cpu_ptr(sha1_mb_alg_state.alg_cstate);
+
+        struct ahash_request *req = cast_mcryptd_ctx_to_req(rctx);
+        struct sha1_hash_ctx *sha_ctx;
+        int ret = 0, nbytes;
+
+
+        /* sanity check */
+        if (rctx->tag.cpu != smp_processor_id()) {
+                pr_err("mcryptd error: cpu clash\n");
+                goto done;
+        }
+
+        /* need to init context */
+        req_ctx_init(rctx, desc);
+
+        nbytes = crypto_ahash_walk_first(req, &rctx->walk);
+
+        if (nbytes < 0) {
+                ret = nbytes;
+                goto done;
+        }
+
+        if (crypto_ahash_walk_last(&rctx->walk))
+                rctx->flag |= HASH_DONE;
+
+        /* submit */
+        sha_ctx = (struct sha1_hash_ctx *) shash_desc_ctx(desc);
+        sha1_mb_add_list(rctx, cstate);
+        kernel_fpu_begin();
+        sha_ctx = sha1_ctx_mgr_submit(cstate->mgr, sha_ctx, rctx->walk.data, nbytes, HASH_UPDATE);
+        kernel_fpu_end();
+
+        /* check if anything is returned */
+        if (!sha_ctx)
+                return -EINPROGRESS;
+
+        if (sha_ctx->error) {
+                ret = sha_ctx->error;
+                rctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+                goto done;
+        }
+
+        rctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+        ret = sha_finish_walk(&rctx, cstate, false);
+
+        if (!rctx)
+                return -EINPROGRESS;
+done:
+        sha_complete_job(rctx, cstate, ret);
+        return ret;
+}
+
+static int sha1_mb_finup(struct shash_desc *desc, const u8 *data,
+                             unsigned int len, u8 *out)
+{
+        struct mcryptd_hash_request_ctx *rctx =
+                        container_of(desc, struct mcryptd_hash_request_ctx, desc);
+        struct mcryptd_alg_cstate *cstate =
+                                this_cpu_ptr(sha1_mb_alg_state.alg_cstate);
+
+        struct ahash_request *req = cast_mcryptd_ctx_to_req(rctx);
+        struct sha1_hash_ctx *sha_ctx;
+        int ret = 0, flag = HASH_UPDATE, nbytes;
+
+        /* sanity check */
+        if (rctx->tag.cpu != smp_processor_id()) {
+                pr_err("mcryptd error: cpu clash\n");
+                goto done;
+        }
+
+        /* need to init context */
+        req_ctx_init(rctx, desc);
+
+        nbytes = crypto_ahash_walk_first(req, &rctx->walk);
+
+        if (nbytes < 0) {
+                ret = nbytes;
+                goto done;
+        }
+
+        if (crypto_ahash_walk_last(&rctx->walk)) {
+                rctx->flag |= HASH_DONE;
+                flag = HASH_LAST;
+        }
+        rctx->out = out;
+
+        /* submit */
+        rctx->flag |= HASH_FINAL;
+        sha_ctx = (struct sha1_hash_ctx *) shash_desc_ctx(desc);
+        sha1_mb_add_list(rctx, cstate);
+
+        kernel_fpu_begin();
+        sha_ctx = sha1_ctx_mgr_submit(cstate->mgr, sha_ctx, rctx->walk.data, nbytes, flag);
+        kernel_fpu_end();
+
+        /* check if anything is returned */
+        if (!sha_ctx)
+                return -EINPROGRESS;
+
+        if (sha_ctx->error) {
+                ret = sha_ctx->error;
+                goto done;
+        }
+
+        rctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+        ret = sha_finish_walk(&rctx, cstate, false);
+        if (!rctx)
+                return -EINPROGRESS;
+done:
+        sha_complete_job(rctx, cstate, ret);
+        return ret;
+}
+
+static int sha1_mb_final(struct shash_desc *desc, u8 *out)
+{
+        struct mcryptd_hash_request_ctx *rctx =
+                        container_of(desc, struct mcryptd_hash_request_ctx, desc);
+        struct mcryptd_alg_cstate *cstate =
+                                this_cpu_ptr(sha1_mb_alg_state.alg_cstate);
+
+        struct sha1_hash_ctx *sha_ctx;
+        int ret = 0;
+        u8 data;
+
+        /* sanity check */
+        if (rctx->tag.cpu != smp_processor_id()) {
+                pr_err("mcryptd error: cpu clash\n");
+                goto done;
+        }
+
+        /* need to init context */
+        req_ctx_init(rctx, desc);
+
+        rctx->out = out;
+        rctx->flag |= HASH_DONE | HASH_FINAL;
+
+        sha_ctx = (struct sha1_hash_ctx *) shash_desc_ctx(desc);
+        /* flag HASH_FINAL and 0 data size */
+        sha1_mb_add_list(rctx, cstate);
+        kernel_fpu_begin();
+        sha_ctx = sha1_ctx_mgr_submit(cstate->mgr, sha_ctx, &data, 0, HASH_LAST);
+        kernel_fpu_end();
+
+        /* check if anything is returned */
+        if (!sha_ctx)
+                return -EINPROGRESS;
+
+        if (sha_ctx->error) {
+                ret = sha_ctx->error;
+                rctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+                goto done;
+        }
+
+        rctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+        ret = sha_finish_walk(&rctx, cstate, false);
+        if (!rctx)
+                return -EINPROGRESS;
+done:
+        sha_complete_job(rctx, cstate, ret);
+        return ret;
+}
+
+static int sha1_mb_export(struct shash_desc *desc, void *out)
+{
+        struct sha1_hash_ctx *sctx = shash_desc_ctx(desc);
+
+        memcpy(out, sctx, sizeof(*sctx));
+
+        return 0;
+}
+
+static int sha1_mb_import(struct shash_desc *desc, const void *in)
+{
+        struct sha1_hash_ctx *sctx = shash_desc_ctx(desc);
+
+        memcpy(sctx, in, sizeof(*sctx));
+
+        return 0;
+}
+
+
+static struct shash_alg sha1_mb_shash_alg = {
+        .digestsize     =       SHA1_DIGEST_SIZE,
+        .init           =       sha1_mb_init,
+        .update         =       sha1_mb_update,
+        .final          =       sha1_mb_final,
+        .finup          =       sha1_mb_finup,
+        .export         =       sha1_mb_export,
+        .import         =       sha1_mb_import,
+        .descsize       =       sizeof(struct sha1_hash_ctx),
+        .statesize      =       sizeof(struct sha1_hash_ctx),
+        .base           =       {
+                .cra_name        = "__sha1-mb",
+                .cra_driver_name = "__intel_sha1-mb",
+                .cra_priority    = 100,
+                /*
+                 * use ASYNC flag as some buffers in multi-buffer
+                 * algo may not have completed before hashing thread sleep
+                 */
+                .cra_flags       = CRYPTO_ALG_TYPE_SHASH | CRYPTO_ALG_ASYNC,
+                .cra_blocksize   = SHA1_BLOCK_SIZE,
+                .cra_module      = THIS_MODULE,
+                .cra_list        = LIST_HEAD_INIT(sha1_mb_shash_alg.base.cra_list),
+        }
+};
+
+static int sha1_mb_async_init(struct ahash_request *req)
+{
+        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+        struct sha1_mb_ctx *ctx = crypto_ahash_ctx(tfm);
+        struct ahash_request *mcryptd_req = ahash_request_ctx(req);
+        struct mcryptd_ahash *mcryptd_tfm = ctx->mcryptd_tfm;
+
+        memcpy(mcryptd_req, req, sizeof(*req));
+        ahash_request_set_tfm(mcryptd_req, &mcryptd_tfm->base);
+        return crypto_ahash_init(mcryptd_req);
+}
+
+static int sha1_mb_async_update(struct ahash_request *req)
+{
+        struct ahash_request *mcryptd_req = ahash_request_ctx(req);
+
+        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+        struct sha1_mb_ctx *ctx = crypto_ahash_ctx(tfm);
+        struct mcryptd_ahash *mcryptd_tfm = ctx->mcryptd_tfm;
+
+        memcpy(mcryptd_req, req, sizeof(*req));
+        ahash_request_set_tfm(mcryptd_req, &mcryptd_tfm->base);
+        return crypto_ahash_update(mcryptd_req);
+}
+
+static int sha1_mb_async_finup(struct ahash_request *req)
+{
+        struct ahash_request *mcryptd_req = ahash_request_ctx(req);
+
+        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+        struct sha1_mb_ctx *ctx = crypto_ahash_ctx(tfm);
+        struct mcryptd_ahash *mcryptd_tfm = ctx->mcryptd_tfm;
+
+        memcpy(mcryptd_req, req, sizeof(*req));
+        ahash_request_set_tfm(mcryptd_req, &mcryptd_tfm->base);
+        return crypto_ahash_finup(mcryptd_req);
+}
+
+static int sha1_mb_async_final(struct ahash_request *req)
+{
+        struct ahash_request *mcryptd_req = ahash_request_ctx(req);
+
+        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+        struct sha1_mb_ctx *ctx = crypto_ahash_ctx(tfm);
+        struct mcryptd_ahash *mcryptd_tfm = ctx->mcryptd_tfm;
+
+        memcpy(mcryptd_req, req, sizeof(*req));
+        ahash_request_set_tfm(mcryptd_req, &mcryptd_tfm->base);
+        return crypto_ahash_final(mcryptd_req);
+}
+
+static int sha1_mb_async_digest(struct ahash_request *req)
+{
+        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+        struct sha1_mb_ctx *ctx = crypto_ahash_ctx(tfm);
+        struct ahash_request *mcryptd_req = ahash_request_ctx(req);
+        struct mcryptd_ahash *mcryptd_tfm = ctx->mcryptd_tfm;
+
+        memcpy(mcryptd_req, req, sizeof(*req));
+        ahash_request_set_tfm(mcryptd_req, &mcryptd_tfm->base);
+        return crypto_ahash_digest(mcryptd_req);
+}
+
+static int sha1_mb_async_init_tfm(struct crypto_tfm *tfm)
+{
+        struct mcryptd_ahash *mcryptd_tfm;
+        struct sha1_mb_ctx *ctx = crypto_tfm_ctx(tfm);
+        struct mcryptd_hash_ctx *mctx;
+
+        mcryptd_tfm = mcryptd_alloc_ahash("__intel_sha1-mb", 0, 0);
+        if (IS_ERR(mcryptd_tfm))
+                return PTR_ERR(mcryptd_tfm);
+        mctx = crypto_ahash_ctx(&mcryptd_tfm->base);
+        mctx->alg_state = &sha1_mb_alg_state;
+        ctx->mcryptd_tfm = mcryptd_tfm;
+        crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
+                                 sizeof(struct ahash_request) +
+                                 crypto_ahash_reqsize(&mcryptd_tfm->base));
+
+        return 0;
+}
+
+static void sha1_mb_async_exit_tfm(struct crypto_tfm *tfm)
+{
+        struct sha1_mb_ctx *ctx = crypto_tfm_ctx(tfm);
+
+        mcryptd_free_ahash(ctx->mcryptd_tfm);
+}
+
+static struct ahash_alg sha1_mb_async_alg = {
+        .init           = sha1_mb_async_init,
+        .update         = sha1_mb_async_update,
+        .final          = sha1_mb_async_final,
+        .finup          = sha1_mb_async_finup,
+        .digest         = sha1_mb_async_digest,
+        .halg = {
+                .digestsize     = SHA1_DIGEST_SIZE,
+                .base = {
+                        .cra_name               = "sha1",
+                        .cra_driver_name        = "sha1_mb",
+                        .cra_priority           = 200,
+                        .cra_flags              = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+                        .cra_blocksize          = SHA1_BLOCK_SIZE,
+                        .cra_type               = &crypto_ahash_type,
+                        .cra_module             = THIS_MODULE,
+                        .cra_list               = LIST_HEAD_INIT(sha1_mb_async_alg.halg.base.cra_list),
+                        .cra_init               = sha1_mb_async_init_tfm,
+                        .cra_exit               = sha1_mb_async_exit_tfm,
+                        .cra_ctxsize            = sizeof(struct sha1_mb_ctx),
+                        .cra_alignmask          = 0,
+                },
+        },
+};
+
+static unsigned long sha1_mb_flusher(struct mcryptd_alg_cstate *cstate)
+{
+        struct mcryptd_hash_request_ctx *rctx;
+        unsigned long cur_time;
+        unsigned long next_flush = 0;
+        struct sha1_hash_ctx *sha_ctx;
+
+
+        cur_time = jiffies;
+
+        while (!list_empty(&cstate->work_list)) {
+                rctx = list_entry(cstate->work_list.next,
+                                struct mcryptd_hash_request_ctx, waiter);
+                if time_before(cur_time, rctx->tag.expire)
+                        break;
+                kernel_fpu_begin();
+                sha_ctx = (struct sha1_hash_ctx *) sha1_ctx_mgr_flush(cstate->mgr);
+                kernel_fpu_end();
+                if (!sha_ctx) {
+                        pr_err("sha1_mb error: nothing got flushed for non-empty list\n");
+                        break;
+                }
+                rctx = cast_hash_to_mcryptd_ctx(sha_ctx);
+                sha_finish_walk(&rctx, cstate, true);
+                sha_complete_job(rctx, cstate, 0);
+        }
+
+        if (!list_empty(&cstate->work_list)) {
+                rctx = list_entry(cstate->work_list.next,
+                                struct mcryptd_hash_request_ctx, waiter);
+                /* get the hash context and then flush time */
+                next_flush = rctx->tag.expire;
+                mcryptd_arm_flusher(cstate, get_delay(next_flush));
+        }
+        return next_flush;
+}
+
+static int __init sha1_mb_mod_init(void)
+{
+
+        int cpu;
+        int err;
+        struct mcryptd_alg_cstate *cpu_state;
+
+        /* check for dependent cpu features */
+        if (!boot_cpu_has(X86_FEATURE_AVX2) ||
+            !boot_cpu_has(X86_FEATURE_BMI2))
+                return -ENODEV;
+
+        /* initialize multibuffer structures */
+        sha1_mb_alg_state.alg_cstate = alloc_percpu(struct mcryptd_alg_cstate);
+
+        sha1_job_mgr_init = sha1_mb_mgr_init_avx2;
+        sha1_job_mgr_submit = sha1_mb_mgr_submit_avx2;
+        sha1_job_mgr_flush = sha1_mb_mgr_flush_avx2;
+        sha1_job_mgr_get_comp_job = sha1_mb_mgr_get_comp_job_avx2;
+
+        if (!sha1_mb_alg_state.alg_cstate)
+                return -ENOMEM;
+        for_each_possible_cpu(cpu) {
+                cpu_state = per_cpu_ptr(sha1_mb_alg_state.alg_cstate, cpu);
+                cpu_state->next_flush = 0;
+                cpu_state->next_seq_num = 0;
+                cpu_state->flusher_engaged = false;
+                INIT_DELAYED_WORK(&cpu_state->flush, mcryptd_flusher);
+                cpu_state->cpu = cpu;
+                cpu_state->alg_state = &sha1_mb_alg_state;
+                cpu_state->mgr = (struct sha1_ctx_mgr *) kzalloc(sizeof(struct sha1_ctx_mgr), GFP_KERNEL);
+                if (!cpu_state->mgr)
+                        goto err2;
+                sha1_ctx_mgr_init(cpu_state->mgr);
+                INIT_LIST_HEAD(&cpu_state->work_list);
+                spin_lock_init(&cpu_state->work_lock);
+        }
+        sha1_mb_alg_state.flusher = &sha1_mb_flusher;
+
+        err = crypto_register_shash(&sha1_mb_shash_alg);
+        if (err)
+                goto err2;
+        err = crypto_register_ahash(&sha1_mb_async_alg);
+        if (err)
+                goto err1;
+
+
+        return 0;
+err1:
+        crypto_unregister_shash(&sha1_mb_shash_alg);
+err2:
+        for_each_possible_cpu(cpu) {
+                cpu_state = per_cpu_ptr(sha1_mb_alg_state.alg_cstate, cpu);
+                kfree(cpu_state->mgr);
+        }
+        free_percpu(sha1_mb_alg_state.alg_cstate);
+        return -ENODEV;
+}
+
+static void __exit sha1_mb_mod_fini(void)
+{
+        int cpu;
+        struct mcryptd_alg_cstate *cpu_state;
+
+        crypto_unregister_ahash(&sha1_mb_async_alg);
+        crypto_unregister_shash(&sha1_mb_shash_alg);
+        for_each_possible_cpu(cpu) {
+                cpu_state = per_cpu_ptr(sha1_mb_alg_state.alg_cstate, cpu);
+                kfree(cpu_state->mgr);
+        }
+        free_percpu(sha1_mb_alg_state.alg_cstate);
+}
+
+module_init(sha1_mb_mod_init);
+module_exit(sha1_mb_mod_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, multi buffer accelerated");
+
+MODULE_ALIAS("sha1");
diff --git a/arch/x86/crypto/sha-mb/sha1_mb_mgr_datastruct.S b/arch/x86/crypto/sha-mb/sha1_mb_mgr_datastruct.S
new file mode 100644
index 000000000000..86688c6e7a25
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha1_mb_mgr_datastruct.S
@@ -0,0 +1,287 @@
+/*
+ * Header file for multi buffer SHA1 algorithm data structure
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      James Guilford <james.guilford@intel.com>
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+# Macros for defining data structures
+
+# Usage example
+
+#START_FIELDS   # JOB_AES
+###     name            size    align
+#FIELD  _plaintext,     8,      8       # pointer to plaintext
+#FIELD  _ciphertext,    8,      8       # pointer to ciphertext
+#FIELD  _IV,            16,     8       # IV
+#FIELD  _keys,          8,      8       # pointer to keys
+#FIELD  _len,           4,      4       # length in bytes
+#FIELD  _status,        4,      4       # status enumeration
+#FIELD  _user_data,     8,      8       # pointer to user data
+#UNION  _union,         size1,  align1, \
+#                       size2,  align2, \
+#                       size3,  align3, \
+#                       ...
+#END_FIELDS
+#%assign _JOB_AES_size  _FIELD_OFFSET
+#%assign _JOB_AES_align _STRUCT_ALIGN
+
+#########################################################################
+
+# Alternate "struc-like" syntax:
+#       STRUCT job_aes2
+#       RES_Q   .plaintext,     1
+#       RES_Q   .ciphertext,    1
+#       RES_DQ  .IV,            1
+#       RES_B   .nested,        _JOB_AES_SIZE, _JOB_AES_ALIGN
+#       RES_U   .union,         size1, align1, \
+#                               size2, align2, \
+#                               ...
+#       ENDSTRUCT
+#       # Following only needed if nesting
+#       %assign job_aes2_size   _FIELD_OFFSET
+#       %assign job_aes2_align  _STRUCT_ALIGN
+#
+# RES_* macros take a name, a count and an optional alignment.
+# The count in in terms of the base size of the macro, and the
+# default alignment is the base size.
+# The macros are:
+# Macro    Base size
+# RES_B     1
+# RES_W     2
+# RES_D     4
+# RES_Q     8
+# RES_DQ   16
+# RES_Y    32
+# RES_Z    64
+#
+# RES_U defines a union. It's arguments are a name and two or more
+# pairs of "size, alignment"
+#
+# The two assigns are only needed if this structure is being nested
+# within another. Even if the assigns are not done, one can still use
+# STRUCT_NAME_size as the size of the structure.
+#
+# Note that for nesting, you still need to assign to STRUCT_NAME_size.
+#
+# The differences between this and using "struc" directly are that each
+# type is implicitly aligned to its natural length (although this can be
+# over-ridden with an explicit third parameter), and that the structure
+# is padded at the end to its overall alignment.
+#
+
+#########################################################################
+
+#ifndef _SHA1_MB_MGR_DATASTRUCT_ASM_
+#define _SHA1_MB_MGR_DATASTRUCT_ASM_
+
+## START_FIELDS
+.macro START_FIELDS
+ _FIELD_OFFSET = 0
+ _STRUCT_ALIGN = 0
+.endm
+
+## FIELD name size align
+.macro FIELD name size align
+ _FIELD_OFFSET = (_FIELD_OFFSET + (\align) - 1) & (~ ((\align)-1))
+ \name  = _FIELD_OFFSET
+ _FIELD_OFFSET = _FIELD_OFFSET + (\size)
+.if (\align > _STRUCT_ALIGN)
+ _STRUCT_ALIGN = \align
+.endif
+.endm
+
+## END_FIELDS
+.macro END_FIELDS
+ _FIELD_OFFSET = (_FIELD_OFFSET + _STRUCT_ALIGN-1) & (~ (_STRUCT_ALIGN-1))
+.endm
+
+########################################################################
+
+.macro STRUCT p1
+START_FIELDS
+.struc \p1
+.endm
+
+.macro ENDSTRUCT
+ tmp = _FIELD_OFFSET
+ END_FIELDS
+ tmp = (_FIELD_OFFSET - %%tmp)
+.if (tmp > 0)
+        .lcomm  tmp
+.endif
+.endstruc
+.endm
+
+## RES_int name size align
+.macro RES_int p1 p2 p3
+ name = \p1
+ size = \p2
+ align = .\p3
+
+ _FIELD_OFFSET = (_FIELD_OFFSET + (align) - 1) & (~ ((align)-1))
+.align align
+.lcomm name size
+ _FIELD_OFFSET = _FIELD_OFFSET + (size)
+.if (align > _STRUCT_ALIGN)
+ _STRUCT_ALIGN = align
+.endif
+.endm
+
+
+
+# macro RES_B name, size [, align]
+.macro RES_B _name, _size, _align=1
+RES_int _name _size _align
+.endm
+
+# macro RES_W name, size [, align]
+.macro RES_W _name, _size, _align=2
+RES_int _name 2*(_size) _align
+.endm
+
+# macro RES_D name, size [, align]
+.macro RES_D _name, _size, _align=4
+RES_int _name 4*(_size) _align
+.endm
+
+# macro RES_Q name, size [, align]
+.macro RES_Q _name, _size, _align=8
+RES_int _name 8*(_size) _align
+.endm
+
+# macro RES_DQ name, size [, align]
+.macro RES_DQ _name, _size, _align=16
+RES_int _name 16*(_size) _align
+.endm
+
+# macro RES_Y name, size [, align]
+.macro RES_Y _name, _size, _align=32
+RES_int _name 32*(_size) _align
+.endm
+
+# macro RES_Z name, size [, align]
+.macro RES_Z _name, _size, _align=64
+RES_int _name 64*(_size) _align
+.endm
+
+
+#endif
+
+########################################################################
+#### Define constants
+########################################################################
+
+########################################################################
+#### Define SHA1 Out Of Order Data Structures
+########################################################################
+
+START_FIELDS    # LANE_DATA
+###     name            size    align
+FIELD   _job_in_lane,   8,      8       # pointer to job object
+END_FIELDS
+
+_LANE_DATA_size = _FIELD_OFFSET
+_LANE_DATA_align = _STRUCT_ALIGN
+
+########################################################################
+
+START_FIELDS    # SHA1_ARGS_X8
+###     name            size    align
+FIELD   _digest,        4*5*8,  16      # transposed digest
+FIELD   _data_ptr,      8*8,    8       # array of pointers to data
+END_FIELDS
+
+_SHA1_ARGS_X4_size =     _FIELD_OFFSET
+_SHA1_ARGS_X4_align =    _STRUCT_ALIGN
+_SHA1_ARGS_X8_size =     _FIELD_OFFSET
+_SHA1_ARGS_X8_align =    _STRUCT_ALIGN
+
+########################################################################
+
+START_FIELDS    # MB_MGR
+###     name            size    align
+FIELD   _args,          _SHA1_ARGS_X4_size, _SHA1_ARGS_X4_align
+FIELD   _lens,          4*8,    8
+FIELD   _unused_lanes,  8,      8
+FIELD   _ldata,         _LANE_DATA_size*8, _LANE_DATA_align
+END_FIELDS
+
+_MB_MGR_size =   _FIELD_OFFSET
+_MB_MGR_align =  _STRUCT_ALIGN
+
+_args_digest    =     _args + _digest
+_args_data_ptr  =     _args + _data_ptr
+
+
+########################################################################
+#### Define constants
+########################################################################
+
+#define STS_UNKNOWN             0
+#define STS_BEING_PROCESSED     1
+#define STS_COMPLETED           2
+
+########################################################################
+#### Define JOB_SHA1 structure
+########################################################################
+
+START_FIELDS    # JOB_SHA1
+
+###     name                            size    align
+FIELD   _buffer,                        8,      8       # pointer to buffer
+FIELD   _len,                           4,      4       # length in bytes
+FIELD   _result_digest,                 5*4,    32      # Digest (output)
+FIELD   _status,                        4,      4
+FIELD   _user_data,                     8,      8
+END_FIELDS
+
+_JOB_SHA1_size =  _FIELD_OFFSET
+_JOB_SHA1_align = _STRUCT_ALIGN
diff --git a/arch/x86/crypto/sha-mb/sha1_mb_mgr_flush_avx2.S b/arch/x86/crypto/sha-mb/sha1_mb_mgr_flush_avx2.S
new file mode 100644
index 000000000000..85c4e1cf7172
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha1_mb_mgr_flush_avx2.S
@@ -0,0 +1,327 @@
+/*
+ * Flush routine for SHA1 multibuffer
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      James Guilford <james.guilford@intel.com>
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <linux/linkage.h>
+#include "sha1_mb_mgr_datastruct.S"
+
+
+.extern sha1_x8_avx2
+
+# LINUX register definitions
+#define arg1    %rdi
+#define arg2    %rsi
+
+# Common definitions
+#define state   arg1
+#define job     arg2
+#define len2    arg2
+
+# idx must be a register not clobbered by sha1_x8_avx2
+#define idx             %r8
+#define DWORD_idx       %r8d
+
+#define unused_lanes    %rbx
+#define lane_data       %rbx
+#define tmp2            %rbx
+#define tmp2_w          %ebx
+
+#define job_rax         %rax
+#define tmp1            %rax
+#define size_offset     %rax
+#define tmp             %rax
+#define start_offset    %rax
+
+#define tmp3            %arg1
+
+#define extra_blocks    %arg2
+#define p               %arg2
+
+
+# STACK_SPACE needs to be an odd multiple of 8
+_XMM_SAVE_SIZE  = 10*16
+_GPR_SAVE_SIZE  = 8*8
+_ALIGN_SIZE     = 8
+
+_XMM_SAVE       = 0
+_GPR_SAVE       = _XMM_SAVE + _XMM_SAVE_SIZE
+STACK_SPACE     = _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
+
+.macro LABEL prefix n
+\prefix\n\():
+.endm
+
+.macro JNE_SKIP i
+jne     skip_\i
+.endm
+
+.altmacro
+.macro SET_OFFSET _offset
+offset = \_offset
+.endm
+.noaltmacro
+
+# JOB* sha1_mb_mgr_flush_avx2(MB_MGR *state)
+# arg 1 : rcx : state
+ENTRY(sha1_mb_mgr_flush_avx2)
+        mov     %rsp, %r10
+        sub     $STACK_SPACE, %rsp
+        and     $~31, %rsp
+        mov     %rbx, _GPR_SAVE(%rsp)
+        mov     %r10, _GPR_SAVE+8*1(%rsp) #save rsp
+        mov     %rbp, _GPR_SAVE+8*3(%rsp)
+        mov     %r12, _GPR_SAVE+8*4(%rsp)
+        mov     %r13, _GPR_SAVE+8*5(%rsp)
+        mov     %r14, _GPR_SAVE+8*6(%rsp)
+        mov     %r15, _GPR_SAVE+8*7(%rsp)
+
+        # If bit (32+3) is set, then all lanes are empty
+        mov     _unused_lanes(state), unused_lanes
+        bt      $32+3, unused_lanes
+        jc      return_null
+
+        # find a lane with a non-null job
+        xor     idx, idx
+        offset = (_ldata + 1 * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+        cmovne  one(%rip), idx
+        offset = (_ldata + 2 * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+        cmovne  two(%rip), idx
+        offset = (_ldata + 3 * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+        cmovne  three(%rip), idx
+        offset = (_ldata + 4 * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+        cmovne  four(%rip), idx
+        offset = (_ldata + 5 * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+        cmovne  five(%rip), idx
+        offset = (_ldata + 6 * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+        cmovne  six(%rip), idx
+        offset = (_ldata + 7 * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+        cmovne  seven(%rip), idx
+
+        # copy idx to empty lanes
+copy_lane_data:
+        offset =  (_args + _data_ptr)
+        mov     offset(state,idx,8), tmp
+
+        I = 0
+.rep 8
+        offset =  (_ldata + I * _LANE_DATA_size + _job_in_lane)
+        cmpq    $0, offset(state)
+.altmacro
+        JNE_SKIP %I
+        offset =  (_args + _data_ptr + 8*I)
+        mov     tmp, offset(state)
+        offset =  (_lens + 4*I)
+        movl    $0xFFFFFFFF, offset(state)
+LABEL skip_ %I
+        I = (I+1)
+.noaltmacro
+.endr
+
+        # Find min length
+        vmovdqa _lens+0*16(state), %xmm0
+        vmovdqa _lens+1*16(state), %xmm1
+
+        vpminud %xmm1, %xmm0, %xmm2     # xmm2 has {D,C,B,A}
+        vpalignr $8, %xmm2, %xmm3, %xmm3   # xmm3 has {x,x,D,C}
+        vpminud %xmm3, %xmm2, %xmm2        # xmm2 has {x,x,E,F}
+        vpalignr $4, %xmm2, %xmm3, %xmm3    # xmm3 has {x,x,x,E}
+        vpminud %xmm3, %xmm2, %xmm2        # xmm2 has min value in low dword
+
+        vmovd   %xmm2, DWORD_idx
+        mov     idx, len2
+        and     $0xF, idx
+        shr     $4, len2
+        jz      len_is_0
+
+        vpand   clear_low_nibble(%rip), %xmm2, %xmm2
+        vpshufd $0, %xmm2, %xmm2
+
+        vpsubd  %xmm2, %xmm0, %xmm0
+        vpsubd  %xmm2, %xmm1, %xmm1
+
+        vmovdqa %xmm0, _lens+0*16(state)
+        vmovdqa %xmm1, _lens+1*16(state)
+
+        # "state" and "args" are the same address, arg1
+        # len is arg2
+        call    sha1_x8_avx2
+        # state and idx are intact
+
+
+len_is_0:
+        # process completed job "idx"
+        imul    $_LANE_DATA_size, idx, lane_data
+        lea     _ldata(state, lane_data), lane_data
+
+        mov     _job_in_lane(lane_data), job_rax
+        movq    $0, _job_in_lane(lane_data)
+        movl    $STS_COMPLETED, _status(job_rax)
+        mov     _unused_lanes(state), unused_lanes
+        shl     $4, unused_lanes
+        or      idx, unused_lanes
+        mov     unused_lanes, _unused_lanes(state)
+
+        movl    $0xFFFFFFFF, _lens(state, idx, 4)
+
+        vmovd    _args_digest(state , idx, 4) , %xmm0
+        vpinsrd  $1, _args_digest+1*32(state, idx, 4), %xmm0, %xmm0
+        vpinsrd  $2, _args_digest+2*32(state, idx, 4), %xmm0, %xmm0
+        vpinsrd  $3, _args_digest+3*32(state, idx, 4), %xmm0, %xmm0
+        movl    _args_digest+4*32(state, idx, 4), tmp2_w
+
+        vmovdqu  %xmm0, _result_digest(job_rax)
+        offset =  (_result_digest + 1*16)
+        mov     tmp2_w, offset(job_rax)
+
+return:
+
+        mov     _GPR_SAVE(%rsp), %rbx
+        mov     _GPR_SAVE+8*1(%rsp), %r10 #saved rsp
+        mov     _GPR_SAVE+8*3(%rsp), %rbp
+        mov     _GPR_SAVE+8*4(%rsp), %r12
+        mov     _GPR_SAVE+8*5(%rsp), %r13
+        mov     _GPR_SAVE+8*6(%rsp), %r14
+        mov     _GPR_SAVE+8*7(%rsp), %r15
+        mov     %r10, %rsp
+
+        ret
+
+return_null:
+        xor     job_rax, job_rax
+        jmp     return
+ENDPROC(sha1_mb_mgr_flush_avx2)
+
+
+#################################################################
+
+.align 16
+ENTRY(sha1_mb_mgr_get_comp_job_avx2)
+        push    %rbx
+
+        ## if bit 32+3 is set, then all lanes are empty
+        mov     _unused_lanes(state), unused_lanes
+        bt      $(32+3), unused_lanes
+        jc      .return_null
+
+        # Find min length
+        vmovdqa _lens(state), %xmm0
+        vmovdqa _lens+1*16(state), %xmm1
+
+        vpminud %xmm1, %xmm0, %xmm2        # xmm2 has {D,C,B,A}
+        vpalignr $8, %xmm2, %xmm3, %xmm3   # xmm3 has {x,x,D,C}
+        vpminud %xmm3, %xmm2, %xmm2        # xmm2 has {x,x,E,F}
+        vpalignr $4, %xmm2, %xmm3, %xmm3    # xmm3 has {x,x,x,E}
+        vpminud %xmm3, %xmm2, %xmm2        # xmm2 has min value in low dword
+
+        vmovd   %xmm2, DWORD_idx
+        test    $~0xF, idx
+        jnz     .return_null
+
+        # process completed job "idx"
+        imul    $_LANE_DATA_size, idx, lane_data
+        lea     _ldata(state, lane_data), lane_data
+
+        mov     _job_in_lane(lane_data), job_rax
+        movq    $0,  _job_in_lane(lane_data)
+        movl    $STS_COMPLETED, _status(job_rax)
+        mov     _unused_lanes(state), unused_lanes
+        shl     $4, unused_lanes
+        or      idx, unused_lanes
+        mov     unused_lanes, _unused_lanes(state)
+
+        movl    $0xFFFFFFFF, _lens(state,  idx, 4)
+
+        vmovd   _args_digest(state, idx, 4), %xmm0
+        vpinsrd $1, _args_digest+1*32(state, idx, 4), %xmm0, %xmm0
+        vpinsrd $2, _args_digest+2*32(state, idx, 4), %xmm0, %xmm0
+        vpinsrd $3, _args_digest+3*32(state, idx, 4), %xmm0, %xmm0
+        movl    _args_digest+4*32(state, idx, 4), tmp2_w
+
+        vmovdqu %xmm0, _result_digest(job_rax)
+        movl    tmp2_w, _result_digest+1*16(job_rax)
+
+        pop     %rbx
+
+        ret
+
+.return_null:
+        xor     job_rax, job_rax
+        pop     %rbx
+        ret
+ENDPROC(sha1_mb_mgr_get_comp_job_avx2)
+
+.data
+
+.align 16
+clear_low_nibble:
+.octa   0x000000000000000000000000FFFFFFF0
+one:
+.quad  1
+two:
+.quad  2
+three:
+.quad  3
+four:
+.quad  4
+five:
+.quad  5
+six:
+.quad  6
+seven:
+.quad  7
diff --git a/arch/x86/crypto/sha-mb/sha1_mb_mgr_init_avx2.c b/arch/x86/crypto/sha-mb/sha1_mb_mgr_init_avx2.c
new file mode 100644
index 000000000000..4ca7e166a2aa
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha1_mb_mgr_init_avx2.c
@@ -0,0 +1,64 @@
+/*
+ * Initialization code for multi buffer SHA1 algorithm for AVX2
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sha_mb_mgr.h"
+
+void sha1_mb_mgr_init_avx2(struct sha1_mb_mgr *state)
+{
+        unsigned int j;
+        state->unused_lanes = 0xF76543210;
+        for (j = 0; j < 8; j++) {
+                state->lens[j] = 0xFFFFFFFF;
+                state->ldata[j].job_in_lane = NULL;
+        }
+}
diff --git a/arch/x86/crypto/sha-mb/sha1_mb_mgr_submit_avx2.S b/arch/x86/crypto/sha-mb/sha1_mb_mgr_submit_avx2.S
new file mode 100644
index 000000000000..2ab9560b53c8
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha1_mb_mgr_submit_avx2.S
@@ -0,0 +1,228 @@
+/*
+ * Buffer submit code for multi buffer SHA1 algorithm
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      James Guilford <james.guilford@intel.com>
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/linkage.h>
+#include "sha1_mb_mgr_datastruct.S"
+
+
+.extern sha1_x8_avx
+
+# LINUX register definitions
+arg1    = %rdi
+arg2    = %rsi
+size_offset     = %rcx
+tmp2            = %rcx
+extra_blocks    = %rdx
+
+# Common definitions
+#define state   arg1
+#define job     %rsi
+#define len2    arg2
+#define p2      arg2
+
+# idx must be a register not clobberred by sha1_x8_avx2
+idx             = %r8
+DWORD_idx       = %r8d
+last_len        = %r8
+
+p               = %r11
+start_offset    = %r11
+
+unused_lanes    = %rbx
+BYTE_unused_lanes = %bl
+
+job_rax         = %rax
+len             = %rax
+DWORD_len       = %eax
+
+lane            = %rbp
+tmp3            = %rbp
+
+tmp             = %r9
+DWORD_tmp       = %r9d
+
+lane_data       = %r10
+
+# STACK_SPACE needs to be an odd multiple of 8
+STACK_SPACE     = 8*8 + 16*10 + 8
+
+# JOB* submit_mb_mgr_submit_avx2(MB_MGR *state, job_sha1 *job)
+# arg 1 : rcx : state
+# arg 2 : rdx : job
+ENTRY(sha1_mb_mgr_submit_avx2)
+
+        mov     %rsp, %r10
+        sub     $STACK_SPACE, %rsp
+        and     $~31, %rsp
+
+        mov     %rbx, (%rsp)
+        mov     %r10, 8*2(%rsp) #save old rsp
+        mov     %rbp, 8*3(%rsp)
+        mov     %r12, 8*4(%rsp)
+        mov     %r13, 8*5(%rsp)
+        mov     %r14, 8*6(%rsp)
+        mov     %r15, 8*7(%rsp)
+
+        mov     _unused_lanes(state), unused_lanes
+        mov     unused_lanes, lane
+        and     $0xF, lane
+        shr     $4, unused_lanes
+        imul    $_LANE_DATA_size, lane, lane_data
+        movl    $STS_BEING_PROCESSED, _status(job)
+        lea     _ldata(state, lane_data), lane_data
+        mov     unused_lanes, _unused_lanes(state)
+        movl    _len(job),  DWORD_len
+
+        mov     job, _job_in_lane(lane_data)
+        shl     $4, len
+        or      lane, len
+
+        movl    DWORD_len,  _lens(state , lane, 4)
+
+        # Load digest words from result_digest
+        vmovdqu _result_digest(job), %xmm0
+        mov     _result_digest+1*16(job), DWORD_tmp
+        vmovd    %xmm0, _args_digest(state, lane, 4)
+        vpextrd  $1, %xmm0, _args_digest+1*32(state , lane, 4)
+        vpextrd  $2, %xmm0, _args_digest+2*32(state , lane, 4)
+        vpextrd  $3, %xmm0, _args_digest+3*32(state , lane, 4)
+        movl    DWORD_tmp, _args_digest+4*32(state , lane, 4)
+
+        mov     _buffer(job), p
+        mov     p, _args_data_ptr(state, lane, 8)
+
+        cmp     $0xF, unused_lanes
+        jne     return_null
+
+start_loop:
+        # Find min length
+        vmovdqa _lens(state), %xmm0
+        vmovdqa _lens+1*16(state), %xmm1
+
+        vpminud %xmm1, %xmm0, %xmm2        # xmm2 has {D,C,B,A}
+        vpalignr $8, %xmm2, %xmm3, %xmm3   # xmm3 has {x,x,D,C}
+        vpminud %xmm3, %xmm2, %xmm2        # xmm2 has {x,x,E,F}
+        vpalignr $4, %xmm2, %xmm3, %xmm3   # xmm3 has {x,x,x,E}
+        vpminud %xmm3, %xmm2, %xmm2        # xmm2 has min value in low dword
+
+        vmovd   %xmm2, DWORD_idx
+        mov    idx, len2
+        and    $0xF, idx
+        shr    $4, len2
+        jz     len_is_0
+
+        vpand   clear_low_nibble(%rip), %xmm2, %xmm2
+        vpshufd $0, %xmm2, %xmm2
+
+        vpsubd  %xmm2, %xmm0, %xmm0
+        vpsubd  %xmm2, %xmm1, %xmm1
+
+        vmovdqa %xmm0, _lens + 0*16(state)
+        vmovdqa %xmm1, _lens + 1*16(state)
+
+
+        # "state" and "args" are the same address, arg1
+        # len is arg2
+        call    sha1_x8_avx2
+
+        # state and idx are intact
+
+len_is_0:
+        # process completed job "idx"
+        imul    $_LANE_DATA_size, idx, lane_data
+        lea     _ldata(state, lane_data), lane_data
+
+        mov     _job_in_lane(lane_data), job_rax
+        mov     _unused_lanes(state), unused_lanes
+        movq    $0, _job_in_lane(lane_data)
+        movl    $STS_COMPLETED, _status(job_rax)
+        shl     $4, unused_lanes
+        or      idx, unused_lanes
+        mov     unused_lanes, _unused_lanes(state)
+
+        movl    $0xFFFFFFFF, _lens(state, idx, 4)
+
+        vmovd    _args_digest(state, idx, 4), %xmm0
+        vpinsrd  $1, _args_digest+1*32(state , idx, 4), %xmm0, %xmm0
+        vpinsrd  $2, _args_digest+2*32(state , idx, 4), %xmm0, %xmm0
+        vpinsrd  $3, _args_digest+3*32(state , idx, 4), %xmm0, %xmm0
+        movl    4*32(state, idx, 4), DWORD_tmp
+
+        vmovdqu  %xmm0, _result_digest(job_rax)
+        movl    DWORD_tmp, _result_digest+1*16(job_rax)
+
+return:
+
+        mov     (%rsp), %rbx
+        mov     8*2(%rsp), %r10 #save old rsp
+        mov     8*3(%rsp), %rbp
+        mov     8*4(%rsp), %r12
+        mov     8*5(%rsp), %r13
+        mov     8*6(%rsp), %r14
+        mov     8*7(%rsp), %r15
+        mov     %r10, %rsp
+
+        ret
+
+return_null:
+        xor     job_rax, job_rax
+        jmp     return
+
+ENDPROC(sha1_mb_mgr_submit_avx2)
+
+.data
+
+.align 16
+clear_low_nibble:
+        .octa   0x000000000000000000000000FFFFFFF0
diff --git a/arch/x86/crypto/sha-mb/sha1_x8_avx2.S b/arch/x86/crypto/sha-mb/sha1_x8_avx2.S
new file mode 100644
index 000000000000..8e1b47792b31
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha1_x8_avx2.S
@@ -0,0 +1,472 @@
+/*
+ * Multi-buffer SHA1 algorithm hash compute routine
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      James Guilford <james.guilford@intel.com>
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/linkage.h>
+#include "sha1_mb_mgr_datastruct.S"
+
+## code to compute oct SHA1 using SSE-256
+## outer calling routine takes care of save and restore of XMM registers
+
+## Function clobbers: rax, rcx, rdx,   rbx, rsi, rdi, r9-r15# ymm0-15
+##
+## Linux clobbers:    rax rbx rcx rdx rsi            r9 r10 r11 r12 r13 r14 r15
+## Linux preserves:                       rdi rbp r8
+##
+## clobbers ymm0-15
+
+
+# TRANSPOSE8 r0, r1, r2, r3, r4, r5, r6, r7, t0, t1
+# "transpose" data in {r0...r7} using temps {t0...t1}
+# Input looks like: {r0 r1 r2 r3 r4 r5 r6 r7}
+# r0 = {a7 a6 a5 a4   a3 a2 a1 a0}
+# r1 = {b7 b6 b5 b4   b3 b2 b1 b0}
+# r2 = {c7 c6 c5 c4   c3 c2 c1 c0}
+# r3 = {d7 d6 d5 d4   d3 d2 d1 d0}
+# r4 = {e7 e6 e5 e4   e3 e2 e1 e0}
+# r5 = {f7 f6 f5 f4   f3 f2 f1 f0}
+# r6 = {g7 g6 g5 g4   g3 g2 g1 g0}
+# r7 = {h7 h6 h5 h4   h3 h2 h1 h0}
+#
+# Output looks like: {r0 r1 r2 r3 r4 r5 r6 r7}
+# r0 = {h0 g0 f0 e0   d0 c0 b0 a0}
+# r1 = {h1 g1 f1 e1   d1 c1 b1 a1}
+# r2 = {h2 g2 f2 e2   d2 c2 b2 a2}
+# r3 = {h3 g3 f3 e3   d3 c3 b3 a3}
+# r4 = {h4 g4 f4 e4   d4 c4 b4 a4}
+# r5 = {h5 g5 f5 e5   d5 c5 b5 a5}
+# r6 = {h6 g6 f6 e6   d6 c6 b6 a6}
+# r7 = {h7 g7 f7 e7   d7 c7 b7 a7}
+#
+
+.macro TRANSPOSE8 r0 r1 r2 r3 r4 r5 r6 r7 t0 t1
+        # process top half (r0..r3) {a...d}
+        vshufps  $0x44, \r1, \r0, \t0 # t0 = {b5 b4 a5 a4   b1 b0 a1 a0}
+        vshufps  $0xEE, \r1, \r0, \r0 # r0 = {b7 b6 a7 a6   b3 b2 a3 a2}
+        vshufps  $0x44, \r3, \r2, \t1 # t1 = {d5 d4 c5 c4   d1 d0 c1 c0}
+        vshufps  $0xEE, \r3, \r2, \r2 # r2 = {d7 d6 c7 c6   d3 d2 c3 c2}
+        vshufps  $0xDD, \t1, \t0, \r3 # r3 = {d5 c5 b5 a5   d1 c1 b1 a1}
+        vshufps  $0x88, \r2, \r0, \r1 # r1 = {d6 c6 b6 a6   d2 c2 b2 a2}
+        vshufps  $0xDD, \r2, \r0, \r0 # r0 = {d7 c7 b7 a7   d3 c3 b3 a3}
+        vshufps  $0x88, \t1, \t0, \t0 # t0 = {d4 c4 b4 a4   d0 c0 b0 a0}
+
+        # use r2 in place of t0
+        # process bottom half (r4..r7) {e...h}
+        vshufps  $0x44, \r5, \r4, \r2 # r2 = {f5 f4 e5 e4   f1 f0 e1 e0}
+        vshufps  $0xEE, \r5, \r4, \r4 # r4 = {f7 f6 e7 e6   f3 f2 e3 e2}
+        vshufps  $0x44, \r7, \r6, \t1 # t1 = {h5 h4 g5 g4   h1 h0 g1 g0}
+        vshufps  $0xEE, \r7, \r6, \r6 # r6 = {h7 h6 g7 g6   h3 h2 g3 g2}
+        vshufps  $0xDD, \t1, \r2, \r7 # r7 = {h5 g5 f5 e5   h1 g1 f1 e1}
+        vshufps  $0x88, \r6, \r4, \r5 # r5 = {h6 g6 f6 e6   h2 g2 f2 e2}
+        vshufps  $0xDD, \r6, \r4, \r4 # r4 = {h7 g7 f7 e7   h3 g3 f3 e3}
+        vshufps  $0x88, \t1, \r2, \t1 # t1 = {h4 g4 f4 e4   h0 g0 f0 e0}
+
+        vperm2f128      $0x13, \r1, \r5, \r6  # h6...a6
+        vperm2f128      $0x02, \r1, \r5, \r2  # h2...a2
+        vperm2f128      $0x13, \r3, \r7, \r5  # h5...a5
+        vperm2f128      $0x02, \r3, \r7, \r1  # h1...a1
+        vperm2f128      $0x13, \r0, \r4, \r7  # h7...a7
+        vperm2f128      $0x02, \r0, \r4, \r3  # h3...a3
+        vperm2f128      $0x13, \t0, \t1, \r4  # h4...a4
+        vperm2f128      $0x02, \t0, \t1, \r0  # h0...a0
+
+.endm
+##
+## Magic functions defined in FIPS 180-1
+##
+# macro MAGIC_F0 F,B,C,D,T   ## F = (D ^ (B & (C ^ D)))
+.macro MAGIC_F0 regF regB regC regD regT
+    vpxor \regD, \regC, \regF
+    vpand \regB, \regF, \regF
+    vpxor \regD, \regF, \regF
+.endm
+
+# macro MAGIC_F1 F,B,C,D,T   ## F = (B ^ C ^ D)
+.macro MAGIC_F1 regF regB regC regD regT
+    vpxor  \regC, \regD, \regF
+    vpxor  \regB, \regF, \regF
+.endm
+
+# macro MAGIC_F2 F,B,C,D,T   ## F = ((B & C) | (B & D) | (C & D))
+.macro MAGIC_F2 regF regB regC regD regT
+    vpor  \regC, \regB, \regF
+    vpand \regC, \regB, \regT
+    vpand \regD, \regF, \regF
+    vpor  \regT, \regF, \regF
+.endm
+
+# macro MAGIC_F3 F,B,C,D,T   ## F = (B ^ C ^ D)
+.macro MAGIC_F3 regF regB regC regD regT
+    MAGIC_F1 \regF,\regB,\regC,\regD,\regT
+.endm
+
+# PROLD reg, imm, tmp
+.macro PROLD reg imm tmp
+        vpsrld  $(32-\imm), \reg, \tmp
+        vpslld  $\imm, \reg, \reg
+        vpor    \tmp, \reg, \reg
+.endm
+
+.macro PROLD_nd reg imm tmp src
+        vpsrld  $(32-\imm), \src, \tmp
+        vpslld  $\imm, \src, \reg
+        vpor    \tmp, \reg, \reg
+.endm
+
+.macro SHA1_STEP_00_15 regA regB regC regD regE regT regF memW immCNT MAGIC
+        vpaddd  \immCNT, \regE, \regE
+        vpaddd  \memW*32(%rsp), \regE, \regE
+        PROLD_nd \regT, 5, \regF, \regA
+        vpaddd  \regT, \regE, \regE
+        \MAGIC  \regF, \regB, \regC, \regD, \regT
+        PROLD   \regB, 30, \regT
+        vpaddd  \regF, \regE, \regE
+.endm
+
+.macro SHA1_STEP_16_79 regA regB regC regD regE regT regF memW immCNT MAGIC
+        vpaddd  \immCNT, \regE, \regE
+        offset = ((\memW - 14) & 15) * 32
+        vmovdqu offset(%rsp), W14
+        vpxor   W14, W16, W16
+        offset = ((\memW -  8) & 15) * 32
+        vpxor   offset(%rsp), W16, W16
+        offset = ((\memW -  3) & 15) * 32
+        vpxor   offset(%rsp), W16, W16
+        vpsrld  $(32-1), W16, \regF
+        vpslld  $1, W16, W16
+        vpor    W16, \regF, \regF
+
+        ROTATE_W
+
+        offset = ((\memW - 0) & 15) * 32
+        vmovdqu \regF, offset(%rsp)
+        vpaddd  \regF, \regE, \regE
+        PROLD_nd \regT, 5, \regF, \regA
+        vpaddd  \regT, \regE, \regE
+        \MAGIC \regF,\regB,\regC,\regD,\regT      ## FUN  = MAGIC_Fi(B,C,D)
+        PROLD   \regB,30, \regT
+        vpaddd  \regF, \regE, \regE
+.endm
+
+########################################################################
+########################################################################
+########################################################################
+
+## FRAMESZ plus pushes must be an odd multiple of 8
+YMM_SAVE = (15-15)*32
+FRAMESZ = 32*16 + YMM_SAVE
+_YMM  =   FRAMESZ - YMM_SAVE
+
+#define VMOVPS   vmovups
+
+IDX  = %rax
+inp0 = %r9
+inp1 = %r10
+inp2 = %r11
+inp3 = %r12
+inp4 = %r13
+inp5 = %r14
+inp6 = %r15
+inp7 = %rcx
+arg1 = %rdi
+arg2 = %rsi
+RSP_SAVE = %rdx
+
+# ymm0 A
+# ymm1 B
+# ymm2 C
+# ymm3 D
+# ymm4 E
+# ymm5         F       AA
+# ymm6         T0      BB
+# ymm7         T1      CC
+# ymm8         T2      DD
+# ymm9         T3      EE
+# ymm10                T4      TMP
+# ymm11                T5      FUN
+# ymm12                T6      K
+# ymm13                T7      W14
+# ymm14                T8      W15
+# ymm15                T9      W16
+
+
+A  =     %ymm0
+B  =     %ymm1
+C  =     %ymm2
+D  =     %ymm3
+E  =     %ymm4
+F  =     %ymm5
+T0 =     %ymm6
+T1 =     %ymm7
+T2 =     %ymm8
+T3 =     %ymm9
+T4 =     %ymm10
+T5 =     %ymm11
+T6 =     %ymm12
+T7 =     %ymm13
+T8  =     %ymm14
+T9  =     %ymm15
+
+AA  =     %ymm5
+BB  =     %ymm6
+CC  =     %ymm7
+DD  =     %ymm8
+EE  =     %ymm9
+TMP =     %ymm10
+FUN =     %ymm11
+K   =     %ymm12
+W14 =     %ymm13
+W15 =     %ymm14
+W16 =     %ymm15
+
+.macro ROTATE_ARGS
+ TMP_ = E
+ E = D
+ D = C
+ C = B
+ B = A
+ A = TMP_
+.endm
+
+.macro ROTATE_W
+TMP_  = W16
+W16  = W15
+W15  = W14
+W14  = TMP_
+.endm
+
+# 8 streams x 5 32bit words per digest x 4 bytes per word
+#define DIGEST_SIZE (8*5*4)
+
+.align 32
+
+# void sha1_x8_avx2(void **input_data, UINT128 *digest, UINT32 size)
+# arg 1 : pointer to array[4] of pointer to input data
+# arg 2 : size (in blocks) ;; assumed to be >= 1
+#
+ENTRY(sha1_x8_avx2)
+
+        push    RSP_SAVE
+
+        #save rsp
+        mov     %rsp, RSP_SAVE
+        sub     $FRAMESZ, %rsp
+
+        #align rsp to 32 Bytes
+        and     $~0x1F, %rsp
+
+        ## Initialize digests
+        vmovdqu  0*32(arg1), A
+        vmovdqu  1*32(arg1), B
+        vmovdqu  2*32(arg1), C
+        vmovdqu  3*32(arg1), D
+        vmovdqu  4*32(arg1), E
+
+        ## transpose input onto stack
+        mov     _data_ptr+0*8(arg1),inp0
+        mov     _data_ptr+1*8(arg1),inp1
+        mov     _data_ptr+2*8(arg1),inp2
+        mov     _data_ptr+3*8(arg1),inp3
+        mov     _data_ptr+4*8(arg1),inp4
+        mov     _data_ptr+5*8(arg1),inp5
+        mov     _data_ptr+6*8(arg1),inp6
+        mov     _data_ptr+7*8(arg1),inp7
+
+        xor     IDX, IDX
+lloop:
+        vmovdqu  PSHUFFLE_BYTE_FLIP_MASK(%rip), F
+        I=0
+.rep 2
+        VMOVPS   (inp0, IDX), T0
+        VMOVPS   (inp1, IDX), T1
+        VMOVPS   (inp2, IDX), T2
+        VMOVPS   (inp3, IDX), T3
+        VMOVPS   (inp4, IDX), T4
+        VMOVPS   (inp5, IDX), T5
+        VMOVPS   (inp6, IDX), T6
+        VMOVPS   (inp7, IDX), T7
+
+        TRANSPOSE8       T0, T1, T2, T3, T4, T5, T6, T7, T8, T9
+        vpshufb  F, T0, T0
+        vmovdqu  T0, (I*8)*32(%rsp)
+        vpshufb  F, T1, T1
+        vmovdqu  T1, (I*8+1)*32(%rsp)
+        vpshufb  F, T2, T2
+        vmovdqu  T2, (I*8+2)*32(%rsp)
+        vpshufb  F, T3, T3
+        vmovdqu  T3, (I*8+3)*32(%rsp)
+        vpshufb  F, T4, T4
+        vmovdqu  T4, (I*8+4)*32(%rsp)
+        vpshufb  F, T5, T5
+        vmovdqu  T5, (I*8+5)*32(%rsp)
+        vpshufb  F, T6, T6
+        vmovdqu  T6, (I*8+6)*32(%rsp)
+        vpshufb  F, T7, T7
+        vmovdqu  T7, (I*8+7)*32(%rsp)
+        add     $32, IDX
+        I = (I+1)
+.endr
+        # save old digests
+        vmovdqu  A,AA
+        vmovdqu  B,BB
+        vmovdqu  C,CC
+        vmovdqu  D,DD
+        vmovdqu  E,EE
+
+##
+## perform 0-79 steps
+##
+        vmovdqu  K00_19(%rip), K
+## do rounds 0...15
+        I = 0
+.rep 16
+        SHA1_STEP_00_15 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F0
+        ROTATE_ARGS
+        I = (I+1)
+.endr
+
+## do rounds 16...19
+        vmovdqu  ((16 - 16) & 15) * 32 (%rsp), W16
+        vmovdqu  ((16 - 15) & 15) * 32 (%rsp), W15
+.rep 4
+        SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F0
+        ROTATE_ARGS
+        I = (I+1)
+.endr
+
+## do rounds 20...39
+        vmovdqu  K20_39(%rip), K
+.rep 20
+        SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F1
+        ROTATE_ARGS
+        I = (I+1)
+.endr
+
+## do rounds 40...59
+        vmovdqu  K40_59(%rip), K
+.rep 20
+        SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F2
+        ROTATE_ARGS
+        I = (I+1)
+.endr
+
+## do rounds 60...79
+        vmovdqu  K60_79(%rip), K
+.rep 20
+        SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F3
+        ROTATE_ARGS
+        I = (I+1)
+.endr
+
+        vpaddd   AA,A,A
+        vpaddd   BB,B,B
+        vpaddd   CC,C,C
+        vpaddd   DD,D,D
+        vpaddd   EE,E,E
+
+        sub     $1, arg2
+        jne     lloop
+
+        # write out digests
+        vmovdqu  A, 0*32(arg1)
+        vmovdqu  B, 1*32(arg1)
+        vmovdqu  C, 2*32(arg1)
+        vmovdqu  D, 3*32(arg1)
+        vmovdqu  E, 4*32(arg1)
+
+        # update input pointers
+        add     IDX, inp0
+        add     IDX, inp1
+        add     IDX, inp2
+        add     IDX, inp3
+        add     IDX, inp4
+        add     IDX, inp5
+        add     IDX, inp6
+        add     IDX, inp7
+        mov     inp0, _data_ptr (arg1)
+        mov     inp1, _data_ptr + 1*8(arg1)
+        mov     inp2, _data_ptr + 2*8(arg1)
+        mov     inp3, _data_ptr + 3*8(arg1)
+        mov     inp4, _data_ptr + 4*8(arg1)
+        mov     inp5, _data_ptr + 5*8(arg1)
+        mov     inp6, _data_ptr + 6*8(arg1)
+        mov     inp7, _data_ptr + 7*8(arg1)
+
+        ################
+        ## Postamble
+
+        mov     RSP_SAVE, %rsp
+        pop     RSP_SAVE
+
+        ret
+ENDPROC(sha1_x8_avx2)
+
+
+.data
+
+.align 32
+K00_19:
+.octa 0x5A8279995A8279995A8279995A827999
+.octa 0x5A8279995A8279995A8279995A827999
+K20_39:
+.octa 0x6ED9EBA16ED9EBA16ED9EBA16ED9EBA1
+.octa 0x6ED9EBA16ED9EBA16ED9EBA16ED9EBA1
+K40_59:
+.octa 0x8F1BBCDC8F1BBCDC8F1BBCDC8F1BBCDC
+.octa 0x8F1BBCDC8F1BBCDC8F1BBCDC8F1BBCDC
+K60_79:
+.octa 0xCA62C1D6CA62C1D6CA62C1D6CA62C1D6
+.octa 0xCA62C1D6CA62C1D6CA62C1D6CA62C1D6
+PSHUFFLE_BYTE_FLIP_MASK:
+.octa 0x0c0d0e0f08090a0b0405060700010203
+.octa 0x0c0d0e0f08090a0b0405060700010203
diff --git a/arch/x86/crypto/sha-mb/sha_mb_ctx.h b/arch/x86/crypto/sha-mb/sha_mb_ctx.h
new file mode 100644
index 000000000000..e36069d0c1bd
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha_mb_ctx.h
@@ -0,0 +1,136 @@
+/*
+ * Header file for multi buffer SHA context
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SHA_MB_CTX_INTERNAL_H
+#define _SHA_MB_CTX_INTERNAL_H
+
+#include "sha_mb_mgr.h"
+
+#define HASH_UPDATE          0x00
+#define HASH_FIRST           0x01
+#define HASH_LAST            0x02
+#define HASH_ENTIRE          0x03
+#define HASH_DONE            0x04
+#define HASH_FINAL           0x08
+
+#define HASH_CTX_STS_IDLE       0x00
+#define HASH_CTX_STS_PROCESSING 0x01
+#define HASH_CTX_STS_LAST       0x02
+#define HASH_CTX_STS_COMPLETE   0x04
+
+enum hash_ctx_error {
+        HASH_CTX_ERROR_NONE               =  0,
+        HASH_CTX_ERROR_INVALID_FLAGS      = -1,
+        HASH_CTX_ERROR_ALREADY_PROCESSING = -2,
+        HASH_CTX_ERROR_ALREADY_COMPLETED  = -3,
+
+#ifdef HASH_CTX_DEBUG
+        HASH_CTX_ERROR_DEBUG_DIGEST_MISMATCH = -4,
+#endif
+};
+
+
+#define hash_ctx_user_data(ctx)  ((ctx)->user_data)
+#define hash_ctx_digest(ctx)     ((ctx)->job.result_digest)
+#define hash_ctx_processing(ctx) ((ctx)->status & HASH_CTX_STS_PROCESSING)
+#define hash_ctx_complete(ctx)   ((ctx)->status == HASH_CTX_STS_COMPLETE)
+#define hash_ctx_status(ctx)     ((ctx)->status)
+#define hash_ctx_error(ctx)      ((ctx)->error)
+#define hash_ctx_init(ctx) \
+        do { \
+                (ctx)->error = HASH_CTX_ERROR_NONE; \
+                (ctx)->status = HASH_CTX_STS_COMPLETE; \
+        } while (0)
+
+
+/* Hash Constants and Typedefs */
+#define SHA1_DIGEST_LENGTH          5
+#define SHA1_LOG2_BLOCK_SIZE        6
+
+#define SHA1_PADLENGTHFIELD_SIZE    8
+
+#ifdef SHA_MB_DEBUG
+#define assert(expr) \
+do { \
+        if (unlikely(!(expr))) { \
+                printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
+                #expr, __FILE__, __func__, __LINE__); \
+        } \
+} while (0)
+#else
+#define assert(expr) do {} while (0)
+#endif
+
+struct sha1_ctx_mgr {
+        struct sha1_mb_mgr mgr;
+};
+
+/* typedef struct sha1_ctx_mgr sha1_ctx_mgr; */
+
+struct sha1_hash_ctx {
+        /* Must be at struct offset 0 */
+        struct job_sha1       job;
+        /* status flag */
+        int status;
+        /* error flag */
+        int error;
+
+        uint32_t        total_length;
+        const void      *incoming_buffer;
+        uint32_t        incoming_buffer_length;
+        uint8_t         partial_block_buffer[SHA1_BLOCK_SIZE * 2];
+        uint32_t        partial_block_buffer_length;
+        void            *user_data;
+};
+
+#endif
diff --git a/arch/x86/crypto/sha-mb/sha_mb_mgr.h b/arch/x86/crypto/sha-mb/sha_mb_mgr.h
new file mode 100644
index 000000000000..08ad1a9acfd7
--- /dev/null
+++ b/arch/x86/crypto/sha-mb/sha_mb_mgr.h
@@ -0,0 +1,110 @@
+/*
+ * Header file for multi buffer SHA1 algorithm manager
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  Contact Information:
+ *      James Guilford <james.guilford@intel.com>
+ *      Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Intel Corporation.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Intel Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __SHA_MB_MGR_H
+#define __SHA_MB_MGR_H
+
+
+#include <linux/types.h>
+
+#define NUM_SHA1_DIGEST_WORDS 5
+
+enum job_sts {  STS_UNKNOWN = 0,
+                STS_BEING_PROCESSED = 1,
+                STS_COMPLETED = 2,
+                STS_INTERNAL_ERROR = 3,
+                STS_ERROR = 4
+};
+
+struct job_sha1 {
+        u8      *buffer;
+        u32     len;
+        u32     result_digest[NUM_SHA1_DIGEST_WORDS] __aligned(32);
+        enum    job_sts status;
+        void    *user_data;
+};
+
+/* SHA1 out-of-order scheduler */
+
+/* typedef uint32_t sha1_digest_array[5][8]; */
+
+struct sha1_args_x8 {
+        uint32_t        digest[5][8];
+        uint8_t         *data_ptr[8];
+};
+
+struct sha1_lane_data {
+        struct job_sha1 *job_in_lane;
+};
+
+struct sha1_mb_mgr {
+        struct sha1_args_x8 args;
+
+        uint32_t lens[8];
+
+        /* each byte is index (0...7) of unused lanes */
+        uint64_t unused_lanes;
+        /* byte 4 is set to FF as a flag */
+        struct sha1_lane_data ldata[8];
+};
+
+
+#define SHA1_MB_MGR_NUM_LANES_AVX2 8
+
+void sha1_mb_mgr_init_avx2(struct sha1_mb_mgr *state);
+struct job_sha1 *sha1_mb_mgr_submit_avx2(struct sha1_mb_mgr *state,
+                                         struct job_sha1 *job);
+struct job_sha1 *sha1_mb_mgr_flush_avx2(struct sha1_mb_mgr *state);
+struct job_sha1 *sha1_mb_mgr_get_comp_job_avx2(struct sha1_mb_mgr *state);
+
+#endif
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index afcd35d331de..cfe3b954d5e4 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -497,8 +497,6 @@ static __always_inline int fls64(__u64 x)
 
 #include <asm-generic/bitops/sched.h>
 
-#define ARCH_HAS_FAST_MULTIPLIER 1
-
 #include <asm/arch_hweight.h>
 
 #include <asm-generic/bitops/const_hweight.h>
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index bb9b258d60e7..094292a63e74 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -202,6 +202,7 @@
 #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */
 #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */
 #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */
+#define X86_FEATURE_VMMCALL     ( 8*32+15) /* Prefer vmmcall to vmcall */
 
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
@@ -250,8 +251,15 @@
 #include <asm/asm.h>
 #include <linux/bitops.h>
 
+#ifdef CONFIG_X86_FEATURE_NAMES
 extern const char * const x86_cap_flags[NCAPINTS*32];
 extern const char * const x86_power_flags[32];
+#define X86_CAP_FMT "%s"
+#define x86_cap_flag(flag) x86_cap_flags[flag]
+#else
+#define X86_CAP_FMT "%d:%d"
+#define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31)
+#endif
 
 /*
  * In order to save room, we index into this array by doing
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 044a2fd3c5fe..0ec241ede5a2 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -159,30 +159,6 @@ static inline efi_status_t efi_thunk_set_virtual_address_map(
 }
 #endif /* CONFIG_EFI_MIXED */
 
-
-/* arch specific definitions used by the stub code */
-
-struct efi_config {
-        u64 image_handle;
-        u64 table;
-        u64 allocate_pool;
-        u64 allocate_pages;
-        u64 get_memory_map;
-        u64 free_pool;
-        u64 free_pages;
-        u64 locate_handle;
-        u64 handle_protocol;
-        u64 exit_boot_services;
-        u64 text_output;
-        efi_status_t (*call)(unsigned long, ...);
-        bool is64;
-} __packed;
-
-extern struct efi_config *efi_early;
-
-#define efi_call_early(f, ...)                                          \
-        efi_early->call(efi_early->f, __VA_ARGS__);
-
 extern bool efi_reboot_required(void);
 
 #else
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index b0910f97a3ea..ffb1733ac91f 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -106,14 +106,14 @@ enum fixed_addresses {
         __end_of_permanent_fixed_addresses,
 
         /*
-         * 256 temporary boot-time mappings, used by early_ioremap(),
+         * 512 temporary boot-time mappings, used by early_ioremap(),
          * before ioremap() is functional.
          *
-         * If necessary we round it up to the next 256 pages boundary so
+         * If necessary we round it up to the next 512 pages boundary so
          * that we can have a single pgd entry and a single pte table:
          */
 #define NR_FIX_BTMAPS           64
-#define FIX_BTMAPS_SLOTS        4
+#define FIX_BTMAPS_SLOTS        8
 #define TOTAL_FIX_BTMAPS        (NR_FIX_BTMAPS * FIX_BTMAPS_SLOTS)
         FIX_BTMAP_END =
          (__end_of_permanent_fixed_addresses ^
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 0aeed5ca356e..1733ab49ac5e 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -227,6 +227,8 @@ static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned
 
 extern void io_apic_eoi(unsigned int apic, unsigned int vector);
 
+extern bool mp_should_keep_irq(struct device *dev);
+
 #else  /* !CONFIG_X86_IO_APIC */
 
 #define io_apic_assign_pci_irqs 0
@@ -237,6 +239,7 @@ static inline int mp_find_ioapic(u32 gsi) { return 0; }
 static inline u32 mp_pin_to_gsi(int ioapic, int pin) { return UINT_MAX; }
 static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags) { return gsi; }
 static inline void mp_unmap_irq(int irq) { }
+static inline bool mp_should_keep_irq(struct device *dev) { return 1; }
 
 static inline int save_ioapic_entries(void)
 {
diff --git a/arch/x86/include/asm/irq_work.h b/arch/x86/include/asm/irq_work.h
new file mode 100644
index 000000000000..78162f8e248b
--- /dev/null
+++ b/arch/x86/include/asm/irq_work.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_IRQ_WORK_H
+#define _ASM_IRQ_WORK_H
+
+#include <asm/processor.h>
+
+static inline bool arch_irq_work_has_interrupt(void)
+{
+        return cpu_has_apic;
+}
+
+#endif /* _ASM_IRQ_WORK_H */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 572460175ba5..7d603a71ab3a 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -95,14 +95,10 @@ static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
 #define KVM_REFILL_PAGES 25
 #define KVM_MAX_CPUID_ENTRIES 80
 #define KVM_NR_FIXED_MTRR_REGION 88
-#define KVM_NR_VAR_MTRR 10
+#define KVM_NR_VAR_MTRR 8
 
 #define ASYNC_PF_PER_VCPU 64
 
-struct kvm_vcpu;
-struct kvm;
-struct kvm_async_pf;
-
 enum kvm_reg {
         VCPU_REGS_RAX = 0,
         VCPU_REGS_RCX = 1,
@@ -266,7 +262,8 @@ struct kvm_mmu {
                                   struct x86_exception *fault);
         gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access,
                             struct x86_exception *exception);
-        gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
+        gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
+                               struct x86_exception *exception);
         int (*sync_page)(struct kvm_vcpu *vcpu,
                          struct kvm_mmu_page *sp);
         void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva);
@@ -481,6 +478,7 @@ struct kvm_vcpu_arch {
         u64 mmio_gva;
         unsigned access;
         gfn_t mmio_gfn;
+        u64 mmio_gen;
 
         struct kvm_pmu pmu;
 
@@ -576,11 +574,10 @@ struct kvm_arch {
         struct kvm_apic_map *apic_map;
 
         unsigned int tss_addr;
-        struct page *apic_access_page;
+        bool apic_access_page_done;
 
         gpa_t wall_clock;
 
-        struct page *ept_identity_pagetable;
         bool ept_identity_pagetable_done;
         gpa_t ept_identity_map_addr;
 
@@ -665,8 +662,8 @@ struct msr_data {
 struct kvm_x86_ops {
         int (*cpu_has_kvm_support)(void);          /* __init */
         int (*disabled_by_bios)(void);             /* __init */
-        int (*hardware_enable)(void *dummy);
-        void (*hardware_disable)(void *dummy);
+        int (*hardware_enable)(void);
+        void (*hardware_disable)(void);
         void (*check_processor_compatibility)(void *rtn);
         int (*hardware_setup)(void);               /* __init */
         void (*hardware_unsetup)(void);            /* __exit */
@@ -710,7 +707,6 @@ struct kvm_x86_ops {
         void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
         unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
         void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
-        void (*fpu_activate)(struct kvm_vcpu *vcpu);
         void (*fpu_deactivate)(struct kvm_vcpu *vcpu);
 
         void (*tlb_flush)(struct kvm_vcpu *vcpu);
@@ -740,6 +736,7 @@ struct kvm_x86_ops {
         void (*hwapic_isr_update)(struct kvm *kvm, int isr);
         void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
         void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set);
+        void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa);
         void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
         void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
         int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
@@ -772,6 +769,8 @@ struct kvm_x86_ops {
         bool (*mpx_supported)(void);
 
         int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr);
+
+        void (*sched_in)(struct kvm_vcpu *kvm, int cpu);
 };
 
 struct kvm_arch_async_pf {
@@ -895,7 +894,6 @@ void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
                             gfn_t gfn, void *data, int offset, int len,
                             u32 access);
-void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
 
 static inline int __kvm_irq_line_state(unsigned long *irq_state,
@@ -917,7 +915,6 @@ void kvm_inject_nmi(struct kvm_vcpu *vcpu);
 
 int fx_init(struct kvm_vcpu *vcpu);
 
-void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
                        const u8 *new, int bytes);
 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
@@ -926,7 +923,8 @@ void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
 int kvm_mmu_load(struct kvm_vcpu *vcpu);
 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
-gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
+gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
+                           struct x86_exception *exception);
 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
                               struct x86_exception *exception);
 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
@@ -946,7 +944,8 @@ void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu);
 void kvm_enable_tdp(void);
 void kvm_disable_tdp(void);
 
-static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
+static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
+                                  struct x86_exception *exception)
 {
         return gpa;
 }
@@ -1037,7 +1036,7 @@ asmlinkage void kvm_spurious_fault(void);
 #define KVM_ARCH_WANT_MMU_NOTIFIER
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end);
-int kvm_age_hva(struct kvm *kvm, unsigned long hva);
+int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu);
@@ -1046,6 +1045,9 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
 void kvm_vcpu_reset(struct kvm_vcpu *vcpu);
+void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu);
+void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
+                                           unsigned long address);
 
 void kvm_define_shared_msr(unsigned index, u32 msr);
 void kvm_set_shared_msr(unsigned index, u64 val, u64 mask);
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index c7678e43465b..e62cf897f781 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -2,6 +2,7 @@
 #define _ASM_X86_KVM_PARA_H
 
 #include <asm/processor.h>
+#include <asm/alternative.h>
 #include <uapi/asm/kvm_para.h>
 
 extern void kvmclock_init(void);
@@ -16,10 +17,15 @@ static inline bool kvm_check_and_clear_guest_paused(void)
 }
 #endif /* CONFIG_KVM_GUEST */
 
-/* This instruction is vmcall.  On non-VT architectures, it will generate a
- * trap that we will then rewrite to the appropriate instruction.
+#ifdef CONFIG_DEBUG_RODATA
+#define KVM_HYPERCALL \
+        ALTERNATIVE(".byte 0x0f,0x01,0xc1", ".byte 0x0f,0x01,0xd9", X86_FEATURE_VMMCALL)
+#else
+/* On AMD processors, vmcall will generate a trap that we will
+ * then rewrite to the appropriate instruction.
  */
 #define KVM_HYPERCALL ".byte 0x0f,0x01,0xc1"
+#endif
 
 /* For KVM hypercalls, a three-byte sequence of either the vmcall or the vmmcall
  * instruction.  The hypervisor may replace it with something else but only the
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 0ec056012618..aa97a070f09f 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -131,8 +131,13 @@ static inline int pte_exec(pte_t pte)
 
 static inline int pte_special(pte_t pte)
 {
-        return (pte_flags(pte) & (_PAGE_PRESENT|_PAGE_SPECIAL)) ==
-                                 (_PAGE_PRESENT|_PAGE_SPECIAL);
+        /*
+         * See CONFIG_NUMA_BALANCING pte_numa in include/asm-generic/pgtable.h.
+         * On x86 we have _PAGE_BIT_NUMA == _PAGE_BIT_GLOBAL+1 ==
+         * __PAGE_BIT_SOFTW1 == _PAGE_BIT_SPECIAL.
+         */
+        return (pte_flags(pte) & _PAGE_SPECIAL) &&
+                (pte_flags(pte) & (_PAGE_PRESENT|_PAGE_PROTNONE));
 }
 
 static inline unsigned long pte_pfn(pte_t pte)
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index 5be9063545d2..3874693c0e53 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -19,6 +19,7 @@ extern pud_t level3_ident_pgt[512];
 extern pmd_t level2_kernel_pgt[512];
 extern pmd_t level2_fixmap_pgt[512];
 extern pmd_t level2_ident_pgt[512];
+extern pte_t level1_fixmap_pgt[512];
 extern pgd_t init_level4_pgt[];
 
 #define swapper_pg_dir init_level4_pgt
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index f216963760e5..0f9724c9c510 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -325,6 +325,20 @@ static inline pteval_t pte_flags(pte_t pte)
         return native_pte_val(pte) & PTE_FLAGS_MASK;
 }
 
+#ifdef CONFIG_NUMA_BALANCING
+/* Set of bits that distinguishes present, prot_none and numa ptes */
+#define _PAGE_NUMA_MASK (_PAGE_NUMA|_PAGE_PROTNONE|_PAGE_PRESENT)
+static inline pteval_t ptenuma_flags(pte_t pte)
+{
+        return pte_flags(pte) & _PAGE_NUMA_MASK;
+}
+
+static inline pmdval_t pmdnuma_flags(pmd_t pmd)
+{
+        return pmd_flags(pmd) & _PAGE_NUMA_MASK;
+}
+#endif /* CONFIG_NUMA_BALANCING */
+
 #define pgprot_val(x)   ((x).pgprot)
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index b5ea75c4a4b4..ada2e2d6be3e 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_FTRACE_SYSCALLS)	+= ftrace.o
 obj-$(CONFIG_X86_TSC)           += trace_clock.o
 obj-$(CONFIG_KEXEC)             += machine_kexec_$(BITS).o
 obj-$(CONFIG_KEXEC)             += relocate_kernel_$(BITS).o crash.o
+obj-$(CONFIG_KEXEC_FILE)        += kexec-bzimage64.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump_$(BITS).o
 obj-y                           += kprobes/
 obj-$(CONFIG_MODULES)           += module.o
@@ -118,5 +119,4 @@ ifeq ($(CONFIG_X86_64),y)
 
         obj-$(CONFIG_PCI_MMCONFIG)      += mmconf-fam10h_64.o
         obj-y                           += vsmp_64.o
-        obj-$(CONFIG_KEXEC)             += kexec-bzimage64.o
 endif
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 29290f554e79..1183d545da1e 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1070,6 +1070,11 @@ static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
         }
 
         if (flags & IOAPIC_MAP_ALLOC) {
+                /* special handling for legacy IRQs */
+                if (irq < nr_legacy_irqs() && info->count == 1 &&
+                    mp_irqdomain_map(domain, irq, pin) != 0)
+                        irq = -1;
+
                 if (irq > 0)
                         info->count++;
                 else if (info->count == 0)
@@ -2618,6 +2623,7 @@ static struct irq_chip ioapic_chip __read_mostly = {
         .irq_eoi                = ack_apic_level,
         .irq_set_affinity       = native_ioapic_set_affinity,
         .irq_retrigger          = ioapic_retrigger_irq,
+        .flags                  = IRQCHIP_SKIP_SET_WAKE,
 };
 
 static inline void init_IO_APIC_traps(void)
@@ -3168,6 +3174,7 @@ static struct irq_chip msi_chip = {
         .irq_ack                = ack_apic_edge,
         .irq_set_affinity       = msi_set_affinity,
         .irq_retrigger          = ioapic_retrigger_irq,
+        .flags                  = IRQCHIP_SKIP_SET_WAKE,
 };
 
 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
@@ -3266,6 +3273,7 @@ static struct irq_chip dmar_msi_type = {
         .irq_ack                = ack_apic_edge,
         .irq_set_affinity       = dmar_msi_set_affinity,
         .irq_retrigger          = ioapic_retrigger_irq,
+        .flags                  = IRQCHIP_SKIP_SET_WAKE,
 };
 
 int arch_setup_dmar_msi(unsigned int irq)
@@ -3316,6 +3324,7 @@ static struct irq_chip hpet_msi_type = {
         .irq_ack = ack_apic_edge,
         .irq_set_affinity = hpet_msi_set_affinity,
         .irq_retrigger = ioapic_retrigger_irq,
+        .flags = IRQCHIP_SKIP_SET_WAKE,
 };
 
 int default_setup_hpet_msi(unsigned int irq, unsigned int id)
@@ -3379,6 +3388,7 @@ static struct irq_chip ht_irq_chip = {
         .irq_ack                = ack_apic_edge,
         .irq_set_affinity       = ht_set_affinity,
         .irq_retrigger          = ioapic_retrigger_irq,
+        .flags                  = IRQCHIP_SKIP_SET_WAKE,
 };
 
 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
@@ -3896,7 +3906,15 @@ int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
                         info->polarity = 1;
                 }
                 info->node = NUMA_NO_NODE;
-                info->set = 1;
+
+                /*
+                 * setup_IO_APIC_irqs() programs all legacy IRQs with default
+                 * trigger and polarity attributes. Don't set the flag for that
+                 * case so the first legacy IRQ user could reprogram the pin
+                 * with real trigger and polarity attributes.
+                 */
+                if (virq >= nr_legacy_irqs() || info->count)
+                        info->set = 1;
         }
         set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
                              info->polarity);
@@ -3946,6 +3964,18 @@ int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
         return ret;
 }
 
+bool mp_should_keep_irq(struct device *dev)
+{
+        if (dev->power.is_prepared)
+                return true;
+#ifdef  CONFIG_PM_RUNTIME
+        if (dev->power.runtime_status == RPM_SUSPENDING)
+                return true;
+#endif
+
+        return false;
+}
+
 /* Enable IOAPIC early just for system timer */
 void __init pre_init_apic_IRQ0(void)
 {
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 7fd54f09b011..77dcab277710 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -13,10 +13,13 @@ nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_common.o         := $(nostackp)
 
 obj-y                   := intel_cacheinfo.o scattered.o topology.o
-obj-y                   += proc.o capflags.o powerflags.o common.o
+obj-y                   += common.o
 obj-y                   += rdrand.o
 obj-y                   += match.o
 
+obj-$(CONFIG_PROC_FS)   += proc.o
+obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o
+
 obj-$(CONFIG_X86_32)    += bugs.o
 obj-$(CONFIG_X86_64)    += bugs_64.o
 
@@ -48,6 +51,7 @@ obj-$(CONFIG_X86_LOCAL_APIC)		+= perfctr-watchdog.o perf_event_amd_ibs.o
 
 obj-$(CONFIG_HYPERVISOR_GUEST)          += vmware.o hypervisor.o mshyperv.o
 
+ifdef CONFIG_X86_FEATURE_NAMES
 quiet_cmd_mkcapflags = MKCAP   $@
       cmd_mkcapflags = $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $< $@
 
@@ -56,3 +60,4 @@ cpufeature = $(src)/../../include/asm/cpufeature.h
 targets += capflags.c
 $(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE
         $(call if_changed,mkcapflags)
+endif
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 60e5497681f5..813d29d00a17 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -525,6 +525,13 @@ static void early_init_amd(struct cpuinfo_x86 *c)
         }
 #endif
 
+        /*
+         * This is only needed to tell the kernel whether to use VMCALL
+         * and VMMCALL.  VMMCALL is never executed except under virt, so
+         * we can set it unconditionally.
+         */
+        set_cpu_cap(c, X86_FEATURE_VMMCALL);
+
         /* F16h erratum 793, CVE-2013-6885 */
         if (c->x86 == 0x16 && c->x86_model <= 0xf)
                 msr_set_bit(MSR_AMD64_LS_CFG, 15);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e4ab2b42bd6f..c649f236e288 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -346,8 +346,8 @@ static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
                         continue;
 
                 printk(KERN_WARNING
-                       "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
-                                x86_cap_flags[df->feature], df->level);
+                       "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
+                                x86_cap_flag(df->feature), df->level);
         }
 }
 
diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c
index 0553a34fa0df..a618fcd2c07d 100644
--- a/arch/x86/kernel/crash.c
+++ b/arch/x86/kernel/crash.c
@@ -182,8 +182,7 @@ void native_machine_crash_shutdown(struct pt_regs *regs)
         crash_save_cpu(regs, safe_smp_processor_id());
 }
 
-#ifdef CONFIG_X86_64
-
+#ifdef CONFIG_KEXEC_FILE
 static int get_nr_ram_ranges_callback(unsigned long start_pfn,
                                 unsigned long nr_pfn, void *arg)
 {
@@ -696,5 +695,4 @@ int crash_load_segments(struct kimage *image)
 
         return ret;
 }
-
-#endif /* CONFIG_X86_64 */
+#endif /* CONFIG_KEXEC_FILE */
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index 47c410d99f5d..4b0e1dfa2226 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -683,7 +683,7 @@ END(syscall_badsys)
 sysenter_badsys:
         movl $-ENOSYS,%eax
         jmp sysenter_after_call
-END(syscall_badsys)
+END(sysenter_badsys)
         CFI_ENDPROC
 
 .macro FIXUP_ESPFIX_STACK
diff --git a/arch/x86/kernel/irq_work.c b/arch/x86/kernel/irq_work.c
index 1de84e3ab4e0..15d741ddfeeb 100644
--- a/arch/x86/kernel/irq_work.c
+++ b/arch/x86/kernel/irq_work.c
@@ -41,7 +41,7 @@ __visible void smp_trace_irq_work_interrupt(struct pt_regs *regs)
 void arch_irq_work_raise(void)
 {
 #ifdef CONFIG_X86_LOCAL_APIC
-        if (!cpu_has_apic)
+        if (!arch_irq_work_has_interrupt())
                 return;
 
         apic->send_IPI_self(IRQ_WORK_VECTOR);
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 1e6cff5814fa..44f1ed42fdf2 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -203,7 +203,7 @@ void __init native_init_IRQ(void)
                 set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
         }
 
-        if (!acpi_ioapic && !of_ioapic)
+        if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
                 setup_irq(2, &irq2);
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c
index f304773285ae..f1314d0bcf0a 100644
--- a/arch/x86/kernel/kprobes/opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -338,8 +338,10 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op)
          * a relative jump.
          */
         rel = (long)op->optinsn.insn - (long)op->kp.addr + RELATIVEJUMP_SIZE;
-        if (abs(rel) > 0x7fffffff)
+        if (abs(rel) > 0x7fffffff) {
+                __arch_remove_optimized_kprobe(op, 0);
                 return -ERANGE;
+        }
 
         buf = (u8 *)op->optinsn.insn;
 
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index 8b04018e5d1f..485981059a40 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -25,9 +25,11 @@
 #include <asm/debugreg.h>
 #include <asm/kexec-bzimage64.h>
 
+#ifdef CONFIG_KEXEC_FILE
 static struct kexec_file_ops *kexec_file_loaders[] = {
                 &kexec_bzImage64_ops,
 };
+#endif
 
 static void free_transition_pgtable(struct kimage *image)
 {
@@ -178,6 +180,7 @@ static void load_segments(void)
                 );
 }
 
+#ifdef CONFIG_KEXEC_FILE
 /* Update purgatory as needed after various image segments have been prepared */
 static int arch_update_purgatory(struct kimage *image)
 {
@@ -209,6 +212,12 @@ static int arch_update_purgatory(struct kimage *image)
 
         return ret;
 }
+#else /* !CONFIG_KEXEC_FILE */
+static inline int arch_update_purgatory(struct kimage *image)
+{
+        return 0;
+}
+#endif /* CONFIG_KEXEC_FILE */
 
 int machine_kexec_prepare(struct kimage *image)
 {
@@ -329,6 +338,7 @@ void arch_crash_save_vmcoreinfo(void)
 
 /* arch-dependent functionality related to kexec file-based syscall */
 
+#ifdef CONFIG_KEXEC_FILE
 int arch_kexec_kernel_image_probe(struct kimage *image, void *buf,
                                   unsigned long buf_len)
 {
@@ -522,3 +532,4 @@ overflow:
                (int)ELF64_R_TYPE(rel[i].r_info), value);
         return -ENOEXEC;
 }
+#endif /* CONFIG_KEXEC_FILE */
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 2d872e08fab9..42a2dca984b3 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1284,6 +1284,9 @@ static void remove_siblinginfo(int cpu)
 
         for_each_cpu(sibling, cpu_sibling_mask(cpu))
                 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
+        for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
+                cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
+        cpumask_clear(cpu_llc_shared_mask(cpu));
         cpumask_clear(cpu_sibling_mask(cpu));
         cpumask_clear(cpu_core_mask(cpu));
         c->phys_proc_id = 0;
diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c
index bf7ef5ce29df..0fa29609b2c4 100644
--- a/arch/x86/kernel/time.c
+++ b/arch/x86/kernel/time.c
@@ -68,6 +68,8 @@ static struct irqaction irq0  = {
 
 void __init setup_default_timer_irq(void)
 {
+        if (!nr_legacy_irqs())
+                return;
         setup_irq(0, &irq0);
 }
 
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 38a0afe83c6b..976e3a57f9ea 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -53,14 +53,14 @@ u64 kvm_supported_xcr0(void)
         return xcr0;
 }
 
-void kvm_update_cpuid(struct kvm_vcpu *vcpu)
+int kvm_update_cpuid(struct kvm_vcpu *vcpu)
 {
         struct kvm_cpuid_entry2 *best;
         struct kvm_lapic *apic = vcpu->arch.apic;
 
         best = kvm_find_cpuid_entry(vcpu, 1, 0);
         if (!best)
-                return;
+                return 0;
 
         /* Update OSXSAVE bit */
         if (cpu_has_xsave && best->function == 0x1) {
@@ -88,7 +88,17 @@ void kvm_update_cpuid(struct kvm_vcpu *vcpu)
                         xstate_required_size(vcpu->arch.xcr0);
         }
 
+        /*
+         * The existing code assumes virtual address is 48-bit in the canonical
+         * address checks; exit if it is ever changed.
+         */
+        best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
+        if (best && ((best->eax & 0xff00) >> 8) != 48 &&
+                ((best->eax & 0xff00) >> 8) != 0)
+                return -EINVAL;
+
         kvm_pmu_cpuid_update(vcpu);
+        return 0;
 }
 
 static int is_efer_nx(void)
@@ -112,8 +122,8 @@ static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
                         break;
                 }
         }
-        if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
-                entry->edx &= ~(1 << 20);
+        if (entry && (entry->edx & bit(X86_FEATURE_NX)) && !is_efer_nx()) {
+                entry->edx &= ~bit(X86_FEATURE_NX);
                 printk(KERN_INFO "kvm: guest NX capability removed\n");
         }
 }
@@ -151,10 +161,9 @@ int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
         }
         vcpu->arch.cpuid_nent = cpuid->nent;
         cpuid_fix_nx_cap(vcpu);
-        r = 0;
         kvm_apic_set_version(vcpu);
         kvm_x86_ops->cpuid_update(vcpu);
-        kvm_update_cpuid(vcpu);
+        r = kvm_update_cpuid(vcpu);
 
 out_free:
         vfree(cpuid_entries);
@@ -178,9 +187,7 @@ int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
         vcpu->arch.cpuid_nent = cpuid->nent;
         kvm_apic_set_version(vcpu);
         kvm_x86_ops->cpuid_update(vcpu);
-        kvm_update_cpuid(vcpu);
-        return 0;
-
+        r = kvm_update_cpuid(vcpu);
 out:
         return r;
 }
@@ -767,6 +774,12 @@ void kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
         if (!best)
                 best = check_cpuid_limit(vcpu, function, index);
 
+        /*
+         * Perfmon not yet supported for L2 guest.
+         */
+        if (is_guest_mode(vcpu) && function == 0xa)
+                best = NULL;
+
         if (best) {
                 *eax = best->eax;
                 *ebx = best->ebx;
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index a5380590ab0e..4452eedfaedd 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -3,7 +3,7 @@
 
 #include "x86.h"
 
-void kvm_update_cpuid(struct kvm_vcpu *vcpu);
+int kvm_update_cpuid(struct kvm_vcpu *vcpu);
 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
                                               u32 function, u32 index);
 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
@@ -88,6 +88,14 @@ static inline bool guest_cpuid_has_x2apic(struct kvm_vcpu *vcpu)
         return best && (best->ecx & bit(X86_FEATURE_X2APIC));
 }
 
+static inline bool guest_cpuid_is_amd(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 0, 0);
+        return best && best->ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx;
+}
+
 static inline bool guest_cpuid_has_gbpages(struct kvm_vcpu *vcpu)
 {
         struct kvm_cpuid_entry2 *best;
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 56657b0bb3bb..a46207a05835 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -527,6 +527,7 @@ static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
                              u32 error, bool valid)
 {
+        WARN_ON(vec > 0x1f);
         ctxt->exception.vector = vec;
         ctxt->exception.error_code = error;
         ctxt->exception.error_code_valid = valid;
@@ -1468,7 +1469,7 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
                 return ret;
 
         err_code = selector & 0xfffc;
-        err_vec = GP_VECTOR;
+        err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
 
         /* can't load system descriptor into segment selector */
         if (seg <= VCPU_SREG_GS && !seg_desc.s)
@@ -1491,9 +1492,6 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
                         goto exception;
                 break;
         case VCPU_SREG_CS:
-                if (in_task_switch && rpl != dpl)
-                        goto exception;
-
                 if (!(seg_desc.type & 8))
                         goto exception;
 
@@ -1506,6 +1504,15 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
                         if (rpl > cpl || dpl != cpl)
                                 goto exception;
                 }
+                /* in long-mode d/b must be clear if l is set */
+                if (seg_desc.d && seg_desc.l) {
+                        u64 efer = 0;
+
+                        ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
+                        if (efer & EFER_LMA)
+                                goto exception;
+                }
+
                 /* CS(RPL) <- CPL */
                 selector = (selector & 0xfffc) | cpl;
                 break;
@@ -1552,8 +1559,7 @@ load:
         ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
         return X86EMUL_CONTINUE;
 exception:
-        emulate_exception(ctxt, err_vec, err_code, true);
-        return X86EMUL_PROPAGATE_FAULT;
+        return emulate_exception(ctxt, err_vec, err_code, true);
 }
 
 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
@@ -2726,8 +2732,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
         if (!next_tss_desc.p ||
             ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
              desc_limit < 0x2b)) {
-                emulate_ts(ctxt, tss_selector & 0xfffc);
-                return X86EMUL_PROPAGATE_FAULT;
+                return emulate_ts(ctxt, tss_selector & 0xfffc);
         }
 
         if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
@@ -3019,7 +3024,7 @@ static int em_movbe(struct x86_emulate_ctxt *ctxt)
                 ctxt->dst.val = swab64(ctxt->src.val);
                 break;
         default:
-                return X86EMUL_PROPAGATE_FAULT;
+                BUG();
         }
         return X86EMUL_CONTINUE;
 }
@@ -3143,12 +3148,8 @@ static int em_clts(struct x86_emulate_ctxt *ctxt)
 
 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
 {
-        int rc;
-
-        if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
-                return X86EMUL_UNHANDLEABLE;
+        int rc = ctxt->ops->fix_hypercall(ctxt);
 
-        rc = ctxt->ops->fix_hypercall(ctxt);
         if (rc != X86EMUL_CONTINUE)
                 return rc;
 
@@ -3566,6 +3567,12 @@ static int check_perm_out(struct x86_emulate_ctxt *ctxt)
                 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),     \
                 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
 
+static const struct opcode group7_rm0[] = {
+        N,
+        I(SrcNone | Priv | EmulateOnUD, em_vmcall),
+        N, N, N, N, N, N,
+};
+
 static const struct opcode group7_rm1[] = {
         DI(SrcNone | Priv, monitor),
         DI(SrcNone | Priv, mwait),
@@ -3659,7 +3666,7 @@ static const struct group_dual group7 = { {
         II(SrcMem16 | Mov | Priv,               em_lmsw, lmsw),
         II(SrcMem | ByteOp | Priv | NoAccess,   em_invlpg, invlpg),
 }, {
-        I(SrcNone | Priv | EmulateOnUD, em_vmcall),
+        EXT(0, group7_rm0),
         EXT(0, group7_rm1),
         N, EXT(0, group7_rm3),
         II(SrcNone | DstMem | Mov,              em_smsw, smsw), N,
@@ -3690,14 +3697,18 @@ static const struct gprefix pfx_0f_6f_0f_7f = {
         I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
 };
 
-static const struct gprefix pfx_vmovntpx = {
-        I(0, em_mov), N, N, N,
+static const struct gprefix pfx_0f_2b = {
+        I(0, em_mov), I(0, em_mov), N, N,
 };
 
 static const struct gprefix pfx_0f_28_0f_29 = {
         I(Aligned, em_mov), I(Aligned, em_mov), N, N,
 };
 
+static const struct gprefix pfx_0f_e7 = {
+        N, I(Sse, em_mov), N, N,
+};
+
 static const struct escape escape_d9 = { {
         N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
 }, {
@@ -3904,7 +3915,7 @@ static const struct opcode twobyte_table[256] = {
         N, N, N, N,
         GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
         GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
-        N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
+        N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
         N, N, N, N,
         /* 0x30 - 0x3F */
         II(ImplicitOps | Priv, em_wrmsr, wrmsr),
@@ -3968,7 +3979,8 @@ static const struct opcode twobyte_table[256] = {
         /* 0xD0 - 0xDF */
         N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
         /* 0xE0 - 0xEF */
-        N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
+        N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
+        N, N, N, N, N, N, N, N,
         /* 0xF0 - 0xFF */
         N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
 };
@@ -4394,8 +4406,11 @@ done_prefixes:
 
         ctxt->execute = opcode.u.execute;
 
+        if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
+                return EMULATION_FAILED;
+
         if (unlikely(ctxt->d &
-                     (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
+                     (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
                 /*
                  * These are copied unconditionally here, and checked unconditionally
                  * in x86_emulate_insn.
@@ -4406,9 +4421,6 @@ done_prefixes:
                 if (ctxt->d & NotImpl)
                         return EMULATION_FAILED;
 
-                if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
-                        return EMULATION_FAILED;
-
                 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
                         ctxt->op_bytes = 8;
 
@@ -4832,8 +4844,10 @@ writeback:
         ctxt->eip = ctxt->_eip;
 
 done:
-        if (rc == X86EMUL_PROPAGATE_FAULT)
+        if (rc == X86EMUL_PROPAGATE_FAULT) {
+                WARN_ON(ctxt->exception.vector > 0x1f);
                 ctxt->have_exception = true;
+        }
         if (rc == X86EMUL_INTERCEPTED)
                 return EMULATION_INTERCEPTED;
 
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 08e8a899e005..b8345dd41b25 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -112,17 +112,6 @@ static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 struct static_key_deferred apic_hw_disabled __read_mostly;
 struct static_key_deferred apic_sw_disabled __read_mostly;
 
-static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
-{
-        if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
-                if (val & APIC_SPIV_APIC_ENABLED)
-                        static_key_slow_dec_deferred(&apic_sw_disabled);
-                else
-                        static_key_slow_inc(&apic_sw_disabled.key);
-        }
-        apic_set_reg(apic, APIC_SPIV, val);
-}
-
 static inline int apic_enabled(struct kvm_lapic *apic)
 {
         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
@@ -210,6 +199,20 @@ out:
         kvm_vcpu_request_scan_ioapic(kvm);
 }
 
+static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
+{
+        u32 prev = kvm_apic_get_reg(apic, APIC_SPIV);
+
+        apic_set_reg(apic, APIC_SPIV, val);
+        if ((prev ^ val) & APIC_SPIV_APIC_ENABLED) {
+                if (val & APIC_SPIV_APIC_ENABLED) {
+                        static_key_slow_dec_deferred(&apic_sw_disabled);
+                        recalculate_apic_map(apic->vcpu->kvm);
+                } else
+                        static_key_slow_inc(&apic_sw_disabled.key);
+        }
+}
+
 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 {
         apic_set_reg(apic, APIC_ID, id << 24);
@@ -706,6 +709,8 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
         int result = 0;
         struct kvm_vcpu *vcpu = apic->vcpu;
 
+        trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
+                                  trig_mode, vector);
         switch (delivery_mode) {
         case APIC_DM_LOWEST:
                 vcpu->arch.apic_arb_prio++;
@@ -727,8 +732,6 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                         kvm_make_request(KVM_REQ_EVENT, vcpu);
                         kvm_vcpu_kick(vcpu);
                 }
-                trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
-                                          trig_mode, vector, false);
                 break;
 
         case APIC_DM_REMRD:
@@ -1352,6 +1355,9 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
                 return;
 
         hrtimer_cancel(&apic->lapic_timer.timer);
+        /* Inject here so clearing tscdeadline won't override new value */
+        if (apic_has_pending_timer(vcpu))
+                kvm_inject_apic_timer_irqs(vcpu);
         apic->lapic_timer.tscdeadline = data;
         start_apic_timer(apic);
 }
@@ -1639,6 +1645,8 @@ void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
 
         if (atomic_read(&apic->lapic_timer.pending) > 0) {
                 kvm_apic_local_deliver(apic, APIC_LVTT);
+                if (apic_lvtt_tscdeadline(apic))
+                        apic->lapic_timer.tscdeadline = 0;
                 atomic_set(&apic->lapic_timer.pending, 0);
         }
 }
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 931467881da7..3201e93ebd07 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -199,16 +199,20 @@ void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
 
 /*
- * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number,
- * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation
- * number.
+ * the low bit of the generation number is always presumed to be zero.
+ * This disables mmio caching during memslot updates.  The concept is
+ * similar to a seqcount but instead of retrying the access we just punt
+ * and ignore the cache.
+ *
+ * spte bits 3-11 are used as bits 1-9 of the generation number,
+ * the bits 52-61 are used as bits 10-19 of the generation number.
  */
-#define MMIO_SPTE_GEN_LOW_SHIFT         3
+#define MMIO_SPTE_GEN_LOW_SHIFT         2
 #define MMIO_SPTE_GEN_HIGH_SHIFT        52
 
-#define MMIO_GEN_SHIFT                  19
-#define MMIO_GEN_LOW_SHIFT              9
-#define MMIO_GEN_LOW_MASK               ((1 << MMIO_GEN_LOW_SHIFT) - 1)
+#define MMIO_GEN_SHIFT                  20
+#define MMIO_GEN_LOW_SHIFT              10
+#define MMIO_GEN_LOW_MASK               ((1 << MMIO_GEN_LOW_SHIFT) - 2)
 #define MMIO_GEN_MASK                   ((1 << MMIO_GEN_SHIFT) - 1)
 #define MMIO_MAX_GEN                    ((1 << MMIO_GEN_SHIFT) - 1)
 
@@ -236,12 +240,7 @@ static unsigned int get_mmio_spte_generation(u64 spte)
 
 static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
 {
-        /*
-         * Init kvm generation close to MMIO_MAX_GEN to easily test the
-         * code of handling generation number wrap-around.
-         */
-        return (kvm_memslots(kvm)->generation +
-                      MMIO_MAX_GEN - 150) & MMIO_GEN_MASK;
+        return kvm_memslots(kvm)->generation & MMIO_GEN_MASK;
 }
 
 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
@@ -296,11 +295,6 @@ static bool check_mmio_spte(struct kvm *kvm, u64 spte)
         return likely(kvm_gen == spte_gen);
 }
 
-static inline u64 rsvd_bits(int s, int e)
-{
-        return ((1ULL << (e - s + 1)) - 1) << s;
-}
-
 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
 {
@@ -1180,7 +1174,7 @@ static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
  * Write-protect on the specified @sptep, @pt_protect indicates whether
  * spte write-protection is caused by protecting shadow page table.
  *
- * Note: write protection is difference between drity logging and spte
+ * Note: write protection is difference between dirty logging and spte
  * protection:
  * - for dirty logging, the spte can be set to writable at anytime if
  *   its dirty bitmap is properly set.
@@ -1268,7 +1262,8 @@ static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
 }
 
 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
-                           struct kvm_memory_slot *slot, unsigned long data)
+                           struct kvm_memory_slot *slot, gfn_t gfn, int level,
+                           unsigned long data)
 {
         u64 *sptep;
         struct rmap_iterator iter;
@@ -1276,7 +1271,8 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
 
         while ((sptep = rmap_get_first(*rmapp, &iter))) {
                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
-                rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
+                rmap_printk("kvm_rmap_unmap_hva: spte %p %llx gfn %llx (%d)\n",
+                             sptep, *sptep, gfn, level);
 
                 drop_spte(kvm, sptep);
                 need_tlb_flush = 1;
@@ -1286,7 +1282,8 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
 }
 
 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
-                             struct kvm_memory_slot *slot, unsigned long data)
+                             struct kvm_memory_slot *slot, gfn_t gfn, int level,
+                             unsigned long data)
 {
         u64 *sptep;
         struct rmap_iterator iter;
@@ -1300,7 +1297,8 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
 
         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
                 BUG_ON(!is_shadow_present_pte(*sptep));
-                rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
+                rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
+                             sptep, *sptep, gfn, level);
 
                 need_flush = 1;
 
@@ -1334,6 +1332,8 @@ static int kvm_handle_hva_range(struct kvm *kvm,
                                 int (*handler)(struct kvm *kvm,
                                                unsigned long *rmapp,
                                                struct kvm_memory_slot *slot,
+                                               gfn_t gfn,
+                                               int level,
                                                unsigned long data))
 {
         int j;
@@ -1363,6 +1363,7 @@ static int kvm_handle_hva_range(struct kvm *kvm,
                      j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
                         unsigned long idx, idx_end;
                         unsigned long *rmapp;
+                        gfn_t gfn = gfn_start;
 
                         /*
                          * {idx(page_j) | page_j intersects with
@@ -1373,8 +1374,10 @@ static int kvm_handle_hva_range(struct kvm *kvm,
 
                         rmapp = __gfn_to_rmap(gfn_start, j, memslot);
 
-                        for (; idx <= idx_end; ++idx)
-                                ret |= handler(kvm, rmapp++, memslot, data);
+                        for (; idx <= idx_end;
+                               ++idx, gfn += (1UL << KVM_HPAGE_GFN_SHIFT(j)))
+                                ret |= handler(kvm, rmapp++, memslot,
+                                               gfn, j, data);
                 }
         }
 
@@ -1385,6 +1388,7 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
                           unsigned long data,
                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
                                          struct kvm_memory_slot *slot,
+                                         gfn_t gfn, int level,
                                          unsigned long data))
 {
         return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
@@ -1406,24 +1410,14 @@ void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
 }
 
 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
-                         struct kvm_memory_slot *slot, unsigned long data)
+                         struct kvm_memory_slot *slot, gfn_t gfn, int level,
+                         unsigned long data)
 {
         u64 *sptep;
         struct rmap_iterator uninitialized_var(iter);
         int young = 0;
 
-        /*
-         * In case of absence of EPT Access and Dirty Bits supports,
-         * emulate the accessed bit for EPT, by checking if this page has
-         * an EPT mapping, and clearing it if it does. On the next access,
-         * a new EPT mapping will be established.
-         * This has some overhead, but not as much as the cost of swapping
-         * out actively used pages or breaking up actively used hugepages.
-         */
-        if (!shadow_accessed_mask) {
-                young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
-                goto out;
-        }
+        BUG_ON(!shadow_accessed_mask);
 
         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
              sptep = rmap_get_next(&iter)) {
@@ -1435,14 +1429,13 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
                                  (unsigned long *)sptep);
                 }
         }
-out:
-        /* @data has hva passed to kvm_age_hva(). */
-        trace_kvm_age_page(data, slot, young);
+        trace_kvm_age_page(gfn, level, slot, young);
         return young;
 }
 
 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
-                              struct kvm_memory_slot *slot, unsigned long data)
+                              struct kvm_memory_slot *slot, gfn_t gfn,
+                              int level, unsigned long data)
 {
         u64 *sptep;
         struct rmap_iterator iter;
@@ -1480,13 +1473,33 @@ static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 
         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
 
-        kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
+        kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, gfn, sp->role.level, 0);
         kvm_flush_remote_tlbs(vcpu->kvm);
 }
 
-int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
 {
-        return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
+        /*
+         * In case of absence of EPT Access and Dirty Bits supports,
+         * emulate the accessed bit for EPT, by checking if this page has
+         * an EPT mapping, and clearing it if it does. On the next access,
+         * a new EPT mapping will be established.
+         * This has some overhead, but not as much as the cost of swapping
+         * out actively used pages or breaking up actively used hugepages.
+         */
+        if (!shadow_accessed_mask) {
+                /*
+                 * We are holding the kvm->mmu_lock, and we are blowing up
+                 * shadow PTEs. MMU notifier consumers need to be kept at bay.
+                 * This is correct as long as we don't decouple the mmu_lock
+                 * protected regions (like invalidate_range_start|end does).
+                 */
+                kvm->mmu_notifier_seq++;
+                return kvm_handle_hva_range(kvm, start, end, 0,
+                                            kvm_unmap_rmapp);
+        }
+
+        return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
 }
 
 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
@@ -1749,7 +1762,7 @@ static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
                 return 1;
         }
 
-        kvm_mmu_flush_tlb(vcpu);
+        kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
         return 0;
 }
 
@@ -1802,7 +1815,7 @@ static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
 
         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
         if (flush)
-                kvm_mmu_flush_tlb(vcpu);
+                kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 }
 
 struct mmu_page_path {
@@ -2536,7 +2549,7 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
               true, host_writable)) {
                 if (write_fault)
                         *emulate = 1;
-                kvm_mmu_flush_tlb(vcpu);
+                kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
         }
 
         if (unlikely(is_mmio_spte(*sptep) && emulate))
@@ -3163,7 +3176,7 @@ static void mmu_sync_roots(struct kvm_vcpu *vcpu)
         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
                 return;
 
-        vcpu_clear_mmio_info(vcpu, ~0ul);
+        vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
                 hpa_t root = vcpu->arch.mmu.root_hpa;
@@ -3206,7 +3219,7 @@ static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
 {
         if (exception)
                 exception->error_code = 0;
-        return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
+        return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
 }
 
 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
@@ -3450,13 +3463,6 @@ static void nonpaging_init_context(struct kvm_vcpu *vcpu,
         context->nx = false;
 }
 
-void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
-{
-        ++vcpu->stat.tlb_flush;
-        kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
-}
-EXPORT_SYMBOL_GPL(kvm_mmu_flush_tlb);
-
 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
 {
         mmu_free_roots(vcpu);
@@ -3518,6 +3524,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
         int maxphyaddr = cpuid_maxphyaddr(vcpu);
         u64 exb_bit_rsvd = 0;
         u64 gbpages_bit_rsvd = 0;
+        u64 nonleaf_bit8_rsvd = 0;
 
         context->bad_mt_xwr = 0;
 
@@ -3525,6 +3532,14 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
                 exb_bit_rsvd = rsvd_bits(63, 63);
         if (!guest_cpuid_has_gbpages(vcpu))
                 gbpages_bit_rsvd = rsvd_bits(7, 7);
+
+        /*
+         * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
+         * leaf entries) on AMD CPUs only.
+         */
+        if (guest_cpuid_is_amd(vcpu))
+                nonleaf_bit8_rsvd = rsvd_bits(8, 8);
+
         switch (context->root_level) {
         case PT32_ROOT_LEVEL:
                 /* no rsvd bits for 2 level 4K page table entries */
@@ -3559,9 +3574,9 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
                 break;
         case PT64_ROOT_LEVEL:
                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
-                        rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7);
+                        nonleaf_bit8_rsvd | rsvd_bits(7, 7) | rsvd_bits(maxphyaddr, 51);
                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
-                        gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51);
+                        nonleaf_bit8_rsvd | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51);
                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
                         rsvd_bits(maxphyaddr, 51);
                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
@@ -3962,7 +3977,7 @@ static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
         if (remote_flush)
                 kvm_flush_remote_tlbs(vcpu->kvm);
         else if (local_flush)
-                kvm_mmu_flush_tlb(vcpu);
+                kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 }
 
 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
@@ -4223,7 +4238,7 @@ EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
 {
         vcpu->arch.mmu.invlpg(vcpu, gva);
-        kvm_mmu_flush_tlb(vcpu);
+        kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
         ++vcpu->stat.invlpg;
 }
 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
@@ -4433,7 +4448,7 @@ void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
          * The very rare case: if the generation-number is round,
          * zap all shadow pages.
          */
-        if (unlikely(kvm_current_mmio_generation(kvm) >= MMIO_MAX_GEN)) {
+        if (unlikely(kvm_current_mmio_generation(kvm) == 0)) {
                 printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
                 kvm_mmu_invalidate_zap_all_pages(kvm);
         }
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index b982112d2ca5..bde8ee725754 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -56,6 +56,11 @@
 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
 
+static inline u64 rsvd_bits(int s, int e)
+{
+        return ((1ULL << (e - s + 1)) - 1) << s;
+}
+
 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask);
 
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 410776528265..806d58e3c320 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -298,8 +298,7 @@ retry_walk:
         }
 #endif
         walker->max_level = walker->level;
-        ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
-               (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
+        ASSERT(!is_long_mode(vcpu) && is_pae(vcpu));
 
         accessed_dirty = PT_GUEST_ACCESSED_MASK;
         pt_access = pte_access = ACC_ALL;
@@ -321,9 +320,22 @@ retry_walk:
                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 
                 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
-                                              PFERR_USER_MASK|PFERR_WRITE_MASK);
+                                              PFERR_USER_MASK|PFERR_WRITE_MASK,
+                                              &walker->fault);
+
+                /*
+                 * FIXME: This can happen if emulation (for of an INS/OUTS
+                 * instruction) triggers a nested page fault.  The exit
+                 * qualification / exit info field will incorrectly have
+                 * "guest page access" as the nested page fault's cause,
+                 * instead of "guest page structure access".  To fix this,
+                 * the x86_exception struct should be augmented with enough
+                 * information to fix the exit_qualification or exit_info_1
+                 * fields.
+                 */
                 if (unlikely(real_gfn == UNMAPPED_GVA))
-                        goto error;
+                        return 0;
+
                 real_gfn = gpa_to_gfn(real_gfn);
 
                 host_addr = gfn_to_hva_prot(vcpu->kvm, real_gfn,
@@ -364,7 +376,7 @@ retry_walk:
         if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
                 gfn += pse36_gfn_delta(pte);
 
-        real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access);
+        real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
         if (real_gpa == UNMAPPED_GVA)
                 return 0;
 
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 3dd6accb64ec..8e6b7d869d2f 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/kvm_host.h>
 #include <linux/perf_event.h>
+#include <asm/perf_event.h>
 #include "x86.h"
 #include "cpuid.h"
 #include "lapic.h"
@@ -463,7 +464,8 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
 {
         struct kvm_pmu *pmu = &vcpu->arch.pmu;
         struct kvm_cpuid_entry2 *entry;
-        unsigned bitmap_len;
+        union cpuid10_eax eax;
+        union cpuid10_edx edx;
 
         pmu->nr_arch_gp_counters = 0;
         pmu->nr_arch_fixed_counters = 0;
@@ -475,25 +477,27 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
         entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
         if (!entry)
                 return;
+        eax.full = entry->eax;
+        edx.full = entry->edx;
 
-        pmu->version = entry->eax & 0xff;
+        pmu->version = eax.split.version_id;
         if (!pmu->version)
                 return;
 
-        pmu->nr_arch_gp_counters = min((int)(entry->eax >> 8) & 0xff,
-                        INTEL_PMC_MAX_GENERIC);
-        pmu->counter_bitmask[KVM_PMC_GP] =
-                ((u64)1 << ((entry->eax >> 16) & 0xff)) - 1;
-        bitmap_len = (entry->eax >> 24) & 0xff;
-        pmu->available_event_types = ~entry->ebx & ((1ull << bitmap_len) - 1);
+        pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
+                                        INTEL_PMC_MAX_GENERIC);
+        pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
+        pmu->available_event_types = ~entry->ebx &
+                                        ((1ull << eax.split.mask_length) - 1);
 
         if (pmu->version == 1) {
                 pmu->nr_arch_fixed_counters = 0;
         } else {
-                pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f),
+                pmu->nr_arch_fixed_counters =
+                        min_t(int, edx.split.num_counters_fixed,
                                 INTEL_PMC_MAX_FIXED);
                 pmu->counter_bitmask[KVM_PMC_FIXED] =
-                        ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1;
+                        ((u64)1 << edx.split.bit_width_fixed) - 1;
         }
 
         pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index ddf742768ecf..f7f6a4a157a6 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -622,7 +622,7 @@ static int has_svm(void)
         return 1;
 }
 
-static void svm_hardware_disable(void *garbage)
+static void svm_hardware_disable(void)
 {
         /* Make sure we clean up behind us */
         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
@@ -633,7 +633,7 @@ static void svm_hardware_disable(void *garbage)
         amd_pmu_disable_virt();
 }
 
-static int svm_hardware_enable(void *garbage)
+static int svm_hardware_enable(void)
 {
 
         struct svm_cpu_data *sd;
@@ -1257,7 +1257,8 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
         svm->asid_generation = 0;
         init_vmcb(svm);
 
-        svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
+        svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
+                                   MSR_IA32_APICBASE_ENABLE;
         if (kvm_vcpu_is_bsp(&svm->vcpu))
                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 
@@ -1974,10 +1975,26 @@ static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
 {
         struct vcpu_svm *svm = to_svm(vcpu);
 
-        svm->vmcb->control.exit_code = SVM_EXIT_NPF;
-        svm->vmcb->control.exit_code_hi = 0;
-        svm->vmcb->control.exit_info_1 = fault->error_code;
-        svm->vmcb->control.exit_info_2 = fault->address;
+        if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
+                /*
+                 * TODO: track the cause of the nested page fault, and
+                 * correctly fill in the high bits of exit_info_1.
+                 */
+                svm->vmcb->control.exit_code = SVM_EXIT_NPF;
+                svm->vmcb->control.exit_code_hi = 0;
+                svm->vmcb->control.exit_info_1 = (1ULL << 32);
+                svm->vmcb->control.exit_info_2 = fault->address;
+        }
+
+        svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
+        svm->vmcb->control.exit_info_1 |= fault->error_code;
+
+        /*
+         * The present bit is always zero for page structure faults on real
+         * hardware.
+         */
+        if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
+                svm->vmcb->control.exit_info_1 &= ~1;
 
         nested_svm_vmexit(svm);
 }
@@ -3031,7 +3048,7 @@ static int cr8_write_interception(struct vcpu_svm *svm)
         return 0;
 }
 
-u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
+static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
 {
         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
         return vmcb->control.tsc_offset +
@@ -4305,6 +4322,10 @@ static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
         local_irq_enable();
 }
 
+static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
+{
+}
+
 static struct kvm_x86_ops svm_x86_ops = {
         .cpu_has_kvm_support = has_svm,
         .disabled_by_bios = is_disabled,
@@ -4349,7 +4370,6 @@ static struct kvm_x86_ops svm_x86_ops = {
         .cache_reg = svm_cache_reg,
         .get_rflags = svm_get_rflags,
         .set_rflags = svm_set_rflags,
-        .fpu_activate = svm_fpu_activate,
         .fpu_deactivate = svm_fpu_deactivate,
 
         .tlb_flush = svm_flush_tlb,
@@ -4406,6 +4426,8 @@ static struct kvm_x86_ops svm_x86_ops = {
 
         .check_intercept = svm_check_intercept,
         .handle_external_intr = svm_handle_external_intr,
+
+        .sched_in = svm_sched_in,
 };
 
 static int __init svm_init(void)
diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h
index e850a7d332be..6b06ab8748dd 100644
--- a/arch/x86/kvm/trace.h
+++ b/arch/x86/kvm/trace.h
@@ -415,15 +415,14 @@ TRACE_EVENT(kvm_apic_ipi,
 );
 
 TRACE_EVENT(kvm_apic_accept_irq,
-            TP_PROTO(__u32 apicid, __u16 dm, __u8 tm, __u8 vec, bool coalesced),
-            TP_ARGS(apicid, dm, tm, vec, coalesced),
+            TP_PROTO(__u32 apicid, __u16 dm, __u8 tm, __u8 vec),
+            TP_ARGS(apicid, dm, tm, vec),
 
         TP_STRUCT__entry(
                 __field(        __u32,          apicid          )
                 __field(        __u16,          dm              )
                 __field(        __u8,           tm              )
                 __field(        __u8,           vec             )
-                __field(        bool,           coalesced       )
         ),
 
         TP_fast_assign(
@@ -431,14 +430,12 @@ TRACE_EVENT(kvm_apic_accept_irq,
                 __entry->dm             = dm;
                 __entry->tm             = tm;
                 __entry->vec            = vec;
-                __entry->coalesced      = coalesced;
         ),
 
-        TP_printk("apicid %x vec %u (%s|%s)%s",
+        TP_printk("apicid %x vec %u (%s|%s)",
                   __entry->apicid, __entry->vec,
                   __print_symbolic((__entry->dm >> 8 & 0x7), kvm_deliver_mode),
-                  __entry->tm ? "level" : "edge",
-                  __entry->coalesced ? " (coalesced)" : "")
+                  __entry->tm ? "level" : "edge")
 );
 
 TRACE_EVENT(kvm_eoi,
@@ -850,6 +847,36 @@ TRACE_EVENT(kvm_track_tsc,
 
 #endif /* CONFIG_X86_64 */
 
+TRACE_EVENT(kvm_ple_window,
+        TP_PROTO(bool grow, unsigned int vcpu_id, int new, int old),
+        TP_ARGS(grow, vcpu_id, new, old),
+
+        TP_STRUCT__entry(
+                __field(                bool,      grow         )
+                __field(        unsigned int,   vcpu_id         )
+                __field(                 int,       new         )
+                __field(                 int,       old         )
+        ),
+
+        TP_fast_assign(
+                __entry->grow           = grow;
+                __entry->vcpu_id        = vcpu_id;
+                __entry->new            = new;
+                __entry->old            = old;
+        ),
+
+        TP_printk("vcpu %u: ple_window %d (%s %d)",
+                  __entry->vcpu_id,
+                  __entry->new,
+                  __entry->grow ? "grow" : "shrink",
+                  __entry->old)
+);
+
+#define trace_kvm_ple_window_grow(vcpu_id, new, old) \
+        trace_kvm_ple_window(true, vcpu_id, new, old)
+#define trace_kvm_ple_window_shrink(vcpu_id, new, old) \
+        trace_kvm_ple_window(false, vcpu_id, new, old)
+
 #endif /* _TRACE_KVM_H */
 
 #undef TRACE_INCLUDE_PATH
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index bfe11cf124a1..04fa1b8298c8 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -125,14 +125,32 @@ module_param(nested, bool, S_IRUGO);
  * Time is measured based on a counter that runs at the same rate as the TSC,
  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  */
-#define KVM_VMX_DEFAULT_PLE_GAP    128
-#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
+#define KVM_VMX_DEFAULT_PLE_GAP           128
+#define KVM_VMX_DEFAULT_PLE_WINDOW        4096
+#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
+#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
+#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
+                INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
+
 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 module_param(ple_gap, int, S_IRUGO);
 
 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 module_param(ple_window, int, S_IRUGO);
 
+/* Default doubles per-vcpu window every exit. */
+static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
+module_param(ple_window_grow, int, S_IRUGO);
+
+/* Default resets per-vcpu window every exit to ple_window. */
+static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
+module_param(ple_window_shrink, int, S_IRUGO);
+
+/* Default is to compute the maximum so we can never overflow. */
+static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
+static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
+module_param(ple_window_max, int, S_IRUGO);
+
 extern const ulong vmx_return;
 
 #define NR_AUTOLOAD_MSRS 8
@@ -379,6 +397,7 @@ struct nested_vmx {
          * we must keep them pinned while L2 runs.
          */
         struct page *apic_access_page;
+        struct page *virtual_apic_page;
         u64 msr_ia32_feature_control;
 
         struct hrtimer preemption_timer;
@@ -484,6 +503,10 @@ struct vcpu_vmx {
 
         /* Support for a guest hypervisor (nested VMX) */
         struct nested_vmx nested;
+
+        /* Dynamic PLE window. */
+        int ple_window;
+        bool ple_window_dirty;
 };
 
 enum segment_cache_field {
@@ -533,6 +556,7 @@ static int max_shadow_read_only_fields =
         ARRAY_SIZE(shadow_read_only_fields);
 
 static unsigned long shadow_read_write_fields[] = {
+        TPR_THRESHOLD,
         GUEST_RIP,
         GUEST_RSP,
         GUEST_CR0,
@@ -743,6 +767,7 @@ static u32 vmx_segment_access_rights(struct kvm_segment *var);
 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
+static int alloc_identity_pagetable(struct kvm *kvm);
 
 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -2135,7 +2160,7 @@ static u64 guest_read_tsc(void)
  * Like guest_read_tsc, but always returns L1's notion of the timestamp
  * counter, even if a nested guest (L2) is currently running.
  */
-u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
+static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
 {
         u64 tsc_offset;
 
@@ -2330,7 +2355,7 @@ static __init void nested_vmx_setup_ctls_msrs(void)
                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
-                CPU_BASED_PAUSE_EXITING |
+                CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
         /*
          * We can allow some features even when not supported by the
@@ -2601,6 +2626,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                 break;
         case MSR_IA32_CR_PAT:
                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
+                        if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
+                                return 1;
                         vmcs_write64(GUEST_IA32_PAT, data);
                         vcpu->arch.pat = data;
                         break;
@@ -2704,7 +2731,7 @@ static void kvm_cpu_vmxon(u64 addr)
                         : "memory", "cc");
 }
 
-static int hardware_enable(void *garbage)
+static int hardware_enable(void)
 {
         int cpu = raw_smp_processor_id();
         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
@@ -2768,7 +2795,7 @@ static void kvm_cpu_vmxoff(void)
         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
 }
 
-static void hardware_disable(void *garbage)
+static void hardware_disable(void)
 {
         if (vmm_exclusive) {
                 vmclear_local_loaded_vmcss();
@@ -3107,9 +3134,17 @@ static __init int hardware_setup(void)
         if (!cpu_has_vmx_unrestricted_guest())
                 enable_unrestricted_guest = 0;
 
-        if (!cpu_has_vmx_flexpriority())
+        if (!cpu_has_vmx_flexpriority()) {
                 flexpriority_enabled = 0;
 
+                /*
+                 * set_apic_access_page_addr() is used to reload apic access
+                 * page upon invalidation.  No need to do anything if the
+                 * processor does not have the APIC_ACCESS_ADDR VMCS field.
+                 */
+                kvm_x86_ops->set_apic_access_page_addr = NULL;
+        }
+
         if (!cpu_has_vmx_tpr_shadow())
                 kvm_x86_ops->update_cr8_intercept = NULL;
 
@@ -3905,7 +3940,7 @@ static int init_rmode_tss(struct kvm *kvm)
 {
         gfn_t fn;
         u16 data = 0;
-        int r, idx, ret = 0;
+        int idx, r;
 
         idx = srcu_read_lock(&kvm->srcu);
         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
@@ -3927,32 +3962,32 @@ static int init_rmode_tss(struct kvm *kvm)
         r = kvm_write_guest_page(kvm, fn, &data,
                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
                                  sizeof(u8));
-        if (r < 0)
-                goto out;
-
-        ret = 1;
 out:
         srcu_read_unlock(&kvm->srcu, idx);
-        return ret;
+        return r;
 }
 
 static int init_rmode_identity_map(struct kvm *kvm)
 {
-        int i, idx, r, ret;
+        int i, idx, r = 0;
         pfn_t identity_map_pfn;
         u32 tmp;
 
         if (!enable_ept)
-                return 1;
-        if (unlikely(!kvm->arch.ept_identity_pagetable)) {
-                printk(KERN_ERR "EPT: identity-mapping pagetable "
-                        "haven't been allocated!\n");
                 return 0;
-        }
+
+        /* Protect kvm->arch.ept_identity_pagetable_done. */
+        mutex_lock(&kvm->slots_lock);
+
         if (likely(kvm->arch.ept_identity_pagetable_done))
-                return 1;
-        ret = 0;
+                goto out2;
+
         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
+
+        r = alloc_identity_pagetable(kvm);
+        if (r < 0)
+                goto out2;
+
         idx = srcu_read_lock(&kvm->srcu);
         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
         if (r < 0)
@@ -3967,10 +4002,13 @@ static int init_rmode_identity_map(struct kvm *kvm)
                         goto out;
         }
         kvm->arch.ept_identity_pagetable_done = true;
-        ret = 1;
+
 out:
         srcu_read_unlock(&kvm->srcu, idx);
-        return ret;
+
+out2:
+        mutex_unlock(&kvm->slots_lock);
+        return r;
 }
 
 static void seg_setup(int seg)
@@ -3995,23 +4033,28 @@ static int alloc_apic_access_page(struct kvm *kvm)
         int r = 0;
 
         mutex_lock(&kvm->slots_lock);
-        if (kvm->arch.apic_access_page)
+        if (kvm->arch.apic_access_page_done)
                 goto out;
         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
         kvm_userspace_mem.flags = 0;
-        kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
+        kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
         kvm_userspace_mem.memory_size = PAGE_SIZE;
         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
         if (r)
                 goto out;
 
-        page = gfn_to_page(kvm, 0xfee00);
+        page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
         if (is_error_page(page)) {
                 r = -EFAULT;
                 goto out;
         }
 
-        kvm->arch.apic_access_page = page;
+        /*
+         * Do not pin the page in memory, so that memory hot-unplug
+         * is able to migrate it.
+         */
+        put_page(page);
+        kvm->arch.apic_access_page_done = true;
 out:
         mutex_unlock(&kvm->slots_lock);
         return r;
@@ -4019,31 +4062,20 @@ out:
 
 static int alloc_identity_pagetable(struct kvm *kvm)
 {
-        struct page *page;
+        /* Called with kvm->slots_lock held. */
+
         struct kvm_userspace_memory_region kvm_userspace_mem;
         int r = 0;
 
-        mutex_lock(&kvm->slots_lock);
-        if (kvm->arch.ept_identity_pagetable)
-                goto out;
+        BUG_ON(kvm->arch.ept_identity_pagetable_done);
+
         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
         kvm_userspace_mem.flags = 0;
         kvm_userspace_mem.guest_phys_addr =
                 kvm->arch.ept_identity_map_addr;
         kvm_userspace_mem.memory_size = PAGE_SIZE;
         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
-        if (r)
-                goto out;
-
-        page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
-        if (is_error_page(page)) {
-                r = -EFAULT;
-                goto out;
-        }
 
-        kvm->arch.ept_identity_pagetable = page;
-out:
-        mutex_unlock(&kvm->slots_lock);
         return r;
 }
 
@@ -4402,7 +4434,8 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 
         if (ple_gap) {
                 vmcs_write32(PLE_GAP, ple_gap);
-                vmcs_write32(PLE_WINDOW, ple_window);
+                vmx->ple_window = ple_window;
+                vmx->ple_window_dirty = true;
         }
 
         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
@@ -4477,7 +4510,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
 
         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
         kvm_set_cr8(&vmx->vcpu, 0);
-        apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
+        apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
         if (kvm_vcpu_is_bsp(&vmx->vcpu))
                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
         apic_base_msr.host_initiated = true;
@@ -4537,9 +4570,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
                 vmcs_write32(TPR_THRESHOLD, 0);
         }
 
-        if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
-                vmcs_write64(APIC_ACCESS_ADDR,
-                             page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
+        kvm_vcpu_reload_apic_access_page(vcpu);
 
         if (vmx_vm_has_apicv(vcpu->kvm))
                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
@@ -4729,10 +4760,7 @@ static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
         if (ret)
                 return ret;
         kvm->arch.tss_addr = addr;
-        if (!init_rmode_tss(kvm))
-                return  -ENOMEM;
-
-        return 0;
+        return init_rmode_tss(kvm);
 }
 
 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
@@ -5521,17 +5549,18 @@ static u64 ept_rsvd_mask(u64 spte, int level)
         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
                 mask |= (1ULL << i);
 
-        if (level > 2)
+        if (level == 4)
                 /* bits 7:3 reserved */
                 mask |= 0xf8;
-        else if (level == 2) {
-                if (spte & (1ULL << 7))
-                        /* 2MB ref, bits 20:12 reserved */
-                        mask |= 0x1ff000;
-                else
-                        /* bits 6:3 reserved */
-                        mask |= 0x78;
-        }
+        else if (spte & (1ULL << 7))
+                /*
+                 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
+                 * level == 1 if the hypervisor is using the ignored bit 7.
+                 */
+                mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
+        else if (level > 1)
+                /* bits 6:3 reserved */
+                mask |= 0x78;
 
         return mask;
 }
@@ -5561,7 +5590,8 @@ static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
                         WARN_ON(1);
                 }
 
-                if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
+                /* bits 5:3 are _not_ reserved for large page or leaf page */
+                if ((rsvd_bits & 0x38) == 0) {
                         u64 ept_mem_type = (spte & 0x38) >> 3;
 
                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
@@ -5676,12 +5706,85 @@ out:
         return ret;
 }
 
+static int __grow_ple_window(int val)
+{
+        if (ple_window_grow < 1)
+                return ple_window;
+
+        val = min(val, ple_window_actual_max);
+
+        if (ple_window_grow < ple_window)
+                val *= ple_window_grow;
+        else
+                val += ple_window_grow;
+
+        return val;
+}
+
+static int __shrink_ple_window(int val, int modifier, int minimum)
+{
+        if (modifier < 1)
+                return ple_window;
+
+        if (modifier < ple_window)
+                val /= modifier;
+        else
+                val -= modifier;
+
+        return max(val, minimum);
+}
+
+static void grow_ple_window(struct kvm_vcpu *vcpu)
+{
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+        int old = vmx->ple_window;
+
+        vmx->ple_window = __grow_ple_window(old);
+
+        if (vmx->ple_window != old)
+                vmx->ple_window_dirty = true;
+
+        trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
+}
+
+static void shrink_ple_window(struct kvm_vcpu *vcpu)
+{
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+        int old = vmx->ple_window;
+
+        vmx->ple_window = __shrink_ple_window(old,
+                                              ple_window_shrink, ple_window);
+
+        if (vmx->ple_window != old)
+                vmx->ple_window_dirty = true;
+
+        trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
+}
+
+/*
+ * ple_window_actual_max is computed to be one grow_ple_window() below
+ * ple_window_max. (See __grow_ple_window for the reason.)
+ * This prevents overflows, because ple_window_max is int.
+ * ple_window_max effectively rounded down to a multiple of ple_window_grow in
+ * this process.
+ * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
+ */
+static void update_ple_window_actual_max(void)
+{
+        ple_window_actual_max =
+                        __shrink_ple_window(max(ple_window_max, ple_window),
+                                            ple_window_grow, INT_MIN);
+}
+
 /*
  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
  */
 static int handle_pause(struct kvm_vcpu *vcpu)
 {
+        if (ple_gap)
+                grow_ple_window(vcpu);
+
         skip_emulated_instruction(vcpu);
         kvm_vcpu_on_spin(vcpu);
 
@@ -6146,7 +6249,11 @@ static void free_nested(struct vcpu_vmx *vmx)
         /* Unpin physical memory we referred to in current vmcs02 */
         if (vmx->nested.apic_access_page) {
                 nested_release_page(vmx->nested.apic_access_page);
-                vmx->nested.apic_access_page = 0;
+                vmx->nested.apic_access_page = NULL;
+        }
+        if (vmx->nested.virtual_apic_page) {
+                nested_release_page(vmx->nested.virtual_apic_page);
+                vmx->nested.virtual_apic_page = NULL;
         }
 
         nested_free_all_saved_vmcss(vmx);
@@ -6617,7 +6724,7 @@ static int handle_invept(struct kvm_vcpu *vcpu)
         switch (type) {
         case VMX_EPT_EXTENT_GLOBAL:
                 kvm_mmu_sync_roots(vcpu);
-                kvm_mmu_flush_tlb(vcpu);
+                kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
                 nested_vmx_succeed(vcpu);
                 break;
         default:
@@ -6892,6 +6999,8 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
         case EXIT_REASON_TASK_SWITCH:
                 return 1;
         case EXIT_REASON_CPUID:
+                if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
+                        return 0;
                 return 1;
         case EXIT_REASON_HLT:
                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
@@ -6936,7 +7045,7 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
         case EXIT_REASON_MCE_DURING_VMENTRY:
                 return 0;
         case EXIT_REASON_TPR_BELOW_THRESHOLD:
-                return 1;
+                return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
         case EXIT_REASON_APIC_ACCESS:
                 return nested_cpu_has2(vmcs12,
                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
@@ -7057,6 +7166,12 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
 
 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
 {
+        struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+
+        if (is_guest_mode(vcpu) &&
+                nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
+                return;
+
         if (irr == -1 || tpr < irr) {
                 vmcs_write32(TPR_THRESHOLD, 0);
                 return;
@@ -7094,6 +7209,29 @@ static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
         vmx_set_msr_bitmap(vcpu);
 }
 
+static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
+{
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+        /*
+         * Currently we do not handle the nested case where L2 has an
+         * APIC access page of its own; that page is still pinned.
+         * Hence, we skip the case where the VCPU is in guest mode _and_
+         * L1 prepared an APIC access page for L2.
+         *
+         * For the case where L1 and L2 share the same APIC access page
+         * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
+         * in the vmcs12), this function will only update either the vmcs01
+         * or the vmcs02.  If the former, the vmcs02 will be updated by
+         * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
+         * the next L2->L1 exit.
+         */
+        if (!is_guest_mode(vcpu) ||
+            !nested_cpu_has2(vmx->nested.current_vmcs12,
+                             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
+                vmcs_write64(APIC_ACCESS_ADDR, hpa);
+}
+
 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
 {
         u16 status;
@@ -7387,6 +7525,11 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
         if (vmx->emulation_required)
                 return;
 
+        if (vmx->ple_window_dirty) {
+                vmx->ple_window_dirty = false;
+                vmcs_write32(PLE_WINDOW, vmx->ple_window);
+        }
+
         if (vmx->nested.sync_shadow_vmcs) {
                 copy_vmcs12_to_shadow(vmx);
                 vmx->nested.sync_shadow_vmcs = false;
@@ -7642,10 +7785,8 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
                 if (!kvm->arch.ept_identity_map_addr)
                         kvm->arch.ept_identity_map_addr =
                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
-                err = -ENOMEM;
-                if (alloc_identity_pagetable(kvm) != 0)
-                        goto free_vmcs;
-                if (!init_rmode_identity_map(kvm))
+                err = init_rmode_identity_map(kvm);
+                if (err)
                         goto free_vmcs;
         }
 
@@ -7824,6 +7965,55 @@ static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
                 kvm_inject_page_fault(vcpu, fault);
 }
 
+static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
+                                        struct vmcs12 *vmcs12)
+{
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+        if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
+                /* TODO: Also verify bits beyond physical address width are 0 */
+                if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
+                        return false;
+
+                /*
+                 * Translate L1 physical address to host physical
+                 * address for vmcs02. Keep the page pinned, so this
+                 * physical address remains valid. We keep a reference
+                 * to it so we can release it later.
+                 */
+                if (vmx->nested.apic_access_page) /* shouldn't happen */
+                        nested_release_page(vmx->nested.apic_access_page);
+                vmx->nested.apic_access_page =
+                        nested_get_page(vcpu, vmcs12->apic_access_addr);
+        }
+
+        if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
+                /* TODO: Also verify bits beyond physical address width are 0 */
+                if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
+                        return false;
+
+                if (vmx->nested.virtual_apic_page) /* shouldn't happen */
+                        nested_release_page(vmx->nested.virtual_apic_page);
+                vmx->nested.virtual_apic_page =
+                        nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
+
+                /*
+                 * Failing the vm entry is _not_ what the processor does
+                 * but it's basically the only possibility we have.
+                 * We could still enter the guest if CR8 load exits are
+                 * enabled, CR8 store exits are enabled, and virtualize APIC
+                 * access is disabled; in this case the processor would never
+                 * use the TPR shadow and we could simply clear the bit from
+                 * the execution control.  But such a configuration is useless,
+                 * so let's keep the code simple.
+                 */
+                if (!vmx->nested.virtual_apic_page)
+                        return false;
+        }
+
+        return true;
+}
+
 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
 {
         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
@@ -7849,7 +8039,7 @@ static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
 /*
  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
- * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
+ * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
  * guest in a way that will both be appropriate to L1's requests, and our
  * needs. In addition to modifying the active vmcs (which is vmcs02), this
  * function also has additional necessary side-effects, like setting various
@@ -7970,16 +8160,6 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 
                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
                         /*
-                         * Translate L1 physical address to host physical
-                         * address for vmcs02. Keep the page pinned, so this
-                         * physical address remains valid. We keep a reference
-                         * to it so we can release it later.
-                         */
-                        if (vmx->nested.apic_access_page) /* shouldn't happen */
-                                nested_release_page(vmx->nested.apic_access_page);
-                        vmx->nested.apic_access_page =
-                                nested_get_page(vcpu, vmcs12->apic_access_addr);
-                        /*
                          * If translation failed, no matter: This feature asks
                          * to exit when accessing the given address, and if it
                          * can never be accessed, this feature won't do
@@ -7994,8 +8174,7 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
                         exec_control |=
                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
-                        vmcs_write64(APIC_ACCESS_ADDR,
-                                page_to_phys(vcpu->kvm->arch.apic_access_page));
+                        kvm_vcpu_reload_apic_access_page(vcpu);
                 }
 
                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
@@ -8024,6 +8203,13 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
         exec_control &= ~CPU_BASED_TPR_SHADOW;
         exec_control |= vmcs12->cpu_based_vm_exec_control;
+
+        if (exec_control & CPU_BASED_TPR_SHADOW) {
+                vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
+                                page_to_phys(vmx->nested.virtual_apic_page));
+                vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
+        }
+
         /*
          * Merging of IO and MSR bitmaps not currently supported.
          * Rather, exit every time.
@@ -8185,8 +8371,7 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
                 return 1;
         }
 
-        if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
-                        !PAGE_ALIGNED(vmcs12->apic_access_addr)) {
+        if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
                 /*TODO: Also verify bits beyond physical address width are 0*/
                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
                 return 1;
@@ -8790,10 +8975,20 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
         /* Unpin physical memory we referred to in vmcs02 */
         if (vmx->nested.apic_access_page) {
                 nested_release_page(vmx->nested.apic_access_page);
-                vmx->nested.apic_access_page = 0;
+                vmx->nested.apic_access_page = NULL;
+        }
+        if (vmx->nested.virtual_apic_page) {
+                nested_release_page(vmx->nested.virtual_apic_page);
+                vmx->nested.virtual_apic_page = NULL;
         }
 
         /*
+         * We are now running in L2, mmu_notifier will force to reload the
+         * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
+         */
+        kvm_vcpu_reload_apic_access_page(vcpu);
+
+        /*
          * Exiting from L2 to L1, we're now back to L1 which thinks it just
          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
          * success or failure flag accordingly.
@@ -8846,6 +9041,12 @@ static int vmx_check_intercept(struct kvm_vcpu *vcpu,
         return X86EMUL_CONTINUE;
 }
 
+static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
+{
+        if (ple_gap)
+                shrink_ple_window(vcpu);
+}
+
 static struct kvm_x86_ops vmx_x86_ops = {
         .cpu_has_kvm_support = cpu_has_kvm_support,
         .disabled_by_bios = vmx_disabled_by_bios,
@@ -8890,7 +9091,6 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .cache_reg = vmx_cache_reg,
         .get_rflags = vmx_get_rflags,
         .set_rflags = vmx_set_rflags,
-        .fpu_activate = vmx_fpu_activate,
         .fpu_deactivate = vmx_fpu_deactivate,
 
         .tlb_flush = vmx_flush_tlb,
@@ -8913,6 +9113,7 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .enable_irq_window = enable_irq_window,
         .update_cr8_intercept = update_cr8_intercept,
         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
+        .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
         .vm_has_apicv = vmx_vm_has_apicv,
         .load_eoi_exitmap = vmx_load_eoi_exitmap,
         .hwapic_irr_update = vmx_hwapic_irr_update,
@@ -8951,6 +9152,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .mpx_supported = vmx_mpx_supported,
 
         .check_nested_events = vmx_check_nested_events,
+
+        .sched_in = vmx_sched_in,
 };
 
 static int __init vmx_init(void)
@@ -9065,6 +9268,8 @@ static int __init vmx_init(void)
         } else
                 kvm_disable_tdp();
 
+        update_ple_window_actual_max();
+
         return 0;
 
 out7:
@@ -9098,7 +9303,7 @@ static void __exit vmx_exit(void)
         free_page((unsigned long)vmx_vmread_bitmap);
 
 #ifdef CONFIG_KEXEC
-        rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
+        RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
         synchronize_rcu();
 #endif
 
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 8f1e22d3b286..5430e4b0af29 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -246,7 +246,7 @@ void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 }
 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 
-static void drop_user_return_notifiers(void *ignore)
+static void drop_user_return_notifiers(void)
 {
         unsigned int cpu = smp_processor_id();
         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
@@ -408,12 +408,14 @@ void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 }
 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 
-void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
+static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 {
         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
         else
                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
+
+        return fault->nested_page_fault;
 }
 
 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
@@ -457,11 +459,12 @@ int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
                             gfn_t ngfn, void *data, int offset, int len,
                             u32 access)
 {
+        struct x86_exception exception;
         gfn_t real_gfn;
         gpa_t ngpa;
 
         ngpa     = gfn_to_gpa(ngfn);
-        real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
+        real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
         if (real_gfn == UNMAPPED_GVA)
                 return -EFAULT;
 
@@ -726,7 +729,7 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 {
         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
                 kvm_mmu_sync_roots(vcpu);
-                kvm_mmu_flush_tlb(vcpu);
+                kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
                 return 0;
         }
 
@@ -1518,7 +1521,7 @@ static void kvm_gen_update_masterclock(struct kvm *kvm)
         pvclock_update_vm_gtod_copy(kvm);
 
         kvm_for_each_vcpu(i, vcpu, kvm)
-                set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
+                kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
 
         /* guest entries allowed */
         kvm_for_each_vcpu(i, vcpu, kvm)
@@ -1661,7 +1664,7 @@ static void kvmclock_update_fn(struct work_struct *work)
         struct kvm_vcpu *vcpu;
 
         kvm_for_each_vcpu(i, vcpu, kvm) {
-                set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
+                kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
                 kvm_vcpu_kick(vcpu);
         }
 }
@@ -1670,7 +1673,7 @@ static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
 {
         struct kvm *kvm = v->kvm;
 
-        set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
+        kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
                                         KVMCLOCK_UPDATE_DELAY);
 }
@@ -1723,9 +1726,10 @@ static bool valid_mtrr_type(unsigned t)
         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
 }
 
-static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
+bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 {
         int i;
+        u64 mask;
 
         if (!msr_mtrr_valid(msr))
                 return false;
@@ -1747,14 +1751,31 @@ static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
         }
 
         /* variable MTRRs */
-        return valid_mtrr_type(data & 0xff);
+        WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
+
+        mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
+        if ((msr & 1) == 0) {
+                /* MTRR base */
+                if (!valid_mtrr_type(data & 0xff))
+                        return false;
+                mask |= 0xf00;
+        } else
+                /* MTRR mask */
+                mask |= 0x7ff;
+        if (data & mask) {
+                kvm_inject_gp(vcpu, 0);
+                return false;
+        }
+
+        return true;
 }
+EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
 
 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 {
         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
 
-        if (!mtrr_valid(vcpu, msr, data))
+        if (!kvm_mtrr_valid(vcpu, msr, data))
                 return 1;
 
         if (msr == MSR_MTRRdefType) {
@@ -1805,7 +1826,7 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                 break;
         default:
                 if (msr >= MSR_IA32_MC0_CTL &&
-                    msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
+                    msr < MSR_IA32_MCx_CTL(bank_num)) {
                         u32 offset = msr - MSR_IA32_MC0_CTL;
                         /* only 0 or all 1s can be written to IA32_MCi_CTL
                          * some Linux kernels though clear bit 10 in bank 4 to
@@ -2164,7 +2185,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 
         case MSR_IA32_MCG_CTL:
         case MSR_IA32_MCG_STATUS:
-        case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
+        case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
                 return set_msr_mce(vcpu, msr, data);
 
         /* Performance counters are not protected by a CPUID bit,
@@ -2330,7 +2351,7 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
                 break;
         default:
                 if (msr >= MSR_IA32_MC0_CTL &&
-                    msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
+                    msr < MSR_IA32_MCx_CTL(bank_num)) {
                         u32 offset = msr - MSR_IA32_MC0_CTL;
                         data = vcpu->arch.mce_banks[offset];
                         break;
@@ -2419,7 +2440,13 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
         case MSR_K7_HWCR:
         case MSR_VM_HSAVE_PA:
         case MSR_K7_EVNTSEL0:
+        case MSR_K7_EVNTSEL1:
+        case MSR_K7_EVNTSEL2:
+        case MSR_K7_EVNTSEL3:
         case MSR_K7_PERFCTR0:
+        case MSR_K7_PERFCTR1:
+        case MSR_K7_PERFCTR2:
+        case MSR_K7_PERFCTR3:
         case MSR_K8_INT_PENDING_MSG:
         case MSR_AMD64_NB_CFG:
         case MSR_FAM10H_MMIO_CONF_BASE:
@@ -2505,7 +2532,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
         case MSR_IA32_MCG_CAP:
         case MSR_IA32_MCG_CTL:
         case MSR_IA32_MCG_STATUS:
-        case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
+        case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
                 return get_msr_mce(vcpu, msr, pdata);
         case MSR_K7_CLK_CTL:
                 /*
@@ -2823,7 +2850,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
                 vcpu->arch.tsc_offset_adjustment = 0;
-                set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
+                kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
         }
 
         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
@@ -4040,16 +4067,16 @@ void kvm_get_segment(struct kvm_vcpu *vcpu,
         kvm_x86_ops->get_segment(vcpu, var, seg);
 }
 
-gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
+gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
+                           struct x86_exception *exception)
 {
         gpa_t t_gpa;
-        struct x86_exception exception;
 
         BUG_ON(!mmu_is_nested(vcpu));
 
         /* NPT walks are always user-walks */
         access |= PFERR_USER_MASK;
-        t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
+        t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
 
         return t_gpa;
 }
@@ -4906,16 +4933,18 @@ static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
         }
 }
 
-static void inject_emulated_exception(struct kvm_vcpu *vcpu)
+static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
 {
         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
         if (ctxt->exception.vector == PF_VECTOR)
-                kvm_propagate_fault(vcpu, &ctxt->exception);
-        else if (ctxt->exception.error_code_valid)
+                return kvm_propagate_fault(vcpu, &ctxt->exception);
+
+        if (ctxt->exception.error_code_valid)
                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
                                       ctxt->exception.error_code);
         else
                 kvm_queue_exception(vcpu, ctxt->exception.vector);
+        return false;
 }
 
 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
@@ -4972,7 +5001,7 @@ static int handle_emulation_failure(struct kvm_vcpu *vcpu)
 
         ++vcpu->stat.insn_emulation_fail;
         trace_kvm_emulate_insn_failed(vcpu);
-        if (!is_guest_mode(vcpu)) {
+        if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
                 vcpu->run->internal.ndata = 0;
@@ -5224,6 +5253,7 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
 
                 ctxt->interruptibility = 0;
                 ctxt->have_exception = false;
+                ctxt->exception.vector = -1;
                 ctxt->perm_ok = false;
 
                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
@@ -5276,8 +5306,9 @@ restart:
         }
 
         if (ctxt->have_exception) {
-                inject_emulated_exception(vcpu);
                 r = EMULATE_DONE;
+                if (inject_emulated_exception(vcpu))
+                        return r;
         } else if (vcpu->arch.pio.count) {
                 if (!vcpu->arch.pio.in) {
                         /* FIXME: return into emulator if single-stepping.  */
@@ -5545,7 +5576,7 @@ static void kvm_set_mmio_spte_mask(void)
          * entry to generate page fault with PFER.RSV = 1.
          */
          /* Mask the reserved physical address bits. */
-        mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
+        mask = rsvd_bits(maxphyaddr, 51);
 
         /* Bit 62 is always reserved for 32bit host. */
         mask |= 0x3ull << 62;
@@ -5576,7 +5607,7 @@ static void pvclock_gtod_update_fn(struct work_struct *work)
         spin_lock(&kvm_lock);
         list_for_each_entry(kvm, &vm_list, vm_list)
                 kvm_for_each_vcpu(i, vcpu, kvm)
-                        set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
+                        kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
         atomic_set(&kvm_guest_has_master_clock, 0);
         spin_unlock(&kvm_lock);
 }
@@ -5989,6 +6020,44 @@ static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
         kvm_apic_update_tmr(vcpu, tmr);
 }
 
+static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
+{
+        ++vcpu->stat.tlb_flush;
+        kvm_x86_ops->tlb_flush(vcpu);
+}
+
+void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
+{
+        struct page *page = NULL;
+
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return;
+
+        if (!kvm_x86_ops->set_apic_access_page_addr)
+                return;
+
+        page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
+        kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
+
+        /*
+         * Do not pin apic access page in memory, the MMU notifier
+         * will call us again if it is migrated or swapped out.
+         */
+        put_page(page);
+}
+EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
+
+void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
+                                           unsigned long address)
+{
+        /*
+         * The physical address of apic access page is stored in the VMCS.
+         * Update it when it becomes invalid.
+         */
+        if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
+                kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
+}
+
 /*
  * Returns 1 to let __vcpu_run() continue the guest execution loop without
  * exiting to the userspace.  Otherwise, the value will be returned to the
@@ -6018,7 +6087,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
                         kvm_mmu_sync_roots(vcpu);
                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
-                        kvm_x86_ops->tlb_flush(vcpu);
+                        kvm_vcpu_flush_tlb(vcpu);
                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
                         r = 0;
@@ -6049,6 +6118,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                         kvm_deliver_pmi(vcpu);
                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
                         vcpu_scan_ioapic(vcpu);
+                if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
+                        kvm_vcpu_reload_apic_access_page(vcpu);
         }
 
         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
@@ -6934,7 +7005,7 @@ void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
         kvm_rip_write(vcpu, 0);
 }
 
-int kvm_arch_hardware_enable(void *garbage)
+int kvm_arch_hardware_enable(void)
 {
         struct kvm *kvm;
         struct kvm_vcpu *vcpu;
@@ -6945,7 +7016,7 @@ int kvm_arch_hardware_enable(void *garbage)
         bool stable, backwards_tsc = false;
 
         kvm_shared_msr_cpu_online();
-        ret = kvm_x86_ops->hardware_enable(garbage);
+        ret = kvm_x86_ops->hardware_enable();
         if (ret != 0)
                 return ret;
 
@@ -6954,7 +7025,7 @@ int kvm_arch_hardware_enable(void *garbage)
         list_for_each_entry(kvm, &vm_list, vm_list) {
                 kvm_for_each_vcpu(i, vcpu, kvm) {
                         if (!stable && vcpu->cpu == smp_processor_id())
-                                set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
+                                kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
                                 backwards_tsc = true;
                                 if (vcpu->arch.last_host_tsc > max_tsc)
@@ -7008,8 +7079,7 @@ int kvm_arch_hardware_enable(void *garbage)
                         kvm_for_each_vcpu(i, vcpu, kvm) {
                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
                                 vcpu->arch.last_host_tsc = local_tsc;
-                                set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
-                                        &vcpu->requests);
+                                kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
                         }
 
                         /*
@@ -7026,10 +7096,10 @@ int kvm_arch_hardware_enable(void *garbage)
         return 0;
 }
 
-void kvm_arch_hardware_disable(void *garbage)
+void kvm_arch_hardware_disable(void)
 {
-        kvm_x86_ops->hardware_disable(garbage);
-        drop_user_return_notifiers(garbage);
+        kvm_x86_ops->hardware_disable();
+        drop_user_return_notifiers();
 }
 
 int kvm_arch_hardware_setup(void)
@@ -7146,6 +7216,11 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
                 static_key_slow_dec(&kvm_no_apic_vcpu);
 }
 
+void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
+{
+        kvm_x86_ops->sched_in(vcpu, cpu);
+}
+
 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 {
         if (type)
@@ -7237,10 +7312,6 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
         kfree(kvm->arch.vpic);
         kfree(kvm->arch.vioapic);
         kvm_free_vcpus(kvm);
-        if (kvm->arch.apic_access_page)
-                put_page(kvm->arch.apic_access_page);
-        if (kvm->arch.ept_identity_pagetable)
-                put_page(kvm->arch.ept_identity_pagetable);
         kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
 }
 
@@ -7643,3 +7714,4 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
+EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 306a1b77581f..7cb9c45a5fe0 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -88,15 +88,23 @@ static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
         vcpu->arch.mmio_gva = gva & PAGE_MASK;
         vcpu->arch.access = access;
         vcpu->arch.mmio_gfn = gfn;
+        vcpu->arch.mmio_gen = kvm_memslots(vcpu->kvm)->generation;
+}
+
+static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
 }
 
 /*
- * Clear the mmio cache info for the given gva,
- * specially, if gva is ~0ul, we clear all mmio cache info.
+ * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
+ * clear all mmio cache info.
  */
+#define MMIO_GVA_ANY (~(gva_t)0)
+
 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
 {
-        if (gva != (~0ul) && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
+        if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
                 return;
 
         vcpu->arch.mmio_gva = 0;
@@ -104,7 +112,8 @@ static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
 
 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
 {
-        if (vcpu->arch.mmio_gva && vcpu->arch.mmio_gva == (gva & PAGE_MASK))
+        if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
+              vcpu->arch.mmio_gva == (gva & PAGE_MASK))
                 return true;
 
         return false;
@@ -112,7 +121,8 @@ static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
 
 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
 {
-        if (vcpu->arch.mmio_gfn && vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
+        if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
+              vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
                 return true;
 
         return false;
@@ -149,6 +159,8 @@ int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
         gva_t addr, void *val, unsigned int bytes,
         struct x86_exception *exception);
 
+bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
+
 #define KVM_SUPPORTED_XCR0     (XSTATE_FP | XSTATE_SSE | XSTATE_YMM \
                                 | XSTATE_BNDREGS | XSTATE_BNDCSR)
 extern u64 host_xcr0;
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c
index 167ffcac16ed..95a427e57887 100644
--- a/arch/x86/mm/dump_pagetables.c
+++ b/arch/x86/mm/dump_pagetables.c
@@ -48,7 +48,9 @@ enum address_markers_idx {
         LOW_KERNEL_NR,
         VMALLOC_START_NR,
         VMEMMAP_START_NR,
+# ifdef CONFIG_X86_ESPFIX64
         ESPFIX_START_NR,
+# endif
         HIGH_KERNEL_NR,
         MODULES_VADDR_NR,
         MODULES_END_NR,
@@ -71,7 +73,9 @@ static struct addr_marker address_markers[] = {
         { PAGE_OFFSET,          "Low Kernel Mapping" },
         { VMALLOC_START,        "vmalloc() Area" },
         { VMEMMAP_START,        "Vmemmap" },
+# ifdef CONFIG_X86_ESPFIX64
         { ESPFIX_BASE_ADDR,     "ESPfix Area", 16 },
+# endif
         { __START_KERNEL_map,   "High Kernel Mapping" },
         { MODULES_VADDR,        "Modules" },
         { MODULES_END,          "End Modules" },
diff --git a/arch/x86/mm/mmap.c b/arch/x86/mm/mmap.c
index 25e7e1372bb2..919b91205cd4 100644
--- a/arch/x86/mm/mmap.c
+++ b/arch/x86/mm/mmap.c
@@ -31,7 +31,7 @@
 #include <linux/sched.h>
 #include <asm/elf.h>
 
-struct __read_mostly va_alignment va_align = {
+struct va_alignment __read_mostly va_align = {
         .flags = -1,
 };
 
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 1fe33987de02..ee61c36d64f8 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -49,7 +49,13 @@ void leave_mm(int cpu)
         if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {
                 cpumask_clear_cpu(cpu, mm_cpumask(active_mm));
                 load_cr3(swapper_pg_dir);
-                trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
+                /*
+                 * This gets called in the idle path where RCU
+                 * functions differently.  Tracing normally
+                 * uses RCU, so we have to call the tracepoint
+                 * specially here.
+                 */
+                trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
         }
 }
 EXPORT_SYMBOL_GPL(leave_mm);
@@ -174,7 +180,7 @@ void flush_tlb_current_task(void)
  *
  * This is in units of pages.
  */
-unsigned long tlb_single_page_flush_ceiling = 33;
+static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
 
 void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
                                 unsigned long end, unsigned long vmflag)
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index 5c8cb8043c5a..d56cd1f515bd 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -8,12 +8,10 @@
  * as published by the Free Software Foundation; version 2
  * of the License.
  */
-#include <linux/moduleloader.h>
-#include <asm/cacheflush.h>
 #include <linux/netdevice.h>
 #include <linux/filter.h>
 #include <linux/if_vlan.h>
-#include <linux/random.h>
+#include <asm/cacheflush.h>
 
 int bpf_jit_enable __read_mostly;
 
@@ -109,39 +107,6 @@ static inline void bpf_flush_icache(void *start, void *end)
 #define CHOOSE_LOAD_FUNC(K, func) \
         ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
 
-struct bpf_binary_header {
-        unsigned int    pages;
-        /* Note : for security reasons, bpf code will follow a randomly
-         * sized amount of int3 instructions
-         */
-        u8              image[];
-};
-
-static struct bpf_binary_header *bpf_alloc_binary(unsigned int proglen,
-                                                  u8 **image_ptr)
-{
-        unsigned int sz, hole;
-        struct bpf_binary_header *header;
-
-        /* Most of BPF filters are really small,
-         * but if some of them fill a page, allow at least
-         * 128 extra bytes to insert a random section of int3
-         */
-        sz = round_up(proglen + sizeof(*header) + 128, PAGE_SIZE);
-        header = module_alloc(sz);
-        if (!header)
-                return NULL;
-
-        memset(header, 0xcc, sz); /* fill whole space with int3 instructions */
-
-        header->pages = sz / PAGE_SIZE;
-        hole = min(sz - (proglen + sizeof(*header)), PAGE_SIZE - sizeof(*header));
-
-        /* insert a random number of int3 instructions before BPF code */
-        *image_ptr = &header->image[prandom_u32() % hole];
-        return header;
-}
-
 /* pick a register outside of BPF range for JIT internal work */
 #define AUX_REG (MAX_BPF_REG + 1)
 
@@ -206,6 +171,12 @@ static inline u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
         return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
 }
 
+static void jit_fill_hole(void *area, unsigned int size)
+{
+        /* fill whole space with int3 instructions */
+        memset(area, 0xcc, size);
+}
+
 struct jit_context {
         unsigned int cleanup_addr; /* epilogue code offset */
         bool seen_ld_abs;
@@ -393,6 +364,23 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
                         EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
                         break;
 
+                case BPF_LD | BPF_IMM | BPF_DW:
+                        if (insn[1].code != 0 || insn[1].src_reg != 0 ||
+                            insn[1].dst_reg != 0 || insn[1].off != 0) {
+                                /* verifier must catch invalid insns */
+                                pr_err("invalid BPF_LD_IMM64 insn\n");
+                                return -EINVAL;
+                        }
+
+                        /* movabsq %rax, imm64 */
+                        EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
+                        EMIT(insn[0].imm, 4);
+                        EMIT(insn[1].imm, 4);
+
+                        insn++;
+                        i++;
+                        break;
+
                         /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
                 case BPF_ALU | BPF_MOD | BPF_X:
                 case BPF_ALU | BPF_DIV | BPF_X:
@@ -515,6 +503,48 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
                         EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
                         break;
 
+                case BPF_ALU | BPF_LSH | BPF_X:
+                case BPF_ALU | BPF_RSH | BPF_X:
+                case BPF_ALU | BPF_ARSH | BPF_X:
+                case BPF_ALU64 | BPF_LSH | BPF_X:
+                case BPF_ALU64 | BPF_RSH | BPF_X:
+                case BPF_ALU64 | BPF_ARSH | BPF_X:
+
+                        /* check for bad case when dst_reg == rcx */
+                        if (dst_reg == BPF_REG_4) {
+                                /* mov r11, dst_reg */
+                                EMIT_mov(AUX_REG, dst_reg);
+                                dst_reg = AUX_REG;
+                        }
+
+                        if (src_reg != BPF_REG_4) { /* common case */
+                                EMIT1(0x51); /* push rcx */
+
+                                /* mov rcx, src_reg */
+                                EMIT_mov(BPF_REG_4, src_reg);
+                        }
+
+                        /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
+                        if (BPF_CLASS(insn->code) == BPF_ALU64)
+                                EMIT1(add_1mod(0x48, dst_reg));
+                        else if (is_ereg(dst_reg))
+                                EMIT1(add_1mod(0x40, dst_reg));
+
+                        switch (BPF_OP(insn->code)) {
+                        case BPF_LSH: b3 = 0xE0; break;
+                        case BPF_RSH: b3 = 0xE8; break;
+                        case BPF_ARSH: b3 = 0xF8; break;
+                        }
+                        EMIT2(0xD3, add_1reg(b3, dst_reg));
+
+                        if (src_reg != BPF_REG_4)
+                                EMIT1(0x59); /* pop rcx */
+
+                        if (insn->dst_reg == BPF_REG_4)
+                                /* mov dst_reg, r11 */
+                                EMIT_mov(insn->dst_reg, AUX_REG);
+                        break;
+
                 case BPF_ALU | BPF_END | BPF_FROM_BE:
                         switch (imm32) {
                         case 16:
@@ -900,7 +930,7 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
                 if (proglen <= 0) {
                         image = NULL;
                         if (header)
-                                module_free(NULL, header);
+                                bpf_jit_binary_free(header);
                         goto out;
                 }
                 if (image) {
@@ -910,7 +940,8 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
                         break;
                 }
                 if (proglen == oldproglen) {
-                        header = bpf_alloc_binary(proglen, &image);
+                        header = bpf_jit_binary_alloc(proglen, &image,
+                                                      1, jit_fill_hole);
                         if (!header)
                                 goto out;
                 }
@@ -924,29 +955,23 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
                 bpf_flush_icache(header, image + proglen);
                 set_memory_ro((unsigned long)header, header->pages);
                 prog->bpf_func = (void *)image;
-                prog->jited = 1;
+                prog->jited = true;
         }
 out:
         kfree(addrs);
 }
 
-static void bpf_jit_free_deferred(struct work_struct *work)
+void bpf_jit_free(struct bpf_prog *fp)
 {
-        struct bpf_prog *fp = container_of(work, struct bpf_prog, work);
         unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
         struct bpf_binary_header *header = (void *)addr;
 
+        if (!fp->jited)
+                goto free_filter;
+
         set_memory_rw(addr, header->pages);
-        module_free(NULL, header);
-        kfree(fp);
-}
+        bpf_jit_binary_free(header);
 
-void bpf_jit_free(struct bpf_prog *fp)
-{
-        if (fp->jited) {
-                INIT_WORK(&fp->work, bpf_jit_free_deferred);
-                schedule_work(&fp->work);
-        } else {
-                kfree(fp);
-        }
+free_filter:
+        bpf_prog_unlock_free(fp);
 }
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 059a76c29739..7b20bccf3648 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -81,14 +81,14 @@ struct pci_ops pci_root_ops = {
  */
 DEFINE_RAW_SPINLOCK(pci_config_lock);
 
-static int can_skip_ioresource_align(const struct dmi_system_id *d)
+static int __init can_skip_ioresource_align(const struct dmi_system_id *d)
 {
         pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
         printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
         return 0;
 }
 
-static const struct dmi_system_id can_skip_pciprobe_dmi_table[] = {
+static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __initconst = {
 /*
  * Systems where PCI IO resource ISA alignment can be skipped
  * when the ISA enable bit in the bridge control is not set
@@ -186,7 +186,7 @@ void pcibios_remove_bus(struct pci_bus *bus)
  * on the kernel command line (which was parsed earlier).
  */
 
-static int set_bf_sort(const struct dmi_system_id *d)
+static int __init set_bf_sort(const struct dmi_system_id *d)
 {
         if (pci_bf_sort == pci_bf_sort_default) {
                 pci_bf_sort = pci_dmi_bf;
@@ -195,8 +195,8 @@ static int set_bf_sort(const struct dmi_system_id *d)
         return 0;
 }
 
-static void read_dmi_type_b1(const struct dmi_header *dm,
-                                       void *private_data)
+static void __init read_dmi_type_b1(const struct dmi_header *dm,
+                                    void *private_data)
 {
         u8 *d = (u8 *)dm + 4;
 
@@ -217,7 +217,7 @@ static void read_dmi_type_b1(const struct dmi_header *dm,
         }
 }
 
-static int find_sort_method(const struct dmi_system_id *d)
+static int __init find_sort_method(const struct dmi_system_id *d)
 {
         dmi_walk(read_dmi_type_b1, NULL);
 
@@ -232,7 +232,7 @@ static int find_sort_method(const struct dmi_system_id *d)
  * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
  */
 #ifdef __i386__
-static int assign_all_busses(const struct dmi_system_id *d)
+static int __init assign_all_busses(const struct dmi_system_id *d)
 {
         pci_probe |= PCI_ASSIGN_ALL_BUSSES;
         printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
@@ -241,7 +241,7 @@ static int assign_all_busses(const struct dmi_system_id *d)
 }
 #endif
 
-static int set_scan_all(const struct dmi_system_id *d)
+static int __init set_scan_all(const struct dmi_system_id *d)
 {
         printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
                d->ident);
@@ -249,7 +249,7 @@ static int set_scan_all(const struct dmi_system_id *d)
         return 0;
 }
 
-static const struct dmi_system_id pciprobe_dmi_table[] = {
+static const struct dmi_system_id pciprobe_dmi_table[] __initconst = {
 #ifdef __i386__
 /*
  * Laptops which need pci=assign-busses to see Cardbus cards
@@ -512,7 +512,7 @@ int __init pcibios_init(void)
         return 0;
 }
 
-char * __init pcibios_setup(char *str)
+char *__init pcibios_setup(char *str)
 {
         if (!strcmp(str, "off")) {
                 pci_probe = 0;
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index c61ea57d1ba1..9a2b7101ae8a 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -326,27 +326,6 @@ static void pci_fixup_video(struct pci_dev *pdev)
         struct pci_bus *bus;
         u16 config;
 
-        if (!vga_default_device()) {
-                resource_size_t start, end;
-                int i;
-
-                /* Does firmware framebuffer belong to us? */
-                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
-                        if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
-                                continue;
-
-                        start = pci_resource_start(pdev, i);
-                        end  = pci_resource_end(pdev, i);
-
-                        if (!start || !end)
-                                continue;
-
-                        if (screen_info.lfb_base >= start &&
-                            (screen_info.lfb_base + screen_info.lfb_size) < end)
-                                vga_set_default_device(pdev);
-                }
-        }
-
         /* Is VGA routed to us? */
         bus = pdev->bus;
         while (bus) {
@@ -371,8 +350,7 @@ static void pci_fixup_video(struct pci_dev *pdev)
                 pci_read_config_word(pdev, PCI_COMMAND, &config);
                 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
                         pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
-                        dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
-                        vga_set_default_device(pdev);
+                        dev_printk(KERN_DEBUG, &pdev->dev, "Video device with shadowed ROM\n");
                 }
         }
 }
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 3865116c51fb..b9958c364075 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -229,7 +229,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 
 static void intel_mid_pci_irq_disable(struct pci_dev *dev)
 {
-        if (!dev->dev.power.is_prepared && dev->irq > 0)
+        if (!mp_should_keep_irq(&dev->dev) && dev->irq > 0)
                 mp_unmap_irq(dev->irq);
 }
 
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index bc1a2c341891..eb500c2592ad 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -1256,7 +1256,7 @@ static int pirq_enable_irq(struct pci_dev *dev)
 
 static void pirq_disable_irq(struct pci_dev *dev)
 {
-        if (io_apic_assign_pci_irqs && !dev->dev.power.is_prepared &&
+        if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) &&
             dev->irq) {
                 mp_unmap_irq(dev->irq);
                 dev->irq = 0;
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 248642f4bab7..326198a4434e 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -31,7 +31,7 @@ static DEFINE_MUTEX(pci_mmcfg_lock);
 
 LIST_HEAD(pci_mmcfg_list);
 
-static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
+static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
 {
         if (cfg->res.parent)
                 release_resource(&cfg->res);
@@ -39,7 +39,7 @@ static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
         kfree(cfg);
 }
 
-static __init void free_all_mmcfg(void)
+static void __init free_all_mmcfg(void)
 {
         struct pci_mmcfg_region *cfg, *tmp;
 
@@ -93,7 +93,7 @@ static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
         return new;
 }
 
-static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
+static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
                                                         int end, u64 addr)
 {
         struct pci_mmcfg_region *new;
@@ -125,7 +125,7 @@ struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
         return NULL;
 }
 
-static const char __init *pci_mmcfg_e7520(void)
+static const char *__init pci_mmcfg_e7520(void)
 {
         u32 win;
         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
@@ -140,7 +140,7 @@ static const char __init *pci_mmcfg_e7520(void)
         return "Intel Corporation E7520 Memory Controller Hub";
 }
 
-static const char __init *pci_mmcfg_intel_945(void)
+static const char *__init pci_mmcfg_intel_945(void)
 {
         u32 pciexbar, mask = 0, len = 0;
 
@@ -184,7 +184,7 @@ static const char __init *pci_mmcfg_intel_945(void)
         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 }
 
-static const char __init *pci_mmcfg_amd_fam10h(void)
+static const char *__init pci_mmcfg_amd_fam10h(void)
 {
         u32 low, high, address;
         u64 base, msr;
@@ -235,21 +235,25 @@ static const char __init *pci_mmcfg_amd_fam10h(void)
 }
 
 static bool __initdata mcp55_checked;
-static const char __init *pci_mmcfg_nvidia_mcp55(void)
+static const char *__init pci_mmcfg_nvidia_mcp55(void)
 {
         int bus;
         int mcp55_mmconf_found = 0;
 
-        static const u32 extcfg_regnum          = 0x90;
-        static const u32 extcfg_regsize         = 4;
-        static const u32 extcfg_enable_mask     = 1<<31;
-        static const u32 extcfg_start_mask      = 0xff<<16;
-        static const int extcfg_start_shift     = 16;
-        static const u32 extcfg_size_mask       = 0x3<<28;
-        static const int extcfg_size_shift      = 28;
-        static const int extcfg_sizebus[]       = {0x100, 0x80, 0x40, 0x20};
-        static const u32 extcfg_base_mask[]     = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
-        static const int extcfg_base_lshift     = 25;
+        static const u32 extcfg_regnum __initconst      = 0x90;
+        static const u32 extcfg_regsize __initconst     = 4;
+        static const u32 extcfg_enable_mask __initconst = 1 << 31;
+        static const u32 extcfg_start_mask __initconst  = 0xff << 16;
+        static const int extcfg_start_shift __initconst = 16;
+        static const u32 extcfg_size_mask __initconst   = 0x3 << 28;
+        static const int extcfg_size_shift __initconst  = 28;
+        static const int extcfg_sizebus[] __initconst   = {
+                0x100, 0x80, 0x40, 0x20
+        };
+        static const u32 extcfg_base_mask[] __initconst = {
+                0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
+        };
+        static const int extcfg_base_lshift __initconst = 25;
 
         /*
          * do check if amd fam10h already took over
@@ -302,7 +306,7 @@ struct pci_mmcfg_hostbridge_probe {
         const char *(*probe)(void);
 };
 
-static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
+static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
           PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
diff --git a/arch/x86/pci/pcbios.c b/arch/x86/pci/pcbios.c
index c77b24a8b2da..9b83b9051ae7 100644
--- a/arch/x86/pci/pcbios.c
+++ b/arch/x86/pci/pcbios.c
@@ -79,13 +79,13 @@ union bios32 {
 static struct {
         unsigned long address;
         unsigned short segment;
-} bios32_indirect = { 0, __KERNEL_CS };
+} bios32_indirect __initdata = { 0, __KERNEL_CS };
 
 /*
  * Returns the entry point for the given service, NULL on error
  */
 
-static unsigned long bios32_service(unsigned long service)
+static unsigned long __init bios32_service(unsigned long service)
 {
         unsigned char return_code;      /* %al */
         unsigned long address;          /* %ebx */
@@ -124,7 +124,7 @@ static struct {
 
 static int pci_bios_present;
 
-static int check_pcibios(void)
+static int __init check_pcibios(void)
 {
         u32 signature, eax, ebx, ecx;
         u8 status, major_ver, minor_ver, hw_mech;
@@ -312,7 +312,7 @@ static const struct pci_raw_ops pci_bios_access = {
  * Try to find PCI BIOS.
  */
 
-static const struct pci_raw_ops *pci_find_bios(void)
+static const struct pci_raw_ops *__init pci_find_bios(void)
 {
         union bios32 *check;
         unsigned char sum;
diff --git a/arch/x86/power/hibernate_32.c b/arch/x86/power/hibernate_32.c
index 7d28c885d238..291226b952a9 100644
--- a/arch/x86/power/hibernate_32.c
+++ b/arch/x86/power/hibernate_32.c
@@ -13,13 +13,11 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/mmzone.h>
+#include <asm/sections.h>
 
 /* Defined in hibernate_asm_32.S */
 extern int restore_image(void);
 
-/* References to section boundaries */
-extern const void __nosave_begin, __nosave_end;
-
 /* Pointer to the temporary resume page tables */
 pgd_t *resume_pg_dir;
 
diff --git a/arch/x86/power/hibernate_64.c b/arch/x86/power/hibernate_64.c
index 35e2bb6c0f37..009947d419a6 100644
--- a/arch/x86/power/hibernate_64.c
+++ b/arch/x86/power/hibernate_64.c
@@ -17,11 +17,9 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/mtrr.h>
+#include <asm/sections.h>
 #include <asm/suspend.h>
 
-/* References to section boundaries */
-extern __visible const void __nosave_begin, __nosave_end;
-
 /* Defined in hibernate_asm_64.S */
 extern asmlinkage __visible int restore_image(void);
 
diff --git a/arch/x86/purgatory/Makefile b/arch/x86/purgatory/Makefile
index 7fde9ee438a4..899dd2454256 100644
--- a/arch/x86/purgatory/Makefile
+++ b/arch/x86/purgatory/Makefile
@@ -11,6 +11,7 @@ targets += purgatory.ro
 # sure how to relocate those. Like kexec-tools, use custom flags.
 
 KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes -fno-zero-initialized-in-bss -fno-builtin -ffreestanding -c -MD -Os -mcmodel=large
+KBUILD_CFLAGS += -m$(BITS)
 
 $(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE
                 $(call if_changed,ld)
@@ -24,7 +25,4 @@ $(obj)/kexec-purgatory.c: $(obj)/purgatory.ro FORCE
         $(call if_changed,bin2c)
 
 
-# No loaders for 32bits yet.
-ifeq ($(CONFIG_X86_64),y)
- obj-$(CONFIG_KEXEC)            += kexec-purgatory.o
-endif
+obj-$(CONFIG_KEXEC_FILE)        += kexec-purgatory.o
diff --git a/arch/x86/syscalls/syscall_32.tbl b/arch/x86/syscalls/syscall_32.tbl
index 028b78168d85..9fe1b5d002f0 100644
--- a/arch/x86/syscalls/syscall_32.tbl
+++ b/arch/x86/syscalls/syscall_32.tbl
@@ -363,3 +363,4 @@
 354     i386    seccomp                 sys_seccomp
 355     i386    getrandom               sys_getrandom
 356     i386    memfd_create            sys_memfd_create
+357     i386    bpf                     sys_bpf
diff --git a/arch/x86/syscalls/syscall_64.tbl b/arch/x86/syscalls/syscall_64.tbl
index 35dd922727b9..281150b539a2 100644
--- a/arch/x86/syscalls/syscall_64.tbl
+++ b/arch/x86/syscalls/syscall_64.tbl
@@ -327,6 +327,7 @@
 318     common  getrandom               sys_getrandom
 319     common  memfd_create            sys_memfd_create
 320     common  kexec_file_load         sys_kexec_file_load
+321     common  bpf                     sys_bpf
 
 #
 # x32-specific system call numbers start at 512 to avoid cache impact
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index e8a1201c3293..16fb0099b7f2 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -1866,12 +1866,11 @@ static void __init check_pt_base(unsigned long *pt_base, unsigned long *pt_end,
  *
  * We can construct this by grafting the Xen provided pagetable into
  * head_64.S's preconstructed pagetables.  We copy the Xen L2's into
- * level2_ident_pgt, level2_kernel_pgt and level2_fixmap_pgt.  This
- * means that only the kernel has a physical mapping to start with -
- * but that's enough to get __va working.  We need to fill in the rest
- * of the physical mapping once some sort of allocator has been set
- * up.
- * NOTE: for PVH, the page tables are native.
+ * level2_ident_pgt, and level2_kernel_pgt.  This means that only the
+ * kernel has a physical mapping to start with - but that's enough to
+ * get __va working.  We need to fill in the rest of the physical
+ * mapping once some sort of allocator has been set up.  NOTE: for
+ * PVH, the page tables are native.
  */
 void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
 {
@@ -1902,8 +1901,11 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
                 /* L3_i[0] -> level2_ident_pgt */
                 convert_pfn_mfn(level3_ident_pgt);
                 /* L3_k[510] -> level2_kernel_pgt
-                 * L3_i[511] -> level2_fixmap_pgt */
+                 * L3_k[511] -> level2_fixmap_pgt */
                 convert_pfn_mfn(level3_kernel_pgt);
+
+                /* L3_k[511][506] -> level1_fixmap_pgt */
+                convert_pfn_mfn(level2_fixmap_pgt);
         }
         /* We get [511][511] and have Xen's version of level2_kernel_pgt */
         l3 = m2v(pgd[pgd_index(__START_KERNEL_map)].pgd);
@@ -1913,21 +1915,15 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
         addr[1] = (unsigned long)l3;
         addr[2] = (unsigned long)l2;
         /* Graft it onto L4[272][0]. Note that we creating an aliasing problem:
-         * Both L4[272][0] and L4[511][511] have entries that point to the same
+         * Both L4[272][0] and L4[511][510] have entries that point to the same
          * L2 (PMD) tables. Meaning that if you modify it in __va space
          * it will be also modified in the __ka space! (But if you just
          * modify the PMD table to point to other PTE's or none, then you
          * are OK - which is what cleanup_highmap does) */
         copy_page(level2_ident_pgt, l2);
-        /* Graft it onto L4[511][511] */
+        /* Graft it onto L4[511][510] */
         copy_page(level2_kernel_pgt, l2);
 
-        /* Get [511][510] and graft that in level2_fixmap_pgt */
-        l3 = m2v(pgd[pgd_index(__START_KERNEL_map + PMD_SIZE)].pgd);
-        l2 = m2v(l3[pud_index(__START_KERNEL_map + PMD_SIZE)].pud);
-        copy_page(level2_fixmap_pgt, l2);
-        /* Note that we don't do anything with level1_fixmap_pgt which
-         * we don't need. */
         if (!xen_feature(XENFEAT_auto_translated_physmap)) {
                 /* Make pagetable pieces RO */
                 set_page_prot(init_level4_pgt, PAGE_KERNEL_RO);
@@ -1937,6 +1933,7 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
                 set_page_prot(level2_ident_pgt, PAGE_KERNEL_RO);
                 set_page_prot(level2_kernel_pgt, PAGE_KERNEL_RO);
                 set_page_prot(level2_fixmap_pgt, PAGE_KERNEL_RO);
+                set_page_prot(level1_fixmap_pgt, PAGE_KERNEL_RO);
 
                 /* Pin down new L4 */
                 pin_pagetable_pfn(MMUEXT_PIN_L4_TABLE,
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 3a617af60d46..49c6c3d94449 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -4,24 +4,23 @@ config ZONE_DMA
 config XTENSA
         def_bool y
         select ARCH_WANT_FRAME_POINTERS
-        select HAVE_IDE
-        select GENERIC_ATOMIC64
-        select GENERIC_CLOCKEVENTS
-        select VIRT_TO_BUS
-        select GENERIC_IRQ_SHOW
-        select GENERIC_SCHED_CLOCK
-        select MODULES_USE_ELF_RELA
-        select GENERIC_PCI_IOMAP
         select ARCH_WANT_IPC_PARSE_VERSION
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select BUILDTIME_EXTABLE_SORT
         select CLONE_BACKWARDS
-        select IRQ_DOMAIN
-        select HAVE_OPROFILE
+        select COMMON_CLK
+        select GENERIC_ATOMIC64
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_SHOW
+        select GENERIC_PCI_IOMAP
+        select GENERIC_SCHED_CLOCK
         select HAVE_FUNCTION_TRACER
         select HAVE_IRQ_TIME_ACCOUNTING
+        select HAVE_OPROFILE
         select HAVE_PERF_EVENTS
-        select COMMON_CLK
+        select IRQ_DOMAIN
+        select MODULES_USE_ELF_RELA
+        select VIRT_TO_BUS
         help
           Xtensa processors are 32-bit RISC machines designed by Tensilica
           primarily for embedded systems.  These processors are both
@@ -62,7 +61,9 @@ config TRACE_IRQFLAGS_SUPPORT
         def_bool y
 
 config MMU
-        def_bool n
+        bool
+        default n if !XTENSA_VARIANT_CUSTOM
+        default XTENSA_VARIANT_MMU if XTENSA_VARIANT_CUSTOM
 
 config VARIANT_IRQ_SWITCH
         def_bool n
@@ -102,8 +103,40 @@ config XTENSA_VARIANT_S6000
         select VARIANT_IRQ_SWITCH
         select ARCH_REQUIRE_GPIOLIB
         select XTENSA_CALIBRATE_CCOUNT
+
+config XTENSA_VARIANT_CUSTOM
+        bool "Custom Xtensa processor configuration"
+        select MAY_HAVE_SMP
+        select HAVE_XTENSA_GPIO32
+        help
+          Select this variant to use a custom Xtensa processor configuration.
+          You will be prompted for a processor variant CORENAME.
 endchoice
 
+config XTENSA_VARIANT_CUSTOM_NAME
+        string "Xtensa Processor Custom Core Variant Name"
+        depends on XTENSA_VARIANT_CUSTOM
+        help
+          Provide the name of a custom Xtensa processor variant.
+          This CORENAME selects arch/xtensa/variant/CORENAME.
+          Dont forget you have to select MMU if you have one.
+
+config XTENSA_VARIANT_NAME
+        string
+        default "dc232b"                        if XTENSA_VARIANT_DC232B
+        default "dc233c"                        if XTENSA_VARIANT_DC233C
+        default "fsf"                           if XTENSA_VARIANT_FSF
+        default "s6000"                         if XTENSA_VARIANT_S6000
+        default XTENSA_VARIANT_CUSTOM_NAME      if XTENSA_VARIANT_CUSTOM
+
+config XTENSA_VARIANT_MMU
+        bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
+        depends on XTENSA_VARIANT_CUSTOM
+        default y
+        help
+          Build a Conventional Kernel with full MMU support,
+          ie: it supports a TLB with auto-loading, page protection.
+
 config XTENSA_UNALIGNED_USER
         bool "Unaligned memory access in use space"
         help
@@ -156,13 +189,9 @@ config HOTPLUG_CPU
 
           Say N if you want to disable CPU hotplug.
 
-config MATH_EMULATION
-        bool "Math emulation"
-        help
-        Can we use information of configuration file?
-
 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
         bool "Initialize Xtensa MMU inside the Linux kernel code"
+        depends on MMU
         default y
         help
           Earlier version initialized the MMU in the exception vector
@@ -192,6 +221,7 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
 
 config HIGHMEM
         bool "High Memory Support"
+        depends on MMU
         help
           Linux can use the full amount of RAM in the system by
           default. However, the default MMUv2 setup only maps the
@@ -208,6 +238,32 @@ config HIGHMEM
 
           If unsure, say Y.
 
+config FAST_SYSCALL_XTENSA
+        bool "Enable fast atomic syscalls"
+        default n
+        help
+          fast_syscall_xtensa is a syscall that can make atomic operations
+          on UP kernel when processor has no s32c1i support.
+
+          This syscall is deprecated. It may have issues when called with
+          invalid arguments. It is provided only for backwards compatibility.
+          Only enable it if your userspace software requires it.
+
+          If unsure, say N.
+
+config FAST_SYSCALL_SPILL_REGISTERS
+        bool "Enable spill registers syscall"
+        default n
+        help
+          fast_syscall_spill_registers is a syscall that spills all active
+          register windows of a calling userspace task onto its stack.
+
+          This syscall is deprecated. It may have issues when called with
+          invalid arguments. It is provided only for backwards compatibility.
+          Only enable it if your userspace software requires it.
+
+          If unsure, say N.
+
 endmenu
 
 config XTENSA_CALIBRATE_CCOUNT
@@ -250,12 +306,14 @@ config XTENSA_PLATFORM_ISS
 
 config XTENSA_PLATFORM_XT2000
         bool "XT2000"
+        select HAVE_IDE
         help
           XT2000 is the name of Tensilica's feature-rich emulation platform.
           This hardware is capable of running a full Linux distribution.
 
 config XTENSA_PLATFORM_S6105
         bool "S6105"
+        select HAVE_IDE
         select SERIAL_CONSOLE
         select NO_IOPORT_MAP
 
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 81250ece3062..472533064b46 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -4,6 +4,7 @@
 # for more details.
 #
 # Copyright (C) 2001 - 2005  Tensilica Inc.
+# Copyright (C) 2014 Cadence Design Systems Inc.
 #
 # This file is included by the global makefile so that you can add your own
 # architecture-specific flags and dependencies. Remember to do have actions
@@ -13,11 +14,7 @@
 # Core configuration.
 # (Use VAR=<xtensa_config> to use another default compiler.)
 
-variant-$(CONFIG_XTENSA_VARIANT_FSF)            := fsf
-variant-$(CONFIG_XTENSA_VARIANT_DC232B)         := dc232b
-variant-$(CONFIG_XTENSA_VARIANT_DC233C)         := dc233c
-variant-$(CONFIG_XTENSA_VARIANT_S6000)          := s6000
-variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM)   := custom
+variant-y := $(patsubst "%",%,$(CONFIG_XTENSA_VARIANT_NAME))
 
 VARIANT = $(variant-y)
 export VARIANT
diff --git a/arch/xtensa/boot/dts/kc705.dts b/arch/xtensa/boot/dts/kc705.dts
index 742a347be67a..c4d17a34ab86 100644
--- a/arch/xtensa/boot/dts/kc705.dts
+++ b/arch/xtensa/boot/dts/kc705.dts
@@ -4,8 +4,11 @@
 
 / {
         compatible = "cdns,xtensa-kc705";
+        chosen {
+                bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000";
+        };
         memory@0 {
                 device_type = "memory";
-                reg = <0x00000000 0x08000000>;
+                reg = <0x00000000 0x38000000>;
         };
 };
diff --git a/arch/xtensa/configs/common_defconfig b/arch/xtensa/configs/common_defconfig
index f6000fe05119..721df1214bc3 100644
--- a/arch/xtensa/configs/common_defconfig
+++ b/arch/xtensa/configs/common_defconfig
@@ -66,7 +66,6 @@ CONFIG_XTENSA_ARCH_LINUX_BE=y
 CONFIG_MMU=y
 # CONFIG_XTENSA_UNALIGNED_USER is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_MATH_EMULATION is not set
 # CONFIG_HIGHMEM is not set
 
 #
diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig
index 1493c68352d1..b966baf82cae 100644
--- a/arch/xtensa/configs/iss_defconfig
+++ b/arch/xtensa/configs/iss_defconfig
@@ -146,7 +146,6 @@ CONFIG_XTENSA_VARIANT_FSF=y
 # CONFIG_XTENSA_VARIANT_S6000 is not set
 # CONFIG_XTENSA_UNALIGNED_USER is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_MATH_EMULATION is not set
 CONFIG_XTENSA_CALIBRATE_CCOUNT=y
 CONFIG_SERIAL_CONSOLE=y
 CONFIG_XTENSA_ISS_NETWORK=y
@@ -308,7 +307,7 @@ CONFIG_MISC_DEVICES=y
 # EEPROM support
 #
 # CONFIG_EEPROM_93CX6 is not set
-CONFIG_HAVE_IDE=y
+# CONFIG_HAVE_IDE is not set
 # CONFIG_IDE is not set
 
 #
diff --git a/arch/xtensa/configs/s6105_defconfig b/arch/xtensa/configs/s6105_defconfig
index 12a492ab6d17..9471265b8ca6 100644
--- a/arch/xtensa/configs/s6105_defconfig
+++ b/arch/xtensa/configs/s6105_defconfig
@@ -109,7 +109,6 @@ CONFIG_VARIANT_IRQ_SWITCH=y
 CONFIG_XTENSA_VARIANT_S6000=y
 # CONFIG_XTENSA_UNALIGNED_USER is not set
 CONFIG_PREEMPT=y
-# CONFIG_MATH_EMULATION is not set
 # CONFIG_HIGHMEM is not set
 CONFIG_XTENSA_CALIBRATE_CCOUNT=y
 CONFIG_SERIAL_CONSOLE=y
diff --git a/arch/xtensa/include/asm/Kbuild b/arch/xtensa/include/asm/Kbuild
index c3d20ba6eb86..105d38922c44 100644
--- a/arch/xtensa/include/asm/Kbuild
+++ b/arch/xtensa/include/asm/Kbuild
@@ -12,6 +12,7 @@ generic-y += hardirq.h
 generic-y += hash.h
 generic-y += ioctl.h
 generic-y += irq_regs.h
+generic-y += irq_work.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += kvm_para.h
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 555a98a18453..e72aaca7a77f 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -37,6 +37,7 @@
  * specials for cache aliasing:
  *
  * __flush_invalidate_dcache_page_alias(vaddr,paddr)
+ * __invalidate_dcache_page_alias(vaddr,paddr)
  * __invalidate_icache_page_alias(vaddr,paddr)
  */
 
@@ -62,6 +63,7 @@ extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
 
 #if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
 extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
+extern void __invalidate_dcache_page_alias(unsigned long, unsigned long);
 #else
 static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
                                                         unsigned long phys) { }
diff --git a/arch/xtensa/include/asm/fixmap.h b/arch/xtensa/include/asm/fixmap.h
index 9f6c33d0428a..62b507deea9d 100644
--- a/arch/xtensa/include/asm/fixmap.h
+++ b/arch/xtensa/include/asm/fixmap.h
@@ -23,8 +23,8 @@
  * Here we define all the compile-time 'special' virtual
  * addresses. The point is to have a constant address at
  * compile time, but to set the physical address only
- * in the boot process. We allocate these special  addresses
- * from the end of the consistent memory region backwards.
+ * in the boot process. We allocate these special addresses
+ * from the start of the consistent memory region upwards.
  * Also this lets us do fail-safe vmalloc(), we
  * can guarantee that these special addresses and
  * vmalloc()-ed addresses never overlap.
@@ -38,7 +38,8 @@ enum fixed_addresses {
 #ifdef CONFIG_HIGHMEM
         /* reserved pte's for temporary kernel mappings */
         FIX_KMAP_BEGIN,
-        FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1,
+        FIX_KMAP_END = FIX_KMAP_BEGIN +
+                (KM_TYPE_NR * NR_CPUS * DCACHE_N_COLORS) - 1,
 #endif
         __end_of_fixed_addresses
 };
@@ -47,7 +48,28 @@ enum fixed_addresses {
 #define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START   ((FIXADDR_TOP - FIXADDR_SIZE) & PMD_MASK)
 
-#include <asm-generic/fixmap.h>
+#define __fix_to_virt(x)        (FIXADDR_START + ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        (((x) - FIXADDR_START) >> PAGE_SHIFT)
+
+#ifndef __ASSEMBLY__
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without translation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static __always_inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        BUILD_BUG_ON(idx >= __end_of_fixed_addresses);
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+#endif
 
 #define kmap_get_fixmap_pte(vaddr) \
         pte_offset_kernel( \
diff --git a/arch/xtensa/include/asm/highmem.h b/arch/xtensa/include/asm/highmem.h
index 2653ef5d55f1..2c7901edffaf 100644
--- a/arch/xtensa/include/asm/highmem.h
+++ b/arch/xtensa/include/asm/highmem.h
@@ -12,19 +12,55 @@
 #ifndef _XTENSA_HIGHMEM_H
 #define _XTENSA_HIGHMEM_H
 
+#include <linux/wait.h>
 #include <asm/cacheflush.h>
 #include <asm/fixmap.h>
 #include <asm/kmap_types.h>
 #include <asm/pgtable.h>
 
-#define PKMAP_BASE              (FIXADDR_START - PMD_SIZE)
-#define LAST_PKMAP              PTRS_PER_PTE
+#define PKMAP_BASE              ((FIXADDR_START - \
+                                  (LAST_PKMAP + 1) * PAGE_SIZE) & PMD_MASK)
+#define LAST_PKMAP              (PTRS_PER_PTE * DCACHE_N_COLORS)
 #define LAST_PKMAP_MASK         (LAST_PKMAP - 1)
 #define PKMAP_NR(virt)          (((virt) - PKMAP_BASE) >> PAGE_SHIFT)
 #define PKMAP_ADDR(nr)          (PKMAP_BASE + ((nr) << PAGE_SHIFT))
 
 #define kmap_prot               PAGE_KERNEL
 
+#if DCACHE_WAY_SIZE > PAGE_SIZE
+#define get_pkmap_color get_pkmap_color
+static inline int get_pkmap_color(struct page *page)
+{
+        return DCACHE_ALIAS(page_to_phys(page));
+}
+
+extern unsigned int last_pkmap_nr_arr[];
+
+static inline unsigned int get_next_pkmap_nr(unsigned int color)
+{
+        last_pkmap_nr_arr[color] =
+                (last_pkmap_nr_arr[color] + DCACHE_N_COLORS) & LAST_PKMAP_MASK;
+        return last_pkmap_nr_arr[color] + color;
+}
+
+static inline int no_more_pkmaps(unsigned int pkmap_nr, unsigned int color)
+{
+        return pkmap_nr < DCACHE_N_COLORS;
+}
+
+static inline int get_pkmap_entries_count(unsigned int color)
+{
+        return LAST_PKMAP / DCACHE_N_COLORS;
+}
+
+extern wait_queue_head_t pkmap_map_wait_arr[];
+
+static inline wait_queue_head_t *get_pkmap_wait_queue_head(unsigned int color)
+{
+        return pkmap_map_wait_arr + color;
+}
+#endif
+
 extern pte_t *pkmap_page_table;
 
 void *kmap_high(struct page *page);
diff --git a/arch/xtensa/include/asm/page.h b/arch/xtensa/include/asm/page.h
index 47f582333f6b..abe24c6f8b2f 100644
--- a/arch/xtensa/include/asm/page.h
+++ b/arch/xtensa/include/asm/page.h
@@ -78,7 +78,9 @@
 # define DCACHE_ALIAS_EQ(a,b)   ((((a) ^ (b)) & DCACHE_ALIAS_MASK) == 0)
 #else
 # define DCACHE_ALIAS_ORDER     0
+# define DCACHE_ALIAS(a)        ((void)(a), 0)
 #endif
+#define DCACHE_N_COLORS         (1 << DCACHE_ALIAS_ORDER)
 
 #if ICACHE_WAY_SIZE > PAGE_SIZE
 # define ICACHE_ALIAS_ORDER     (ICACHE_WAY_SHIFT - PAGE_SHIFT)
@@ -134,6 +136,7 @@ static inline __attribute_const__ int get_order(unsigned long size)
 #endif
 
 struct page;
+struct vm_area_struct;
 extern void clear_page(void *page);
 extern void copy_page(void *to, void *from);
 
@@ -143,8 +146,15 @@ extern void copy_page(void *to, void *from);
  */
 
 #if DCACHE_WAY_SIZE > PAGE_SIZE
-extern void clear_user_page(void*, unsigned long, struct page*);
-extern void copy_user_page(void*, void*, unsigned long, struct page*);
+extern void clear_page_alias(void *vaddr, unsigned long paddr);
+extern void copy_page_alias(void *to, void *from,
+                            unsigned long to_paddr, unsigned long from_paddr);
+
+#define clear_user_highpage clear_user_highpage
+void clear_user_highpage(struct page *page, unsigned long vaddr);
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+void copy_user_highpage(struct page *to, struct page *from,
+                        unsigned long vaddr, struct vm_area_struct *vma);
 #else
 # define clear_user_page(page, vaddr, pg)       clear_page(page)
 # define copy_user_page(to, from, vaddr, pg)    copy_page(to, from)
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index 4b0ca35a93b1..b2173e5da601 100644
--- a/arch/xtensa/include/asm/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
@@ -67,7 +67,12 @@
 #define VMALLOC_START           0xC0000000
 #define VMALLOC_END             0xC7FEFFFF
 #define TLBTEMP_BASE_1          0xC7FF0000
-#define TLBTEMP_BASE_2          0xC7FF8000
+#define TLBTEMP_BASE_2          (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
+#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
+#define TLBTEMP_SIZE            (2 * DCACHE_WAY_SIZE)
+#else
+#define TLBTEMP_SIZE            ICACHE_WAY_SIZE
+#endif
 
 /*
  * For the Xtensa architecture, the PTE layout is as follows:
diff --git a/arch/xtensa/include/asm/uaccess.h b/arch/xtensa/include/asm/uaccess.h
index fd686dc45d1a..c7211e7e182d 100644
--- a/arch/xtensa/include/asm/uaccess.h
+++ b/arch/xtensa/include/asm/uaccess.h
@@ -52,7 +52,12 @@
  */
         .macro  get_fs  ad, sp
         GET_CURRENT(\ad,\sp)
+#if THREAD_CURRENT_DS > 1020
+        addi    \ad, \ad, TASK_THREAD
+        l32i    \ad, \ad, THREAD_CURRENT_DS - TASK_THREAD
+#else
         l32i    \ad, \ad, THREAD_CURRENT_DS
+#endif
         .endm
 
 /*
diff --git a/arch/xtensa/include/uapi/asm/ioctls.h b/arch/xtensa/include/uapi/asm/ioctls.h
index b4cb1100c0fb..518954e74e6d 100644
--- a/arch/xtensa/include/uapi/asm/ioctls.h
+++ b/arch/xtensa/include/uapi/asm/ioctls.h
@@ -28,17 +28,17 @@
 #define TCSETSW         0x5403
 #define TCSETSF         0x5404
 
-#define TCGETA          _IOR('t', 23, struct termio)
-#define TCSETA          _IOW('t', 24, struct termio)
-#define TCSETAW         _IOW('t', 25, struct termio)
-#define TCSETAF         _IOW('t', 28, struct termio)
+#define TCGETA          0x80127417      /* _IOR('t', 23, struct termio) */
+#define TCSETA          0x40127418      /* _IOW('t', 24, struct termio) */
+#define TCSETAW         0x40127419      /* _IOW('t', 25, struct termio) */
+#define TCSETAF         0x4012741C      /* _IOW('t', 28, struct termio) */
 
 #define TCSBRK          _IO('t', 29)
 #define TCXONC          _IO('t', 30)
 #define TCFLSH          _IO('t', 31)
 
-#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
-#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
+#define TIOCSWINSZ      0x40087467      /* _IOW('t', 103, struct winsize) */
+#define TIOCGWINSZ      0x80087468      /* _IOR('t', 104, struct winsize) */
 #define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
 #define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
 #define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
@@ -88,7 +88,6 @@
 #define TIOCSETD        _IOW('T', 35, int)
 #define TIOCGETD        _IOR('T', 36, int)
 #define TCSBRKP         _IOW('T', 37, int)   /* Needed for POSIX tcsendbreak()*/
-#define TIOCTTYGSTRUCT  _IOR('T', 38, struct tty_struct) /* For debugging only*/
 #define TIOCSBRK        _IO('T', 39)         /* BSD compatibility */
 #define TIOCCBRK        _IO('T', 40)         /* BSD compatibility */
 #define TIOCGSID        _IOR('T', 41, pid_t) /* Return the session ID of FD*/
@@ -96,6 +95,8 @@
 #define TCSETS2         _IOW('T', 43, struct termios2)
 #define TCSETSW2        _IOW('T', 44, struct termios2)
 #define TCSETSF2        _IOW('T', 45, struct termios2)
+#define TIOCGRS485      _IOR('T', 46, struct serial_rs485)
+#define TIOCSRS485      _IOWR('T', 47, struct serial_rs485)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
 #define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
@@ -114,8 +115,10 @@
 #define TIOCSERGETLSR   _IOR('T', 89, unsigned int) /* Get line status reg. */
   /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
 # define TIOCSER_TEMT    0x01                /* Transmitter physically empty */
-#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* Get multiport config  */
-#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* Set multiport config */
+#define TIOCSERGETMULTI 0x80a8545a /* Get multiport config  */
+                        /* _IOR('T', 90, struct serial_multiport_struct) */
+#define TIOCSERSETMULTI 0x40a8545b /* Set multiport config */
+                        /* _IOW('T', 91, struct serial_multiport_struct) */
 
 #define TIOCMIWAIT      _IO('T', 92) /* wait for a change on serial input line(s) */
 #define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
diff --git a/arch/xtensa/include/uapi/asm/unistd.h b/arch/xtensa/include/uapi/asm/unistd.h
index b9395529f02d..8883fc877c5c 100644
--- a/arch/xtensa/include/uapi/asm/unistd.h
+++ b/arch/xtensa/include/uapi/asm/unistd.h
@@ -739,7 +739,10 @@ __SYSCALL(334, sys_sched_setattr, 2)
 #define __NR_sched_getattr                      335
 __SYSCALL(335, sys_sched_getattr, 3)
 
-#define __NR_syscall_count                      336
+#define __NR_renameat2                          336
+__SYSCALL(336, sys_renameat2, 5)
+
+#define __NR_syscall_count                      337
 
 /*
  * sysxtensa syscall handler
diff --git a/arch/xtensa/kernel/align.S b/arch/xtensa/kernel/align.S
index d4cef6039a5c..890004af03a9 100644
--- a/arch/xtensa/kernel/align.S
+++ b/arch/xtensa/kernel/align.S
@@ -8,6 +8,7 @@
  * this archive for more details.
  *
  * Copyright (C) 2001 - 2005 Tensilica, Inc.
+ * Copyright (C) 2014 Cadence Design Systems Inc.
  *
  * Rewritten by Chris Zankel <chris@zankel.net>
  *
@@ -174,6 +175,10 @@ ENTRY(fast_unaligned)
         s32i    a0, a2, PT_AREG2
         s32i    a3, a2, PT_AREG3
 
+        rsr     a3, excsave1
+        movi    a4, fast_unaligned_fixup
+        s32i    a4, a3, EXC_TABLE_FIXUP
+
         /* Keep value of SAR in a0 */
 
         rsr     a0, sar
@@ -225,10 +230,6 @@ ENTRY(fast_unaligned)
         addx8   a5, a6, a5
         jx      a5                      # jump into table
 
-        /* Invalid instruction, CRITICAL! */
-.Linvalid_instruction_load:
-        j       .Linvalid_instruction
-
         /* Load: Load memory address. */
 
 .Lload: movi    a3, ~3
@@ -272,18 +273,6 @@ ENTRY(fast_unaligned)
         /* Set target register. */
 
 1:
-
-#if XCHAL_HAVE_LOOPS
-        rsr     a5, lend                # check if we reached LEND
-        bne     a7, a5, 1f
-        rsr     a5, lcount              # and LCOUNT != 0
-        beqz    a5, 1f
-        addi    a5, a5, -1              # decrement LCOUNT and set
-        rsr     a7, lbeg                # set PC to LBEGIN
-        wsr     a5, lcount
-#endif
-
-1:      wsr     a7, epc1                # skip load instruction
         extui   a4, a4, INSN_T, 4       # extract target register
         movi    a5, .Lload_table
         addx8   a4, a4, a5
@@ -326,6 +315,35 @@ ENTRY(fast_unaligned)
         mov     a3, a14         ;       _j 1f;  .align 8
         mov     a3, a15         ;       _j 1f;  .align 8
 
+        /* We cannot handle this exception. */
+
+        .extern _kernel_exception
+.Linvalid_instruction_load:
+.Linvalid_instruction_store:
+
+        movi    a4, 0
+        rsr     a3, excsave1
+        s32i    a4, a3, EXC_TABLE_FIXUP
+
+        /* Restore a4...a8 and SAR, set SP, and jump to default exception. */
+
+        l32i    a8, a2, PT_AREG8
+        l32i    a7, a2, PT_AREG7
+        l32i    a6, a2, PT_AREG6
+        l32i    a5, a2, PT_AREG5
+        l32i    a4, a2, PT_AREG4
+        wsr     a0, sar
+        mov     a1, a2
+
+        rsr     a0, ps
+        bbsi.l  a0, PS_UM_BIT, 2f     # jump if user mode
+
+        movi    a0, _kernel_exception
+        jx      a0
+
+2:      movi    a0, _user_exception
+        jx      a0
+
 1:      # a7: instruction pointer, a4: instruction, a3: value
 
         movi    a6, 0                   # mask: ffffffff:00000000
@@ -353,17 +371,6 @@ ENTRY(fast_unaligned)
         /* Get memory address */
 
 1:
-#if XCHAL_HAVE_LOOPS
-        rsr     a4, lend                # check if we reached LEND
-        bne     a7, a4, 1f
-        rsr     a4, lcount              # and LCOUNT != 0
-        beqz    a4, 1f
-        addi    a4, a4, -1              # decrement LCOUNT and set
-        rsr     a7, lbeg                # set PC to LBEGIN
-        wsr     a4, lcount
-#endif
-
-1:      wsr     a7, epc1                # skip store instruction
         movi    a4, ~3
         and     a4, a4, a8              # align memory address
 
@@ -375,25 +382,25 @@ ENTRY(fast_unaligned)
 #endif
 
         __ssa8r a8
-        __src_b a7, a5, a6              # lo-mask  F..F0..0 (BE) 0..0F..F (LE)
+        __src_b a8, a5, a6              # lo-mask  F..F0..0 (BE) 0..0F..F (LE)
         __src_b a6, a6, a5              # hi-mask  0..0F..F (BE) F..F0..0 (LE)
 #ifdef UNALIGNED_USER_EXCEPTION
         l32e    a5, a4, -8
 #else
         l32i    a5, a4, 0               # load lower address word
 #endif
-        and     a5, a5, a7              # mask
-        __sh    a7, a3                  # shift value
-        or      a5, a5, a7              # or with original value
+        and     a5, a5, a8              # mask
+        __sh    a8, a3                  # shift value
+        or      a5, a5, a8              # or with original value
 #ifdef UNALIGNED_USER_EXCEPTION
         s32e    a5, a4, -8
-        l32e    a7, a4, -4
+        l32e    a8, a4, -4
 #else
         s32i    a5, a4, 0               # store
-        l32i    a7, a4, 4               # same for upper address word
+        l32i    a8, a4, 4               # same for upper address word
 #endif
         __sl    a5, a3
-        and     a6, a7, a6
+        and     a6, a8, a6
         or      a6, a6, a5
 #ifdef UNALIGNED_USER_EXCEPTION
         s32e    a6, a4, -4
@@ -401,9 +408,27 @@ ENTRY(fast_unaligned)
         s32i    a6, a4, 4
 #endif
 
-        /* Done. restore stack and return */
-
 .Lexit:
+#if XCHAL_HAVE_LOOPS
+        rsr     a4, lend                # check if we reached LEND
+        bne     a7, a4, 1f
+        rsr     a4, lcount              # and LCOUNT != 0
+        beqz    a4, 1f
+        addi    a4, a4, -1              # decrement LCOUNT and set
+        rsr     a7, lbeg                # set PC to LBEGIN
+        wsr     a4, lcount
+#endif
+
+1:      wsr     a7, epc1                # skip emulated instruction
+
+        /* Update icount if we're single-stepping in userspace. */
+        rsr     a4, icountlevel
+        beqz    a4, 1f
+        bgeui   a4, LOCKLEVEL + 1, 1f
+        rsr     a4, icount
+        addi    a4, a4, 1
+        wsr     a4, icount
+1:
         movi    a4, 0
         rsr     a3, excsave1
         s32i    a4, a3, EXC_TABLE_FIXUP
@@ -424,31 +449,40 @@ ENTRY(fast_unaligned)
         l32i    a2, a2, PT_AREG2
         rfe
 
-        /* We cannot handle this exception. */
+ENDPROC(fast_unaligned)
 
-        .extern _kernel_exception
-.Linvalid_instruction_store:
-.Linvalid_instruction:
+ENTRY(fast_unaligned_fixup)
 
-        /* Restore a4...a8 and SAR, set SP, and jump to default exception. */
+        l32i    a2, a3, EXC_TABLE_DOUBLE_SAVE
+        wsr     a3, excsave1
 
         l32i    a8, a2, PT_AREG8
         l32i    a7, a2, PT_AREG7
         l32i    a6, a2, PT_AREG6
         l32i    a5, a2, PT_AREG5
         l32i    a4, a2, PT_AREG4
+        l32i    a0, a2, PT_AREG2
+        xsr     a0, depc                        # restore depc and a0
         wsr     a0, sar
-        mov     a1, a2
+
+        rsr     a0, exccause
+        s32i    a0, a2, PT_DEPC                 # mark as a regular exception
 
         rsr     a0, ps
-        bbsi.l  a2, PS_UM_BIT, 1f     # jump if user mode
+        bbsi.l  a0, PS_UM_BIT, 1f               # jump if user mode
 
-        movi    a0, _kernel_exception
+        rsr     a0, exccause
+        addx4   a0, a0, a3                      # find entry in table
+        l32i    a0, a0, EXC_TABLE_FAST_KERNEL   # load handler
+        l32i    a3, a2, PT_AREG3
         jx      a0
-
-1:      movi    a0, _user_exception
+1:
+        rsr     a0, exccause
+        addx4   a0, a0, a3                      # find entry in table
+        l32i    a0, a0, EXC_TABLE_FAST_USER     # load handler
+        l32i    a3, a2, PT_AREG3
         jx      a0
 
-ENDPROC(fast_unaligned)
+ENDPROC(fast_unaligned_fixup)
 
 #endif /* XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION */
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index ef7f4990722b..82bbfa5a05b3 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -986,6 +986,8 @@ ENDPROC(fast_syscall_unrecoverable)
  *              j done
  */
 
+#ifdef CONFIG_FAST_SYSCALL_XTENSA
+
 #define TRY                                                             \
         .section __ex_table, "a";                                       \
         .word   66f, 67f;                                               \
@@ -1001,9 +1003,8 @@ ENTRY(fast_syscall_xtensa)
         movi    a7, 4                   # sizeof(unsigned int)
         access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
 
-        addi    a6, a6, -1              # assuming SYS_XTENSA_ATOMIC_SET = 1
-        _bgeui  a6, SYS_XTENSA_COUNT - 1, .Lill
-        _bnei   a6, SYS_XTENSA_ATOMIC_CMP_SWP - 1, .Lnswp
+        _bgeui  a6, SYS_XTENSA_COUNT, .Lill
+        _bnei   a6, SYS_XTENSA_ATOMIC_CMP_SWP, .Lnswp
 
         /* Fall through for ATOMIC_CMP_SWP. */
 
@@ -1015,27 +1016,26 @@ TRY	s32i	a5, a3, 0		# different, modify value
         l32i    a7, a2, PT_AREG7        # restore a7
         l32i    a0, a2, PT_AREG0        # restore a0
         movi    a2, 1                   # and return 1
-        addi    a6, a6, 1               # restore a6 (really necessary?)
         rfe
 
 1:      l32i    a7, a2, PT_AREG7        # restore a7
         l32i    a0, a2, PT_AREG0        # restore a0
         movi    a2, 0                   # return 0 (note that we cannot set
-        addi    a6, a6, 1               # restore a6 (really necessary?)
         rfe
 
 .Lnswp: /* Atomic set, add, and exg_add. */
 
 TRY     l32i    a7, a3, 0               # orig
+        addi    a6, a6, -SYS_XTENSA_ATOMIC_SET
         add     a0, a4, a7              # + arg
         moveqz  a0, a4, a6              # set
+        addi    a6, a6, SYS_XTENSA_ATOMIC_SET
 TRY     s32i    a0, a3, 0               # write new value
 
         mov     a0, a2
         mov     a2, a7
         l32i    a7, a0, PT_AREG7        # restore a7
         l32i    a0, a0, PT_AREG0        # restore a0
-        addi    a6, a6, 1               # restore a6 (really necessary?)
         rfe
 
 CATCH
@@ -1044,13 +1044,25 @@ CATCH
         movi    a2, -EFAULT
         rfe
 
-.Lill:  l32i    a7, a2, PT_AREG0        # restore a7
+.Lill:  l32i    a7, a2, PT_AREG7        # restore a7
         l32i    a0, a2, PT_AREG0        # restore a0
         movi    a2, -EINVAL
         rfe
 
 ENDPROC(fast_syscall_xtensa)
 
+#else /* CONFIG_FAST_SYSCALL_XTENSA */
+
+ENTRY(fast_syscall_xtensa)
+
+        l32i    a0, a2, PT_AREG0        # restore a0
+        movi    a2, -ENOSYS
+        rfe
+
+ENDPROC(fast_syscall_xtensa)
+
+#endif /* CONFIG_FAST_SYSCALL_XTENSA */
+
 
 /* fast_syscall_spill_registers.
  *
@@ -1066,6 +1078,8 @@ ENDPROC(fast_syscall_xtensa)
  * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler.
  */
 
+#ifdef CONFIG_FAST_SYSCALL_SPILL_REGISTERS
+
 ENTRY(fast_syscall_spill_registers)
 
         /* Register a FIXUP handler (pass current wb as a parameter) */
@@ -1400,6 +1414,18 @@ ENTRY(fast_syscall_spill_registers_fixup_return)
 
 ENDPROC(fast_syscall_spill_registers_fixup_return)
 
+#else /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
+
+ENTRY(fast_syscall_spill_registers)
+
+        l32i    a0, a2, PT_AREG0        # restore a0
+        movi    a2, -ENOSYS
+        rfe
+
+ENDPROC(fast_syscall_spill_registers)
+
+#endif /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
+
 #ifdef CONFIG_MMU
 /*
  * We should never get here. Bail out!
@@ -1565,7 +1591,7 @@ ENTRY(fast_second_level_miss)
         rsr     a0, excvaddr
         bltu    a0, a3, 2f
 
-        addi    a1, a0, -(2 << (DCACHE_ALIAS_ORDER + PAGE_SHIFT))
+        addi    a1, a0, -TLBTEMP_SIZE
         bgeu    a1, a3, 2f
 
         /* Check if we have to restore an ITLB mapping. */
@@ -1820,7 +1846,6 @@ ENTRY(_switch_to)
 
         entry   a1, 16
 
-        mov     a10, a2                 # preserve 'prev' (a2)
         mov     a11, a3                 # and 'next' (a3)
 
         l32i    a4, a2, TASK_THREAD_INFO
@@ -1828,8 +1853,14 @@ ENTRY(_switch_to)
 
         save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
 
-        s32i    a0, a10, THREAD_RA      # save return address
-        s32i    a1, a10, THREAD_SP      # save stack pointer
+#if THREAD_RA > 1020 || THREAD_SP > 1020
+        addi    a10, a2, TASK_THREAD
+        s32i    a0, a10, THREAD_RA - TASK_THREAD        # save return address
+        s32i    a1, a10, THREAD_SP - TASK_THREAD        # save stack pointer
+#else
+        s32i    a0, a2, THREAD_RA       # save return address
+        s32i    a1, a2, THREAD_SP       # save stack pointer
+#endif
 
         /* Disable ints while we manipulate the stack pointer. */
 
@@ -1870,7 +1901,6 @@ ENTRY(_switch_to)
         load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
 
         wsr     a14, ps
-        mov     a2, a10                 # return 'prev'
         rsync
 
         retw
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index 2d9cc6dbfd78..e8b76b8e4b29 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -49,9 +49,8 @@ dma_alloc_coherent(struct device *dev,size_t size,dma_addr_t *handle,gfp_t flag)
 
         /* We currently don't support coherent memory outside KSEG */
 
-        if (ret < XCHAL_KSEG_CACHED_VADDR
-            || ret >= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE)
-                BUG();
+        BUG_ON(ret < XCHAL_KSEG_CACHED_VADDR ||
+               ret > XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE - 1);
 
 
         if (ret != 0) {
@@ -68,10 +67,11 @@ EXPORT_SYMBOL(dma_alloc_coherent);
 void dma_free_coherent(struct device *hwdev, size_t size,
                          void *vaddr, dma_addr_t dma_handle)
 {
-        long addr=(long)vaddr+XCHAL_KSEG_CACHED_VADDR-XCHAL_KSEG_BYPASS_VADDR;
+        unsigned long addr = (unsigned long)vaddr +
+                XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR;
 
-        if (addr < 0 || addr >= XCHAL_KSEG_SIZE)
-                BUG();
+        BUG_ON(addr < XCHAL_KSEG_CACHED_VADDR ||
+               addr > XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE - 1);
 
         free_pages(addr, get_order(size));
 }
diff --git a/arch/xtensa/kernel/smp.c b/arch/xtensa/kernel/smp.c
index 40b5a3771fb0..4d02e38514f5 100644
--- a/arch/xtensa/kernel/smp.c
+++ b/arch/xtensa/kernel/smp.c
@@ -571,6 +571,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
         };
         on_each_cpu(ipi_flush_icache_range, &fd, 1);
 }
+EXPORT_SYMBOL(flush_icache_range);
 
 /* ------------------------------------------------------------------------- */
 
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index eebbfd8c26fc..9d2f45f010ef 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -101,9 +101,8 @@ static dispatch_init_table_t __initdata dispatch_init_table[] = {
 #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
 #ifdef CONFIG_XTENSA_UNALIGNED_USER
 { EXCCAUSE_UNALIGNED,           USER,      fast_unaligned },
-#else
-{ EXCCAUSE_UNALIGNED,           0,         do_unaligned_user },
 #endif
+{ EXCCAUSE_UNALIGNED,           0,         do_unaligned_user },
 { EXCCAUSE_UNALIGNED,           KRNL,      fast_unaligned },
 #endif
 #ifdef CONFIG_MMU
@@ -264,7 +263,6 @@ do_illegal_instruction(struct pt_regs *regs)
  */
 
 #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
-#ifndef CONFIG_XTENSA_UNALIGNED_USER
 void
 do_unaligned_user (struct pt_regs *regs)
 {
@@ -286,7 +284,6 @@ do_unaligned_user (struct pt_regs *regs)
 
 }
 #endif
-#endif
 
 void
 do_debug(struct pt_regs *regs)
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S
index 8453e6e39895..1b397a902292 100644
--- a/arch/xtensa/kernel/vectors.S
+++ b/arch/xtensa/kernel/vectors.S
@@ -454,8 +454,14 @@ _DoubleExceptionVector_WindowOverflow:
         s32i    a0, a2, PT_DEPC
 
 _DoubleExceptionVector_handle_exception:
+        addi    a0, a0, -EXCCAUSE_UNALIGNED
+        beqz    a0, 2f
         addx4   a0, a0, a3
-        l32i    a0, a0, EXC_TABLE_FAST_USER
+        l32i    a0, a0, EXC_TABLE_FAST_USER + 4 * EXCCAUSE_UNALIGNED
+        xsr     a3, excsave1
+        jx      a0
+2:
+        movi    a0, user_exception
         xsr     a3, excsave1
         jx      a0
 
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index d16db6df86f8..fc1bc2ba8d5d 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -269,13 +269,13 @@ SECTIONS
                   .UserExceptionVector.literal)
   SECTION_VECTOR (_DoubleExceptionVector_literal,
                   .DoubleExceptionVector.literal,
-                  DOUBLEEXC_VECTOR_VADDR - 40,
+                  DOUBLEEXC_VECTOR_VADDR - 48,
                   SIZEOF(.UserExceptionVector.text),
                   .UserExceptionVector.text)
   SECTION_VECTOR (_DoubleExceptionVector_text,
                   .DoubleExceptionVector.text,
                   DOUBLEEXC_VECTOR_VADDR,
-                  40,
+                  48,
                   .DoubleExceptionVector.literal)
 
   . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3;
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index 63cbb867dadd..d75aa1476da7 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -59,9 +59,68 @@
  *
  */
 
-#if (DCACHE_WAY_SIZE > PAGE_SIZE) && defined(CONFIG_HIGHMEM)
-#error "HIGHMEM is not supported on cores with aliasing cache."
-#endif
+#if (DCACHE_WAY_SIZE > PAGE_SIZE)
+static inline void kmap_invalidate_coherent(struct page *page,
+                                            unsigned long vaddr)
+{
+        if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
+                unsigned long kvaddr;
+
+                if (!PageHighMem(page)) {
+                        kvaddr = (unsigned long)page_to_virt(page);
+
+                        __invalidate_dcache_page(kvaddr);
+                } else {
+                        kvaddr = TLBTEMP_BASE_1 +
+                                (page_to_phys(page) & DCACHE_ALIAS_MASK);
+
+                        __invalidate_dcache_page_alias(kvaddr,
+                                                       page_to_phys(page));
+                }
+        }
+}
+
+static inline void *coherent_kvaddr(struct page *page, unsigned long base,
+                                    unsigned long vaddr, unsigned long *paddr)
+{
+        if (PageHighMem(page) || !DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
+                *paddr = page_to_phys(page);
+                return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
+        } else {
+                *paddr = 0;
+                return page_to_virt(page);
+        }
+}
+
+void clear_user_highpage(struct page *page, unsigned long vaddr)
+{
+        unsigned long paddr;
+        void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
+
+        pagefault_disable();
+        kmap_invalidate_coherent(page, vaddr);
+        set_bit(PG_arch_1, &page->flags);
+        clear_page_alias(kvaddr, paddr);
+        pagefault_enable();
+}
+
+void copy_user_highpage(struct page *dst, struct page *src,
+                        unsigned long vaddr, struct vm_area_struct *vma)
+{
+        unsigned long dst_paddr, src_paddr;
+        void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
+                                          &dst_paddr);
+        void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
+                                          &src_paddr);
+
+        pagefault_disable();
+        kmap_invalidate_coherent(dst, vaddr);
+        set_bit(PG_arch_1, &dst->flags);
+        copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
+        pagefault_enable();
+}
+
+#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
 
 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 
@@ -103,7 +162,8 @@ void flush_dcache_page(struct page *page)
                 if (!alias && !mapping)
                         return;
 
-                __flush_invalidate_dcache_page((long)page_address(page));
+                virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
+                __flush_invalidate_dcache_page_alias(virt, phys);
 
                 virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
 
@@ -168,13 +228,12 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 
         if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
-
-                unsigned long paddr = (unsigned long) page_address(page);
                 unsigned long phys = page_to_phys(page);
-                unsigned long tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
-
-                __flush_invalidate_dcache_page(paddr);
+                unsigned long tmp;
 
+                tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
+                __flush_invalidate_dcache_page_alias(tmp, phys);
+                tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
                 __flush_invalidate_dcache_page_alias(tmp, phys);
                 __invalidate_icache_page_alias(tmp, phys);
 
diff --git a/arch/xtensa/mm/highmem.c b/arch/xtensa/mm/highmem.c
index 17a8c0d6fd17..8cfb71ec0937 100644
--- a/arch/xtensa/mm/highmem.c
+++ b/arch/xtensa/mm/highmem.c
@@ -14,23 +14,45 @@
 
 static pte_t *kmap_pte;
 
+#if DCACHE_WAY_SIZE > PAGE_SIZE
+unsigned int last_pkmap_nr_arr[DCACHE_N_COLORS];
+wait_queue_head_t pkmap_map_wait_arr[DCACHE_N_COLORS];
+
+static void __init kmap_waitqueues_init(void)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(pkmap_map_wait_arr); ++i)
+                init_waitqueue_head(pkmap_map_wait_arr + i);
+}
+#else
+static inline void kmap_waitqueues_init(void)
+{
+}
+#endif
+
+static inline enum fixed_addresses kmap_idx(int type, unsigned long color)
+{
+        return (type + KM_TYPE_NR * smp_processor_id()) * DCACHE_N_COLORS +
+                color;
+}
+
 void *kmap_atomic(struct page *page)
 {
         enum fixed_addresses idx;
         unsigned long vaddr;
-        int type;
 
         pagefault_disable();
         if (!PageHighMem(page))
                 return page_address(page);
 
-        type = kmap_atomic_idx_push();
-        idx = type + KM_TYPE_NR * smp_processor_id();
+        idx = kmap_idx(kmap_atomic_idx_push(),
+                       DCACHE_ALIAS(page_to_phys(page)));
         vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
 #ifdef CONFIG_DEBUG_HIGHMEM
-        BUG_ON(!pte_none(*(kmap_pte - idx)));
+        BUG_ON(!pte_none(*(kmap_pte + idx)));
 #endif
-        set_pte(kmap_pte - idx, mk_pte(page, PAGE_KERNEL_EXEC));
+        set_pte(kmap_pte + idx, mk_pte(page, PAGE_KERNEL_EXEC));
 
         return (void *)vaddr;
 }
@@ -38,12 +60,10 @@ EXPORT_SYMBOL(kmap_atomic);
 
 void __kunmap_atomic(void *kvaddr)
 {
-        int idx, type;
-
         if (kvaddr >= (void *)FIXADDR_START &&
             kvaddr < (void *)FIXADDR_TOP) {
-                type = kmap_atomic_idx();
-                idx = type + KM_TYPE_NR * smp_processor_id();
+                int idx = kmap_idx(kmap_atomic_idx(),
+                                   DCACHE_ALIAS((unsigned long)kvaddr));
 
                 /*
                  * Force other mappings to Oops if they'll try to access this
@@ -51,7 +71,7 @@ void __kunmap_atomic(void *kvaddr)
                  * is a bad idea also, in case the page changes cacheability
                  * attributes or becomes a protected page in a hypervisor.
                  */
-                pte_clear(&init_mm, kvaddr, kmap_pte - idx);
+                pte_clear(&init_mm, kvaddr, kmap_pte + idx);
                 local_flush_tlb_kernel_range((unsigned long)kvaddr,
                                              (unsigned long)kvaddr + PAGE_SIZE);
 
@@ -69,4 +89,5 @@ void __init kmap_init(void)
         /* cache the first kmap pte */
         kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN);
         kmap_pte = kmap_get_fixmap_pte(kmap_vstart);
+        kmap_waitqueues_init();
 }
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index 1f68558dbcc2..11a01c3e9cea 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -110,41 +110,24 @@ ENTRY(__tlbtemp_mapping_start)
 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
 
 /*
- * clear_user_page (void *addr, unsigned long vaddr, struct page *page)
- *                     a2              a3                 a4
+ * clear_page_alias(void *addr, unsigned long paddr)
+ *                     a2              a3
  */
 
-ENTRY(clear_user_page)
+ENTRY(clear_page_alias)
 
         entry   a1, 32
 
-        /* Mark page dirty and determine alias. */
+        /* Skip setting up a temporary DTLB if not aliased low page. */
 
-        movi    a7, (1 << PG_ARCH_1)
-        l32i    a5, a4, PAGE_FLAGS
-        xor     a6, a2, a3
-        extui   a3, a3, PAGE_SHIFT, DCACHE_ALIAS_ORDER
-        extui   a6, a6, PAGE_SHIFT, DCACHE_ALIAS_ORDER
-        or      a5, a5, a7
-        slli    a3, a3, PAGE_SHIFT
-        s32i    a5, a4, PAGE_FLAGS
+        movi    a5, PAGE_OFFSET
+        movi    a6, 0
+        beqz    a3, 1f
 
-        /* Skip setting up a temporary DTLB if not aliased. */
-
-        beqz    a6, 1f
-
-        /* Invalidate kernel page. */
-
-        mov     a10, a2
-        call8   __invalidate_dcache_page
-
-        /* Setup a temporary DTLB with the color of the VPN */
-
-        movi    a4, ((PAGE_KERNEL | _PAGE_HW_WRITE) - PAGE_OFFSET) & 0xffffffff
-        movi    a5, TLBTEMP_BASE_1                      # virt
-        add     a6, a2, a4                              # ppn
-        add     a2, a5, a3                              # add 'color'
+        /* Setup a temporary DTLB for the addr. */
 
+        addi    a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
+        mov     a4, a2
         wdtlb   a6, a2
         dsync
 
@@ -165,62 +148,43 @@ ENTRY(clear_user_page)
 
         /* We need to invalidate the temporary idtlb entry, if any. */
 
-1:      addi    a2, a2, -PAGE_SIZE
-        idtlb   a2
+1:      idtlb   a4
         dsync
 
         retw
 
-ENDPROC(clear_user_page)
+ENDPROC(clear_page_alias)
 
 /*
- * copy_page_user (void *to, void *from, unsigned long vaddr, struct page *page)
- *                    a2          a3            a4                  a5
+ * copy_page_alias(void *to, void *from,
+ *                      a2        a3
+ *                 unsigned long to_paddr, unsigned long from_paddr)
+ *                               a4                      a5
  */
 
-ENTRY(copy_user_page)
+ENTRY(copy_page_alias)
 
         entry   a1, 32
 
-        /* Mark page dirty and determine alias for destination. */
-
-        movi    a8, (1 << PG_ARCH_1)
-        l32i    a9, a5, PAGE_FLAGS
-        xor     a6, a2, a4
-        xor     a7, a3, a4
-        extui   a4, a4, PAGE_SHIFT, DCACHE_ALIAS_ORDER
-        extui   a6, a6, PAGE_SHIFT, DCACHE_ALIAS_ORDER
-        extui   a7, a7, PAGE_SHIFT, DCACHE_ALIAS_ORDER
-        or      a9, a9, a8
-        slli    a4, a4, PAGE_SHIFT
-        s32i    a9, a5, PAGE_FLAGS
-        movi    a5, ((PAGE_KERNEL | _PAGE_HW_WRITE) - PAGE_OFFSET) & 0xffffffff
-
-        beqz    a6, 1f
-
-        /* Invalidate dcache */
-
-        mov     a10, a2
-        call8   __invalidate_dcache_page
+        /* Skip setting up a temporary DTLB for destination if not aliased. */
 
-        /* Setup a temporary DTLB with a matching color. */
+        movi    a6, 0
+        movi    a7, 0
+        beqz    a4, 1f
 
-        movi    a8, TLBTEMP_BASE_1                      # base
-        add     a6, a2, a5                              # ppn
-        add     a2, a8, a4                              # add 'color'
+        /* Setup a temporary DTLB for destination. */
 
+        addi    a6, a4, (PAGE_KERNEL | _PAGE_HW_WRITE)
         wdtlb   a6, a2
         dsync
 
-        /* Skip setting up a temporary DTLB for destination if not aliased. */
+        /* Skip setting up a temporary DTLB for source if not aliased. */
 
-1:      beqz    a7, 1f
+1:      beqz    a5, 1f
 
-        /* Setup a temporary DTLB with a matching color. */
+        /* Setup a temporary DTLB for source. */
 
-        movi    a8, TLBTEMP_BASE_2                      # base
-        add     a7, a3, a5                              # ppn
-        add     a3, a8, a4
+        addi    a7, a5, PAGE_KERNEL
         addi    a8, a3, 1                               # way1
 
         wdtlb   a7, a8
@@ -271,7 +235,7 @@ ENTRY(copy_user_page)
 
         retw
 
-ENDPROC(copy_user_page)
+ENDPROC(copy_page_alias)
 
 #endif
 
@@ -300,6 +264,30 @@ ENTRY(__flush_invalidate_dcache_page_alias)
         retw
 
 ENDPROC(__flush_invalidate_dcache_page_alias)
+
+/*
+ * void __invalidate_dcache_page_alias (addr, phys)
+ *                                       a2    a3
+ */
+
+ENTRY(__invalidate_dcache_page_alias)
+
+        entry   sp, 16
+
+        movi    a7, 0                   # required for exception handler
+        addi    a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
+        mov     a4, a2
+        wdtlb   a6, a2
+        dsync
+
+        ___invalidate_dcache_page a2 a3
+
+        idtlb   a4
+        dsync
+
+        retw
+
+ENDPROC(__invalidate_dcache_page_alias)
 #endif
 
 ENTRY(__tlbtemp_mapping_itlb)
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
index 3429b483d9f8..abe4513eb0dd 100644
--- a/arch/xtensa/mm/mmu.c
+++ b/arch/xtensa/mm/mmu.c
@@ -18,32 +18,38 @@
 #include <asm/io.h>
 
 #if defined(CONFIG_HIGHMEM)
-static void * __init init_pmd(unsigned long vaddr)
+static void * __init init_pmd(unsigned long vaddr, unsigned long n_pages)
 {
         pgd_t *pgd = pgd_offset_k(vaddr);
         pmd_t *pmd = pmd_offset(pgd, vaddr);
+        pte_t *pte;
+        unsigned long i;
 
-        if (pmd_none(*pmd)) {
-                unsigned i;
-                pte_t *pte = alloc_bootmem_low_pages(PAGE_SIZE);
+        n_pages = ALIGN(n_pages, PTRS_PER_PTE);
 
-                for (i = 0; i < 1024; i++)
-                        pte_clear(NULL, 0, pte + i);
+        pr_debug("%s: vaddr: 0x%08lx, n_pages: %ld\n",
+                 __func__, vaddr, n_pages);
 
-                set_pmd(pmd, __pmd(((unsigned long)pte) & PAGE_MASK));
-                BUG_ON(pte != pte_offset_kernel(pmd, 0));
-                pr_debug("%s: vaddr: 0x%08lx, pmd: 0x%p, pte: 0x%p\n",
-                         __func__, vaddr, pmd, pte);
-                return pte;
-        } else {
-                return pte_offset_kernel(pmd, 0);
+        pte = alloc_bootmem_low_pages(n_pages * sizeof(pte_t));
+
+        for (i = 0; i < n_pages; ++i)
+                pte_clear(NULL, 0, pte + i);
+
+        for (i = 0; i < n_pages; i += PTRS_PER_PTE, ++pmd) {
+                pte_t *cur_pte = pte + i;
+
+                BUG_ON(!pmd_none(*pmd));
+                set_pmd(pmd, __pmd(((unsigned long)cur_pte) & PAGE_MASK));
+                BUG_ON(cur_pte != pte_offset_kernel(pmd, 0));
+                pr_debug("%s: pmd: 0x%p, pte: 0x%p\n",
+                         __func__, pmd, cur_pte);
         }
+        return pte;
 }
 
 static void __init fixedrange_init(void)
 {
-        BUILD_BUG_ON(FIXADDR_SIZE > PMD_SIZE);
-        init_pmd(__fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK);
+        init_pmd(__fix_to_virt(0), __end_of_fixed_addresses);
 }
 #endif
 
@@ -52,7 +58,7 @@ void __init paging_init(void)
         memset(swapper_pg_dir, 0, PAGE_SIZE);
 #ifdef CONFIG_HIGHMEM
         fixedrange_init();
-        pkmap_page_table = init_pmd(PKMAP_BASE);
+        pkmap_page_table = init_pmd(PKMAP_BASE, LAST_PKMAP);
         kmap_init();
 #endif
 }