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-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts29
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts77
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts74
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts65
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts45
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi71
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi127
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/Makefile.boot2
-rw-r--r--arch/arm/mach-tegra/board-dt.c49
-rw-r--r--arch/arm/mach-tegra/irq.c10
11 files changed, 495 insertions, 56 deletions
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 0e225b86b652..80afa1b70b80 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -1,16 +1,11 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
5 4
6/ { 5/ {
7 model = "NVIDIA Tegra2 Harmony evaluation board"; 6 model = "NVIDIA Tegra2 Harmony evaluation board";
8 compatible = "nvidia,harmony", "nvidia,tegra20"; 7 compatible = "nvidia,harmony", "nvidia,tegra20";
9 8
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
12 };
13
14 memory@0 { 9 memory@0 {
15 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
16 }; 11 };
@@ -52,16 +47,40 @@
52 ext-mic-en-gpios = <&gpio 185 0>; 47 ext-mic-en-gpios = <&gpio 185 0>;
53 }; 48 };
54 49
50 serial@70006000 {
51 status = "disable";
52 };
53
54 serial@70006040 {
55 status = "disable";
56 };
57
58 serial@70006200 {
59 status = "disable";
60 };
61
55 serial@70006300 { 62 serial@70006300 {
56 clock-frequency = < 216000000 >; 63 clock-frequency = < 216000000 >;
57 }; 64 };
58 65
66 serial@70006400 {
67 status = "disable";
68 };
69
70 sdhci@c8000000 {
71 status = "disable";
72 };
73
59 sdhci@c8000200 { 74 sdhci@c8000200 {
60 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 75 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
61 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 76 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
62 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 77 power-gpios = <&gpio 155 0>; /* gpio PT3 */
63 }; 78 };
64 79
80 sdhci@c8000400 {
81 status = "disable";
82 };
83
65 sdhci@c8000600 { 84 sdhci@c8000600 {
66 cd-gpios = <&gpio 58 0>; /* gpio PH2 */ 85 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
67 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 86 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
new file mode 100644
index 000000000000..1a1d7023b69b
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -0,0 +1,77 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
8
9 memory@0 {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 i2c@7000c000 {
14 clock-frequency = <400000>;
15 };
16
17 i2c@7000c400 {
18 clock-frequency = <400000>;
19 };
20
21 i2c@7000c500 {
22 status = "disable";
23 };
24
25 nvec@7000c500 {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 compatible = "nvidia,nvec";
29 reg = <0x7000C500 0x100>;
30 interrupts = <0 92 0x04>;
31 clock-frequency = <80000>;
32 request-gpios = <&gpio 170 0>;
33 slave-addr = <138>;
34 };
35
36 i2c@7000d000 {
37 clock-frequency = <400000>;
38 };
39
40 serial@70006000 {
41 clock-frequency = <216000000>;
42 };
43
44 serial@70006040 {
45 status = "disable";
46 };
47
48 serial@70006200 {
49 status = "disable";
50 };
51
52 serial@70006300 {
53 clock-frequency = <216000000>;
54 };
55
56 serial@70006400 {
57 status = "disable";
58 };
59
60 sdhci@c8000000 {
61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
63 power-gpios = <&gpio 155 0>; /* gpio PT3 */
64 };
65
66 sdhci@c8000200 {
67 status = "disable";
68 };
69
70 sdhci@c8000400 {
71 status = "disable";
72 };
73
74 sdhci@c8000600 {
75 support-8bit;
76 };
77};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index a72299b8e668..b55a02e34ba7 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -1,25 +1,65 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
5 4
6/ { 5/ {
7 model = "NVIDIA Seaboard"; 6 model = "NVIDIA Seaboard";
8 compatible = "nvidia,seaboard", "nvidia,tegra20"; 7 compatible = "nvidia,seaboard", "nvidia,tegra20";
9 8
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
12 };
13
14 memory { 9 memory {
15 device_type = "memory"; 10 device_type = "memory";
16 reg = < 0x00000000 0x40000000 >; 11 reg = < 0x00000000 0x40000000 >;
17 }; 12 };
18 13
14 i2c@7000c000 {
15 clock-frequency = <400000>;
16 };
17
18 i2c@7000c400 {
19 clock-frequency = <400000>;
20 };
21
22 i2c@7000c500 {
23 clock-frequency = <400000>;
24 };
25
26 i2c@7000d000 {
27 clock-frequency = <400000>;
28
29 adt7461@4c {
30 compatible = "adt7461";
31 reg = <0x4c>;
32 };
33 };
34
35 serial@70006000 {
36 status = "disable";
37 };
38
39 serial@70006040 {
40 status = "disable";
41 };
42
43 serial@70006200 {
44 status = "disable";
45 };
46
19 serial@70006300 { 47 serial@70006300 {
20 clock-frequency = < 216000000 >; 48 clock-frequency = < 216000000 >;
21 }; 49 };
22 50
51 serial@70006400 {
52 status = "disable";
53 };
54
55 sdhci@c8000000 {
56 status = "disable";
57 };
58
59 sdhci@c8000200 {
60 status = "disable";
61 };
62
23 sdhci@c8000400 { 63 sdhci@c8000400 {
24 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 64 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
25 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 65 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
@@ -29,4 +69,28 @@
29 sdhci@c8000600 { 69 sdhci@c8000600 {
30 support-8bit; 70 support-8bit;
31 }; 71 };
72
73 usb@c5000000 {
74 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
75 };
76
77 gpio-keys {
78 compatible = "gpio-keys";
79
80 power {
81 label = "Power";
82 gpios = <&gpio 170 1>; /* gpio PV2, active low */
83 linux,code = <116>; /* KEY_POWER */
84 gpio-key,wakeup;
85 };
86
87 lid {
88 label = "Lid";
89 gpios = <&gpio 23 0>; /* gpio PC7 */
90 linux,input-type = <5>; /* EV_SW */
91 linux,code = <0>; /* SW_LID */
92 debounce-interval = <1>;
93 gpio-key,wakeup;
94 };
95 };
32}; 96};
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
new file mode 100644
index 000000000000..3b3ee7db99f3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -0,0 +1,65 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20";
8
9 memory@0 {
10 reg = < 0x00000000 0x40000000 >;
11 };
12
13 i2c@7000c000 {
14 clock-frequency = <400000>;
15 };
16
17 i2c@7000c400 {
18 clock-frequency = <400000>;
19 };
20
21 i2c@7000c500 {
22 clock-frequency = <400000>;
23 };
24
25 i2c@7000d000 {
26 status = "disable";
27 };
28
29 serial@70006000 {
30 clock-frequency = < 216000000 >;
31 };
32
33 serial@70006040 {
34 status = "disable";
35 };
36
37 serial@70006200 {
38 status = "disable";
39 };
40
41 serial@70006300 {
42 status = "disable";
43 };
44
45 serial@70006400 {
46 status = "disable";
47 };
48
49 sdhci@c8000000 {
50 status = "disable";
51 };
52
53 sdhci@c8000200 {
54 status = "disable";
55 };
56
57 sdhci@c8000400 {
58 status = "disable";
59 };
60
61 sdhci@c8000600 {
62 cd-gpios = <&gpio 121 0>;
63 wp-gpios = <&gpio 122 0>;
64 };
65};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 3f9abd6b6964..c7d3b87f29df 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -1,24 +1,59 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/memreserve/ 0x1c000000 0x04000000;
4/include/ "tegra20.dtsi" 3/include/ "tegra20.dtsi"
5 4
6/ { 5/ {
7 model = "NVIDIA Tegra2 Ventana evaluation board"; 6 model = "NVIDIA Tegra2 Ventana evaluation board";
8 compatible = "nvidia,ventana", "nvidia,tegra20"; 7 compatible = "nvidia,ventana", "nvidia,tegra20";
9 8
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
12 };
13
14 memory { 9 memory {
15 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
16 }; 11 };
17 12
13 i2c@7000c000 {
14 clock-frequency = <400000>;
15 };
16
17 i2c@7000c400 {
18 clock-frequency = <400000>;
19 };
20
21 i2c@7000c500 {
22 clock-frequency = <400000>;
23 };
24
25 i2c@7000d000 {
26 clock-frequency = <400000>;
27 };
28
29 serial@70006000 {
30 status = "disable";
31 };
32
33 serial@70006040 {
34 status = "disable";
35 };
36
37 serial@70006200 {
38 status = "disable";
39 };
40
18 serial@70006300 { 41 serial@70006300 {
19 clock-frequency = < 216000000 >; 42 clock-frequency = < 216000000 >;
20 }; 43 };
21 44
45 serial@70006400 {
46 status = "disable";
47 };
48
49 sdhci@c8000000 {
50 status = "disable";
51 };
52
53 sdhci@c8000200 {
54 status = "disable";
55 };
56
22 sdhci@c8000400 { 57 sdhci@c8000400 {
23 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 58 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
24 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 59 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 65d7e6a333eb..3da7afd45322 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -5,9 +5,9 @@
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 intc: interrupt-controller@50041000 { 7 intc: interrupt-controller@50041000 {
8 compatible = "nvidia,tegra20-gic"; 8 compatible = "arm,cortex-a9-gic";
9 interrupt-controller; 9 interrupt-controller;
10 #interrupt-cells = <1>; 10 #interrupt-cells = <3>;
11 reg = < 0x50041000 0x1000 >, 11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >; 12 < 0x50040100 0x0100 >;
13 }; 13 };
@@ -17,7 +17,7 @@
17 #size-cells = <0>; 17 #size-cells = <0>;
18 compatible = "nvidia,tegra20-i2c"; 18 compatible = "nvidia,tegra20-i2c";
19 reg = <0x7000C000 0x100>; 19 reg = <0x7000C000 0x100>;
20 interrupts = < 70 >; 20 interrupts = < 0 38 0x04 >;
21 }; 21 };
22 22
23 i2c@7000c400 { 23 i2c@7000c400 {
@@ -25,7 +25,7 @@
25 #size-cells = <0>; 25 #size-cells = <0>;
26 compatible = "nvidia,tegra20-i2c"; 26 compatible = "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>; 27 reg = <0x7000C400 0x100>;
28 interrupts = < 116 >; 28 interrupts = < 0 84 0x04 >;
29 }; 29 };
30 30
31 i2c@7000c500 { 31 i2c@7000c500 {
@@ -33,38 +33,32 @@
33 #size-cells = <0>; 33 #size-cells = <0>;
34 compatible = "nvidia,tegra20-i2c"; 34 compatible = "nvidia,tegra20-i2c";
35 reg = <0x7000C500 0x100>; 35 reg = <0x7000C500 0x100>;
36 interrupts = < 124 >; 36 interrupts = < 0 92 0x04 >;
37 }; 37 };
38 38
39 i2c@7000d000 { 39 i2c@7000d000 {
40 #address-cells = <1>; 40 #address-cells = <1>;
41 #size-cells = <0>; 41 #size-cells = <0>;
42 compatible = "nvidia,tegra20-i2c"; 42 compatible = "nvidia,tegra20-i2c-dvc";
43 reg = <0x7000D000 0x200>; 43 reg = <0x7000D000 0x200>;
44 interrupts = < 85 >; 44 interrupts = < 0 53 0x04 >;
45 }; 45 };
46 46
47 i2s@70002800 { 47 i2s@70002800 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "nvidia,tegra20-i2s"; 48 compatible = "nvidia,tegra20-i2s";
51 reg = <0x70002800 0x200>; 49 reg = <0x70002800 0x200>;
52 interrupts = < 45 >; 50 interrupts = < 0 13 0x04 >;
53 dma-channel = < 2 >; 51 dma-channel = < 2 >;
54 }; 52 };
55 53
56 i2s@70002a00 { 54 i2s@70002a00 {
57 #address-cells = <1>;
58 #size-cells = <0>;
59 compatible = "nvidia,tegra20-i2s"; 55 compatible = "nvidia,tegra20-i2s";
60 reg = <0x70002a00 0x200>; 56 reg = <0x70002a00 0x200>;
61 interrupts = < 35 >; 57 interrupts = < 0 3 0x04 >;
62 dma-channel = < 1 >; 58 dma-channel = < 1 >;
63 }; 59 };
64 60
65 das@70000c00 { 61 das@70000c00 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "nvidia,tegra20-das"; 62 compatible = "nvidia,tegra20-das";
69 reg = <0x70000c00 0x80>; 63 reg = <0x70000c00 0x80>;
70 }; 64 };
@@ -72,7 +66,13 @@
72 gpio: gpio@6000d000 { 66 gpio: gpio@6000d000 {
73 compatible = "nvidia,tegra20-gpio"; 67 compatible = "nvidia,tegra20-gpio";
74 reg = < 0x6000d000 0x1000 >; 68 reg = < 0x6000d000 0x1000 >;
75 interrupts = < 64 65 66 67 87 119 121 >; 69 interrupts = < 0 32 0x04
70 0 33 0x04
71 0 34 0x04
72 0 35 0x04
73 0 55 0x04
74 0 87 0x04
75 0 89 0x04 >;
76 #gpio-cells = <2>; 76 #gpio-cells = <2>;
77 gpio-controller; 77 gpio-controller;
78 }; 78 };
@@ -89,59 +89,80 @@
89 compatible = "nvidia,tegra20-uart"; 89 compatible = "nvidia,tegra20-uart";
90 reg = <0x70006000 0x40>; 90 reg = <0x70006000 0x40>;
91 reg-shift = <2>; 91 reg-shift = <2>;
92 interrupts = < 68 >; 92 interrupts = < 0 36 0x04 >;
93 }; 93 };
94 94
95 serial@70006040 { 95 serial@70006040 {
96 compatible = "nvidia,tegra20-uart"; 96 compatible = "nvidia,tegra20-uart";
97 reg = <0x70006040 0x40>; 97 reg = <0x70006040 0x40>;
98 reg-shift = <2>; 98 reg-shift = <2>;
99 interrupts = < 69 >; 99 interrupts = < 0 37 0x04 >;
100 }; 100 };
101 101
102 serial@70006200 { 102 serial@70006200 {
103 compatible = "nvidia,tegra20-uart"; 103 compatible = "nvidia,tegra20-uart";
104 reg = <0x70006200 0x100>; 104 reg = <0x70006200 0x100>;
105 reg-shift = <2>; 105 reg-shift = <2>;
106 interrupts = < 78 >; 106 interrupts = < 0 46 0x04 >;
107 }; 107 };
108 108
109 serial@70006300 { 109 serial@70006300 {
110 compatible = "nvidia,tegra20-uart"; 110 compatible = "nvidia,tegra20-uart";
111 reg = <0x70006300 0x100>; 111 reg = <0x70006300 0x100>;
112 reg-shift = <2>; 112 reg-shift = <2>;
113 interrupts = < 122 >; 113 interrupts = < 0 90 0x04 >;
114 }; 114 };
115 115
116 serial@70006400 { 116 serial@70006400 {
117 compatible = "nvidia,tegra20-uart"; 117 compatible = "nvidia,tegra20-uart";
118 reg = <0x70006400 0x100>; 118 reg = <0x70006400 0x100>;
119 reg-shift = <2>; 119 reg-shift = <2>;
120 interrupts = < 123 >; 120 interrupts = < 0 91 0x04 >;
121 }; 121 };
122 122
123 sdhci@c8000000 { 123 sdhci@c8000000 {
124 compatible = "nvidia,tegra20-sdhci"; 124 compatible = "nvidia,tegra20-sdhci";
125 reg = <0xc8000000 0x200>; 125 reg = <0xc8000000 0x200>;
126 interrupts = < 46 >; 126 interrupts = < 0 14 0x04 >;
127 }; 127 };
128 128
129 sdhci@c8000200 { 129 sdhci@c8000200 {
130 compatible = "nvidia,tegra20-sdhci"; 130 compatible = "nvidia,tegra20-sdhci";
131 reg = <0xc8000200 0x200>; 131 reg = <0xc8000200 0x200>;
132 interrupts = < 47 >; 132 interrupts = < 0 15 0x04 >;
133 }; 133 };
134 134
135 sdhci@c8000400 { 135 sdhci@c8000400 {
136 compatible = "nvidia,tegra20-sdhci"; 136 compatible = "nvidia,tegra20-sdhci";
137 reg = <0xc8000400 0x200>; 137 reg = <0xc8000400 0x200>;
138 interrupts = < 51 >; 138 interrupts = < 0 19 0x04 >;
139 }; 139 };
140 140
141 sdhci@c8000600 { 141 sdhci@c8000600 {
142 compatible = "nvidia,tegra20-sdhci"; 142 compatible = "nvidia,tegra20-sdhci";
143 reg = <0xc8000600 0x200>; 143 reg = <0xc8000600 0x200>;
144 interrupts = < 63 >; 144 interrupts = < 0 31 0x04 >;
145 };
146
147 usb@c5000000 {
148 compatible = "nvidia,tegra20-ehci", "usb-ehci";
149 reg = <0xc5000000 0x4000>;
150 interrupts = < 0 20 0x04 >;
151 phy_type = "utmi";
152 };
153
154 usb@c5004000 {
155 compatible = "nvidia,tegra20-ehci", "usb-ehci";
156 reg = <0xc5004000 0x4000>;
157 interrupts = < 0 21 0x04 >;
158 phy_type = "ulpi";
159 };
160
161 usb@c5008000 {
162 compatible = "nvidia,tegra20-ehci", "usb-ehci";
163 reg = <0xc5008000 0x4000>;
164 interrupts = < 0 97 0x04 >;
165 phy_type = "utmi";
145 }; 166 };
146}; 167};
147 168
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
new file mode 100644
index 000000000000..ee7db9892e02
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -0,0 +1,127 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
7 intc: interrupt-controller@50041000 {
8 compatible = "arm,cortex-a9-gic";
9 interrupt-controller;
10 #interrupt-cells = <3>;
11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >;
13 };
14
15 i2c@7000c000 {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
19 reg = <0x7000C000 0x100>;
20 interrupts = < 0 38 0x04 >;
21 };
22
23 i2c@7000c400 {
24 #address-cells = <1>;
25 #size-cells = <0>;
26 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>;
28 interrupts = < 0 84 0x04 >;
29 };
30
31 i2c@7000c500 {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
35 reg = <0x7000C500 0x100>;
36 interrupts = < 0 92 0x04 >;
37 };
38
39 i2c@7000c700 {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
43 reg = <0x7000c700 0x100>;
44 interrupts = < 0 120 0x04 >;
45 };
46
47 i2c@7000d000 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
51 reg = <0x7000D000 0x100>;
52 interrupts = < 0 53 0x04 >;
53 };
54
55 gpio: gpio@6000d000 {
56 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
57 reg = < 0x6000d000 0x1000 >;
58 interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
59 #gpio-cells = <2>;
60 gpio-controller;
61 };
62
63 serial@70006000 {
64 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
65 reg = <0x70006000 0x40>;
66 reg-shift = <2>;
67 interrupts = < 0 36 0x04 >;
68 };
69
70 serial@70006040 {
71 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
72 reg = <0x70006040 0x40>;
73 reg-shift = <2>;
74 interrupts = < 0 37 0x04 >;
75 };
76
77 serial@70006200 {
78 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
79 reg = <0x70006200 0x100>;
80 reg-shift = <2>;
81 interrupts = < 0 46 0x04 >;
82 };
83
84 serial@70006300 {
85 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
86 reg = <0x70006300 0x100>;
87 reg-shift = <2>;
88 interrupts = < 0 90 0x04 >;
89 };
90
91 serial@70006400 {
92 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
93 reg = <0x70006400 0x100>;
94 reg-shift = <2>;
95 interrupts = < 0 91 0x04 >;
96 };
97
98 sdhci@78000000 {
99 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
100 reg = <0x78000000 0x200>;
101 interrupts = < 0 14 0x04 >;
102 };
103
104 sdhci@78000200 {
105 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
106 reg = <0x78000200 0x200>;
107 interrupts = < 0 15 0x04 >;
108 };
109
110 sdhci@78000400 {
111 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
112 reg = <0x78000400 0x200>;
113 interrupts = < 0 19 0x04 >;
114 };
115
116 sdhci@78000600 {
117 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
118 reg = <0x78000600 0x200>;
119 interrupts = < 0 31 0x04 >;
120 };
121
122 pinmux: pinmux@70000000 {
123 compatible = "nvidia,tegra30-pinmux";
124 reg = < 0x70000868 0xd0 /* Pad control registers */
125 0x70003000 0x3e0 >; /* Mux registers */
126 };
127};
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 5be8e9eefc95..c9ec38e82991 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -32,6 +32,8 @@ obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o
32obj-$(CONFIG_MACH_TEGRA_DT) += board-dt.o 32obj-$(CONFIG_MACH_TEGRA_DT) += board-dt.o
33obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o 33obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o
34obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o 34obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o
35obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o
36obj-$(CONFIG_MACH_TEGRA_DT) += board-trimslice-pinmux.o
35 37
36obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o 38obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o
37obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o 39obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index bd12c9fb81e8..cf51a000d400 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,5 +3,7 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
4 4
5dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb 5dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
6dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
6dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb 7dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
8dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
7dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb 9dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
index e417a8383dbb..46074a2f0b82 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt.c
@@ -37,6 +37,7 @@
37#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
38#include <asm/mach/time.h> 38#include <asm/mach/time.h>
39#include <asm/setup.h> 39#include <asm/setup.h>
40#include <asm/hardware/gic.h>
40 41
41#include <mach/iomap.h> 42#include <mach/iomap.h>
42#include <mach/irqs.h> 43#include <mach/irqs.h>
@@ -47,9 +48,22 @@
47#include "devices.h" 48#include "devices.h"
48 49
49void harmony_pinmux_init(void); 50void harmony_pinmux_init(void);
51void paz00_pinmux_init(void);
50void seaboard_pinmux_init(void); 52void seaboard_pinmux_init(void);
53void trimslice_pinmux_init(void);
51void ventana_pinmux_init(void); 54void ventana_pinmux_init(void);
52 55
56static const struct of_device_id tegra_dt_irq_match[] __initconst = {
57 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
58 { }
59};
60
61void __init tegra_dt_init_irq(void)
62{
63 tegra_init_irq();
64 of_irq_init(tegra_dt_irq_match);
65}
66
53struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 67struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
54 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), 68 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
55 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), 69 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
@@ -58,16 +72,30 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
58 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), 72 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
59 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), 73 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
60 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), 74 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
61 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), 75 OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
62 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL), 76 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
63 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL), 77 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
64 OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL), 78 OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
79 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
80 &tegra_ehci1_device.dev.platform_data),
81 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
82 &tegra_ehci2_device.dev.platform_data),
83 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
84 &tegra_ehci3_device.dev.platform_data),
65 {} 85 {}
66}; 86};
67 87
68static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 88static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
69 /* name parent rate enabled */ 89 /* name parent rate enabled */
70 { "uartd", "pll_p", 216000000, true }, 90 { "uartd", "pll_p", 216000000, true },
91 { "usbd", "clk_m", 12000000, false },
92 { "usb2", "clk_m", 12000000, false },
93 { "usb3", "clk_m", 12000000, false },
94 { "pll_a", "pll_p_out1", 56448000, true },
95 { "pll_a_out0", "pll_a", 11289600, true },
96 { "cdev1", NULL, 0, true },
97 { "i2s1", "pll_a_out0", 11289600, false},
98 { "i2s2", "pll_a_out0", 11289600, false},
71 { NULL, NULL, 0, 0}, 99 { NULL, NULL, 0, 0},
72}; 100};
73 101
@@ -76,30 +104,21 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
76 {} 104 {}
77}; 105};
78 106
79static struct of_device_id tegra_dt_gic_match[] __initdata = {
80 { .compatible = "nvidia,tegra20-gic", },
81 {}
82};
83
84static struct { 107static struct {
85 char *machine; 108 char *machine;
86 void (*init)(void); 109 void (*init)(void);
87} pinmux_configs[] = { 110} pinmux_configs[] = {
111 { "compulab,trimslice", trimslice_pinmux_init },
88 { "nvidia,harmony", harmony_pinmux_init }, 112 { "nvidia,harmony", harmony_pinmux_init },
113 { "compal,paz00", paz00_pinmux_init },
89 { "nvidia,seaboard", seaboard_pinmux_init }, 114 { "nvidia,seaboard", seaboard_pinmux_init },
90 { "nvidia,ventana", ventana_pinmux_init }, 115 { "nvidia,ventana", ventana_pinmux_init },
91}; 116};
92 117
93static void __init tegra_dt_init(void) 118static void __init tegra_dt_init(void)
94{ 119{
95 struct device_node *node;
96 int i; 120 int i;
97 121
98 node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
99 TEGRA_ARM_INT_DIST_BASE);
100 if (node)
101 irq_domain_add_simple(node, INT_GIC_BASE);
102
103 tegra_clk_init_from_table(tegra_dt_clk_init_table); 122 tegra_clk_init_from_table(tegra_dt_clk_init_table);
104 123
105 /* 124 /*
@@ -121,7 +140,9 @@ static void __init tegra_dt_init(void)
121} 140}
122 141
123static const char * tegra_dt_board_compat[] = { 142static const char * tegra_dt_board_compat[] = {
143 "compulab,trimslice",
124 "nvidia,harmony", 144 "nvidia,harmony",
145 "compal,paz00",
125 "nvidia,seaboard", 146 "nvidia,seaboard",
126 "nvidia,ventana", 147 "nvidia,ventana",
127 NULL 148 NULL
@@ -130,7 +151,7 @@ static const char * tegra_dt_board_compat[] = {
130DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") 151DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
131 .map_io = tegra_map_common_io, 152 .map_io = tegra_map_common_io,
132 .init_early = tegra_init_early, 153 .init_early = tegra_init_early,
133 .init_irq = tegra_init_irq, 154 .init_irq = tegra_dt_init_irq,
134 .handle_irq = gic_handle_irq, 155 .handle_irq = gic_handle_irq,
135 .timer = &tegra_timer, 156 .timer = &tegra_timer,
136 .init_machine = tegra_dt_init, 157 .init_machine = tegra_dt_init,
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 8ad82af6a293..4e1afcd54fae 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -21,6 +21,7 @@
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/of.h>
24 25
25#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
26 27
@@ -125,6 +126,11 @@ void __init tegra_init_irq(void)
125 gic_arch_extn.irq_unmask = tegra_unmask; 126 gic_arch_extn.irq_unmask = tegra_unmask;
126 gic_arch_extn.irq_retrigger = tegra_retrigger; 127 gic_arch_extn.irq_retrigger = tegra_retrigger;
127 128
128 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 129 /*
129 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 130 * Check if there is a devicetree present, since the GIC will be
131 * initialized elsewhere under DT.
132 */
133 if (!of_have_populated_dt())
134 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
135 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
130} 136}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 02:47:33 -0500