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-rw-r--r--arch/powerpc/Kconfig1
-rw-r--r--arch/powerpc/boot/dts/ksi8560.dts4
-rw-r--r--arch/powerpc/boot/dts/pq2fads.dts20
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts4
-rw-r--r--arch/powerpc/boot/dts/socrates.dts1
-rw-r--r--arch/powerpc/boot/dts/stx_gp3_8560.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts4
-rw-r--r--arch/powerpc/include/asm/mpic.h12
-rw-r--r--arch/powerpc/include/asm/reg.h30
-rw-r--r--arch/powerpc/include/asm/reg_booke.h30
-rw-r--r--arch/powerpc/include/asm/sfp-machine.h6
-rw-r--r--arch/powerpc/sysdev/mpic.c34
16 files changed, 111 insertions, 55 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9e08d8a69fdf..e0f0a4dbe9ae 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -775,6 +775,7 @@ config LOWMEM_CAM_NUM_BOOL
775 Say N here unless you know what you are doing. 775 Say N here unless you know what you are doing.
776 776
777config LOWMEM_CAM_NUM 777config LOWMEM_CAM_NUM
778 depends on FSL_BOOKE
778 int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL 779 int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL
779 default 3 780 default 3
780 781
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index 308fe7c29dea..c9cfd374bffb 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -57,14 +57,14 @@
57 bus-frequency = <0>; /* Fixed by bootwrapper */ 57 bus-frequency = <0>; /* Fixed by bootwrapper */
58 58
59 memory-controller@2000 { 59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
63 interrupts = <0x12 0x2>; 63 interrupts = <0x12 0x2>;
64 }; 64 };
65 65
66 L2: l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,mpc8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
69 cache-line-size = <0x20>; /* 32 bytes */ 69 cache-line-size = <0x20>; /* 32 bytes */
70 cache-size = <0x40000>; /* L2, 256K */ 70 cache-size = <0x40000>; /* L2, 256K */
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
index b2d61091b36d..0bb669376743 100644
--- a/arch/powerpc/boot/dts/pq2fads.dts
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -17,6 +17,14 @@
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
20 cpus { 28 cpus {
21 #address-cells = <1>; 29 #address-cells = <1>;
22 #size-cells = <0>; 30 #size-cells = <0>;
@@ -45,7 +53,7 @@
45 #size-cells = <1>; 53 #size-cells = <1>;
46 reg = <0xf0010100 0x60>; 54 reg = <0xf0010100 0x60>;
47 55
48 ranges = <0x0 0x0 0xfe000000 0x800000 56 ranges = <0x0 0x0 0xff800000 0x800000
49 0x1 0x0 0xf4500000 0x8000 57 0x1 0x0 0xf4500000 0x8000
50 0x8 0x0 0xf8200000 0x8000>; 58 0x8 0x0 0xf8200000 0x8000>;
51 59
@@ -71,7 +79,7 @@
71 }; 79 };
72 }; 80 };
73 81
74 pci@f0010800 { 82 pci0: pci@f0010800 {
75 device_type = "pci"; 83 device_type = "pci";
76 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; 84 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
77 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; 85 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
@@ -142,7 +150,7 @@
142 reg = <0x119f0 0x10 0x115f0 0x10>; 150 reg = <0x119f0 0x10 0x115f0 0x10>;
143 }; 151 };
144 152
145 serial@11a00 { 153 serial0: serial@11a00 {
146 device_type = "serial"; 154 device_type = "serial";
147 compatible = "fsl,mpc8280-scc-uart", 155 compatible = "fsl,mpc8280-scc-uart",
148 "fsl,cpm2-scc-uart"; 156 "fsl,cpm2-scc-uart";
@@ -153,7 +161,7 @@
153 fsl,cpm-command = <0x800000>; 161 fsl,cpm-command = <0x800000>;
154 }; 162 };
155 163
156 serial@11a20 { 164 serial1: serial@11a20 {
157 device_type = "serial"; 165 device_type = "serial";
158 compatible = "fsl,mpc8280-scc-uart", 166 compatible = "fsl,mpc8280-scc-uart",
159 "fsl,cpm2-scc-uart"; 167 "fsl,cpm2-scc-uart";
@@ -164,7 +172,7 @@
164 fsl,cpm-command = <0x4a00000>; 172 fsl,cpm-command = <0x4a00000>;
165 }; 173 };
166 174
167 ethernet@11320 { 175 enet0: ethernet@11320 {
168 device_type = "network"; 176 device_type = "network";
169 compatible = "fsl,mpc8280-fcc-enet", 177 compatible = "fsl,mpc8280-fcc-enet",
170 "fsl,cpm2-fcc-enet"; 178 "fsl,cpm2-fcc-enet";
@@ -176,7 +184,7 @@
176 fsl,cpm-command = <0x16200300>; 184 fsl,cpm-command = <0x16200300>;
177 }; 185 };
178 186
179 ethernet@11340 { 187 enet1: ethernet@11340 {
180 device_type = "network"; 188 device_type = "network";
181 compatible = "fsl,mpc8280-fcc-enet", 189 compatible = "fsl,mpc8280-fcc-enet",
182 "fsl,cpm2-fcc-enet"; 190 "fsl,cpm2-fcc-enet";
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 9c5079fec4f2..b1f1416ac998 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -156,14 +156,14 @@
156 compatible = "simple-bus"; 156 compatible = "simple-bus";
157 157
158 memory-controller@2000 { 158 memory-controller@2000 {
159 compatible = "fsl,8548-memory-controller"; 159 compatible = "fsl,mpc8548-memory-controller";
160 reg = <0x2000 0x1000>; 160 reg = <0x2000 0x1000>;
161 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>;
162 interrupts = <0x12 0x2>; 162 interrupts = <0x12 0x2>;
163 }; 163 };
164 164
165 L2: l2-cache-controller@20000 { 165 L2: l2-cache-controller@20000 {
166 compatible = "fsl,8548-l2-cache-controller"; 166 compatible = "fsl,mpc8548-l2-cache-controller";
167 reg = <0x20000 0x1000>; 167 reg = <0x20000 0x1000>;
168 cache-line-size = <0x20>; // 32 bytes 168 cache-line-size = <0x20>; // 32 bytes
169 cache-size = <0x80000>; // L2, 512K 169 cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index b772405a9a0a..c4564b81e473 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -61,14 +61,14 @@
61 clock-frequency = <0>; 61 clock-frequency = <0>;
62 62
63 memory-controller@2000 { 63 memory-controller@2000 {
64 compatible = "fsl,8560-memory-controller"; 64 compatible = "fsl,mpc8560-memory-controller";
65 reg = <0x2000 0x1000>; 65 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>; 66 interrupt-parent = <&mpic>;
67 interrupts = <0x12 0x2>; 67 interrupts = <0x12 0x2>;
68 }; 68 };
69 69
70 L2: l2-cache-controller@20000 { 70 L2: l2-cache-controller@20000 {
71 compatible = "fsl,8560-l2-cache-controller"; 71 compatible = "fsl,mpc8560-l2-cache-controller";
72 reg = <0x20000 0x1000>; 72 reg = <0x20000 0x1000>;
73 cache-line-size = <0x20>; // 32 bytes 73 cache-line-size = <0x20>; // 32 bytes
74 cache-size = <0x40000>; // L2, 256K 74 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index b8d0fc6f0042..04c398862e03 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -52,6 +52,7 @@
52 soc8544@e0000000 { 52 soc8544@e0000000 {
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc";
55 56
56 ranges = <0x00000000 0xe0000000 0x00100000>; 57 ranges = <0x00000000 0xe0000000 0x00100000>;
57 reg = <0xe0000000 0x00001000>; // CCSRBAR 1M 58 reg = <0xe0000000 0x00001000>; // CCSRBAR 1M
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index 8b173957fb5f..ea6b15152de3 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -57,14 +57,14 @@
57 compatible = "fsl,mpc8560-immr", "simple-bus"; 57 compatible = "fsl,mpc8560-immr", "simple-bus";
58 58
59 memory-controller@2000 { 59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
63 interrupts = <18 2>; 63 interrupts = <18 2>;
64 }; 64 };
65 65
66 L2: l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,mpc8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; 69 cache-line-size = <32>;
70 cache-size = <0x40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index ac9413a29f9f..231bae756637 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -59,14 +59,14 @@
59 compatible = "fsl,mpc8540-immr", "simple-bus"; 59 compatible = "fsl,mpc8540-immr", "simple-bus";
60 60
61 memory-controller@2000 { 61 memory-controller@2000 {
62 compatible = "fsl,8540-memory-controller"; 62 compatible = "fsl,mpc8540-memory-controller";
63 reg = <0x2000 0x1000>; 63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>; 64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>; 65 interrupts = <18 2>;
66 }; 66 };
67 67
68 L2: l2-cache-controller@20000 { 68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8540-l2-cache-controller"; 69 compatible = "fsl,mpc8540-l2-cache-controller";
70 reg = <0x20000 0x1000>; 70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; 71 cache-line-size = <32>;
72 cache-size = <0x40000>; // L2, 256K 72 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index c71bb5dd5e5e..4356a1f08295 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -58,14 +58,14 @@
58 compatible = "fsl,mpc8541-immr", "simple-bus"; 58 compatible = "fsl,mpc8541-immr", "simple-bus";
59 59
60 memory-controller@2000 { 60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 L2: l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,mpc8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index a133ded6dddb..06d366ebbda3 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -58,14 +58,14 @@
58 compatible = "fsl,mpc8555-immr", "simple-bus"; 58 compatible = "fsl,mpc8555-immr", "simple-bus";
59 59
60 memory-controller@2000 { 60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 L2: l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,mpc8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 649e2e576267..feff915e0492 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -60,14 +60,14 @@
60 compatible = "fsl,mpc8560-immr", "simple-bus"; 60 compatible = "fsl,mpc8560-immr", "simple-bus";
61 61
62 memory-controller@2000 { 62 memory-controller@2000 {
63 compatible = "fsl,8540-memory-controller"; 63 compatible = "fsl,mpc8540-memory-controller";
64 reg = <0x2000 0x1000>; 64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>; 65 interrupt-parent = <&mpic>;
66 interrupts = <18 2>; 66 interrupts = <18 2>;
67 }; 67 };
68 68
69 L2: l2-cache-controller@20000 { 69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8540-l2-cache-controller"; 70 compatible = "fsl,mpc8540-l2-cache-controller";
71 reg = <0x20000 0x1000>; 71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; 72 cache-line-size = <32>;
73 cache-size = <0x40000>; // L2, 256K 73 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c2ccca53b991..a002682f3a6d 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -22,6 +22,14 @@
22#define MPIC_GREG_FEATURE_1 0x00010 22#define MPIC_GREG_FEATURE_1 0x00010
23#define MPIC_GREG_GLOBAL_CONF_0 0x00020 23#define MPIC_GREG_GLOBAL_CONF_0 0x00020
24#define MPIC_GREG_GCONF_RESET 0x80000000 24#define MPIC_GREG_GCONF_RESET 0x80000000
25/* On the FSL mpic implementations the Mode field is expand to be
26 * 2 bits wide:
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
29 * 0b10 = reserved
30 * 0b11 = External proxy / coreint
31 */
32#define MPIC_GREG_GCONF_COREINT 0x60000000
25#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 33#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
26#define MPIC_GREG_GCONF_NO_BIAS 0x10000000 34#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
27#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff 35#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
@@ -357,6 +365,8 @@ struct mpic
357#define MPIC_BROKEN_FRR_NIRQS 0x00000800 365#define MPIC_BROKEN_FRR_NIRQS 0x00000800
358/* Destination only supports a single CPU at a time */ 366/* Destination only supports a single CPU at a time */
359#define MPIC_SINGLE_DEST_CPU 0x00001000 367#define MPIC_SINGLE_DEST_CPU 0x00001000
368/* Enable CoreInt delivery of interrupts */
369#define MPIC_ENABLE_COREINT 0x00002000
360 370
361/* MPIC HW modification ID */ 371/* MPIC HW modification ID */
362#define MPIC_REGSET_MASK 0xf0000000 372#define MPIC_REGSET_MASK 0xf0000000
@@ -470,6 +480,8 @@ extern void mpic_end_irq(unsigned int irq);
470extern unsigned int mpic_get_one_irq(struct mpic *mpic); 480extern unsigned int mpic_get_one_irq(struct mpic *mpic);
471/* This one gets from the primary mpic */ 481/* This one gets from the primary mpic */
472extern unsigned int mpic_get_irq(void); 482extern unsigned int mpic_get_irq(void);
483/* This one gets from the primary mpic via CoreInt*/
484extern unsigned int mpic_get_coreint_irq(void);
473/* Fetch Machine Check interrupt from primary mpic */ 485/* Fetch Machine Check interrupt from primary mpic */
474extern unsigned int mpic_get_mcirq(void); 486extern unsigned int mpic_get_mcirq(void);
475 487
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c9ff1ec97479..e8018d540e87 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -143,6 +143,36 @@
143#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 143#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
144#define FPSCR_RN 0x00000003 /* FPU rounding control */ 144#define FPSCR_RN 0x00000003 /* FPU rounding control */
145 145
146/* Bit definitions for SPEFSCR. */
147#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
148#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
149#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
150#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
151#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
152#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
153#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
154#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
155#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
156#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
157#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
158#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
159#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
160#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
161#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
162#define SPEFSCR_OV 0x00004000 /* Integer overflow */
163#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
164#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
165#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
166#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
167#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
168#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
169#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
170#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
171#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
172#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
173#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
174#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
175
146/* Special Purpose Registers (SPRNs)*/ 176/* Special Purpose Registers (SPRNs)*/
147#define SPRN_CTR 0x009 /* Count Register */ 177#define SPRN_CTR 0x009 /* Count Register */
148#define SPRN_DSCR 0x11 178#define SPRN_DSCR 0x11
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index a56f4d61aa72..601ddbc46002 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -423,36 +423,6 @@
423#define SGR_NORMAL 0 /* Speculative fetching allowed. */ 423#define SGR_NORMAL 0 /* Speculative fetching allowed. */
424#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ 424#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
425 425
426/* Bit definitions for SPEFSCR. */
427#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
428#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
429#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
430#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
431#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
432#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
433#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
434#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
435#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
436#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
437#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
438#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
439#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
440#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
441#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
442#define SPEFSCR_OV 0x00004000 /* Integer overflow */
443#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
444#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
445#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
446#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
447#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
448#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
449#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
450#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
451#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
452#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
453#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
454#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
455
456/* 426/*
457 * The IBM-403 is an even more odd special case, as it is much 427 * The IBM-403 is an even more odd special case, as it is much
458 * older than the IBM-405 series. We put these down here incase someone 428 * older than the IBM-405 series. We put these down here incase someone
diff --git a/arch/powerpc/include/asm/sfp-machine.h b/arch/powerpc/include/asm/sfp-machine.h
index 3d9f831c3c55..3a7a67a0d006 100644
--- a/arch/powerpc/include/asm/sfp-machine.h
+++ b/arch/powerpc/include/asm/sfp-machine.h
@@ -29,9 +29,9 @@
29 29
30/* basic word size definitions */ 30/* basic word size definitions */
31#define _FP_W_TYPE_SIZE 32 31#define _FP_W_TYPE_SIZE 32
32#define _FP_W_TYPE unsigned long 32#define _FP_W_TYPE unsigned int
33#define _FP_WS_TYPE signed long 33#define _FP_WS_TYPE signed int
34#define _FP_I_TYPE long 34#define _FP_I_TYPE int
35 35
36#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) 36#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
37#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) 37#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 532e205303a2..21b956701596 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1170,6 +1170,12 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1170 mb(); 1170 mb();
1171 } 1171 }
1172 1172
1173 /* CoreInt */
1174 if (flags & MPIC_ENABLE_COREINT)
1175 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1176 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1177 | MPIC_GREG_GCONF_COREINT);
1178
1173 if (flags & MPIC_ENABLE_MCK) 1179 if (flags & MPIC_ENABLE_MCK)
1174 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), 1180 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1175 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) 1181 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
@@ -1525,6 +1531,34 @@ unsigned int mpic_get_irq(void)
1525 return mpic_get_one_irq(mpic); 1531 return mpic_get_one_irq(mpic);
1526} 1532}
1527 1533
1534unsigned int mpic_get_coreint_irq(void)
1535{
1536#ifdef CONFIG_BOOKE
1537 struct mpic *mpic = mpic_primary;
1538 u32 src;
1539
1540 BUG_ON(mpic == NULL);
1541
1542 src = mfspr(SPRN_EPR);
1543
1544 if (unlikely(src == mpic->spurious_vec)) {
1545 if (mpic->flags & MPIC_SPV_EOI)
1546 mpic_eoi(mpic);
1547 return NO_IRQ;
1548 }
1549 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1550 if (printk_ratelimit())
1551 printk(KERN_WARNING "%s: Got protected source %d !\n",
1552 mpic->name, (int)src);
1553 return NO_IRQ;
1554 }
1555
1556 return irq_linear_revmap(mpic->irqhost, src);
1557#else
1558 return NO_IRQ;
1559#endif
1560}
1561
1528unsigned int mpic_get_mcirq(void) 1562unsigned int mpic_get_mcirq(void)
1529{ 1563{
1530 struct mpic *mpic = mpic_primary; 1564 struct mpic *mpic = mpic_primary;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 18:36:31 -0500