153 files changed, 5612 insertions, 793 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7af7d1368942..bf11bf5427da 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -671,6 +671,7 @@ config ARCH_TEGRA
         select HAVE_CLK
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
         help
@@ -1666,7 +1667,7 @@ config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 512 if SOC_OMAP5
-        default 355 if ARCH_U8500
+        default 392 if ARCH_U8500
         default 288 if ARCH_VT8500 || ARCH_SUNXI
         default 264 if MACH_H4700
         default 0
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2be254709dcb..20358fb43450 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -33,6 +33,11 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
+# sama5d3
+dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
 
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts
new file mode 100644
index 000000000000..ab042ca8dea1
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6-evb.dts
@@ -0,0 +1,78 @@
+/*
+ * DTS file for CSR SiRFatlas6 Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "atlas6.dtsi"
+
+/ {
+        model = "CSR SiRFatlas6 Evaluation Board";
+        compatible = "sirf,atlas6-cb", "sirf,atlas6";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        axi {
+                peri-iobg {
+                        uart@b0060000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart1_pins_a>;
+                        };
+                        spi@b00d0000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi0_pins_a>;
+                                spi@0 {
+                                        compatible = "spidev";
+                                        reg = <0>;
+                                        spi-max-frequency = <1000000>;
+                                };
+                        };
+                        spi@b0170000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi1_pins_a>;
+                        };
+                        i2c0: i2c@b00e0000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                lcd@40 {
+                                        compatible = "sirf,lcd";
+                                        reg = <0x40>;
+                                };
+                        };
+
+                };
+                disp-iobg {
+                        lcd@90010000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcd_24pins_a>;
+                        };
+                };
+        };
+        display: display@0 {
+            panels {
+                panel0: panel@0 {
+                        panel-name = "Innolux TFT";
+                        hactive = <800>;
+                        vactive = <480>;
+                        left_margin = <20>;
+                        right_margin = <234>;
+                        upper_margin = <3>;
+                        lower_margin = <41>;
+                        hsync_len = <3>;
+                        vsync_len = <2>;
+                        pixclock = <33264000>;
+                        sync = <3>;
+                        timing = <0x88>;
+                        };
+            };
+        };
+};
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
new file mode 100644
index 000000000000..7d1a27949c13
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -0,0 +1,668 @@
+/*
+ * DTS file for CSR SiRFatlas6 SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "sirf,atlas6";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&intc>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        /* from bootloader */
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+
+        axi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x40000000 0x40000000 0x80000000>;
+
+                intc: interrupt-controller@80020000 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "sirf,prima2-intc";
+                        reg = <0x80020000 0x1000>;
+                };
+
+                sys-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x88000000 0x88000000 0x40000>;
+
+                        clks: clock-controller@88000000 {
+                                compatible = "sirf,atlas6-clkc";
+                                reg = <0x88000000 0x1000>;
+                                interrupts = <3>;
+                                #clock-cells = <1>;
+                        };
+
+                        reset-controller@88010000 {
+                                compatible = "sirf,prima2-rstc";
+                                reg = <0x88010000 0x1000>;
+                        };
+
+                        rsc-controller@88020000 {
+                                compatible = "sirf,prima2-rsc";
+                                reg = <0x88020000 0x1000>;
+                        };
+                };
+
+                mem-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90000000 0x90000000 0x10000>;
+
+                        memory-controller@90000000 {
+                                compatible = "sirf,prima2-memc";
+                                reg = <0x90000000 0x10000>;
+                                interrupts = <27>;
+                                clocks = <&clks 5>;
+                        };
+                };
+
+                disp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90010000 0x90010000 0x30000>;
+
+                        lcd@90010000 {
+                                compatible = "sirf,prima2-lcd";
+                                reg = <0x90010000 0x20000>;
+                                interrupts = <30>;
+                                clocks = <&clks 34>;
+                                display=<&display>;
+                                /* later transfer to pwm */
+                                bl-gpio = <&gpio 7 0>;
+                                default-panel = <&panel0>;
+                        };
+
+                        vpp@90020000 {
+                                compatible = "sirf,prima2-vpp";
+                                reg = <0x90020000 0x10000>;
+                                interrupts = <31>;
+                                clocks = <&clks 35>;
+                        };
+                };
+
+                graphics-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x98000000 0x98000000 0x8000000>;
+
+                        graphics@98000000 {
+                                compatible = "powervr,sgx510";
+                                reg = <0x98000000 0x8000000>;
+                                interrupts = <6>;
+                                clocks = <&clks 32>;
+                        };
+                };
+
+                dsp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa8000000 0xa8000000 0x2000000>;
+
+                        dspif@a8000000 {
+                                compatible = "sirf,prima2-dspif";
+                                reg = <0xa8000000 0x10000>;
+                                interrupts = <9>;
+                        };
+
+                        gps@a8010000 {
+                                compatible = "sirf,prima2-gps";
+                                reg = <0xa8010000 0x10000>;
+                                interrupts = <7>;
+                                clocks = <&clks 9>;
+                        };
+
+                        dsp@a9000000 {
+                                compatible = "sirf,prima2-dsp";
+                                reg = <0xa9000000 0x1000000>;
+                                interrupts = <8>;
+                                clocks = <&clks 8>;
+                        };
+                };
+
+                peri-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb0000000 0xb0000000 0x180000>,
+                               <0x56000000 0x56000000 0x1b00000>;
+
+                        timer@b0020000 {
+                                compatible = "sirf,prima2-tick";
+                                reg = <0xb0020000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        nand@b0030000 {
+                                compatible = "sirf,prima2-nand";
+                                reg = <0xb0030000 0x10000>;
+                                interrupts = <41>;
+                                clocks = <&clks 26>;
+                        };
+
+                        audio@b0040000 {
+                                compatible = "sirf,prima2-audio";
+                                reg = <0xb0040000 0x10000>;
+                                interrupts = <35>;
+                                clocks = <&clks 27>;
+                        };
+
+                        uart0: uart@b0050000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0050000 0x1000>;
+                                interrupts = <17>;
+                                fifosize = <128>;
+                                clocks = <&clks 13>;
+                        };
+
+                        uart1: uart@b0060000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0060000 0x1000>;
+                                interrupts = <18>;
+                                fifosize = <32>;
+                                clocks = <&clks 14>;
+                        };
+
+                        uart2: uart@b0070000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0070000 0x1000>;
+                                interrupts = <19>;
+                                fifosize = <128>;
+                                clocks = <&clks 15>;
+                        };
+
+                        usp0: usp@b0080000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0080000 0x10000>;
+                                interrupts = <20>;
+                                clocks = <&clks 28>;
+                        };
+
+                        usp1: usp@b0090000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0090000 0x10000>;
+                                interrupts = <21>;
+                                clocks = <&clks 29>;
+                        };
+
+                        dmac0: dma-controller@b00b0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb00b0000 0x10000>;
+                                interrupts = <12>;
+                                clocks = <&clks 24>;
+                        };
+
+                        dmac1: dma-controller@b0160000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb0160000 0x10000>;
+                                interrupts = <13>;
+                                clocks = <&clks 25>;
+                        };
+
+                        vip@b00C0000 {
+                                compatible = "sirf,prima2-vip";
+                                reg = <0xb00C0000 0x10000>;
+                                clocks = <&clks 31>;
+                        };
+
+                        spi0: spi@b00d0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb00d0000 0x10000>;
+                                interrupts = <15>;
+                                sirf,spi-num-chipselects = <1>;
+                                cs-gpios = <&gpio 0 0>;
+                                sirf,spi-dma-rx-channel = <25>;
+                                sirf,spi-dma-tx-channel = <20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clks 19>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@b0170000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb0170000 0x10000>;
+                                interrupts = <16>;
+                                clocks = <&clks 20>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@b00e0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00e0000 0x10000>;
+                                interrupts = <24>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clks 17>;
+                        };
+
+                        i2c1: i2c@b00f0000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00f0000 0x10000>;
+                                interrupts = <25>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clks 18>;
+                        };
+
+                        tsc@b0110000 {
+                                compatible = "sirf,prima2-tsc";
+                                reg = <0xb0110000 0x10000>;
+                                interrupts = <33>;
+                                clocks = <&clks 16>;
+                        };
+
+                        gpio: pinctrl@b0120000 {
+                                #gpio-cells = <2>;
+                                #interrupt-cells = <2>;
+                                compatible = "sirf,atlas6-pinctrl";
+                                reg = <0xb0120000 0x10000>;
+                                interrupts = <43 44 45 46 47>;
+                                gpio-controller;
+                                interrupt-controller;
+
+                                lcd_16pins_a: lcd0@0 {
+                                        lcd {
+                                                sirf,pins = "lcd_16bitsgrp";
+                                                sirf,function = "lcd_16bits";
+                                        };
+                                };
+                                lcd_18pins_a: lcd0@1 {
+                                        lcd {
+                                                sirf,pins = "lcd_18bitsgrp";
+                                                sirf,function = "lcd_18bits";
+                                        };
+                                };
+                                lcd_24pins_a: lcd0@2 {
+                                        lcd {
+                                                sirf,pins = "lcd_24bitsgrp";
+                                                sirf,function = "lcd_24bits";
+                                        };
+                                };
+                                lcdrom_pins_a: lcdrom0@0 {
+                                        lcd {
+                                                sirf,pins = "lcdromgrp";
+                                                sirf,function = "lcdrom";
+                                        };
+                                };
+                                uart0_pins_a: uart0@0 {
+                                        uart {
+                                                sirf,pins = "uart0grp";
+                                                sirf,function = "uart0";
+                                        };
+                                };
+                                uart1_pins_a: uart1@0 {
+                                        uart {
+                                                sirf,pins = "uart1grp";
+                                                sirf,function = "uart1";
+                                        };
+                                };
+                                uart2_pins_a: uart2@0 {
+                                        uart {
+                                                sirf,pins = "uart2grp";
+                                                sirf,function = "uart2";
+                                        };
+                                };
+                                uart2_noflow_pins_a: uart2@1 {
+                                        uart {
+                                                sirf,pins = "uart2_nostreamctrlgrp";
+                                                sirf,function = "uart2_nostreamctrl";
+                                        };
+                                };
+                                spi0_pins_a: spi0@0 {
+                                        spi {
+                                                sirf,pins = "spi0grp";
+                                                sirf,function = "spi0";
+                                        };
+                                };
+                                spi1_pins_a: spi1@0 {
+                                        spi {
+                                                sirf,pins = "spi1grp";
+                                                sirf,function = "spi1";
+                                        };
+                                };
+                                i2c0_pins_a: i2c0@0 {
+                                        i2c {
+                                                sirf,pins = "i2c0grp";
+                                                sirf,function = "i2c0";
+                                        };
+                                };
+                                i2c1_pins_a: i2c1@0 {
+                                        i2c {
+                                                sirf,pins = "i2c1grp";
+                                                sirf,function = "i2c1";
+                                        };
+                                };
+                                pwm0_pins_a: pwm0@0 {
+                                        pwm {
+                                                sirf,pins = "pwm0grp";
+                                                sirf,function = "pwm0";
+                                        };
+                                };
+                                pwm1_pins_a: pwm1@0 {
+                                        pwm {
+                                                sirf,pins = "pwm1grp";
+                                                sirf,function = "pwm1";
+                                        };
+                                };
+                                pwm2_pins_a: pwm2@0 {
+                                        pwm {
+                                                sirf,pins = "pwm2grp";
+                                                sirf,function = "pwm2";
+                                        };
+                                };
+                                pwm3_pins_a: pwm3@0 {
+                                        pwm {
+                                                sirf,pins = "pwm3grp";
+                                                sirf,function = "pwm3";
+                                        };
+                                };
+                                pwm4_pins_a: pwm4@0 {
+                                        pwm {
+                                                sirf,pins = "pwm4grp";
+                                                sirf,function = "pwm4";
+                                        };
+                                };
+                                gps_pins_a: gps@0 {
+                                        gps {
+                                                sirf,pins = "gpsgrp";
+                                                sirf,function = "gps";
+                                        };
+                                };
+                                vip_pins_a: vip@0 {
+                                        vip {
+                                                sirf,pins = "vipgrp";
+                                                sirf,function = "vip";
+                                        };
+                                };
+                                sdmmc0_pins_a: sdmmc0@0 {
+                                        sdmmc0 {
+                                                sirf,pins = "sdmmc0grp";
+                                                sirf,function = "sdmmc0";
+                                        };
+                                };
+                                sdmmc1_pins_a: sdmmc1@0 {
+                                        sdmmc1 {
+                                                sirf,pins = "sdmmc1grp";
+                                                sirf,function = "sdmmc1";
+                                        };
+                                };
+                                sdmmc2_pins_a: sdmmc2@0 {
+                                        sdmmc2 {
+                                                sirf,pins = "sdmmc2grp";
+                                                sirf,function = "sdmmc2";
+                                        };
+                                };
+                                sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
+                                        sdmmc2_nowp {
+                                                sirf,pins = "sdmmc2_nowpgrp";
+                                                sirf,function = "sdmmc2_nowp";
+                                        };
+                                };
+                                sdmmc3_pins_a: sdmmc3@0 {
+                                        sdmmc3 {
+                                                sirf,pins = "sdmmc3grp";
+                                                sirf,function = "sdmmc3";
+                                        };
+                                };
+                                sdmmc5_pins_a: sdmmc5@0 {
+                                        sdmmc5 {
+                                                sirf,pins = "sdmmc5grp";
+                                                sirf,function = "sdmmc5";
+                                        };
+                                };
+                                i2s_pins_a: i2s@0 {
+                                        i2s {
+                                                sirf,pins = "i2sgrp";
+                                                sirf,function = "i2s";
+                                        };
+                                };
+                                i2s_no_din_pins_a: i2s_no_din@0 {
+                                        i2s_no_din {
+                                                sirf,pins = "i2s_no_dingrp";
+                                                sirf,function = "i2s_no_din";
+                                        };
+                                };
+                                i2s_6chn_pins_a: i2s_6chn@0 {
+                                        i2s_6chn {
+                                                sirf,pins = "i2s_6chngrp";
+                                                sirf,function = "i2s_6chn";
+                                        };
+                                };
+                                ac97_pins_a: ac97@0 {
+                                        ac97 {
+                                                sirf,pins = "ac97grp";
+                                                sirf,function = "ac97";
+                                        };
+                                };
+                                nand_pins_a: nand@0 {
+                                        nand {
+                                                sirf,pins = "nandgrp";
+                                                sirf,function = "nand";
+                                        };
+                                };
+                                usp0_pins_a: usp0@0 {
+                                        usp0 {
+                                                sirf,pins = "usp0grp";
+                                                sirf,function = "usp0";
+                                        };
+                                };
+                                usp1_pins_a: usp1@0 {
+                                        usp1 {
+                                                sirf,pins = "usp1grp";
+                                                sirf,function = "usp1";
+                                        };
+                                };
+                                usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
+                                        usb0_upli_drvbus {
+                                                sirf,pins = "usb0_upli_drvbusgrp";
+                                                sirf,function = "usb0_upli_drvbus";
+                                        };
+                                };
+                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
+                                        usb1_utmi_drvbus {
+                                                sirf,pins = "usb1_utmi_drvbusgrp";
+                                                sirf,function = "usb1_utmi_drvbus";
+                                        };
+                                };
+                                warm_rst_pins_a: warm_rst@0 {
+                                        warm_rst {
+                                                sirf,pins = "warm_rstgrp";
+                                                sirf,function = "warm_rst";
+                                        };
+                                };
+                                pulse_count_pins_a: pulse_count@0 {
+                                        pulse_count {
+                                                sirf,pins = "pulse_countgrp";
+                                                sirf,function = "pulse_count";
+                                        };
+                                };
+                                cko0_rst_pins_a: cko0_rst@0 {
+                                        cko0_rst {
+                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,function = "cko0_rst";
+                                        };
+                                };
+                                cko1_rst_pins_a: cko1_rst@0 {
+                                        cko1_rst {
+                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,function = "cko1_rst";
+                                        };
+                                };
+                        };
+
+                        pwm@b0130000 {
+                                compatible = "sirf,prima2-pwm";
+                                reg = <0xb0130000 0x10000>;
+                                clocks = <&clks 21>;
+                        };
+
+                        efusesys@b0140000 {
+                                compatible = "sirf,prima2-efuse";
+                                reg = <0xb0140000 0x10000>;
+                                clocks = <&clks 22>;
+                        };
+
+                        pulsec@b0150000 {
+                                compatible = "sirf,prima2-pulsec";
+                                reg = <0xb0150000 0x10000>;
+                                interrupts = <48>;
+                                clocks = <&clks 23>;
+                        };
+
+                        pci-iobg {
+                                compatible = "sirf,prima2-pciiobg", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x56000000 0x56000000 0x1b00000>;
+
+                                sd0: sdhci@56000000 {
+                                        cell-index = <0>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56000000 0x100000>;
+                                        interrupts = <38>;
+                                        bus-width = <8>;
+                                        clocks = <&clks 36>;
+                                };
+
+                                sd1: sdhci@56100000 {
+                                        cell-index = <1>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56100000 0x100000>;
+                                        interrupts = <38>;
+                                        status = "disabled";
+                                        clocks = <&clks 36>;
+                                };
+
+                                sd2: sdhci@56200000 {
+                                        cell-index = <2>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56200000 0x100000>;
+                                        interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
+                                };
+
+                                sd3: sdhci@56300000 {
+                                        cell-index = <3>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56300000 0x100000>;
+                                        interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
+                                };
+
+                                sd5: sdhci@56500000 {
+                                        cell-index = <5>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56500000 0x100000>;
+                                        interrupts = <39>;
+                                        status = "disabled";
+                                        clocks = <&clks 38>;
+                                };
+
+                                pci-copy@57900000 {
+                                        compatible = "sirf,prima2-pcicp";
+                                        reg = <0x57900000 0x100000>;
+                                        interrupts = <40>;
+                                };
+
+                                rom-interface@57a00000 {
+                                        compatible = "sirf,prima2-romif";
+                                        reg = <0x57a00000 0x100000>;
+                                };
+                        };
+                };
+
+                rtc-iobg {
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80030000 0x10000>;
+
+                        gpsrtc@1000 {
+                                compatible = "sirf,prima2-gpsrtc";
+                                reg = <0x1000 0x1000>;
+                                interrupts = <55 56 57>;
+                        };
+
+                        sysrtc@2000 {
+                                compatible = "sirf,prima2-sysrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <52 53 54>;
+                        };
+
+                        pwrc@3000 {
+                                compatible = "sirf,prima2-pwrc";
+                                reg = <0x3000 0x1000>;
+                                interrupts = <32>;
+                        };
+                };
+
+                uus-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb8000000 0xb8000000 0x40000>;
+
+                        usb0: usb@b00e0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8000000 0x10000>;
+                                interrupts = <10>;
+                                clocks = <&clks 40>;
+                        };
+
+                        usb1: usb@b00f0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8010000 0x10000>;
+                                interrupts = <11>;
+                                clocks = <&clks 41>;
+                        };
+
+                        security@b00f0000 {
+                                compatible = "sirf,prima2-security";
+                                reg = <0xb8030000 0x10000>;
+                                interrupts = <42>;
+                                clocks = <&clks 7>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index ad135885bd2a..8f71f40722b9 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -47,4 +47,12 @@
                     cache-unified;
                     cache-level = <2>;
         };
+
+        timer@35006000 {
+                compatible = "bcm,kona-timer";
+                reg = <0x35006000 0x1000>;
+                interrupts = <0x0 7 0x4>;
+                clock-frequency = <32768>;
+        };
+
 };
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index f712fb607a42..c5834a6c5bf4 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -35,14 +35,84 @@
                         clock-frequency = <100000>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&i2c0_pins>;
+
+                        tps: tps@48 {
+                                reg = <0x48>;
+                        };
                 };
                 wdt: wdt@1c21000 {
                         status = "okay";
                 };
+                mmc0: mmc@1c40000 {
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
+                        status = "okay";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins>;
+                };
         };
         nand_cs3@62000000 {
                 status = "okay";
                 pinctrl-names = "default";
                 pinctrl-0 = <&nand_cs3_pins>;
         };
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+
+/include/ "tps6507x.dtsi"
+
+&tps {
+        vdcdc1_2-supply = <&vbat>;
+        vdcdc3-supply = <&vbat>;
+        vldo1_2-supply = <&vbat>;
+
+        regulators {
+                vdcdc1_reg: regulator@0 {
+                        regulator-name = "VDCDC1_3.3V";
+                        regulator-min-microvolt = <3150000>;
+                        regulator-max-microvolt = <3450000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                vdcdc2_reg: regulator@1 {
+                        regulator-name = "VDCDC2_3.3V";
+                        regulator-min-microvolt = <1710000>;
+                        regulator-max-microvolt = <3450000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        ti,defdcdc_default = <1>;
+                };
+
+                vdcdc3_reg: regulator@2 {
+                        regulator-name = "VDCDC3_1.2V";
+                        regulator-min-microvolt = <950000>;
+                        regulator-max-microvolt = <1350000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        ti,defdcdc_default = <1>;
+                };
+
+                ldo1_reg: regulator@3 {
+                        regulator-name = "LDO1_1.8V";
+                        regulator-min-microvolt = <1710000>;
+                        regulator-max-microvolt = <1890000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                ldo2_reg: regulator@4 {
+                        regulator-name = "LDO2_1.2V";
+                        regulator-min-microvolt = <1140000>;
+                        regulator-max-microvolt = <1320000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 3ec1bda64356..3ade343f13cc 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -62,6 +62,15 @@
                                         0x10 0x00002200 0x0000ff00
                                 >;
                         };
+                        mmc0_pins: pinmux_mmc_pins {
+                                pinctrl-single,bits = <
+                                        /* MMCSD0_DAT[3] MMCSD0_DAT[2]
+                                         * MMCSD0_DAT[1] MMCSD0_DAT[0]
+                                         * MMCSD0_CMD    MMCSD0_CLK
+                                         */
+                                        0x28 0x00222222  0x00ffffff
+                                >;
+                        };
                 };
                 serial0: serial@1c42000 {
                         compatible = "ns16550a";
@@ -107,6 +116,12 @@
                         reg = <0x21000 0x1000>;
                         status = "disabled";
                 };
+                mmc0: mmc@1c40000 {
+                        compatible = "ti,da830-mmc";
+                        reg = <0x40000 0x1000>;
+                        interrupts = <16>;
+                        status = "disabled";
+                };
         };
         nand_cs3@62000000 {
                 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 67f8670c4d6a..9bf49b3826ea 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -16,19 +16,13 @@
         };
 
         timer@2000004 {
-                compatible = "qcom,msm-gpt", "qcom,msm-timer";
-                interrupts = <1 1 0x301>;
-                reg = <0x02000004 0x10>;
-                clock-frequency = <32768>;
-                cpu-offset = <0x40000>;
-        };
-
-        timer@2000024 {
-                compatible = "qcom,msm-dgt", "qcom,msm-timer";
-                interrupts = <1 0 0x301>;
-                reg = <0x02000024 0x10>,
-                      <0x02000034 0x4>;
-                clock-frequency = <6750000>;
+                compatible = "qcom,scss-timer", "qcom,msm-timer";
+                interrupts = <1 0 0x301>,
+                             <1 1 0x301>,
+                             <1 2 0x301>;
+                reg = <0x02000000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
                 cpu-offset = <0x40000>;
         };
 
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index c9b09a813a4b..2e4d87a125d6 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -15,20 +15,14 @@
                       < 0x02002000 0x1000 >;
         };
 
-        timer@200a004 {
-                compatible = "qcom,msm-gpt", "qcom,msm-timer";
-                interrupts = <1 2 0x301>;
-                reg = <0x0200a004 0x10>;
-                clock-frequency = <32768>;
-                cpu-offset = <0x80000>;
-        };
-
-        timer@200a024 {
-                compatible = "qcom,msm-dgt", "qcom,msm-timer";
-                interrupts = <1 1 0x301>;
-                reg = <0x0200a024 0x10>,
-                      <0x0200a034 0x4>;
-                clock-frequency = <6750000>;
+        timer@200a000 {
+                compatible = "qcom,kpss-timer", "qcom,msm-timer";
+                interrupts = <1 1 0x301>,
+                             <1 2 0x301>,
+                             <1 3 0x301>;
+                reg = <0x0200a000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
                 cpu-offset = <0x80000>;
         };
 
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
new file mode 100644
index 000000000000..fe5c6f213271
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Device Tree Source for Renesas r8a7779
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "renesas,r8a7779";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                };
+        };
+
+        gic: interrupt-controller@f0001000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xf0001000 0x1000>,
+                      <0xf0000100 0x100>;
+        };
+
+        i2c0: i2c@0xffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 79 0x4>;
+        };
+
+        i2c1: i2c@0xffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 82 0x4>;
+        };
+
+        i2c2: i2c@0xffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 80 0x4>;
+        };
+
+        i2c3: i2c@0xffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 81 0x4>;
+        };
+
+        thermal@ffc48000 {
+                compatible = "renesas,rcar-thermal";
+                reg = <0xffc48000 0x38>;
+        };
+
+        sata: sata@fc600000 {
+                compatible = "renesas,rcar-sata";
+                reg = <0xfc600000 0x2000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 100 0x4>;
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
new file mode 100644
index 000000000000..39b0458d365a
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -0,0 +1,1031 @@
+/*
+ * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
+ *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Atmel SAMA5D3 family SoC";
+        compatible = "atmel,sama5d3", "atmel,sama5";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a5";
+                };
+        };
+
+        memory {
+                reg = <0x20000000 0x8000000>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        mmc0: mmc@f0000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf0000000 0x600>;
+                                interrupts = <21 4 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        spi0: spi@f0004000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9x5-spi";
+                                reg = <0xf0004000 0x100>;
+                                interrupts = <24 4 3>;
+                                cs-gpios = <&pioD 13 0
+                                            &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
+                                            &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
+                                            &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
+                                           >;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf0008000 0x4000>;
+                                interrupts = <38 4 4>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                status = "disabled";
+                        };
+
+                        can0: can@f000c000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf000c000 0x300>;
+                                interrupts = <40 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can0_rx_tx>;
+                                status = "disabled";
+                        };
+
+                        tcb0: timer@f0010000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf0010000 0x100>;
+                                interrupts = <26 4 0>;
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf0014000 0x4000>;
+                                interrupts = <18 4 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf0018000 0x4000>;
+                                interrupts = <19 4 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        usart0: serial@f001c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf001c000 0x100>;
+                                interrupts = <12 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
+                                status = "disabled";
+                        };
+
+                        usart1: serial@f0020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf0020000 0x100>;
+                                interrupts = <13 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
+                                status = "disabled";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                compatible = "cnds,pc302-gem", "cdns,gem";
+                                reg = <0xf0028000 0x100>;
+                                interrupts = <34 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+                                status = "disabled";
+                        };
+
+                        isi: isi@f0034000 {
+                                compatible = "atmel,at91sam9g45-isi";
+                                reg = <0xf0034000 0x4000>;
+                                interrupts = <37 4 5>;
+                                status = "disabled";
+                        };
+
+                        mmc1: mmc@f8000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf8000000 0x600>;
+                                interrupts = <22 4 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        mmc2: mmc@f8004000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf8004000 0x600>;
+                                interrupts = <23 4 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        spi1: spi@f8008000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9x5-spi";
+                                reg = <0xf8008000 0x100>;
+                                interrupts = <25 4 3>;
+                                cs-gpios = <&pioC 25 0
+                                            &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
+                                            &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
+                                            &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
+                                           >;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
+
+                        ssc1: ssc@f800c000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf800c000 0x4000>;
+                                interrupts = <39 4 4>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                status = "disabled";
+                        };
+
+                        can1: can@f8010000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf8010000 0x300>;
+                                interrupts = <41 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can1_rx_tx>;
+                        };
+
+                        tcb1: timer@f8014000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf8014000 0x100>;
+                                interrupts = <27 4 0>;
+                        };
+
+                        adc0: adc@f8018000 {
+                                compatible = "atmel,at91sam9260-adc";
+                                reg = <0xf8018000 0x100>;
+                                interrupts = <29 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_adtrg
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        &pinctrl_adc0_ad5
+                                        &pinctrl_adc0_ad6
+                                        &pinctrl_adc0_ad7
+                                        &pinctrl_adc0_ad8
+                                        &pinctrl_adc0_ad9
+                                        &pinctrl_adc0_ad10
+                                        &pinctrl_adc0_ad11
+                                        >;
+                                atmel,adc-channel-base = <0x50>;
+                                atmel,adc-channels-used = <0xfff>;
+                                atmel,adc-drdy-mask = <0x1000000>;
+                                atmel,adc-num-channels = <12>;
+                                atmel,adc-startup-time = <40>;
+                                atmel,adc-status-register = <0x30>;
+                                atmel,adc-trigger-register = <0xc0>;
+                                atmel,adc-use-external;
+                                atmel,adc-vref = <3000>;
+                                atmel,adc-res = <10 12>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                status = "disabled";
+
+                                trigger@0 {
+                                        trigger-name = "external-rising";
+                                        trigger-value = <0x1>;
+                                        trigger-external;
+                                };
+                                trigger@1 {
+                                        trigger-name = "external-falling";
+                                        trigger-value = <0x2>;
+                                        trigger-external;
+                                };
+                                trigger@2 {
+                                        trigger-name = "external-any";
+                                        trigger-value = <0x3>;
+                                        trigger-external;
+                                };
+                                trigger@3 {
+                                        trigger-name = "continuous";
+                                        trigger-value = <0x6>;
+                                };
+                        };
+
+                        tsadcc: tsadcc@f8018000 {
+                                compatible = "atmel,at91sam9x5-tsadcc";
+                                reg = <0xf8018000 0x4000>;
+                                interrupts = <29 4 5>;
+                                atmel,tsadcc_clock = <300000>;
+                                atmel,filtering_average = <0x03>;
+                                atmel,pendet_debounce = <0x08>;
+                                atmel,pendet_sensitivity = <0x02>;
+                                atmel,ts_sample_hold_time = <0x0a>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@f801c000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf801c000 0x4000>;
+                                interrupts = <20 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        usart2: serial@f8020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8020000 0x100>;
+                                interrupts = <14 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                status = "disabled";
+                        };
+
+                        usart3: serial@f8024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8024000 0x100>;
+                                interrupts = <15 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
+                                status = "disabled";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xf802c000 0x100>;
+                                interrupts = <35 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb1_rmii>;
+                                status = "disabled";
+                        };
+
+                        sha@f8034000 {
+                                compatible = "atmel,sam9g46-sha";
+                                reg = <0xf8034000 0x100>;
+                                interrupts = <42 4 0>;
+                        };
+
+                        aes@f8038000 {
+                                compatible = "atmel,sam9g46-aes";
+                                reg = <0xf8038000 0x100>;
+                                interrupts = <43 4 0>;
+                        };
+
+                        tdes@f803c000 {
+                                compatible = "atmel,sam9g46-tdes";
+                                reg = <0xf803c000 0x100>;
+                                interrupts = <44 4 0>;
+                        };
+
+                        dma0: dma-controller@ffffe600 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffe600 0x200>;
+                                interrupts = <30 4 0>;
+                                #dma-cells = <1>;
+                        };
+
+                        dma1: dma-controller@ffffe800 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffe800 0x200>;
+                                interrupts = <31 4 0>;
+                                #dma-cells = <1>;
+                        };
+
+                        ramc0: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9g45-ddramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <2 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
+                                status = "disabled";
+                        };
+
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <3>;
+                                compatible = "atmel,sama5d3-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <47>;
+                        };
+
+                        pinctrl@fffff200 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                                ranges = <0xfffff200 0xfffff200 0xa00>;
+                                atmel,mux-mask = <
+                                        /*   A          B          C  */
+                                        0xffffffff 0xc0fc0000 0xc0ff0000        /* pioA */
+                                        0xffffffff 0x0ff8ffff 0x00000000        /* pioB */
+                                        0xffffffff 0xbc00f1ff 0x7c00fc00        /* pioC */
+                                        0xffffffff 0xc001c0e0 0x0001c1e0        /* pioD */
+                                        0xffffffff 0xbf9f8000 0x18000000        /* pioE */
+                                        >;
+
+                                /* shared pinctrl settings */
+                                adc0 {
+                                        pinctrl_adc0_adtrg: adc0_adtrg {
+                                                atmel,pins =
+                                                        <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
+                                        };
+                                        pinctrl_adc0_ad0: adc0_ad0 {
+                                                atmel,pins =
+                                                        <3 20 0x1 0x0>; /* PD20 periph A AD0 */
+                                        };
+                                        pinctrl_adc0_ad1: adc0_ad1 {
+                                                atmel,pins =
+                                                        <3 21 0x1 0x0>; /* PD21 periph A AD1 */
+                                        };
+                                        pinctrl_adc0_ad2: adc0_ad2 {
+                                                atmel,pins =
+                                                        <3 22 0x1 0x0>; /* PD22 periph A AD2 */
+                                        };
+                                        pinctrl_adc0_ad3: adc0_ad3 {
+                                                atmel,pins =
+                                                        <3 23 0x1 0x0>; /* PD23 periph A AD3 */
+                                        };
+                                        pinctrl_adc0_ad4: adc0_ad4 {
+                                                atmel,pins =
+                                                        <3 24 0x1 0x0>; /* PD24 periph A AD4 */
+                                        };
+                                        pinctrl_adc0_ad5: adc0_ad5 {
+                                                atmel,pins =
+                                                        <3 25 0x1 0x0>; /* PD25 periph A AD5 */
+                                        };
+                                        pinctrl_adc0_ad6: adc0_ad6 {
+                                                atmel,pins =
+                                                        <3 26 0x1 0x0>; /* PD26 periph A AD6 */
+                                        };
+                                        pinctrl_adc0_ad7: adc0_ad7 {
+                                                atmel,pins =
+                                                        <3 27 0x1 0x0>; /* PD27 periph A AD7 */
+                                        };
+                                        pinctrl_adc0_ad8: adc0_ad8 {
+                                                atmel,pins =
+                                                        <3 28 0x1 0x0>; /* PD28 periph A AD8 */
+                                        };
+                                        pinctrl_adc0_ad9: adc0_ad9 {
+                                                atmel,pins =
+                                                        <3 29 0x1 0x0>; /* PD29 periph A AD9 */
+                                        };
+                                        pinctrl_adc0_ad10: adc0_ad10 {
+                                                atmel,pins =
+                                                        <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
+                                        };
+                                        pinctrl_adc0_ad11: adc0_ad11 {
+                                                atmel,pins =
+                                                        <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
+                                        };
+                                };
+
+                                can0 {
+                                        pinctrl_can0_rx_tx: can0_rx_tx {
+                                                atmel,pins =
+                                                        <3 14 0x3 0x0   /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+                                                         3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+                                        };
+                                };
+
+                                can1 {
+                                        pinctrl_can1_rx_tx: can1_rx_tx {
+                                                atmel,pins =
+                                                        <1 14 0x2 0x0   /* PB14 periph B RX, conflicts with GCRS */
+                                                         1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
+                                        };
+                                };
+
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <1 30 0x1 0x0   /* PB30 periph A */
+                                                         1 31 0x1 0x1>; /* PB31 periph A with pullup */
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <0 30 0x1 0x0   /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
+                                                         0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <2 26 0x2 0x0   /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
+                                                         2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
+                                        };
+                                };
+
+                                isi {
+                                        pinctrl_isi: isi-0 {
+                                                atmel,pins =
+                                                        <0 16 0x3 0x0   /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
+                                                         0 17 0x3 0x0   /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
+                                                         0 18 0x3 0x0   /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
+                                                         0 19 0x3 0x0   /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
+                                                         0 20 0x3 0x0   /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
+                                                         0 21 0x3 0x0   /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
+                                                         0 22 0x3 0x0   /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
+                                                         0 23 0x3 0x0   /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
+                                                         2 30 0x3 0x0   /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
+                                                         0 31 0x3 0x0   /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
+                                                         0 30 0x3 0x0   /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
+                                                         2 29 0x3 0x0   /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
+                                                         2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
+                                        };
+                                        pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
+                                                atmel,pins =
+                                                        <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
+                                        };
+                                };
+
+                                lcd {
+                                        pinctrl_lcd: lcd-0 {
+                                                atmel,pins =
+                                                        <0 24 0x1 0x0   /* PA24 periph A LCDPWM */
+                                                         0 26 0x1 0x0   /* PA26 periph A LCDVSYNC */
+                                                         0 27 0x1 0x0   /* PA27 periph A LCDHSYNC */
+                                                         0 25 0x1 0x0   /* PA25 periph A LCDDISP */
+                                                         0 29 0x1 0x0   /* PA29 periph A LCDDEN */
+                                                         0 28 0x1 0x0   /* PA28 periph A LCDPCK */
+                                                         0 0 0x1 0x0    /* PA0 periph A LCDD0 pin */
+                                                         0 1 0x1 0x0    /* PA1 periph A LCDD1 pin */
+                                                         0 2 0x1 0x0    /* PA2 periph A LCDD2 pin */
+                                                         0 3 0x1 0x0    /* PA3 periph A LCDD3 pin */
+                                                         0 4 0x1 0x0    /* PA4 periph A LCDD4 pin */
+                                                         0 5 0x1 0x0    /* PA5 periph A LCDD5 pin */
+                                                         0 6 0x1 0x0    /* PA6 periph A LCDD6 pin */
+                                                         0 7 0x1 0x0    /* PA7 periph A LCDD7 pin */
+                                                         0 8 0x1 0x0    /* PA8 periph A LCDD8 pin */
+                                                         0 9 0x1 0x0    /* PA9 periph A LCDD9 pin */
+                                                         0 10 0x1 0x0   /* PA10 periph A LCDD10 pin */
+                                                         0 11 0x1 0x0   /* PA11 periph A LCDD11 pin */
+                                                         0 12 0x1 0x0   /* PA12 periph A LCDD12 pin */
+                                                         0 13 0x1 0x0   /* PA13 periph A LCDD13 pin */
+                                                         0 14 0x1 0x0   /* PA14 periph A LCDD14 pin */
+                                                         0 15 0x1 0x0   /* PA15 periph A LCDD15 pin */
+                                                         2 14 0x3 0x0   /* PC14 periph C LCDD16 pin */
+                                                         2 13 0x3 0x0   /* PC13 periph C LCDD17 pin */
+                                                         2 12 0x3 0x0   /* PC12 periph C LCDD18 pin */
+                                                         2 11 0x3 0x0   /* PC11 periph C LCDD19 pin */
+                                                         2 10 0x3 0x0   /* PC10 periph C LCDD20 pin */
+                                                         2 15 0x3 0x0   /* PC15 periph C LCDD21 pin */
+                                                         4 27 0x3 0x0   /* PE27 periph C LCDD22 pin */
+                                                         4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
+                                        };
+                                };
+
+                                macb0 {
+                                        pinctrl_macb0_data_rgmii: macb0_data_rgmii {
+                                                atmel,pins =
+                                                        <1 0 0x1 0x0    /* PB0 periph A GTX0, conflicts with PWMH0 */
+                                                         1 1 0x1 0x0    /* PB1 periph A GTX1, conflicts with PWML0 */
+                                                         1 2 0x1 0x0    /* PB2 periph A GTX2, conflicts with TK1 */
+                                                         1 3 0x1 0x0    /* PB3 periph A GTX3, conflicts with TF1 */
+                                                         1 4 0x1 0x0    /* PB4 periph A GRX0, conflicts with PWMH1 */
+                                                         1 5 0x1 0x0    /* PB5 periph A GRX1, conflicts with PWML1 */
+                                                         1 6 0x1 0x0    /* PB6 periph A GRX2, conflicts with TD1 */
+                                                         1 7 0x1 0x0>;  /* PB7 periph A GRX3, conflicts with RK1 */
+                                        };
+                                        pinctrl_macb0_data_gmii: macb0_data_gmii {
+                                                atmel,pins =
+                                                        <1 19 0x2 0x0   /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+                                                         1 20 0x2 0x0   /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+                                                         1 21 0x2 0x0   /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+                                                         1 22 0x2 0x0   /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+                                                         1 23 0x2 0x0   /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+                                                         1 24 0x2 0x0   /* PB24 periph B GRX5, conflicts with MCI1_CK */
+                                                         1 25 0x2 0x0   /* PB25 periph B GRX6, conflicts with SCK1 */
+                                                         1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
+                                        };
+                                        pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
+                                                atmel,pins =
+                                                        <1 8 0x1 0x0    /* PB8 periph A GTXCK, conflicts with PWMH2 */
+                                                         1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         1 18 0x1 0x0>; /* PB18 periph A G125CK */
+                                        };
+                                        pinctrl_macb0_signal_gmii: macb0_signal_gmii {
+                                                atmel,pins =
+                                                        <1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         1 10 0x1 0x0   /* PB10 periph A GTXER, conflicts with RF1 */
+                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         1 12 0x1 0x0   /* PB12 periph A GRXDV, conflicts with PWMH3 */
+                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         1 14 0x1 0x0   /* PB14 periph A GCRS, conflicts with CANRX1 */
+                                                         1 15 0x1 0x0   /* PB15 periph A GCOL, conflicts with CANTX1 */
+                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         1 27 0x2 0x0>; /* PB27 periph B G125CKO */
+                                        };
+
+                                };
+
+                                macb1 {
+                                        pinctrl_macb1_rmii: macb1_rmii-0 {
+                                                atmel,pins =
+                                                        <2 0 0x1 0x0    /* PC0 periph A ETX0, conflicts with TIOA3 */
+                                                         2 1 0x1 0x0    /* PC1 periph A ETX1, conflicts with TIOB3 */
+                                                         2 2 0x1 0x0    /* PC2 periph A ERX0, conflicts with TCLK3 */
+                                                         2 3 0x1 0x0    /* PC3 periph A ERX1, conflicts with TIOA4 */
+                                                         2 4 0x1 0x0    /* PC4 periph A ETXEN, conflicts with TIOB4 */
+                                                         2 5 0x1 0x0    /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+                                                         2 6 0x1 0x0    /* PC6 periph A ERXER, conflicts with TIOA5 */
+                                                         2 7 0x1 0x0    /* PC7 periph A EREFCK, conflicts with TIOB5 */
+                                                         2 8 0x1 0x0    /* PC8 periph A EMDC, conflicts with TCLK5 */
+                                                         2 9 0x1 0x0>;  /* PC9 periph A EMDIO  */
+                                        };
+                                };
+
+                                mmc0 {
+                                        pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <3 9 0x1 0x0    /* PD9 periph A MCI0_CK */
+                                                         3 0 0x1 0x1    /* PD0 periph A MCI0_CDA with pullup */
+                                                         3 1 0x1 0x1>;  /* PD1 periph A MCI0_DA0 with pullup */
+                                        };
+                                        pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
+                                                atmel,pins =
+                                                        <3 2 0x1 0x1    /* PD2 periph A MCI0_DA1 with pullup */
+                                                         3 3 0x1 0x1    /* PD3 periph A MCI0_DA2 with pullup */
+                                                         3 4 0x1 0x1>;  /* PD4 periph A MCI0_DA3 with pullup */
+                                        };
+                                        pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
+                                                atmel,pins =
+                                                        <3 5 0x1 0x1    /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
+                                                         3 6 0x1 0x1    /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
+                                                         3 7 0x1 0x1    /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
+                                                         3 8 0x1 0x1>;  /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
+                                        };
+                                };
+
+                                mmc1 {
+                                        pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <1 24 0x1 0x0   /* PB24 periph A MCI1_CK, conflicts with GRX5 */
+                                                         1 19 0x1 0x1   /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
+                                                         1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
+                                        };
+                                        pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
+                                                atmel,pins =
+                                                        <1 21 0x1 0x1   /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
+                                                         1 22 0x1 0x1   /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
+                                                         1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
+                                        };
+                                };
+
+                                mmc2 {
+                                        pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <2 15 0x1 0x0   /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+                                                         2 10 0x1 0x1   /* PC10 periph A MCI2_CDA with pullup */
+                                                         2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
+                                        };
+                                        pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
+                                                atmel,pins =
+                                                        <2 12 0x1 0x0   /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+                                                         2 13 0x1 0x0   /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+                                                         2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+                                        };
+                                };
+
+                                nand0 {
+                                        pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
+                                                atmel,pins =
+                                                        <4 21 0x1 0x1   /* PE21 periph A with pullup */
+                                                         4 22 0x1 0x1>; /* PE22 periph A with pullup */
+                                        };
+                                };
+
+                                pioA: gpio@fffff200 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff200 0x100>;
+                                        interrupts = <6 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioB: gpio@fffff400 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x100>;
+                                        interrupts = <7 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioC: gpio@fffff600 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x100>;
+                                        interrupts = <8 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioD: gpio@fffff800 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x100>;
+                                        interrupts = <9 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioE: gpio@fffffa00 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x100>;
+                                        interrupts = <10 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <3 10 0x1 0x0   /* PD10 periph A SPI0_MISO pin */
+                                                         3 11 0x1 0x0   /* PD11 periph A SPI0_MOSI pin */
+                                                         3 12 0x1 0x0   /* PD12 periph A SPI0_SPCK pin */
+                                                         3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <2 22 0x1 0x0   /* PC22 periph A SPI1_MISO pin */
+                                                         2 23 0x1 0x0   /* PC23 periph A SPI1_MOSI pin */
+                                                         2 24 0x1 0x0   /* PC24 periph A SPI1_SPCK pin */
+                                                         2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
+                                        };
+                                };
+
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx {
+                                                atmel,pins =
+                                                        <2 16 0x1 0x0   /* PC16 periph A TK0 */
+                                                         2 17 0x1 0x0   /* PC17 periph A TF0 */
+                                                         2 18 0x1 0x0>; /* PC18 periph A TD0 */
+                                        };
+
+                                        pinctrl_ssc0_rx: ssc0_rx {
+                                                atmel,pins =
+                                                        <2 19 0x1 0x0   /* PC19 periph A RK0 */
+                                                         2 20 0x1 0x0   /* PC20 periph A RF0 */
+                                                         2 21 0x1 0x0>; /* PC21 periph A RD0 */
+                                        };
+                                };
+
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx {
+                                                atmel,pins =
+                                                        <1 2 0x2 0x0    /* PB2 periph B TK1, conflicts with GTX2 */
+                                                         1 3 0x2 0x0    /* PB3 periph B TF1, conflicts with GTX3 */
+                                                         1 6 0x2 0x0>;  /* PB6 periph B TD1, conflicts with TD1 */
+                                        };
+
+                                        pinctrl_ssc1_rx: ssc1_rx {
+                                                atmel,pins =
+                                                        <1 7 0x2 0x0    /* PB7 periph B RK1, conflicts with EREFCK */
+                                                         1 10 0x2 0x0   /* PB10 periph B RF1, conflicts with GTXER */
+                                                         1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
+                                        };
+                                };
+
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <2 29 0x1 0x0   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+                                                         2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <0 30 0x2 0x0   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+                                                         0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+                                        };
+                                };
+
+                                usart0 {
+                                        pinctrl_usart0: usart0-0 {
+                                                atmel,pins =
+                                                        <3 17 0x1 0x0   /* PD17 periph A */
+                                                         3 18 0x1 0x1>; /* PD18 periph A with pullup */
+                                        };
+
+                                        pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
+                                                atmel,pins =
+                                                        <3 15 0x1 0x0   /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
+                                                         3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
+                                        };
+                                };
+
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <1 28 0x1 0x0   /* PB28 periph A */
+                                                         1 29 0x1 0x1>; /* PB29 periph A with pullup */
+                                        };
+
+                                        pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
+                                                atmel,pins =
+                                                        <1 26 0x1 0x0   /* PB26 periph A, conflicts with GRX7 */
+                                                         1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
+                                        };
+                                };
+
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <4 25 0x2 0x0   /* PE25 periph B, conflicts with A25 */
+                                                         4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
+                                        };
+
+                                        pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
+                                                atmel,pins =
+                                                        <4 23 0x2 0x0   /* PE23 periph B, conflicts with A23 */
+                                                         4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
+                                        };
+                                };
+
+                                usart3 {
+                                        pinctrl_usart3: usart3-0 {
+                                                atmel,pins =
+                                                        <4 18 0x2 0x0   /* PE18 periph B, conflicts with A18 */
+                                                         4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
+                                        };
+
+                                        pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
+                                                atmel,pins =
+                                                        <4 16 0x2 0x0   /* PE16 periph B, conflicts with A16 */
+                                                         4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
+                                        };
+                                };
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x120>;
+                        };
+
+                        rstc@fffffe00 {
+                                compatible = "atmel,at91sam9g45-rstc";
+                                reg = <0xfffffe00 0x10>;
+                        };
+
+                        pit: timer@fffffe30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffe30 0xf>;
+                                interrupts = <3 4 5>;
+                        };
+
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
+
+                        rtc@fffffeb0 {
+                                compatible = "atmel,at91rm9200-rtc";
+                                reg = <0xfffffeb0 0x30>;
+                                interrupts = <1 4 7>;
+                        };
+                };
+
+                usb0: gadget@00500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "atmel,at91sam9rl-udc";
+                        reg = <0x00500000 0x100000
+                               0xf8030000 0x4000>;
+                        interrupts = <33 4 2>;
+                        status = "disabled";
+
+                        ep0 {
+                                reg = <0>;
+                                atmel,fifo-size = <64>;
+                                atmel,nb-banks = <1>;
+                        };
+
+                        ep1 {
+                                reg = <1>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep2 {
+                                reg = <2>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep3 {
+                                reg = <3>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep4 {
+                                reg = <4>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep5 {
+                                reg = <5>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep6 {
+                                reg = <6>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep7 {
+                                reg = <7>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep8 {
+                                reg = <8>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep9 {
+                                reg = <9>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep10 {
+                                reg = <10>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep11 {
+                                reg = <11>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep12 {
+                                reg = <12>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep13 {
+                                reg = <13>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep14 {
+                                reg = <14>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep15 {
+                                reg = <15>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+                };
+
+                usb1: ohci@00600000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00600000 0x100000>;
+                        interrupts = <32 4 2>;
+                        status = "disabled";
+                };
+
+                usb2: ehci@00700000 {
+                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                        reg = <0x00700000 0x100000>;
+                        interrupts = <32 4 2>;
+                        status = "disabled";
+                };
+
+                nand0: nand@60000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = < 0x60000000 0x01000000   /* EBI CS3 */
+                                0xffffc070 0x00000490   /* SMC PMECC regs */
+                                0xffffc500 0x00000100   /* SMC PMECC Error Location regs */
+                                0x00100000 0x00100000   /* ROM code */
+                                0x70000000 0x10000000   /* NFC Command Registers */
+                                0xffffc000 0x00000070   /* NFC HSMC regs */
+                                0x00200000 0x00100000   /* NFC SRAM banks */
+                                >;
+                        interrupts = <5 4 6>;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand0_ale_cle>;
+                        atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
new file mode 100644
index 000000000000..fa5d216f1db7
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -0,0 +1,51 @@
+/*
+ * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D31-EK";
+        compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                d3 {
+                        label = "d3";
+                        gpios = <&pioE 24 0>;
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
new file mode 100644
index 000000000000..c38c9433d7a5
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -0,0 +1,44 @@
+/*
+ * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D33-EK";
+        compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
new file mode 100644
index 000000000000..d2739f8d7ae9
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -0,0 +1,61 @@
+/*
+ * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D34-EK";
+        compatible = "atmel,sama5d34ek", "atmel,sama5ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+
+                                24c256@50 {
+                                        compatible = "24c256";
+                                        reg = <0x50>;
+                                        pagesize = <64>;
+                                };
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                d3 {
+                        label = "d3";
+                        gpios = <&pioE 24 0>;
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
new file mode 100644
index 000000000000..a488fc4e9777
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -0,0 +1,56 @@
+/*
+ * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+
+/ {
+        model = "Atmel SAMA5D35-EK";
+        compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+
+                        isi: isi@f0034000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pb_user1 {
+                        label = "pb_user1";
+                        gpios = <&pioE 27 0>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
new file mode 100644
index 000000000000..1f8ed404626c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -0,0 +1,91 @@
+/*
+ * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "sama5d3.dtsi"
+
+/ {
+        compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
+        };
+
+        memory {
+                reg = <0x20000000 0x20000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        macb0: ethernet@f0028000 {
+                                phy-mode = "rgmii";
+                        };
+                };
+
+                nand0: nand@60000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;
+                        atmel,pmecc-cap = <4>;
+                        atmel,pmecc-sector-size = <512>;
+                        atmel,has-nfc;
+                        atmel,use-nfc-sram;
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                d2 {
+                        label = "d2";
+                        gpios = <&pioE 25 1>;   /* PE25, conflicts with A25, RXD2 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
new file mode 100644
index 000000000000..4b8830eb2060
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -0,0 +1,42 @@
+/*
+ * sama5d3dm.dtsi - Device Tree file for SAMA5 display module
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        ahb {
+                apb {
+                        i2c1: i2c@f0018000 {
+                                qt1070: keyboard@1b {
+                                        compatible = "qt1070";
+                                        reg = <0x1b>;
+                                        interrupt-parent = <&pioE>;
+                                        interrupts = <31 0x0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_qt1070_irq>;
+                                };
+                        };
+
+                        adc0: adc@f8018000 {
+                                status = "disabled";
+                        };
+
+                        tsadcc: tsadcc@f8018000 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_qt1070_irq: qt1070_irq {
+                                                atmel,pins =
+                                                        <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
new file mode 100644
index 000000000000..661d7ca9c309
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -0,0 +1,166 @@
+/*
+ * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "sama5d3xcm.dtsi"
+
+/ {
+        compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 17 0>;
+                                };
+                        };
+
+                        spi0: spi@f0004000 {
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
+
+                        /*
+                         * i2c0 conflicts with ISI:
+                         * disable it to allow the use of ISI
+                         * can not enable audio when i2c0 disabled
+                         */
+                        i2c0: i2c@f0014000 {
+                                wm8904: wm8904@1a {
+                                        compatible = "wm8904";
+                                        reg = <0x1a>;
+                                };
+                        };
+
+                        usart1: serial@f0020000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
+                                status = "okay";
+                        };
+
+                        isi: isi@f0034000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>;
+                        };
+
+                        mmc1: mmc@f8000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 18 0>;
+                                };
+                        };
+
+                        adc0: adc@f8018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_adtrg
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        >;
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                        };
+
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_mmc0_cd: mmc0_cd {
+                                                atmel,pins =
+                                                        <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
+                                        };
+
+                                        pinctrl_mmc1_cd: mmc1_cd {
+                                                atmel,pins =
+                                                        <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
+                                        };
+
+                                        pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
+                                                atmel,pins =
+                                                        <3 30 0x2 0x0>; /* PD30 periph B */
+                                        };
+
+                                        pinctrl_isi_reset: isi_reset-0 {
+                                                atmel,pins =
+                                                        <4 24 0x0 0x0>;   /* PE24 gpio */
+                                        };
+
+                                        pinctrl_isi_power: isi_power-0 {
+                                                atmel,pins =
+                                                        <4 29 0x0 0x0>; /* PE29 gpio */
+                                        };
+
+                                        pinctrl_usba_vbus: usba_vbus {
+                                                atmel,pins =
+                                                        <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */
+                                        };
+                                };
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: gadget@00500000 {
+                        atmel,vbus-gpio = <&pioD 29 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usba_vbus>;
+                        status = "okay";
+                };
+
+                usb1: ohci@00600000 {
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <&pioD 25 0
+                                           &pioD 26 1
+                                           &pioD 27 1
+                                          >;
+                        status = "okay";
+                };
+
+                usb2: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+
+        sound {
+                compatible = "atmel,sama5d3ek-wm8904";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
+
+                atmel,model = "wm8904 @ SAMA5D3EK";
+                atmel,audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "IN2L", "Line In Jack",
+                        "IN2R", "Line In Jack",
+                        "IN1L", "Mic";
+
+                atmel,ssc-controller = <&ssc0>;
+                atmel,audio-codec = <&wm8904>;
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 7e8769bd5977..16a6e13e08b4 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -81,6 +81,163 @@
                         };
                 };
 
+                clkmgr@ffd04000 {
+                                compatible = "altr,clk-mgr";
+                                reg = <0xffd04000 0x1000>;
+
+                                clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        osc: osc1 {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                        };
+
+                                        main_pll: main_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc>;
+                                                reg = <0x40>;
+
+                                                mpuclk: mpuclk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        fixed-divider = <2>;
+                                                        reg = <0x48>;
+                                                };
+
+                                                mainclk: mainclk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        fixed-divider = <4>;
+                                                        reg = <0x4C>;
+                                                };
+
+                                                dbg_base_clk: dbg_base_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        fixed-divider = <4>;
+                                                        reg = <0x50>;
+                                                };
+
+                                                main_qspi_clk: main_qspi_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        reg = <0x54>;
+                                                };
+
+                                                main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        reg = <0x58>;
+                                                };
+
+                                                cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        reg = <0x5C>;
+                                                };
+                                        };
+
+                                        periph_pll: periph_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc>;
+                                                reg = <0x80>;
+
+                                                emac0_clk: emac0_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x88>;
+                                                };
+
+                                                emac1_clk: emac1_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x8C>;
+                                                };
+
+                                                per_qspi_clk: per_qsi_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x90>;
+                                                };
+
+                                                per_nand_mmc_clk: per_nand_mmc_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x94>;
+                                                };
+
+                                                per_base_clk: per_base_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x98>;
+                                                };
+
+                                                s2f_usr1_clk: s2f_usr1_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x9C>;
+                                                };
+                                        };
+
+                                        sdram_pll: sdram_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc>;
+                                                reg = <0xC0>;
+
+                                                ddr_dqs_clk: ddr_dqs_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xC8>;
+                                                };
+
+                                                ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xCC>;
+                                                };
+
+                                                ddr_dq_clk: ddr_dq_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xD0>;
+                                                };
+
+                                                s2f_usr2_clk: s2f_usr2_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xD4>;
+                                                };
+                                        };
+                                };
+                        };
+
                 gmac0: stmmac@ff700000 {
                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
                         reg = <0xff700000 0x2000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 3ae8a83a0875..2495958f1016 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -33,6 +33,14 @@
         };
 
         soc {
+                clkmgr@ffd04000 {
+                        clocks {
+                                osc1 {
+                                        clock-frequency = <25000000>;
+                                };
+                        };
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <100000000>;
                 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 1036eba40bbf..0bf035d607f0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -33,6 +33,14 @@
         };
 
         soc {
+                clkmgr@ffd04000 {
+                        clocks {
+                                osc1 {
+                                        clock-frequency = <10000000>;
+                                };
+                        };
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <7000000>;
                 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a30aca62658a..6ebc1b704190 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -18,4 +18,17 @@
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 9bea8f57aa47..5deb8692b350 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -18,4 +18,17 @@
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index e4ddeddcd437..c0b527d15fda 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -101,6 +101,8 @@
         pmc {
                 compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 261>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         iommu {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index cb73e62d61a9..4e3afdef28a8 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -447,6 +447,19 @@
                 cd-gpios = <&gpio 23 1>; /* gpio PC7 */
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
                                  "nvidia,tegra-audio-wm9712";
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 1f79c0debb05..ae9d5a20834e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -451,6 +451,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 9db36da8e023..fd60940e4063 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -447,6 +447,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 715a8b8dd9cd..4ee700a33ca5 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -595,6 +595,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 6e9d91fc6195..c19025725918 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -471,6 +471,19 @@
                 status = "okay";
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
 
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 98f3e44f2a51..a9f3f06580f5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -330,6 +330,19 @@
                 bus-width = <4>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         poweroff {
                 compatible = "gpio-poweroff";
                 gpios = <&gpio 191 1>; /* gpio PX7, active low */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 4aef56f2d96a..f544806e9618 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -531,6 +531,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 5762188c60ad..258cf945f515 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -520,6 +520,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <20>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index ad64c8cc9da7..fc7febc2b386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -418,6 +418,8 @@
         pmc {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 110>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 0a2cd24df853..6248b2445b32 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -268,6 +268,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 3e2d21018a5b..65bf2b63174e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -322,6 +322,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 9491edf1a067..9fe7a92b4c85 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -427,6 +427,8 @@
         pmc {
                 compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller {
diff --git a/arch/arm/boot/dts/tps6507x.dtsi b/arch/arm/boot/dts/tps6507x.dtsi
new file mode 100644
index 000000000000..4c326e591e5a
--- /dev/null
+++ b/arch/arm/boot/dts/tps6507x.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65070.pdf
+ */
+
+&tps {
+        compatible = "ti,tps6507x";
+
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdcdc1_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "VDCDC1";
+                };
+
+                vdcdc2_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "VDCDC2";
+                };
+
+                vdcdc3_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "VDCDC3";
+                };
+
+                ldo1_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "LDO1";
+                };
+
+                ldo2_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "LDO2";
+                };
+
+        };
+};
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
new file mode 100644
index 000000000000..dab5a7dfadc6
--- /dev/null
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -0,0 +1,95 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A73A4=y
+CONFIG_MACH_APE6EVM=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_NR_CPUS=8
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+# CONFIG_HW_PERF_EVENTS is not set
+# CONFIG_COMPACTION is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_NETFILTER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER_USER_HELPER is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=12
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_GPIO_SH_PFC=y
+CONFIG_GPIOLIB=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 0b98100d2ae7..0f2d80da7378 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -20,15 +20,19 @@ CONFIG_ARCH_R8A7740=y
 CONFIG_MACH_ARMADILLO800EVA=y
 # CONFIG_SH_TIMER_TMU is not set
 CONFIG_ARM_THUMB=y
-CONFIG_CPU_BPREDICT_DISABLE=y
 CONFIG_CACHE_L2X0=y
 CONFIG_ARM_ERRATA_430973=y
 CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
+CONFIG_PL310_ERRATA_588369=y
 CONFIG_ARM_ERRATA_720789=y
+CONFIG_PL310_ERRATA_727915=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_751472=y
+CONFIG_PL310_ERRATA_753970=y
 CONFIG_ARM_ERRATA_754322=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_ARM_ERRATA_775420=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_FORCE_MAX_ZONEORDER=13
@@ -37,6 +41,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_KEXEC=y
 CONFIG_VFP=y
+CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
@@ -88,6 +93,7 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index af472e4ed451..abc7c8d4631b 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -59,10 +59,13 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_TTY_PRINTK=y
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM2835=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BCM2835=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM2835=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 # CONFIG_USB_SUPPORT is not set
@@ -108,9 +111,5 @@ CONFIG_TEST_KSTRTOX=y
 CONFIG_STRICT_DEVMEM=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-# CONFIG_XZ_DEC_X86 is not set
-# CONFIG_XZ_DEC_POWERPC is not set
-# CONFIG_XZ_DEC_IA64 is not set
 # CONFIG_XZ_DEC_ARM is not set
 # CONFIG_XZ_DEC_ARMTHUMB is not set
-# CONFIG_XZ_DEC_SPARC is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 670c3b60f936..f6e585b353a4 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -33,7 +33,6 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_SCHED_MC=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_HIGHMEM=y
@@ -86,7 +85,6 @@ CONFIG_I2C_SH_MOBILE=y
 CONFIG_GPIO_PCF857X=y
 # CONFIG_HWMON is not set
 CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DUMMY=y
 CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index afa7249fac6e..398a367ffce8 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -18,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_LPC32XX=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -48,6 +48,8 @@ CONFIG_IPV6=y
 CONFIG_IPV6_PRIVACY=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
@@ -55,7 +57,6 @@ CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_MUSEUM_IDS=y
 CONFIG_MTD_NAND_SLC_LPC32XX=y
 CONFIG_MTD_NAND_MLC_LPC32XX=y
 CONFIG_BLK_DEV_LOOP=y
@@ -70,7 +71,6 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 # CONFIG_NET_VENDOR_CIRRUS is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
@@ -84,7 +84,6 @@ CONFIG_LPC_ENET=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
-CONFIG_INPUT_MATRIXKMAP=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
@@ -108,6 +107,19 @@ CONFIG_I2C_PNX=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_EM=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_MAX7300=y
+CONFIG_GPIO_MAX732X=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_SX150X=y
+CONFIG_GPIO_ADP5588=y
+CONFIG_GPIO_ADNP=y
+CONFIG_GPIO_MAX7301=y
+CONFIG_GPIO_MCP23S08=y
+CONFIG_GPIO_MC33880=y
+CONFIG_GPIO_74X164=y
 CONFIG_SENSORS_DS620=y
 CONFIG_SENSORS_MAX6639=y
 CONFIG_WATCHDOG=y
@@ -144,6 +156,7 @@ CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 7594b3aff259..9fb11895b2e2 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -75,6 +75,7 @@ CONFIG_I2C=y
 CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
 # CONFIG_MFD_SUPPORT is not set
+CONFIG_REGULATOR=y
 CONFIG_FB=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_SH_MOBILE_LCDC=y
@@ -94,6 +95,9 @@ CONFIG_USB_RENESAS_USBHS=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index afb17d630d44..494e70aeb9e1 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -49,6 +49,10 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_ATA_SFF=y
+CONFIG_ATA_BMDMA=y
+CONFIG_SATA_RCAR=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -75,6 +79,7 @@ CONFIG_I2C_RCAR=y
 CONFIG_SPI=y
 CONFIG_SPI_SH_HSPI=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_RCAR=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
@@ -88,6 +93,9 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 87924d671115..7ba48d22bcd9 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -75,7 +75,7 @@ CONFIG_REALTEK_PHY=y
 CONFIG_MICREL_PHY=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
@@ -99,6 +99,8 @@ CONFIG_SPI_MXS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_STMP3XXX_RTC_WATCHDOG=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
@@ -123,6 +125,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_PHY=y
 CONFIG_USB_MXS_PHY=y
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_MXS=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
new file mode 100644
index 000000000000..4d0dc3c16063
--- /dev/null
+++ b/arch/arm/configs/sama5_defconfig
@@ -0,0 +1,181 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_AT91=y
+CONFIG_SOC_SAM_V7=y
+CONFIG_SOC_SAMA5D3=y
+CONFIG_MACH_SAMA5_DT=y
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_CAN=y
+CONFIG_CAN_AT91=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
+# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=4
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_GPIO=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_SSB=m
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_HID_GENERIC is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_AT91=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_ATMELMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_DMADEVICES=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IIO=y
+CONFIG_AT91_ADC=y
+CONFIG_EXT2_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_DEV_ATMEL_AES=y
+CONFIG_CRYPTO_DEV_ATMEL_TDES=y
+CONFIG_CRYPTO_DEV_ATMEL_SHA=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_ITU_T=m
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index aba4881d20e5..a5f0485133cf 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
@@ -20,15 +19,14 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
+CONFIG_ARCH_TEGRA_114_SOC=y
 CONFIG_TEGRA_PCI=y
-CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
@@ -37,8 +35,8 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
@@ -108,6 +106,7 @@ CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
@@ -117,7 +116,6 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
@@ -126,6 +124,7 @@ CONFIG_SPI=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PALMAS=y
 CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
@@ -136,12 +135,17 @@ CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
 CONFIG_MFD_MAX8907=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_PALMAS=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_TPS51632=y
 CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65090=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_REGULATOR_TPS65910=y
 CONFIG_MEDIA_SUPPORT=y
@@ -187,10 +191,8 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
 CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TPS6586X=y
 CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 426270fe080d..c037aa1065b7 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -5,7 +5,6 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_U8500=y
 CONFIG_MACH_HREFV60=y
@@ -90,6 +89,8 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_LM3530=y
 CONFIG_LEDS_LP5521=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AB8500=y
 CONFIG_RTC_DRV_PL031=y
@@ -103,6 +104,7 @@ CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
 CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 440682b708f3..02802386b894 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -6,6 +6,10 @@ config HAVE_AT91_DBGU0
 config HAVE_AT91_DBGU1
         bool
 
+config AT91_PMC_UNIT
+        bool
+        default !ARCH_AT91X40
+
 config AT91_SAM9_ALT_RESET
         bool
         default !ARCH_AT91X40
@@ -14,17 +18,59 @@ config AT91_SAM9G45_RESET
         bool
         default !ARCH_AT91X40
 
+config AT91_SAM9_TIME
+        bool
+
 config SOC_AT91SAM9
         bool
+        select AT91_SAM9_TIME
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
 
+config SOC_SAMA5
+        bool
+        select AT91_SAM9_TIME
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+
 menu "Atmel AT91 System-on-Chip"
 
+choice
+
+        prompt "Core type"
+
+config SOC_SAM_V4_V5
+        bool "ARM7/ARM9"
+        help
+          Select this if you are using one of Atmel's AT91SAM9, AT91RM9200
+          or AT91X40 SoC.
+
+config SOC_SAM_V7
+        bool "Cortex A5"
+        help
+          Select this if you are using one of Atmel's SAMA5D3 SoC.
+
+endchoice
+
 comment "Atmel AT91 Processor"
 
+if SOC_SAM_V7
+config SOC_SAMA5D3
+        bool "SAMA5D3 family"
+        depends on SOC_SAM_V7
+        select SOC_SAMA5
+        select HAVE_FB_ATMEL
+        select HAVE_AT91_DBGU1
+        help
+          Select this if you are using one of Atmel's SAMA5D3 family SoC.
+          This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
+endif
+
+if SOC_SAM_V4_V5
 config SOC_AT91RM9200
         bool "AT91RM9200"
         select CPU_ARM920T
@@ -90,13 +136,10 @@ config SOC_AT91SAM9N12
         help
           Select this if you are using Atmel's AT91SAM9N12 SoC.
 
-config AT91_PMC_UNIT
-        bool
-        default !ARCH_AT91X40
-
 # ----------------------------------------------------------
 
 source arch/arm/mach-at91/Kconfig.non_dt
+endif # SOC_SAM_V4_V5
 
 comment "Generic Board Type"
 
@@ -116,6 +159,14 @@ config MACH_AT91SAM9_DT
           Select this if you want to experiment device-tree with
           an Atmel Evaluation Kit.
 
+config MACH_SAMA5_DT
+        bool "Atmel SAMA5 Evaluation Kits with device-tree support"
+        depends on SOC_SAMA5
+        select USE_OF
+        help
+          Select this if you want to experiment device-tree with
+          an Atmel Evaluation Kit.
+
 # ----------------------------------------------------------
 
 comment "AT91 Feature Selections"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 505fed961eb0..788562dccb43 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,7 +10,8 @@ obj-		:=
 obj-$(CONFIG_AT91_PMC_UNIT)     += clock.o
 obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
 obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
-obj-$(CONFIG_SOC_AT91SAM9)      += at91sam926x_time.o sam9_smc.o
+obj-$(CONFIG_AT91_SAM9_TIME)    += at91sam926x_time.o
+obj-$(CONFIG_SOC_AT91SAM9)      += sam9_smc.o
 
 # CPU-specific support
 obj-$(CONFIG_SOC_AT91RM9200)    += at91rm9200.o at91rm9200_time.o
@@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9G45)	+= at91sam9g45.o
 obj-$(CONFIG_SOC_AT91SAM9N12)   += at91sam9n12.o
 obj-$(CONFIG_SOC_AT91SAM9X5)    += at91sam9x5.o
 obj-$(CONFIG_SOC_AT91SAM9RL)    += at91sam9rl.o
+obj-$(CONFIG_SOC_SAMA5D3)       += sama5d3.o
 
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
@@ -90,6 +92,9 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
 obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
 
+# SAMA5 board with device-tree
+obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
+
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
 
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 36b05fc28816..d193a409bc45 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -385,7 +385,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0       /* Advanced Interrupt Controller (IRQ6) */
 };
 
-AT91_SOC_START(rm9200)
+AT91_SOC_START(at91rm9200)
         .map_io = at91rm9200_map_io,
         .default_irq_priority = at91rm9200_default_irq_priority,
         .ioremap_registers = at91rm9200_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 44199bc2c665..a8ce24538da6 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -397,7 +397,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9260)
+AT91_SOC_START(at91sam9260)
         .map_io = at91sam9260_map_io,
         .default_irq_priority = at91sam9260_default_irq_priority,
         .ioremap_registers = at91sam9260_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 2998a08afc2d..ac7a341bd0ff 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -337,7 +337,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9261)
+AT91_SOC_START(at91sam9261)
         .map_io = at91sam9261_map_io,
         .default_irq_priority = at91sam9261_default_irq_priority,
         .ioremap_registers = at91sam9261_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index b9fc60d1b33a..8e2d9f4a9a45 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -374,7 +374,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ1) */
 };
 
-AT91_SOC_START(sam9263)
+AT91_SOC_START(at91sam9263)
         .map_io = at91sam9263_map_io,
         .default_irq_priority = at91sam9263_default_irq_priority,
         .ioremap_registers = at91sam9263_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 2ec5efea3f03..a6c224fc9542 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -420,7 +420,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ0) */
 };
 
-AT91_SOC_START(sam9g45)
+AT91_SOC_START(at91sam9g45)
         .map_io = at91sam9g45_map_io,
         .default_irq_priority = at91sam9g45_default_irq_priority,
         .ioremap_registers = at91sam9g45_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index ccd078355eed..13cdbcd48f51 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -228,7 +228,7 @@ void __init at91sam9n12_initialize(void)
         at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
 }
 
-AT91_SOC_START(sam9n12)
+AT91_SOC_START(at91sam9n12)
         .map_io = at91sam9n12_map_io,
         .register_clocks = at91sam9n12_register_clocks,
         .init = at91sam9n12_initialize,
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index eb98704db2d9..c39600764236 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -340,7 +340,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9rl)
+AT91_SOC_START(at91sam9rl)
         .map_io = at91sam9rl_map_io,
         .default_irq_priority = at91sam9rl_default_irq_priority,
         .ioremap_registers = at91sam9rl_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index a200d8a17123..e631fec040ce 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -322,7 +322,7 @@ static void __init at91sam9x5_map_io(void)
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
 
-AT91_SOC_START(sam9x5)
+AT91_SOC_START(at91sam9x5)
         .map_io = at91sam9x5_map_io,
         .register_clocks = at91sam9x5_register_clocks,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
new file mode 100644
index 000000000000..705305e62bbc
--- /dev/null
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -0,0 +1,86 @@
+/*
+ *  Setup code for SAMA5 Evaluation Kits with Device Tree support
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/micrel_phy.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/phy.h>
+
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include "at91_aic.h"
+#include "generic.h"
+
+
+static const struct of_device_id irq_of_match[] __initconst = {
+
+        { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
+        { /*sentinel*/ }
+};
+
+static void __init at91_dt_init_irq(void)
+{
+        of_irq_init(irq_of_match);
+}
+
+static int ksz9021rn_phy_fixup(struct phy_device *phy)
+{
+        int value;
+
+#define GMII_RCCPSR     260
+#define GMII_RRDPSR     261
+#define GMII_ERCR       11
+#define GMII_ERDWR      12
+
+        /* Set delay values */
+        value = GMII_RCCPSR | 0x8000;
+        phy_write(phy, GMII_ERCR, value);
+        value = 0xF2F4;
+        phy_write(phy, GMII_ERDWR, value);
+        value = GMII_RRDPSR | 0x8000;
+        phy_write(phy, GMII_ERCR, value);
+        value = 0x2222;
+        phy_write(phy, GMII_ERDWR, value);
+
+        return 0;
+}
+
+static void __init sama5_dt_device_init(void)
+{
+        if (of_machine_is_compatible("atmel,sama5d3xcm"))
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                        ksz9021rn_phy_fixup);
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *sama5_dt_board_compat[] __initdata = {
+        "atmel,sama5",
+        NULL
+};
+
+DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
+        /* Maintainer: Atmel */
+        .init_time      = at91sam926x_pit_init,
+        .map_io         = at91_map_io,
+        .handle_irq     = at91_aic5_handle_irq,
+        .init_early     = at91_dt_initialize,
+        .init_irq       = at91_dt_init_irq,
+        .init_machine   = sama5_dt_device_init,
+        .dt_compat      = sama5_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 33361505c0cd..da841885d01c 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -54,7 +54,10 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
  */
 #define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3())
+
+#define cpu_has_1056M_plla()    (cpu_is_sama5d3())
 
 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
                                 || cpu_is_at91sam9g45() \
@@ -75,7 +78,8 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
                                 || cpu_is_at91sam9n12()))
 
 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3())
 
 /* USB host HS & FS */
 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
@@ -83,18 +87,22 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
 /* USB device FS only */
 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5()))
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3()))
 
 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -210,10 +218,26 @@ struct clk mck = {
 
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
-        if (is_on)
-                at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
-        else
-                at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
+        u32 regval = 0;
+
+        /*
+         * With sama5d3 devices, we are managing clock division so we have to
+         * use the Peripheral Control Register introduced from at91sam9x5
+         * devices.
+         */
+        if (cpu_is_sama5d3()) {
+                regval |= AT91_PMC_PCR_CMD; /* write command */
+                regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
+                regval |= AT91_PMC_PCR_DIV(clk->div);
+                if (is_on)
+                        regval |= AT91_PMC_PCR_EN; /* enable clock */
+                at91_pmc_write(AT91_PMC_PCR, regval);
+        } else {
+                if (is_on)
+                        at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
+                else
+                        at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
+        }
 }
 
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -443,14 +467,18 @@ static void __init init_programmable_clock(struct clk *clk)
 
 static int at91_clk_show(struct seq_file *s, void *unused)
 {
-        u32             scsr, pcsr, uckr = 0, sr;
+        u32             scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
         struct clk      *clk;
 
         scsr = at91_pmc_read(AT91_PMC_SCSR);
         pcsr = at91_pmc_read(AT91_PMC_PCSR);
+        if (cpu_is_sama5d3())
+                pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
         sr = at91_pmc_read(AT91_PMC_SR);
         seq_printf(s, "SCSR = %8x\n", scsr);
         seq_printf(s, "PCSR = %8x\n", pcsr);
+        if (cpu_is_sama5d3())
+                seq_printf(s, "PCSR1 = %8x\n", pcsr1);
         seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
         seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
         seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
@@ -470,20 +498,30 @@ static int at91_clk_show(struct seq_file *s, void *unused)
         list_for_each_entry(clk, &clocks, node) {
                 char    *state;
 
-                if (clk->mode == pmc_sys_mode)
+                if (clk->mode == pmc_sys_mode) {
                         state = (scsr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->mode == pmc_periph_mode)
-                        state = (pcsr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->mode == pmc_uckr_mode)
+                } else if (clk->mode == pmc_periph_mode) {
+                        if (cpu_is_sama5d3()) {
+                                u32 pmc_mask = 1 << (clk->pid % 32);
+
+                                if (clk->pid > 31)
+                                        state = (pcsr1 & pmc_mask) ? "on" : "off";
+                                else
+                                        state = (pcsr & pmc_mask) ? "on" : "off";
+                        } else {
+                                state = (pcsr & clk->pmc_mask) ? "on" : "off";
+                        }
+                } else if (clk->mode == pmc_uckr_mode) {
                         state = (uckr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->pmc_mask)
+                } else if (clk->pmc_mask) {
                         state = (sr & clk->pmc_mask) ? "on" : "off";
-                else if (clk == &clk32k || clk == &main_clk)
+                } else if (clk == &clk32k || clk == &main_clk) {
                         state = "on";
-                else
+                } else {
                         state = "";
+                }
 
-                seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
+                seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
                         clk->name, clk->users, state, clk_get_rate(clk),
                         clk->parent ? clk->parent->name : "");
         }
@@ -530,6 +568,9 @@ int __init clk_register(struct clk *clk)
         if (clk_is_peripheral(clk)) {
                 if (!clk->parent)
                         clk->parent = &mck;
+                if (cpu_is_sama5d3())
+                        clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
+                                                    1 << clk->div);
                 clk->mode = pmc_periph_mode;
         }
         else if (clk_is_sys(clk)) {
@@ -555,7 +596,11 @@ static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
         unsigned mul, div;
 
         div = reg & 0xff;
-        mul = (reg >> 16) & 0x7ff;
+        if (cpu_is_sama5d3())
+                mul = AT91_PMC3_MUL_GET(reg);
+        else
+                mul = AT91_PMC_MUL_GET(reg);
+
         if (div && mul) {
                 freq /= div;
                 freq *= mul + 1;
@@ -706,12 +751,15 @@ static int __init at91_pmc_init(unsigned long main_clock)
 
         /* report if PLLA is more than mildly overclocked */
         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
-        if (cpu_has_300M_plla()) {
-                if (plla.rate_hz > 300000000)
+        if (cpu_has_1056M_plla()) {
+                if (plla.rate_hz > 1056000000)
                         pll_overclock = true;
         } else if (cpu_has_800M_plla()) {
                 if (plla.rate_hz > 800000000)
                         pll_overclock = true;
+        } else if (cpu_has_300M_plla()) {
+                if (plla.rate_hz > 300000000)
+                        pll_overclock = true;
         } else if (cpu_has_240M_plla()) {
                 if (plla.rate_hz > 240000000)
                         pll_overclock = true;
@@ -872,6 +920,7 @@ int __init at91_clock_init(unsigned long main_clock)
 static int __init at91_clock_reset(void)
 {
         unsigned long pcdr = 0;
+        unsigned long pcdr1 = 0;
         unsigned long scdr = 0;
         struct clk *clk;
 
@@ -879,8 +928,17 @@ static int __init at91_clock_reset(void)
                 if (clk->users > 0)
                         continue;
 
-                if (clk->mode == pmc_periph_mode)
-                        pcdr |= clk->pmc_mask;
+                if (clk->mode == pmc_periph_mode) {
+                        if (cpu_is_sama5d3()) {
+                                u32 pmc_mask = 1 << (clk->pid % 32);
+
+                                if (clk->pid > 31)
+                                        pcdr1 |= pmc_mask;
+                                else
+                                        pcdr |= pmc_mask;
+                        } else
+                                pcdr |= clk->pmc_mask;
+                }
 
                 if (clk->mode == pmc_sys_mode)
                         scdr |= clk->pmc_mask;
@@ -888,8 +946,9 @@ static int __init at91_clock_reset(void)
                 pr_debug("Clocks: disable unused %s\n", clk->name);
         }
 
-        at91_pmc_write(AT91_PMC_PCDR, pcdr);
         at91_pmc_write(AT91_PMC_SCDR, scdr);
+        if (cpu_is_sama5d3())
+                at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
 
         return 0;
 }
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index c2e63e47dcbe..a98a39bbd883 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -20,7 +20,9 @@ struct clk {
         const char      *name;          /* unique clock name */
         struct clk_lookup cl;
         unsigned long   rate_hz;
+        unsigned        div;            /* parent clock divider */
         struct clk      *parent;
+        unsigned        pid;            /* peripheral ID */
         u32             pmc_mask;
         void            (*mode)(struct clk *, int);
         unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index ea2c57a86ca6..31df12029c4e 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -75,6 +75,9 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
 #define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_MUL_GET(n)     ((n) >> 16 & 0x7ff)
+#define         AT91_PMC3_MUL           (0x7f  << 18)           /* PLL Multiplier [SAMA5 only] */
+#define         AT91_PMC3_MUL_GET(n)    ((n) >> 18 & 0x7f)
 #define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
 #define                 AT91_PMC_USBDIV_1               (0 << 28)
 #define                 AT91_PMC_USBDIV_2               (1 << 28)
@@ -167,11 +170,18 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
 #define         AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
 
-#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9] */
+#define AT91_PMC_PCER1          0x100                   /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
+#define AT91_PMC_PCDR1          0x104                   /* Peripheral Clock Enable Register 1 */
+#define AT91_PMC_PCSR1          0x108                   /* Peripheral Clock Enable Register 1 */
+
+#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9 and SAMA5] */
 #define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
-#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command */
-#define         AT91_PMC_PCR_DIV        (0x3  <<  16)           /* Divisor Value */
-#define         AT91_PMC_PCRDIV(n)      (((n) <<  16) & AT91_PMC_PCR_DIV)
+#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command (read=0, write=1) */
+#define         AT91_PMC_PCR_DIV(n)     ((n)  <<  16)           /* Divisor Value */
+#define                 AT91_PMC_PCR_DIV0       0x0                     /* Peripheral clock is MCK */
+#define                 AT91_PMC_PCR_DIV2       0x2                     /* Peripheral clock is MCK/2 */
+#define                 AT91_PMC_PCR_DIV4       0x4                     /* Peripheral clock is MCK/4 */
+#define                 AT91_PMC_PCR_DIV8       0x8                     /* Peripheral clock is MCK/8 */
 #define         AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index b6504c19d55c..0f3379fe645f 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -36,6 +36,8 @@
 #define ARCH_ID_AT91M40807      0x14080745
 #define ARCH_ID_AT91R40008      0x44000840
 
+#define ARCH_ID_SAMA5D3         0x8A5C07C0
+
 #define ARCH_EXID_AT91SAM9M11   0x00000001
 #define ARCH_EXID_AT91SAM9M10   0x00000002
 #define ARCH_EXID_AT91SAM9G46   0x00000003
@@ -47,6 +49,11 @@
 #define ARCH_EXID_AT91SAM9G25   0x00000003
 #define ARCH_EXID_AT91SAM9X25   0x00000004
 
+#define ARCH_EXID_SAMA5D31      0x00444300
+#define ARCH_EXID_SAMA5D33      0x00414300
+#define ARCH_EXID_SAMA5D34      0x00414301
+#define ARCH_EXID_SAMA5D35      0x00584300
+
 #define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
@@ -75,6 +82,9 @@ enum at91_soc_type {
         /* SAM9N12 */
         AT91_SOC_SAM9N12,
 
+        /* SAMA5D3 */
+        AT91_SOC_SAMA5D3,
+
         /* Unknown type */
         AT91_SOC_NONE
 };
@@ -93,6 +103,10 @@ enum at91_soc_subtype {
         AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
         AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
 
+        /* SAMA5D3 */
+        AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
+        AT91_SOC_SAMA5D35,
+
         /* Unknown subtype */
         AT91_SOC_SUBTYPE_NONE
 };
@@ -187,6 +201,12 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9n12()    (0)
 #endif
 
+#ifdef CONFIG_SOC_SAMA5D3
+#define cpu_is_sama5d3()        (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
+#else
+#define cpu_is_sama5d3()        (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
new file mode 100644
index 000000000000..6dc81ee38048
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -0,0 +1,73 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Common definitions.
+ * Based on SAMA5D3 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ              0      /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS              1      /* System Peripherals */
+#define SAMA5D3_ID_DBGU          2      /* debug Unit (usually no special interrupt line) */
+#define AT91_ID_PIT              3      /* PIT */
+#define SAMA5D3_ID_WDT           4      /* Watchdog Timer Interrupt */
+#define SAMA5D3_ID_HSMC          5      /* Static Memory Controller */
+#define SAMA5D3_ID_PIOA          6      /* PIOA */
+#define SAMA5D3_ID_PIOB          7      /* PIOB */
+#define SAMA5D3_ID_PIOC          8      /* PIOC */
+#define SAMA5D3_ID_PIOD          9      /* PIOD */
+#define SAMA5D3_ID_PIOE         10      /* PIOE */
+#define SAMA5D3_ID_SMD          11      /* SMD Soft Modem */
+#define SAMA5D3_ID_USART0       12      /* USART0 */
+#define SAMA5D3_ID_USART1       13      /* USART1 */
+#define SAMA5D3_ID_USART2       14      /* USART2 */
+#define SAMA5D3_ID_USART3       15      /* USART3 */
+#define SAMA5D3_ID_UART0        16      /* UART 0 */
+#define SAMA5D3_ID_UART1        17      /* UART 1 */
+#define SAMA5D3_ID_TWI0         18      /* Two-Wire Interface 0 */
+#define SAMA5D3_ID_TWI1         19      /* Two-Wire Interface 1 */
+#define SAMA5D3_ID_TWI2         20      /* Two-Wire Interface 2 */
+#define SAMA5D3_ID_HSMCI0       21      /* MCI */
+#define SAMA5D3_ID_HSMCI1       22      /* MCI */
+#define SAMA5D3_ID_HSMCI2       23      /* MCI */
+#define SAMA5D3_ID_SPI0         24      /* Serial Peripheral Interface 0 */
+#define SAMA5D3_ID_SPI1         25      /* Serial Peripheral Interface 1 */
+#define SAMA5D3_ID_TC0          26      /* Timer Counter 0 */
+#define SAMA5D3_ID_TC1          27      /* Timer Counter 2 */
+#define SAMA5D3_ID_PWM          28      /* Pulse Width Modulation Controller */
+#define SAMA5D3_ID_ADC          29      /* Touch Screen ADC Controller */
+#define SAMA5D3_ID_DMA0         30      /* DMA Controller 0 */
+#define SAMA5D3_ID_DMA1         31      /* DMA Controller 1 */
+#define SAMA5D3_ID_UHPHS        32      /* USB Host High Speed */
+#define SAMA5D3_ID_UDPHS        33      /* USB Device High Speed */
+#define SAMA5D3_ID_GMAC         34      /* Gigabit Ethernet MAC */
+#define SAMA5D3_ID_EMAC         35      /* Ethernet MAC */
+#define SAMA5D3_ID_LCDC         36      /* LCD Controller */
+#define SAMA5D3_ID_ISI          37      /* Image Sensor Interface */
+#define SAMA5D3_ID_SSC0         38      /* Synchronous Serial Controller 0 */
+#define SAMA5D3_ID_SSC1         39      /* Synchronous Serial Controller 1 */
+#define SAMA5D3_ID_CAN0         40      /* CAN Controller 0 */
+#define SAMA5D3_ID_CAN1         41      /* CAN Controller 1 */
+#define SAMA5D3_ID_SHA          42      /* Secure Hash Algorithm */
+#define SAMA5D3_ID_AES          43      /* Advanced Encryption Standard */
+#define SAMA5D3_ID_TDES         44      /* Triple Data Encryption Standard */
+#define SAMA5D3_ID_TRNG         45      /* True Random Generator Number */
+#define SAMA5D3_ID_IRQ0         47      /* Advanced Interrupt Controller (IRQ0) */
+
+/*
+ * Internal Memory
+ */
+#define SAMA5D3_SRAM_BASE       0x00300000      /* Internal SRAM base address */
+#define SAMA5D3_SRAM_SIZE       (128 * SZ_1K)   /* Internal SRAM size (128Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
new file mode 100644
index 000000000000..401279715ab1
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -0,0 +1,377 @@
+/*
+ *  Chip-specific setup code for the SAMA5D3 family
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/sama5d3.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pid            = SAMA5D3_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pid            = SAMA5D3_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pid            = SAMA5D3_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioD_clk = {
+        .name           = "pioD_clk",
+        .pid            = SAMA5D3_ID_PIOD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioE_clk = {
+        .name           = "pioE_clk",
+        .pid            = SAMA5D3_ID_PIOE,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pid            = SAMA5D3_ID_USART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pid            = SAMA5D3_ID_USART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pid            = SAMA5D3_ID_USART2,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pid            = SAMA5D3_ID_USART3,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk uart0_clk = {
+        .name           = "uart0_clk",
+        .pid            = SAMA5D3_ID_UART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk uart1_clk = {
+        .name           = "uart1_clk",
+        .pid            = SAMA5D3_ID_UART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pid            = SAMA5D3_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pid            = SAMA5D3_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi2_clk = {
+        .name           = "twi2_clk",
+        .pid            = SAMA5D3_ID_TWI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk mmc0_clk = {
+        .name           = "mci0_clk",
+        .pid            = SAMA5D3_ID_HSMCI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+        .name           = "mci1_clk",
+        .pid            = SAMA5D3_ID_HSMCI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc2_clk = {
+        .name           = "mci2_clk",
+        .pid            = SAMA5D3_ID_HSMCI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pid            = SAMA5D3_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pid            = SAMA5D3_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb0_clk = {
+        .name           = "tcb0_clk",
+        .pid            = SAMA5D3_ID_TC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk tcb1_clk = {
+        .name           = "tcb1_clk",
+        .pid            = SAMA5D3_ID_TC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pid            = SAMA5D3_ID_ADC,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk adc_op_clk = {
+        .name           = "adc_op_clk",
+        .type           = CLK_TYPE_PERIPHERAL,
+        .rate_hz        = 5000000,
+};
+static struct clk dma0_clk = {
+        .name           = "dma0_clk",
+        .pid            = SAMA5D3_ID_DMA0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma1_clk = {
+        .name           = "dma1_clk",
+        .pid            = SAMA5D3_ID_DMA1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+        .name           = "uhphs",
+        .pid            = SAMA5D3_ID_UHPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+        .name           = "udphs_clk",
+        .pid            = SAMA5D3_ID_UDPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* gmac only for sama5d33, sama5d34, sama5d35 */
+static struct clk macb0_clk = {
+        .name           = "macb0_clk",
+        .pid            = SAMA5D3_ID_GMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac only for sama5d31, sama5d35 */
+static struct clk macb1_clk = {
+        .name           = "macb1_clk",
+        .pid            = SAMA5D3_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* lcd only for sama5d31, sama5d33, sama5d34 */
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pid            = SAMA5D3_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* isi only for sama5d33, sama5d35 */
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pid            = SAMA5D3_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pid            = SAMA5D3_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pid            = SAMA5D3_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pid            = SAMA5D3_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pid            = SAMA5D3_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk sha_clk = {
+        .name           = "sha_clk",
+        .pid            = SAMA5D3_ID_SHA,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV8,
+};
+static struct clk aes_clk = {
+        .name           = "aes_clk",
+        .pid            = SAMA5D3_ID_AES,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tdes_clk = {
+        .name           = "tdes_clk",
+        .pid            = SAMA5D3_ID_TDES,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &pioD_clk,
+        &pioE_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &usart3_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &twi2_clk,
+        &mmc0_clk,
+        &mmc1_clk,
+        &mmc2_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &tcb0_clk,
+        &tcb1_clk,
+        &adc_clk,
+        &adc_op_clk,
+        &dma0_clk,
+        &dma1_clk,
+        &uhphs_clk,
+        &udphs_clk,
+        &macb0_clk,
+        &macb1_clk,
+        &lcdc_clk,
+        &isi_clk,
+        &can0_clk,
+        &can1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &sha_clk,
+        &aes_clk,
+        &tdes_clk,
+};
+
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 2,
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
+        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
+        CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
+        CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
+        CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
+        CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
+        CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
+        CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
+};
+
+static void __init sama5d3_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clk_register(&pck2);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init sama5d3_map_io(void)
+{
+        at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
+}
+
+AT91_SOC_START(sama5d3)
+        .map_io = sama5d3_map_io,
+        .register_clocks = sama5d3_register_clocks,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 9e7c1e1528e5..e8491e77b1f7 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -151,6 +151,11 @@ static void __init soc_detect(u32 dbgu_base)
                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
                 at91_boot_soc = at91sam9n12_soc;
                 break;
+
+        case ARCH_ID_SAMA5D3:
+                at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+                at91_boot_soc = sama5d3_soc;
+                break;
         }
 
         /* at91sam9g10 */
@@ -206,6 +211,23 @@ static void __init soc_detect(u32 dbgu_base)
                         break;
                 }
         }
+
+        if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
+                switch (at91_soc_initdata.exid) {
+                case ARCH_EXID_SAMA5D31:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
+                        break;
+                case ARCH_EXID_SAMA5D33:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
+                        break;
+                case ARCH_EXID_SAMA5D34:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
+                        break;
+                case ARCH_EXID_SAMA5D35:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
+                        break;
+                }
+        }
 }
 
 static const char *soc_name[] = {
@@ -219,6 +241,7 @@ static const char *soc_name[] = {
         [AT91_SOC_SAM9RL]       = "at91sam9rl",
         [AT91_SOC_SAM9X5]       = "at91sam9x5",
         [AT91_SOC_SAM9N12]      = "at91sam9n12",
+        [AT91_SOC_SAMA5D3]      = "sama5d3",
         [AT91_SOC_NONE]         = "Unknown"
 };
 
@@ -241,6 +264,10 @@ static const char *soc_subtype_name[] = {
         [AT91_SOC_SAM9X35]      = "at91sam9x35",
         [AT91_SOC_SAM9G25]      = "at91sam9g25",
         [AT91_SOC_SAM9X25]      = "at91sam9x25",
+        [AT91_SOC_SAMA5D31]     = "sama5d31",
+        [AT91_SOC_SAMA5D33]     = "sama5d33",
+        [AT91_SOC_SAMA5D34]     = "sama5d34",
+        [AT91_SOC_SAMA5D35]     = "sama5d35",
         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
 };
 
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 9c6d3d4f9a23..43a225f9e713 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -22,9 +22,10 @@ extern struct at91_init_soc at91sam9g45_soc;
 extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
 extern struct at91_init_soc at91sam9n12_soc;
+extern struct at91_init_soc sama5d3_soc;
 
 #define AT91_SOC_START(_name)                           \
-struct at91_init_soc __initdata at91##_name##_soc       \
+struct at91_init_soc __initdata _name##_soc             \
  __used                                                 \
                                                 = {     \
         .builtin        = 1,                            \
@@ -68,3 +69,7 @@ static inline int at91_soc_is_enabled(void)
 #if !defined(CONFIG_SOC_AT91SAM9N12)
 #define at91sam9n12_soc at91_boot_soc
 #endif
+
+#if !defined(CONFIG_SOC_SAMA5D3)
+#define sama5d3_soc     at91_boot_soc
+#endif
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 6da25eebf911..12e6f756361d 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -246,7 +246,6 @@ static struct davinci_mmc_config da830_evm_mmc_config = {
         .wires                  = 8,
         .max_freq               = 50000000,
         .caps                   = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version                = MMC_CTLR_VERSION_2,
 };
 
 static inline void da830_evm_init_mmc(void)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index c2dfe06563df..dcc8710936a5 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -802,7 +802,6 @@ static struct davinci_mmc_config da850_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static const short da850_evm_mmcsd0_pins[] __initconst = {
@@ -1372,7 +1371,6 @@ static struct davinci_mmc_config da850_wl12xx_mmc_config = {
         .max_freq       = 25000000,
         .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE |
                           MMC_CAP_POWER_OFF_CARD,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static const short da850_wl12xx_pins[] __initconst = {
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 886481c12173..c2a0a67d09e0 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -345,7 +345,6 @@ static struct davinci_mmc_config dm355evm_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_1,
 };
 
 /* Don't connect anything to J10 unless you're only using USB host
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 2a6674356585..fd38c8d22e3c 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -255,7 +255,6 @@ static struct davinci_mmc_config dm365evm_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static void dm365evm_emac_configure(void)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 745280d4144c..e62108fd7926 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -570,7 +570,6 @@ static struct davinci_mmc_config dm6446evm_mmc_config = {
         .get_cd         = dm6444evm_mmc_get_cd,
         .get_ro         = dm6444evm_mmc_get_ro,
         .wires          = 4,
-        .version        = MMC_CTLR_VERSION_1
 };
 
 static struct i2c_board_info __initdata i2c_info[] =  {
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 1c98107527fa..b70e83c03bed 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -164,7 +164,6 @@ static void __init davinci_ntosd2_map_io(void)
 
 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
         .wires          = 4,
-        .version        = MMC_CTLR_VERSION_1
 };
 
 
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 5a2bd44da54d..328dbd8a37f5 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -136,7 +136,6 @@ static struct davinci_mmc_config da850_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static __init void omapl138_hawk_mmc_init(void)
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index 4f416023d4e2..ba798370fc96 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -85,7 +85,6 @@ static struct davinci_mmc_config mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_1,
 };
 
 static const short sdio1_pins[] __initconst = {
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index d458558ee84a..dc9a470ff9c5 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -35,19 +35,26 @@ static void __clk_enable(struct clk *clk)
 {
         if (clk->parent)
                 __clk_enable(clk->parent);
-        if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
-                                true, clk->flags);
+        if (clk->usecount++ == 0) {
+                if (clk->flags & CLK_PSC)
+                        davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
+                                           true, clk->flags);
+                else if (clk->clk_enable)
+                        clk->clk_enable(clk);
+        }
 }
 
 static void __clk_disable(struct clk *clk)
 {
         if (WARN_ON(clk->usecount == 0))
                 return;
-        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
-            (clk->flags & CLK_PSC))
-                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
-                                false, clk->flags);
+        if (--clk->usecount == 0) {
+                if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
+                        davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
+                                           false, clk->flags);
+                else if (clk->clk_disable)
+                        clk->clk_disable(clk);
+        }
         if (clk->parent)
                 __clk_disable(clk->parent);
 }
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 8694b395fc92..1e4e836173a1 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -104,6 +104,8 @@ struct clk {
         int (*set_rate) (struct clk *clk, unsigned long rate);
         int (*round_rate) (struct clk *clk, unsigned long rate);
         int (*reset) (struct clk *clk, bool reset);
+        void (*clk_enable) (struct clk *clk);
+        void (*clk_disable) (struct clk *clk);
 };
 
 /* Clock flags: SoC-specific flags start at BIT(16) */
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 678a54a64dae..abbaf0270be6 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -394,7 +394,7 @@ static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "tpcc",         &tpcc_clk),
         CLK(NULL,               "tptc0",        &tptc0_clk),
         CLK(NULL,               "tptc1",        &tptc1_clk),
-        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+        CLK("da830-mmc.0",      NULL,           &mmcsd_clk),
         CLK(NULL,               "uart0",        &uart0_clk),
         CLK(NULL,               "uart1",        &uart1_clk),
         CLK(NULL,               "uart2",        &uart2_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 0c4a26ddebba..4d6933848abf 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -383,6 +383,49 @@ static struct clk dsp_clk = {
         .flags          = PSC_LRST | PSC_FORCE,
 };
 
+static struct clk ehrpwm_clk = {
+        .name           = "ehrpwm",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .gpsc           = 1,
+        .flags          = DA850_CLK_ASYNC3,
+};
+
+#define DA8XX_EHRPWM_TBCLKSYNC  BIT(12)
+
+static void ehrpwm_tblck_enable(struct clk *clk)
+{
+        u32 val;
+
+        val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+        val |= DA8XX_EHRPWM_TBCLKSYNC;
+        writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+}
+
+static void ehrpwm_tblck_disable(struct clk *clk)
+{
+        u32 val;
+
+        val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+        val &= ~DA8XX_EHRPWM_TBCLKSYNC;
+        writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+}
+
+static struct clk ehrpwm_tbclk = {
+        .name           = "ehrpwm_tbclk",
+        .parent         = &ehrpwm_clk,
+        .clk_enable     = ehrpwm_tblck_enable,
+        .clk_disable    = ehrpwm_tblck_disable,
+};
+
+static struct clk ecap_clk = {
+        .name           = "ecap",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .gpsc           = 1,
+        .flags          = DA850_CLK_ASYNC3,
+};
+
 static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
@@ -420,8 +463,8 @@ static struct clk_lookup da850_clks[] = {
         CLK("davinci_emac.1",   NULL,           &emac_clk),
         CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
         CLK("da8xx_lcdc.0",     "fck",          &lcdc_clk),
-        CLK("davinci_mmc.0",    NULL,           &mmcsd0_clk),
-        CLK("davinci_mmc.1",    NULL,           &mmcsd1_clk),
+        CLK("da830-mmc.0",      NULL,           &mmcsd0_clk),
+        CLK("da830-mmc.1",      NULL,           &mmcsd1_clk),
         CLK(NULL,               "aemif",        &aemif_clk),
         CLK(NULL,               "usb11",        &usb11_clk),
         CLK(NULL,               "usb20",        &usb20_clk),
@@ -430,6 +473,9 @@ static struct clk_lookup da850_clks[] = {
         CLK("vpif",             NULL,           &vpif_clk),
         CLK("ahci",             NULL,           &sata_clk),
         CLK("davinci-rproc.0",  NULL,           &dsp_clk),
+        CLK("ehrpwm",           "fck",          &ehrpwm_clk),
+        CLK("ehrpwm",           "tbclk",        &ehrpwm_tbclk),
+        CLK("ecap",             "fck",          &ecap_clk),
         CLK(NULL,               NULL,           NULL),
 };
 
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 6b7a0a27fbd1..b1c0a5958275 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -20,7 +20,7 @@
 
 #define DA8XX_NUM_UARTS 3
 
-void __init da8xx_uart_clk_enable(void)
+static void __init da8xx_uart_clk_enable(void)
 {
         int i;
         for (i = 0; i < DA8XX_NUM_UARTS; i++)
@@ -37,9 +37,10 @@ static void __init da8xx_init_irq(void)
         of_irq_init(da8xx_irq_match);
 }
 
-struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
+static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
         OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL),
+        OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL),
         {}
 };
 
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index fc50243b1481..bf572525175d 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -12,7 +12,7 @@
  */
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-contiguous.h>
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
@@ -664,7 +664,7 @@ static struct resource da8xx_mmcsd0_resources[] = {
 };
 
 static struct platform_device da8xx_mmcsd0_device = {
-        .name           = "davinci_mmc",
+        .name           = "da830-mmc",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
         .resource       = da8xx_mmcsd0_resources,
@@ -701,7 +701,7 @@ static struct resource da850_mmcsd1_resources[] = {
 };
 
 static struct platform_device da850_mmcsd1_device = {
-        .name           = "davinci_mmc",
+        .name           = "da830-mmc",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
         .resource       = da850_mmcsd1_resources,
@@ -714,6 +714,92 @@ int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
 }
 #endif
 
+static struct resource da8xx_rproc_resources[] = {
+        { /* DSP boot address */
+                .start          = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
+                .end            = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
+                .flags          = IORESOURCE_MEM,
+        },
+        { /* DSP interrupt registers */
+                .start          = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
+                .end            = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
+                .flags          = IORESOURCE_MEM,
+        },
+        { /* dsp irq */
+                .start          = IRQ_DA8XX_CHIPINT0,
+                .end            = IRQ_DA8XX_CHIPINT0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_dsp = {
+        .name   = "davinci-rproc",
+        .dev    = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(da8xx_rproc_resources),
+        .resource       = da8xx_rproc_resources,
+};
+
+#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
+
+static phys_addr_t rproc_base __initdata;
+static unsigned long rproc_size __initdata;
+
+static int __init early_rproc_mem(char *p)
+{
+        char *endp;
+
+        if (p == NULL)
+                return 0;
+
+        rproc_size = memparse(p, &endp);
+        if (*endp == '@')
+                rproc_base = memparse(endp + 1, NULL);
+
+        return 0;
+}
+early_param("rproc_mem", early_rproc_mem);
+
+void __init da8xx_rproc_reserve_cma(void)
+{
+        int ret;
+
+        if (!rproc_base || !rproc_size) {
+                pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
+                       "    'nn' and 'address' must both be non-zero\n",
+                       __func__);
+
+                return;
+        }
+
+        pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
+                __func__, rproc_size, (unsigned long)rproc_base);
+
+        ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
+        if (ret)
+                pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
+}
+
+#else
+
+void __init da8xx_rproc_reserve_cma(void)
+{
+}
+
+#endif
+
+int __init da8xx_register_rproc(void)
+{
+        int ret;
+
+        ret = platform_device_register(&da8xx_dsp);
+        if (ret)
+                pr_err("%s: can't register DSP device: %d\n", __func__, ret);
+
+        return ret;
+};
+
 static struct resource da8xx_rtc_resources[] = {
         {
                 .start          = DA8XX_RTC_BASE,
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 773ab07a71a0..cfb194df18ed 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -218,7 +218,7 @@ static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
 
 static struct platform_device mmc_devices[2] = {
         {
-                .name           = "davinci_mmc",
+                .name           = "dm6441-mmc",
                 .id             = 0,
                 .dev            = {
                         .dma_mask               = &mmc0_dma_mask,
@@ -228,7 +228,7 @@ static struct platform_device mmc_devices[2] = {
                 .resource       = mmc0_resources
         },
         {
-                .name           = "davinci_mmc",
+                .name           = "dm6441-mmc",
                 .id             = 1,
                 .dev            = {
                         .dma_mask               = &mmc1_dma_mask,
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 4c48a36ee567..f6927df2dda8 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -150,7 +150,7 @@ static struct resource mmcsd0_resources[] = {
 };
 
 static struct platform_device davinci_mmcsd0_device = {
-        .name = "davinci_mmc",
+        .name = "dm6441-mmc",
         .id = 0,
         .dev = {
                 .dma_mask = &mmcsd0_dma_mask,
@@ -187,7 +187,7 @@ static struct resource mmcsd1_resources[] = {
 };
 
 static struct platform_device davinci_mmcsd1_device = {
-        .name = "davinci_mmc",
+        .name = "dm6441-mmc",
         .id = 1,
         .dev = {
                 .dma_mask = &mmcsd1_dma_mask,
@@ -235,6 +235,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
                                                         SZ_4K - 1;
                         mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
+                        davinci_mmcsd1_device.name = "da830-mmc";
                 } else
                         break;
 
@@ -256,6 +257,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
                                                         SZ_4K - 1;
                         mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
+                        davinci_mmcsd0_device.name = "da830-mmc";
                 } else if (cpu_is_davinci_dm644x()) {
                         /* REVISIT: should this be in board-init code? */
                         /* Power-on 3.3V IO cells */
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index bf9a9d4ad9f5..a11034a358f1 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -363,8 +363,8 @@ static struct clk_lookup dm355_clks[] = {
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("davinci-mcbsp.0", NULL, &asp0_clk),
         CLK("davinci-mcbsp.1", NULL, &asp1_clk),
-        CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
-        CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
+        CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
+        CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
         CLK("spi_davinci.0", NULL, &spi0_clk),
         CLK("spi_davinci.1", NULL, &spi1_clk),
         CLK("spi_davinci.2", NULL, &spi2_clk),
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ff771ceac3f1..40fa4fee9331 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -458,8 +458,8 @@ static struct clk_lookup dm365_clks[] = {
         CLK(NULL, "uart0", &uart0_clk),
         CLK(NULL, "uart1", &uart1_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
-        CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
-        CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
+        CLK("da830-mmc.0", NULL, &mmcsd0_clk),
+        CLK("da830-mmc.1", NULL, &mmcsd1_clk),
         CLK("spi_davinci.0", NULL, &spi0_clk),
         CLK("spi_davinci.1", NULL, &spi1_clk),
         CLK("spi_davinci.2", NULL, &spi2_clk),
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c2a9273330bf..4d37d3e2a193 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -310,7 +310,7 @@ static struct clk_lookup dm644x_clks[] = {
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("palm_bk3710", NULL, &ide_clk),
         CLK("davinci-mcbsp", NULL, &asp_clk),
-        CLK("davinci_mmc.0", NULL, &mmcsd_clk),
+        CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
         CLK(NULL, "spi", &spi_clk),
         CLK(NULL, "gpio", &gpio_clk),
         CLK(NULL, "usb", &usb_clk),
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index de439b7b9af1..2e1c9eae0a58 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -54,7 +54,10 @@ extern unsigned int da850_max_speed;
 #define DA8XX_SYSCFG0_BASE      (IO_PHYS + 0x14000)
 #define DA8XX_SYSCFG0_VIRT(x)   (da8xx_syscfg0_base + (x))
 #define DA8XX_JTAG_ID_REG       0x18
+#define DA8XX_HOST1CFG_REG      0x44
+#define DA8XX_CHIPSIG_REG       0x174
 #define DA8XX_CFGCHIP0_REG      0x17c
+#define DA8XX_CFGCHIP1_REG      0x180
 #define DA8XX_CFGCHIP2_REG      0x184
 #define DA8XX_CFGCHIP3_REG      0x188
 
@@ -104,6 +107,8 @@ int __init da850_register_vpif_display
 int __init da850_register_vpif_capture
                         (struct vpif_capture_config *capture_config);
 void da8xx_restart(char mode, const char *cmd);
+void da8xx_rproc_reserve_cma(void);
+int da8xx_register_rproc(void);
 
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 34290d14754b..b18b8ebc6508 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -24,8 +24,6 @@
 
 #if defined(CONFIG_DEBUG_DAVINCI_DMx_UART0)
 #define UART_BASE       DAVINCI_UART0_BASE
-#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART0)
-#define UART_BASE       DA8XX_UART0_BASE
 #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART1)
 #define UART_BASE       DA8XX_UART1_BASE
 #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART2)
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index eb8360b33aa9..a508fe587af7 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -19,6 +19,7 @@
 #include <asm/delay.h>
 #include <asm/io.h>
 
+#include <mach/common.h>
 #include <mach/da8xx.h>
 #include <mach/sram.h>
 #include <mach/pm.h>
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index c5f7ee5cc80a..f18928b073f5 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -62,7 +62,7 @@ static int __init sram_init(void)
         phys_addr_t phys = davinci_soc_info.sram_dma;
         unsigned len = davinci_soc_info.sram_len;
         int status = 0;
-        void *addr;
+        void __iomem *addr;
 
         if (len) {
                 len = min_t(unsigned, len, SRAM_SIZE);
@@ -75,7 +75,7 @@ static int __init sram_init(void)
                 addr = ioremap(phys, len);
                 if (!addr)
                         return -ENOMEM;
-                status = gen_pool_add_virt(sram_pool, (unsigned)addr,
+                status = gen_pool_add_virt(sram_pool, (unsigned long) addr,
                                            phys, len, -1);
                 if (status < 0)
                         iounmap(addr);
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index dc1a209b9b66..3b2a70d43efa 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -272,7 +272,7 @@ static struct clk_lookup clks[] = {
         CLK("tnetv107x-keypad.0", NULL,                 &clk_keypad),
         CLK(NULL,               "clk_gpio",             &clk_gpio),
         CLK(NULL,               "clk_mdio",             &clk_mdio),
-        CLK("davinci_mmc.0",    NULL,                   &clk_sdio0),
+        CLK("dm6441-mmc.0",     NULL,                   &clk_sdio0),
         CLK(NULL,               "uart0",                &clk_uart0),
         CLK(NULL,               "uart1",                &clk_uart1),
         CLK(NULL,               "timer0",               &clk_timer0),
@@ -292,7 +292,7 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_system",           &clk_system),
         CLK(NULL,               "clk_imcop",            &clk_imcop),
         CLK(NULL,               "clk_spare",            &clk_spare),
-        CLK("davinci_mmc.1",    NULL,                   &clk_sdio1),
+        CLK("dm6441-mmc.1",     NULL,                   &clk_sdio1),
         CLK(NULL,               "clk_ddr2_vrst",        &clk_ddr2_vrst),
         CLK(NULL,               "clk_ddr2_vctl_rst",    &clk_ddr2_vctl_rst),
         CLK(NULL,               NULL,                   NULL),
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 34509ffba221..2b4c648f99b6 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -10,6 +10,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
+#include <mach/da8xx.h>
 #include <linux/platform_data/usb-davinci.h>
 
 #define DAVINCI_USB_OTG_BASE    0x01c64000
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 1b0fa7afc7f8..15718da30c45 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -463,6 +463,8 @@ void __init exynos4_init_irq(void)
          * uses GIC instead of VIC.
          */
         s5p_init_irq(NULL, 0);
+
+        gic_arch_extn.irq_set_wake = s3c_irq_wake;
 }
 
 void __init exynos5_init_irq(void)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 498a7a23e260..17a18ff3d71e 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -41,23 +41,24 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index);
 
-static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
-        [0] = ARM_CPUIDLE_WFI_STATE,
-        [1] = {
-                .enter                  = exynos4_enter_lowpower,
-                .exit_latency           = 300,
-                .target_residency       = 100000,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "C1",
-                .desc                   = "ARM power down",
-        },
-};
-
 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
 
 static struct cpuidle_driver exynos4_idle_driver = {
         .name                   = "exynos4_idle",
         .owner                  = THIS_MODULE,
+        .states = {
+                [0] = ARM_CPUIDLE_WFI_STATE,
+                [1] = {
+                        .enter                  = exynos4_enter_lowpower,
+                        .exit_latency           = 300,
+                        .target_residency       = 100000,
+                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                        .name                   = "C1",
+                        .desc                   = "ARM power down",
+                },
+        },
+        .state_count = 2,
+        .safe_state_index = 0,
 };
 
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
@@ -192,37 +193,30 @@ static void __init exynos5_core_down_clk(void)
 
 static int __init exynos4_init_cpuidle(void)
 {
-        int i, max_cpuidle_state, cpu_id;
+        int cpu_id, ret;
         struct cpuidle_device *device;
-        struct cpuidle_driver *drv = &exynos4_idle_driver;
 
         if (soc_is_exynos5250())
                 exynos5_core_down_clk();
 
-        /* Setup cpuidle driver */
-        drv->state_count = (sizeof(exynos4_cpuidle_set) /
-                                       sizeof(struct cpuidle_state));
-        max_cpuidle_state = drv->state_count;
-        for (i = 0; i < max_cpuidle_state; i++) {
-                memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
-                                sizeof(struct cpuidle_state));
+        ret = cpuidle_register_driver(&exynos4_idle_driver);
+        if (ret) {
+                printk(KERN_ERR "CPUidle failed to register driver\n");
+                return ret;
         }
-        drv->safe_state_index = 0;
-        cpuidle_register_driver(&exynos4_idle_driver);
 
-        for_each_cpu(cpu_id, cpu_online_mask) {
+        for_each_online_cpu(cpu_id) {
                 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
                 device->cpu = cpu_id;
 
-                if (cpu_id == 0)
-                        device->state_count = (sizeof(exynos4_cpuidle_set) /
-                                               sizeof(struct cpuidle_state));
-                else
-                        device->state_count = 1;        /* Support IDLE only */
+                /* Support IDLE only */
+                if (cpu_id != 0)
+                        device->state_count = 1;
 
-                if (cpuidle_register_device(device)) {
-                        printk(KERN_ERR "CPUidle register device failed\n,");
-                        return -EIO;
+                ret = cpuidle_register_device(device);
+                if (ret) {
+                        printk(KERN_ERR "CPUidle register device failed\n");
+                        return ret;
                 }
         }
 
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index a67ecfaf1216..7dbbfec13ea5 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -27,13 +27,8 @@ static inline void s3c_pm_debug_init_uart(void)
 
 static inline void s3c_pm_arch_prepare_irqs(void)
 {
-        unsigned int tmp;
-        tmp = __raw_readl(S5P_WAKEUP_MASK);
-        tmp &= ~(1 << 31);
-        __raw_writel(tmp, S5P_WAKEUP_MASK);
-
-        __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
-        __raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
+        __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+        __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 }
 
 static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index f9fd77e8f1f5..284313f3e02c 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -30,19 +30,22 @@
 
 #include "common.h"
 
-#define TIMER_MATCH_VAL         0x0000
-#define TIMER_COUNT_VAL         0x0004
-#define TIMER_ENABLE            0x0008
-#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
-#define TIMER_ENABLE_EN                 BIT(0)
-#define TIMER_CLEAR             0x000C
-#define DGT_CLK_CTL_DIV_4       0x3
+#define TIMER_MATCH_VAL                 0x0000
+#define TIMER_COUNT_VAL                 0x0004
+#define TIMER_ENABLE                    0x0008
+#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
+#define TIMER_ENABLE_EN                 BIT(0)
+#define TIMER_CLEAR                     0x000C
+#define DGT_CLK_CTL                     0x10
+#define DGT_CLK_CTL_DIV_4               0x3
+#define TIMER_STS_GPT0_CLR_PEND         BIT(10)
 
 #define GPT_HZ 32768
 
 #define MSM_DGT_SHIFT 5
 
 static void __iomem *event_base;
+static void __iomem *sts_base;
 
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
@@ -67,6 +70,11 @@ static int msm_timer_set_next_event(unsigned long cycles,
 
         writel_relaxed(ctrl, event_base + TIMER_CLEAR);
         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
+
+        if (sts_base)
+                while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
+                        cpu_relax();
+
         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
         return 0;
 }
@@ -137,9 +145,6 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
         if (!smp_processor_id())
                 return 0;
 
-        writel_relaxed(0, event_base + TIMER_ENABLE);
-        writel_relaxed(0, event_base + TIMER_CLEAR);
-        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
         evt->irq = msm_clockevent.irq;
         evt->name = "local_timer";
         evt->features = msm_clockevent.features;
@@ -177,9 +182,6 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
         struct clocksource *cs = &msm_clocksource;
         int res;
 
-        writel_relaxed(0, event_base + TIMER_ENABLE);
-        writel_relaxed(0, event_base + TIMER_CLEAR);
-        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
         ce->cpumask = cpumask_of(0);
         ce->irq = irq;
 
@@ -217,13 +219,9 @@ err:
 }
 
 #ifdef CONFIG_OF
-static const struct of_device_id msm_dgt_match[] __initconst = {
-        { .compatible = "qcom,msm-dgt" },
-        { },
-};
-
-static const struct of_device_id msm_gpt_match[] __initconst = {
-        { .compatible = "qcom,msm-gpt" },
+static const struct of_device_id msm_timer_match[] __initconst = {
+        { .compatible = "qcom,kpss-timer" },
+        { .compatible = "qcom,scss-timer" },
         { },
 };
 
@@ -234,33 +232,29 @@ void __init msm_dt_timer_init(void)
         int irq;
         struct resource res;
         u32 percpu_offset;
-        void __iomem *dgt_clk_ctl;
+        void __iomem *base;
+        void __iomem *cpu0_base;
 
-        np = of_find_matching_node(NULL, msm_gpt_match);
+        np = of_find_matching_node(NULL, msm_timer_match);
         if (!np) {
-                pr_err("Can't find GPT DT node\n");
+                pr_err("Can't find msm timer DT node\n");
                 return;
         }
 
-        event_base = of_iomap(np, 0);
-        if (!event_base) {
+        base = of_iomap(np, 0);
+        if (!base) {
                 pr_err("Failed to map event base\n");
                 return;
         }
 
-        irq = irq_of_parse_and_map(np, 0);
+        /* We use GPT0 for the clockevent */
+        irq = irq_of_parse_and_map(np, 1);
         if (irq <= 0) {
                 pr_err("Can't get irq\n");
                 return;
         }
-        of_node_put(np);
-
-        np = of_find_matching_node(NULL, msm_dgt_match);
-        if (!np) {
-                pr_err("Can't find DGT DT node\n");
-                return;
-        }
 
+        /* We use CPU0's DGT for the clocksource */
         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
                 percpu_offset = 0;
 
@@ -269,45 +263,43 @@ void __init msm_dt_timer_init(void)
                 return;
         }
 
-        source_base = ioremap(res.start + percpu_offset, resource_size(&res));
-        if (!source_base) {
+        cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
+        if (!cpu0_base) {
                 pr_err("Failed to map source base\n");
                 return;
         }
 
-        if (!of_address_to_resource(np, 1, &res)) {
-                dgt_clk_ctl = ioremap(res.start + percpu_offset,
-                                      resource_size(&res));
-                if (!dgt_clk_ctl) {
-                        pr_err("Failed to map DGT control base\n");
-                        return;
-                }
-                writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
-                iounmap(dgt_clk_ctl);
-        }
-
         if (of_property_read_u32(np, "clock-frequency", &freq)) {
                 pr_err("Unknown frequency\n");
                 return;
         }
         of_node_put(np);
 
+        event_base = base + 0x4;
+        sts_base = base + 0x88;
+        source_base = cpu0_base + 0x24;
+        freq /= 4;
+        writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
+
         msm_timer_init(freq, 32, irq, !!percpu_offset);
 }
 #endif
 
-static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
+static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
+                                u32 sts)
 {
-        event_base = ioremap(event, SZ_64);
-        if (!event_base) {
-                pr_err("Failed to map event base\n");
-                return 1;
-        }
-        source_base = ioremap(source, SZ_64);
-        if (!source_base) {
-                pr_err("Failed to map source base\n");
-                return 1;
+        void __iomem *base;
+
+        base = ioremap(addr, SZ_256);
+        if (!base) {
+                pr_err("Failed to map timer base\n");
+                return -ENOMEM;
         }
+        event_base = base + event;
+        source_base = base + source;
+        if (sts)
+                sts_base = base + sts;
+
         return 0;
 }
 
@@ -315,7 +307,7 @@ void __init msm7x01_timer_init(void)
 {
         struct clocksource *cs = &msm_clocksource;
 
-        if (msm_timer_map(0xc0100000, 0xc0100010))
+        if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
                 return;
         cs->read = msm_read_timer_count_shift;
         cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
@@ -326,14 +318,14 @@ void __init msm7x01_timer_init(void)
 
 void __init msm7x30_timer_init(void)
 {
-        if (msm_timer_map(0xc0100004, 0xc0100024))
+        if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
                 return;
         msm_timer_init(24576000 / 4, 32, 1, false);
 }
 
 void __init qsd8x50_timer_init(void)
 {
-        if (msm_timer_map(0xAC100000, 0xAC100010))
+        if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
                 return;
         msm_timer_init(19200000 / 4, 32, 7, false);
 }
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index ecc431909d6f..c4495a13751a 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -3,6 +3,7 @@ if ARCH_MXS
 config SOC_IMX23
         bool
         select ARM_AMBA
+        select ARM_CPU_SUSPEND if PM
         select CPU_ARM926T
         select HAVE_PWM
         select PINCTRL_IMX23
@@ -10,6 +11,7 @@ config SOC_IMX23
 config SOC_IMX28
         bool
         select ARM_AMBA
+        select ARM_CPU_SUSPEND if PM
         select CPU_ARM926T
         select HAVE_CAN_FLEXCAN if CAN
         select HAVE_PWM
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4dc34ae6a857..5c27c4747469 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,6 +15,7 @@ config ARCH_OMAP2PLUS
         select OMAP_DM_TIMER
         select PINCTRL
         select PROC_DEVICETREE if PROC_FS
+        select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
         help
@@ -99,6 +100,8 @@ config ARCH_OMAP4
         select PM_RUNTIME if CPU_IDLE
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select COMMON_CLK
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_775420
 
 config SOC_OMAP5
         bool "TI OMAP5"
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index bda353b2f7d9..5e4b037bb24c 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1978,9 +1978,11 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "sdrc_ick",     &sdrc_ick),
         CLK(NULL,       "des_ick",      &des_ick),
         CLK("omap-sham",        "ick",  &sha_ick),
-        CLK("omap_rng", "ick",          &rng_ick),
+        CLK(NULL,       "sha_ick",      &sha_ick),
+        CLK("omap_rng", "ick",          &rng_ick),
         CLK(NULL,       "rng_ick",      &rng_ick),
         CLK("omap-aes", "ick",  &aes_ick),
+        CLK(NULL,       "aes_ick",      &aes_ick),
         CLK(NULL,       "pka_ick",      &pka_ick),
         CLK(NULL,       "usb_fck",      &usb_fck),
         CLK("musb-omap2430",    "ick",  &usbhs_ick),
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 332c6d3e55a9..6ebc7803bc3e 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -413,6 +413,14 @@ static struct clk smartreflex1_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
 DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk sha0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
+DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
+
+static struct clk aes0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
+DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -878,6 +886,8 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "mmu_fck",              &mmu_fck),
         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck),
         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
+        CLK(NULL,       "sha0_fck",             &sha0_fck),
+        CLK(NULL,       "aes0_fck",             &aes0_fck),
         CLK(NULL,       "timer1_fck",           &timer1_fck),
         CLK(NULL,       "timer2_fck",           &timer2_fck),
         CLK(NULL,       "timer3_fck",           &timer3_fck),
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 438d13341e23..45cd26430d1f 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3471,8 +3471,10 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
         CLK(NULL,       "init_60m_fclk",        &dummy_ck),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck),
+        CLK(NULL,       "aes2_ick",     &aes2_ick),
         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck),
         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck),
+        CLK(NULL,       "sha12_ick",    &sha12_ick),
         CLK(NULL,       "wdt2_fck",             &wdt2_fck),
         CLK("omap_wdt", "ick",          &wdt2_ick),
         CLK(NULL,       "wdt2_ick",     &wdt2_ick),
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 14522d077c88..df00e7580aa7 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -110,6 +110,14 @@ void am35xx_init_late(void);
 void ti81xx_init_late(void);
 int omap2_common_pm_late_init(void);
 
+#ifdef CONFIG_SOC_BUS
+void omap_soc_device_init(void);
+#else
+static inline void omap_soc_device_init(void)
+{
+}
+#endif
+
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
 void omap2xxx_restart(char mode, const char *cmd);
 #else
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 1ec7f0597710..4269fc145698 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -504,140 +504,31 @@ static void omap_init_rng(void)
         WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_sham_resources[] = {
-        {
-                .start  = OMAP24XX_SEC_SHA1MD5_BASE,
-                .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = 51 + OMAP_INTC_START,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
-#else
-#define omap2_sham_resources            NULL
-#define omap2_sham_resources_sz         0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_sham_resources[] = {
-        {
-                .start  = OMAP34XX_SEC_SHA1MD5_BASE,
-                .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = 49 + OMAP_INTC_START,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = OMAP34XX_DMA_SHA1MD5_RX,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
-#else
-#define omap3_sham_resources            NULL
-#define omap3_sham_resources_sz         0
-#endif
-
-static struct platform_device sham_device = {
-        .name           = "omap-sham",
-        .id             = -1,
-};
-
-static void omap_init_sham(void)
+static void __init omap_init_sham(void)
 {
-        if (cpu_is_omap24xx()) {
-                sham_device.resource = omap2_sham_resources;
-                sham_device.num_resources = omap2_sham_resources_sz;
-        } else if (cpu_is_omap34xx()) {
-                sham_device.resource = omap3_sham_resources;
-                sham_device.num_resources = omap3_sham_resources_sz;
-        } else {
-                pr_err("%s: platform not supported\n", __func__);
-                return;
-        }
-        platform_device_register(&sham_device);
-}
-#else
-static inline void omap_init_sham(void) { }
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_aes_resources[] = {
-        {
-                .start  = OMAP24XX_SEC_AES_BASE,
-                .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP24XX_DMA_AES_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        {
-                .start  = OMAP24XX_DMA_AES_RX,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
-#else
-#define omap2_aes_resources             NULL
-#define omap2_aes_resources_sz          0
-#endif
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_aes_resources[] = {
-        {
-                .start  = OMAP34XX_SEC_AES_BASE,
-                .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP34XX_DMA_AES2_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        {
-                .start  = OMAP34XX_DMA_AES2_RX,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
-#else
-#define omap3_aes_resources             NULL
-#define omap3_aes_resources_sz          0
-#endif
+        oh = omap_hwmod_lookup("sham");
+        if (!oh)
+                return;
 
-static struct platform_device aes_device = {
-        .name           = "omap-aes",
-        .id             = -1,
-};
+        pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
+}
 
-static void omap_init_aes(void)
+static void __init omap_init_aes(void)
 {
-        if (cpu_is_omap24xx()) {
-                aes_device.resource = omap2_aes_resources;
-                aes_device.num_resources = omap2_aes_resources_sz;
-        } else if (cpu_is_omap34xx()) {
-                aes_device.resource = omap3_aes_resources;
-                aes_device.num_resources = omap3_aes_resources_sz;
-        } else {
-                pr_err("%s: platform not supported\n", __func__);
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("aes");
+        if (!oh)
                 return;
-        }
-        platform_device_register(&aes_device);
-}
 
-#else
-static inline void omap_init_aes(void) { }
-#endif
+        pdev = omap_device_build("omap-aes", -1, oh, NULL, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
+}
 
 /*-------------------------------------------------------------------------*/
 
@@ -764,11 +655,11 @@ static int __init omap2_init_devices(void)
                 omap_init_dmic();
                 omap_init_mcpdm();
                 omap_init_mcspi();
+                omap_init_sham();
+                omap_init_aes();
         }
         omap_init_sti();
         omap_init_rng();
-        omap_init_sham();
-        omap_init_aes();
         omap_init_vout();
         omap_init_ocp2scp();
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index ff0bc9e51aa7..2fb17caa8683 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,6 +18,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+
+#ifdef CONFIG_SOC_BUS
+#include <linux/sys_soc.h>
+#endif
 
 #include <asm/cputype.h>
 
@@ -31,8 +36,11 @@
 #define OMAP4_SILICON_TYPE_STANDARD             0x01
 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
 
+#define OMAP_SOC_MAX_NAME_LENGTH                16
+
 static unsigned int omap_revision;
-static const char *cpu_rev;
+static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
+static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
 u32 omap_features;
 
 unsigned int omap_rev(void)
@@ -169,9 +177,12 @@ void __init omap2xxx_check_revision(void)
                 j = i;
         }
 
-        pr_info("OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
+
+        pr_info("%s", soc_name);
         if ((omap_rev() >> 8) & 0x0f)
-                pr_info("ES%x", (omap_rev() >> 12) & 0xf);
+                pr_info("%s", soc_rev);
         pr_info("\n");
 }
 
@@ -211,8 +222,10 @@ static void __init omap3_cpuinfo(void)
                 cpu_name = "OMAP3503";
         }
 
+        sprintf(soc_name, "%s", cpu_name);
+
         /* Print verbose information */
-        pr_info("%s ES%s (", cpu_name, cpu_rev);
+        pr_info("%s %s (", soc_name, soc_rev);
 
         OMAP3_SHOW_FEATURE(l2cache);
         OMAP3_SHOW_FEATURE(iva);
@@ -291,6 +304,7 @@ void __init ti81xx_check_features(void)
 
 void __init omap3xxx_check_revision(void)
 {
+        const char *cpu_rev;
         u32 cpuid, idcode;
         u16 hawkeye;
         u8 rev;
@@ -438,6 +452,7 @@ void __init omap3xxx_check_revision(void)
                 cpu_rev = "1.2";
                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
         }
+        sprintf(soc_rev, "ES%s", cpu_rev);
 }
 
 void __init omap4xxx_check_revision(void)
@@ -512,8 +527,10 @@ void __init omap4xxx_check_revision(void)
                 omap_revision = OMAP4430_REV_ES2_3;
         }
 
-        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
-                ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
+                                                (omap_rev() >> 8) & 0xf);
+        pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 void __init omap5xxx_check_revision(void)
@@ -553,8 +570,10 @@ void __init omap5xxx_check_revision(void)
                 omap_revision = OMAP5430_REV_ES2_0;
         }
 
-        pr_info("OMAP%04x ES%d.0\n",
-                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
+
+        pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 /*
@@ -575,3 +594,63 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
         else
                 tap_prod_id = 0x0208;
 }
+
+#ifdef CONFIG_SOC_BUS
+
+static const char const *omap_types[] = {
+        [OMAP2_DEVICE_TYPE_TEST]        = "TST",
+        [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
+        [OMAP2_DEVICE_TYPE_SEC]         = "HS",
+        [OMAP2_DEVICE_TYPE_GP]          = "GP",
+        [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
+};
+
+static const char * __init omap_get_family(void)
+{
+        if (cpu_is_omap24xx())
+                return kasprintf(GFP_KERNEL, "OMAP2");
+        else if (cpu_is_omap34xx())
+                return kasprintf(GFP_KERNEL, "OMAP3");
+        else if (cpu_is_omap44xx())
+                return kasprintf(GFP_KERNEL, "OMAP4");
+        else if (soc_is_omap54xx())
+                return kasprintf(GFP_KERNEL, "OMAP5");
+        else
+                return kasprintf(GFP_KERNEL, "Unknown");
+}
+
+static ssize_t omap_get_type(struct device *dev,
+                                        struct device_attribute *attr,
+                                        char *buf)
+{
+        return sprintf(buf, "%s\n", omap_types[omap_type()]);
+}
+
+static struct device_attribute omap_soc_attr =
+        __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
+
+void __init omap_soc_device_init(void)
+{
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+
+        soc_dev_attr->machine  = soc_name;
+        soc_dev_attr->family   = omap_get_family();
+        soc_dev_attr->revision = soc_rev;
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR_OR_NULL(soc_dev)) {
+                kfree(soc_dev_attr);
+                return;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+        if (!IS_ERR_OR_NULL(parent))
+                device_create_file(parent, &omap_soc_attr);
+}
+#endif /* CONFIG_SOC_BUS */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e210fa830f8d..09abf99e9e57 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -394,6 +394,13 @@ static void __init omap_hwmod_init_postsetup(void)
         omap_pm_if_early_init();
 }
 
+static void __init omap_common_late_init(void)
+{
+        omap_mux_late_init();
+        omap2_common_pm_late_init();
+        omap_soc_device_init();
+}
+
 #ifdef CONFIG_SOC_OMAP2420
 void __init omap2420_init_early(void)
 {
@@ -417,8 +424,7 @@ void __init omap2420_init_early(void)
 
 void __init omap2420_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap2_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -447,8 +453,7 @@ void __init omap2430_init_early(void)
 
 void __init omap2430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap2_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -520,48 +525,42 @@ void __init ti81xx_init_early(void)
 
 void __init omap3_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap3430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap35xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap3630_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init am35xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init ti81xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -613,8 +612,7 @@ void __init omap4430_init_early(void)
 
 void __init omap4430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap4_pm_init();
         omap2_clk_enable_autoidle_all();
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6a764af6c6d3..5137cc84b504 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -610,6 +610,8 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2420_l4_core__mcbsp2,
         &omap2420_l4_core__msdi1,
         &omap2xxx_l4_core__rng,
+        &omap2xxx_l4_core__sham,
+        &omap2xxx_l4_core__aes,
         &omap2420_l4_core__hdq1w,
         &omap2420_l4_wkup__counter_32k,
         &omap2420_l3__gpmc,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index d2d3840557c3..4ce999ee3ee9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -963,6 +963,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2430_l4_core__mcbsp5,
         &omap2430_l4_core__hdq1w,
         &omap2xxx_l4_core__rng,
+        &omap2xxx_l4_core__sham,
+        &omap2xxx_l4_core__aes,
         &omap2430_l4_wkup__counter_32k,
         &omap2430_l3__gpmc,
         NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 47901a5e76de..5fd40d4a989e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -138,6 +138,24 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
+        {
+                .pa_start       = 0x480a4000,
+                .pa_end         = 0x480a4000 + 0x64 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
+        {
+                .pa_start       = 0x480a6000,
+                .pa_end         = 0x480a6000 + 0x50 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /*
  * Common interconnect data
  */
@@ -389,3 +407,21 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
         .addr           = omap2_rng_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+
+/* l4 core -> sham interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_sham_hwmod,
+        .clk            = "sha_ick",
+        .addr           = omap2xxx_sham_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> aes interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_aes_hwmod,
+        .clk            = "aes_ick",
+        .addr           = omap2xxx_aes_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index e596117004d4..c8c64b3e1acc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -864,3 +864,84 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
         .flags          = HWMOD_INIT_NO_RESET,
         .class          = &omap2_rng_hwmod_class,
 };
+
+/* SHAM */
+
+static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
+        .rev_offs       = 0x5c,
+        .sysc_offs      = 0x60,
+        .syss_offs      = 0x64,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_sham_class = {
+        .name   = "sham",
+        .sysc   = &omap2_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
+        { .irq = 51 + OMAP_INTC_START, },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
+        { .name = "rx", .dma_req = 13 },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_sham_hwmod = {
+        .name           = "sham",
+        .mpu_irqs       = omap2_sham_mpu_irqs,
+        .sdma_reqs      = omap2_sham_sdma_chs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_SHA_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_sham_class,
+};
+
+/* AES */
+
+static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
+        .rev_offs       = 0x44,
+        .sysc_offs      = 0x48,
+        .syss_offs      = 0x4c,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_aes_class = {
+        .name   = "aes",
+        .sysc   = &omap2_aes_sysc,
+};
+
+static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
+        { .name = "tx", .dma_req = 9 },
+        { .name = "rx", .dma_req = 10 },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_aes_hwmod = {
+        .name           = "aes",
+        .sdma_reqs      = omap2_aes_sdma_chs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_AES_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_aes_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 31bea1ce3de1..01d8f324450a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -418,8 +418,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *    - clkdiv32k
  *    - debugss
  *    - ocp watch point
- *    - aes0
- *    - sha0
  */
 #if 0
 /*
@@ -500,25 +498,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = {
                 },
         },
 };
+#endif
 
 /*
- * 'aes' class
+ * 'aes0' class
  */
-static struct omap_hwmod_class am33xx_aes_hwmod_class = {
-        .name           = "aes",
+static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
+        .rev_offs       = 0x80,
+        .sysc_offs      = 0x84,
+        .syss_offs      = 0x88,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
+        .name           = "aes0",
+        .sysc           = &am33xx_aes0_sysc,
 };
 
 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
-        { .irq = 102 + OMAP_INTC_START, },
+        { .irq = 103 + OMAP_INTC_START, },
         { .irq = -1 },
 };
 
+static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 6, },
+        { .name = "rx", .dma_req = 5, },
+        { .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_aes0_hwmod = {
-        .name           = "aes0",
-        .class          = &am33xx_aes_hwmod_class,
+        .name           = "aes",
+        .class          = &am33xx_aes0_hwmod_class,
         .clkdm_name     = "l3_clkdm",
         .mpu_irqs       = am33xx_aes0_irqs,
-        .main_clk       = "l3_gclk",
+        .sdma_reqs      = am33xx_aes0_edma_reqs,
+        .main_clk       = "aes0_fck",
         .prcm           = {
                 .omap4  = {
                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
@@ -527,21 +541,35 @@ static struct omap_hwmod am33xx_aes0_hwmod = {
         },
 };
 
-/* sha0 */
+/* sha0 HIB2 (the 'P' (public) device) */
+static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
+        .rev_offs       = 0x100,
+        .sysc_offs      = 0x110,
+        .syss_offs      = 0x114,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
         .name           = "sha0",
+        .sysc           = &am33xx_sha0_sysc,
 };
 
 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-        { .irq = 108 + OMAP_INTC_START, },
+        { .irq = 109 + OMAP_INTC_START, },
         { .irq = -1 },
 };
 
+static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
+        { .name = "rx", .dma_req = 36, },
+        { .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_sha0_hwmod = {
-        .name           = "sha0",
+        .name           = "sham",
         .class          = &am33xx_sha0_hwmod_class,
         .clkdm_name     = "l3_clkdm",
         .mpu_irqs       = am33xx_sha0_irqs,
+        .sdma_reqs      = am33xx_sha0_edma_reqs,
         .main_clk       = "l3_gclk",
         .prcm           = {
                 .omap4  = {
@@ -551,8 +579,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
         },
 };
 
-#endif
-
 /* ocmcram */
 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
         .name = "ocmcram",
@@ -3449,6 +3475,42 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3 main -> sha0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
+        {
+                .pa_start       = 0x53100000,
+                .pa_end         = 0x53100000 + SZ_512 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_sha0_hwmod,
+        .clk            = "sha0_fck",
+        .addr           = am33xx_sha0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> AES0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
+        {
+                .pa_start       = 0x53500000,
+                .pa_end         = 0x53500000 + SZ_1M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_aes0_hwmod,
+        .clk            = "aes0_fck",
+        .addr           = am33xx_aes0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_fw__emif_fw,
         &am33xx_l3_main__emif,
@@ -3529,6 +3591,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l3_s__usbss,
         &am33xx_l4_hs__cpgmac0,
         &am33xx_cpgmac0__mdio,
+        &am33xx_l3_main__sha0,
+        &am33xx_l3_main__aes0,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5112d04e7b79..4083606ea1da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3550,6 +3550,132 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
+static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+        .sidle_shift    = 4,
+        .srst_shift     = 1,
+        .autoidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
+        .rev_offs       = 0x5c,
+        .sysc_offs      = 0x60,
+        .syss_offs      = 0x64,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap3_sham_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_sham_class = {
+        .name   = "sham",
+        .sysc   = &omap3_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
+        { .irq = 49 + OMAP_INTC_START, },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_sham_hwmod = {
+        .name           = "sham",
+        .mpu_irqs       = omap3_sham_mpu_irqs,
+        .sdma_reqs      = omap3_sham_sdma_reqs,
+        .main_clk       = "sha12_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SHA12_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_sham_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
+        {
+                .pa_start       = 0x480c3000,
+                .pa_end         = 0x480c3000 + 0x64 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_sham_hwmod,
+        .clk            = "sha12_ick",
+        .addr           = omap3xxx_sham_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> AES */
+static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
+        .sidle_shift    = 6,
+        .srst_shift     = 1,
+        .autoidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
+        .rev_offs       = 0x44,
+        .sysc_offs      = 0x48,
+        .syss_offs      = 0x4c,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap3xxx_aes_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_aes_class = {
+        .name   = "aes",
+        .sysc   = &omap3_aes_sysc,
+};
+
+static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
+        { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_aes_hwmod = {
+        .name           = "aes",
+        .sdma_reqs      = omap3_aes_sdma_reqs,
+        .main_clk       = "aes2_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_AES2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_aes_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
+        {
+                .pa_start       = 0x480c5000,
+                .pa_end         = 0x480c5000 + 0x50 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_aes_hwmod,
+        .clk            = "aes2_ick",
+        .addr           = omap3xxx_aes_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
@@ -3601,8 +3727,32 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 };
 
 /* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
+static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_sec__timer12,
+        &omap3xxx_l4_core__sham,
+        &omap3xxx_l4_core__aes,
+        NULL
+};
+
+static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_sec__timer12,
+        &omap3xxx_l4_core__sham,
+        &omap3xxx_l4_core__aes,
+        NULL
+};
+
+static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_sec__timer12,
+        /*
+         * Apparently the SHA/MD5 and AES accelerator IP blocks are
+         * only present on some AM35xx chips, and no one knows which
+         * ones.  See
+         * http://www.spinics.net/lists/arm-kernel/msg215466.html So
+         * if you need these IP blocks on an AM35xx, try uncommenting
+         * the following lines.
+         */
+        /* &omap3xxx_l4_core__sham, */
+        /* &omap3xxx_l4_core__aes, */
         NULL
 };
 
@@ -3709,7 +3859,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
 int __init omap3xxx_hwmod_init(void)
 {
         int r;
-        struct omap_hwmod_ocp_if **h = NULL;
+        struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
         unsigned int rev;
 
         omap_hwmod_init();
@@ -3719,13 +3869,6 @@ int __init omap3xxx_hwmod_init(void)
         if (r < 0)
                 return r;
 
-        /* Register GP-only hwmod links. */
-        if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
-                r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
-                if (r < 0)
-                        return r;
-        }
-
         rev = omap_rev();
 
         /*
@@ -3737,11 +3880,14 @@ int __init omap3xxx_hwmod_init(void)
             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
                 h = omap34xx_hwmod_ocp_ifs;
+                h_gp = omap34xx_gp_hwmod_ocp_ifs;
         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
                 h = am35xx_hwmod_ocp_ifs;
+                h_gp = am35xx_gp_hwmod_ocp_ifs;
         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
                    rev == OMAP3630_REV_ES1_2) {
                 h = omap36xx_hwmod_ocp_ifs;
+                h_gp = omap36xx_gp_hwmod_ocp_ifs;
         } else {
                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
                 return -EINVAL;
@@ -3751,6 +3897,14 @@ int __init omap3xxx_hwmod_init(void)
         if (r < 0)
                 return r;
 
+        /* Register GP-only hwmod links. */
+        if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
+                r = omap_hwmod_register_links(h_gp);
+                if (r < 0)
+                        return r;
+        }
+
+
         /*
          * Register hwmod links specific to certain ES levels of a
          * particular family of silicon (e.g., 34xx ES1.0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index cfcce299177c..6e04ff7065e1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -78,6 +78,8 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
 extern struct omap_hwmod omap2xxx_gpmc_hwmod;
 extern struct omap_hwmod omap2xxx_rng_hwmod;
+extern struct omap_hwmod omap2xxx_sham_hwmod;
+extern struct omap_hwmod omap2xxx_aes_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -105,6 +107,8 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 4f7379fe01e2..b3be7994a2b1 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,6 +1,14 @@
 if ARCH_SIRF
 
-menu "CSR SiRF primaII/Marco/Polo Specific Features"
+menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
+
+config ARCH_ATLAS6
+        bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
+        default y
+        select CPU_V7
+        select SIRF_IRQ
+        help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
 
 config ARCH_PRIMA2
         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 2d57aa479a7b..72efb4ff2803 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -37,6 +37,27 @@ static __init void sirfsoc_map_io(void)
         sirfsoc_map_scu();
 }
 
+#ifdef CONFIG_ARCH_ATLAS6
+static const char *atlas6_dt_match[] __initdata = {
+        "sirf,atlas6",
+        NULL
+};
+
+DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
+        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .map_io         = sirfsoc_map_io,
+        .init_irq       = sirfsoc_of_irq_init,
+        .init_time      = sirfsoc_prima2_timer_init,
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        .handle_irq     = sirfsoc_handle_irq,
+#endif
+        .init_machine   = sirfsoc_mach_init,
+        .init_late      = sirfsoc_init_late,
+        .dt_compat      = atlas6_dt_match,
+        .restart        = sirfsoc_restart,
+MACHINE_END
+#endif
+
 #ifdef CONFIG_ARCH_PRIMA2
 static const char *prima2_dt_match[] __initdata = {
        "sirf,prima2",
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 6af1aa1ef213..759846c28d12 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -509,6 +509,7 @@ int s3c2410_dma_request(enum dma_ch channel,
         chan->client = client;
         chan->in_use = 1;
         chan->peripheral = channel;
+        chan->flags = 0;
 
         local_irq_restore(flags);
 
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index bf3d1c09b085..a946b759fabd 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -210,6 +210,7 @@ static struct arizona_pdata wm5102_reva_pdata = {
         .gpio_base = CODEC_GPIO_BASE,
         .irq_active_high = true,
         .micd_pol_gpio = CODEC_GPIO_BASE + 4,
+        .micd_rate = 6,
         .gpio_defaults = {
                 [2] = 0x10000, /* AIF3TXLRCLK */
                 [3] = 0x4,     /* OPCLK */
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e1fac57514b9..b646ff4d742a 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -14,10 +14,9 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o clock-emev2.o
 
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
-smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-sh73a0.o
-smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
-smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o
+smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-scu.o
+smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o headsmp-scu.o
+smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o headsmp-scu.o
 
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 19ce885a3b43..1feb9a2286a8 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -593,29 +593,42 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 
         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
+        CLKDEV_DEV_ID("e6c80000.sci",           &mstp_clks[MSTP200]),
         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
+        CLKDEV_DEV_ID("e6c70000.sci",           &mstp_clks[MSTP201]),
         CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("e6c60000.sci",           &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.sci",           &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.sci",           &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c30000.sci",           &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6cb0000.sci",           &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-dma-engine.3",        &mstp_clks[MSTP214]),
         CLKDEV_DEV_ID("sh-dma-engine.2",        &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-dma-engine.1",        &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0",        &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
+        CLKDEV_DEV_ID("e6cd0000.sci",           &mstp_clks[MSTP222]),
         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
+        CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
 
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("e6860000.sdhi",          &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
+        CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
 
         /* ICK */
         CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1db36537255c..d9edeaf66007 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,7 +87,8 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP101, MSTP100,
+        MSTP115,
+        MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
@@ -99,6 +100,8 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */
+        [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1,  3, 0), /* DU */
         [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
         [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
         [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
@@ -156,6 +159,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
+        CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
         CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
         CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
@@ -180,6 +185,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
+        CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
 };
 
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afa5423a0f93..71843dd39e16 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
         [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
         [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
-        [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
+        [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
         [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
         [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
         [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
@@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
         CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bec4c0d9b713..7d113f898e7f 100644
--- a/arch/arm/mach-shmobile/headsmp-sh73a0.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -1,5 +1,5 @@
 /*
- * SMP support for SoC sh73a0
+ * Shared SCU setup for mach-shmobile
  *
  * Copyright (C) 2012 Bastian Hecht
  *
@@ -35,11 +35,12 @@
  * the physical address as the MMU is still turned off.
  */
         .align  12
-ENTRY(sh73a0_secondary_vector)
+ENTRY(shmobile_secondary_vector_scu)
         mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
         and     r0, r0, #3              @ mask out cpu ID
         lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
-        mov     r1, #0xf0000000         @ SCU base address
+        ldr     r1, 2f
+        ldr     r1, [r1]                @ SCU base address
         ldr     r2, [r1, #8]            @ SCU Power Status Register
         mov     r3, #3
         bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
@@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector)
 
         ldr     pc, 1f
 1:      .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(sh73a0_secondary_vector)
+2:      .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_secondary_vector_scu)
+
+        .text
+        .globl  shmobile_scu_base
+shmobile_scu_base:
+        .space  4
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
deleted file mode 100644
index a1524e3367b0..000000000000
--- a/arch/arm/mach-shmobile/hotplug.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * SMP support for R-Mobile / SH-Mobile
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/delay.h>
-#include <linux/of.h>
-#include <mach/common.h>
-#include <mach/r8a7779.h>
-#include <mach/emev2.h>
-#include <asm/cacheflush.h>
-#include <asm/mach-types.h>
-
-static cpumask_t dead_cpus;
-
-void shmobile_cpu_die(unsigned int cpu)
-{
-        /* hardware shutdown code running on the CPU that is being offlined */
-        flush_cache_all();
-        dsb();
-
-        /* notify platform_cpu_kill() that hardware shutdown is finished */
-        cpumask_set_cpu(cpu, &dead_cpus);
-
-        /* wait for SoC code in platform_cpu_kill() to shut off CPU core
-         * power. CPU bring up starts from the reset vector.
-         */
-        while (1) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
-        }
-}
-
-int shmobile_cpu_disable(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
-
-int shmobile_cpu_disable_any(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        return 0;
-}
-
-int shmobile_cpu_is_dead(unsigned int cpu)
-{
-        return cpumask_test_cpu(cpu, &dead_cpus);
-}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 362f9b2d2c02..62c04c252418 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
+extern void shmobile_secondary_vector_scu(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -30,23 +31,23 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
+extern void sh73a0_init_delay(void);
 extern void sh73a0_init_irq(void);
 extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
 extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);
-extern void sh73a0_add_early_devices_dt(void);
 extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_add_standard_devices_dt(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);
-extern void sh73a0_secondary_vector(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
 extern struct clk sh73a0_extalr_clk;
 
+extern void r8a7740_meram_workaround(void);
 extern void r8a7740_init_irq(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
@@ -55,16 +56,17 @@ extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
 
+extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq(void);
+extern void r8a7779_init_irq_dt(void);
 extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
+extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
-extern void r8a7740_meram_workaround(void);
-
 extern void r8a7779_register_twd(void);
 
 #ifdef CONFIG_SUSPEND
@@ -79,16 +81,7 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
-extern void shmobile_cpu_die(unsigned int cpu);
-extern int shmobile_cpu_disable(unsigned int cpu);
-extern int shmobile_cpu_disable_any(unsigned int cpu);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern int shmobile_cpu_is_dead(unsigned int cpu);
-#else
-static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
-#endif
-
+extern void __iomem *shmobile_scu_base;
 extern void shmobile_smp_init_cpus(unsigned int ncores);
 
 static inline void __init shmobile_init_late(void)
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 06a5da3c3050..992ed213cec1 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -5,6 +5,7 @@
 
 /* GIC */
 #define gic_spi(nr)             ((nr) + 32)
+#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
 
 /* INTCS */
 #define INTCS_VECT_BASE         0x3400
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 8807c27f71f9..f9cc4bc9c798 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
+#include <linux/irqchip.h>
 #include <mach/intc.h>
 #include <mach/r8a7779.h>
 #include <asm/mach-types.h>
@@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
         return 0; /* always allow wakeup */
 }
 
-void __init r8a7779_init_irq(void)
+static void __init r8a7779_init_irq_common(void)
 {
-        void __iomem *gic_dist_base = IOMEM(0xf0001000);
-        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
-
-        /* use GIC to handle interrupts */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 
         /* route all interrupts to ARM */
@@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void)
         __raw_writel(0xbffffffc, INT2SMSKCR3);
         __raw_writel(0x003fee3f, INT2SMSKCR4);
 }
+
+void __init r8a7779_init_irq(void)
+{
+        void __iomem *gic_dist_base = IOMEM(0xf0001000);
+        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
+
+        /* use GIC to handle interrupts */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+
+        r8a7779_init_irq_common();
+}
+
+#ifdef CONFIG_OF
+void __init r8a7779_init_irq_dt(void)
+{
+        irqchip_init();
+        r8a7779_init_irq_common();
+}
+#endif
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 91faba666d46..a81a1d804e2e 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -460,11 +460,3 @@ void __init sh73a0_init_irq(void)
         sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
         setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
 }
-
-#ifdef CONFIG_OF
-void __init sh73a0_init_irq_dt(void)
-{
-        irqchip_init();
-        gic_arch_extn.irq_set_wake = sh73a0_set_wake;
-}
-#endif
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 47662a581c0a..e4545c152722 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void)
                              ARRAY_SIZE(emev2_late_devices));
 }
 
-void __init emev2_init_delay(void)
+static void __init emev2_init_delay(void)
 {
         shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
@@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
         { }
 };
 
-void __init emev2_add_standard_devices_dt(void)
+static void __init emev2_add_standard_devices_dt(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table,
                              emev2_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index c54ff9b29fe5..042df35e71a0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -28,6 +29,7 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/r8a7779.h>
@@ -91,7 +93,7 @@ static struct plat_sci_port scif0_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(88)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x78)),
 };
 
 static struct platform_device scif0_device = {
@@ -108,7 +110,7 @@ static struct plat_sci_port scif1_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(89)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x79)),
 };
 
 static struct platform_device scif1_device = {
@@ -125,7 +127,7 @@ static struct plat_sci_port scif2_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(90)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7a)),
 };
 
 static struct platform_device scif2_device = {
@@ -142,7 +144,7 @@ static struct plat_sci_port scif3_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(91)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7b)),
 };
 
 static struct platform_device scif3_device = {
@@ -159,7 +161,7 @@ static struct plat_sci_port scif4_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(92)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7c)),
 };
 
 static struct platform_device scif4_device = {
@@ -176,7 +178,7 @@ static struct plat_sci_port scif5_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(93)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7d)),
 };
 
 static struct platform_device scif5_device = {
@@ -203,7 +205,7 @@ static struct resource tmu00_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(32),
+                .start  = gic_iid(0x40),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -233,7 +235,7 @@ static struct resource tmu01_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(33),
+                .start  = gic_iid(0x41),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -255,7 +257,7 @@ static struct resource rcar_i2c0_res[] = {
                 .end    = 0xffc70fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(79),
+                .start  = gic_iid(0x6f),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -273,7 +275,7 @@ static struct resource rcar_i2c1_res[] = {
                 .end    = 0xffc71fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(82),
+                .start  = gic_iid(0x72),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -291,7 +293,7 @@ static struct resource rcar_i2c2_res[] = {
                 .end    = 0xffc72fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(80),
+                .start  = gic_iid(0x70),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -309,7 +311,7 @@ static struct resource rcar_i2c3_res[] = {
                 .end    = 0xffc73fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(81),
+                .start  = gic_iid(0x71),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -321,7 +323,31 @@ static struct platform_device i2c3_device = {
         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 };
 
-static struct platform_device *r8a7779_early_devices[] __initdata = {
+static struct resource sata_resources[] = {
+        [0] = {
+                .name   = "rcar-sata",
+                .start  = 0xfc600000,
+                .end    = 0xfc601fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x84),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sata_device = {
+        .name           = "sata_rcar",
+        .id             = -1,
+        .resource       = sata_resources,
+        .num_resources  = ARRAY_SIZE(sata_resources),
+        .dev            = {
+                .dma_mask               = &sata_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct platform_device *r8a7779_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -330,13 +356,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
         &scif5_device,
         &tmu00_device,
         &tmu01_device,
+};
+
+static struct platform_device *r8a7779_late_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
         &i2c3_device,
-};
-
-static struct platform_device *r8a7779_late_devices[] __initdata = {
+        &sata_device,
 };
 
 void __init r8a7779_add_standard_devices(void)
@@ -349,8 +376,8 @@ void __init r8a7779_add_standard_devices(void)
 
         r8a7779_init_pm_domains();
 
-        platform_add_devices(r8a7779_early_devices,
-                            ARRAY_SIZE(r8a7779_early_devices));
+        platform_add_devices(r8a7779_devices_dt,
+                            ARRAY_SIZE(r8a7779_devices_dt));
         platform_add_devices(r8a7779_late_devices,
                             ARRAY_SIZE(r8a7779_late_devices));
 }
@@ -367,8 +394,8 @@ void __init r8a7779_earlytimer_init(void)
 
 void __init r8a7779_add_early_devices(void)
 {
-        early_platform_add_devices(r8a7779_early_devices,
-                                   ARRAY_SIZE(r8a7779_early_devices));
+        early_platform_add_devices(r8a7779_devices_dt,
+                                   ARRAY_SIZE(r8a7779_devices_dt));
 
         /* Early serial console setup is not included here due to
          * memory map collisions. The SCIF serial ports in r8a7779
@@ -386,3 +413,40 @@ void __init r8a7779_add_early_devices(void)
          * command line in case of the marzen board.
          */
 }
+
+#ifdef CONFIG_USE_OF
+void __init r8a7779_init_delay(void)
+{
+        shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
+}
+
+static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
+        {},
+};
+
+void __init r8a7779_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        r8a7779_clock_init();
+
+        platform_add_devices(r8a7779_devices_dt,
+                             ARRAY_SIZE(r8a7779_devices_dt));
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             r8a7779_auxdata_lookup, NULL);
+}
+
+static const char *r8a7779_compat_dt[] __initdata = {
+        "renesas,r8a7779",
+        NULL,
+};
+
+DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = r8a7779_init_irq_dt,
+        .init_machine   = r8a7779_add_standard_devices_dt,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = r8a7779_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index bdab575f88bc..2257a915746d 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -810,7 +811,7 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
+static struct platform_device *sh73a0_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -847,8 +848,8 @@ void __init sh73a0_add_standard_devices(void)
         /* Clear software reset bit on SY-DMAC module */
         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                            ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                            ARRAY_SIZE(sh73a0_devices_dt));
         platform_add_devices(sh73a0_early_devices,
                             ARRAY_SIZE(sh73a0_early_devices));
         platform_add_devices(sh73a0_late_devices,
@@ -867,8 +868,8 @@ void __init sh73a0_earlytimer_init(void)
 
 void __init sh73a0_add_early_devices(void)
 {
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
+        early_platform_add_devices(sh73a0_devices_dt,
+                                   ARRAY_SIZE(sh73a0_devices_dt));
         early_platform_add_devices(sh73a0_early_devices,
                                    ARRAY_SIZE(sh73a0_early_devices));
 
@@ -878,23 +879,9 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-/* Please note that the clock initialisation shcheme used in
- * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
- * does not work with SMP as there is a yet to be resolved lock-up in
- * workqueue initialisation.
- *
- * CONFIG_SMP should be disabled when using this code.
- */
-
-void __init sh73a0_add_early_devices_dt(void)
+void __init sh73a0_init_delay(void)
 {
         shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
 }
 
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
@@ -906,8 +893,8 @@ void __init sh73a0_add_standard_devices_dt(void)
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                             ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                             ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
 }
@@ -918,10 +905,11 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
+        .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
-        .init_early     = sh73a0_add_early_devices_dt,
+        .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = sh73a0_init_irq_dt,
+        .init_irq       = irqchip_init,
         .init_machine   = sh73a0_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = sh73a0_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 384e27dd3601..e38691b4d0dd 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -27,90 +27,35 @@
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <asm/cacheflush.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static DEFINE_SPINLOCK(scu_lock);
-static void __iomem *scu_base;
-
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        unsigned long tmp;
-
-        /* we assume this code is running on a different cpu
-         * than the one that is changing coherency setting */
-        spin_lock(&scu_lock);
-        tmp = readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        writel(tmp, scu_base + 8);
-        spin_unlock(&scu_lock);
-
-}
-
-static unsigned int __init emev2_get_core_count(void)
-{
-        if (!scu_base) {
-                scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
-                emev2_clock_init(); /* need ioremapped SMU */
-        }
-
-        WARN_ON_ONCE(!scu_base);
-
-        return scu_base ? scu_get_core_count(scu_base) : 1;
-}
-
-static int emev2_platform_cpu_kill(unsigned int cpu)
-{
-        return 0; /* not supported yet */
-}
-
-static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return emev2_platform_cpu_kill(cpu);
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
 static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        cpu = cpu_logical_map(cpu);
-
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
-        /* Tell ROM loader about our vector (in headsmp.S) */
-        emev2_set_boot_vector(__pa(shmobile_secondary_vector));
-
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
         return 0;
 }
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
+        scu_enable(shmobile_scu_base);
 
-        scu_enable(scu_base);
+        /* Tell ROM loader about our vector (in headsmp-scu.S) */
+        emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
 
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init emev2_smp_init_cpus(void)
 {
-        unsigned int ncores = emev2_get_core_count();
+        unsigned int ncores;
+
+        /* setup EMEV2 specific SCU base */
+        shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
+        emev2_clock_init(); /* need ioremapped SMU */
+
+        ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
 
         shmobile_smp_init_cpus(ncores);
 }
@@ -119,9 +64,4 @@ struct smp_operations emev2_smp_ops __initdata = {
         .smp_init_cpus          = emev2_smp_init_cpus,
         .smp_prepare_cpus       = emev2_smp_prepare_cpus,
         .smp_boot_secondary     = emev2_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_kill               = emev2_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
-#endif
 };
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 994906560edd..a853bf182ed5 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -25,11 +25,13 @@
 #include <linux/delay.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
+#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
 #define AVECR IOMEM(0xfe700040)
+#define R8A7779_SCU_BASE 0xf0000000
 
 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
@@ -55,44 +57,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
         [3] = &r8a7779_ch_cpu3,
 };
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
-
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
-
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
 void __init r8a7779_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        spin_lock(&scu_lock);
-        tmp = __raw_readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        spin_unlock(&scu_lock);
-
-        /* disable cache coherency after releasing the lock */
-        __raw_writel(tmp, scu_base + 8);
-}
-
-static unsigned int __init r8a7779_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
 static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
         struct r8a7779_pm_ch *ch = NULL;
@@ -100,9 +72,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
 
         cpu = cpu_logical_map(cpu);
 
-        /* disable cache coherency */
-        modify_scu_cpu_psr(3 << (cpu * 8), 0);
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -112,25 +81,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
         return ret ? ret : 1;
 }
 
-static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return r8a7779_platform_cpu_kill(cpu);
-
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
 static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         struct r8a7779_pm_ch *ch = NULL;
@@ -138,9 +88,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
         cpu = cpu_logical_map(cpu);
 
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -152,15 +99,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
+        scu_enable(shmobile_scu_base);
 
-        scu_enable(scu_base_addr());
+        /* Map the reset vector (in headsmp-scu.S) */
+        __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
 
-        /* Map the reset vector (in headsmp.S) */
-        __raw_writel(__pa(shmobile_secondary_vector), AVECR);
-
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 
         r8a7779_pm_init();
 
@@ -172,10 +117,60 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 
 static void __init r8a7779_smp_init_cpus(void)
 {
-        unsigned int ncores = r8a7779_get_core_count();
+        /* setup r8a7779 specific SCU base */
+        shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
+
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
+}
 
-        shmobile_smp_init_cpus(ncores);
+#ifdef CONFIG_HOTPLUG_CPU
+static int r8a7779_scu_psr_core_disabled(int cpu)
+{
+        unsigned long mask = 3 << (cpu * 8);
+
+        if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
+                return 1;
+
+        return 0;
+}
+
+static int r8a7779_cpu_kill(unsigned int cpu)
+{
+        int k;
+
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (r8a7779_scu_psr_core_disabled(cpu))
+                        return r8a7779_platform_cpu_kill(cpu);
+
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+static void r8a7779_cpu_die(unsigned int cpu)
+{
+        dsb();
+        flush_cache_all();
+
+        /* disable cache coherency */
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
+
+        /* Endless loop until power off from r8a7779_cpu_kill() */
+        while (1)
+                cpu_do_idle();
+}
+
+static int r8a7779_cpu_disable(unsigned int cpu)
+{
+        /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
+        return cpu == 0 ? -EPERM : 0;
 }
+#endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_init_cpus          = r8a7779_smp_init_cpus,
@@ -183,7 +178,7 @@ struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_boot_secondary     = r8a7779_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = r8a7779_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
+        .cpu_die                = r8a7779_cpu_die,
+        .cpu_disable            = r8a7779_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index d0f9aca22477..bf79626ee5a4 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -38,26 +38,16 @@
 
 #define PSTR_SHUTDOWN_MODE      3
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
+#define SH73A0_SCU_BASE 0xf0000000
 
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
 void __init sh73a0_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static unsigned int __init sh73a0_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
 static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         cpu = cpu_logical_map(cpu);
@@ -72,21 +62,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-        scu_enable(scu_base_addr());
+        scu_enable(shmobile_scu_base);
 
-        /* Map the reset vector (in headsmp-sh73a0.S) */
+        /* Map the reset vector (in headsmp-scu.S) */
         __raw_writel(0, APARMBAREA);      /* 4k */
-        __raw_writel(__pa(sh73a0_secondary_vector), SBAR);
+        __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
 
         /* enable cache coherency on booting CPU */
-        scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init sh73a0_smp_init_cpus(void)
 {
-        unsigned int ncores = sh73a0_get_core_count();
+        /* setup sh73a0 specific SCU base */
+        shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
 
-        shmobile_smp_init_cpus(ncores);
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -122,11 +113,16 @@ static void sh73a0_cpu_die(unsigned int cpu)
         flush_cache_all();
 
         /* Set power off mode. This takes the CPU out of the MP cluster */
-        scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
 
         /* Enter shutdown mode */
         cpu_do_idle();
 }
+
+static int sh73a0_cpu_disable(unsigned int cpu)
+{
+        return 0; /* CPU0 and CPU1 supported */
+}
 #endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations sh73a0_smp_ops __initdata = {
@@ -136,6 +132,6 @@ struct smp_operations sh73a0_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = sh73a0_cpu_kill,
         .cpu_die                = sh73a0_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable_any,
+        .cpu_disable            = sh73a0_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 315edff610f2..572b8f719ffb 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -20,12 +20,23 @@
 #ifndef __MACH_CORE_H
 #define __MACH_CORE_H
 
+#define SOCFPGA_RSTMGR_CTRL     0x04
+#define SOCFPGA_RSTMGR_MODPERRST        0x14
+#define SOCFPGA_RSTMGR_BRGMODRST        0x1c
+
+/* System Manager bits */
+#define RSTMGR_CTRL_SWCOLDRSTREQ        0x1     /* Cold Reset */
+#define RSTMGR_CTRL_SWWARMRSTREQ        0x2     /* Warm Reset */
+
 extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);
 extern void socfpga_sysmgr_init(void);
 
+extern void __iomem *sys_manager_base_addr;
+extern void __iomem *rst_manager_base_addr;
+
 extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
 
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index ca14d1d5ac7f..b51ce8c7929d 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -29,9 +29,6 @@
 
 #include "core.h"
 
-extern void __iomem *sys_manager_base_addr;
-extern void __iomem *rst_manager_base_addr;
-
 static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 1042c023cf24..46a051359f02 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -15,6 +15,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/dw_apb_timer.h>
+#include <linux/clk-provider.h>
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -29,6 +30,7 @@
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
 void __iomem *rst_manager_base_addr;
+void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 
 static struct map_desc scu_io_desc __initdata = {
@@ -77,6 +79,9 @@ void __init socfpga_sysmgr_init(void)
 
         np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
         rst_manager_base_addr = of_iomap(np, 0);
+
+        np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
+        clk_mgr_base_addr = of_iomap(np, 0);
 }
 
 static void __init socfpga_init_irq(void)
@@ -87,13 +92,22 @@ static void __init socfpga_init_irq(void)
 
 static void socfpga_cyclone5_restart(char mode, const char *cmd)
 {
-        /* TODO: */
+        u32 temp;
+
+        temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
+
+        if (mode == 'h')
+                temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
+        else
+                temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
 
 static void __init socfpga_cyclone5_init(void)
 {
         l2x0_of_init(0, ~0UL);
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_clk_init(NULL);
         socfpga_init_clocks();
 }
 
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c1970005f805..b78f0d71b328 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f0315c95c76d..eb1f3c8c74cc 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
+#include "irq.h"
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
@@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = {
 void __init tegra_dt_init_irq(void)
 {
         tegra_clocks_init();
+        tegra_pmc_init();
         tegra_init_irq();
         irqchip_init();
+        tegra_legacy_irq_syscore_init();
 }
 #endif
 
@@ -100,12 +103,12 @@ void __init tegra_init_early(void)
         tegra_apb_io_init();
         tegra_init_fuse();
         tegra_init_cache();
-        tegra_pmc_init();
         tegra_powergate_init();
         tegra_hotplug_init();
 }
 
 void __init tegra_init_late(void)
 {
+        tegra_init_suspend();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 590ec25855dd..0cdba8de8c77 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -131,10 +131,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         while (tegra20_cpu_is_resettable_soon())
                 cpu_relax();
 
@@ -143,7 +139,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 9387daeeadc8..3cf9aca5f3ea 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -69,10 +69,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         /* All CPUs entering LP2 is not working.
          * Don't let CPU0 enter LP2 when any secondary CPU is online.
          */
@@ -83,7 +79,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f7db0782a6b6..e035cd284a6e 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/fuse.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -137,6 +138,9 @@ void tegra_init_fuse(void)
                 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
                 tegra_init_speedo_data = &tegra30_init_speedo_data;
                 break;
+        case TEGRA114:
+                tegra_init_speedo_data = &tegra114_init_speedo_data;
+                break;
         default:
                 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index da78434678c7..aacc00d05980 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void);
 static inline void tegra30_init_speedo_data(void) {}
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_init_speedo_data(void);
+#else
+static inline void tegra114_init_speedo_data(void) {}
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1952e82797cc..0de4eed1493d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,7 +4,7 @@
  * Author:
  *      Colin Cross <ccross@android.com>
  *
- * Copyright (C) 2010, NVIDIA Corporation
+ * Copyright (C) 2010,2013, NVIDIA Corporation
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/syscore_ops.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -43,6 +44,7 @@
 #define ICTLR_COP_IEP_CLASS     0x3c
 
 #define FIRST_LEGACY_IRQ 32
+#define TEGRA_MAX_NUM_ICTLRS    5
 
 #define SGI_MASK 0xFFFF
 
@@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
         IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
+#ifdef CONFIG_PM_SLEEP
+static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+
 bool tegra_pending_sgi(void)
 {
         u32 pending_set;
@@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
         return 1;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+        u32 irq = d->irq;
+        u32 index, mask;
+
+        if (irq < FIRST_LEGACY_IRQ ||
+                irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
+                return -EINVAL;
+
+        index = ((irq - FIRST_LEGACY_IRQ) / 32);
+        mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
+        if (enable)
+                ictlr_wake_mask[index] |= mask;
+        else
+                ictlr_wake_mask[index] &= ~mask;
+
+        return 0;
+}
+
+static int tegra_legacy_irq_suspend(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                /* Save interrupt state */
+                cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
+                cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
+                cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
+                cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
+
+                /* Disable COP interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+
+                /* Disable CPU interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+
+                /* Enable the wakeup sources of ictlr */
+                writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
+        }
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void tegra_legacy_irq_resume(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+                writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
+                writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+                writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
+        }
+        local_irq_restore(flags);
+}
+
+static struct syscore_ops tegra_legacy_irq_syscore_ops = {
+        .suspend = tegra_legacy_irq_suspend,
+        .resume = tegra_legacy_irq_resume,
+};
+
+int tegra_legacy_irq_syscore_init(void)
+{
+        register_syscore_ops(&tegra_legacy_irq_syscore_ops);
+
+        return 0;
+}
+#else
+#define tegra_set_wake NULL
+#endif
+
 void __init tegra_init_irq(void)
 {
         int i;
@@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_mask = tegra_mask;
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
+        gic_arch_extn.irq_set_wake = tegra_set_wake;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
         /*
          * Check if there is a devicetree present, since the GIC will be
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
index 5142649bba05..bc05ce5613fb 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/arch/arm/mach-tegra/irq.h
@@ -19,4 +19,10 @@
 
 bool tegra_pending_sgi(void);
 
+#ifdef CONFIG_PM_SLEEP
+int tegra_legacy_irq_syscore_init(void);
+#else
+static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index c31db797e199..0c4963bd4b44 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -138,6 +138,12 @@ remove_clamps:
         return 0;
 }
 
+static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        cpu = cpu_logical_map(cpu);
+        return tegra_pmc_cpu_power_on(cpu);
+}
+
 static int __cpuinit tegra_boot_secondary(unsigned int cpu,
                                           struct task_struct *idle)
 {
@@ -145,6 +151,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu,
                 return tegra20_boot_secondary(cpu, idle);
         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
                 return tegra30_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                return tegra114_boot_secondary(cpu, idle);
 
         return -EINVAL;
 }
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 891fb70d0aa7..45cf52c7e528 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -22,7 +22,7 @@
 #include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/cpu_pm.h>
-#include <linux/clk.h>
+#include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/clk/tegra.h>
 
@@ -37,52 +37,13 @@
 #include "reset.h"
 #include "flowctrl.h"
 #include "fuse.h"
+#include "pmc.h"
 #include "sleep.h"
 
-#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
-
-#define PMC_CTRL                0x0
-#define PMC_CPUPWRGOOD_TIMER    0xc8
-#define PMC_CPUPWROFF_TIMER     0xcc
-
 #ifdef CONFIG_PM_SLEEP
 static DEFINE_SPINLOCK(tegra_lp2_lock);
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-static struct clk *tegra_pclk;
 void (*tegra_tear_down_cpu)(void);
 
-static void set_power_timers(unsigned long us_on, unsigned long us_off)
-{
-        unsigned long long ticks;
-        unsigned long long pclk;
-        unsigned long rate;
-        static unsigned long tegra_last_pclk;
-
-        if (tegra_pclk == NULL) {
-                tegra_pclk = clk_get_sys(NULL, "pclk");
-                WARN_ON(IS_ERR(tegra_pclk));
-        }
-
-        rate = clk_get_rate(tegra_pclk);
-
-        if (WARN_ON_ONCE(rate <= 0))
-                pclk = 100000000;
-        else
-                pclk = rate;
-
-        if ((rate != tegra_last_pclk)) {
-                ticks = (us_on * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
-
-                ticks = (us_off * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
-                wmb();
-        }
-        tegra_last_pclk = pclk;
-}
-
 /*
  * restore_cpu_complex
  *
@@ -178,16 +139,9 @@ static int tegra_sleep_cpu(unsigned long v2p)
         return 0;
 }
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+void tegra_idle_lp2_last(void)
 {
-        u32 mode;
-
-        /* Only the last cpu down does the final suspend steps */
-        mode = readl(pmc + PMC_CTRL);
-        mode |= TEGRA_POWER_CPU_PWRREQ_OE;
-        writel(mode, pmc + PMC_CTRL);
-
-        set_power_timers(cpu_on_time, cpu_off_time);
+        tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
 
         cpu_cluster_pm_enter();
         suspend_cpu_complex();
@@ -197,4 +151,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
         restore_cpu_complex();
         cpu_cluster_pm_exit();
 }
+
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        /* Tegra114 didn't support any suspending mode yet. */
+        if (tegra_chip_id == TEGRA114)
+                return TEGRA_SUSPEND_NONE;
+
+        /*
+         * The Tegra devices only support suspending to LP2 currently.
+         */
+        if (mode > TEGRA_SUSPEND_LP2)
+                return TEGRA_SUSPEND_LP2;
+
+        return mode;
+}
+
+static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
+        [TEGRA_SUSPEND_NONE] = "none",
+        [TEGRA_SUSPEND_LP2] = "LP2",
+        [TEGRA_SUSPEND_LP1] = "LP1",
+        [TEGRA_SUSPEND_LP0] = "LP0",
+};
+
+static int __cpuinit tegra_suspend_enter(suspend_state_t state)
+{
+        enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
+
+        if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
+                    mode >= TEGRA_MAX_SUSPEND_MODE))
+                return -EINVAL;
+
+        pr_info("Entering suspend state %s\n", lp_state[mode]);
+
+        tegra_pmc_pm_set(mode);
+
+        local_fiq_disable();
+
+        suspend_cpu_complex();
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_set_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_clear_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+        restore_cpu_complex();
+
+        local_fiq_enable();
+
+        return 0;
+}
+
+static const struct platform_suspend_ops tegra_suspend_ops = {
+        .valid          = suspend_valid_only_mem,
+        .enter          = tegra_suspend_enter,
+};
+
+void __init tegra_init_suspend(void)
+{
+        if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
+                return;
+
+        tegra_pmc_suspend_init();
+
+        suspend_set_ops(&tegra_suspend_ops);
+}
 #endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 787335cc964c..778a4aa7c3fa 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,6 +21,8 @@
 #ifndef _MACH_TEGRA_PM_H_
 #define _MACH_TEGRA_PM_H_
 
+#include "pmc.h"
+
 extern unsigned long l2x0_saved_regs_addr;
 
 void save_cpu_arch_register(void);
@@ -29,7 +31,20 @@ void restore_cpu_arch_register(void);
 void tegra_clear_cpu_in_lp2(int phy_cpu_id);
 bool tegra_set_cpu_in_lp2(int phy_cpu_id);
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
 
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode);
+void tegra_init_suspend(void);
+#else
+static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        return TEGRA_SUSPEND_NONE;
+}
+static inline void tegra_init_suspend(void) {}
+#endif
+
 #endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index b30e921cc3a9..32360e540ce6 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -16,10 +16,20 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+#include "fuse.h"
+#include "pm.h"
+#include "pmc.h"
+#include "sleep.h"
+
+#define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
+#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
+#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
+
 #define PMC_CTRL                        0x0
 #define PMC_CTRL_INTR_LOW               (1 << 17)
 #define PMC_PWRGATE_TOGGLE              0x30
@@ -27,6 +37,9 @@
 #define PMC_REMOVE_CLAMPING             0x34
 #define PMC_PWRGATE_STATUS              0x38
 
+#define PMC_CPUPWRGOOD_TIMER    0xc8
+#define PMC_CPUPWROFF_TIMER     0xcc
+
 #define TEGRA_POWERGATE_PCIE    3
 #define TEGRA_POWERGATE_VDEC    4
 #define TEGRA_POWERGATE_CPU1    9
@@ -43,6 +56,23 @@ static DEFINE_SPINLOCK(tegra_powergate_lock);
 
 static void __iomem *tegra_pmc_base;
 static bool tegra_pmc_invert_interrupt;
+static struct clk *tegra_pclk;
+
+struct pmc_pm_data {
+        u32 cpu_good_time;      /* CPU power good time in uS */
+        u32 cpu_off_time;       /* CPU power off time in uS */
+        u32 core_osc_time;      /* Core power good osc time in uS */
+        u32 core_pmu_time;      /* Core power good pmu time in uS */
+        u32 core_off_time;      /* Core power off time in uS */
+        bool corereq_high;      /* Core power request active-high */
+        bool sysclkreq_high;    /* System clock request active-high */
+        bool combined_req;      /* Combined pwr req for CPU & Core */
+        bool cpu_pwr_good_en;   /* CPU power good signal is enabled */
+        u32 lp0_vec_phy_addr;   /* The phy addr of LP0 warm boot code */
+        u32 lp0_vec_size;       /* The size of LP0 warm boot code */
+        enum tegra_suspend_mode suspend_mode;
+};
+static struct pmc_pm_data pmc_pm_data;
 
 static inline u32 tegra_pmc_readl(u32 reg)
 {
@@ -133,6 +163,70 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
         return tegra_pmc_powergate_remove_clamping(id);
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
+{
+        unsigned long long ticks;
+        unsigned long long pclk;
+        static unsigned long tegra_last_pclk;
+
+        if (WARN_ON_ONCE(rate <= 0))
+                pclk = 100000000;
+        else
+                pclk = rate;
+
+        if ((rate != tegra_last_pclk)) {
+                ticks = (us_on * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
+
+                ticks = (us_off * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
+                wmb();
+        }
+        tegra_last_pclk = pclk;
+}
+
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+        return pmc_pm_data.suspend_mode;
+}
+
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
+{
+        u32 reg;
+        unsigned long rate = 0;
+
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        reg &= ~TEGRA_POWER_EFFECT_LP0;
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                rate = clk_get_rate(tegra_pclk);
+                break;
+        default:
+                break;
+        }
+
+        set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
+                         rate);
+
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+
+void tegra_pmc_suspend_init(void)
+{
+        u32 reg;
+
+        /* Always enable CPU power request */
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+#endif
+
 static const struct of_device_id matches[] __initconst = {
         { .compatible = "nvidia,tegra114-pmc" },
         { .compatible = "nvidia,tegra30-pmc" },
@@ -143,6 +237,10 @@ static const struct of_device_id matches[] __initconst = {
 static void tegra_pmc_parse_dt(void)
 {
         struct device_node *np;
+        u32 prop;
+        enum tegra_suspend_mode suspend_mode;
+        u32 core_good_time[2] = {0, 0};
+        u32 lp0_vec[2] = {0, 0};
 
         np = of_find_matching_node(NULL, matches);
         BUG_ON(!np);
@@ -151,6 +249,70 @@ static void tegra_pmc_parse_dt(void)
 
         tegra_pmc_invert_interrupt = of_property_read_bool(np,
                                      "nvidia,invert-interrupt");
+        tegra_pclk = of_clk_get_by_name(np, "pclk");
+        WARN_ON(IS_ERR(tegra_pclk));
+
+        /* Grabbing the power management configurations */
+        if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        } else {
+                switch (prop) {
+                case 0:
+                        suspend_mode = TEGRA_SUSPEND_LP0;
+                        break;
+                case 1:
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+                        break;
+                case 2:
+                        suspend_mode = TEGRA_SUSPEND_LP2;
+                        break;
+                default:
+                        suspend_mode = TEGRA_SUSPEND_NONE;
+                        break;
+                }
+        }
+        suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_good_time = prop;
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_off_time = prop;
+
+        if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
+                        core_good_time, ARRAY_SIZE(core_good_time)))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_osc_time = core_good_time[0];
+        pmc_pm_data.core_pmu_time = core_good_time[1];
+
+        if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
+                                 &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_off_time = prop;
+
+        pmc_pm_data.corereq_high = of_property_read_bool(np,
+                                "nvidia,core-power-req-active-high");
+
+        pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
+                                "nvidia,sys-clock-req-active-high");
+
+        pmc_pm_data.combined_req = of_property_read_bool(np,
+                                "nvidia,combined-power-req");
+
+        pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
+                                "nvidia,cpu-pwr-good-en");
+
+        if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
+                                       ARRAY_SIZE(lp0_vec)))
+                if (suspend_mode == TEGRA_SUSPEND_LP0)
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+
+        pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
+        pmc_pm_data.lp0_vec_size = lp0_vec[1];
+
+        pmc_pm_data.suspend_mode = suspend_mode;
 }
 
 void __init tegra_pmc_init(void)
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 7d44710368be..e1c2df272f7d 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,20 @@
 #ifndef __MACH_TEGRA_PMC_H
 #define __MACH_TEGRA_PMC_H
 
+enum tegra_suspend_mode {
+        TEGRA_SUSPEND_NONE = 0,
+        TEGRA_SUSPEND_LP2,      /* CPU voltage off */
+        TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
+        TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
+        TEGRA_MAX_SUSPEND_MODE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
+void tegra_pmc_suspend_init(void);
+#endif
+
 bool tegra_pmc_cpu_is_powered(int cpuid);
 int tegra_pmc_cpu_power_on(int cpuid);
 int tegra_pmc_cpu_remove_clamping(int cpuid);
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 27232c901a22..84deeab23ee7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -33,6 +33,8 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
 
 #include <asm/mach-types.h>
@@ -42,6 +44,7 @@
 
 #include "board.h"
 #include "common.h"
+#include "fuse.h"
 #include "iomap.h"
 
 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
@@ -80,12 +83,36 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 
 static void __init tegra_dt_init(void)
 {
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        struct device *parent = NULL;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                goto out;
+
+        soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->family);
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+                goto out;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+
         /*
          * Finished with the static registrations now; fill in the missing
          * devices
          */
+out:
         of_platform_populate(NULL, of_default_bus_match_table,
-                                tegra20_auxdata_lookup, NULL);
+                                tegra20_auxdata_lookup, parent);
 }
 
 static void __init trimslice_init(void)
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c
new file mode 100644
index 000000000000..5218d4853cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114_speedo.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CORE_PROCESS_CORNERS_NUM        2
+#define CPU_PROCESS_CORNERS_NUM         2
+
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+        {1123,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+        {1695,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
+{
+        u32 tmp;
+
+        switch (sku) {
+        case 0x00:
+        case 0x10:
+        case 0x05:
+        case 0x06:
+                tegra_cpu_speedo_id = 1;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+
+        case 0x03:
+        case 0x04:
+                tegra_cpu_speedo_id = 2;
+                tegra_soc_speedo_id = 1;
+                *threshold = THRESHOLD_INDEX_1;
+                break;
+
+        default:
+                pr_err("Tegra114 Unknown SKU %d\n", sku);
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+        }
+
+        if (rev == TEGRA_REVISION_A01) {
+                tmp = tegra_fuse_readl(0x270) << 1;
+                tmp |= tegra_fuse_readl(0x26c);
+                if (!tmp)
+                        tegra_cpu_speedo_id = 0;
+        }
+}
+
+void tegra114_init_speedo_data(void)
+{
+        u32 cpu_speedo_val;
+        u32 core_speedo_val;
+        int threshold;
+        int i;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+
+        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
+
+        cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
+        core_speedo_val = tegra_fuse_readl(0x134);
+
+        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
+                if (cpu_speedo_val < cpu_process_speedos[threshold][i])
+                        break;
+        tegra_cpu_process_id = i;
+
+        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
+                if (core_speedo_val < core_process_speedos[threshold][i])
+                        break;
+        tegra_core_process_id = i;
+}
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 1c1609da76ce..f815efe54c73 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void)
         /* Unlock before init */
         ux500_l2x0_unlock();
 
-        /* DB9540's L2 has 128KB way size */
-        if (cpu_is_u9540())
+        /* DBx540's L2 has 128KB way size */
+        if (cpu_is_ux540_family())
                 /* 128KB way size */
                 aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
         else
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
index bdf6dadf8790..a030e7301da8 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/plat-samsung/s5p-sleep.S
@@ -25,6 +25,9 @@
 #include <asm/asm-offsets.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#define CPU_MASK        0xff0ffff0
+#define CPU_CORTEX_A9   0x410fc090
+
 /*
  *       The following code is located into the .data section. This is to
  *       allow l2x0_regs_phys to be accessed with a relative load while we
@@ -51,6 +54,12 @@
 
 ENTRY(s3c_cpu_resume)
 #ifdef CONFIG_CACHE_L2X0
+        mrc     p15, 0, r0, c0, c0, 0
+        ldr     r1, =CPU_MASK
+        and     r0, r0, r1
+        ldr     r1, =CPU_CORTEX_A9
+        cmp     r0, r1
+        bne     resume_l2on
         adr     r0, l2x0_regs_phys
         ldr     r0, [r0]
         ldr     r1, [r0, #L2X0_R_PHY_BASE]
diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c
index 147459327601..66df315990a7 100644
--- a/arch/arm/plat-samsung/setup-mipiphy.c
+++ b/arch/arm/plat-samsung/setup-mipiphy.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -50,8 +51,10 @@ int s5p_csis_phy_enable(int id, bool on)
 {
         return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN);
 }
+EXPORT_SYMBOL(s5p_csis_phy_enable);
 
 int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
 {
         return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN);
 }
+EXPORT_SYMBOL(s5p_dsim_phy_enable);