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-rw-r--r--arch/arm/boot/dts/omap3430es1-clocks.dtsi6
-rw-r--r--arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi6
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
index 6f31954636a1..4c22f3a7f813 100644
--- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -152,7 +152,7 @@
152 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; 152 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
153 }; 153 };
154 154
155 dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 { 155 dss1_alwon_fck: dss1_alwon_fck_3430es1 {
156 #clock-cells = <0>; 156 #clock-cells = <0>;
157 compatible = "ti,gate-clock"; 157 compatible = "ti,gate-clock";
158 clocks = <&dpll4_m4x2_ck>; 158 clocks = <&dpll4_m4x2_ck>;
@@ -161,7 +161,7 @@
161 ti,set-rate-parent; 161 ti,set-rate-parent;
162 }; 162 };
163 163
164 dss_ick_3430es1: dss_ick_3430es1 { 164 dss_ick: dss_ick_3430es1 {
165 #clock-cells = <0>; 165 #clock-cells = <0>;
166 compatible = "ti,omap3-no-wait-interface-clock"; 166 compatible = "ti,omap3-no-wait-interface-clock";
167 clocks = <&l4_ick>; 167 clocks = <&l4_ick>;
@@ -184,7 +184,7 @@
184 dss_clkdm: dss_clkdm { 184 dss_clkdm: dss_clkdm {
185 compatible = "ti,clockdomain"; 185 compatible = "ti,clockdomain";
186 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, 186 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
187 <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>; 187 <&dss1_alwon_fck>, <&dss_ick>;
188 }; 188 };
189 189
190 d2d_clkdm: d2d_clkdm { 190 d2d_clkdm: d2d_clkdm {
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index af9ae5346bf2..080fb3f4e429 100644
--- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -160,7 +160,7 @@
160 ti,bit-shift = <30>; 160 ti,bit-shift = <30>;
161 }; 161 };
162 162
163 dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 { 163 dss1_alwon_fck: dss1_alwon_fck_3430es2 {
164 #clock-cells = <0>; 164 #clock-cells = <0>;
165 compatible = "ti,dss-gate-clock"; 165 compatible = "ti,dss-gate-clock";
166 clocks = <&dpll4_m4x2_ck>; 166 clocks = <&dpll4_m4x2_ck>;
@@ -169,7 +169,7 @@
169 ti,set-rate-parent; 169 ti,set-rate-parent;
170 }; 170 };
171 171
172 dss_ick_3430es2: dss_ick_3430es2 { 172 dss_ick: dss_ick_3430es2 {
173 #clock-cells = <0>; 173 #clock-cells = <0>;
174 compatible = "ti,omap3-dss-interface-clock"; 174 compatible = "ti,omap3-dss-interface-clock";
175 clocks = <&l4_ick>; 175 clocks = <&l4_ick>;
@@ -216,7 +216,7 @@
216 dss_clkdm: dss_clkdm { 216 dss_clkdm: dss_clkdm {
217 compatible = "ti,clockdomain"; 217 compatible = "ti,clockdomain";
218 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, 218 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
219 <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; 219 <&dss1_alwon_fck>, <&dss_ick>;
220 }; 220 };
221 221
222 core_l4_clkdm: core_l4_clkdm { 222 core_l4_clkdm: core_l4_clkdm {