734 files changed, 44564 insertions, 15629 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4039a133006e..d8d253285a94 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -255,6 +255,7 @@ config ARCH_EP93XX
         select ARM_AMBA
         select ARM_VIC
         select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           This enables support for the Cirrus EP93xx series of CPUs.
 
@@ -377,15 +378,17 @@ config ARCH_MXC
         help
           Support for Freescale MXC/iMX-based family of processors
 
-config ARCH_ORION
+config ARCH_ORION5X
         bool "Marvell Orion"
         depends on MMU
         select PCI
         select GENERIC_GPIO
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
         help
-          Support for Marvell Orion System on Chip family.
+          Support for the following Marvell Orion 5x series SoCs:
+          Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
 
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
@@ -422,10 +425,15 @@ config ARCH_SA1100
         bool "SA1100-based"
         select ISA
         select ARCH_DISCONTIGMEM_ENABLE
+        select ARCH_SPARSEMEM_ENABLE
+        select ARCH_SELECT_MEMORY_MODEL
         select ARCH_MTD_XIP
         select GENERIC_GPIO
         select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select TICK_ONESHOT
         select HAVE_IDE
+        select HAVE_GPIO_LIB
         help
           Support for StrongARM 11x0 based boards.
 
@@ -468,6 +476,7 @@ config ARCH_DAVINCI
 config ARCH_OMAP
         bool "TI OMAP"
         select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         help
@@ -516,7 +525,7 @@ source "arch/arm/mach-omap1/Kconfig"
 
 source "arch/arm/mach-omap2/Kconfig"
 
-source "arch/arm/mach-orion/Kconfig"
+source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
@@ -563,6 +572,9 @@ config ARCH_ACORN
 config PLAT_IOP
         bool
 
+config PLAT_ORION
+        bool
+
 source arch/arm/mm/Kconfig
 
 config IWMMXT
@@ -650,7 +662,7 @@ source "kernel/time/Kconfig"
 
 config SMP
         bool "Symmetric Multi-Processing (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP
+        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
         help
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -683,7 +695,7 @@ config HOTPLUG_CPU
 
 config LOCAL_TIMERS
         bool "Use local timer interrupts"
-        depends on SMP && REALVIEW_EB_ARM11MP
+        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
         default y
         help
           Enable support for local timers on SMP platforms, rather then the
@@ -774,6 +786,12 @@ config ARCH_DISCONTIGMEM_ENABLE
           or have huge holes in the physical address space for other reasons.
           See <file:Documentation/vm/numa> for more.
 
+config ARCH_SPARSEMEM_ENABLE
+        bool
+
+config ARCH_SELECT_MEMORY_MODEL
+        bool
+
 config NODES_SHIFT
         int
         default "4" if ARCH_LH7A40X
@@ -1174,6 +1192,8 @@ source "drivers/dma/Kconfig"
 
 source "drivers/dca/Kconfig"
 
+source "drivers/uio/Kconfig"
+
 endmenu
 
 source "fs/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1a4649667ec8..e72db27e0ba0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -134,12 +134,11 @@ endif
  machine-$(CONFIG_ARCH_PNX4008)    := pnx4008
  machine-$(CONFIG_ARCH_NETX)       := netx
  machine-$(CONFIG_ARCH_NS9XXX)     := ns9xxx
- textofs-$(CONFIG_ARCH_NS9XXX)     := 0x00108000
  machine-$(CONFIG_ARCH_DAVINCI)    := davinci
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
   incdir-$(CONFIG_ARCH_MXC)        := mxc
  machine-$(CONFIG_ARCH_MX3)        := mx3
- machine-$(CONFIG_ARCH_ORION)      := orion
+ machine-$(CONFIG_ARCH_ORION5X)    := orion5x
  machine-$(CONFIG_ARCH_MSM7X00A)   := msm
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
@@ -185,6 +184,7 @@ core-$(CONFIG_VFP)		+= arch/arm/vfp/
 
 # If we have a common platform directory, then include it in the build.
 core-$(CONFIG_PLAT_IOP)         += arch/arm/plat-iop/
+core-$(CONFIG_PLAT_ORION)               += arch/arm/plat-orion/
 core-$(CONFIG_ARCH_OMAP)        += arch/arm/plat-omap/
 core-$(CONFIG_PLAT_S3C24XX)             += arch/arm/plat-s3c24xx/
 core-$(CONFIG_ARCH_MXC)         += arch/arm/plat-mxc/
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 25f12303b106..da226abce2d0 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -61,9 +61,15 @@ endif
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-                   -C none -a $(ZRELADDR) -e $(ZRELADDR) \
+                   -C none -a $(LOADADDR) -e $(LOADADDR) \
                    -n 'Linux-$(KERNELRELEASE)' -d $< $@
 
+ifeq ($(CONFIG_ZBOOT_ROM),y)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
+else
+$(obj)/uImage: LOADADDR=$(ZRELADDR)
+endif
+
 $(obj)/uImage:  $(obj)/zImage FORCE
         $(call if_changed,uimage)
         @echo '  Image $@ is ready'
diff --git a/arch/arm/common/rtctime.c b/arch/arm/common/rtctime.c
index f53bca46e23c..aa8f7739c822 100644
--- a/arch/arm/common/rtctime.c
+++ b/arch/arm/common/rtctime.c
@@ -22,7 +22,6 @@
 #include <linux/mutex.h>
 
 #include <asm/rtc.h>
-#include <asm/semaphore.h>
 
 static DECLARE_WAIT_QUEUE_HEAD(rtc_wait);
 static struct fasync_struct *rtc_async_queue;
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index 314ebd3a1d71..bc299b07a6fa 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/hardware/scoop.h>
 
 /* PCMCIA to Scoop linkage
@@ -30,10 +31,9 @@
 struct scoop_pcmcia_config *platform_scoop_config;
 EXPORT_SYMBOL(platform_scoop_config);
 
-#define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr)))
-
 struct  scoop_dev {
-        void  *base;
+        void __iomem *base;
+        struct gpio_chip gpio;
         spinlock_t scoop_lock;
         unsigned short suspend_clr;
         unsigned short suspend_set;
@@ -44,13 +44,84 @@ void reset_scoop(struct device *dev)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
 
-        SCOOP_REG(sdev->base,SCOOP_MCR) = 0x0100;  // 00
-        SCOOP_REG(sdev->base,SCOOP_CDR) = 0x0000;  // 04
-        SCOOP_REG(sdev->base,SCOOP_CCR) = 0x0000;  // 10
-        SCOOP_REG(sdev->base,SCOOP_IMR) = 0x0000;  // 18
-        SCOOP_REG(sdev->base,SCOOP_IRM) = 0x00FF;  // 14
-        SCOOP_REG(sdev->base,SCOOP_ISR) = 0x0000;  // 1C
-        SCOOP_REG(sdev->base,SCOOP_IRM) = 0x0000;
+        iowrite16(0x0100, sdev->base + SCOOP_MCR);  // 00
+        iowrite16(0x0000, sdev->base + SCOOP_CDR);  // 04
+        iowrite16(0x0000, sdev->base + SCOOP_CCR);  // 10
+        iowrite16(0x0000, sdev->base + SCOOP_IMR);  // 18
+        iowrite16(0x00FF, sdev->base + SCOOP_IRM);  // 14
+        iowrite16(0x0000, sdev->base + SCOOP_ISR);  // 1C
+        iowrite16(0x0000, sdev->base + SCOOP_IRM);
+}
+
+static void __scoop_gpio_set(struct scoop_dev *sdev,
+                        unsigned offset, int value)
+{
+        unsigned short gpwr;
+
+        gpwr = ioread16(sdev->base + SCOOP_GPWR);
+        if (value)
+                gpwr |= 1 << (offset + 1);
+        else
+                gpwr &= ~(1 << (offset + 1));
+        iowrite16(gpwr, sdev->base + SCOOP_GPWR);
+}
+
+static void scoop_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+        unsigned long flags;
+
+        spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+        __scoop_gpio_set(sdev, offset, value);
+
+        spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+}
+
+static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+
+        /* XXX: I'm usure,  but it seems so */
+        return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
+}
+
+static int scoop_gpio_direction_input(struct gpio_chip *chip,
+                        unsigned offset)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+        unsigned long flags;
+        unsigned short gpcr;
+
+        spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+        gpcr = ioread16(sdev->base + SCOOP_GPCR);
+        gpcr &= ~(1 << (offset + 1));
+        iowrite16(gpcr, sdev->base + SCOOP_GPCR);
+
+        spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+
+        return 0;
+}
+
+static int scoop_gpio_direction_output(struct gpio_chip *chip,
+                        unsigned offset, int value)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+        unsigned long flags;
+        unsigned short gpcr;
+
+        spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+        __scoop_gpio_set(sdev, offset, value);
+
+        gpcr = ioread16(sdev->base + SCOOP_GPCR);
+        gpcr |= 1 << (offset + 1);
+        iowrite16(gpcr, sdev->base + SCOOP_GPCR);
+
+        spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+
+        return 0;
 }
 
 unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
@@ -60,8 +131,8 @@ unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
         struct scoop_dev *sdev = dev_get_drvdata(dev);
 
         spin_lock_irqsave(&sdev->scoop_lock, flag);
-        gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) | bit;
-        SCOOP_REG(sdev->base, SCOOP_GPWR) = gpio_bit;
+        gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit;
+        iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
         spin_unlock_irqrestore(&sdev->scoop_lock, flag);
 
         return gpio_bit;
@@ -74,8 +145,8 @@ unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit)
         struct scoop_dev *sdev = dev_get_drvdata(dev);
 
         spin_lock_irqsave(&sdev->scoop_lock, flag);
-        gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) & ~bit;
-        SCOOP_REG(sdev->base,SCOOP_GPWR) = gpio_bit;
+        gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit;
+        iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
         spin_unlock_irqrestore(&sdev->scoop_lock, flag);
 
         return gpio_bit;
@@ -87,13 +158,13 @@ EXPORT_SYMBOL(reset_scoop_gpio);
 unsigned short read_scoop_reg(struct device *dev, unsigned short reg)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
-        return SCOOP_REG(sdev->base,reg);
+        return ioread16(sdev->base + reg);
 }
 
 void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
-        SCOOP_REG(sdev->base,reg)=data;
+        iowrite16(data, sdev->base + reg);
 }
 
 EXPORT_SYMBOL(reset_scoop);
@@ -104,9 +175,9 @@ static void check_scoop_reg(struct scoop_dev *sdev)
 {
         unsigned short mcr;
 
-        mcr = SCOOP_REG(sdev->base, SCOOP_MCR);
+        mcr = ioread16(sdev->base + SCOOP_MCR);
         if ((mcr & 0x100) == 0)
-                SCOOP_REG(sdev->base, SCOOP_MCR) = 0x0101;
+                iowrite16(0x0101, sdev->base + SCOOP_MCR);
 }
 
 #ifdef CONFIG_PM
@@ -115,8 +186,8 @@ static int scoop_suspend(struct platform_device *dev, pm_message_t state)
         struct scoop_dev *sdev = platform_get_drvdata(dev);
 
         check_scoop_reg(sdev);
-        sdev->scoop_gpwr = SCOOP_REG(sdev->base, SCOOP_GPWR);
-        SCOOP_REG(sdev->base, SCOOP_GPWR) = (sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set;
+        sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR);
+        iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR);
 
         return 0;
 }
@@ -126,7 +197,7 @@ static int scoop_resume(struct platform_device *dev)
         struct scoop_dev *sdev = platform_get_drvdata(dev);
 
         check_scoop_reg(sdev);
-        SCOOP_REG(sdev->base,SCOOP_GPWR) = sdev->scoop_gpwr;
+        iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR);
 
         return 0;
 }
@@ -135,11 +206,13 @@ static int scoop_resume(struct platform_device *dev)
 #define scoop_resume    NULL
 #endif
 
-int __init scoop_probe(struct platform_device *pdev)
+static int __devinit scoop_probe(struct platform_device *pdev)
 {
         struct scoop_dev *devptr;
         struct scoop_config *inf;
         struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        int ret;
+        int temp;
 
         if (!mem)
                 return -EINVAL;
@@ -154,40 +227,78 @@ int __init scoop_probe(struct platform_device *pdev)
         devptr->base = ioremap(mem->start, mem->end - mem->start + 1);
 
         if (!devptr->base) {
-                kfree(devptr);
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto err_ioremap;
         }
 
         platform_set_drvdata(pdev, devptr);
 
-        printk("Sharp Scoop Device found at 0x%08x -> 0x%08x\n",(unsigned int)mem->start,(unsigned int)devptr->base);
+        printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base);
 
-        SCOOP_REG(devptr->base, SCOOP_MCR) = 0x0140;
+        iowrite16(0x0140, devptr->base + SCOOP_MCR);
         reset_scoop(&pdev->dev);
-        SCOOP_REG(devptr->base, SCOOP_CPR) = 0x0000;
-        SCOOP_REG(devptr->base, SCOOP_GPCR) = inf->io_dir & 0xffff;
-        SCOOP_REG(devptr->base, SCOOP_GPWR) = inf->io_out & 0xffff;
+        iowrite16(0x0000, devptr->base + SCOOP_CPR);
+        iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR);
+        iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR);
 
         devptr->suspend_clr = inf->suspend_clr;
         devptr->suspend_set = inf->suspend_set;
 
+        devptr->gpio.base = -1;
+
+        if (inf->gpio_base != 0) {
+                devptr->gpio.label = pdev->dev.bus_id;
+                devptr->gpio.base = inf->gpio_base;
+                devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
+                devptr->gpio.set = scoop_gpio_set;
+                devptr->gpio.get = scoop_gpio_get;
+                devptr->gpio.direction_input = scoop_gpio_direction_input;
+                devptr->gpio.direction_output = scoop_gpio_direction_output;
+
+                ret = gpiochip_add(&devptr->gpio);
+                if (ret)
+                        goto err_gpio;
+        }
+
         return 0;
+
+        if (devptr->gpio.base != -1)
+                temp = gpiochip_remove(&devptr->gpio);
+err_gpio:
+        platform_set_drvdata(pdev, NULL);
+err_ioremap:
+        iounmap(devptr->base);
+        kfree(devptr);
+
+        return ret;
 }
 
-static int scoop_remove(struct platform_device *pdev)
+static int __devexit scoop_remove(struct platform_device *pdev)
 {
         struct scoop_dev *sdev = platform_get_drvdata(pdev);
-        if (sdev) {
-                iounmap(sdev->base);
-                kfree(sdev);
-                platform_set_drvdata(pdev, NULL);
+        int ret;
+
+        if (!sdev)
+                return -EINVAL;
+
+        if (sdev->gpio.base != -1) {
+                ret = gpiochip_remove(&sdev->gpio);
+                if (ret) {
+                        dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret);
+                        return ret;
+                }
         }
+
+        platform_set_drvdata(pdev, NULL);
+        iounmap(sdev->base);
+        kfree(sdev);
+
         return 0;
 }
 
 static struct platform_driver scoop_driver = {
         .probe          = scoop_probe,
-        .remove         = scoop_remove,
+        .remove         = __devexit_p(scoop_remove),
         .suspend        = scoop_suspend,
         .resume         = scoop_resume,
         .driver         = {
@@ -195,7 +306,7 @@ static struct platform_driver scoop_driver = {
         },
 };
 
-int __init scoop_init(void)
+static int __init scoop_init(void)
 {
         return platform_driver_register(&scoop_driver);
 }
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
new file mode 100644
index 000000000000..dc030cfe5009
--- /dev/null
+++ b/arch/arm/configs/am200epdkit_defconfig
@@ -0,0 +1,1149 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc3
+# Sun Mar  9 06:33:33 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="gum"
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+# CONFIG_EPOLL is not set
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+CONFIG_ARCH_GUMSTIX=y
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+CONFIG_MACH_GUMSTIX_F=y
+CONFIG_PXA25x=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+# CONFIG_IWMMXT is not set
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+# CONFIG_PCMCIA_IOCTL is not set
+
+#
+# PC-card bridges
+#
+CONFIG_PCMCIA_PXA2XX=y
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+# CONFIG_BT_HIDP is not set
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=m
+CONFIG_IDE_MAX_HWIFS=2
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=m
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=m
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+# CONFIG_DEBUG_GPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_SA1100_WATCHDOG=m
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+CONFIG_FB_PXA_PARAMETERS=y
+CONFIG_FB_MBX=m
+CONFIG_FB_VIRTUAL=m
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_AC97=m
+
+#
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+CONFIG_USB_GADGET_PXA2XX=y
+CONFIG_USB_PXA2XX=y
+# CONFIG_USB_PXA2XX_SMALL is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index e10d003566d6..2dbbbc3d4ac3 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -620,14 +620,14 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 834dddb51314..6e994f7820c6 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -594,14 +594,14 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index 46b0c734aeb9..f659c938473f 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -1,43 +1,56 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.19-rc6
-# Fri Nov 17 18:42:21 2006
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:20:50 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -53,30 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
+# CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -108,12 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -121,29 +138,52 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
 CONFIG_ARCH_AT91SAM9260=y
 # CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
 
 #
-# AT91SAM9260 Board Type
+# AT91SAM9260 / AT91SAM9XE Board Type
 #
 CONFIG_MACH_AT91SAM9260EK=y
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
 
 #
 # AT91 Board Options
 #
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
 # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
 #
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -166,19 +206,19 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -191,8 +231,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -203,6 +247,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -228,7 +273,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -238,13 +283,9 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -263,33 +304,23 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
 # CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -302,10 +333,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -315,7 +342,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -324,34 +361,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 # CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
@@ -360,15 +380,19 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
@@ -388,6 +412,8 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -395,43 +421,72 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
+# USB Network Adapters
 #
-# CONFIG_NETDEVICES is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -439,6 +494,7 @@ CONFIG_SCSI_MULTI_LUN=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -448,7 +504,6 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -458,6 +513,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -492,114 +548,131 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
 
 #
-# Ftape, the floppy tape device driver
+# I2C Algorithms
 #
-# CONFIG_RAW_DRIVER is not set
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# TPM devices
+# I2C Hardware Bus support
 #
-# CONFIG_TCG_TPM is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
 
 #
-# I2C support
+# Miscellaneous I2C Chip support
 #
-# CONFIG_I2C is not set
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 
 #
 # SPI support
 #
 # CONFIG_SPI is not set
 # CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# USB support
+# USB Input Devices
 #
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -610,7 +683,7 @@ CONFIG_USB=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -619,9 +692,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -640,6 +715,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -650,43 +726,10 @@ CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -708,6 +751,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -717,6 +761,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -727,13 +772,19 @@ CONFIG_USB_MON=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -745,17 +796,56 @@ CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# MMC/SD Card support
+# RTC interfaces
 #
-# CONFIG_MMC is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# Real Time Clock
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
 #
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -806,7 +896,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -825,10 +914,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
@@ -836,17 +922,12 @@ CONFIG_CRAMFS=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -887,41 +968,49 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
-# CONFIG_HEADERS_CHECK is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -932,18 +1021,21 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index fcd8fa091e9d..3802e85f7483 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -1,43 +1,56 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.19-rc6
-# Fri Nov 17 18:00:38 2006
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:21:49 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -53,30 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
+# CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -108,12 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -121,14 +138,27 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
 # CONFIG_ARCH_AT91SAM9260 is not set
 CONFIG_ARCH_AT91SAM9261=y
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91SAM9261 Board Type
@@ -138,12 +168,15 @@ CONFIG_MACH_AT91SAM9261EK=y
 #
 # AT91 Board Options
 #
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
 # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
 #
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -166,19 +199,19 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -191,8 +224,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -203,6 +240,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -228,7 +266,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -238,13 +276,13 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -266,30 +304,20 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
 # CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -302,10 +330,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -315,7 +339,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -324,20 +358,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -350,12 +378,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
 # User Modules And Translation Layers
 #
 # CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -375,7 +405,6 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -386,6 +415,8 @@ CONFIG_MTD_CFI_I2=y
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -397,35 +428,24 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 CONFIG_MTD_NAND_AT91=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
@@ -434,15 +454,19 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
@@ -462,6 +486,8 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -469,75 +495,49 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -545,10 +545,6 @@ CONFIG_DM9000=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -556,6 +552,7 @@ CONFIG_DM9000=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -565,23 +562,43 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -609,75 +626,47 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
 # CONFIG_I2C_PCA is not set
-# CONFIG_I2C_PCA_ISA is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -686,70 +675,125 @@ CONFIG_I2C_AT91=y
 #
 # SPI support
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
 
 #
-# Dallas's 1-wire bus
+# SPI Master Controller Drivers
 #
-# CONFIG_W1 is not set
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
 
 #
-# Hardware Monitoring support
+# SPI Protocol Masters
 #
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
 # CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D15605 is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
+# CONFIG_FB_INTSRAM is not set
+# CONFIG_FB_ATMEL_STN is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# USB support
+# USB Input Devices
 #
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -760,7 +804,7 @@ CONFIG_USB=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -769,9 +813,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -790,6 +836,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -800,43 +847,10 @@ CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -858,6 +872,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -867,6 +882,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -877,13 +893,19 @@ CONFIG_USB_MON=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -895,21 +917,73 @@ CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card support
+# MMC/SD Card Drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=m
-# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# Real Time Clock
+# MMC/SD Host Controller Drivers
 #
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -960,7 +1034,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -973,7 +1046,6 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 # CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
@@ -981,10 +1053,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
@@ -992,17 +1061,12 @@ CONFIG_CRAMFS=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -1043,41 +1107,49 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
-# CONFIG_HEADERS_CHECK is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -1088,18 +1160,21 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index c72ab82873d5..32a0d74e0c89 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -1,12 +1,18 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20-rc1
-# Mon Jan  8 16:06:54 2007
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:12:20 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
@@ -15,32 +21,36 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -56,32 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -113,13 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -127,15 +138,27 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
 # CONFIG_ARCH_AT91SAM9260 is not set
 # CONFIG_ARCH_AT91SAM9261 is not set
 CONFIG_ARCH_AT91SAM9263=y
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91SAM9263 Board Type
@@ -152,6 +175,8 @@ CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # AT91 Feature Selections
 #
 # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -174,19 +199,19 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -199,8 +224,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -211,6 +240,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -236,7 +266,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -246,7 +276,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -271,6 +300,7 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
@@ -281,20 +311,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -307,10 +325,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -320,7 +334,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -329,20 +353,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -362,6 +380,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -381,7 +400,6 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -405,35 +423,24 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 CONFIG_MTD_NAND_AT91=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -443,15 +450,18 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
@@ -473,6 +483,7 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -480,80 +491,65 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
+# Wireless LAN
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -561,10 +557,6 @@ CONFIG_MII=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -572,6 +564,7 @@ CONFIG_MII=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -581,20 +574,26 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_TSDEV=y
-CONFIG_INPUT_TSDEV_SCREEN_X=240
-CONFIG_INPUT_TSDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -603,6 +602,7 @@ CONFIG_TOUCHSCREEN_ADS7846=y
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -636,71 +636,47 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
 # CONFIG_I2C_PCA is not set
-# CONFIG_I2C_PCA_ISA is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -722,61 +698,80 @@ CONFIG_SPI_ATMEL=y
 #
 # SPI Protocol Masters
 #
-
-#
-# Dallas's 1-wire bus
-#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D15605 is not set
 # CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -784,26 +779,28 @@ CONFIG_FB=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# HID Devices
+# USB Input Devices
 #
-CONFIG_HID=y
+# CONFIG_USB_HID is not set
 
 #
-# USB support
+# USB HID Boot Protocol drivers
 #
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -814,9 +811,8 @@ CONFIG_USB=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_MULTITHREAD_PROBE is not set
 # CONFIG_USB_OTG is not set
 
 #
@@ -824,9 +820,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -845,6 +843,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -856,43 +855,10 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -914,6 +880,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -923,6 +890,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -933,13 +901,19 @@ CONFIG_USB_MON=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -951,21 +925,73 @@ CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card support
+# MMC/SD Card Drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=m
-# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# Real Time Clock
+# MMC/SD Host Controller Drivers
 #
+CONFIG_MMC_AT91=m
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -1016,7 +1042,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1032,10 +1057,12 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
@@ -1044,10 +1071,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 # CONFIG_NFS_V3 is not set
 # CONFIG_NFS_V4 is not set
@@ -1057,6 +1081,7 @@ CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1064,17 +1089,12 @@ CONFIG_SUNRPC=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -1115,36 +1135,35 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
-
-#
-# Profiling support
-#
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -1152,9 +1171,13 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -1165,10 +1188,7 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
@@ -1177,8 +1197,13 @@ CONFIG_DEBUG_LL=y
 CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index fbe8b3049343..98e6746d02be 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -1,15 +1,18 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21
-# Mon May  7 16:30:40 2007
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:24:14 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
@@ -23,27 +26,28 @@ CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -62,32 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -119,14 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -134,9 +138,18 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
@@ -144,6 +157,8 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_AT91SAM9261 is not set
 # CONFIG_ARCH_AT91SAM9263 is not set
 CONFIG_ARCH_AT91SAM9RL=y
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91SAM9RL Board Type
@@ -157,7 +172,9 @@ CONFIG_MACH_AT91SAM9RLEK=y
 #
 # AT91 Feature Selections
 #
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -185,15 +202,14 @@ CONFIG_CPU_CP15_MMU=y
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -206,9 +222,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -245,6 +264,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -254,7 +274,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 # CONFIG_PACKET is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
@@ -271,10 +290,6 @@ CONFIG_UNIX=y
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -284,7 +299,16 @@ CONFIG_UNIX=y
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -293,21 +317,14 @@ CONFIG_UNIX=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
@@ -327,6 +344,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -346,7 +364,6 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -370,36 +387,23 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 CONFIG_MTD_NAND_AT91=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -410,12 +414,16 @@ CONFIG_BLK_DEV_RAM_SIZE=24576
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
@@ -437,6 +445,7 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -444,47 +453,13 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 # CONFIG_NETDEVICES is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -492,6 +467,7 @@ CONFIG_SCSI_MULTI_LUN=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -501,7 +477,6 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -511,8 +486,10 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -521,6 +498,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -554,37 +532,50 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
 
 #
-# TPM devices
+# I2C Algorithms
 #
-# CONFIG_TCG_TPM is not set
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C support
+# I2C Hardware Bus support
 #
-# CONFIG_I2C is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 
 #
 # SPI support
@@ -603,21 +594,25 @@ CONFIG_SPI_ATMEL=y
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
-
-#
-# Dallas's 1-wire bus
-#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Hardware Monitoring support
+# Watchdog Device Drivers
 #
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -625,37 +620,28 @@ CONFIG_SPI_ATMEL=y
 # CONFIG_MFD_SM501 is not set
 
 #
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -665,9 +651,16 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 #
 # Frame buffer hardware drivers
 #
+# CONFIG_FB_S1D15605 is not set
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -675,97 +668,97 @@ CONFIG_FB_ATMEL=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
 
 #
 # Sound
 #
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_SEQ_DUMMY=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_DETECT=y
-# CONFIG_SND_PCM_XRUN_DEBUG is not set
-
-#
-# Generic devices
-#
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
 
 #
-# ALSA ARM devices
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
 
 #
-# SoC audio support
+# USB Gadget Support
 #
-# CONFIG_SND_SOC is not set
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# Open Sound System
+# MMC/SD Card Drivers
 #
-# CONFIG_SOUND_PRIME is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# HID Devices
+# MMC/SD Host Controller Drivers
 #
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# USB support
+# RTC interfaces
 #
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# I2C RTC drivers
 #
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
 
 #
-# USB Gadget Support
+# SPI RTC drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
 
 #
-# MMC/SD Card support
+# Platform RTC drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Real Time Clock
+# on-CPU RTC drivers
 #
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -816,7 +809,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -836,20 +828,13 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -890,16 +875,15 @@ CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=y
-
-#
-# Profiling support
-#
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -907,8 +891,8 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
@@ -916,6 +900,9 @@ CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -923,10 +910,13 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -937,10 +927,7 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
@@ -949,9 +936,12 @@ CONFIG_DEBUG_LL=y
 CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig
index baa97698c744..d846a492e5ce 100644
--- a/arch/arm/configs/ateb9200_defconfig
+++ b/arch/arm/configs/ateb9200_defconfig
@@ -714,7 +714,7 @@ CONFIG_I2C_ALGOPCA=m
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=m
+CONFIG_I2C_GPIO=m
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
new file mode 100644
index 000000000000..f3cd4a95373a
--- /dev/null
+++ b/arch/arm/configs/cam60_defconfig
@@ -0,0 +1,1228 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Thu Mar  6 10:07:26 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_AUDIT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+CONFIG_MACH_CAM60=y
+# CONFIG_MACH_SAM9_L9260 is not set
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0x20004000
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_CMDLINE="console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RCSIMPLE=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_RAM=m
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=m
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_AT91_ECC_SOFT is not set
+CONFIG_MTD_NAND_AT91_ECC_HW=y
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+# CONFIG_ICPLUS_PHY is not set
+CONFIG_FIXED_PHY=m
+# CONFIG_FIXED_MII_10_FDX is not set
+# CONFIG_FIXED_MII_100_FDX is not set
+# CONFIG_FIXED_MII_1000_FDX is not set
+CONFIG_FIXED_MII_AMNT=1
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_VSXXXAA=m
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_TEST=m
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ABLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+# CONFIG_CRYPTO_XTS is not set
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_TEST=m
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=m
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=m
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig
index 88e5d28aeec7..67e65e4f0cdc 100644
--- a/arch/arm/configs/csb337_defconfig
+++ b/arch/arm/configs/csb337_defconfig
@@ -1,69 +1,96 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.15
-# Mon Jan  9 21:51:31 2006
+# Linux kernel version: 2.6.24-rc7
+# Wed Jan  9 22:19:24 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -81,62 +108,101 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 #
 # System Type
 #
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_AAEC2000 is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200=y
 
 #
-# AT91RM9200 Implementations
+# Boot options
 #
 
 #
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
 # AT91RM9200 Board Type
 #
+# CONFIG_MACH_ONEARM is not set
 # CONFIG_ARCH_AT91RM9200DK is not set
 # CONFIG_MACH_AT91RM9200EK is not set
 CONFIG_MACH_CSB337=y
 # CONFIG_MACH_CSB637 is not set
 # CONFIG_MACH_CARMEVA is not set
-# CONFIG_MACH_KB9200 is not set
 # CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_CHUB is not set
+# CONFIG_MACH_HOMEMATIC is not set
+# CONFIG_MACH_ECBAT91 is not set
+# CONFIG_MACH_SWEDATMS is not set
+
+#
+# AT91 Board Options
+#
 
 #
-# AT91RM9200 Feature Selections
+# AT91 Feature Selections
 #
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=128
 
 #
 # Processor Type
 #
 CONFIG_CPU_32=y
 CONFIG_CPU_ARM920T=y
-CONFIG_CPU_32v4=y
+CONFIG_CPU_32v4T=y
 CONFIG_CPU_ABRT_EV4T=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
 CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
 
 #
 # Processor Features
@@ -145,15 +211,13 @@ CONFIG_CPU_TLB_V4WBI=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-CONFIG_ISA_DMA_API=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
@@ -168,8 +232,13 @@ CONFIG_AT91_CF=y
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -178,9 +247,13 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
 CONFIG_LEDS_CPU=y
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -191,6 +264,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -215,6 +289,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -227,6 +302,10 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -243,23 +322,26 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
@@ -269,13 +351,8 @@ CONFIG_TCP_CONG_BIC=y
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -285,7 +362,17 @@ CONFIG_TCP_CONG_BIC=y
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -294,19 +381,14 @@ CONFIG_TCP_CONG_BIC=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -319,11 +401,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -349,15 +434,14 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0
-CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -368,7 +452,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
 # CONFIG_MTD_BLOCK2MTD is not set
 
 #
@@ -378,29 +461,15 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
 # CONFIG_MTD_AT91_DATAFLASH is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -409,13 +478,12 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 # CONFIG_IDE is not set
 
 #
@@ -423,6 +491,9 @@ CONFIG_BLK_DEV_INITRD=y
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -441,97 +512,61 @@ CONFIG_SCSI_PROC_FS=y
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# SCSI Transport Attributes
+# SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -539,26 +574,23 @@ CONFIG_ARM_AT91_ETHER=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
 #
 CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -568,6 +600,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -583,6 +616,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -601,152 +635,114 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT91RM9200_WATCHDOG=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
 #
-# Ftape, the floppy tape device driver
-#
-
-#
 # PCMCIA character devices
 #
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
 CONFIG_AT91_SPI=y
 CONFIG_AT91_SPIDEV=y
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
 # CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 
 #
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Multimedia devices
+# Watchdog Device Drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -758,12 +754,25 @@ CONFIG_DUMMY_CONSOLE=y
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
 
 #
-# USB support
+# USB HID Boot Protocol drivers
 #
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
 
@@ -771,7 +780,7 @@ CONFIG_USB_DEBUG=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -780,9 +789,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -801,59 +812,21 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -866,15 +839,18 @@ CONFIG_USB_MON=y
 CONFIG_USB_SERIAL=y
 CONFIG_USB_SERIAL_CONSOLE=y
 CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
 # CONFIG_USB_SERIAL_AIRPRIME is not set
-# CONFIG_USB_SERIAL_ANYDATA is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
 # CONFIG_USB_SERIAL_CP2101 is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
 # CONFIG_USB_SERIAL_VISOR is not set
 # CONFIG_USB_SERIAL_IPAQ is not set
 # CONFIG_USB_SERIAL_IR is not set
@@ -899,14 +875,20 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
 CONFIG_USB_EZUSB=y
 
 #
@@ -914,16 +896,22 @@ CONFIG_USB_EZUSB=y
 #
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
 # CONFIG_USB_AUERSWALD is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -934,13 +922,19 @@ CONFIG_USB_EZUSB=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -950,22 +944,28 @@ CONFIG_USB_AT91=y
 # CONFIG_USB_GADGETFS is not set
 # CONFIG_USB_FILE_STORAGE is not set
 # CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card support
+# MMC/SD Card Drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91RM9200=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# Real Time Clock
+# MMC/SD Host Controller Drivers
 #
+# CONFIG_MMC_AT91 is not set
+# CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
+# CONFIG_RTC_DEBUG is not set
 
 #
 # RTC interfaces
@@ -974,39 +974,60 @@ CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_X1205 is not set
 CONFIG_RTC_DRV_DS1307=y
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-CONFIG_RTC_DRV_AT91RM9200=y
-# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
 CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
@@ -1030,11 +1051,12 @@ CONFIG_DNOTIFY=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
 
 #
 # Miscellaneous filesystems
@@ -1046,7 +1068,6 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 # CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
@@ -1054,10 +1075,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
@@ -1070,6 +1088,7 @@ CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1077,43 +1096,56 @@ CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -1124,12 +1156,13 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
 # CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
@@ -1138,7 +1171,15 @@ CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
 # CONFIG_CRYPTO_TWOFISH is not set
 # CONFIG_CRYPTO_SERPENT is not set
@@ -1149,20 +1190,27 @@ CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
index 669f035896f9..99702146c9fc 100644
--- a/arch/arm/configs/csb637_defconfig
+++ b/arch/arm/configs/csb637_defconfig
@@ -1,69 +1,112 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.15
-# Mon Jan  9 21:52:00 2006
+# Linux kernel version: 2.6.25-rc8
+# Fri Apr  4 22:06:15 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -77,66 +120,111 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System Type
 #
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_AAEC2000 is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
 
 #
-# AT91RM9200 Implementations
+# Atmel AT91 System-on-Chip
 #
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91RM9200 Board Type
 #
+# CONFIG_MACH_ONEARM is not set
 # CONFIG_ARCH_AT91RM9200DK is not set
 # CONFIG_MACH_AT91RM9200EK is not set
 # CONFIG_MACH_CSB337 is not set
 CONFIG_MACH_CSB637=y
 # CONFIG_MACH_CARMEVA is not set
-# CONFIG_MACH_KB9200 is not set
 # CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
 
 #
-# AT91RM9200 Feature Selections
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
 #
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=128
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
 
 #
 # Processor Type
 #
 CONFIG_CPU_32=y
 CONFIG_CPU_ARM920T=y
-CONFIG_CPU_32v4=y
+CONFIG_CPU_32v4T=y
 CONFIG_CPU_ABRT_EV4T=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
 CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
 
 #
 # Processor Features
@@ -145,15 +233,13 @@ CONFIG_CPU_TLB_V4WBI=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-CONFIG_ISA_DMA_API=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
@@ -168,8 +254,13 @@ CONFIG_AT91_CF=y
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -178,9 +269,13 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
 CONFIG_LEDS_CPU=y
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -191,6 +286,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -215,6 +311,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # Networking
@@ -227,6 +324,11 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -243,23 +345,26 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
@@ -269,13 +374,8 @@ CONFIG_TCP_CONG_BIC=y
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -283,9 +383,20 @@ CONFIG_TCP_CONG_BIC=y
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -294,19 +405,14 @@ CONFIG_TCP_CONG_BIC=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -319,11 +425,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -349,15 +458,14 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0
-CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -368,7 +476,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
 # CONFIG_MTD_BLOCK2MTD is not set
 
 #
@@ -377,30 +484,15 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_AT91_DATAFLASH is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -409,13 +501,15 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -423,6 +517,9 @@ CONFIG_BLK_DEV_INITRD=y
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -441,114 +538,78 @@ CONFIG_SCSI_PROC_FS=y
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# SCSI Transport Attributes
+# SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -558,7 +619,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -568,6 +628,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -583,6 +644,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -595,64 +657,29 @@ CONFIG_HW_CONSOLE=y
 #
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT91RM9200_WATCHDOG=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=m
 # CONFIG_NVRAM is not set
-CONFIG_RTC=y
-# CONFIG_AT91RM9200_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
 #
-# Ftape, the floppy tape device driver
-#
-
-#
 # PCMCIA character devices
 #
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-CONFIG_AT91_SPI=y
-CONFIG_AT91_SPIDEV=y
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
@@ -665,43 +692,53 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 
 #
-# Hardware Monitoring support
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -715,39 +752,72 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
 
 #
-# Multimedia Capabilities Port drivers
+# USB-based Watchdog Cards
 #
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -759,20 +829,34 @@ CONFIG_DUMMY_CONSOLE=y
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
 
 #
-# USB support
+# USB Input Devices
 #
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -781,9 +865,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -802,80 +888,42 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 CONFIG_USB_SERIAL=y
 CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_EZUSB=y
 CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
 # CONFIG_USB_SERIAL_AIRPRIME is not set
-# CONFIG_USB_SERIAL_ANYDATA is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
 # CONFIG_USB_SERIAL_CP2101 is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
 # CONFIG_USB_SERIAL_VISOR is not set
 # CONFIG_USB_SERIAL_IPAQ is not set
 # CONFIG_USB_SERIAL_IR is not set
@@ -883,6 +931,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y
 # CONFIG_USB_SERIAL_EDGEPORT_TI is not set
 # CONFIG_USB_SERIAL_GARMIN is not set
 # CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 CONFIG_USB_SERIAL_KEYSPAN=y
 CONFIG_USB_SERIAL_KEYSPAN_MPR=y
@@ -900,46 +949,66 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
-CONFIG_USB_EZUSB=y
+# CONFIG_USB_SERIAL_DEBUG is not set
 
 #
 # USB Miscellaneous drivers
 #
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
 # CONFIG_USB_AUERSWALD is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# USB DSL modem support
+# LED drivers
 #
+CONFIG_LEDS_GPIO=y
 
 #
-# USB Gadget Support
+# LED Triggers
 #
-# CONFIG_USB_GADGET is not set
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
 
 #
-# MMC/SD Card support
+# Userspace I/O
 #
-# CONFIG_MMC is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -948,16 +1017,17 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -979,11 +1049,12 @@ CONFIG_DNOTIFY=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
 
 #
 # Miscellaneous filesystems
@@ -995,18 +1066,16 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 # CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
@@ -1019,6 +1088,7 @@ CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1026,45 +1096,57 @@ CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 
@@ -1073,12 +1155,14 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=y
 # CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
@@ -1087,7 +1171,18 @@ CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
 # CONFIG_CRYPTO_TWOFISH is not set
 # CONFIG_CRYPTO_SERPENT is not set
@@ -1098,20 +1193,29 @@ CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ecbat91_defconfig b/arch/arm/configs/ecbat91_defconfig
new file mode 100644
index 000000000000..90ed214e3673
--- /dev/null
+++ b/arch/arm/configs/ecbat91_defconfig
@@ -0,0 +1,1315 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22-rc4
+# Sat Jun  9 01:30:18 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_CHUB is not set
+CONFIG_MACH_ECBAT91=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_AT91_CF=y
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="rootfstype=reiserfs root=/dev/mmcblk0p1 console=ttyS0,115200n8 rootdelay=1"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=y
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_IEEE80211_SOFTMAC=y
+CONFIG_IEEE80211_SOFTMAC_DEBUG=y
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_AT91RM9200_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_AT91_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ATMEL is not set
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_AT91=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+# CONFIG_BLINK is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# LED devices
+#
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig
index a0f48d54fbcc..ae51a40db6f9 100644
--- a/arch/arm/configs/kafa_defconfig
+++ b/arch/arm/configs/kafa_defconfig
@@ -587,14 +587,14 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
new file mode 100644
index 000000000000..4d11678584db
--- /dev/null
+++ b/arch/arm/configs/magician_defconfig
@@ -0,0 +1,1182 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc6
+# Sun Dec 30 13:02:54 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_UID16 is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_ARMCORE is not set
+CONFIG_MACH_MAGICIAN=y
+CONFIG_PXA27x=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="keepinitrd"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+CONFIG_APM_EMULATION=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+# CONFIG_IRNET is not set
+CONFIG_IRCOMM=m
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+CONFIG_IRDA_DEBUG=y
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+CONFIG_PXA_FICP=m
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x04000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+# CONFIG_MTD_PXA2XX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_PXA27x is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+# CONFIG_SERIAL_PXA_CONSOLE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_PXA=m
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+CONFIG_W1=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2482 is not set
+CONFIG_W1_MASTER_DS1WM=y
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+CONFIG_W1_SLAVE_DS2760=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+# CONFIG_APM_POWER is not set
+CONFIG_BATTERY_DS2760=y
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+CONFIG_HTC_EGPIO=y
+CONFIG_HTC_PASIC3=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+# CONFIG_SND_PXA2XX_AC97 is not set
+
+#
+# System on Chip audio support
+#
+CONFIG_SND_SOC=m
+CONFIG_SND_PXA2XX_SOC=m
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_HID=m
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+CONFIG_NEW_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_DEBUG=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1251=m
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_CBC is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig
index 0e5794c6a48e..7dc1580e4d99 100644
--- a/arch/arm/configs/ns9xxx_defconfig
+++ b/arch/arm/configs/ns9xxx_defconfig
@@ -1,621 +1,79 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Thu Feb 15 20:51:47 2007
-#
-CONFIG_ARM=y
-# CONFIG_GENERIC_TIME is not set
-CONFIG_MMU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_UTS_NS is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
 # CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEFAULT_IOSCHED="noop"
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_L7200 is not set
 CONFIG_ARCH_NS9XXX=y
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# NS9xxx Implementations
-#
+CONFIG_MACH_A9M9360=y
+CONFIG_MACH_A9M9750=y
+CONFIG_MACH_CC7UCAMRY=y
+CONFIG_MACH_CC9C=y
+CONFIG_MACH_CC9P9210=y
+CONFIG_MACH_CC9P9210JS=y
+CONFIG_MACH_CC9P9215=y
+CONFIG_MACH_CC9P9215JS=y
 CONFIG_MACH_CC9P9360DEV=y
-CONFIG_PROCESSOR_NS9360=y
-CONFIG_BOARD_A9M9750DEV=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_ARM926T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
+CONFIG_MACH_CC9P9360JS=y
+CONFIG_MACH_CC9P9360VAL=y
+CONFIG_MACH_CC9P9750DEV=y
+CONFIG_MACH_CC9P9750VAL=y
+CONFIG_MACH_CCW9C=y
+CONFIG_MACH_INC20OTTER=y
+CONFIG_MACH_OTTER=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_VFP is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-# CONFIG_APM is not set
-
-#
-# Networking
-#
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# ISDN subsystem
-#
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
+CONFIG_NET=y
+CONFIG_PACKET=m
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_MTD=m
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NS9XXX_ETH=y
 # CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-# CONFIG_SERIAL_8250_MANY_PORTS is not set
-# CONFIG_SERIAL_8250_SHARE_IRQ is not set
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
+CONFIG_SERIAL_NS921X=y
+CONFIG_SERIAL_NS921X_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+CONFIG_ADC_NS9215=m
+CONFIG_I2C=m
+CONFIG_I2C_GPIO=m
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Misc devices
-#
-# CONFIG_TIFM_CORE is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# Real Time Clock
-#
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_RTC_CLASS=m
+CONFIG_RTC_DRV_NS9215=m
+CONFIG_EXT2_FS=m
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
+CONFIG_JFFS2_FS=m
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 # CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_ICEDCC=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC32 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion5x_defconfig
index 1e5aaa645fcd..52cd99bd52fb 100644
--- a/arch/arm/configs/orion_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_MXC is not set
-CONFIG_ARCH_ORION=y
+CONFIG_ARCH_ORION5X=y
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig
index 3c0c4f192dc1..95a22f512805 100644
--- a/arch/arm/configs/picotux200_defconfig
+++ b/arch/arm/configs/picotux200_defconfig
@@ -727,14 +727,14 @@ CONFIG_I2C_CHARDEV=m
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=m
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=m
+CONFIG_I2C_GPIO=m
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
new file mode 100644
index 000000000000..484dc9739dfc
--- /dev/null
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -0,0 +1,1098 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23
+# Sun Oct 14 02:01:07 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+CONFIG_MACH_SAM9_L9260=y
+
+#
+# AT91 Board Options
+#
+CONFIG_MTD_AT91_DATAFLASH_CARD=y
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+# CONFIG_ATMEL_TCLIB is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 mem=64M initrd=0x21100000,4194304 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=3
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DS1553=y
+# CONFIG_RTC_DRV_STK17TA8 is not set
+CONFIG_RTC_DRV_DS1742=y
+CONFIG_RTC_DRV_M48T86=y
+# CONFIG_RTC_DRV_M48T59 is not set
+CONFIG_RTC_DRV_V3020=y
+
+#
+# on-CPU RTC drivers
+#
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_NFS_DIRECTIO=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
new file mode 100644
index 000000000000..576b8339f0d6
--- /dev/null
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -0,0 +1,886 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc7-hammer
+# Thu Mar 27 16:39:48 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_BUG is not set
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLAB is not set
+# CONFIG_SLUB is not set
+CONFIG_SLOB=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_S3C2410=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+CONFIG_PLAT_S3C24XX=y
+# CONFIG_S3C2410_DMA is not set
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2410_ONLY=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+
+#
+# Power management
+#
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+
+#
+# S3C2400 Machines
+#
+CONFIG_CPU_S3C2410=y
+CONFIG_S3C2410_GPIO=y
+CONFIG_S3C2410_CLOCK=y
+
+#
+# S3C2410 Machines
+#
+# CONFIG_ARCH_SMDK2410 is not set
+# CONFIG_ARCH_H1940 is not set
+# CONFIG_MACH_N30 is not set
+# CONFIG_ARCH_BAST is not set
+# CONFIG_MACH_OTOM is not set
+# CONFIG_MACH_AML_M5900 is not set
+CONFIG_MACH_TCT_HAMMER=y
+# CONFIG_MACH_VR1000 is not set
+# CONFIG_MACH_QT2410 is not set
+
+#
+# S3C2412 Machines
+#
+# CONFIG_MACH_SMDK2413 is not set
+# CONFIG_MACH_SMDK2412 is not set
+# CONFIG_MACH_VSTMS is not set
+
+#
+# S3C2440 Machines
+#
+# CONFIG_MACH_ANUBIS is not set
+# CONFIG_MACH_OSIRIS is not set
+# CONFIG_MACH_RX3715 is not set
+# CONFIG_ARCH_S3C2440 is not set
+# CONFIG_MACH_NEXCODER_2440 is not set
+
+#
+# S3C2442 Machines
+#
+
+#
+# S3C2443 Machines
+#
+# CONFIG_MACH_SMDK2443 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=200
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+# CONFIG_INET is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=10240
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_S3C2410=y
+CONFIG_SERIAL_S3C2410_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_S3C2410=y
+CONFIG_USB_S3C2410=y
+# CONFIG_USB_S3C2410_DEBUG is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_SYSCTL is not set
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_S3C_PORT is not set
+CONFIG_DEBUG_S3C_UART=0
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/yl9200_defconfig b/arch/arm/configs/yl9200_defconfig
new file mode 100644
index 000000000000..26de37f74686
--- /dev/null
+++ b/arch/arm/configs/yl9200_defconfig
@@ -0,0 +1,1216 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc6
+# Fri Jan 11 09:53:59 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+CONFIG_ARCH_AT91RM9200DK=y
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+CONFIG_MACH_YL9200=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0000000
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=3
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+CONFIG_DAVICOM_PHY=y
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S1D135XX=y
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=y
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+CONFIG_INSTRUMENTATION=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+CONFIG_SLUB_DEBUG_ON=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_DEBUG_KOBJECT=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+CONFIG_DEBUG_LIST=y
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 6235f72a14f0..ad455ff5aebe 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_KPROBES)           += kprobes.o kprobes-decode.o
 obj-$(CONFIG_ATAGS_PROC)        += atags.o
 obj-$(CONFIG_OABI_COMPAT)       += sys_oabi-compat.o
+obj-$(CONFIG_ARM_THUMBEE)       += thumbee.o
 
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 3278e713c32a..0a0d2479274b 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -58,6 +58,9 @@ int main(void)
   DEFINE(TI_TP_VALUE,           offsetof(struct thread_info, tp_value));
   DEFINE(TI_FPSTATE,            offsetof(struct thread_info, fpstate));
   DEFINE(TI_VFPSTATE,           offsetof(struct thread_info, vfpstate));
+#ifdef CONFIG_ARM_THUMBEE
+  DEFINE(TI_THUMBEE_STATE,      offsetof(struct thread_info, thumbee_state));
+#endif
 #ifdef CONFIG_IWMMXT
   DEFINE(TI_IWMMXT_STATE,       offsetof(struct thread_info, fpstate.iwmmxt));
 #endif
@@ -108,5 +111,12 @@ int main(void)
   DEFINE(PROCINFO_INITFUNC,     offsetof(struct proc_info_list, __cpu_flush));
   DEFINE(PROCINFO_MM_MMUFLAGS,  offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
   DEFINE(PROCINFO_IO_MMUFLAGS,  offsetof(struct proc_info_list, __cpu_io_mmu_flags));
+  BLANK();
+#ifdef MULTI_DABORT
+  DEFINE(PROCESSOR_DABT_FUNC,   offsetof(struct processor, _data_abort));
+#endif
+#ifdef MULTI_PABORT
+  DEFINE(PROCESSOR_PABT_FUNC,   offsetof(struct processor, _prefetch_abort));
+#endif
   return 0; 
 }
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 7e97b7376563..30a67a5a40a8 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -359,9 +359,11 @@
                 CALL(sys_kexec_load)
                 CALL(sys_utimensat)
                 CALL(sys_signalfd)
-/* 350 */       CALL(sys_ni_syscall)
+/* 350 */       CALL(sys_timerfd_create)
                 CALL(sys_eventfd)
                 CALL(sys_fallocate)
+                CALL(sys_timerfd_settime)
+                CALL(sys_timerfd_gettime)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index a46d5b456765..7dca225752c1 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -166,12 +166,12 @@ __dabt_svc:
         @ The abort handler must return the aborted address in r0, and
         @ the fault status register in r1.  r9 must be preserved.
         @
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
         ldr     r4, .LCprocfns
         mov     lr, pc
-        ldr     pc, [r4]
+        ldr     pc, [r4, #PROCESSOR_DABT_FUNC]
 #else
-        bl      CPU_ABORT_HANDLER
+        bl      CPU_DABORT_HANDLER
 #endif
 
         @
@@ -209,14 +209,12 @@ __irq_svc:
 
         irq_handler
 #ifdef CONFIG_PREEMPT
+        str     r8, [tsk, #TI_PREEMPT]          @ restore preempt count
         ldr     r0, [tsk, #TI_FLAGS]            @ get flags
+        teq     r8, #0                          @ if preempt count != 0
+        movne   r0, #0                          @ force flags to 0
         tst     r0, #_TIF_NEED_RESCHED
         blne    svc_preempt
-preempt_return:
-        ldr     r0, [tsk, #TI_PREEMPT]          @ read preempt value
-        str     r8, [tsk, #TI_PREEMPT]          @ restore preempt count
-        teq     r0, r7
-        strne   r0, [r0, -r0]                   @ bug()
 #endif
         ldr     r0, [sp, #S_PSR]                @ irqs are already disabled
         msr     spsr_cxsf, r0
@@ -230,19 +228,11 @@ preempt_return:
 
 #ifdef CONFIG_PREEMPT
 svc_preempt:
-        teq     r8, #0                          @ was preempt count = 0
-        ldreq   r6, .LCirq_stat
-        movne   pc, lr                          @ no
-        ldr     r0, [r6, #4]                    @ local_irq_count
-        ldr     r1, [r6, #8]                    @ local_bh_count
-        adds    r0, r0, r1
-        movne   pc, lr
-        mov     r7, #0                          @ preempt_schedule_irq
-        str     r7, [tsk, #TI_PREEMPT]          @ expects preempt_count == 0
+        mov     r8, lr
 1:      bl      preempt_schedule_irq            @ irq en/disable is done inside
         ldr     r0, [tsk, #TI_FLAGS]            @ get new tasks TI_FLAGS
         tst     r0, #_TIF_NEED_RESCHED
-        beq     preempt_return                  @ go again
+        moveq   pc, r8                          @ go again
         b       1b
 #endif
 
@@ -293,7 +283,6 @@ __pabt_svc:
         mrs     r9, cpsr
         tst     r3, #PSR_I_BIT
         biceq   r9, r9, #PSR_I_BIT
-        msr     cpsr_c, r9
 
         @
         @ set args, then call main handler
@@ -301,7 +290,15 @@ __pabt_svc:
         @  r0 - address of faulting instruction
         @  r1 - pointer to registers on stack
         @
-        mov     r0, r2                          @ address (pc)
+#ifdef MULTI_PABORT
+        mov     r0, r2                  @ pass address of aborted instruction.
+        ldr     r4, .LCprocfns
+        mov     lr, pc
+        ldr     pc, [r4, #PROCESSOR_PABT_FUNC]
+#else
+        CPU_PABORT_HANDLER(r0, r2)
+#endif
+        msr     cpsr_c, r9                      @ Maybe enable interrupts
         mov     r1, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
 
@@ -320,16 +317,12 @@ __pabt_svc:
         .align  5
 .LCcralign:
         .word   cr_alignment
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
 .LCprocfns:
         .word   processor
 #endif
 .LCfp:
         .word   fp_enter
-#ifdef CONFIG_PREEMPT
-.LCirq_stat:
-        .word   irq_stat
-#endif
 
 /*
  * User mode handlers
@@ -404,12 +397,12 @@ __dabt_usr:
         @ The abort handler must return the aborted address in r0, and
         @ the fault status register in r1.
         @
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
         ldr     r4, .LCprocfns
         mov     lr, pc
-        ldr     pc, [r4]
+        ldr     pc, [r4, #PROCESSOR_DABT_FUNC]
 #else
-        bl      CPU_ABORT_HANDLER
+        bl      CPU_DABORT_HANDLER
 #endif
 
         @
@@ -455,10 +448,6 @@ __irq_usr:
 __und_usr:
         usr_entry
 
-        tst     r3, #PSR_T_BIT                  @ Thumb mode?
-        bne     __und_usr_unknown               @ ignore FP
-        sub     r4, r2, #4
-
         @
         @ fall through to the emulation code, which returns using r9 if
         @ it has emulated the instruction, or the more conventional lr
@@ -468,7 +457,24 @@ __und_usr:
         @
         adr     r9, ret_from_exception
         adr     lr, __und_usr_unknown
-1:      ldrt    r0, [r4]
+        tst     r3, #PSR_T_BIT                  @ Thumb mode?
+        subeq   r4, r2, #4                      @ ARM instr at LR - 4
+        subne   r4, r2, #2                      @ Thumb instr at LR - 2
+1:      ldreqt  r0, [r4]
+        beq     call_fpe
+        @ Thumb instruction
+#if __LINUX_ARM_ARCH__ >= 7
+2:      ldrht   r5, [r4], #2
+        and     r0, r5, #0xf800                 @ mask bits 111x x... .... ....
+        cmp     r0, #0xe800                     @ 32bit instruction if xx != 0
+        blo     __und_usr_unknown
+3:      ldrht   r0, [r4]
+        add     r2, r2, #2                      @ r2 is PC + 2, make it PC + 4
+        orr     r0, r0, r5, lsl #16
+#else
+        b       __und_usr_unknown
+#endif
+
         @
         @ fallthrough to call_fpe
         @
@@ -477,10 +483,14 @@ __und_usr:
  * The out of line fixup for the ldrt above.
  */
         .section .fixup, "ax"
-2:      mov     pc, r9
+4:      mov     pc, r9
         .previous
         .section __ex_table,"a"
-        .long   1b, 2b
+        .long   1b, 4b
+#if __LINUX_ARM_ARCH__ >= 7
+        .long   2b, 4b
+        .long   3b, 4b
+#endif
         .previous
 
 /*
@@ -507,9 +517,16 @@ __und_usr:
  *  r10 = this threads thread_info structure.
  *  lr  = unrecognised instruction return address
  */
+        @
+        @ Fall-through from Thumb-2 __und_usr
+        @
+#ifdef CONFIG_NEON
+        adr     r6, .LCneon_thumb_opcodes
+        b       2f
+#endif
 call_fpe:
 #ifdef CONFIG_NEON
-        adr     r6, .LCneon_opcodes
+        adr     r6, .LCneon_arm_opcodes
 2:
         ldr     r7, [r6], #4                    @ mask value
         cmp     r7, #0                          @ end mask?
@@ -526,6 +543,7 @@ call_fpe:
 1:
 #endif
         tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
+        tstne   r0, #0x04000000                 @ bit 26 set on both ARM and Thumb-2
 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
         and     r8, r0, #0x0f000000             @ mask out op-code bits
         teqne   r8, #0x0f000000                 @ SWI (ARM6/7 bug)?
@@ -577,7 +595,7 @@ call_fpe:
 #ifdef CONFIG_NEON
         .align  6
 
-.LCneon_opcodes:
+.LCneon_arm_opcodes:
         .word   0xfe000000                      @ mask
         .word   0xf2000000                      @ opcode
 
@@ -586,6 +604,16 @@ call_fpe:
 
         .word   0x00000000                      @ mask
         .word   0x00000000                      @ opcode
+
+.LCneon_thumb_opcodes:
+        .word   0xef000000                      @ mask
+        .word   0xef000000                      @ opcode
+
+        .word   0xff100000                      @ mask
+        .word   0xf9000000                      @ opcode
+
+        .word   0x00000000                      @ mask
+        .word   0x00000000                      @ opcode
 #endif
 
 do_fpe:
@@ -619,8 +647,15 @@ __und_usr_unknown:
 __pabt_usr:
         usr_entry
 
+#ifdef MULTI_PABORT
+        mov     r0, r2                  @ pass address of aborted instruction.
+        ldr     r4, .LCprocfns
+        mov     lr, pc
+        ldr     pc, [r4, #PROCESSOR_PABT_FUNC]
+#else
+        CPU_PABORT_HANDLER(r0, r2)
+#endif
         enable_irq                              @ Enable interrupts
-        mov     r0, r2                          @ address (pc)
         mov     r1, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
         /* fall through */
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 6c90c50a9ee3..597ed00a08d8 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -352,6 +352,11 @@ sys_mmap2:
                 b       do_mmap2
 #endif
 
+ENTRY(pabort_ifar)
+                mrc     p15, 0, r0, cr6, cr0, 2
+ENTRY(pabort_noifar)
+                mov     pc, lr
+
 #ifdef CONFIG_OABI_COMPAT
 
 /*
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 50f667febe29..7e9c00a8a412 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -75,8 +75,13 @@ __error_p:
 #ifdef CONFIG_DEBUG_LL
         adr     r0, str_p1
         bl      printascii
+        mov     r0, r9
+        bl      printhex8
+        adr     r0, str_p2
+        bl      printascii
         b       __error
-str_p1: .asciz  "\nError: unrecognized/unsupported processor variant.\n"
+str_p1: .asciz  "\nError: unrecognized/unsupported processor variant (0x"
+str_p2: .asciz  ").\n"
         .align
 #endif
 
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
new file mode 100644
index 000000000000..df3f6b7ebcea
--- /dev/null
+++ b/arch/arm/kernel/thumbee.c
@@ -0,0 +1,81 @@
+/*
+ * arch/arm/kernel/thumbee.c
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/thread_notify.h>
+
+/*
+ * Access to the ThumbEE Handler Base register
+ */
+static inline unsigned long teehbr_read()
+{
+        unsigned long v;
+        asm("mrc        p14, 6, %0, c1, c0, 0\n" : "=r" (v));
+        return v;
+}
+
+static inline void teehbr_write(unsigned long v)
+{
+        asm("mcr        p14, 6, %0, c1, c0, 0\n" : : "r" (v));
+}
+
+static int thumbee_notifier(struct notifier_block *self, unsigned long cmd, void *t)
+{
+        struct thread_info *thread = t;
+
+        switch (cmd) {
+        case THREAD_NOTIFY_FLUSH:
+                thread->thumbee_state = 0;
+                break;
+        case THREAD_NOTIFY_SWITCH:
+                current_thread_info()->thumbee_state = teehbr_read();
+                teehbr_write(thread->thumbee_state);
+                break;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block thumbee_notifier_block = {
+        .notifier_call  = thumbee_notifier,
+};
+
+static int __init thumbee_init(void)
+{
+        unsigned long pfr0;
+        unsigned int cpu_arch = cpu_architecture();
+
+        if (cpu_arch < CPU_ARCH_ARMv7)
+                return 0;
+
+        /* processor feature register 0 */
+        asm("mrc        p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0));
+        if ((pfr0 & 0x0000f000) != 0x00001000)
+                return 0;
+
+        printk(KERN_INFO "ThumbEE CPU extension supported.\n");
+        elf_hwcap |= HWCAP_THUMBEE;
+        thread_register_notifier(&thumbee_notifier_block);
+
+        return 0;
+}
+
+late_initcall(thumbee_init);
diff --git a/arch/arm/mach-aaec2000/clock.c b/arch/arm/mach-aaec2000/clock.c
index 74aa7a39bb68..e10ee158d720 100644
--- a/arch/arm/mach-aaec2000/clock.c
+++ b/arch/arm/mach-aaec2000/clock.c
@@ -18,8 +18,6 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 
-#include <asm/semaphore.h>
-
 #include "clock.h"
 
 static LIST_HEAD(clocks);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 074dcd5d9a7e..0fc07b6db749 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,18 +12,28 @@ config ARCH_AT91RM9200
 
 config ARCH_AT91SAM9260
         bool "AT91SAM9260 or AT91SAM9XE"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91SAM9263
         bool "AT91SAM9263"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91CAP9
         bool "AT91CAP9"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91X40
         bool "AT91x40"
@@ -109,6 +119,13 @@ config MACH_KAFA
         help
           Select this if you are using Sperry-Sun's KAFA board.
 
+config MACH_ECBAT91
+        bool "emQbit ECB_AT91 SBC"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using emQbit's ECB_AT91 board.
+          <http://wiki.emqbit.com/free-ecb-at91>
+
 endif
 
 # ----------------------------------------------------------
@@ -133,6 +150,20 @@ config MACH_AT91SAM9260EK
           Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
 
+config MACH_CAM60
+        bool "KwikByte KB9260 (CAM60) board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
+          <http://www.kwikbyte.com/KB9260.html>
+
+config MACH_SAM9_L9260
+        bool "Olimex SAM9-L9260 board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
+          <http://www.olimex.com/dev/sam9-L9260.html>
+
 endif
 
 # ----------------------------------------------------------
@@ -216,7 +247,7 @@ comment "AT91 Board Options"
 
 config MTD_AT91_DATAFLASH_CARD
         bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK)
+        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91)
         help
           Enable support for the DataFlash card.
 
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bf5f293dccf8..8d9bc0153b18 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -29,9 +29,12 @@ obj-$(CONFIG_MACH_KB9200)	+= board-kb9202.o
 obj-$(CONFIG_MACH_ATEB9200)     += board-eb9200.o
 obj-$(CONFIG_MACH_KAFA)         += board-kafa.o
 obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
+obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
 
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
+obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
+obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 48d27d8000b0..933fa8f55cbc 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -13,12 +13,14 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/arch/at91cap9.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -288,6 +290,12 @@ static void at91cap9_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91cap9_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
+
 /* --------------------------------------------------------------------
  *  AT91CAP9 processor initialization
  * -------------------------------------------------------------------- */
@@ -298,6 +306,7 @@ void __init at91cap9_initialize(unsigned long main_clock)
         iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
 
         at91_arch_reset = at91cap9_reset;
+        pm_power_off = at91cap9_poweroff;
         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 
         /* Init clock subsystem */
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index c50fad9cd143..f1a80d74a4b6 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -16,15 +16,15 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
+#include <linux/i2c-gpio.h>
 
 #include <video/atmel_lcdc.h>
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91cap9.h>
-#include <asm/arch/at91sam926x_mc.h>
 #include <asm/arch/at91cap9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -283,10 +283,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -344,6 +349,7 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
 void __init at91_add_device_nand(struct at91_nand_data *data) {}
 #endif
 
+
 /* --------------------------------------------------------------------
  *  TWI (i2c)
  * -------------------------------------------------------------------- */
@@ -532,13 +538,59 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91CAP9_BASE_TCB0,
+                .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91CAP9_ID_TCB,
+                .end    = AT91CAP9_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91cap9_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has one clock and irq for all three TC channels */
+        at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
+        platform_device_register(&at91cap9_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
+static struct resource rtt_resources[] = {
+        {
+                .start  = AT91_BASE_SYS + AT91_RTT,
+                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91cap9_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
-        .num_resources  = 0,
+        .id             = 0,
+        .resource       = rtt_resources,
+        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
 static void __init at91_add_device_rtt(void)
@@ -990,7 +1042,7 @@ static inline void configure_usart2_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
@@ -1031,8 +1083,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1043,6 +1093,9 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
@@ -1060,6 +1113,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index ef6aeb86e980..de19bee83f75 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -577,6 +577,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+        [0] = {
+                .start  = AT91RM9200_BASE_TCB0,
+                .end    = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91RM9200_ID_TC0,
+                .end    = AT91RM9200_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91RM9200_ID_TC1,
+                .end    = AT91RM9200_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91RM9200_ID_TC2,
+                .end    = AT91RM9200_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91rm9200_tcb0_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb0_resources,
+        .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+        [0] = {
+                .start  = AT91RM9200_BASE_TCB1,
+                .end    = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91RM9200_ID_TC3,
+                .end    = AT91RM9200_ID_TC3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91RM9200_ID_TC4,
+                .end    = AT91RM9200_ID_TC4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91RM9200_ID_TC5,
+                .end    = AT91RM9200_ID_TC5,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91rm9200_tcb1_device = {
+        .name           = "atmel_tcb",
+        .id             = 1,
+        .resource       = tcb1_resources,
+        .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk");
+        platform_device_register(&at91rm9200_tcb0_device);
+
+        at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk");
+        at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk");
+        at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk");
+        platform_device_register(&at91rm9200_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTC
  * -------------------------------------------------------------------- */
 
@@ -1019,7 +1103,7 @@ static inline void configure_usart3_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PB0, 0);     /* RTS3 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
@@ -1110,8 +1194,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1122,6 +1204,9 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
@@ -1141,6 +1226,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtc();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 18d06612ce8a..ee26550cdc21 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -18,6 +19,7 @@
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -267,6 +269,11 @@ static void at91sam9260_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9260_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9260 processor initialization
@@ -304,6 +311,7 @@ void __init at91sam9260_initialize(unsigned long main_clock)
                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 
         at91_arch_reset = at91sam9260_reset;
+        pm_power_off = at91sam9260_poweroff;
         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                         | (1 << AT91SAM9260_ID_IRQ2);
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 105f8403860b..393a32aefce5 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -19,8 +19,8 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam926x_mc.h>
 #include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -288,10 +288,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -540,6 +545,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_TCB0,
+                .end    = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_TC0,
+                .end    = AT91SAM9260_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9260_ID_TC1,
+                .end    = AT91SAM9260_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9260_ID_TC2,
+                .end    = AT91SAM9260_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_tcb0_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb0_resources,
+        .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_TCB1,
+                .end    = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_TC3,
+                .end    = AT91SAM9260_ID_TC3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9260_ID_TC4,
+                .end    = AT91SAM9260_ID_TC4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9260_ID_TC5,
+                .end    = AT91SAM9260_ID_TC5,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_tcb1_device = {
+        .name           = "atmel_tcb",
+        .id             = 1,
+        .resource       = tcb1_resources,
+        .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
+        platform_device_register(&at91sam9260_tcb0_device);
+
+        at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
+        at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
+        at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
+        platform_device_register(&at91sam9260_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
@@ -553,7 +642,7 @@ static struct resource rtt_resources[] = {
 
 static struct platform_device at91sam9260_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
+        .id             = 0,
         .resource       = rtt_resources,
         .num_resources  = ARRAY_SIZE(rtt_resources),
 };
@@ -962,64 +1051,9 @@ static inline void configure_usart5_pins(void)
         at91_set_A_periph(AT91_PIN_PB13, 0);            /* RXD5 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
-                                at91_uarts[i] = &at91sam9260_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9260_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(0);
-                                at91_uarts[i] = &at91sam9260_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_usart3_pins(0);
-                                at91_uarts[i] = &at91sam9260_uart3_device;
-                                at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
-                                break;
-                        case 4:
-                                configure_usart4_pins();
-                                at91_uarts[i] = &at91sam9260_uart4_device;
-                                at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
-                                break;
-                        case 5:
-                                configure_usart5_pins();
-                                at91_uarts[i] = &at91sam9260_uart5_device;
-                                at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
-                                break;
-                        case 6:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9260_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -1073,8 +1107,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1085,9 +1117,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -1103,6 +1137,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 90b87e1877d9..35bf6fd52516 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,12 +11,14 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -245,6 +247,11 @@ static void at91sam9261_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9261_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9261 processor initialization
@@ -256,6 +263,7 @@ void __init at91sam9261_initialize(unsigned long main_clock)
         iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
 
         at91_arch_reset = at91sam9261_reset;
+        pm_power_off = at91sam9261_poweroff;
         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                         | (1 << AT91SAM9261_ID_IRQ2);
 
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 245641263fce..37cd547855b1 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,7 +24,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91sam9261_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -548,6 +548,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_TCB0,
+                .end    = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_TC0,
+                .end    = AT91SAM9261_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9261_ID_TC1,
+                .end    = AT91SAM9261_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9261_ID_TC2,
+                .end    = AT91SAM9261_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk");
+        platform_device_register(&at91sam9261_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
@@ -561,7 +610,7 @@ static struct resource rtt_resources[] = {
 
 static struct platform_device at91sam9261_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
+        .id             = 0,
         .resource       = rtt_resources,
         .num_resources  = ARRAY_SIZE(rtt_resources),
 };
@@ -938,49 +987,9 @@ static inline void configure_usart2_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PA16, 0);    /* CTS2 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9261_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(0);
-                                at91_uarts[i] = &at91sam9261_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(0);
-                                at91_uarts[i] = &at91sam9261_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9261_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -1019,8 +1028,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1031,9 +1038,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -1050,6 +1059,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index a53ba0f74351..052074a9f2d3 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,12 +11,14 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -271,6 +273,11 @@ static void at91sam9263_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9263_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9263 processor initialization
@@ -282,6 +289,7 @@ void __init at91sam9263_initialize(unsigned long main_clock)
         iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
 
         at91_arch_reset = at91sam9263_reset;
+        pm_power_off = at91sam9263_poweroff;
         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
         /* Init clock subsystem */
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 0b12e1adcc8e..b6454c525962 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -22,8 +22,8 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam926x_mc.h>
 #include <asm/arch/at91sam9263_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -358,10 +358,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC0,
+                .end    = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -783,6 +788,43 @@ void __init at91_add_device_isi(void) {}
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91SAM9263_BASE_TCB0,
+                .end    = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9263_ID_TCB,
+                .end    = AT91SAM9263_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9263_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has one clock and irq for all three TC channels */
+        at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
+        platform_device_register(&at91sam9263_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
@@ -933,9 +975,6 @@ static inline void configure_ssc1_pins(unsigned pins)
 }
 
 /*
- * Return the device node so that board init code can use it as the
- * parent for the device node reflecting how it's used on this board.
- *
  * SSC controllers are accessed through library code, instead of any
  * kind of all-singing/all-dancing driver.  For example one could be
  * used by a particular I2S audio codec's driver, while another one
@@ -1146,49 +1185,9 @@ static inline void configure_usart2_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9263_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9263_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9263_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9263_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9263_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9263_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9263_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9263_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -1227,8 +1226,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1239,9 +1236,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -1257,6 +1256,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index e38d23770992..5cecbd7de6a6 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -1,23 +1,20 @@
 /*
- * linux/arch/arm/mach-at91/at91sam926x_time.c
+ * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
  *
  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
  * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
+ * Converted to ClockSource/ClockEvents by David Brownell.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
 
-#include <asm/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/time.h>
 
 #include <asm/arch/at91_pit.h>
@@ -26,85 +23,167 @@
 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
 #define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
 
+static u32 pit_cycle;           /* write-once */
+static u32 pit_cnt;             /* access only w/system irq blocked */
+
+
 /*
- * Returns number of microseconds since last timer interrupt.  Note that interrupts
- * will have been disabled by do_gettimeofday()
- *  'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * Clocksource:  just a monotonic counter of MCK/16 cycles.
+ * We don't care whether or not PIT irqs are enabled.
  */
-static unsigned long at91sam926x_gettimeoffset(void)
+static cycle_t read_pit_clk(void)
 {
-        unsigned long elapsed;
-        unsigned long t = at91_sys_read(AT91_PIT_PIIR);
+        unsigned long flags;
+        u32 elapsed;
+        u32 t;
+
+        raw_local_irq_save(flags);
+        elapsed = pit_cnt;
+        t = at91_sys_read(AT91_PIT_PIIR);
+        raw_local_irq_restore(flags);
+
+        elapsed += PIT_PICNT(t) * pit_cycle;
+        elapsed += PIT_CPIV(t);
+        return elapsed;
+}
+
+static struct clocksource pit_clk = {
+        .name           = "pit",
+        .rating         = 175,
+        .read           = read_pit_clk,
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
 
-        elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t);         /* hardware clock cycles */
 
-        return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
+/*
+ * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
+ */
+static void
+pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+        unsigned long   flags;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* update clocksource counter, then enable the IRQ */
+                raw_local_irq_save(flags);
+                pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+                                | AT91_PIT_PITIEN);
+                raw_local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                BUG();
+                /* FALLTHROUGH */
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                /* disable irq, leaving the clocksource active */
+                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
 }
 
+static struct clock_event_device pit_clkevt = {
+        .name           = "pit",
+        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 100,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_mode       = pit_clkevt_mode,
+};
+
+
 /*
  * IRQ handler for the timer.
  */
-static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 {
-        volatile long nr_ticks;
 
-        if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) {       /* This is a shared interrupt */
-                /* Get number to ticks performed before interrupt and clear PIT interrupt */
+        /* The PIT interrupt may be disabled, and is shared */
+        if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
+                        && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
+                unsigned nr_ticks;
+
+                /* Get number of ticks performed before irq, and ack it */
                 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
                 do {
-                        timer_tick();
+                        pit_cnt += pit_cycle;
+                        pit_clkevt.event_handler(&pit_clkevt);
                         nr_ticks--;
                 } while (nr_ticks);
 
                 return IRQ_HANDLED;
-        } else
-                return IRQ_NONE;                /* not handled */
+        }
+
+        return IRQ_NONE;
 }
 
-static struct irqaction at91sam926x_timer_irq = {
+static struct irqaction at91sam926x_pit_irq = {
         .name           = "at91_tick",
         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91sam926x_timer_interrupt
+        .handler        = at91sam926x_pit_interrupt
 };
 
-void at91sam926x_timer_reset(void)
+static void at91sam926x_pit_reset(void)
 {
-        /* Disable timer */
+        /* Disable timer and irqs */
         at91_sys_write(AT91_PIT_MR, 0);
 
-        /* Clear any pending interrupts */
-        (void) at91_sys_read(AT91_PIT_PIVR);
+        /* Clear any pending interrupts, wait for PIT to stop counting */
+        while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+                cpu_relax();
 
-        /* Set Period Interval timer and enable its interrupt */
-        at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
+        /* Start PIT but don't enable IRQ */
+        at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
 /*
- * Set up timer interrupt.
+ * Set up both clocksource and clockevent support.
  */
-void __init at91sam926x_timer_init(void)
+static void __init at91sam926x_pit_init(void)
 {
-        /* Initialize and enable the timer */
-        at91sam926x_timer_reset();
+        unsigned long   pit_rate;
+        unsigned        bits;
+
+        /*
+         * Use our actual MCK to figure out how many MCK/16 ticks per
+         * 1/HZ period (instead of a compile-time constant LATCH).
+         */
+        pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+        pit_cycle = (pit_rate + HZ/2) / HZ;
+        WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
 
-        /* Make IRQs happen for the system timer. */
-        setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
+        /* Initialize and enable the timer */
+        at91sam926x_pit_reset();
+
+        /*
+         * Register clocksource.  The high order bits of PIV are unused,
+         * so this isn't a 32-bit counter unless we get clockevent irqs.
+         */
+        pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
+        bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
+        pit_clk.mask = CLOCKSOURCE_MASK(bits);
+        clocksource_register(&pit_clk);
+
+        /* Set up irq handler */
+        setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+
+        /* Set up and register clockevents */
+        pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
+        clockevents_register_device(&pit_clkevt);
 }
 
-#ifdef CONFIG_PM
-static void at91sam926x_timer_suspend(void)
+static void at91sam926x_pit_suspend(void)
 {
         /* Disable timer */
         at91_sys_write(AT91_PIT_MR, 0);
 }
-#else
-#define at91sam926x_timer_suspend       NULL
-#endif
 
 struct sys_timer at91sam926x_timer = {
-        .init           = at91sam926x_timer_init,
-        .offset         = at91sam926x_gettimeoffset,
-        .suspend        = at91sam926x_timer_suspend,
-        .resume         = at91sam926x_timer_reset,
+        .init           = at91sam926x_pit_init,
+        .suspend        = at91sam926x_pit_suspend,
+        .resume         = at91sam926x_pit_reset,
 };
-
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 4813a35f6cf5..902c79893ec7 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -17,6 +18,7 @@
 #include <asm/arch/at91sam9rl.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -244,6 +246,11 @@ static void at91sam9rl_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9rl_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9RL processor initialization
@@ -274,6 +281,7 @@ void __init at91sam9rl_initialize(unsigned long main_clock)
         iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
 
         at91_arch_reset = at91sam9rl_reset;
+        pm_power_off = at91sam9rl_poweroff;
         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
         /* Init clock subsystem */
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f43b5c33e45d..dbb9a5fc2090 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,7 +20,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9rl.h>
 #include <asm/arch/at91sam9rl_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -105,10 +105,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -385,6 +390,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_BASE_TCB0,
+                .end    = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9RL_ID_TC0,
+                .end    = AT91SAM9RL_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9RL_ID_TC1,
+                .end    = AT91SAM9RL_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9RL_ID_TC2,
+                .end    = AT91SAM9RL_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9rl_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
+        platform_device_register(&at91sam9rl_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTC
  * -------------------------------------------------------------------- */
 
@@ -418,7 +472,7 @@ static struct resource rtt_resources[] = {
 
 static struct platform_device at91sam9rl_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
+        .id             = 0,
         .resource       = rtt_resources,
         .num_resources  = ARRAY_SIZE(rtt_resources),
 };
@@ -539,9 +593,6 @@ static inline void configure_ssc1_pins(unsigned pins)
 }
 
 /*
- * Return the device node so that board init code can use it as the
- * parent for the device node reflecting how it's used on this board.
- *
  * SSC controllers are accessed through library code, instead of any
  * kind of all-singing/all-dancing driver.  For example one could be
  * used by a particular I2S audio codec's driver, while another one
@@ -802,54 +853,9 @@ static inline void configure_usart3_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PD3, 0);     /* CTS3 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9rl_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(0);
-                                at91_uarts[i] = &at91sam9rl_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(0);
-                                at91_uarts[i] = &at91sam9rl_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_usart3_pins(0);
-                                at91_uarts[i] = &at91sam9rl_uart3_device;
-                                at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
-                                break;
-                        case 4:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9rl_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -893,8 +899,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -905,9 +909,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -925,6 +931,7 @@ static int __init at91_add_standard_devices(void)
         at91_add_device_rtc();
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
new file mode 100644
index 000000000000..b22a1a004055
--- /dev/null
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -0,0 +1,180 @@
+/*
+ * KwikByte CAM60 (KB9260)
+ *
+ * based on board-sam9260ek.c
+ *   Copyright (C) 2005 SAN People
+ *   Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init cam60_map_io(void)
+{
+        /* Initialize processor: 10 MHz crystal */
+        at91sam9260_initialize(10000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init cam60_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host
+ */
+static struct at91_usbh_data __initdata cam60_usbh_data = {
+        .ports          = 1,
+};
+
+
+/*
+ * SPI devices.
+ */
+#if defined(CONFIG_MTD_DATAFLASH)
+static struct mtd_partition __initdata cam60_spi_partitions[] = {
+        {
+                .name   = "BOOT1",
+                .offset = 0,
+                .size   = 4 * 1056,
+        },
+        {
+                .name   = "BOOT2",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 256 * 1056,
+        },
+        {
+                .name   = "kernel",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 2222 * 1056,
+        },
+        {
+                .name   = "file system",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct flash_platform_data __initdata cam60_spi_flash_platform_data = {
+        .name           = "spi_flash",
+        .parts          = cam60_spi_partitions,
+        .nr_parts       = ARRAY_SIZE(cam60_spi_partitions)
+};
+#endif
+
+static struct spi_board_info cam60_spi_devices[] = {
+#if defined(CONFIG_MTD_DATAFLASH)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+                .platform_data  = &cam60_spi_flash_platform_data
+        },
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct __initdata at91_eth_data cam60_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PB5,
+        .is_rmii        = 0,
+};
+
+
+/*
+ * NAND Flash
+ */
+static struct mtd_partition __initdata cam60_nand_partition[] = {
+        {
+                .name   = "nand_fs",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(cam60_nand_partition);
+        return cam60_nand_partition;
+}
+
+static struct at91_nand_data __initdata cam60_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        // .det_pin     = ... not there
+        .rdy_pin        = AT91_PIN_PA9,
+        .enable_pin     = AT91_PIN_PA7,
+        .partition_info = nand_partitions,
+};
+
+
+static void __init cam60_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* SPI */
+        at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
+        /* Ethernet */
+        at91_add_device_eth(&cam60_macb_data);
+        /* USB Host */
+        /* enable USB power supply circuit */
+        at91_set_gpio_output(AT91_PIN_PB18, 1);
+        at91_add_device_usbh(&cam60_usbh_data);
+        /* NAND */
+        at91_add_device_nand(&cam60_nand_data);
+}
+
+MACHINE_START(CAM60, "KwikByte CAM60")
+        /* Maintainer: KwikByte */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = cam60_map_io,
+        .init_irq       = cam60_init_irq,
+        .init_machine   = cam60_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 185437131541..e5512d1ff217 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -45,7 +45,7 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91cap9_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 0e2a11fc5bbd..26fea4dcc3a0 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -43,17 +43,6 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata csb337_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init csb337_map_io(void)
 {
         /* Initialize processor: 3.6864 MHz crystal */
@@ -62,8 +51,11 @@ static void __init csb337_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&csb337_uart_config);
+        /* DBGU on ttyS0 */
+        at91_register_uart(0, 0, 0);
+
+        /* make console=ttyS0 the default */
+        at91_set_serial_console(0);
 }
 
 static void __init csb337_init_irq(void)
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index c5c721d27f42..419fd19b620b 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -40,27 +40,16 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata csb637_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init csb637_map_io(void)
 {
         /* Initialize processor: 3.6864 MHz crystal */
         at91rm9200_initialize(3686400, AT91RM9200_BGA);
 
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
+        /* DBGU on ttyS0 */
+        at91_register_uart(0, 0, 0);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&csb637_uart_config);
+        /* make console=ttyS0 the default */
+        at91_set_serial_console(0);
 }
 
 static void __init csb637_init_irq(void)
@@ -118,8 +107,19 @@ static struct platform_device csb_flash = {
         .num_resources  = ARRAY_SIZE(csb_flash_resources),
 };
 
+static struct gpio_led csb_leds[] = {
+        {       /* "d1", red */
+                .name                   = "d1",
+                .gpio                   = AT91_PIN_PB2,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+};
+
 static void __init csb637_board_init(void)
 {
+        /* LED(s) */
+        at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
         /* Serial */
         at91_add_device_serial();
         /* Ethernet */
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
new file mode 100644
index 000000000000..e77fad443835
--- /dev/null
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -0,0 +1,178 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/board-ecbat91.c
+ * Copyright (C) 2007 emQbit.com.
+ *
+ * We started from board-dk.c, which is Copyright (C) 2005 SAN People.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ecb_at91map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx & Tx only) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ecb_at91init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+
+static struct at91_eth_data __initdata ecb_at91eth_data = {
+        .phy_irq_pin    = AT91_PIN_PC4,
+        .is_rmii        = 0,
+};
+
+static struct at91_usbh_data __initdata ecb_at91usbh_data = {
+        .ports          = 1,
+};
+
+static struct at91_mmc_data __initdata ecb_at91mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 1,
+};
+
+
+#if defined(CONFIG_MTD_DATAFLASH)
+static struct mtd_partition __initdata my_flash0_partitions[] =
+{
+        {       /* 0x8400 */
+                .name   = "Darrell-loader",
+                .offset = 0,
+                .size   = 12* 1056,
+        },
+        {
+                .name   = "U-boot",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 110 * 1056,
+        },
+        {       /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
+                .name   = "UBoot-env",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 8 * 1056,
+        },
+        {       /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
+                .name   = "Kernel",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 1534 * 1056,
+        },
+        {       /* 190200 - jffs2 root filesystem */
+                .name   = "Filesystem",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,     /* 26 sectors */
+        }
+};
+
+static struct flash_platform_data __initdata my_flash0_platform = {
+        .name           = "Removable flash card",
+        .parts          = my_flash0_partitions,
+        .nr_parts       = ARRAY_SIZE(my_flash0_partitions)
+};
+
+#endif
+
+static struct spi_board_info __initdata ecb_at91spi_devices[] = {
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+#if defined(CONFIG_MTD_DATAFLASH)
+                .platform_data  = &my_flash0_platform,
+#endif
+        },
+        {       /* User accessable spi - cs1 (250KHz) */
+                .modalias       = "spi-cs1",
+                .chip_select    = 1,
+                .max_speed_hz   = 250 * 1000,
+        },
+        {       /* User accessable spi - cs2 (1MHz) */
+                .modalias       = "spi-cs2",
+                .chip_select    = 2,
+                .max_speed_hz   = 1 * 1000 * 1000,
+        },
+        {       /* User accessable spi - cs3 (10MHz) */
+                .modalias       = "spi-cs3",
+                .chip_select    = 3,
+                .max_speed_hz   = 10 * 1000 * 1000,
+        },
+};
+
+static void __init ecb_at91board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+
+        /* Ethernet */
+        at91_add_device_eth(&ecb_at91eth_data);
+
+        /* USB Host */
+        at91_add_device_usbh(&ecb_at91usbh_data);
+
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+
+        /* MMC */
+        at91_add_device_mmc(0, &ecb_at91mmc_data);
+
+        /* SPI */
+        at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
+}
+
+MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
+        /* Maintainer: emQbit.com */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91rm9200_timer,
+        .map_io         = ecb_at91map_io,
+        .init_irq       = ecb_at91init_irq,
+        .init_machine   = ecb_at91board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
new file mode 100644
index 000000000000..8f76af5e219a
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -0,0 +1,199 @@
+/*
+ * linux/arch/arm/mach-at91/board-sam9-l9260.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2007 Olimex Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* DataFlash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA7,
+        .is_rmii        = 0,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Bootloader Area",
+                .offset = 0,
+                .size   = 10 * 1024 * 1024,
+        },
+        {
+                .name   = "User Area",
+                .offset = 10 * 1024 * 1024,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .slot_b         = 1,
+        .wire4          = 1,
+        .det_pin        = AT91_PIN_PC8,
+        .wp_pin         = AT91_PIN_PC4,
+//      .vcc_pin        = ... not connected
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &ek_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+}
+
+MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
+        /* Maintainer: Olimex */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index b343a6c28120..4d1d9c777084 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -25,6 +25,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/setup.h>
@@ -37,29 +39,28 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 5 = USART0 .. USART5
- *    6      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 3,
-        .tty_map        = { 6, 0, 1, -1, -1, -1, -1 }   /* ttyS0, ..., ttyS6 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -85,6 +86,35 @@ static struct at91_udc_data __initdata ek_udc_data = {
 
 
 /*
+ * Audio
+ */
+static struct at73c213_board_info at73c213_data = {
+        .ssc_id         = 0,
+        .shortname      = "AT91SAM9260-EK external DAC",
+};
+
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+static void __init at73c213_set_clk(struct at73c213_board_info *info)
+{
+        struct clk *pck0;
+        struct clk *plla;
+
+        pck0 = clk_get(NULL, "pck0");
+        plla = clk_get(NULL, "plla");
+
+        /* AT73C213 MCK Clock */
+        at91_set_B_periph(AT91_PIN_PC1, 0);     /* PCK0 */
+
+        clk_set_parent(pck0, plla);
+        clk_put(plla);
+
+        info->dac_clk = pck0;
+}
+#else
+static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
+#endif
+
+/*
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
@@ -110,6 +140,8 @@ static struct spi_board_info ek_spi_devices[] = {
                 .chip_select    = 0,
                 .max_speed_hz   = 10 * 1000 * 1000,
                 .bus_num        = 1,
+                .mode           = SPI_MODE_1,
+                .platform_data  = &at73c213_data,
         },
 #endif
 };
@@ -172,6 +204,24 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
 //      .vcc_pin        = ... not connected
 };
 
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds5",
+                .gpio                   = AT91_PIN_PA6,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PA9,
+                .default_trigger        = "heartbeat",
+        }
+};
+
 static void __init ek_board_init(void)
 {
         /* Serial */
@@ -190,6 +240,11 @@ static void __init ek_board_init(void)
         at91_add_device_mmc(0, &ek_mmc_data);
         /* I2C */
         at91_add_device_i2c(NULL, 0);
+        /* SSC (to AT73C213) */
+        at73c213_set_clk(&at73c213_data);
+        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 0ce38dfa6ebe..08382c0df221 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -26,6 +26,8 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
 #include <linux/dm9000.h>
 #include <linux/fb.h>
 #include <linux/gpio_keys.h>
@@ -44,22 +46,11 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 2 = USART0 .. USART2
- *    3      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 1,
-        .tty_map        = { 3, -1, -1, -1 }             /* ttyS0, ..., ttyS3 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
@@ -68,8 +59,11 @@ static void __init ek_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -239,6 +233,35 @@ static void __init ek_add_device_ts(void) {}
 #endif
 
 /*
+ * Audio
+ */
+static struct at73c213_board_info at73c213_data = {
+        .ssc_id         = 1,
+        .shortname      = "AT91SAM9261-EK external DAC",
+};
+
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+static void __init at73c213_set_clk(struct at73c213_board_info *info)
+{
+        struct clk *pck2;
+        struct clk *plla;
+
+        pck2 = clk_get(NULL, "pck2");
+        plla = clk_get(NULL, "plla");
+
+        /* AT73C213 MCK Clock */
+        at91_set_B_periph(AT91_PIN_PB31, 0);    /* PCK2 */
+
+        clk_set_parent(pck2, plla);
+        clk_put(plla);
+
+        info->dac_clk = pck2;
+}
+#else
+static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
+#endif
+
+/*
  * SPI devices
  */
 static struct spi_board_info ek_spi_devices[] = {
@@ -256,6 +279,7 @@ static struct spi_board_info ek_spi_devices[] = {
                 .bus_num        = 0,
                 .platform_data  = &ads_info,
                 .irq            = AT91SAM9261_ID_IRQ0,
+                .controller_data = (void *) AT91_PIN_PA28,      /* CS pin */
         },
 #endif
 #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
@@ -271,6 +295,9 @@ static struct spi_board_info ek_spi_devices[] = {
                 .chip_select    = 3,
                 .max_speed_hz   = 10 * 1000 * 1000,
                 .bus_num        = 0,
+                .mode           = SPI_MODE_1,
+                .platform_data  = &at73c213_data,
+                .controller_data = (void*) AT91_PIN_PA29,       /* default for CS3 is PA6, but it must be PA29 */
         },
 #endif
 };
@@ -460,6 +487,29 @@ static void __init ek_add_device_buttons(void)
 static void __init ek_add_device_buttons(void) {}
 #endif
 
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds7",
+                .gpio                   = AT91_PIN_PA14,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "top" led, green, userled2 to be defined */
+                .name                   = "ds8",
+                .gpio                   = AT91_PIN_PA13,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PA23,
+                .default_trigger        = "heartbeat",
+        }
+};
+
 static void __init ek_board_init(void)
 {
         /* Serial */
@@ -481,6 +531,9 @@ static void __init ek_board_init(void)
         at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
         /* Touchscreen */
         ek_add_device_ts();
+        /* SSC (to AT73C213) */
+        at73c213_set_clk(&at73c213_data);
+        at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
 #else
         /* MMC */
         at91_add_device_mmc(0, &ek_mmc_data);
@@ -489,6 +542,8 @@ static void __init ek_board_init(void)
         at91_add_device_lcdc(&ek_lcdc_data);
         /* Push Buttons */
         ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index bf103b24c937..b4cd5d0ed597 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -43,29 +43,24 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 2 = USART0 .. USART2
- *    3      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 3, 0, -1, -1, }             /* ttyS0, ..., ttyS3 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 16.367 MHz crystal */
         at91sam9263_initialize(16367660);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -341,7 +336,7 @@ static struct gpio_led ek_leds[] = {
                 .name                   = "ds3",
                 .gpio                   = AT91_PIN_PB7,
                 .default_trigger        = "heartbeat",
-        },
+        }
 };
 
 
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index bc0546d7245f..ffc0597aee8d 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -29,29 +29,24 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 0, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 12.000 MHz crystal */
         at91sam9rl_initialize(12000000);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
new file mode 100755
index 000000000000..b5717108991d
--- /dev/null
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -0,0 +1,683 @@
+/*
+ * linux/arch/arm/mach-at91/board-yl-9200.c
+ *
+ * Adapted from:
+ *various board files in
+ * /arch/arm/mach-at91
+ * modifications  to convert to  YL-9200 platform
+ *  Copyright (C) 2007 S.Birtles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+/*#include <linux/can_bus/candata.h>*/
+#include <linux/spi/ads7846.h>
+#include <linux/mtd/physmap.h>
+
+/*#include <sound/gpio_sounder.h>*/
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mc.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include "generic.h"
+#include <asm/arch/at91_pio.h>
+
+#define YL_9200_FLASH_BASE      AT91_CHIPSELECT_0
+#define YL_9200_FLASH_SIZE      0x800000
+
+/*
+ * Serial port configuration.
+ *    0 .. 3 = USART0 .. USART3
+ *    4      = DBGU
+ *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
+ *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
+ *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
+ *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
+ *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
+ * on the YL-9200 we are sitting at the following
+ *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
+ *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
+ */
+
+/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/
+
+static struct at91_uart_config __initdata yl_9200_uart_config = {
+        .console_tty    = 0,                            /* ttyS0 */
+        .nr_tty         = 3,
+        .tty_map        = { 4, 1, 0, -1, -1 }           /* ttyS0, ..., ttyS4 */
+};
+
+static void __init yl_9200_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        /*Also initialises register clocks & gpio*/
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
+
+        /* Setup the serial ports and console */
+        at91_init_serial(&yl_9200_uart_config);
+
+        /* Setup the LEDs D2=PB17,D3=PB16 */
+        at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/
+}
+
+static void __init yl_9200_init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+
+static struct at91_eth_data __initdata yl_9200_eth_data = {
+        .phy_irq_pin    = AT91_PIN_PB28,
+        .is_rmii        = 1,
+};
+
+static struct at91_usbh_data __initdata yl_9200_usbh_data = {
+        .ports          = 1,  /* this should be 1 not 2 for the Yl9200*/
+};
+
+static struct at91_udc_data __initdata yl_9200_udc_data = {
+/*on sheet 7 Schemitic rev 1.0*/
+        .pullup_pin     = AT91_PIN_PC4,
+        .vbus_pin=  AT91_PIN_PC5,
+        .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
+
+};
+/*
+static struct at91_cf_data __initdata yl_9200_cf_data = {
+TODO S.BIRTLES
+        .det_pin        = AT91_PIN_xxx,
+        .rst_pin        = AT91_PIN_xxx,
+        .irq_pin        = ... not connected
+        .vcc_pin        = ... always powered
+
+};
+*/
+static struct at91_mmc_data __initdata yl_9200_mmc_data = {
+        .det_pin        = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
+/*      .wp_pin         = ... not connected  SHEET7*/
+        .slot_b         = 0,
+        .wire4          = 1,
+
+};
+
+/* --------------------------------------------------------------------
+ *  Touch screen
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static int ads7843_pendown_state(void)
+{
+        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
+}
+
+static void __init at91_init_device_ts(void)
+{
+/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
+THAT IS TO SAY THAT  MISO,MOSI,SPCK AND CS  are already configured
+we only need to enable the other datapins which are:
+PB10/RK1 BUSY
+*/
+/* Touchscreen BUSY signal ,  pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
+at91_set_gpio_input(AT91_PIN_PB10, 1);
+}
+
+#else
+static void __init at91_init_device_ts(void) {}
+#endif
+
+static struct ads7846_platform_data ads_info = {
+        .model                  = 7843,
+        .x_min                  = 150,
+        .x_max                  = 3830,
+        .y_min                  = 190,
+        .y_max                  = 3830,
+        .vref_delay_usecs       = 100,
+/* for a 8" touch screen*/
+        //.x_plate_ohms         = 603, //= 450, S.Birtles TODO
+        //.y_plate_ohms         = 332, //= 250, S.Birtles TODO
+/*for a 10.4" touch screen*/
+        //.x_plate_ohms         =611,
+        //.y_plate_ohms         =325,
+
+        .x_plate_ohms   = 576,
+        .y_plate_ohms   = 366,
+                //
+        .pressure_max           = 15000, /*generally nonsense on the 7843*/
+         /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
+        .debounce_max           = 1,
+        .debounce_rep           = 0,
+        .debounce_tol           = (~0),
+        .get_pendown_state      = ads7843_pendown_state,
+};
+
+/*static struct canbus_platform_data can_info = {
+        .model                  = 2510,
+};
+*/
+
+static struct spi_board_info yl_9200_spi_devices[] = {
+/*this sticks it at:
+ /sys/devices/platform/atmel_spi.0/spi0.0
+ /sys/bus/platform/devices/
+Documentation/spi IIRC*/
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ /*(this IS correct 04-NOV-2007)*/
+        {
+                .modalias               = "ads7846", /* because the driver is called ads7846*/
+                .chip_select    = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
+/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/
+                /*.controller_data =AT91_PIN_PA3 ,*/
+                .max_speed_hz   = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
+                .bus_num                = 0,
+                .platform_data  = &ads_info,
+                .irq                    = AT91_PIN_PB11,
+        },
+#endif
+/*we need to put our CAN driver data here!!*/
+/*THIS IS ALL DUMMY DATA*/
+/*      {
+                .modalias               = "mcp2510", //DUMMY for MCP2510 chip
+                .chip_select    = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
+        /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
+        /*  .controller_data =AT91_PIN_PA4 ,
+                .max_speed_hz   = 25000 * 26,
+                .bus_num                = 0,
+                .platform_data  = &can_info,
+                .irq                    = AT91_PIN_PC0,
+        },
+        */
+        //max SPI chip needs to go here
+};
+
+static struct mtd_partition __initdata yl_9200_nand_partition[] = {
+        {
+                .name   = "AT91 NAND partition 1, boot",
+                .offset = 0,
+                .size   = 1 * SZ_256K
+        },
+        {
+                .name   = "AT91 NAND partition 2, kernel",
+                .offset = 1 * SZ_256K,
+                .size   = 2 * SZ_1M - 1 * SZ_256K
+        },
+        {
+                .name   = "AT91 NAND partition 3, filesystem",
+                .offset = 2 * SZ_1M,
+                .size   = 14 * SZ_1M
+        },
+        {
+                .name   = "AT91 NAND partition 4, storage",
+                .offset = 16 * SZ_1M,
+                .size   = 16 * SZ_1M
+        },
+        {
+                .name   = "AT91 NAND partition 5, ext-fs",
+                .offset = 32 * SZ_1M,
+                .size   = 32 * SZ_1M
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(yl_9200_nand_partition);
+        return yl_9200_nand_partition;
+}
+
+static struct at91_nand_data __initdata yl_9200_nand_data = {
+        .ale= 6,
+        .cle= 7,
+        /*.det_pin      = AT91_PIN_PCxx,*/   /*we don't have a det pin because NandFlash is fixed to board*/
+        .rdy_pin        = AT91_PIN_PC14,  /*R/!B Sheet10*/
+        .enable_pin     = AT91_PIN_PC15,  /*!CE  Sheet10 */
+        .partition_info = nand_partitions,
+};
+
+
+
+/*
+TODO S.Birtles
+potentially a problem with the size above
+physmap platform flash device: 00800000 at 10000000
+physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
+NOR chip too large to fit in mapping. Attempting to cope...
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+Reducing visibility of 16384KiB chip to 8192KiB
+*/
+
+static struct mtd_partition yl_9200_flash_partitions[] = {
+        {
+                .name =         "Bootloader",
+                .size =         0x00040000,
+                .offset =       0,
+                .mask_flags =   MTD_WRITEABLE  /* force read-only */
+        },{
+                .name =         "Kernel",
+                .size =         0x001C0000,
+                .offset =       0x00040000,
+        },{
+                .name =         "Filesystem",
+                .size =         MTDPART_SIZ_FULL,
+                .offset =       0x00200000
+        }
+
+};
+
+static struct physmap_flash_data yl_9200_flash_data = {
+        .width  = 2,
+        .parts          = yl_9200_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(yl_9200_flash_partitions),
+};
+
+static struct resource yl_9200_flash_resources[] = {
+{
+        .start          = YL_9200_FLASH_BASE,
+        .end            = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device yl_9200_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &yl_9200_flash_data,
+                        },
+        .resource       = yl_9200_flash_resources,
+        .num_resources  = ARRAY_SIZE(yl_9200_flash_resources),
+};
+
+
+static struct gpio_led yl_9200_leds[] = {
+/*D2 &D3 are passed directly in via at91_init_leds*/
+        {
+                .name                   = "led4",  /*D4*/
+                .gpio                   = AT91_PIN_PB15,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+                /*.default_trigger      = "timer",*/
+        },
+        {
+                .name                   = "led5",  /*D5*/
+                .gpio                   = AT91_PIN_PB8,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+//static struct gpio_sounder yl_9200_sounder[] = {*/
+/*This is a simple speaker attached to a gpo line*/
+
+//      {
+//              .name                   = "Speaker",  /*LS1*/
+//              .gpio                   = AT91_PIN_PA22,
+//              .active_low             = 0,
+//              .default_trigger        = "heartbeat",
+                /*.default_trigger      = "timer",*/
+//      },
+//};
+
+
+
+static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
+        {
+        /*TODO*/
+                I2C_BOARD_INFO("CS4334", 0x00),
+        }
+};
+
+
+ /*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button yl_9200_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PA24,
+                .code   = BTN_2,
+                .desc           = "SW2",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB1,
+                .code   = BTN_3,
+                .desc           = "SW3",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB2,
+                .code   = BTN_4,
+                .desc           = "SW4",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB6,
+                .code   = BTN_5,
+                .desc           = "SW5",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+
+};
+
+static struct gpio_keys_platform_data yl_9200_button_data = {
+        .buttons        = yl_9200_buttons,
+        .nbuttons       = ARRAY_SIZE(yl_9200_buttons),
+};
+
+static struct platform_device yl_9200_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+        .platform_data  = &yl_9200_button_data,
+        }
+};
+
+static void __init yl_9200_add_device_buttons(void)
+{
+        //SW2
+        at91_set_gpio_input(AT91_PIN_PA24, 0);
+        at91_set_deglitch(AT91_PIN_PA24, 1);
+
+        //SW3
+        at91_set_gpio_input(AT91_PIN_PB1, 0);
+        at91_set_deglitch(AT91_PIN_PB1, 1);
+        //SW4
+        at91_set_gpio_input(AT91_PIN_PB2, 0);
+        at91_set_deglitch(AT91_PIN_PB2, 1);
+
+        //SW5
+        at91_set_gpio_input(AT91_PIN_PB6, 0);
+        at91_set_deglitch(AT91_PIN_PB6, 1);
+
+
+        at91_set_gpio_output(AT91_PIN_PB7, 1);  /* #TURN BUTTONS ON, SHEET 5  of schematics */
+        platform_device_register(&yl_9200_button_device);
+}
+#else
+static void __init yl_9200_add_device_buttons(void) {}
+#endif
+
+#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
+#include <video/s1d13xxxfb.h>
+
+/* EPSON S1D13806 FB (discontinued chip)*/
+/* EPSON S1D13506 FB */
+
+#define AT91_FB_REG_BASE        0x80000000L
+#define AT91_FB_REG_SIZE        0x200
+#define AT91_FB_VMEM_BASE       0x80200000L
+#define AT91_FB_VMEM_SIZE       0x200000L
+
+/*#define S1D_DISPLAY_WIDTH           640*/
+/*#define S1D_DISPLAY_HEIGHT          480*/
+
+
+static void __init yl_9200_init_video(void)
+{
+        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
+        at91_sys_write(AT91_PIOC + PIO_BSR,0);
+        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
+
+        at91_sys_write( AT91_SMC_CSR(2),
+        AT91_SMC_NWS_(0x4) |
+        AT91_SMC_WSEN |
+        AT91_SMC_TDF_(0x100) |
+        AT91_SMC_DBW
+        );
+
+
+
+}
+
+
+static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
+{
+        {S1DREG_MISC,                           0x00},   /* Miscellaneous Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
+        {S1DREG_GPIO_CNF0,                      0x00},   /* General IO Pins Configuration Register*/
+        {S1DREG_GPIO_CTL0,                      0x00},   /* General IO Pins Control Register*/
+        {S1DREG_CLK_CNF,                        0x11},   /* Memory Clock Configuration Register*/
+        {S1DREG_LCD_CLK_CNF,            0x10},   /* LCD Pixel Clock Configuration Register*/
+        {S1DREG_CRT_CLK_CNF,            0x12},   /* CRT/TV Pixel Clock Configuration Register*/
+        {S1DREG_MPLUG_CLK_CNF,          0x01},   /* MediaPlug Clock Configuration Register*/
+        {S1DREG_CPU2MEM_WST_SEL,        0x02},   /* CPU To Memory Wait State Select Register*/
+        {S1DREG_MEM_CNF,                        0x00},   /* Memory Configuration Register*/
+        {S1DREG_SDRAM_REF_RATE,         0x04},   /* DRAM Refresh Rate Register, MCLK source*/
+        {S1DREG_SDRAM_TC0,                      0x12},   /* DRAM Timings Control Register 0*/
+        {S1DREG_SDRAM_TC1,                      0x02},   /* DRAM Timings Control Register 1*/
+        {S1DREG_PANEL_TYPE,                     0x25},   /* Panel Type Register*/
+        {S1DREG_MOD_RATE,                       0x00},   /* MOD Rate Register*/
+        {S1DREG_LCD_DISP_HWIDTH,        0x4F},   /* LCD Horizontal Display Width Register*/
+        {S1DREG_LCD_NDISP_HPER,         0x13},   /* LCD Horizontal Non-Display Period Register*/
+        {S1DREG_TFT_FPLINE_START,       0x01},   /* TFT FPLINE Start Position Register*/
+        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},   /* TFT FPLINE Pulse Width Register*/
+        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},   /* LCD Vertical Display Height Register 0*/
+        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},   /* LCD Vertical Display Height Register 1*/
+        {S1DREG_LCD_NDISP_VPER,         0x2c},   /* LCD Vertical Non-Display Period Register*/
+        {S1DREG_TFT_FPFRAME_START,      0x0a},   /* TFT FPFRAME Start Position Register*/
+        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},   /* TFT FPFRAME Pulse Width Register*/
+        {S1DREG_LCD_DISP_MODE,          0x05},   /* LCD Display Mode Register*/
+        {S1DREG_LCD_MISC,                       0x01},   /* LCD Miscellaneous Register*/
+        {S1DREG_LCD_DISP_START0,        0x00},   /* LCD Display Start Address Register 0*/
+        {S1DREG_LCD_DISP_START1,        0x00},   /* LCD Display Start Address Register 1*/
+        {S1DREG_LCD_DISP_START2,        0x00},   /* LCD Display Start Address Register 2*/
+        {S1DREG_LCD_MEM_OFF0,           0x80},   /* LCD Memory Address Offset Register 0*/
+        {S1DREG_LCD_MEM_OFF1,           0x02},   /* LCD Memory Address Offset Register 1*/
+        {S1DREG_LCD_PIX_PAN,            0x03},   /* LCD Pixel Panning Register*/
+        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},   /* LCD Display FIFO High Threshold Control Register*/
+        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},   /* LCD Display FIFO Low Threshold Control Register*/
+        {S1DREG_CRT_DISP_HWIDTH,        0x4F},   /* CRT/TV Horizontal Display Width Register*/
+        {S1DREG_CRT_NDISP_HPER,         0x13},   /* CRT/TV Horizontal Non-Display Period Register*/
+        {S1DREG_CRT_HRTC_START,         0x01},   /* CRT/TV HRTC Start Position Register*/
+        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},   /* CRT/TV HRTC Pulse Width Register*/
+        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},   /* CRT/TV Vertical Display Height Register 0*/
+        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},   /* CRT/TV Vertical Display Height Register 1*/
+        {S1DREG_CRT_NDISP_VPER,         0x2B},   /* CRT/TV Vertical Non-Display Period Register*/
+        {S1DREG_CRT_VRTC_START,         0x09},   /* CRT/TV VRTC Start Position Register*/
+        {S1DREG_CRT_VRTC_PWIDTH,        0x01},   /* CRT/TV VRTC Pulse Width Register*/
+        {S1DREG_TV_OUT_CTL,                     0x18},   /* TV Output Control Register */
+        {S1DREG_CRT_DISP_MODE,          0x05},   /* CRT/TV Display Mode Register, 16BPP*/
+        {S1DREG_CRT_DISP_START0,        0x00},   /* CRT/TV Display Start Address Register 0*/
+        {S1DREG_CRT_DISP_START1,        0x00},   /* CRT/TV Display Start Address Register 1*/
+        {S1DREG_CRT_DISP_START2,        0x00},   /* CRT/TV Display Start Address Register 2*/
+        {S1DREG_CRT_MEM_OFF0,           0x80},   /* CRT/TV Memory Address Offset Register 0*/
+        {S1DREG_CRT_MEM_OFF1,           0x02},   /* CRT/TV Memory Address Offset Register 1*/
+        {S1DREG_CRT_PIX_PAN,            0x00},   /* CRT/TV Pixel Panning Register*/
+        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},   /* CRT/TV Display FIFO High Threshold Control Register*/
+        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},   /* CRT/TV Display FIFO Low Threshold Control Register*/
+        {S1DREG_LCD_CUR_CTL,            0x00},   /* LCD Ink/Cursor Control Register*/
+        {S1DREG_LCD_CUR_START,          0x01},   /* LCD Ink/Cursor Start Address Register*/
+        {S1DREG_LCD_CUR_XPOS0,          0x00},   /* LCD Cursor X Position Register 0*/
+        {S1DREG_LCD_CUR_XPOS1,          0x00},   /* LCD Cursor X Position Register 1*/
+        {S1DREG_LCD_CUR_YPOS0,          0x00},   /* LCD Cursor Y Position Register 0*/
+        {S1DREG_LCD_CUR_YPOS1,          0x00},   /* LCD Cursor Y Position Register 1*/
+        {S1DREG_LCD_CUR_BCTL0,          0x00},   /* LCD Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_LCD_CUR_GCTL0,          0x00},   /* LCD Ink/Cursor Green Color 0 Register*/
+        {S1DREG_LCD_CUR_RCTL0,          0x00},   /* LCD Ink/Cursor Red Color 0 Register*/
+        {S1DREG_LCD_CUR_BCTL1,          0x1F},   /* LCD Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_LCD_CUR_GCTL1,          0x3F},   /* LCD Ink/Cursor Green Color 1 Register*/
+        {S1DREG_LCD_CUR_RCTL1,          0x1F},   /* LCD Ink/Cursor Red Color 1 Register*/
+        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},   /* LCD Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_CRT_CUR_CTL,            0x00},   /* CRT/TV Ink/Cursor Control Register*/
+        {S1DREG_CRT_CUR_START,          0x01},   /* CRT/TV Ink/Cursor Start Address Register*/
+        {S1DREG_CRT_CUR_XPOS0,          0x00},   /* CRT/TV Cursor X Position Register 0*/
+        {S1DREG_CRT_CUR_XPOS1,          0x00},   /* CRT/TV Cursor X Position Register 1*/
+        {S1DREG_CRT_CUR_YPOS0,          0x00},   /* CRT/TV Cursor Y Position Register 0*/
+        {S1DREG_CRT_CUR_YPOS1,          0x00},   /* CRT/TV Cursor Y Position Register 1*/
+        {S1DREG_CRT_CUR_BCTL0,          0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_CRT_CUR_GCTL0,          0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register*/
+        {S1DREG_CRT_CUR_RCTL0,          0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register*/
+        {S1DREG_CRT_CUR_BCTL1,          0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_CRT_CUR_GCTL1,          0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register*/
+        {S1DREG_CRT_CUR_RCTL1,          0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register*/
+        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_BBLT_CTL0,                      0x00},   /* BitBlt Control Register 0*/
+        {S1DREG_BBLT_CTL1,                      0x01},   /* BitBlt Control Register 1*/
+        {S1DREG_BBLT_CC_EXP,            0x00},   /* BitBlt ROP Code/Color Expansion Register*/
+        {S1DREG_BBLT_OP,                        0x00},   /* BitBlt Operation Register*/
+        {S1DREG_BBLT_SRC_START0,        0x00},   /* BitBlt Source Start Address Register 0*/
+        {S1DREG_BBLT_SRC_START1,        0x00},   /* BitBlt Source Start Address Register 1*/
+        {S1DREG_BBLT_SRC_START2,        0x00},   /* BitBlt Source Start Address Register 2*/
+        {S1DREG_BBLT_DST_START0,        0x00},   /* BitBlt Destination Start Address Register 0*/
+        {S1DREG_BBLT_DST_START1,        0x00},   /* BitBlt Destination Start Address Register 1*/
+        {S1DREG_BBLT_DST_START2,        0x00},   /* BitBlt Destination Start Address Register 2*/
+        {S1DREG_BBLT_MEM_OFF0,          0x00},   /* BitBlt Memory Address Offset Register 0*/
+        {S1DREG_BBLT_MEM_OFF1,          0x00},   /* BitBlt Memory Address Offset Register 1*/
+        {S1DREG_BBLT_WIDTH0,            0x00},   /* BitBlt Width Register 0*/
+        {S1DREG_BBLT_WIDTH1,            0x00},   /* BitBlt Width Register 1*/
+        {S1DREG_BBLT_HEIGHT0,           0x00},   /* BitBlt Height Register 0*/
+        {S1DREG_BBLT_HEIGHT1,           0x00},   /* BitBlt Height Register 1*/
+        {S1DREG_BBLT_BGC0,                      0x00},   /* BitBlt Background Color Register 0*/
+        {S1DREG_BBLT_BGC1,                      0x00},   /* BitBlt Background Color Register 1*/
+        {S1DREG_BBLT_FGC0,                      0x00},   /* BitBlt Foreground Color Register 0*/
+        {S1DREG_BBLT_FGC1,                      0x00},   /* BitBlt Foreground Color Register 1*/
+        {S1DREG_LKUP_MODE,                      0x00},   /* Look-Up Table Mode Register*/
+        {S1DREG_LKUP_ADDR,                      0x00},   /* Look-Up Table Address Register*/
+        {S1DREG_PS_CNF,                         0x00},   /* Power Save Configuration Register*/
+        {S1DREG_PS_STATUS,                      0x00},   /* Power Save Status Register*/
+        {S1DREG_CPU2MEM_WDOGT,          0x00},   /* CPU-to-Memory Access Watchdog Timer Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
+};
+
+static u64 s1dfb_dmamask = 0xffffffffUL;
+
+static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = {
+                .initregs                               = yl_9200_s1dfb_initregs,
+                .initregssize                   = ARRAY_SIZE(yl_9200_s1dfb_initregs),
+                .platform_init_video    = yl_9200_init_video,
+};
+
+static struct resource yl_9200_s1dfb_resource[] = {
+        [0] = { /* video mem */
+                .name   = "s1d13xxxfb memory",
+        /*      .name   = "s1d13806 memory",*/
+                .start  = AT91_FB_VMEM_BASE,
+                .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* video registers */
+                .name   = "s1d13xxxfb registers",
+        /*      .name   = "s1d13806 registers",*/
+                .start  = AT91_FB_REG_BASE,
+                .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device yl_9200_s1dfb_device = {
+        /*TODO S.Birtles , really we need the chip revision in here as well*/
+                .name           = "s1d13806fb",
+        /*  .name               = "s1d13506fb",*/
+                .id                     = -1,
+                .dev            = {
+        /*TODO theres a waring here!!*/
+        /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
+                .dma_mask               = &s1dfb_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &yl_9200_s1dfb_pdata,
+        },
+        .resource       = yl_9200_s1dfb_resource,
+        .num_resources  = ARRAY_SIZE(yl_9200_s1dfb_resource),
+};
+
+void __init yl_9200_add_device_video(void)
+{
+        platform_device_register(&yl_9200_s1dfb_device);
+}
+#else
+        void __init yl_9200_add_device_video(void) {}
+#endif
+
+/*this is not called first , yl_9200_map_io is called first*/
+static void __init yl_9200_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* Ethernet */
+        at91_add_device_eth(&yl_9200_eth_data);
+        /* USB Host */
+        at91_add_device_usbh(&yl_9200_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&yl_9200_udc_data);
+        /* pullup_pin it is  actually active low, but this is not needed, driver sets it up */
+        /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
+
+        /* Compact Flash */
+        /*at91_add_device_cf(&yl_9200_cf_data);*/
+
+        /* I2C */
+        at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices));
+        /* SPI */
+        /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/
+        /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the  max 485 NOT SPI*/
+
+        /*touch screen and CAN*/
+        at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
+
+        /*Basically the  TS uses  PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
+        /* we need this incase the board is running without a touch screen*/
+        #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        at91_init_device_ts(); /*init the touch screen device*/
+        #endif
+        /* DataFlash card */
+        at91_add_device_mmc(0, &yl_9200_mmc_data);
+        /* NAND */
+        at91_add_device_nand(&yl_9200_nand_data);
+        /* NOR Flash */
+        platform_device_register(&yl_9200_flash);
+        /* LEDs. Note!! this does not include the led's we passed for the processor status */
+        at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds));
+        /* VGA  */
+        /*this is self registered by including the s1d13xxx chip in the kernel build*/
+        yl_9200_add_device_video();
+        /* Push Buttons */
+        yl_9200_add_device_buttons();
+        /*TODO fixup the Sounder */
+//      yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder));
+
+}
+
+MACHINE_START(YL9200, "uCdragon YL-9200")
+        /* Maintainer: S.Birtles*/
+        .phys_io                = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer                  = &at91rm9200_timer,
+        .map_io                 = yl_9200_map_io,
+        .init_irq               = yl_9200_init_irq,
+        .init_machine   = yl_9200_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index de6424e9ac02..a33dfe450726 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -23,7 +23,6 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 
-#include <asm/semaphore.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index a67defd50438..39733b6992aa 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -26,12 +26,135 @@
 #include <asm/mach-types.h>
 
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91rm9200_mc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/cpu.h>
 
 #include "generic.h"
 
+#ifdef CONFIG_ARCH_AT91RM9200
+#include <asm/arch/at91rm9200_mc.h>
+
+/*
+ * The AT91RM9200 goes into self-refresh mode with this command, and will
+ * terminate self-refresh automatically on the next SDRAM access.
+ */
+#define sdram_selfrefresh_enable()      at91_sys_write(AT91_SDRAMC_SRR, 1)
+#define sdram_selfrefresh_disable()     do {} while (0)
+
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <asm/arch/at91cap9_ddrsdr.h>
+
+static u32 saved_lpr;
+
+static inline void sdram_selfrefresh_enable(void)
+{
+        u32 lpr;
+
+        saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+
+        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
+        at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+}
+
+#define sdram_selfrefresh_disable()     at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+
+#else
+#include <asm/arch/at91sam9_sdramc.h>
+
+static u32 saved_lpr;
+
+static inline void sdram_selfrefresh_enable(void)
+{
+        u32 lpr;
+
+        saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+
+        lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
+        at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+}
+
+#define sdram_selfrefresh_disable()     at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+
+/*
+ * FIXME: The AT91SAM9263 has a second EBI controller which may have
+ *        additional SDRAM.  pm_slowclock.S will require a similar fix.
+ */
+
+#endif
+
+
+/*
+ * Show the reason for the previous system reset.
+ */
+#if defined(AT91_SHDWC)
+
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
+
+static void __init show_reset_status(void)
+{
+        static char reset[] __initdata = "reset";
+
+        static char general[] __initdata = "general";
+        static char wakeup[] __initdata = "wakeup";
+        static char watchdog[] __initdata = "watchdog";
+        static char software[] __initdata = "software";
+        static char user[] __initdata = "user";
+        static char unknown[] __initdata = "unknown";
+
+        static char signal[] __initdata = "signal";
+        static char rtc[] __initdata = "rtc";
+        static char rtt[] __initdata = "rtt";
+        static char restore[] __initdata = "power-restored";
+
+        char *reason, *r2 = reset;
+        u32 reset_type, wake_type;
+
+        reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
+        wake_type = at91_sys_read(AT91_SHDW_SR);
+
+        switch (reset_type) {
+        case AT91_RSTC_RSTTYP_GENERAL:
+                reason = general;
+                break;
+        case AT91_RSTC_RSTTYP_WAKEUP:
+                /* board-specific code enabled the wakeup sources */
+                reason = wakeup;
+
+                /* "wakeup signal" */
+                if (wake_type & AT91_SHDW_WAKEUP0)
+                        r2 = signal;
+                else {
+                        r2 = reason;
+                        if (wake_type & AT91_SHDW_RTTWK)        /* rtt wakeup */
+                                reason = rtt;
+                        else if (wake_type & AT91_SHDW_RTCWK)   /* rtc wakeup */
+                                reason = rtc;
+                        else if (wake_type == 0)        /* power-restored wakeup */
+                                reason = restore;
+                        else                            /* unknown wakeup */
+                                reason = unknown;
+                }
+                break;
+        case AT91_RSTC_RSTTYP_WATCHDOG:
+                reason = watchdog;
+                break;
+        case AT91_RSTC_RSTTYP_SOFTWARE:
+                reason = software;
+                break;
+        case AT91_RSTC_RSTTYP_USER:
+                reason = user;
+                break;
+        default:
+                reason = unknown;
+                break;
+        }
+        pr_info("AT91: Starting after %s %s\n", reason, r2);
+}
+#else
+static void __init show_reset_status(void) {}
+#endif
+
 
 static int at91_pm_valid_state(suspend_state_t state)
 {
@@ -125,6 +248,11 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
 
 static void (*slow_clock)(void);
 
+#ifdef CONFIG_AT91_SLOW_CLOCK
+extern void at91_slow_clock(void);
+extern u32 at91_slow_clock_sz;
+#endif
+
 
 static int at91_pm_enter(suspend_state_t state)
 {
@@ -158,11 +286,14 @@ static int at91_pm_enter(suspend_state_t state)
                          * turning off the main oscillator; reverse on wakeup.
                          */
                         if (slow_clock) {
+#ifdef CONFIG_AT91_SLOW_CLOCK
+                                /* copy slow_clock handler to SRAM, and call it */
+                                memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
+#endif
                                 slow_clock();
                                 break;
                         } else {
-                                /* DEVELOPMENT ONLY */
-                                pr_info("AT91: PM - no slow clock mode yet ...\n");
+                                pr_info("AT91: PM - no slow clock mode enabled ...\n");
                                 /* FALLTHROUGH leaving master clock alone */
                         }
 
@@ -175,13 +306,15 @@ static int at91_pm_enter(suspend_state_t state)
                 case PM_SUSPEND_STANDBY:
                         /*
                          * NOTE: the Wait-for-Interrupt instruction needs to be
-                         * in icache so the SDRAM stays in self-refresh mode until
-                         * the wakeup IRQ occurs.
+                         * in icache so no SDRAM accesses are needed until the
+                         * wakeup IRQ occurs and self-refresh is terminated.
                          */
                         asm("b 1f; .align 5; 1:");
                         asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
-                        at91_sys_write(AT91_SDRAMC_SRR, 1);     /* self-refresh mode */
-                        /* fall though to next state */
+                        sdram_selfrefresh_enable();
+                        asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
+                        sdram_selfrefresh_disable();
+                        break;
 
                 case PM_SUSPEND_ON:
                         asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
@@ -196,6 +329,7 @@ static int at91_pm_enter(suspend_state_t state)
                         at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
 
 error:
+        sdram_selfrefresh_disable();
         target_state = PM_SUSPEND_ON;
         at91_irq_resume();
         at91_gpio_resume();
@@ -220,21 +354,20 @@ static struct platform_suspend_ops at91_pm_ops ={
 
 static int __init at91_pm_init(void)
 {
-        printk("AT91: Power Management\n");
-
-#ifdef CONFIG_AT91_PM_SLOW_CLOCK
-        /* REVISIT allocations of SRAM should be dynamically managed.
-         * FIQ handlers and other components will want SRAM/TCM too...
-         */
-        slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
-        memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
+#ifdef CONFIG_AT91_SLOW_CLOCK
+        slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
 #endif
 
-        /* Disable SDRAM low-power mode.  Cannot be used with self-refresh. */
+        pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
+
+#ifdef CONFIG_ARCH_AT91RM9200
+        /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
         at91_sys_write(AT91_SDRAMC_LPR, 0);
+#endif
 
         suspend_set_ops(&at91_pm_ops);
 
+        show_reset_status();
         return 0;
 }
 arch_initcall(at91_pm_init);
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 0e2b641268ad..dbaae5f746a1 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -31,6 +31,8 @@ config ARCH_EDB7211
         bool "EDB7211"
         select ISA
         select ARCH_DISCONTIGMEM_ENABLE
+        select ARCH_SPARSEMEM_ENABLE
+        select ARCH_SELECT_MEMORY_MODEL
         help
           Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
           evaluation board.
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 0ecf99761feb..c1252ca9648e 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for the linux kernel.
 #
-obj-y                   := core.o clock.o
+obj-y                   := core.o clock.o gpio.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 91f6a07a51d5..8bc187240542 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -159,7 +159,7 @@ static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
 static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
 static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x5c };
 
-static void update_gpio_int_params(unsigned port)
+void ep93xx_gpio_update_int_params(unsigned port)
 {
         BUG_ON(port > 2);
 
@@ -175,98 +175,10 @@ static void update_gpio_int_params(unsigned port)
                 EP93XX_GPIO_REG(int_en_register_offset[port]));
 }
 
-/* Port ordering is: A B F D E C G H */
-static const u8 data_register_offset[8] = {
-        0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
-};
-
-static const u8 data_direction_register_offset[8] = {
-        0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
-};
-
-#define GPIO_IN         0
-#define GPIO_OUT        1
-
-static void ep93xx_gpio_set_direction(unsigned line, int direction)
-{
-        unsigned int data_direction_register;
-        unsigned long flags;
-        unsigned char v;
-
-        data_direction_register =
-                EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
-
-        local_irq_save(flags);
-        if (direction == GPIO_OUT) {
-                if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
-                        /* Port A/B/F */
-                        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
-                        update_gpio_int_params(line >> 3);
-                }
-
-                v = __raw_readb(data_direction_register);
-                v |= 1 << (line & 7);
-                __raw_writeb(v, data_direction_register);
-        } else if (direction == GPIO_IN) {
-                v = __raw_readb(data_direction_register);
-                v &= ~(1 << (line & 7));
-                __raw_writeb(v, data_direction_register);
-        }
-        local_irq_restore(flags);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-        if (gpio > EP93XX_GPIO_LINE_MAX)
-                return -EINVAL;
-
-        ep93xx_gpio_set_direction(gpio, GPIO_IN);
-
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-        if (gpio > EP93XX_GPIO_LINE_MAX)
-                return -EINVAL;
-
-        gpio_set_value(gpio, value);
-        ep93xx_gpio_set_direction(gpio, GPIO_OUT);
-
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-int gpio_get_value(unsigned gpio)
-{
-        unsigned int data_register;
-
-        data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
-
-        return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
-}
-EXPORT_SYMBOL(gpio_get_value);
-
-void gpio_set_value(unsigned gpio, int value)
+void ep93xx_gpio_int_mask(unsigned line)
 {
-        unsigned int data_register;
-        unsigned long flags;
-        unsigned char v;
-
-        data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
-
-        local_irq_save(flags);
-        v = __raw_readb(data_register);
-        if (value)
-                v |= 1 << (gpio & 7);
-        else
-                v &= ~(1 << (gpio & 7));
-        __raw_writeb(v, data_register);
-        local_irq_restore(flags);
+        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
 }
-EXPORT_SYMBOL(gpio_set_value);
-
 
 /*************************************************************************
  * EP93xx IRQ handling
@@ -316,7 +228,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq)
 
         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-                update_gpio_int_params(port);
+                ep93xx_gpio_update_int_params(port);
         }
 
         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
@@ -332,7 +244,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 
         gpio_int_unmasked[port] &= ~port_mask;
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 
         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 }
@@ -343,7 +255,7 @@ static void ep93xx_gpio_irq_mask(unsigned int irq)
         int port = line >> 3;
 
         gpio_int_unmasked[port] &= ~(1 << (line & 7));
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 }
 
 static void ep93xx_gpio_irq_unmask(unsigned int irq)
@@ -352,7 +264,7 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq)
         int port = line >> 3;
 
         gpio_int_unmasked[port] |= 1 << (line & 7);
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 }
 
 
@@ -368,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
         const int port = gpio >> 3;
         const int port_mask = 1 << (gpio & 7);
 
-        ep93xx_gpio_set_direction(gpio, GPIO_IN);
+        gpio_direction_output(gpio, gpio_get_value(gpio));
 
         switch (type) {
         case IRQT_RISING:
@@ -411,7 +323,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
         desc->status &= ~IRQ_TYPE_SENSE_MASK;
         desc->status |= type & IRQ_TYPE_SENSE_MASK;
 
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 
         return 0;
 }
@@ -549,6 +461,7 @@ static struct platform_device ep93xx_ohci_device = {
         .resource       = ep93xx_ohci_resources,
 };
 
+extern void ep93xx_gpio_init(void);
 
 void __init ep93xx_init_devices(void)
 {
@@ -562,6 +475,8 @@ void __init ep93xx_init_devices(void)
         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
         __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
 
+        ep93xx_gpio_init();
+
         amba_device_register(&uart1_device, &iomem_resource);
         amba_device_register(&uart2_device, &iomem_resource);
         amba_device_register(&uart3_device, &iomem_resource);
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
new file mode 100644
index 000000000000..dc2e4c00d989
--- /dev/null
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -0,0 +1,158 @@
+/*
+ * linux/arch/arm/mach-ep93xx/gpio.c
+ *
+ * Generic EP93xx GPIO handling
+ *
+ * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * Based on code originally from:
+ *  linux/arch/arm/mach-ep93xx/core.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+
+#include <asm/arch/ep93xx-regs.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+struct ep93xx_gpio_chip {
+        struct gpio_chip        chip;
+
+        unsigned int            data_reg;
+        unsigned int            data_dir_reg;
+};
+
+#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
+
+/* From core.c */
+extern void ep93xx_gpio_int_mask(unsigned line);
+extern void ep93xx_gpio_update_int_params(unsigned port);
+
+static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        unsigned long flags;
+        u8 v;
+
+        local_irq_save(flags);
+        v = __raw_readb(ep93xx_chip->data_dir_reg);
+        v &= ~(1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_dir_reg);
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int val)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        unsigned long flags;
+        int line;
+        u8 v;
+
+        local_irq_save(flags);
+
+        /* Set the value */
+        v = __raw_readb(ep93xx_chip->data_reg);
+        if (val)
+                v |= (1 << offset);
+        else
+                v &= ~(1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_reg);
+
+        /* Drive as an output */
+        line = chip->base + offset;
+        if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
+                /* Ports A/B/F */
+                ep93xx_gpio_int_mask(line);
+                ep93xx_gpio_update_int_params(line >> 3);
+        }
+
+        v = __raw_readb(ep93xx_chip->data_dir_reg);
+        v |= (1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_dir_reg);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+
+        return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
+}
+
+static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        unsigned long flags;
+        u8 v;
+
+        local_irq_save(flags);
+        v = __raw_readb(ep93xx_chip->data_reg);
+        if (val)
+                v |= (1 << offset);
+        else
+                v &= ~(1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_reg);
+        local_irq_restore(flags);
+}
+
+static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        u8 data_reg, data_dir_reg;
+        int i;
+
+        data_reg = __raw_readb(ep93xx_chip->data_reg);
+        data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
+
+        for (i = 0; i < chip->ngpio; i++)
+                seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i,
+                           (data_reg & (1 << i)) ? "set" : "clear",
+                           (data_dir_reg & (1 << i)) ? "out" : "in");
+}
+
+#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio)                      \
+        {                                                               \
+                .chip = {                                               \
+                        .label            = name,                       \
+                        .direction_input  = ep93xx_gpio_direction_input, \
+                        .direction_output = ep93xx_gpio_direction_output, \
+                        .get              = ep93xx_gpio_get,            \
+                        .set              = ep93xx_gpio_set,            \
+                        .dbg_show         = ep93xx_gpio_dbg_show,       \
+                        .base             = base_gpio,                  \
+                        .ngpio            = 8,                          \
+                },                                                      \
+                .data_reg       = EP93XX_GPIO_REG(dr),                  \
+                .data_dir_reg   = EP93XX_GPIO_REG(ddr),                 \
+        }
+
+static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
+        EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
+        EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
+        EP93XX_GPIO_BANK("C", 0x30, 0x34, 40),
+        EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
+        EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
+        EP93XX_GPIO_BANK("F", 0x08, 0x18, 16),
+        EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
+        EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
+};
+
+void __init ep93xx_gpio_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
+                gpiochip_add(&ep93xx_gpio_banks[i].chip);
+}
diff --git a/arch/arm/mach-integrator/clock.c b/arch/arm/mach-integrator/clock.c
index 95a1e263f7fa..8d761fdd2ecd 100644
--- a/arch/arm/mach-integrator/clock.c
+++ b/arch/arm/mach-integrator/clock.c
@@ -17,7 +17,6 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 
-#include <asm/semaphore.h>
 #include <asm/hardware/icst525.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-integrator/time.c b/arch/arm/mach-integrator/time.c
index 5278f589fcee..5235f64f235b 100644
--- a/arch/arm/mach-integrator/time.c
+++ b/arch/arm/mach-integrator/time.c
@@ -125,7 +125,7 @@ static int rtc_probe(struct amba_device *dev, void *id)
         xtime.tv_sec = __raw_readl(rtc_base + RTC_DR);
 
         ret = request_irq(dev->irq[0], arm_rtc_interrupt, IRQF_DISABLED,
-                          "rtc-pl030", dev);
+                          "rtc-pl030", NULL);
         if (ret)
                 goto map_out;
 
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index dbe07c9472ed..5e8c6f7dfabb 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -34,14 +34,6 @@ config MACH_N2100
           Say Y here if you want to run your kernel on the Thecus n2100
           NAS appliance.
 
-config IOP3XX_ATU
-        bool "Enable the PCI Controller"
-        default y
-        help
-          Say Y here if you want the IOP to initialize its PCI Controller.
-          Say N if the IOP is an add in card, the host system owns the PCI
-          bus in this case.
-
 config MACH_EM7210
         bool "Enable support for the Lanner EM7210"
         help
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 98cfa1cd6bdb..4a89823bcebb 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = {
 
 static int __init iq31244_pci_init(void)
 {
-        if (is_ep80219()) {
-                if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
-                        pci_common_init(&ep80219_pci);
-        } else if (machine_is_iq31244()) {
+        if (is_ep80219())
+                pci_common_init(&ep80219_pci);
+        else if (machine_is_iq31244()) {
                 if (is_80219()) {
                         printk("note: iq31244 board type has been selected\n");
                         printk("note: to select ep80219 operation:\n");
@@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void)
                         printk("\t2/ update boot loader to pass"
                                 " the ep80219 id: %d\n", MACH_TYPE_EP80219);
                 }
-
-                if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
-                        pci_common_init(&iq31244_pci);
+                pci_common_init(&iq31244_pci);
         }
 
         return 0;
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 18ad29f213b2..1da3c911edd3 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = {
         .swizzle        = pci_std_swizzle,
         .nr_controllers = 1,
         .setup          = iop3xx_pci_setup,
-        .preinit        = iop3xx_pci_preinit,
+        .preinit        = iop3xx_pci_preinit_cond,
         .scan           = iop3xx_pci_scan_bus,
         .map_irq        = iq80321_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
index 45598e096898..9aa016bb18f9 100644
--- a/arch/arm/mach-iop33x/Kconfig
+++ b/arch/arm/mach-iop33x/Kconfig
@@ -16,14 +16,6 @@ config MACH_IQ80332
           Say Y here if you want to run your kernel on the Intel IQ80332
           evaluation kit for the IOP332 chipset.
 
-config IOP3XX_ATU
-        bool "Enable the PCI Controller"
-        default y
-        help
-          Say Y here if you want the IOP to initialize its PCI Controller.
-          Say N if the IOP is an add in card, the host system owns the PCI
-          bus in this case.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 433188ebff2a..de39fd778579 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = {
         .swizzle        = pci_std_swizzle,
         .nr_controllers = 1,
         .setup          = iop3xx_pci_setup,
-        .preinit        = iop3xx_pci_preinit,
+        .preinit        = iop3xx_pci_preinit_cond,
         .scan           = iop3xx_pci_scan_bus,
         .map_irq        = iq80331_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 416c09564cc6..4904fd78445f 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = {
         .swizzle        = pci_std_swizzle,
         .nr_controllers = 1,
         .setup          = iop3xx_pci_setup,
-        .preinit        = iop3xx_pci_preinit,
+        .preinit        = iop3xx_pci_preinit_cond,
         .scan           = iop3xx_pci_scan_bus,
         .map_irq        = iq80332_pci_map_irq,
 };
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
index 730a3af12c98..ade42b73afbb 100644
--- a/arch/arm/mach-ks8695/Makefile
+++ b/arch/arm/mach-ks8695/Makefile
@@ -11,5 +11,8 @@ obj-				:=
 # PCI support is optional
 obj-$(CONFIG_PCI)               += pci.o
 
+# LEDs
+obj-$(CONFIG_LEDS)              += leds.o
+
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)       += board-micrel.o
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 386593f8ac65..3db2ec61d06f 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -176,6 +176,27 @@ static void __init ks8695_add_device_watchdog(void) {}
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  LEDs
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_LEDS)
+short ks8695_leds_cpu = -1;
+short ks8695_leds_timer = -1;
+
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
+{
+        /* Enable GPIO to access the LEDs */
+        gpio_direction_output(cpu_led, 1);
+        gpio_direction_output(timer_led, 1);
+
+        ks8695_leds_cpu   = cpu_led;
+        ks8695_leds_timer = timer_led;
+}
+#else
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
+#endif
+
 /* -------------------------------------------------------------------- */
 
 /*
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
new file mode 100644
index 000000000000..d61762ae50d8
--- /dev/null
+++ b/arch/arm/mach-ks8695/leds.c
@@ -0,0 +1,94 @@
+/*
+ * LED driver for KS8695-based boards.
+ *
+ * Copyright (C) Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/leds.h>
+#include <asm/arch/devices.h>
+#include <asm/arch/gpio.h>
+
+
+static inline void ks8695_led_on(unsigned int led)
+{
+        gpio_set_value(led, 0);
+}
+
+static inline void ks8695_led_off(unsigned int led)
+{
+        gpio_set_value(led, 1);
+}
+
+static inline void ks8695_led_toggle(unsigned int led)
+{
+        unsigned long is_off = gpio_get_value(led);
+        if (is_off)
+                ks8695_led_on(led);
+        else
+                ks8695_led_off(led);
+}
+
+
+/*
+ * Handle LED events.
+ */
+static void ks8695_leds_event(led_event_t evt)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        switch(evt) {
+        case led_start:         /* System startup */
+                ks8695_led_on(ks8695_leds_cpu);
+                break;
+
+        case led_stop:          /* System stop / suspend */
+                ks8695_led_off(ks8695_leds_cpu);
+                break;
+
+#ifdef CONFIG_LEDS_TIMER
+        case led_timer:         /* Every 50 timer ticks */
+                ks8695_led_toggle(ks8695_leds_timer);
+                break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+        case led_idle_start:    /* Entering idle state */
+                ks8695_led_off(ks8695_leds_cpu);
+                break;
+
+        case led_idle_end:      /* Exit idle state */
+                ks8695_led_on(ks8695_leds_cpu);
+                break;
+#endif
+
+        default:
+                break;
+        }
+
+        local_irq_restore(flags);
+}
+
+
+static int __init leds_init(void)
+{
+        if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
+                return -ENODEV;
+
+        leds_event = ks8695_leds_event;
+
+        leds_event(led_start);
+        return 0;
+}
+
+__initcall(leds_init);
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig
index 8584ed107991..dd0cd5ac4b8b 100644
--- a/arch/arm/mach-ns9xxx/Kconfig
+++ b/arch/arm/mach-ns9xxx/Kconfig
@@ -2,9 +2,26 @@ if ARCH_NS9XXX
 
 menu "NS9xxx Implementations"
 
+config NS9XXX_HAVE_SERIAL8250
+        bool
+
+config PROCESSOR_NS9360
+        bool
+
+config MODULE_CC9P9360
+        bool
+        select PROCESSOR_NS9360
+
+config BOARD_A9M9750DEV
+        select NS9XXX_HAVE_SERIAL8250
+        bool
+
+config BOARD_JSCC9P9360
+        bool
+
 config MACH_CC9P9360DEV
         bool "ConnectCore 9P 9360 on an A9M9750 Devboard"
-        select PROCESSOR_NS9360
+        select MODULE_CC9P9360
         select BOARD_A9M9750DEV
         help
           Say Y here if you are using the Digi ConnectCore 9P 9360
@@ -12,21 +29,12 @@ config MACH_CC9P9360DEV
 
 config MACH_CC9P9360JS
         bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard"
-        select PROCESSOR_NS9360
+        select MODULE_CC9P9360
         select BOARD_JSCC9P9360
         help
           Say Y here if you are using the Digi ConnectCore 9P 9360
           on an JSCC9P9360 Development Board.
 
-config PROCESSOR_NS9360
-        bool
-
-config BOARD_A9M9750DEV
-        bool
-
-config BOARD_JSCC9P9360
-        bool
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile
index 6fb82b855a55..41efaf9ad50b 100644
--- a/arch/arm/mach-ns9xxx/Makefile
+++ b/arch/arm/mach-ns9xxx/Makefile
@@ -1,7 +1,12 @@
-obj-y := irq.o time.o generic.o gpio.o
+obj-y := clock.o generic.o gpio.o irq.o
 
 obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
 obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
 
+obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o
+
 obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
 obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
+
+# platform devices
+obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o
diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot
index 75ed64e90fa4..54654919229b 100644
--- a/arch/arm/mach-ns9xxx/Makefile.boot
+++ b/arch/arm/mach-ns9xxx/Makefile.boot
@@ -1,2 +1,2 @@
-zreladdr-y := 0x108000
+zreladdr-y := 0x8000
 params_phys-y := 0x100
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 0f65177f9e5f..a494b71c0195 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -8,15 +8,14 @@
  * under the terms of the GNU General Public License version 2 as published by
  * the Free Software Foundation.
  */
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
 #include <linux/irq.h>
 
 #include <asm/mach/map.h>
 #include <asm/gpio.h>
 
 #include <asm/arch-ns9xxx/board.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
 #include <asm/arch-ns9xxx/regs-mem.h>
 #include <asm/arch-ns9xxx/regs-bbu.h>
 #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
@@ -105,9 +104,9 @@ void __init board_a9m9750dev_init_irq(void)
         int i;
 
         if (gpio_request(11, "board a9m9750dev extirq2") == 0)
-                ns9xxx_gpio_configure(11, 0, 1);
+                ns9360_gpio_configure(11, 0, 1);
         else
-                printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n",
+                printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
                                 __func__);
 
         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
@@ -116,69 +115,16 @@ void __init board_a9m9750dev_init_irq(void)
                 set_irq_flags(i, IRQF_VALID);
         }
 
-        /* IRQ_EXT2: level sensitive + active low */
+        /* IRQ_NS9XXX_EXT2: level sensitive + active low */
         eic = __raw_readl(SYS_EIC(2));
         REGSET(eic, SYS_EIC, PLTY, AL);
         REGSET(eic, SYS_EIC, LVEDG, LEVEL);
         __raw_writel(eic, SYS_EIC(2));
 
-        set_irq_chained_handler(IRQ_EXT2,
+        set_irq_chained_handler(IRQ_NS9XXX_EXT2,
                         a9m9750dev_fpga_demux_handler);
 }
 
-static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
-        {
-                .iobase         = FPGA_UARTA_BASE,
-                .membase        = (unsigned char*)FPGA_UARTA_BASE,
-                .mapbase        = FPGA_UARTA_BASE,
-                .irq            = IRQ_FPGA_UARTA,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                .iobase         = FPGA_UARTB_BASE,
-                .membase        = (unsigned char*)FPGA_UARTB_BASE,
-                .mapbase        = FPGA_UARTB_BASE,
-                .irq            = IRQ_FPGA_UARTB,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                .iobase         = FPGA_UARTC_BASE,
-                .membase        = (unsigned char*)FPGA_UARTC_BASE,
-                .mapbase        = FPGA_UARTC_BASE,
-                .irq            = IRQ_FPGA_UARTC,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                .iobase         = FPGA_UARTD_BASE,
-                .membase        = (unsigned char*)FPGA_UARTD_BASE,
-                .mapbase        = FPGA_UARTD_BASE,
-                .irq            = IRQ_FPGA_UARTD,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                /* end marker */
-        },
-};
-
-static struct platform_device board_a9m9750dev_serial_device = {
-        .name = "serial8250",
-        .dev = {
-                .platform_data = board_a9m9750dev_serial8250_port,
-        },
-};
-
-static struct platform_device *board_a9m9750dev_devices[] __initdata = {
-        &board_a9m9750dev_serial_device,
-};
-
 void __init board_a9m9750dev_init_machine(void)
 {
         u32 reg;
@@ -210,7 +156,4 @@ void __init board_a9m9750dev_init_machine(void)
         __raw_writel(0x2, MEM_SMOED(0));
         __raw_writel(0x6, MEM_SMRD(0));
         __raw_writel(0x6, MEM_SMWD(0));
-
-        platform_add_devices(board_a9m9750dev_devices,
-                        ARRAY_SIZE(board_a9m9750dev_devices));
 }
diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c
new file mode 100644
index 000000000000..f8639161068f
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/clock.c
@@ -0,0 +1,215 @@
+/*
+ * arch/arm/mach-ns9xxx/clock.c
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <asm/semaphore.h>
+#include "clock.h"
+
+static LIST_HEAD(clocks);
+static DEFINE_SPINLOCK(clk_lock);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        struct clk *p, *ret = NULL, *retgen = NULL;
+        unsigned long flags;
+        int idno;
+
+        if (dev == NULL || dev->bus != &platform_bus_type)
+                idno = -1;
+        else
+                idno = to_platform_device(dev)->id;
+
+        spin_lock_irqsave(&clk_lock, flags);
+        list_for_each_entry(p, &clocks, node) {
+                if (strcmp(id, p->name) == 0) {
+                        if (p->id == idno) {
+                                if (!try_module_get(p->owner))
+                                        continue;
+                                ret = p;
+                                break;
+                        } else if (p->id == -1)
+                                /* remember match with id == -1 in case there is
+                                 * no clock for idno */
+                                retgen = p;
+                }
+        }
+
+        if (!ret && retgen && try_module_get(retgen->owner))
+                ret = retgen;
+
+        if (ret)
+                ++ret->refcount;
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return ret ? ret : ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+        module_put(clk->owner);
+        --clk->refcount;
+}
+EXPORT_SYMBOL(clk_put);
+
+static int clk_enable_unlocked(struct clk *clk)
+{
+        int ret = 0;
+        if (clk->parent) {
+                ret = clk_enable_unlocked(clk->parent);
+                if (ret)
+                        return ret;
+        }
+
+        if (clk->usage++ == 0 && clk->endisable)
+                ret = clk->endisable(clk, 1);
+
+        return ret;
+}
+
+int clk_enable(struct clk *clk)
+{
+        int ret;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        ret = clk_enable_unlocked(clk);
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+static void clk_disable_unlocked(struct clk *clk)
+{
+        if (--clk->usage == 0 && clk->endisable)
+                clk->endisable(clk, 0);
+
+        if (clk->parent)
+                clk_disable_unlocked(clk->parent);
+}
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        clk_disable_unlocked(clk);
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        if (clk->rate)
+                return clk->rate;
+
+        if (clk->parent)
+                return clk_get_rate(clk->parent);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_register(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        list_add(&clk->node, &clocks);
+
+        if (clk->parent)
+                ++clk->parent->refcount;
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+
+int clk_unregister(struct clk *clk)
+{
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        if (clk->usage || clk->refcount)
+                ret = -EBUSY;
+        else
+                list_del(&clk->node);
+
+        if (clk->parent)
+                --clk->parent->refcount;
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return ret;
+}
+
+#if defined CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static int clk_debugfs_show(struct seq_file *s, void *null)
+{
+        unsigned long flags;
+        struct clk *p;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        list_for_each_entry(p, &clocks, node)
+                seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n",
+                                p->name, p->id, p->usage, p->refcount,
+                                p->usage ? clk_get_rate(p) : 0);
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+
+static int clk_debugfs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, clk_debugfs_show, NULL);
+}
+
+static struct file_operations clk_debugfs_operations = {
+        .open = clk_debugfs_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static int __init clk_debugfs_init(void)
+{
+        struct dentry *dentry;
+
+        dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL,
+                        &clk_debugfs_operations);
+        return IS_ERR(dentry) ? PTR_ERR(dentry) : 0;
+}
+subsys_initcall(clk_debugfs_init);
+
+#endif /* if defined CONFIG_DEBUG_FS */
diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h
new file mode 100644
index 000000000000..b86c30dd79eb
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/clock.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-ns9xxx/clock.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __NS9XXX_CLOCK_H
+#define __NS9XXX_CLOCK_H
+
+#include <linux/list.h>
+
+struct clk {
+        struct module *owner;
+        const char *name;
+        int id;
+
+        struct clk *parent;
+
+        unsigned long rate;
+        int (*endisable)(struct clk *, int enable);
+        unsigned long (*get_rate)(struct clk *);
+
+        struct list_head node;
+        unsigned long refcount;
+        unsigned long usage;
+};
+
+int clk_register(struct clk *clk);
+int clk_unregister(struct clk *clk);
+
+#endif /* ifndef __NS9XXX_CLOCK_H */
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c
index d742c921e34d..1e0f467879cc 100644
--- a/arch/arm/mach-ns9xxx/generic.c
+++ b/arch/arm/mach-ns9xxx/generic.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/generic.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,34 +11,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <asm/memory.h>
-#include <asm/page.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/arch-ns9xxx/regs-mem.h>
-#include <asm/arch-ns9xxx/board.h>
 
 #include "generic.h"
 
-static struct map_desc standard_io_desc[] __initdata = {
-        { /* BBus */
-                .virtual = io_p2v(0x90000000),
-                .pfn = __phys_to_pfn(0x90000000),
-                .length = 0x00700000,
-                .type = MT_DEVICE,
-        }, { /* AHB */
-                .virtual = io_p2v(0xa0100000),
-                .pfn = __phys_to_pfn(0xa0100000),
-                .length = 0x00900000,
-                .type = MT_DEVICE,
-        },
-};
-
-void __init ns9xxx_map_io(void)
-{
-        iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
-}
-
 void __init ns9xxx_init_machine(void)
 {
 }
diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h
index 687e291773f4..82493191aad6 100644
--- a/arch/arm/mach-ns9xxx/generic.h
+++ b/arch/arm/mach-ns9xxx/generic.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/generic.h
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -13,7 +13,4 @@
 #include <linux/init.h>
 
 void __init ns9xxx_init_irq(void);
-void __init ns9xxx_map_io(void);
 void __init ns9xxx_init_machine(void);
-
-extern struct sys_timer ns9xxx_timer;
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c
new file mode 100644
index 000000000000..cabfb879dda9
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/gpio-ns9360.c
@@ -0,0 +1,118 @@
+/*
+ * arch/arm/mach-ns9xxx/gpio-ns9360.c
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/bug.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/arch-ns9xxx/regs-bbu.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
+#include "gpio-ns9360.h"
+
+static inline int ns9360_valid_gpio(unsigned gpio)
+{
+        return gpio <= 72;
+}
+
+static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio)
+{
+        if (gpio < 56)
+                return BBU_GCONFb1(gpio / 8);
+        else
+                /*
+                 * this could be optimised away on
+                 * ns9750 only builds, but it isn't ...
+                 */
+                return BBU_GCONFb2((gpio - 56) / 8);
+}
+
+static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio)
+{
+        if (gpio < 32)
+                return BBU_GCTRL1;
+        else if (gpio < 64)
+                return BBU_GCTRL2;
+        else
+                /* this could be optimised away on ns9750 only builds */
+                return BBU_GCTRL3;
+}
+
+static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio)
+{
+        if (gpio < 32)
+                return BBU_GSTAT1;
+        else if (gpio < 64)
+                return BBU_GSTAT2;
+        else
+                /* this could be optimised away on ns9750 only builds */
+                return BBU_GSTAT3;
+}
+
+/*
+ * each gpio can serve for 4 different purposes [0..3].  These are called
+ * "functions" and passed in the parameter func.  Functions 0-2 are always some
+ * special things, function 3 is GPIO.  If func == 3 dir specifies input or
+ * output, and with inv you can enable an inverter (independent of func).
+ */
+int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func)
+{
+        void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio);
+        u32 confval;
+
+        confval = __raw_readl(conf);
+        REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
+        REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
+        REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
+        __raw_writel(confval, conf);
+
+        return 0;
+}
+
+int ns9360_gpio_configure(unsigned gpio, int inv, int func)
+{
+        if (likely(ns9360_valid_gpio(gpio))) {
+                if (func == 3) {
+                        printk(KERN_WARNING "use gpio_direction_input "
+                                        "or gpio_direction_output\n");
+                        return -EINVAL;
+                } else
+                        return __ns9360_gpio_configure(gpio, 0, inv, func);
+        } else
+                return -EINVAL;
+}
+EXPORT_SYMBOL(ns9360_gpio_configure);
+
+int ns9360_gpio_get_value(unsigned gpio)
+{
+        void __iomem *stat = ns9360_gpio_get_gstataddr(gpio);
+        int ret;
+
+        ret = 1 & (__raw_readl(stat) >> (gpio & 31));
+
+        return ret;
+}
+
+void ns9360_gpio_set_value(unsigned gpio, int value)
+{
+        void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio);
+        u32 ctrlval;
+
+        ctrlval = __raw_readl(ctrl);
+
+        if (value)
+                ctrlval |= 1 << (gpio & 31);
+        else
+                ctrlval &= ~(1 << (gpio & 31));
+
+        __raw_writel(ctrlval, ctrl);
+}
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h
new file mode 100644
index 000000000000..131cd1715caa
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/gpio-ns9360.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-ns9xxx/gpio-ns9360.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func);
+int ns9360_gpio_get_value(unsigned gpio);
+void ns9360_gpio_set_value(unsigned gpio, int value);
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c
index 5286e9fc1d30..b3c963b0c8f5 100644
--- a/arch/arm/mach-ns9xxx/gpio.c
+++ b/arch/arm/mach-ns9xxx/gpio.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/gpio.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -15,12 +15,13 @@
 
 #include <asm/arch-ns9xxx/gpio.h>
 #include <asm/arch-ns9xxx/processor.h>
-#include <asm/arch-ns9xxx/regs-bbu.h>
-#include <asm/io.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
 #include <asm/bug.h>
 #include <asm/types.h>
 #include <asm/bitops.h>
 
+#include "gpio-ns9360.h"
+
 #if defined(CONFIG_PROCESSOR_NS9360)
 #define GPIO_MAX 72
 #elif defined(CONFIG_PROCESSOR_NS9750)
@@ -45,41 +46,10 @@ static inline int ns9xxx_valid_gpio(unsigned gpio)
                 return gpio <= 49;
         else
 #endif
+        {
                 BUG();
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio)
-{
-        if (gpio < 56)
-                return BBU_GCONFb1(gpio / 8);
-        else
-                /*
-                 * this could be optimised away on
-                 * ns9750 only builds, but it isn't ...
-                 */
-                return BBU_GCONFb2((gpio - 56) / 8);
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio)
-{
-        if (gpio < 32)
-                return BBU_GCTRL1;
-        else if (gpio < 64)
-                return BBU_GCTRL2;
-        else
-                /* this could be optimised away on ns9750 only builds */
-                return BBU_GCTRL3;
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio)
-{
-        if (gpio < 32)
-                return BBU_GSTAT1;
-        else if (gpio < 64)
-                return BBU_GSTAT2;
-        else
-                /* this could be optimised away on ns9750 only builds */
-                return BBU_GSTAT3;
+                return 0;
+        }
 }
 
 int gpio_request(unsigned gpio, const char *label)
@@ -98,49 +68,24 @@ void gpio_free(unsigned gpio)
 }
 EXPORT_SYMBOL(gpio_free);
 
-/*
- * each gpio can serve for 4 different purposes [0..3].  These are called
- * "functions" and passed in the parameter func.  Functions 0-2 are always some
- * special things, function 3 is GPIO.  If func == 3 dir specifies input or
- * output, and with inv you can enable an inverter (independent of func).
- */
-static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func)
+int gpio_direction_input(unsigned gpio)
 {
-        void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio);
-        u32 confval;
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        confval = __raw_readl(conf);
-        REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
-        REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
-        REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
-        __raw_writel(confval, conf);
+        if (likely(ns9xxx_valid_gpio(gpio))) {
+                int ret = -EINVAL;
+                unsigned long flags;
 
-        spin_unlock_irqrestore(&gpio_lock, flags);
+                spin_lock_irqsave(&gpio_lock, flags);
+#if defined(CONFIG_PROCESSOR_NS9360)
+                if (processor_is_ns9360())
+                        ret = __ns9360_gpio_configure(gpio, 0, 0, 3);
+                else
+#endif
+                        BUG();
 
-        return 0;
-}
+                spin_unlock_irqrestore(&gpio_lock, flags);
 
-int ns9xxx_gpio_configure(unsigned gpio, int inv, int func)
-{
-        if (likely(ns9xxx_valid_gpio(gpio))) {
-                if (func == 3) {
-                        printk(KERN_WARNING "use gpio_direction_input "
-                                        "or gpio_direction_output\n");
-                        return -EINVAL;
-                } else
-                        return __ns9xxx_gpio_configure(gpio, 0, inv, func);
-        } else
-                return -EINVAL;
-}
-EXPORT_SYMBOL(ns9xxx_gpio_configure);
+                return ret;
 
-int gpio_direction_input(unsigned gpio)
-{
-        if (likely(ns9xxx_valid_gpio(gpio))) {
-                return __ns9xxx_gpio_configure(gpio, 0, 0, 3);
         } else
                 return -EINVAL;
 }
@@ -149,9 +94,22 @@ EXPORT_SYMBOL(gpio_direction_input);
 int gpio_direction_output(unsigned gpio, int value)
 {
         if (likely(ns9xxx_valid_gpio(gpio))) {
+                int ret = -EINVAL;
+                unsigned long flags;
+
                 gpio_set_value(gpio, value);
 
-                return __ns9xxx_gpio_configure(gpio, 1, 0, 3);
+                spin_lock_irqsave(&gpio_lock, flags);
+#if defined(CONFIG_PROCESSOR_NS9360)
+                if (processor_is_ns9360())
+                        ret = __ns9360_gpio_configure(gpio, 1, 0, 3);
+                else
+#endif
+                        BUG();
+
+                spin_unlock_irqrestore(&gpio_lock, flags);
+
+                return ret;
         } else
                 return -EINVAL;
 }
@@ -159,31 +117,28 @@ EXPORT_SYMBOL(gpio_direction_output);
 
 int gpio_get_value(unsigned gpio)
 {
-        void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio);
-        int ret;
-
-        ret = 1 & (__raw_readl(stat) >> (gpio & 31));
-
-        return ret;
+#if defined(CONFIG_PROCESSOR_NS9360)
+        if (processor_is_ns9360())
+                return ns9360_gpio_get_value(gpio);
+        else
+#endif
+        {
+                BUG();
+                return -EINVAL;
+        }
 }
 EXPORT_SYMBOL(gpio_get_value);
 
 void gpio_set_value(unsigned gpio, int value)
 {
-        void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio);
-        u32 ctrlval;
         unsigned long flags;
-
         spin_lock_irqsave(&gpio_lock, flags);
-
-        ctrlval = __raw_readl(ctrl);
-
-        if (value)
-                ctrlval |= 1 << (gpio & 31);
+#if defined(CONFIG_PROCESSOR_NS9360)
+        if (processor_is_ns9360())
+                ns9360_gpio_set_value(gpio, value);
         else
-                ctrlval &= ~(1 << (gpio & 31));
-
-        __raw_writel(ctrlval, ctrl);
+#endif
+                BUG();
 
         spin_unlock_irqrestore(&gpio_lock, flags);
 }
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 00001b874e97..36e5835e6097 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -9,21 +9,27 @@
  * the Free Software Foundation.
  */
 #include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
 #include <asm/io.h>
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-sys-common.h>
 #include <asm/arch-ns9xxx/irqs.h>
 #include <asm/arch-ns9xxx/board.h>
 
 #include "generic.h"
 
+/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */
+#define irq2prio(i) (i)
+#define prio2irq(p) (p)
+
 static void ns9xxx_mask_irq(unsigned int irq)
 {
         /* XXX: better use cpp symbols */
-        u32 ic = __raw_readl(SYS_IC(irq / 4));
-        ic &= ~(1 << (7 + 8 * (3 - (irq & 3))));
-        __raw_writel(ic, SYS_IC(irq / 4));
+        int prio = irq2prio(irq);
+        u32 ic = __raw_readl(SYS_IC(prio / 4));
+        ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
+        __raw_writel(ic, SYS_IC(prio / 4));
 }
 
 static void ns9xxx_ack_irq(unsigned int irq)
@@ -40,9 +46,10 @@ static void ns9xxx_maskack_irq(unsigned int irq)
 static void ns9xxx_unmask_irq(unsigned int irq)
 {
         /* XXX: better use cpp symbols */
-        u32 ic = __raw_readl(SYS_IC(irq / 4));
-        ic |= 1 << (7 + 8 * (3 - (irq & 3)));
-        __raw_writel(ic, SYS_IC(irq / 4));
+        int prio = irq2prio(irq);
+        u32 ic = __raw_readl(SYS_IC(prio / 4));
+        ic |= 1 << (7 + 8 * (3 - (prio & 3)));
+        __raw_writel(ic, SYS_IC(prio / 4));
 }
 
 static struct irq_chip ns9xxx_chip = {
@@ -52,24 +59,61 @@ static struct irq_chip ns9xxx_chip = {
         .unmask         = ns9xxx_unmask_irq,
 };
 
+#if 0
+#define handle_irq handle_level_irq
+#else
+void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned int cpu = smp_processor_id();
+        struct irqaction *action;
+        irqreturn_t action_ret;
+
+        spin_lock(&desc->lock);
+
+        if (unlikely(desc->status & IRQ_INPROGRESS))
+                goto out_unlock;
+
+        desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
+        kstat_cpu(cpu).irqs[irq]++;
+
+        action = desc->action;
+        if (unlikely(!action || (desc->status & IRQ_DISABLED)))
+                goto out_unlock;
+
+        desc->status |= IRQ_INPROGRESS;
+        spin_unlock(&desc->lock);
+
+        action_ret = handle_IRQ_event(irq, action);
+
+        spin_lock(&desc->lock);
+        desc->status &= ~IRQ_INPROGRESS;
+        if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)
+                desc->chip->ack(irq);
+
+out_unlock:
+        spin_unlock(&desc->lock);
+}
+#define handle_irq handle_prio_irq
+#endif
+
 void __init ns9xxx_init_irq(void)
 {
         int i;
 
         /* disable all IRQs */
         for (i = 0; i < 8; ++i)
-                __raw_writel((4 * i) << 24 | (4 * i + 1) << 16 |
-                                (4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i));
+                __raw_writel(prio2irq(4 * i) << 24 |
+                                prio2irq(4 * i + 1) << 16 |
+                                prio2irq(4 * i + 2) << 8 |
+                                prio2irq(4 * i + 3),
+                                SYS_IC(i));
 
-        /* simple interrupt prio table:
-         * prio(x) < prio(y) <=> x < y
-         */
         for (i = 0; i < 32; ++i)
-                __raw_writel(i, SYS_IVA(i));
+                __raw_writel(prio2irq(i), SYS_IVA(i));
 
-        for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) {
+        for (i = 0; i <= 31; ++i) {
                 set_irq_chip(i, &ns9xxx_chip);
-                set_irq_handler(i, handle_level_irq);
+                set_irq_handler(i, handle_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
index 760c9d0db7c3..9623fff6b3bc 100644
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,12 +11,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
 #include "board-a9m9750dev.h"
 #include "generic.h"
 
 static void __init mach_cc9p9360dev_map_io(void)
 {
-        ns9xxx_map_io();
+        ns9360_map_io();
         board_a9m9750dev_map_io();
 }
 
@@ -36,6 +38,6 @@ MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard")
         .map_io = mach_cc9p9360dev_map_io,
         .init_irq = mach_cc9p9360dev_init_irq,
         .init_machine = mach_cc9p9360dev_init_machine,
-        .timer = &ns9xxx_timer,
+        .timer = &ns9360_timer,
         .boot_params = 0x100,
 MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
index 85c8b41105c9..fcc815bdd291 100644
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/mach-cc9p9360js.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,6 +11,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
 #include "board-jscc9p9360.h"
 #include "generic.h"
 
@@ -21,9 +23,9 @@ static void __init mach_cc9p9360js_init_machine(void)
 }
 
 MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
-        .map_io = ns9xxx_map_io,
+        .map_io = ns9360_map_io,
         .init_irq = ns9xxx_init_irq,
         .init_machine = mach_cc9p9360js_init_machine,
-        .timer = &ns9xxx_timer,
+        .timer = &ns9360_timer,
         .boot_params = 0x100,
 MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c
new file mode 100644
index 000000000000..5aa5d9baf8c8
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/plat-serial8250.c
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/mach-ns9xxx/plat-serial8250.c
+ *
+ * Copyright (C) 2008 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
+#include <asm/arch-ns9xxx/board.h>
+
+#define DRIVER_NAME "serial8250"
+
+static int __init ns9xxx_plat_serial8250_init(void)
+{
+        struct plat_serial8250_port *pdata;
+        struct platform_device *pdev;
+        int ret = -ENOMEM;
+        int i;
+
+        if (!board_is_a9m9750dev())
+                return -ENODEV;
+
+        pdev = platform_device_alloc(DRIVER_NAME, 0);
+        if (!pdev)
+                goto err;
+
+        pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL);
+        if (!pdata)
+                goto err;
+
+        pdev->dev.platform_data = pdata;
+
+        pdata[0].iobase = FPGA_UARTA_BASE;
+        pdata[1].iobase = FPGA_UARTB_BASE;
+        pdata[2].iobase = FPGA_UARTC_BASE;
+        pdata[3].iobase = FPGA_UARTD_BASE;
+
+        for (i = 0; i < 4; ++i) {
+                pdata[i].membase = (void __iomem *)pdata[i].iobase;
+                pdata[i].mapbase = pdata[i].iobase;
+                pdata[i].iotype = UPIO_MEM;
+                pdata[i].uartclk = 18432000;
+                pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+        }
+
+        pdata[0].irq = IRQ_FPGA_UARTA;
+        pdata[1].irq = IRQ_FPGA_UARTB;
+        pdata[2].irq = IRQ_FPGA_UARTC;
+        pdata[3].irq = IRQ_FPGA_UARTD;
+
+        ret = platform_device_add(pdev);
+        if (ret) {
+err:
+                platform_device_put(pdev);
+
+                printk(KERN_WARNING "Could not add %s (errno=%d)\n",
+                                DRIVER_NAME, ret);
+        }
+
+        return 0;
+}
+
+arch_initcall(ns9xxx_plat_serial8250_init);
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c
new file mode 100644
index 000000000000..2bee0b7fccbb
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/processor-ns9360.c
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-ns9xxx/processor-ns9360.c
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
+
+void ns9360_reset(char mode)
+{
+        u32 reg;
+
+        reg = __raw_readl(SYS_PLL) >> 16;
+        REGSET(reg, SYS_PLL, SWC, YES);
+        __raw_writel(reg, SYS_PLL);
+}
+
+#define CRYSTAL 29491200 /* Hz */
+unsigned long ns9360_systemclock(void)
+{
+        u32 pll = __raw_readl(SYS_PLL);
+        return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
+                >> REGGETIM(pll, SYS_PLL, FS);
+}
+
+static struct map_desc ns9360_io_desc[] __initdata = {
+        { /* BBus */
+                .virtual = io_p2v(0x90000000),
+                .pfn = __phys_to_pfn(0x90000000),
+                .length = 0x00700000,
+                .type = MT_DEVICE,
+        }, { /* AHB */
+                .virtual = io_p2v(0xa0100000),
+                .pfn = __phys_to_pfn(0xa0100000),
+                .length = 0x00900000,
+                .type = MT_DEVICE,
+        },
+};
+
+void __init ns9360_map_io(void)
+{
+        iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc));
+}
diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time-ns9360.c
index c3dd1f4acb99..4d573c9793ed 100644
--- a/arch/arm/mach-ns9xxx/time.c
+++ b/arch/arm/mach-ns9xxx/time-ns9360.c
@@ -1,7 +1,7 @@
 /*
- * arch/arm/mach-ns9xxx/time.c
+ * arch/arm/mach-ns9xxx/time-ns9360.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -15,8 +15,8 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/arch-ns9xxx/clock.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
 #include <asm/arch-ns9xxx/irqs.h>
 #include <asm/arch/system.h>
 #include "generic.h"
@@ -25,26 +25,26 @@
 #define TIMER_CLOCKEVENT 1
 static u32 latch;
 
-static cycle_t ns9xxx_clocksource_read(void)
+static cycle_t ns9360_clocksource_read(void)
 {
         return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
 }
 
-static struct clocksource ns9xxx_clocksource = {
-        .name   = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE),
+static struct clocksource ns9360_clocksource = {
+        .name   = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE),
         .rating = 300,
-        .read   = ns9xxx_clocksource_read,
+        .read   = ns9360_clocksource_read,
         .mask   = CLOCKSOURCE_MASK(32),
         .shift  = 20,
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
+static void ns9360_clockevent_setmode(enum clock_event_mode mode,
                 struct clock_event_device *clk)
 {
         u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
 
-        switch(mode) {
+        switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
                 REGSET(tc, SYS_TCx, REN, EN);
@@ -69,7 +69,7 @@ static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
         __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
 }
 
-static int ns9xxx_clockevent_setnextevent(unsigned long evt,
+static int ns9360_clockevent_setnextevent(unsigned long evt,
                 struct clock_event_device *clk)
 {
         u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
@@ -88,20 +88,20 @@ static int ns9xxx_clockevent_setnextevent(unsigned long evt,
         return 0;
 }
 
-static struct clock_event_device ns9xxx_clockevent_device = {
-        .name           = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
+static struct clock_event_device ns9360_clockevent_device = {
+        .name           = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
         .shift          = 20,
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = ns9xxx_clockevent_setmode,
-        .set_next_event = ns9xxx_clockevent_setnextevent,
+        .set_mode       = ns9360_clockevent_setmode,
+        .set_next_event = ns9360_clockevent_setnextevent,
 };
 
-static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
+static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id)
 {
-        int timerno = irq - IRQ_TIMER0;
+        int timerno = irq - IRQ_NS9360_TIMER0;
         u32 tc;
 
-        struct clock_event_device *evt = &ns9xxx_clockevent_device;
+        struct clock_event_device *evt = &ns9360_clockevent_device;
 
         /* clear irq */
         tc = __raw_readl(SYS_TC(timerno));
@@ -119,13 +119,13 @@ static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction ns9xxx_clockevent_action = {
-        .name           = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
+static struct irqaction ns9360_clockevent_action = {
+        .name           = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = ns9xxx_clockevent_handler,
+        .handler        = ns9360_clockevent_handler,
 };
 
-static void __init ns9xxx_timer_init(void)
+static void __init ns9360_timer_init(void)
 {
         int tc;
 
@@ -148,12 +148,12 @@ static void __init ns9xxx_timer_init(void)
 
         __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
 
-        ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(),
-                        ns9xxx_clocksource.shift);
+        ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(),
+                        ns9360_clocksource.shift);
 
-        clocksource_register(&ns9xxx_clocksource);
+        clocksource_register(&ns9360_clocksource);
 
-        latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0);
+        latch = SH_DIV(ns9360_cpuclock(), HZ, 0);
 
         tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
         REGSET(tc, SYS_TCx, TEN, DIS);
@@ -166,19 +166,20 @@ static void __init ns9xxx_timer_init(void)
         REGSET(tc, SYS_TCx, REN, EN);
         __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
 
-        ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(),
-                        NSEC_PER_SEC, ns9xxx_clockevent_device.shift);
-        ns9xxx_clockevent_device.max_delta_ns =
-                clockevent_delta2ns(-1, &ns9xxx_clockevent_device);
-        ns9xxx_clockevent_device.min_delta_ns =
-                clockevent_delta2ns(1, &ns9xxx_clockevent_device);
+        ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(),
+                        NSEC_PER_SEC, ns9360_clockevent_device.shift);
+        ns9360_clockevent_device.max_delta_ns =
+                clockevent_delta2ns(-1, &ns9360_clockevent_device);
+        ns9360_clockevent_device.min_delta_ns =
+                clockevent_delta2ns(1, &ns9360_clockevent_device);
 
-        ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0);
-        clockevents_register_device(&ns9xxx_clockevent_device);
+        ns9360_clockevent_device.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&ns9360_clockevent_device);
 
-        setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action);
+        setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT,
+                        &ns9360_clockevent_action);
 }
 
-struct sys_timer ns9xxx_timer = {
-        .init = ns9xxx_timer_init,
+struct sys_timer ns9360_timer = {
+        .init = ns9360_timer_init,
 };
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 015a66b3ca8e..c06f5254c0f3 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -5,7 +5,8 @@
 # Common support
 obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
 
-obj-$(CONFIG_OMAP_MPU_TIMER)            += time.o
+obj-$(CONFIG_OMAP_MPU_TIMER)    += time.o
+obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
 
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 5279e35a8aec..4f9baba7d893 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/i2c.h>
+#include <linux/leds.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -183,11 +184,80 @@ static struct platform_device *osk5912_devices[] __initdata = {
         &osk5912_mcbsp1_device,
 };
 
+static struct gpio_led tps_leds[] = {
+        /* NOTE:  D9 and D2 have hardware blink support.
+         * Also, D9 requires non-battery power.
+         */
+        { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", },
+        { .gpio = OSK_TPS_GPIO_LED_D2, .name = "d2", },
+        { .gpio = OSK_TPS_GPIO_LED_D3, .name = "d3", .active_low = 1,
+                        .default_trigger = "heartbeat", },
+};
+
+static struct gpio_led_platform_data tps_leds_data = {
+        .num_leds       = 3,
+        .leds           = tps_leds,
+};
+
+static struct platform_device osk5912_tps_leds = {
+        .name                   = "leds-gpio",
+        .id                     = 0,
+        .dev.platform_data      = &tps_leds_data,
+};
+
+static int osk_tps_setup(struct i2c_client *client, void *context)
+{
+        /* Set GPIO 1 HIGH to disable VBUS power supply;
+         * OHCI driver powers it up/down as needed.
+         */
+        gpio_request(OSK_TPS_GPIO_USB_PWR_EN, "n_vbus_en");
+        gpio_direction_output(OSK_TPS_GPIO_USB_PWR_EN, 1);
+
+        /* Set GPIO 2 high so LED D3 is off by default */
+        tps65010_set_gpio_out_value(GPIO2, HIGH);
+
+        /* Set GPIO 3 low to take ethernet out of reset */
+        gpio_request(OSK_TPS_GPIO_LAN_RESET, "smc_reset");
+        gpio_direction_output(OSK_TPS_GPIO_LAN_RESET, 0);
+
+        /* GPIO4 is VDD_DSP */
+        gpio_request(OSK_TPS_GPIO_DSP_PWR_EN, "dsp_power");
+        gpio_direction_output(OSK_TPS_GPIO_DSP_PWR_EN, 1);
+        /* REVISIT if DSP support isn't configured, power it off ... */
+
+        /* Let LED1 (D9) blink; leds-gpio may override it */
+        tps65010_set_led(LED1, BLINK);
+
+        /* Set LED2 off by default */
+        tps65010_set_led(LED2, OFF);
+
+        /* Enable LOW_PWR handshake */
+        tps65010_set_low_pwr(ON);
+
+        /* Switch VLDO2 to 3.0V for AIC23 */
+        tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
+                        | TPS_LDO1_ENABLE);
+
+        /* register these three LEDs */
+        osk5912_tps_leds.dev.parent = &client->dev;
+        platform_device_register(&osk5912_tps_leds);
+
+        return 0;
+}
+
+static struct tps65010_board tps_board = {
+        .base           = OSK_TPS_GPIO_BASE,
+        .outmask        = 0x0f,
+        .setup          = osk_tps_setup,
+};
+
 static struct i2c_board_info __initdata osk_i2c_board_info[] = {
         {
                 I2C_BOARD_INFO("tps65010", 0x48),
                 .type           = "tps65010",
                 .irq            = OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
+                .platform_data  = &tps_board,
+
         },
         /* TODO when driver support is ready:
          *  - aic23 audio chip at 0x1a
@@ -198,7 +268,7 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 
 static void __init osk_init_smc91x(void)
 {
-        if ((omap_request_gpio(0)) < 0) {
+        if ((gpio_request(0, "smc_irq")) < 0) {
                 printk("Error requesting gpio 0 for smc91x irq\n");
                 return;
         }
@@ -210,7 +280,7 @@ static void __init osk_init_smc91x(void)
 static void __init osk_init_cf(void)
 {
         omap_cfg_reg(M7_1610_GPIO62);
-        if ((omap_request_gpio(62)) < 0) {
+        if ((gpio_request(62, "cf_irq")) < 0) {
                 printk("Error requesting gpio 62 for CF irq\n");
                 return;
         }
@@ -334,7 +404,7 @@ static struct platform_device *mistral_devices[] __initdata = {
 
 static int mistral_get_pendown_state(void)
 {
-        return !omap_get_gpio_datain(4);
+        return !gpio_get_value(4);
 }
 
 static const struct ads7846_platform_data mistral_ts_info = {
@@ -396,25 +466,31 @@ static void __init osk_mistral_init(void)
         omap_cfg_reg(W14_1610_CCP_DATAP);
 
         /* CAM_PWDN */
-        if (omap_request_gpio(11) == 0) {
+        if (gpio_request(11, "cam_pwdn") == 0) {
                 omap_cfg_reg(N20_1610_GPIO11);
-                omap_set_gpio_direction(11, 0 /* out */);
-                omap_set_gpio_dataout(11, 0 /* off */);
+                gpio_direction_output(11, 0);
         } else
                 pr_debug("OSK+Mistral: CAM_PWDN is awol\n");
 
 
         /* omap_cfg_reg(P19_1610_GPIO6); */     /* BUSY */
+        gpio_request(6, "ts_busy");
+        gpio_direction_input(6);
+
         omap_cfg_reg(P20_1610_GPIO4);   /* PENIRQ */
+        gpio_request(4, "ts_int");
+        gpio_direction_input(4);
         set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
+
         spi_register_board_info(mistral_boardinfo,
                         ARRAY_SIZE(mistral_boardinfo));
 
         /* the sideways button (SW1) is for use as a "wakeup" button */
         omap_cfg_reg(N15_1610_MPUIO2);
-        if (omap_request_gpio(OMAP_MPUIO(2)) == 0) {
+        if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) {
                 int ret = 0;
-                omap_set_gpio_direction(OMAP_MPUIO(2), 1);
+
+                gpio_direction_input(OMAP_MPUIO(2));
                 set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING);
 #ifdef  CONFIG_PM
                 /* share the IRQ in case someone wants to use the
@@ -425,7 +501,7 @@ static void __init osk_mistral_init(void)
                                 IRQF_SHARED, "mistral_wakeup",
                                 &osk_mistral_wake_interrupt);
                 if (ret != 0) {
-                        omap_free_gpio(OMAP_MPUIO(2));
+                        gpio_free(OMAP_MPUIO(2));
                         printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n",
                                 ret);
                 } else
@@ -438,10 +514,8 @@ static void __init osk_mistral_init(void)
          * board, like the touchscreen, EEPROM, and wakeup (!) switch.
          */
         omap_cfg_reg(PWL);
-        if (omap_request_gpio(2) == 0) {
-                omap_set_gpio_direction(2, 0 /* out */);
-                omap_set_gpio_dataout(2, 1 /* on */);
-        }
+        if (gpio_request(2, "lcd_pwr") == 0)
+                gpio_direction_output(2, 1);
 
         platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices));
 }
@@ -484,44 +558,6 @@ static void __init osk_map_io(void)
         omap1_map_common_io();
 }
 
-#ifdef CONFIG_TPS65010
-static int __init osk_tps_init(void)
-{
-        if (!machine_is_omap_osk())
-                return 0;
-
-        /* Let LED1 (D9) blink */
-        tps65010_set_led(LED1, BLINK);
-
-        /* Disable LED 2 (D2) */
-        tps65010_set_led(LED2, OFF);
-
-        /* Set GPIO 1 HIGH to disable VBUS power supply;
-         * OHCI driver powers it up/down as needed.
-         */
-        tps65010_set_gpio_out_value(GPIO1, HIGH);
-
-        /* Set GPIO 2 low to turn on LED D3 */
-        tps65010_set_gpio_out_value(GPIO2, HIGH);
-
-        /* Set GPIO 3 low to take ethernet out of reset */
-        tps65010_set_gpio_out_value(GPIO3, LOW);
-
-        /* gpio4 for VDD_DSP */
-        /* FIXME send power to DSP iff it's configured */
-
-        /* Enable LOW_PWR */
-        tps65010_set_low_pwr(ON);
-
-        /* Switch VLDO2 to 3.0V for AIC23 */
-        tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
-                        | TPS_LDO1_ENABLE);
-
-        return 0;
-}
-fs_initcall(osk_tps_init);
-#endif
-
 MACHINE_START(OMAP_OSK, "TI-OSK")
         /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
         .phys_io        = 0xfff00000,
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index 026685ed461a..754383dde807 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -1,11 +1,9 @@
 /*
  * linux/arch/arm/mach-omap1/leds-osk.c
  *
- * LED driver for OSK, and optionally Mistral QVGA, boards
+ * LED driver for OSK with optional Mistral QVGA board
  */
 #include <linux/init.h>
-#include <linux/workqueue.h>
-#include <linux/i2c/tps65010.h>
 
 #include <asm/hardware.h>
 #include <asm/leds.h>
@@ -20,49 +18,11 @@
 #define LED_STATE_CLAIMED       (1 << 1)
 static u8 led_state;
 
-#define GREEN_LED               (1 << 0)        /* TPS65010 LED1 */
-#define AMBER_LED               (1 << 1)        /* TPS65010 LED2 */
-#define RED_LED                 (1 << 2)        /* TPS65010 GPIO2 */
 #define TIMER_LED               (1 << 3)        /* Mistral board */
 #define IDLE_LED                (1 << 4)        /* Mistral board */
 static u8 hw_led_state;
 
 
-/* TPS65010 leds are changed using i2c -- from a task context.
- * Using one of these for the "idle" LED would be impractical...
- */
-#define TPS_LEDS        (GREEN_LED | RED_LED | AMBER_LED)
-
-static u8 tps_leds_change;
-
-static void tps_work(struct work_struct *unused)
-{
-        for (;;) {
-                u8      leds;
-
-                local_irq_disable();
-                leds = tps_leds_change;
-                tps_leds_change = 0;
-                local_irq_enable();
-
-                if (!leds)
-                        break;
-
-                /* careful:  the set_led() value is on/off/blink */
-                if (leds & GREEN_LED)
-                        tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED));
-                if (leds & AMBER_LED)
-                        tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED));
-
-                /* the gpio led doesn't have that issue */
-                if (leds & RED_LED)
-                        tps65010_set_gpio_out_value(GPIO2,
-                                        !(hw_led_state & RED_LED));
-        }
-}
-
-static DECLARE_WORK(work, tps_work);
-
 #ifdef  CONFIG_OMAP_OSK_MISTRAL
 
 /* For now, all system indicators require the Mistral board, since that
@@ -112,7 +72,6 @@ void osk_leds_event(led_event_t evt)
         case led_stop:
                 led_state &= ~LED_STATE_ENABLED;
                 hw_led_state = 0;
-                /* NOTE:  work may still be pending!! */
                 break;
 
         case led_claim:
@@ -145,48 +104,11 @@ void osk_leds_event(led_event_t evt)
 
 #endif  /* CONFIG_OMAP_OSK_MISTRAL */
 
-        /* "green" == tps LED1 (leftmost, normally power-good)
-         * works only with DC adapter, not on battery power!
-         */
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GREEN_LED;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~GREEN_LED;
-                break;
-
-        /* "amber" == tps LED2 (middle) */
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= AMBER_LED;
-                break;
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~AMBER_LED;
-                break;
-
-        /* "red" == LED on tps gpio3 (rightmost) */
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= RED_LED;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~RED_LED;
-                break;
-
         default:
                 break;
         }
 
         leds ^= hw_led_state;
-        leds &= TPS_LEDS;
-        if (leds && (led_state & LED_STATE_CLAIMED)) {
-                tps_leds_change |= leds;
-                schedule_work(&work);
-        }
 
 done:
         local_irq_restore(flags);
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 52c70e5fcf65..e207bf7cb853 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -3,9 +3,9 @@
  *
  * OMAP1 pin multiplexing configurations
  *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -32,8 +32,10 @@
 
 #ifdef CONFIG_OMAP_MUX
 
+static struct omap_mux_cfg arch_mux_cfg;
+
 #ifdef CONFIG_ARCH_OMAP730
-struct pin_config __initdata_or_module omap730_pins[] = {
+static struct pin_config __initdata_or_module omap730_pins[] = {
 MUX_CFG_730("E2_730_KBR0",        12,   21,    0,   20,   1, 0)
 MUX_CFG_730("J7_730_KBR1",        12,   25,    0,   24,   1, 0)
 MUX_CFG_730("E1_730_KBR2",        12,   29,    0,   28,   1, 0)
@@ -49,10 +51,14 @@ MUX_CFG_730("AA17_730_USB_DM",     2,   21,    0,   20,   0, 0)
 MUX_CFG_730("W16_730_USB_PU_EN",   2,   25,    0,   24,   0, 0)
 MUX_CFG_730("W17_730_USB_VBUSI",   2,   29,    0,   28,   0, 0)
 };
-#endif
+#define OMAP730_PINS_SZ         ARRAY_SIZE(omap730_pins)
+#else
+#define omap730_pins            NULL
+#define OMAP730_PINS_SZ         0
+#endif  /* CONFIG_ARCH_OMAP730 */
 
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-struct pin_config __initdata_or_module omap1xxx_pins[] = {
+static struct pin_config __initdata_or_module omap1xxx_pins[] = {
 /*
  *       description            mux  mode   mux  pull pull  pull  pu_pd  pu  dbg
  *                              reg  offset mode reg  bit   ena   reg
@@ -306,22 +312,136 @@ MUX_CFG("Y12_1610_CCP_CLKP",	 8,   18,    6,   1,  24,   1,    1,     0,  0)
 MUX_CFG("W13_1610_CCP_CLKM",     9,    0,    6,   1,  28,   1,    1,     0,  0)
 MUX_CFG("W14_1610_CCP_DATAP",    9,   24,    6,   2,   4,   1,    2,     0,  0)
 MUX_CFG("Y14_1610_CCP_DATAM",    9,   21,    6,   2,   3,   1,    2,     0,  0)
-
 };
+#define OMAP1XXX_PINS_SZ        ARRAY_SIZE(omap1xxx_pins)
+#else
+#define omap1xxx_pins           NULL
+#define OMAP1XXX_PINS_SZ        0
 #endif  /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
 
-int __init omap1_mux_init(void)
+int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 {
-
-#ifdef CONFIG_ARCH_OMAP730
-        omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins));
+        static DEFINE_SPINLOCK(mux_spin_lock);
+        unsigned long flags;
+        unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
+                pull_orig = 0, pull = 0;
+        unsigned int mask, warn = 0;
+
+        /* Check the mux register in question */
+        if (cfg->mux_reg) {
+                unsigned        tmp1, tmp2;
+
+                spin_lock_irqsave(&mux_spin_lock, flags);
+                reg_orig = omap_readl(cfg->mux_reg);
+
+                /* The mux registers always seem to be 3 bits long */
+                mask = (0x7 << cfg->mask_offset);
+                tmp1 = reg_orig & mask;
+                reg = reg_orig & ~mask;
+
+                tmp2 = (cfg->mask << cfg->mask_offset);
+                reg |= tmp2;
+
+                if (tmp1 != tmp2)
+                        warn = 1;
+
+                omap_writel(reg, cfg->mux_reg);
+                spin_unlock_irqrestore(&mux_spin_lock, flags);
+        }
+
+        /* Check for pull up or pull down selection on 1610 */
+        if (!cpu_is_omap15xx()) {
+                if (cfg->pu_pd_reg && cfg->pull_val) {
+                        spin_lock_irqsave(&mux_spin_lock, flags);
+                        pu_pd_orig = omap_readl(cfg->pu_pd_reg);
+                        mask = 1 << cfg->pull_bit;
+
+                        if (cfg->pu_pd_val) {
+                                if (!(pu_pd_orig & mask))
+                                        warn = 1;
+                                /* Use pull up */
+                                pu_pd = pu_pd_orig | mask;
+                        } else {
+                                if (pu_pd_orig & mask)
+                                        warn = 1;
+                                /* Use pull down */
+                                pu_pd = pu_pd_orig & ~mask;
+                        }
+                        omap_writel(pu_pd, cfg->pu_pd_reg);
+                        spin_unlock_irqrestore(&mux_spin_lock, flags);
+                }
+        }
+
+        /* Check for an associated pull down register */
+        if (cfg->pull_reg) {
+                spin_lock_irqsave(&mux_spin_lock, flags);
+                pull_orig = omap_readl(cfg->pull_reg);
+                mask = 1 << cfg->pull_bit;
+
+                if (cfg->pull_val) {
+                        if (pull_orig & mask)
+                                warn = 1;
+                        /* Low bit = pull enabled */
+                        pull = pull_orig & ~mask;
+                } else {
+                        if (!(pull_orig & mask))
+                                warn = 1;
+                        /* High bit = pull disabled */
+                        pull = pull_orig | mask;
+                }
+
+                omap_writel(pull, cfg->pull_reg);
+                spin_unlock_irqrestore(&mux_spin_lock, flags);
+        }
+
+        if (warn) {
+#ifdef CONFIG_OMAP_MUX_WARNINGS
+                printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
 #endif
-
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-        omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins));
+        }
+
+#ifdef CONFIG_OMAP_MUX_DEBUG
+        if (cfg->debug || warn) {
+                printk("MUX: Setting register %s\n", cfg->name);
+                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
+
+                if (!cpu_is_omap15xx()) {
+                        if (cfg->pu_pd_reg && cfg->pull_val) {
+                                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                                       cfg->pu_pd_name, cfg->pu_pd_reg,
+                                       pu_pd_orig, pu_pd);
+                        }
+                }
+
+                if (cfg->pull_reg)
+                        printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                               cfg->pull_name, cfg->pull_reg, pull_orig, pull);
+        }
 #endif
 
+#ifdef CONFIG_OMAP_MUX_ERRORS
+        return warn ? -ETXTBSY : 0;
+#else
         return 0;
+#endif
+}
+
+int __init omap1_mux_init(void)
+{
+        if (cpu_is_omap730()) {
+                arch_mux_cfg.pins       = omap730_pins;
+                arch_mux_cfg.size       = OMAP730_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap1_cfg_reg;
+        }
+
+        if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+                arch_mux_cfg.pins       = omap1xxx_pins;
+                arch_mux_cfg.size       = OMAP1XXX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap1_cfg_reg;
+        }
+
+        return omap_mux_register(&arch_mux_cfg);
 }
 
 #endif
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index a4f8b2055437..5d2b270935a2 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -56,37 +56,6 @@
 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
 #define OMAP_MPU_TIMER_OFFSET           0x100
 
-/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
- * converted to use kHz by Kevin Hilman */
-/* convert from cycles(64bits) => nanoseconds (64bits)
- *  basic equation:
- *              ns = cycles / (freq / ns_per_sec)
- *              ns = cycles * (ns_per_sec / freq)
- *              ns = cycles * (10^9 / (cpu_khz * 10^3))
- *              ns = cycles * (10^6 / cpu_khz)
- *
- *      Then we use scaling math (suggested by george at mvista.com) to get:
- *              ns = cycles * (10^6 * SC / cpu_khz / SC
- *              ns = cycles * cyc2ns_scale / SC
- *
- *      And since SC is a constant power of two, we can convert the div
- *  into a shift.
- *                      -johnstul at us.ibm.com "math is hard, lets go shopping!"
- */
-static unsigned long cyc2ns_scale;
-#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
-
-static inline void set_cyc2ns_scale(unsigned long cpu_khz)
-{
-        cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
-}
-
-static inline unsigned long long cycles_2_ns(unsigned long long cyc)
-{
-        return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
-}
-
-
 typedef struct {
         u32 cntl;                       /* CNTL_TIMER, R/W */
         u32 load_tim;                   /* LOAD_TIM,   W */
@@ -194,8 +163,6 @@ static struct irqaction omap_mpu_timer1_irq = {
 
 static __init void omap_init_mpu_timer(unsigned long rate)
 {
-        set_cyc2ns_scale(rate / 1000);
-
         setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
         omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
 
@@ -260,22 +227,6 @@ static void __init omap_init_clocksource(unsigned long rate)
                 printk(err, clocksource_mpu.name);
 }
 
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
-        unsigned long ticks = 0 - omap_mpu_timer_read(1);
-        unsigned long long ticks64;
-
-        ticks64 = omap_mpu_timer2_overflows;
-        ticks64 <<= 32;
-        ticks64 |= ticks;
-
-        return cycles_2_ns(ticks64);
-}
-
 /*
  * ---------------------------------------------------------------------------
  * Timer initialization
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index ea76f1979a3d..fbbdb806c95a 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/plat-omap/timer32k.c
+ * linux/arch/arm/mach-omap1/timer32k.c
  *
  * OMAP 32K Timer
  *
@@ -70,8 +70,6 @@ struct sys_timer omap_timer;
 
 #if defined(CONFIG_ARCH_OMAP16XX)
 #define TIMER_32K_SYNCHRONIZED          0xfffbc410
-#elif defined(CONFIG_ARCH_OMAP24XX)
-#define TIMER_32K_SYNCHRONIZED          (OMAP24XX_32KSYNCT_BASE + 0x10)
 #else
 #error OMAP 32KHz timer does not currently work on 15XX!
 #endif
@@ -93,8 +91,6 @@ struct sys_timer omap_timer;
 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                     \
                                 (((nr_jiffies) * (clock_rate)) / HZ)
 
-#if defined(CONFIG_ARCH_OMAP1)
-
 static inline void omap_32k_timer_write(int val, int reg)
 {
         omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
@@ -120,30 +116,14 @@ static inline void omap_32k_timer_stop(void)
 
 #define omap_32k_timer_ack_irq()
 
-#elif defined(CONFIG_ARCH_OMAP2)
-
-static struct omap_dm_timer *gptimer;
-
-static inline void omap_32k_timer_start(unsigned long load_val)
-{
-        omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
-        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        omap_dm_timer_start(gptimer);
-}
-
-static inline void omap_32k_timer_stop(void)
+static int omap_32k_timer_set_next_event(unsigned long delta,
+                                         struct clock_event_device *dev)
 {
-        omap_dm_timer_stop(gptimer);
-}
+        omap_32k_timer_start(delta);
 
-static inline void omap_32k_timer_ack_irq(void)
-{
-        u32 status = omap_dm_timer_read_status(gptimer);
-        omap_dm_timer_write_status(gptimer, status);
+        return 0;
 }
 
-#endif
-
 static void omap_32k_timer_set_mode(enum clock_event_mode mode,
                                     struct clock_event_device *evt)
 {
@@ -164,8 +144,9 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode,
 
 static struct clock_event_device clockevent_32k_timer = {
         .name           = "32k-timer",
-        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .shift          = 32,
+        .set_next_event = omap_32k_timer_set_next_event,
         .set_mode       = omap_32k_timer_set_mode,
 };
 
@@ -178,32 +159,6 @@ static inline unsigned long omap_32k_sync_timer_read(void)
         return omap_readl(TIMER_32K_SYNCHRONIZED);
 }
 
-/*
- * Rounds down to nearest usec. Note that this will overflow for larger values.
- */
-static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
-{
-        return (ticks_32k * 5*5*5*5*5*5) >> 9;
-}
-
-/*
- * Rounds down to nearest nsec.
- */
-static inline unsigned long long
-omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
-{
-        return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
-}
-
-/*
- * Returns current time from boot in nsecs. It's OK for this to wrap
- * around for now, as it's just a relative time stamp.
- */
-unsigned long long sched_clock(void)
-{
-        return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
-}
-
 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = &clockevent_32k_timer;
@@ -222,22 +177,7 @@ static struct irqaction omap_32k_timer_irq = {
 
 static __init void omap_init_32k_timer(void)
 {
-        if (cpu_class_is_omap1())
-                setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
-
-#ifdef CONFIG_ARCH_OMAP2
-        /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
-        if (cpu_is_omap24xx()) {
-                gptimer = omap_dm_timer_request_specific(1);
-                BUG_ON(gptimer == NULL);
-
-                omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
-                setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
-                omap_dm_timer_set_int_enable(gptimer,
-                        OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
-                        OMAP_TIMER_INT_MATCH);
-        }
-#endif
+        setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
 
         clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
                                            NSEC_PER_SEC,
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b05b738d31e6..2feb6870b735 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,13 +3,15 @@
 #
 
 # Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
-         serial.o gpmc.o
-
-obj-$(CONFIG_OMAP_MPU_TIMER)            += timer-gp.o
+obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
+                devices.o serial.o gpmc.o timer-gp.o
 
 # Power Management
-obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
+obj-$(CONFIG_PM) += pm.o sleep.o
+
+# Clock framework
+obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
 
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 64235dee5614..1c12d7c6c7fc 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,7 +33,6 @@
 #include <asm/arch/board.h>
 #include <asm/arch/common.h>
 #include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
 
 #include <asm/io.h>
 
@@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void)
         int eth_cs;
         unsigned long cs_mem_base;
         unsigned int rate;
-        struct clk *l3ck;
+        struct clk *gpmc_fck;
 
         eth_cs = SDP2430_SMC91X_CS;
 
-        l3ck = clk_get(NULL, "core_l3_ck");
-        if (IS_ERR(l3ck))
-                rate = 100000000;
-        else
-                rate = clk_get_rate(l3ck);
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
 
         /* Make sure CS1 timings are correct, for 2430 always muxed */
         gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
@@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void)
 
         if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
                 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
-                return;
+                goto out;
         }
 
         sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
@@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void)
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         OMAP24XX_ETHR_GPIO_IRQ);
                 gpmc_cs_free(eth_cs);
-                return;
+                goto out;
         }
         omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
 
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
 }
 
 static void __init omap_2430sdp_init_irq(void)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7846551f0575..a1e1e6765b5b 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -26,6 +26,8 @@
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/leds.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -39,7 +41,7 @@
 #include <asm/arch/board.h>
 #include <asm/arch/common.h>
 #include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
+#include <asm/arch/control.h>
 
 /* LED & Switch macros */
 #define LED0_GPIO13             13
@@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void)
 {
         unsigned long base;
 
+        unsigned int rate;
+        struct clk *gpmc_fck;
+        int eth_cs;
+
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
+
+        eth_cs = APOLLON_ETH_CS;
+
         /* Make sure CS1 timings are correct */
-        GPMC_CONFIG1_1 = 0x00011203;
-        GPMC_CONFIG2_1 = 0x001f1f01;
-        GPMC_CONFIG3_1 = 0x00080803;
-        GPMC_CONFIG4_1 = 0x1c091c09;
-        GPMC_CONFIG5_1 = 0x041f1f1f;
-        GPMC_CONFIG6_1 = 0x000004c4;
+        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
+
+        if (rate >= 160000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else if (rate >= 130000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else {/* rate = 100000000 */
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+        }
 
         if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
                 printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
-                return;
+                goto out;
         }
         apollon_smc91x_resources[0].start = base + 0x300;
         apollon_smc91x_resources[0].end   = base + 0x30f;
@@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void)
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         APOLLON_ETHR_GPIO_IRQ);
                 gpmc_cs_free(APOLLON_ETH_CS);
-                return;
+                goto out;
         }
         omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
+
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
 }
 
 static void __init omap_apollon_init_irq(void)
@@ -330,6 +366,8 @@ static void __init apollon_usb_init(void)
 
 static void __init omap_apollon_init(void)
 {
+        u32 v;
+
         apollon_led_init();
         apollon_sw_init();
         apollon_flash_init();
@@ -339,7 +377,9 @@ static void __init omap_apollon_init(void)
         omap_cfg_reg(W19_24XX_SYS_NIRQ);
 
         /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
-        CONTROL_DEVCONF |= (1 << 24);
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        v |= (1 << 24);
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 
         /*
          * Make sure the serial ports are muxed on at this point.
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f125f432cc3e..d1915f99a5fa 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,8 @@
 #include <linux/delay.h>
 #include <linux/workqueue.h>
 #include <linux/input.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -26,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/gpioexpander.h>
 #include <asm/arch/mux.h>
@@ -36,10 +39,13 @@
 #include <asm/arch/keypad.h>
 #include <asm/arch/menelaus.h>
 #include <asm/arch/dma.h>
-#include "prcm-regs.h"
+#include <asm/arch/gpmc.h>
 
 #include <asm/io.h>
 
+#define H4_FLASH_CS     0
+#define H4_SMC91X_CS    1
+
 static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
 static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
 
@@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = {
 };
 
 static struct resource h4_flash_resource = {
-        .start          = H4_CS0_BASE,
-        .end            = H4_CS0_BASE + SZ_64M - 1,
         .flags          = IORESOURCE_MEM,
 };
 
@@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = {
         &h4_lcd_device,
 };
 
+/* 2420 Sysboot setup (2430 is different) */
+static u32 get_sysboot_value(void)
+{
+        return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
+                (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
+                 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
+                 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
+}
+
+/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
+ *
+ * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
+ *  correctly.  The macro needs to look at production_id not just hawkeye.
+ */
+static u32 is_gpmc_muxed(void)
+{
+        u32 mux;
+        mux = get_sysboot_value();
+        if ((mux & 0xF) == 0xd)
+                return 1;       /* NAND config (could be either) */
+        if (mux & 0x2)          /* if mux'ed */
+                return 1;
+        else
+                return 0;
+}
+
 static inline void __init h4_init_debug(void)
 {
+        int eth_cs;
+        unsigned long cs_mem_base;
+        unsigned int muxed, rate;
+        struct clk *gpmc_fck;
+
+        eth_cs  = H4_SMC91X_CS;
+
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
+
+        if (is_gpmc_muxed())
+                muxed = 0x200;
+        else
+                muxed = 0;
+
         /* Make sure CS1 timings are correct */
-        GPMC_CONFIG1_1 = 0x00011200;
-        GPMC_CONFIG2_1 = 0x001f1f01;
-        GPMC_CONFIG3_1 = 0x00080803;
-        GPMC_CONFIG4_1 = 0x1c091c09;
-        GPMC_CONFIG5_1 = 0x041f1f1f;
-        GPMC_CONFIG6_1 = 0x000004c4;
-        GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
+        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
+                          0x00011000 | muxed);
+
+        if (rate >= 160000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else if (rate >= 130000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else {/* rate = 100000000 */
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+        }
+
+        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+                goto out;
+        }
+
         udelay(100);
 
         omap_cfg_reg(M15_24XX_GPIO92);
         if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)
                 gpmc_cs_free(eth_cs);
+
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
+}
+
+static void __init h4_init_flash(void)
+{
+        unsigned long base;
+
+        if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
+                printk("Can't request GPMC CS for flash\n");
+                return;
+        }
+        h4_flash_resource.start = base;
+        h4_flash_resource.end   = base + SZ_64M - 1;
 }
 
 static void __init omap_h4_init_irq(void)
@@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void)
         omap2_init_common_hw();
         omap_init_irq();
         omap_gpio_init();
+        h4_init_flash();
 }
 
 static struct omap_uart_config h4_uart_config __initdata = {
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e6e85b7b097b..b57ffb5a22a5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1,20 +1,19 @@
 /*
  *  linux/arch/arm/mach-omap2/clock.c
  *
- *  Copyright (C) 2005 Texas Instruments Inc.
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Created for OMAP2.
- *
- *  Cleaned up and modified to use omap shared clock framework by
- *  Tony Lindgren <tony@atomide.com>
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
  *
- *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
@@ -22,176 +21,227 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <asm/bitops.h>
 
 #include <asm/io.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
+#include <asm/arch/cpu.h>
 #include <asm/div64.h>
 
-#include "prcm-regs.h"
 #include "memory.h"
+#include "sdrc.h"
 #include "clock.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
 
-#undef DEBUG
-
-//#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
+#define MAX_CLOCK_ENABLE_WAIT           100000
 
-static struct prcm_config *curr_prcm_set;
-static u32 curr_perf_level = PRCM_FULL_SPEED;
-static struct clk *vclk;
-static struct clk *sclk;
+u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
  * Omap2 specific clock functions
  *-------------------------------------------------------------------------*/
 
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk * clk)
+/**
+ * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
+ * @clk: OMAP clock struct ptr to use
+ *
+ * Given a pointer to a source-selectable struct clk, read the hardware
+ * register and determine what its parent is currently set to.  Update the
+ * clk->parent field with the appropriate clk ptr.
+ */
+void omap2_init_clksel_parent(struct clk *clk)
 {
-        u32 div = PRCM_CLKSRC_CTRL;
-        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
-        div >>= clk->rate_offset;
-        clk->rate = (clk->parent->rate / div);
-        propagate_rate(clk);
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 r, found = 0;
+
+        if (!clk->clksel)
+                return;
+
+        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        r >>= __ffs(clk->clksel_mask);
+
+        for (clks = clk->clksel; clks->parent && !found; clks++) {
+                for (clkr = clks->rates; clkr->div && !found; clkr++) {
+                        if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
+                                if (clk->parent != clks->parent) {
+                                        pr_debug("clock: inited %s parent "
+                                                 "to %s (was %s)\n",
+                                                 clk->name, clks->parent->name,
+                                                 ((clk->parent) ?
+                                                  clk->parent->name : "NULL"));
+                                        clk->parent = clks->parent;
+                                };
+                                found = 1;
+                        }
+                }
+        }
+
+        if (!found)
+                printk(KERN_ERR "clock: init parent: could not find "
+                       "regval %0x for clock %s\n", r,  clk->name);
+
+        return;
 }
 
-static u32 omap2_get_dpll_rate(struct clk * tclk)
+/* Returns the DPLL rate */
+u32 omap2_get_dpll_rate(struct clk *clk)
 {
         long long dpll_clk;
-        int dpll_mult, dpll_div, amult;
+        u32 dpll_mult, dpll_div, dpll;
+        const struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        /* REVISIT: What do we return on error? */
+        if (!dd)
+                return 0;
+
+        dpll = __raw_readl(dd->mult_div1_reg);
+        dpll_mult = dpll & dd->mult_mask;
+        dpll_mult >>= __ffs(dd->mult_mask);
+        dpll_div = dpll & dd->div1_mask;
+        dpll_div >>= __ffs(dd->div1_mask);
 
-        dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff;    /* 10 bits */
-        dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f;        /* 4 bits */
-        dpll_clk = (long long)tclk->parent->rate * dpll_mult;
+        dpll_clk = (long long)clk->parent->rate * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
-        amult = CM_CLKSEL2_PLL & 0x3;
-        dpll_clk *= amult;
 
         return dpll_clk;
 }
 
-static void omap2_followparent_recalc(struct clk *clk)
-{
-        followparent_recalc(clk);
-}
-
-static void omap2_propagate_rate(struct clk * clk)
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+void omap2_fixed_divisor_recalc(struct clk *clk)
 {
-        if (!(clk->flags & RATE_FIXED))
-                clk->rate = clk->parent->rate;
+        WARN_ON(!clk->fixed_div);
 
-        propagate_rate(clk);
-}
+        clk->rate = clk->parent->rate / clk->fixed_div;
 
-static void omap2_set_osc_ck(int enable)
-{
-        if (enable)
-                PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
-        else
-                PRCM_CLKSRC_CTRL |= 0x3 << 3;
+        if (clk->flags & RATE_PROPAGATES)
+                propagate_rate(clk);
 }
 
-/* Enable an APLL if off */
-static void omap2_clk_fixed_enable(struct clk *clk)
+/**
+ * omap2_wait_clock_ready - wait for clock to enable
+ * @reg: physical address of clock IDLEST register
+ * @mask: value to mask against to determine if the clock is active
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the clock enabled in time, or 0 if it failed to enable
+ * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
+ */
+int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 {
-        u32 cval, i=0;
+        int i = 0;
+        int ena = 0;
 
-        if (clk->enable_bit == 0xff)                    /* Parent will do it */
-                return;
+        /*
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         */
+        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
+                ena = mask;
+        } else if (cpu_mask & RATE_IN_343X) {
+                ena = 0;
+        }
 
-        cval = CM_CLKEN_PLL;
+        /* Wait for lock */
+        while (((__raw_readl(reg) & mask) != ena) &&
+               (i++ < MAX_CLOCK_ENABLE_WAIT)) {
+                udelay(1);
+        }
 
-        if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
-                return;
+        if (i < MAX_CLOCK_ENABLE_WAIT)
+                pr_debug("Clock %s stable after %d loops\n", name, i);
+        else
+                printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
+                       name, MAX_CLOCK_ENABLE_WAIT);
 
-        cval &= ~(0x3 << clk->enable_bit);
-        cval |= (0x3 << clk->enable_bit);
-        CM_CLKEN_PLL = cval;
 
-        if (clk == &apll96_ck)
-                cval = (1 << 8);
-        else if (clk == &apll54_ck)
-                cval = (1 << 6);
+        return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
+};
 
-        while (!(CM_IDLEST_CKGEN & cval)) {             /* Wait for lock */
-                ++i;
-                udelay(1);
-                if (i == 100000) {
-                        printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
-                        break;
-                }
-        }
-}
 
+/*
+ * Note: We don't need special code here for INVERT_ENABLE
+ * for the time being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL
+ */
 static void omap2_clk_wait_ready(struct clk *clk)
 {
-        unsigned long reg, other_reg, st_reg;
+        void __iomem *reg, *other_reg, *st_reg;
         u32 bit;
-        int i;
-
-        reg = (unsigned long) clk->enable_reg;
-        if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
-            reg == (unsigned long) &CM_FCLKEN2_CORE)
-                other_reg = (reg & ~0xf0) | 0x10;
-        else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
-                 reg == (unsigned long) &CM_ICLKEN2_CORE)
-                other_reg = (reg & ~0xf0) | 0x00;
+
+        /*
+         * REVISIT: This code is pretty ugly.  It would be nice to generalize
+         * it and pull it into struct clk itself somehow.
+         */
+        reg = clk->enable_reg;
+        if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
+            (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
+                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
+        else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
+                 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
+                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
         else
                 return;
 
+        /* REVISIT: What are the appropriate exclusions for 34XX? */
         /* No check for DSS or cam clocks */
-        if ((reg & 0x0f) == 0) {
-                if (clk->enable_bit <= 1 || clk->enable_bit == 31)
+        if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+                if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
+                    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
+                    clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
                         return;
         }
 
+        /* REVISIT: What are the appropriate exclusions for 34XX? */
+        /* OMAP3: ignore DSS-mod clocks */
+        if (cpu_is_omap34xx() &&
+            (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
+                return;
+
         /* Check if both functional and interface clocks
          * are running. */
         bit = 1 << clk->enable_bit;
         if (!(__raw_readl(other_reg) & bit))
                 return;
-        st_reg = (other_reg & ~0xf0) | 0x20;
-        i = 0;
-        while (!(__raw_readl(st_reg) & bit)) {
-                i++;
-                if (i == 100000) {
-                        printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
-                        break;
-                }
-        }
-        if (i)
-                pr_debug("Clock %s stable after %d loops\n", clk->name, i);
+        st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+
+        omap2_wait_clock_ready(st_reg, bit, clk->name);
 }
 
 /* Enables clock without considering parent dependencies or use count
  * REVISIT: Maybe change this to use clk->enable like on omap1?
  */
-static int _omap2_clk_enable(struct clk * clk)
+int _omap2_clk_enable(struct clk *clk)
 {
         u32 regval32;
 
-        if (clk->flags & ALWAYS_ENABLED)
+        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
                 return 0;
 
-        if (unlikely(clk == &osc_ck)) {
-                omap2_set_osc_ck(1);
-                return 0;
-        }
+        if (clk->enable)
+                return clk->enable(clk);
 
         if (unlikely(clk->enable_reg == 0)) {
                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
                        clk->name);
-                return 0;
-        }
-
-        if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
-                omap2_clk_fixed_enable(clk);
-                return 0;
+                return 0; /* REVISIT: -EINVAL */
         }
 
         regval32 = __raw_readl(clk->enable_reg);
-        regval32 |= (1 << clk->enable_bit);
+        if (clk->flags & INVERT_ENABLE)
+                regval32 &= ~(1 << clk->enable_bit);
+        else
+                regval32 |= (1 << clk->enable_bit);
         __raw_writel(regval32, clk->enable_reg);
         wmb();
 
@@ -200,44 +250,48 @@ static int _omap2_clk_enable(struct clk * clk)
         return 0;
 }
 
-/* Stop APLL */
-static void omap2_clk_fixed_disable(struct clk *clk)
-{
-        u32 cval;
-
-        if(clk->enable_bit == 0xff)             /* let parent off do it */
-                return;
-
-        cval = CM_CLKEN_PLL;
-        cval &= ~(0x3 << clk->enable_bit);
-        CM_CLKEN_PLL = cval;
-}
-
 /* Disables clock without considering parent dependencies or use count */
-static void _omap2_clk_disable(struct clk *clk)
+void _omap2_clk_disable(struct clk *clk)
 {
         u32 regval32;
 
-        if (unlikely(clk == &osc_ck)) {
-                omap2_set_osc_ck(0);
+        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
                 return;
-        }
 
-        if (clk->enable_reg == 0)
+        if (clk->disable) {
+                clk->disable(clk);
                 return;
+        }
 
-        if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
-                omap2_clk_fixed_disable(clk);
+        if (clk->enable_reg == 0) {
+                /*
+                 * 'Independent' here refers to a clock which is not
+                 * controlled by its parent.
+                 */
+                printk(KERN_ERR "clock: clk_disable called on independent "
+                       "clock %s which has no enable_reg\n", clk->name);
                 return;
         }
 
         regval32 = __raw_readl(clk->enable_reg);
-        regval32 &= ~(1 << clk->enable_bit);
+        if (clk->flags & INVERT_ENABLE)
+                regval32 |= (1 << clk->enable_bit);
+        else
+                regval32 &= ~(1 << clk->enable_bit);
         __raw_writel(regval32, clk->enable_reg);
         wmb();
 }
 
-static int omap2_clk_enable(struct clk *clk)
+void omap2_clk_disable(struct clk *clk)
+{
+        if (clk->usecount > 0 && !(--clk->usecount)) {
+                _omap2_clk_disable(clk);
+                if (likely((u32)clk->parent))
+                        omap2_clk_disable(clk->parent);
+        }
+}
+
+int omap2_clk_enable(struct clk *clk)
 {
         int ret = 0;
 
@@ -261,519 +315,314 @@ static int omap2_clk_enable(struct clk *clk)
         return ret;
 }
 
-static void omap2_clk_disable(struct clk *clk)
-{
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                _omap2_clk_disable(clk);
-                if (likely((u32)clk->parent))
-                        omap2_clk_disable(clk->parent);
-        }
-}
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static u32 omap2_dpll_round_rate(unsigned long target_rate)
-{
-        u32 high, low;
-
-        if ((CM_CLKSEL2_PLL & 0x3) == 1) {      /* DPLL clockout */
-                high = curr_prcm_set->dpll_speed * 2;
-                low = curr_prcm_set->dpll_speed;
-        } else {                                /* DPLL clockout x 2 */
-                high = curr_prcm_set->dpll_speed;
-                low = curr_prcm_set->dpll_speed / 2;
-        }
-
-#ifdef DOWN_VARIABLE_DPLL
-        if (target_rate > high)
-                return high;
-        else
-                return target_rate;
-#else
-        if (target_rate > low)
-                return high;
-        else
-                return low;
-#endif
-
-}
-
 /*
  * Used for clocks that are part of CLKSEL_xyz governed clocks.
  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
  */
-static void omap2_clksel_recalc(struct clk * clk)
+void omap2_clksel_recalc(struct clk *clk)
 {
-        u32 fixed = 0, div = 0;
+        u32 div = 0;
 
-        if (clk == &dpll_ck) {
-                clk->rate = omap2_get_dpll_rate(clk);
-                fixed = 1;
-                div = 0;
-        }
+        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
 
-        if (clk == &iva1_mpu_int_ifck) {
-                div = 2;
-                fixed = 1;
-        }
-
-        if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
-                clk->rate = sys_ck.rate;
+        div = omap2_clksel_get_divisor(clk);
+        if (div == 0)
                 return;
-        }
 
-        if (!fixed) {
-                div = omap2_clksel_get_divisor(clk);
-                if (div == 0)
-                        return;
-        }
+        if (unlikely(clk->rate == clk->parent->rate / div))
+                return;
+        clk->rate = clk->parent->rate / div;
 
-        if (div != 0) {
-                if (unlikely(clk->rate == clk->parent->rate / div))
-                        return;
-                clk->rate = clk->parent->rate / div;
-        }
+        pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
 
         if (unlikely(clk->flags & RATE_PROPAGATES))
                 propagate_rate(clk);
 }
 
-/*
- * Finds best divider value in an array based on the source and target
- * rates. The divider array must be sorted with smallest divider first.
+/**
+ * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
+ * @clk: OMAP struct clk ptr to inspect
+ * @src_clk: OMAP struct clk ptr of the parent clk to search for
+ *
+ * Scan the struct clksel array associated with the clock to find
+ * the element associated with the supplied parent clock address.
+ * Returns a pointer to the struct clksel on success or NULL on error.
  */
-static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
-                                           u32 src_rate, u32 tgt_rate)
+const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
+                                                struct clk *src_clk)
 {
-        int i, test_rate;
+        const struct clksel *clks;
 
-        if (div_array == NULL)
-                return ~1;
+        if (!clk->clksel)
+                return NULL;
 
-        for (i=0; i < size; i++) {
-                test_rate = src_rate / *div_array;
-                if (test_rate <= tgt_rate)
-                        return *div_array;
-                ++div_array;
+        for (clks = clk->clksel; clks->parent; clks++) {
+                if (clks->parent == src_clk)
+                        break; /* Found the requested parent */
         }
 
-        return ~0;      /* No acceptable divider */
+        if (!clks->parent) {
+                printk(KERN_ERR "clock: Could not find parent clock %s in "
+                       "clksel array of clock %s\n", src_clk->name,
+                       clk->name);
+                return NULL;
+        }
+
+        return clks;
 }
 
-/*
- * Find divisor for the given clock and target rate.
+/**
+ * omap2_clksel_round_rate_div - find divisor for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ * @new_div: ptr to where we should store the divisor
  *
+ * Finds 'best' divider value in an array based on the source and target
+ * rates.  The divider array must be sorted with smallest divider first.
  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
  * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
-        u32 *new_div)
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+                                u32 *new_div)
 {
-        u32 gfx_div[] = {2, 3, 4};
-        u32 sysclkout_div[] = {1, 2, 4, 8, 16};
-        u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
-        u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
-        u32 best_div = ~0, asize = 0;
-        u32 *div_array = NULL;
-
-        switch (tclk->flags & SRC_RATE_SEL_MASK) {
-        case CM_GFX_SEL1:
-                asize = 3;
-                div_array = gfx_div;
-                break;
-        case CM_PLL_SEL1:
-                return omap2_dpll_round_rate(target_rate);
-        case CM_SYSCLKOUT_SEL1:
-                asize = 5;
-                div_array = sysclkout_div;
-                break;
-        case CM_CORE_SEL1:
-                if(tclk == &dss1_fck){
-                        if(tclk->parent == &core_ck){
-                                asize = 10;
-                                div_array = dss1_div;
-                        } else {
-                                *new_div = 0; /* fixed clk */
-                                return(tclk->parent->rate);
-                        }
-                } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
-                        if(tclk->parent == &core_ck){
-                                asize = 10;
-                                div_array = vylnq_div;
-                        } else {
-                                *new_div = 0; /* fixed clk */
-                                return(tclk->parent->rate);
-                        }
-                }
-                break;
+        unsigned long test_rate;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 last_div = 0;
+
+        printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
+               clk->name, target_rate);
+
+        *new_div = 1;
+
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
+                return ~0;
+
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (!(clkr->flags & cpu_mask))
+                    continue;
+
+                /* Sanity check */
+                if (clkr->div <= last_div)
+                        printk(KERN_ERR "clock: clksel_rate table not sorted "
+                               "for clock %s", clk->name);
+
+                last_div = clkr->div;
+
+                test_rate = clk->parent->rate / clkr->div;
+
+                if (test_rate <= target_rate)
+                        break; /* found it */
         }
 
-        best_div = omap2_divider_from_table(asize, div_array,
-         tclk->parent->rate, target_rate);
-        if (best_div == ~0){
-                *new_div = 1;
-                return best_div; /* signal error */
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find divisor for target "
+                       "rate %ld for clock %s parent %s\n", target_rate,
+                       clk->name, clk->parent->name);
+                return ~0;
         }
 
-        *new_div = best_div;
-        return (tclk->parent->rate / best_div);
+        *new_div = clkr->div;
+
+        printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
+               (clk->parent->rate / clkr->div));
+
+        return (clk->parent->rate / clkr->div);
 }
 
-/* Given a clock and a rate apply a clock specific rounding function */
-static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+/**
+ * omap2_clksel_round_rate - find rounded rate for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ *
+ * Compatibility wrapper for OMAP clock framework
+ * Finds best target rate based on the source clock and possible dividers.
+ * rates. The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
 {
-        u32 new_div = 0;
-        int valid_rate;
+        u32 new_div;
 
-        if (clk->flags & RATE_FIXED)
-                return clk->rate;
+        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
+}
 
-        if (clk->flags & RATE_CKCTL) {
-                valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
-                return valid_rate;
-        }
 
+/* Given a clock and a rate apply a clock specific rounding function */
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+{
         if (clk->round_rate != 0)
                 return clk->round_rate(clk, rate);
 
+        if (clk->flags & RATE_FIXED)
+                printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
+                       "on fixed-rate clock %s\n", clk->name);
+
         return clk->rate;
 }
 
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
+/**
+ * omap2_clksel_to_divisor() - turn clksel field value into integer divider
+ * @clk: OMAP struct clk to use
+ * @field_val: register field value to find
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a register field
+ * value to search for, find the corresponding clock divisor.  The register
+ * field value should be pre-masked and shifted down so the LSB is at bit 0
+ * before calling.  Returns 0 on error
  */
-static u32 omap2_dll_force_needed(void)
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
 {
-        u32 dll_state = SDRC_DLLA_CTRL;         /* dlla and dllb are a set */
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-        if ((dll_state & (1 << 2)) == (1 << 2))
-                return 1;
-        else
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
                 return 0;
-}
 
-static u32 omap2_reprogram_sdrc(u32 level, u32 force)
-{
-        u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
-        u32 prev = curr_perf_level, flags;
-
-        if ((curr_perf_level == level) && !force)
-                return prev;
-
-        m_type = omap2_memory_get_type();
-        slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
-        fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
-
-        if (level == PRCM_HALF_SPEED) {
-                local_irq_save(flags);
-                PRCM_VOLTSETUP = 0xffff;
-                omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
-                                          slow_dll_ctrl, m_type);
-                curr_perf_level = PRCM_HALF_SPEED;
-                local_irq_restore(flags);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
+                        break;
         }
-        if (level == PRCM_FULL_SPEED) {
-                local_irq_save(flags);
-                PRCM_VOLTSETUP = 0xffff;
-                omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
-                                          fast_dll_ctrl, m_type);
-                curr_perf_level = PRCM_FULL_SPEED;
-                local_irq_restore(flags);
+
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find fieldval %d for "
+                       "clock %s parent %s\n", field_val, clk->name,
+                       clk->parent->name);
+                return 0;
         }
 
-        return prev;
+        return clkr->div;
 }
 
-static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
+/**
+ * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
+ * @clk: OMAP struct clk to use
+ * @div: integer divisor to search for
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
+ * find the corresponding register field value.  The return register value is
+ * the value before left-shifting.  Returns 0xffffffff on error
+ */
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
 {
-        u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
-        u32 bypass = 0;
-        struct prcm_config tmpset;
-        int ret = -EINVAL;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-        local_irq_save(flags);
-        cur_rate = omap2_get_dpll_rate(&dpll_ck);
-        mult = CM_CLKSEL2_PLL & 0x3;
-
-        if ((rate == (cur_rate / 2)) && (mult == 2)) {
-                omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
-        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
-        } else if (rate != cur_rate) {
-                valid_rate = omap2_dpll_round_rate(rate);
-                if (valid_rate != rate)
-                        goto dpll_exit;
-
-                if ((CM_CLKSEL2_PLL & 0x3) == 1)
-                        low = curr_prcm_set->dpll_speed;
-                else
-                        low = curr_prcm_set->dpll_speed / 2;
-
-                tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
-                tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
-                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
-                tmpset.cm_clksel2_pll &= ~0x3;
-                if (rate > low) {
-                        tmpset.cm_clksel2_pll |= 0x2;
-                        mult = ((rate / 2) / 1000000);
-                        done_rate = PRCM_FULL_SPEED;
-                } else {
-                        tmpset.cm_clksel2_pll |= 0x1;
-                        mult = (rate / 1000000);
-                        done_rate = PRCM_HALF_SPEED;
-                }
-                tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
-
-                /* Worst case */
-                tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
-
-                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
-                        bypass = 1;
+        /* should never happen */
+        WARN_ON(div == 0);
 
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
-
-                /* Force dll lock mode */
-                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
-                               bypass);
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
+                return 0;
 
-                /* Errata: ret dll entry state */
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->div == div))
+                        break;
         }
-        omap2_clksel_recalc(&dpll_ck);
-        ret = 0;
 
-dpll_exit:
-        local_irq_restore(flags);
-        return(ret);
-}
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find divisor %d for "
+                       "clock %s parent %s\n", div, clk->name,
+                       clk->parent->name);
+                return 0;
+        }
 
-/* Just return the MPU speed */
-static void omap2_mpu_recalc(struct clk * clk)
-{
-        clk->rate = curr_prcm_set->mpu_speed;
+        return clkr->val;
 }
 
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
+/**
+ * omap2_get_clksel - find clksel register addr & field mask for a clk
+ * @clk: struct clk to use
+ * @field_mask: ptr to u32 to store the register field mask
  *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
+ * Returns the address of the clksel register upon success or NULL on error.
  */
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
+void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
 {
-        struct prcm_config * ptr;
-        long highest_rate;
-
-        if (clk != &virt_prcm_set)
-                return -EINVAL;
-
-        highest_rate = -EINVAL;
-
-        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
-                if (ptr->xtal_speed != sys_ck.rate)
-                        continue;
+        if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
+                return NULL;
 
-                highest_rate = ptr->mpu_speed;
+        *field_mask = clk->clksel_mask;
 
-                /* Can check only after xtal frequency check */
-                if (ptr->mpu_speed <= rate)
-                        break;
-        }
-        return highest_rate;
+        return clk->clksel_reg;
 }
 
-/*
- * omap2_convert_field_to_div() - turn field value into integer divider
+/**
+ * omap2_clksel_get_divisor - get current divider applied to parent clock.
+ * @clk: OMAP struct clk to use.
+ *
+ * Returns the integer divisor upon success or 0 on error.
  */
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
+u32 omap2_clksel_get_divisor(struct clk *clk)
 {
-        u32 i;
-        u32 clkout_array[] = {1, 2, 4, 8, 16};
+        u32 field_mask, field_val;
+        void __iomem *div_addr;
 
-        if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
-                for (i = 0; i < 5; i++) {
-                        if (field_val == i)
-                                return clkout_array[i];
-                }
-                return ~0;
-        } else
-                return field_val;
+        div_addr = omap2_get_clksel(clk, &field_mask);
+        if (div_addr == 0)
+                return 0;
+
+        field_val = __raw_readl(div_addr) & field_mask;
+        field_val >>= __ffs(field_mask);
+
+        return omap2_clksel_to_divisor(clk, field_val);
 }
 
-/*
- * Returns the CLKSEL divider register value
- * REVISIT: This should be cleaned up to work nicely with void __iomem *
- */
-static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
-                            struct clk *clk)
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
-        int ret = ~0;
-        u32 reg_val, div_off;
-        u32 div_addr = 0;
-        u32 mask = ~0;
-
-        div_off = clk->rate_offset;
-
-        switch ((*div_sel & SRC_RATE_SEL_MASK)) {
-        case CM_MPU_SEL1:
-                div_addr = (u32)&CM_CLKSEL_MPU;
-                mask = 0x1f;
-                break;
-        case CM_DSP_SEL1:
-                div_addr = (u32)&CM_CLKSEL_DSP;
-                if (cpu_is_omap2420()) {
-                        if ((div_off == 0) || (div_off == 8))
-                                mask = 0x1f;
-                        else if (div_off == 5)
-                                mask = 0x3;
-                } else if (cpu_is_omap2430()) {
-                        if (div_off == 0)
-                                mask = 0x1f;
-                        else if (div_off == 5)
-                                mask = 0x3;
-                }
-                break;
-        case CM_GFX_SEL1:
-                div_addr = (u32)&CM_CLKSEL_GFX;
-                if (div_off == 0)
-                        mask = 0x7;
-                break;
-        case CM_MODEM_SEL1:
-                div_addr = (u32)&CM_CLKSEL_MDM;
-                if (div_off == 0)
-                        mask = 0xf;
-                break;
-        case CM_SYSCLKOUT_SEL1:
-                div_addr = (u32)&PRCM_CLKOUT_CTRL;
-                if ((div_off == 3) || (div_off == 11))
-                        mask= 0x3;
-                break;
-        case CM_CORE_SEL1:
-                div_addr = (u32)&CM_CLKSEL1_CORE;
-                switch (div_off) {
-                case 0:                                 /* l3 */
-                case 8:                                 /* dss1 */
-                case 15:                                /* vylnc-2420 */
-                case 20:                                /* ssi */
-                        mask = 0x1f; break;
-                case 5:                                 /* l4 */
-                        mask = 0x3; break;
-                case 13:                                /* dss2 */
-                        mask = 0x1; break;
-                case 25:                                /* usb */
-                        mask = 0x7; break;
-                }
-        }
+        u32 field_mask, field_val, reg_val, validrate, new_div = 0;
+        void __iomem *div_addr;
 
-        *field_mask = mask;
+        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+        if (validrate != rate)
+                return -EINVAL;
 
-        if (unlikely(mask == ~0))
-                div_addr = 0;
+        div_addr = omap2_get_clksel(clk, &field_mask);
+        if (div_addr == 0)
+                return -EINVAL;
 
-        *div_sel = div_addr;
+        field_val = omap2_divisor_to_clksel(clk, new_div);
+        if (field_val == ~0)
+                return -EINVAL;
 
-        if (unlikely(div_addr == 0))
-                return ret;
+        reg_val = __raw_readl(div_addr);
+        reg_val &= ~field_mask;
+        reg_val |= (field_val << __ffs(field_mask));
+        __raw_writel(reg_val, div_addr);
+        wmb();
 
-        /* Isolate field */
-        reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
+        clk->rate = clk->parent->rate / new_div;
 
-        /* Normalize back to divider value */
-        reg_val >>= div_off;
+        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                wmb();
+        }
 
-        return reg_val;
+        return 0;
 }
 
-/*
- * Return divider to be applied to parent clock.
- * Return 0 on error.
- */
-static u32 omap2_clksel_get_divisor(struct clk *clk)
-{
-        int ret = 0;
-        u32 div, div_sel, div_off, field_mask, field_val;
-
-        /* isolate control register */
-        div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-
-        div_off = clk->rate_offset;
-        field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-        if (div_sel == 0)
-                return ret;
-
-        div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-        div = omap2_clksel_to_divisor(div_sel, field_val);
-
-        return div;
-}
 
 /* Set the clock rate for a clock source */
-static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
-
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         int ret = -EINVAL;
-        void __iomem * reg;
-        u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
-        u32 new_div = 0;
-
-        if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
-                if (clk == &dpll_ck)
-                        return omap2_reprogram_dpll(clk, rate);
-
-                /* Isolate control register */
-                div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-                div_off = clk->rate_offset;
-
-                validrate = omap2_clksel_round_rate(clk, rate, &new_div);
-                if (validrate != rate)
-                        return(ret);
 
-                field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-                if (div_sel == 0)
-                        return ret;
-
-                if (clk->flags & CM_SYSCLKOUT_SEL1) {
-                        switch (new_div) {
-                        case 16:
-                                field_val = 4;
-                                break;
-                        case 8:
-                                field_val = 3;
-                                break;
-                        case 4:
-                                field_val = 2;
-                                break;
-                        case 2:
-                                field_val = 1;
-                                break;
-                        case 1:
-                                field_val = 0;
-                                break;
-                        }
-                } else
-                        field_val = new_div;
+        pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
 
-                reg = (void __iomem *)div_sel;
-
-                reg_val = __raw_readl(reg);
-                reg_val &= ~(field_mask << div_off);
-                reg_val |= (field_val << div_off);
-                __raw_writel(reg_val, reg);
-                wmb();
-                clk->rate = clk->parent->rate / field_val;
+        /* CONFIG_PARTICIPANT clocks are changed only in sets via the
+           rate table mechanism, driven by mpu_speed  */
+        if (clk->flags & CONFIG_PARTICIPANT)
+                return -EINVAL;
 
-                if (clk->flags & DELAYED_APP) {
-                        __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
-                        wmb();
-                }
-                ret = 0;
-        } else if (clk->set_rate != 0)
+        /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
+        if (clk->set_rate != 0)
                 ret = clk->set_rate(clk, rate);
 
         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -782,242 +631,92 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
         return ret;
 }
 
-/* Converts encoded control register address into a full address */
-static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
-                               struct clk *src_clk, u32 *field_mask)
-{
-        u32 val = ~0, src_reg_addr = 0, mask = 0;
-
-        /* Find target control register.*/
-        switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
-        case CM_CORE_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL1_CORE;
-                if (reg_offset == 13) {                 /* DSS2_fclk */
-                        mask = 0x1;
-                        if (src_clk == &sys_ck)
-                                val = 0;
-                        if (src_clk == &func_48m_ck)
-                                val = 1;
-                } else if (reg_offset == 8) {           /* DSS1_fclk */
-                        mask = 0x1f;
-                        if (src_clk == &sys_ck)
-                                val = 0;
-                        else if (src_clk == &core_ck)   /* divided clock */
-                                val = 0x10;             /* rate needs fixing */
-                } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
-                        mask = 0x1F;
-                        if(src_clk == &func_96m_ck)
-                                val = 0;
-                        else if (src_clk == &core_ck)
-                                val = 0x10;
-                }
-                break;
-        case CM_CORE_SEL2:
-                src_reg_addr = (u32)&CM_CLKSEL2_CORE;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &sys_ck)
-                        val = 0x1;
-                if (src_clk == &alt_ck)
-                        val = 0x2;
-                break;
-        case CM_WKUP_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL_WKUP;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &sys_ck)
-                        val = 0x1;
-                if (src_clk == &alt_ck)
-                        val = 0x2;
-                break;
-        case CM_PLL_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL1_PLL;
-                mask = 0x1;
-                if (reg_offset == 0x3) {
-                        if (src_clk == &apll96_ck)
-                                val = 0;
-                        if (src_clk == &alt_ck)
-                                val = 1;
-                }
-                else if (reg_offset == 0x5) {
-                        if (src_clk == &apll54_ck)
-                                val = 0;
-                        if (src_clk == &alt_ck)
-                                val = 1;
-                }
-                break;
-        case CM_PLL_SEL2:
-                src_reg_addr = (u32)&CM_CLKSEL2_PLL;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &dpll_ck)
-                        val = 0x2;
-                break;
-        case CM_SYSCLKOUT_SEL1:
-                src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
-                mask = 0x3;
-                if (src_clk == &dpll_ck)
-                        val = 0;
-                if (src_clk == &sys_ck)
-                        val = 1;
-                if (src_clk == &func_96m_ck)
-                        val = 2;
-                if (src_clk == &func_54m_ck)
-                        val = 3;
-                break;
-        }
-
-        if (val == ~0)                  /* Catch errors in offset */
-                *type_to_addr = 0;
-        else
-                *type_to_addr = src_reg_addr;
-        *field_mask = mask;
-
-        return val;
-}
-
-static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
+/*
+ * Converts encoded control register address into a full address
+ * On error, *src_addr will be returned as 0.
+ */
+static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
+                                      struct clk *src_clk, u32 *field_mask,
+                                      struct clk *clk, u32 *parent_div)
 {
-        void __iomem * reg;
-        u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
-        int ret = -EINVAL;
-
-        if (unlikely(clk->flags & CONFIG_PARTICIPANT))
-                return ret;
-
-        if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
-                src_sel = (SRC_RATE_SEL_MASK & clk->flags);
-                src_off = clk->src_offset;
-
-                if (src_sel == 0)
-                        goto set_parent_error;
-
-                field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
-                                                &field_mask);
-
-                reg = (void __iomem *)src_sel;
-
-                if (clk->usecount > 0)
-                        _omap2_clk_disable(clk);
-
-                /* Set new source value (previous dividers if any in effect) */
-                reg_val = __raw_readl(reg) & ~(field_mask << src_off);
-                reg_val |= (field_val << src_off);
-                __raw_writel(reg_val, reg);
-                wmb();
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-                if (clk->flags & DELAYED_APP) {
-                        __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
-                        wmb();
-                }
-                if (clk->usecount > 0)
-                        _omap2_clk_enable(clk);
-
-                clk->parent = new_parent;
+        *parent_div = 0;
+        *src_addr = 0;
 
-                /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
-                if ((new_parent == &core_ck) && (clk == &dss1_fck))
-                        clk->rate = new_parent->rate / 0x10;
-                else
-                        clk->rate = new_parent->rate;
+        clks = omap2_get_clksel_by_parent(clk, src_clk);
+        if (clks == NULL)
+                return 0;
 
-                if (unlikely(clk->flags & RATE_PROPAGATES))
-                        propagate_rate(clk);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (clkr->flags & (cpu_mask | DEFAULT_RATE))
+                        break; /* Found the default rate for this platform */
+        }
 
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find default rate for "
+                       "clock %s parent %s\n", clk->name,
+                       src_clk->parent->name);
                 return 0;
-        } else {
-                clk->parent = new_parent;
-                rate = new_parent->rate;
-                omap2_clk_set_rate(clk, rate);
-                ret = 0;
         }
 
- set_parent_error:
-        return ret;
+        /* Should never happen.  Add a clksel mask to the struct clk. */
+        WARN_ON(clk->clksel_mask == 0);
+
+        *field_mask = clk->clksel_mask;
+        *src_addr = clk->clksel_reg;
+        *parent_div = clkr->div;
+
+        return clkr->val;
 }
 
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-        u32 flags, cur_rate, done_rate, bypass = 0;
-        u8 cpu_mask = 0;
-        struct prcm_config *prcm;
-        unsigned long found_speed = 0;
+        void __iomem *src_addr;
+        u32 field_val, field_mask, reg_val, parent_div;
 
-        if (clk != &virt_prcm_set)
+        if (unlikely(clk->flags & CONFIG_PARTICIPANT))
                 return -EINVAL;
 
-        /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
-        if (cpu_is_omap2420())
-                cpu_mask = RATE_IN_242X;
-        else if (cpu_is_omap2430())
-                cpu_mask = RATE_IN_243X;
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-
-                if (prcm->mpu_speed <= rate) {
-                        found_speed = prcm->mpu_speed;
-                        break;
-                }
-        }
-
-        if (!found_speed) {
-                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
-         rate / 1000000);
+        if (!clk->clksel)
                 return -EINVAL;
-        }
-
-        curr_prcm_set = prcm;
-        cur_rate = omap2_get_dpll_rate(&dpll_ck);
-
-        if (prcm->dpll_speed == cur_rate / 2) {
-                omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
-        } else if (prcm->dpll_speed == cur_rate * 2) {
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
-        } else if (prcm->dpll_speed != cur_rate) {
-                local_irq_save(flags);
 
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        bypass = 1;
+        field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
+                                               &field_mask, clk, &parent_div);
+        if (src_addr == 0)
+                return -EINVAL;
 
-                if ((prcm->cm_clksel2_pll & 0x3) == 2)
-                        done_rate = PRCM_FULL_SPEED;
-                else
-                        done_rate = PRCM_HALF_SPEED;
+        if (clk->usecount > 0)
+                _omap2_clk_disable(clk);
 
-                /* MPU divider */
-                CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
+        /* Set new source value (previous dividers if any in effect) */
+        reg_val = __raw_readl(src_addr) & ~field_mask;
+        reg_val |= (field_val << __ffs(field_mask));
+        __raw_writel(reg_val, src_addr);
+        wmb();
 
-                /* dsp + iva1 div(2420), iva2.1(2430) */
-                CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
+        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                wmb();
+        }
 
-                CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
+        if (clk->usecount > 0)
+                _omap2_clk_enable(clk);
 
-                /* Major subsystem dividers */
-                CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
-                if (cpu_is_omap2430())
-                        CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
+        clk->parent = new_parent;
 
-                /* x2 to enter init_mem */
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
+        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
+        clk->rate = new_parent->rate;
 
-                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
-                               bypass);
+        if (parent_div > 0)
+                clk->rate /= parent_div;
 
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+                 clk->name, clk->parent->name, clk->rate);
 
-                local_irq_restore(flags);
-        }
-        omap2_clksel_recalc(&dpll_ck);
+        if (unlikely(clk->flags & RATE_PROPAGATES))
+                propagate_rate(clk);
 
         return 0;
 }
@@ -1027,150 +726,17 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
  *-------------------------------------------------------------------------*/
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
-static void __init omap2_clk_disable_unused(struct clk *clk)
+void omap2_clk_disable_unused(struct clk *clk)
 {
-        u32 regval32;
+        u32 regval32, v;
+
+        v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
 
         regval32 = __raw_readl(clk->enable_reg);
-        if ((regval32 & (1 << clk->enable_bit)) == 0)
+        if ((regval32 & (1 << clk->enable_bit)) == v)
                 return;
 
         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
         _omap2_clk_disable(clk);
 }
-#else
-#define omap2_clk_disable_unused        NULL
 #endif
-
-static struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-};
-
-static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
-{
-        u32 div, aplls, sclk = 13000000;
-
-        aplls = CM_CLKSEL1_PLL;
-        aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
-        aplls >>= 23;                   /* Isolate field, 0,2,3 */
-
-        if (aplls == 0)
-                sclk = 19200000;
-        else if (aplls == 2)
-                sclk = 13000000;
-        else if (aplls == 3)
-                sclk = 12000000;
-
-        div = PRCM_CLKSRC_CTRL;
-        div &= ((1 << 7) | (1 << 6));
-        div >>= sys->rate_offset;
-
-        osc->rate = sclk * div;
-        sys->rate = sclk;
-}
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
-        u32 rate;
-
-        if (vclk == NULL || sclk == NULL)
-                return;
-
-        rate = clk_get_rate(sclk);
-        clk_set_rate(vclk, rate);
-}
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap2_clk_arch_init(void)
-{
-        if (!mpurate)
-                return -EINVAL;
-
-        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
-                printk(KERN_ERR "Could not find matching MPU rate\n");
-
-        propagate_rate(&osc_ck);                /* update main root fast */
-        propagate_rate(&func_32k_ck);           /* update main root slow */
-
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        return 0;
-}
-arch_initcall(omap2_clk_arch_init);
-
-int __init omap2_clk_init(void)
-{
-        struct prcm_config *prcm;
-        struct clk ** clkp;
-        u32 clkrate;
-
-        clk_init(&omap2_clk_functions);
-        omap2_get_crystal_rate(&osc_ck, &sys_ck);
-
-        for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-             clkp++) {
-
-                if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-
-                if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-        }
-
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                         break;
-        }
-        curr_prcm_set = prcm;
-
-        propagate_rate(&osc_ck);                /* update main root fast */
-        propagate_rate(&func_32k_ck);           /* update main root slow */
-
-        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable(&sync_32k_ick);
-        clk_enable(&omapctrl_ick);
-
-        /* Force the APLLs always active. The clocks are idled
-         * automatically by hardware. */
-        clk_enable(&apll96_ck);
-        clk_enable(&apll54_ck);
-
-        if (cpu_is_omap2430())
-                clk_enable(&sdrc_ick);
-
-        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4f791866b910..d5980a9e09a4 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1,13 +1,12 @@
 /*
- *  linux/arch/arm/mach-omap24xx/clock.h
+ *  linux/arch/arm/mach-omap2/clock.h
  *
- *  Copyright (C) 2005 Texas Instruments Inc.
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Created for OMAP2.
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
  *
- *  Copyright (C) 2004 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,2095 +16,53 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 
-static void omap2_sys_clk_recalc(struct clk * clk);
-static void omap2_clksel_recalc(struct clk * clk);
-static void omap2_followparent_recalc(struct clk * clk);
-static void omap2_propagate_rate(struct clk * clk);
-static void omap2_mpu_recalc(struct clk * clk);
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
-static void omap2_clk_disable(struct clk *clk);
-static void omap2_sys_clk_recalc(struct clk * clk);
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
-static u32 omap2_clksel_get_divisor(struct clk *clk);
-
-
-#define RATE_IN_242X    (1 << 0)
-#define RATE_IN_243X    (1 << 1)
-
-/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- */
-struct prcm_config {
-        unsigned long xtal_speed;       /* crystal rate */
-        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
-        unsigned long mpu_speed;        /* speed of MPU */
-        unsigned long cm_clksel_mpu;    /* mpu divider */
-        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
-        unsigned long cm_clksel_gfx;    /* gfx dividers */
-        unsigned long cm_clksel1_core;  /* major subsystem dividers */
-        unsigned long cm_clksel1_pll;   /* m,n */
-        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
-        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
-        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
-};
-
-/* Mask for clksel which support parent settign in set_rate */
-#define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
-                        CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
-
-/* Mask for clksel regs which support rate operations */
-#define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
-                        CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
-                        CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
-                        CM_SYSCLKOUT_SEL1)
-
-/*
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- */
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1                  (0x10 << 8)
-#define RX_CLKSEL_DSS2                  (0x0 << 13)
-#define RX_CLKSEL_SSI                   (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3                    (4 << 0)
-#define R1_CLKSEL_L4                    (2 << 5)
-#define R1_CLKSEL_USB                   (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU                   (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP                   (2 << 0)
-#define R1_CLKSEL_DSP_IF                (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX                   (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM                   (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3                    (6 << 0)
-#define R2_CLKSEL_L4                    (2 << 5)
-#define R2_CLKSEL_USB                   (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU                   (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP                   (2 << 0)
-#define R2_CLKSEL_DSP_IF                (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX                   (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM                   (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3                    (1 << 0)
-#define RB_CLKSEL_L4                    (1 << 5)
-#define RB_CLKSEL_USB                   (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU                   (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP                   (1 << 0)
-#define RB_CLKSEL_DSP_IF                (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX                   (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM                   (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
-#define RXX_CLKSEL_SSI                  (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
-#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
-#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
-                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
-                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
-                                        RIII_CLKSEL_L3
-#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
-#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
-                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
-                                        RIII_CLKSEL_DSP
-#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
-#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
-#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
-                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
-#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
-#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
-#define RII_CLKSEL_IVA                  (6 << 8)        /* iva1 - 200MHz */
-#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
-                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
-                                        RII_CLKSEL_DSP
-#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3                  (1 << 0)
-#define RVII_CLKSEL_L4                  (1 << 5)
-#define RVII_CLKSEL_DSS1                (1 << 8)
-#define RVII_CLKSEL_DSS2                (0 << 13)
-#define RVII_CLKSEL_VLYNQ               (1 << 15)
-#define RVII_CLKSEL_SSI                 (1 << 20)
-#define RVII_CLKSEL_USB                 (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
-                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
-                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
-
-#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+#include <asm/arch/clock.h>
 
-#define RVII_CLKSEL_DSP                 (1 << 0)
-#define RVII_CLKSEL_DSP_IF              (1 << 5)
-#define RVII_SYNC_DSP                   (0 << 7)
-#define RVII_CLKSEL_IVA                 (1 << 8)
-#define RVII_SYNC_IVA                   (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
-                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
-
-#define RVII_CLKSEL_GFX                 (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC                      (0 << 3)
-#define MX_54M_SRC                      (0 << 5)
-#define MX_APLLS_CLIKIN_12              (3 << 23)
-#define MX_APLLS_CLIKIN_13              (2 << 23)
-#define MX_APLLS_CLIKIN_19_2            (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #2   (ratio1) baseport-target
- * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12                (133 << 12)
-#define M5A_DPLL_DIV_12                 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13                (266 << 12)
-#define M5A_DPLL_DIV_13                 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19                (180 << 12)
-#define M5A_DPLL_DIV_19                 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12                (50 << 12)
-#define M5B_DPLL_DIV_12                 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13                (200 << 12)
-#define M5B_DPLL_DIV_13                 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19                (125 << 12)
-#define M5B_DPLL_DIV_19                 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/*
- * #4   (ratio2)
- * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12                 (55 << 12)
-#define M3_DPLL_DIV_12                  (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13                 (330 << 12)
-#define M3_DPLL_DIV_13                  (12 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19                 (275 << 12)
-#define M3_DPLL_DIV_19                  (15 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* boot (boot) */
-#define MB_DPLL_MULT                    (1 << 12)
-#define MB_DPLL_DIV                     (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12                (50 << 12)
-#define MII_DPLL_DIV_12                 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MII_DPLL_MULT_13                (300 << 12)
-#define MII_DPLL_DIV_13                 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12               (133 << 12)
-#define MIII_DPLL_DIV_12                (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MIII_DPLL_MULT_13               (266 << 12)
-#define MIII_DPLL_DIV_13                (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
-
-/*
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
-#define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
-#define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
-#define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
-
-/* MPU speed defines */
-#define S12M    12000000
-#define S13M    13000000
-#define S19M    19200000
-#define S26M    26000000
-#define S100M   100000000
-#define S133M   133000000
-#define S150M   150000000
-#define S165M   165000000
-#define S200M   200000000
-#define S266M   266000000
-#define S300M   300000000
-#define S330M   330000000
-#define S400M   400000000
-#define S532M   532000000
-#define S600M   600000000
-#define S660M   660000000
-
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used.    Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set.    The exception is the bypass setting which is
- * availble for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
-static struct prcm_config rate_table[] = {
-        /* PRCM II - FAST */
-        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - FAST */
-        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM II - SLOW */
-        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - SLOW */
-        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM #3 - ratio2 (ES2) - FAST */
-        {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_110MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - FAST */
-        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - FAST */
-        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM #3 - ratio2 (ES2) - SLOW */
-        {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_110MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - SLOW */
-        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - SLOW*/
-        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
-
-/*-------------------------------------------------------------------------
- * 24xx clock tree.
- *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- *      cases the parent is selectable. The get/set parent calls will also
- *      switch sources.
- *
- *      Many some clocks say always_enabled, but they can be auto idled for
- *      power savings. They will always be available upon clock request.
- *
- *      Several sources are given initial rates which may be wrong, this will
- *      be fixed up in the init func.
- *
- *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most periferals have dependencies on multiple clock
- *      domains. Many get their interface clocks from the L4 domain, but get
- *      functional clocks from fixed sources or other core domain derived
- *      clocks.
- *-------------------------------------------------------------------------*/
-
-/* Base external input clocks */
-static struct clk func_32k_ck = {
-        .name           = "func_32k_ck",
-        .rate           = 32000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED,
-};
-
-/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
-static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
-        .name           = "osc_ck",
-        .rate           = 26000000,             /* fixed up in clock init */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-};
-
-/* With out modem likely 12MHz, with modem likely 13MHz */
-static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
-        .name           = "sys_ck",             /* ~ ref_clk also */
-        .parent         = &osc_ck,
-        .rate           = 13000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-        .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
-        .recalc         = &omap2_sys_clk_recalc,
-};
-
-static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
-        .name           = "alt_ck",
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-};
-
-/*
- * Analog domain root source clocks
- */
-
-/* dpll_ck, is broken out in to special cases through clksel */
-static struct clk dpll_ck = {
-        .name           = "dpll_ck",
-        .parent         = &sys_ck,              /* Can be func_32k also */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk apll96_ck = {
-        .name           = "apll96_ck",
-        .parent         = &sys_ck,
-        .rate           = 96000000,
-        .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0x2,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk apll54_ck = {
-        .name           = "apll54_ck",
-        .parent         = &sys_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0x6,
-        .recalc         = &omap2_propagate_rate,
-};
+int omap2_clk_enable(struct clk *clk);
+void omap2_clk_disable(struct clk *clk);
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
 
-/*
- * PRCM digital base sources
- */
-static struct clk func_54m_ck = {
-        .name           = "func_54m_ck",
-        .parent         = &apll54_ck,   /* can also be alt_clk */
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-        .src_offset     = 5,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .parent         = &dpll_ck,             /* can also be 32k */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk sleep_ck = {          /* sys_clk or 32k */
-        .name           = "sleep_ck",
-        .parent         = &func_32k_ck,
-        .rate           = 32000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_96m_ck = {
-        .name           = "func_96m_ck",
-        .parent         = &apll96_ck,
-        .rate           = 96000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_48m_ck = {
-        .name           = "func_48m_ck",
-        .parent         = &apll96_ck,    /* 96M or Alt */
-        .rate           = 48000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-        .src_offset     = 3,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_12m_ck = {
-        .name           = "func_12m_ck",
-        .parent         = &func_48m_ck,
-        .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-};
-
-/* Secure timer, only available in secure mode */
-static struct clk wdt1_osc_ck = {
-        .name           = "ck_wdt1_osc",
-        .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sys_clkout = {
-        .name           = "sys_clkout",
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-        .src_offset     = 0,
-        .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
-        .enable_bit     = 7,
-        .rate_offset    = 3,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2 = {
-        .name           = "sys_clkout2",
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-        .src_offset     = 8,
-        .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
-        .enable_bit     = 15,
-        .rate_offset    = 11,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk emul_ck = {
-        .name           = "emul_ck",
-        .parent         = &func_54m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&PRCM_CLKEMUL_CTRL,
-        .enable_bit     = 0,
-        .recalc         = &omap2_propagate_rate,
-
-};
-
-/*
- * MPU clock domain
- *      Clocks:
- *              MPU_FCLK, MPU_ICLK
- *              INT_M_FCLK, INT_M_I_CLK
- *
- * - Individual clocks are hardware managed.
- * - Base divider comes from: CM_CLKSEL_MPU
- *
- */
-static struct clk mpu_ck = {    /* Control cpu */
-        .name           = "mpu_ck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
-                                ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
-                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
-        .rate_offset    = 0,    /* bits 0-4 */
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
- * Clocks:
- *      2430: IVA2.1_FCLK, IVA2.1_ICLK
- *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
- */
-static struct clk iva2_1_fck = {
-        .name           = "iva2_1_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | RATE_PROPAGATES |
-                                CONFIG_PARTICIPANT,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva2_1_ick = {
-        .name           = "iva2_1_ick",
-        .parent         = &iva2_1_fck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset    = 5,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * Won't be too specific here. The core clock comes into this block
- * it is divided then tee'ed. One branch goes directly to xyz enable
- * controls. The other branch gets further divided by 2 then possibly
- * routed into a synchronizer and out of clocks abc.
- */
-static struct clk dsp_fck = {
-        .name           = "dsp_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
-                        DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dsp_ick = {
-        .name           = "dsp_ick",     /* apparently ipi and isp */
-        .parent         = &dsp_fck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset = 5,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_DSP,
-        .enable_bit     = 1,            /* for ipi */
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva1_ifck = {
-        .name           = "iva1_ifck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
-                        CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
-        .rate_offset= 8,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 10,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* IVA1 mpu/int/i/f clocks are /2 of parent */
-static struct clk iva1_mpu_int_ifck = {
-        .name           = "iva1_mpu_int_ifck",
-        .parent         = &iva1_ifck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 8,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * L3 clock domain
- * L3 clocks are used for both interface and functional clocks to
- * multiple entities. Some of these clocks are completely managed
- * by hardware, and some others allow software control. Hardware
- * managed ones general are based on directly CLK_REQ signals and
- * various auto idle settings. The functional spec sets many of these
- * as 'tie-high' for their enables.
- *
- * I-CLOCKS:
- *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
- *      CAM, HS-USB.
- * F-CLOCK
- *      SSI.
- *
- * GPMC memories and SDRC have timing and clock sensitive registers which
- * may very well need notification when the clock changes. Currently for low
- * operating points, these are taken care of in sleep.S.
- */
-static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
-        .name           = "core_l3_ck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT |
-                                RATE_PROPAGATES,
-        .rate_offset    = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk usb_l4_ick = {        /* FS-USB interface clock */
-        .name           = "usb_l4_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
-                                CONFIG_PARTICIPANT,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 0,
-        .rate_offset = 25,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * SSI is in L3 management domain, its direct parent is core not l3,
- * many core power domain entities are grouped into the L3 clock
- * domain.
- * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
- *
- * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
- */
-static struct clk ssi_ssr_sst_fck = {
-        .name           = "ssi_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,     /* bit 1 */
-        .enable_bit     = 1,
-        .rate_offset = 20,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * GFX clock domain
- *      Clocks:
- * GFX_FCLK, GFX_ICLK
- * GFX_CG1(2d), GFX_CG2(3d)
- *
- * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
- * The 2d and 3d clocks run at a hardware determined
- * divided value of fclk.
- *
- */
-static struct clk gfx_3d_fck = {
-        .name           = "gfx_3d_fck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_GFX_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
-        .enable_bit     = 2,
-        .rate_offset= 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_2d_fck = {
-        .name           = "gfx_2d_fck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_GFX_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
-        .enable_bit     = 1,
-        .rate_offset= 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_ick = {
-        .name           = "gfx_ick",            /* From l3 */
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_GFX,       /* bit 0 */
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * Modem clock domain (2430)
- *      CLOCKS:
- *              MDM_OSC_CLK
- *              MDM_ICLK
- */
-static struct clk mdm_ick = {           /* used both as a ick and fck */
-        .name           = "mdm_ick",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_MDM,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mdm_osc_ck = {
-        .name           = "mdm_osc_ck",
-        .rate           = 26000000,
-        .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_MDM,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * L4 clock management domain
- *
- * This domain contains lots of interface clocks from the L4 interface, some
- * functional clocks.   Fixed APLL functional source clocks are managed in
- * this domain.
- */
-static struct clk l4_ck = {             /* used both as an ick and fck */
-        .name           = "l4_ck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
-                                DELAYED_APP | RATE_PROPAGATES,
-        .rate_offset    = 5,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,     /* bit 1 */
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * DSS clock domain
- * CLOCKs:
- * DSS_L4_ICLK, DSS_L3_ICLK,
- * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
- *
- * DSS is both initiator and target.
- */
-static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
-        .name           = "dss_ick",
-        .parent         = &l4_ck,       /* really both l3 and l4 */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk dss1_fck = {
-        .name           = "dss1_fck",
-        .parent         = &core_ck,             /* Core or sys */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 0,
-        .rate_offset    = 8,
-        .src_offset     = 8,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dss2_fck = {          /* Alt clk used in power management */
-        .name           = "dss2_fck",
-        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
-                                DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 1,
-        .src_offset     = 13,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk dss_54m_fck = {       /* Alt clk used in power management */
-        .name           = "dss_54m_fck",        /* 54m tv clk */
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_propagate_rate,
-};
-
-/*
- * CORE power domain ICLK & FCLK defines.
- * Many of the these can have more than one possible parent. Entries
- * here will likely have an L4 interface parent, and may have multiple
- * functional clock parents.
- */
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,      /* Bit0 */
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_WKUP_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,      /* Bit0 */
-        .enable_bit     = 0,
-        .src_offset     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit4 */
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 4,
-        .src_offset     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit5 */
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 5,
-        .src_offset     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit6 */
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 6,
-        .src_offset     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* Bit7 */
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 7,
-        .src_offset     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 8,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit8 */
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 8,
-        .src_offset     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit9 */
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 9,
-        .src_offset     = 12,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit10 */
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 10,
-        .src_offset     = 14,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 11,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 11,
-        .src_offset     = 16,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 12,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 12,
-        .src_offset     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 13,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 13,
-        .src_offset     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit14 */
-        .enable_bit     = 14,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 14,
-        .src_offset     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 15,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit16 */
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 15,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 16,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 16,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_ick = {
-        .name           = "mcspi_ick",
-        .id             = 1,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_fck = {
-        .name           = "mcspi_fck",
-        .id             = 1,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_ick = {
-        .name           = "mcspi_ick",
-        .id             = 2,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_fck = {
-        .name           = "mcspi_fck",
-        .id             = 2,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_ick = {
-        .name           = "mcspi_ick",
-        .id             = 3,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_fck = {
-        .name           = "mcspi_fck",
-        .id             = 3,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 21,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 21,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_ick = {
-        .name           = "gpios_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_fck = {
-        .name           = "gpios_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_ick = {
-        .name           = "mpu_wdt_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_fck = {
-        .name           = "mpu_wdt_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sync_32k_ick = {
-        .name           = "sync_32k_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk icr_ick = {
-        .name           = "icr_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk cam_ick = {
-        .name           = "cam_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 31,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk cam_fck = {
-        .name           = "cam_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 31,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 30,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_ick = {
-        .name           = "wdt4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 29,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_fck = {
-        .name           = "wdt4_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 29,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_ick = {
-        .name           = "wdt3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 28,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 28,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 27,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 27,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_ick = {
-        .name           = "mmc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 26,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_fck = {
-        .name           = "mmc_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 26,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 25,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk fac_fck = {
-        .name           = "fac_fck",
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 25,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk eac_ick = {
-        .name           = "eac_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 24,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk eac_fck = {
-        .name           = "eac_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 24,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 23,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 23,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_ick = {
-        .name           = "i2c_ick",
-        .id             = 2,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_fck = {
-        .name           = "i2c_fck",
-        .id             = 2,
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs2_fck = {
-        .name           = "i2chs2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_ick = {
-        .name           = "i2c_ick",
-        .id             = 1,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_fck = {
-        .name           = "i2c_fck",
-        .id             = 1,
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs1_fck = {
-        .name           = "i2chs1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_ick = {
-        .name           = "vlynq_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_fck = {
-        .name           = "vlynq_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 3,
-        .src_offset     = 15,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN3_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk des_ick = {
-        .name           = "des_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sha_ick = {
-        .name           = "sha_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk aes_ick = {
-        .name           = "aes_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk usb_fck = {
-        .name           = "usb_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk usbhs_ick = {
-        .name           = "usbhs_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_ick = {
-        .name           = "mmchs1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_fck = {
-        .name           = "mmchs1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_ick = {
-        .name           = "mmchs2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_fck = {
-        .name           = "mmchs2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+void omap2_clk_disable_unused(struct clk *clk);
+#else
+#define omap2_clk_disable_unused        NULL
+#endif
 
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
+void omap2_clksel_recalc(struct clk *clk);
+void omap2_init_clksel_parent(struct clk *clk);
+u32 omap2_clksel_get_divisor(struct clk *clk);
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+                                u32 *new_div);
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
+void omap2_fixed_divisor_recalc(struct clk *clk);
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+u32 omap2_get_dpll_rate(struct clk *clk);
+int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 
-static struct clk gpio5_fck = {
-        .name           = "gpio5_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
+extern u8 cpu_mask;
 
-static struct clk mdm_intc_ick = {
-        .name           = "mdm_intc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 11,
-        .recalc         = &omap2_followparent_recalc,
+/* clksel_rate data common to 24xx/343x */
+static const struct clksel_rate gpt_32k_rates[] = {
+         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
 };
 
-static struct clk mmchsdb1_fck = {
-        .name           = "mmchsdb1_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 16,
-        .recalc         = &omap2_followparent_recalc,
+static const struct clksel_rate gpt_sys_rates[] = {
+         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
 };
 
-static struct clk mmchsdb2_fck = {
-        .name           = "mmchsdb2_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
+static const struct clksel_rate gfx_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 0 }
 };
 
-/*
- * This clock is a composite clock which does entire set changes then
- * forces a rebalance. It keys on the MPU speed, but it really could
- * be any key speed part of a set in the rate table.
- *
- * to really change a set, you need memory table sets which get changed
- * in sram, pre-notifiers & post notifiers, changing the top set, without
- * having low level display recalc's won't work... this is why dpm notifiers
- * work, isr's off, walk a list of clocks already _off_ and not messing with
- * the bus.
- *
- * This clock should have no parent. It embodies the entire upper level
- * active set. A parent will mess up some of the init also.
- */
-static struct clk virt_prcm_set = {
-        .name           = "virt_prcm_set",
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
-        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
-        .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
-        .set_rate       = &omap2_select_table_rate,
-        .round_rate     = &omap2_round_to_table_rate,
-};
-
-static struct clk *onchip_clks[] = {
-        /* external root sources */
-        &func_32k_ck,
-        &osc_ck,
-        &sys_ck,
-        &alt_ck,
-        /* internal analog sources */
-        &dpll_ck,
-        &apll96_ck,
-        &apll54_ck,
-        /* internal prcm root sources */
-        &func_54m_ck,
-        &core_ck,
-        &sleep_ck,
-        &func_96m_ck,
-        &func_48m_ck,
-        &func_12m_ck,
-        &wdt1_osc_ck,
-        &sys_clkout,
-        &sys_clkout2,
-        &emul_ck,
-        /* mpu domain clocks */
-        &mpu_ck,
-        /* dsp domain clocks */
-        &iva2_1_fck,            /* 2430 */
-        &iva2_1_ick,
-        &dsp_ick,               /* 2420 */
-        &dsp_fck,
-        &iva1_ifck,
-        &iva1_mpu_int_ifck,
-        /* GFX domain clocks */
-        &gfx_3d_fck,
-        &gfx_2d_fck,
-        &gfx_ick,
-        /* Modem domain clocks */
-        &mdm_ick,
-        &mdm_osc_ck,
-        /* DSS domain clocks */
-        &dss_ick,
-        &dss1_fck,
-        &dss2_fck,
-        &dss_54m_fck,
-        /* L3 domain clocks */
-        &core_l3_ck,
-        &ssi_ssr_sst_fck,
-        &usb_l4_ick,
-        /* L4 domain clocks */
-        &l4_ck,                 /* used as both core_l4 and wu_l4 */
-        &ssi_l4_ick,
-        /* virtual meta-group clock */
-        &virt_prcm_set,
-        /* general l4 interface ck, multi-parent functional clk */
-        &gpt1_ick,
-        &gpt1_fck,
-        &gpt2_ick,
-        &gpt2_fck,
-        &gpt3_ick,
-        &gpt3_fck,
-        &gpt4_ick,
-        &gpt4_fck,
-        &gpt5_ick,
-        &gpt5_fck,
-        &gpt6_ick,
-        &gpt6_fck,
-        &gpt7_ick,
-        &gpt7_fck,
-        &gpt8_ick,
-        &gpt8_fck,
-        &gpt9_ick,
-        &gpt9_fck,
-        &gpt10_ick,
-        &gpt10_fck,
-        &gpt11_ick,
-        &gpt11_fck,
-        &gpt12_ick,
-        &gpt12_fck,
-        &mcbsp1_ick,
-        &mcbsp1_fck,
-        &mcbsp2_ick,
-        &mcbsp2_fck,
-        &mcbsp3_ick,
-        &mcbsp3_fck,
-        &mcbsp4_ick,
-        &mcbsp4_fck,
-        &mcbsp5_ick,
-        &mcbsp5_fck,
-        &mcspi1_ick,
-        &mcspi1_fck,
-        &mcspi2_ick,
-        &mcspi2_fck,
-        &mcspi3_ick,
-        &mcspi3_fck,
-        &uart1_ick,
-        &uart1_fck,
-        &uart2_ick,
-        &uart2_fck,
-        &uart3_ick,
-        &uart3_fck,
-        &gpios_ick,
-        &gpios_fck,
-        &mpu_wdt_ick,
-        &mpu_wdt_fck,
-        &sync_32k_ick,
-        &wdt1_ick,
-        &omapctrl_ick,
-        &icr_ick,
-        &cam_fck,
-        &cam_ick,
-        &mailboxes_ick,
-        &wdt4_ick,
-        &wdt4_fck,
-        &wdt3_ick,
-        &wdt3_fck,
-        &mspro_ick,
-        &mspro_fck,
-        &mmc_ick,
-        &mmc_fck,
-        &fac_ick,
-        &fac_fck,
-        &eac_ick,
-        &eac_fck,
-        &hdq_ick,
-        &hdq_fck,
-        &i2c1_ick,
-        &i2c1_fck,
-        &i2chs1_fck,
-        &i2c2_ick,
-        &i2c2_fck,
-        &i2chs2_fck,
-        &vlynq_ick,
-        &vlynq_fck,
-        &sdrc_ick,
-        &des_ick,
-        &sha_ick,
-        &rng_ick,
-        &aes_ick,
-        &pka_ick,
-        &usb_fck,
-        &usbhs_ick,
-        &mmchs1_ick,
-        &mmchs1_fck,
-        &mmchs2_ick,
-        &mmchs2_fck,
-        &gpio5_ick,
-        &gpio5_fck,
-        &mdm_intc_ick,
-        &mmchsdb1_fck,
-        &mmchsdb2_fck,
-};
 
 #endif
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
new file mode 100644
index 000000000000..ece32d8acba4
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -0,0 +1,539 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock.c
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ *  Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock24xx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED                 0
+#define EN_APLL_LOCKED                  3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ             0
+#define APLLS_CLKIN_13MHZ               2
+#define APLLS_CLKIN_12MHZ               3
+
+/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
+
+static struct prcm_config *curr_prcm_set;
+static struct clk *vclk;
+static struct clk *sclk;
+
+/*-------------------------------------------------------------------------
+ * Omap24xx specific clock functions
+ *-------------------------------------------------------------------------*/
+
+/* This actually returns the rate of core_ck, not dpll_ck. */
+static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
+{
+        long long dpll_clk;
+        u8 amult;
+
+        dpll_clk = omap2_get_dpll_rate(tclk);
+
+        amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        amult &= OMAP24XX_CORE_CLK_SRC_MASK;
+        dpll_clk *= amult;
+
+        return dpll_clk;
+}
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
+                      OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
+                      OMAP24XX_PRCM_CLKSRC_CTRL);
+}
+
+#ifdef OLD_CK
+/* Recalculate SYST_CLK */
+static void omap2_sys_clk_recalc(struct clk * clk)
+{
+        u32 div = PRCM_CLKSRC_CTRL;
+        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
+        div >>= clk->rate_offset;
+        clk->rate = (clk->parent->rate / div);
+        propagate_rate(clk);
+}
+#endif  /* OLD_CK */
+
+/* Enable an APLL if off */
+static int omap2_clk_fixed_enable(struct clk *clk)
+{
+        u32 cval, apll_mask;
+
+        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+        if ((cval & apll_mask) == apll_mask)
+                return 0;   /* apll already enabled */
+
+        cval &= ~apll_mask;
+        cval |= apll_mask;
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+        if (clk == &apll96_ck)
+                cval = OMAP24XX_ST_96M_APLL;
+        else if (clk == &apll54_ck)
+                cval = OMAP24XX_ST_54M_APLL;
+
+        omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+                            clk->name);
+
+        /*
+         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+         * fails?
+         */
+        return 0;
+}
+
+/* Stop APLL */
+static void omap2_clk_fixed_disable(struct clk *clk)
+{
+        u32 cval;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+static u32 omap2_dpll_round_rate(unsigned long target_rate)
+{
+        u32 high, low, core_clk_src;
+
+        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
+                high = curr_prcm_set->dpll_speed * 2;
+                low = curr_prcm_set->dpll_speed;
+        } else {                                /* DPLL clockout x 2 */
+                high = curr_prcm_set->dpll_speed;
+                low = curr_prcm_set->dpll_speed / 2;
+        }
+
+#ifdef DOWN_VARIABLE_DPLL
+        if (target_rate > high)
+                return high;
+        else
+                return target_rate;
+#else
+        if (target_rate > low)
+                return high;
+        else
+                return low;
+#endif
+
+}
+
+static void omap2_dpll_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_dpll_rate_24xx(clk);
+
+        propagate_rate(clk);
+}
+
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, low, mult, div, valid_rate, done_rate;
+        u32 bypass = 0;
+        struct prcm_config tmpset;
+        const struct dpll_data *dd;
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        local_irq_save(flags);
+        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if ((rate == (cur_rate / 2)) && (mult == 2)) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (rate != cur_rate) {
+                valid_rate = omap2_dpll_round_rate(rate);
+                if (valid_rate != rate)
+                        goto dpll_exit;
+
+                if (mult == 1)
+                        low = curr_prcm_set->dpll_speed;
+                else
+                        low = curr_prcm_set->dpll_speed / 2;
+
+                dd = clk->dpll_data;
+                if (!dd)
+                        goto dpll_exit;
+
+                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+                                           dd->div1_mask);
+                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+                if (rate > low) {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+                        mult = ((rate / 2) / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                } else {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+                        mult = (rate / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL;
+                }
+                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+                /* Worst case */
+                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
+                        bypass = 1;
+
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
+
+                /* Force dll lock mode */
+                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+                               bypass);
+
+                /* Errata: ret dll entry state */
+                omap2_init_memory_params(omap2_dll_force_needed());
+                omap2_reprogram_sdrc(done_rate, 0);
+        }
+        omap2_dpll_recalc(&dpll_ck);
+        ret = 0;
+
+dpll_exit:
+        local_irq_restore(flags);
+        return(ret);
+}
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+static void omap2_table_mpu_recalc(struct clk *clk)
+{
+        clk->rate = curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+        struct prcm_config *ptr;
+        long highest_rate;
+
+        if (clk != &virt_prcm_set)
+                return -EINVAL;
+
+        highest_rate = -EINVAL;
+
+        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+                if (ptr->xtal_speed != sys_ck.rate)
+                        continue;
+
+                highest_rate = ptr->mpu_speed;
+
+                /* Can check only after xtal frequency check */
+                if (ptr->mpu_speed <= rate)
+                        break;
+        }
+        return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, done_rate, bypass = 0, tmp;
+        struct prcm_config *prcm;
+        unsigned long found_speed = 0;
+        unsigned long flags;
+
+        if (clk != &virt_prcm_set)
+                return -EINVAL;
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+
+                if (prcm->mpu_speed <= rate) {
+                        found_speed = prcm->mpu_speed;
+                        break;
+                }
+        }
+
+        if (!found_speed) {
+                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+                       rate / 1000000);
+                return -EINVAL;
+        }
+
+        curr_prcm_set = prcm;
+        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+
+        if (prcm->dpll_speed == cur_rate / 2) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+        } else if (prcm->dpll_speed == cur_rate * 2) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (prcm->dpll_speed != cur_rate) {
+                local_irq_save(flags);
+
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        bypass = 1;
+
+                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+                    CORE_CLK_SRC_DPLL_X2)
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                else
+                        done_rate = CORE_CLK_SRC_DPLL;
+
+                /* MPU divider */
+                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+                /* dsp + iva1 div(2420), iva2.1(2430) */
+                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+                /* Major subsystem dividers */
+                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+                if (cpu_is_omap2430())
+                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                                         OMAP2430_MDM_MOD, CM_CLKSEL);
+
+                /* x2 to enter init_mem */
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+
+                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+                               bypass);
+
+                omap2_init_memory_params(omap2_dll_force_needed());
+                omap2_reprogram_sdrc(done_rate, 0);
+
+                local_irq_restore(flags);
+        }
+        omap2_dpll_recalc(&dpll_ck);
+
+        return 0;
+}
+
+static struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+static u32 omap2_get_apll_clkin(void)
+{
+        u32 aplls, sclk = 0;
+
+        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+        if (aplls == APLLS_CLKIN_19_2MHZ)
+                sclk = 19200000;
+        else if (aplls == APLLS_CLKIN_13MHZ)
+                sclk = 13000000;
+        else if (aplls == APLLS_CLKIN_12MHZ)
+                sclk = 12000000;
+
+        return sclk;
+}
+
+static u32 omap2_get_sysclkdiv(void)
+{
+        u32 div;
+
+        div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+        div &= OMAP_SYSCLKDIV_MASK;
+        div >>= OMAP_SYSCLKDIV_SHIFT;
+
+        return div;
+}
+
+static void omap2_osc_clk_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
+        propagate_rate(clk);
+}
+
+static void omap2_sys_clk_recalc(struct clk *clk)
+{
+        clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
+        propagate_rate(clk);
+}
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+}
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        if (!mpurate)
+                return -EINVAL;
+
+        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+        struct prcm_config *prcm;
+        struct clk **clkp;
+        u32 clkrate;
+
+        if (cpu_is_omap242x())
+                cpu_mask = RATE_IN_242X;
+        else if (cpu_is_omap2430())
+                cpu_mask = RATE_IN_243X;
+
+        clk_init(&omap2_clk_functions);
+
+        omap2_osc_clk_recalc(&osc_ck);
+        omap2_sys_clk_recalc(&sys_ck);
+
+        for (clkp = onchip_24xx_clks;
+             clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
+             clkp++) {
+
+                if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
+                        clk_register(*clkp);
+                        continue;
+                }
+
+                if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
+                        clk_register(*clkp);
+                        continue;
+                }
+        }
+
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                         break;
+        }
+        curr_prcm_set = prcm;
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
new file mode 100644
index 000000000000..88081ed13f96
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -0,0 +1,2643 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock24xx.h
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+
+#include "clock.h"
+
+#include "prm.h"
+#include "cm.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+
+static void omap2_table_mpu_recalc(struct clk *clk);
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_osc_clk_recalc(struct clk *clk);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_dpll_recalc(struct clk *clk);
+static int omap2_clk_fixed_enable(struct clk *clk);
+static void omap2_clk_fixed_disable(struct clk *clk);
+static int omap2_enable_osc_ck(struct clk *clk);
+static void omap2_disable_osc_ck(struct clk *clk);
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
+
+/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
+ * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ */
+struct prcm_config {
+        unsigned long xtal_speed;       /* crystal rate */
+        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
+        unsigned long mpu_speed;        /* speed of MPU */
+        unsigned long cm_clksel_mpu;    /* mpu divider */
+        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
+        unsigned long cm_clksel_gfx;    /* gfx dividers */
+        unsigned long cm_clksel1_core;  /* major subsystem dividers */
+        unsigned long cm_clksel1_pll;   /* m,n */
+        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
+        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
+        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
+        unsigned char flags;
+};
+
+/*
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ */
+
+/* Core fields for cm_clksel, not ratio governed */
+#define RX_CLKSEL_DSS1                  (0x10 << 8)
+#define RX_CLKSEL_DSS2                  (0x0 << 13)
+#define RX_CLKSEL_SSI                   (0x5 << 20)
+
+/*-------------------------------------------------------------------------
+ * Voltage/DPLL ratios
+ *-------------------------------------------------------------------------*/
+
+/* 2430 Ratio's, 2430-Ratio Config 1 */
+#define R1_CLKSEL_L3                    (4 << 0)
+#define R1_CLKSEL_L4                    (2 << 5)
+#define R1_CLKSEL_USB                   (4 << 25)
+#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
+#define R1_CLKSEL_MPU                   (2 << 0)
+#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
+#define R1_CLKSEL_DSP                   (2 << 0)
+#define R1_CLKSEL_DSP_IF                (2 << 5)
+#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
+#define R1_CLKSEL_GFX                   (2 << 0)
+#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
+#define R1_CLKSEL_MDM                   (4 << 0)
+#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
+
+/* 2430-Ratio Config 2 */
+#define R2_CLKSEL_L3                    (6 << 0)
+#define R2_CLKSEL_L4                    (2 << 5)
+#define R2_CLKSEL_USB                   (2 << 25)
+#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
+#define R2_CLKSEL_MPU                   (2 << 0)
+#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
+#define R2_CLKSEL_DSP                   (2 << 0)
+#define R2_CLKSEL_DSP_IF                (3 << 5)
+#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
+#define R2_CLKSEL_GFX                   (2 << 0)
+#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
+#define R2_CLKSEL_MDM                   (6 << 0)
+#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
+
+/* 2430-Ratio Bootm (BYPASS) */
+#define RB_CLKSEL_L3                    (1 << 0)
+#define RB_CLKSEL_L4                    (1 << 5)
+#define RB_CLKSEL_USB                   (1 << 25)
+#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
+#define RB_CLKSEL_MPU                   (1 << 0)
+#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
+#define RB_CLKSEL_DSP                   (1 << 0)
+#define RB_CLKSEL_DSP_IF                (1 << 5)
+#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
+#define RB_CLKSEL_GFX                   (1 << 0)
+#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
+#define RB_CLKSEL_MDM                   (1 << 0)
+#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
+
+/* 2420 Ratio Equivalents */
+#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
+#define RXX_CLKSEL_SSI                  (0x8 << 20)
+
+/* 2420-PRCM III 532MHz core */
+#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
+#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
+#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
+#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
+                                        RIII_CLKSEL_L3
+#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
+#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
+#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
+#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
+#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
+#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
+#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
+#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
+                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
+                                        RIII_CLKSEL_DSP
+#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
+#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
+
+/* 2420-PRCM II 600MHz core */
+#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
+#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
+#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
+#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
+                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
+#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
+#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
+#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
+#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
+#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
+#define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
+#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
+#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
+                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
+                                        RII_CLKSEL_DSP
+#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
+#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
+
+/* 2420-PRCM I 660MHz core */
+#define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
+#define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
+#define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
+#define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
+                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RI_CLKSEL_L4 | RI_CLKSEL_L3
+#define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
+#define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
+#define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
+#define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
+#define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
+#define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
+#define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
+#define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
+                                        RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
+                                        RI_CLKSEL_DSP
+#define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
+#define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
+
+/* 2420-PRCM VII (boot) */
+#define RVII_CLKSEL_L3                  (1 << 0)
+#define RVII_CLKSEL_L4                  (1 << 5)
+#define RVII_CLKSEL_DSS1                (1 << 8)
+#define RVII_CLKSEL_DSS2                (0 << 13)
+#define RVII_CLKSEL_VLYNQ               (1 << 15)
+#define RVII_CLKSEL_SSI                 (1 << 20)
+#define RVII_CLKSEL_USB                 (1 << 25)
+
+#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
+                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
+                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
+
+#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
+#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+
+#define RVII_CLKSEL_DSP                 (1 << 0)
+#define RVII_CLKSEL_DSP_IF              (1 << 5)
+#define RVII_SYNC_DSP                   (0 << 7)
+#define RVII_CLKSEL_IVA                 (1 << 8)
+#define RVII_SYNC_IVA                   (0 << 13)
+#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
+                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
+
+#define RVII_CLKSEL_GFX                 (1 << 0)
+#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
+
+/*-------------------------------------------------------------------------
+ * 2430 Target modes: Along with each configuration the CPU has several
+ * modes which goes along with them. Modes mainly are the addition of
+ * describe DPLL combinations to go along with a ratio.
+ *-------------------------------------------------------------------------*/
+
+/* Hardware governed */
+#define MX_48M_SRC                      (0 << 3)
+#define MX_54M_SRC                      (0 << 5)
+#define MX_APLLS_CLIKIN_12              (3 << 23)
+#define MX_APLLS_CLIKIN_13              (2 << 23)
+#define MX_APLLS_CLIKIN_19_2            (0 << 23)
+
+/*
+ * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
+ * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
+ */
+#define M5A_DPLL_MULT_12                (133 << 12)
+#define M5A_DPLL_DIV_12                 (5 << 8)
+#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M5A_DPLL_MULT_13                (61 << 12)
+#define M5A_DPLL_DIV_13                 (2 << 8)
+#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M5A_DPLL_MULT_19                (55 << 12)
+#define M5A_DPLL_DIV_19                 (3 << 8)
+#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
+#define M5B_DPLL_MULT_12                (50 << 12)
+#define M5B_DPLL_DIV_12                 (2 << 8)
+#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M5B_DPLL_MULT_13                (200 << 12)
+#define M5B_DPLL_DIV_13                 (12 << 8)
+
+#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M5B_DPLL_MULT_19                (125 << 12)
+#define M5B_DPLL_DIV_19                 (31 << 8)
+#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+/*
+ * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
+ */
+#define M4_DPLL_MULT_12                 (133 << 12)
+#define M4_DPLL_DIV_12                  (3 << 8)
+#define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+#define M4_DPLL_MULT_13                 (399 << 12)
+#define M4_DPLL_DIV_13                  (12 << 8)
+#define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+#define M4_DPLL_MULT_19                 (145 << 12)
+#define M4_DPLL_DIV_19                  (6 << 8)
+#define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/*
+ * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
+ */
+#define M3_DPLL_MULT_12                 (55 << 12)
+#define M3_DPLL_DIV_12                  (1 << 8)
+#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M3_DPLL_MULT_13                 (76 << 12)
+#define M3_DPLL_DIV_13                  (2 << 8)
+#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M3_DPLL_MULT_19                 (17 << 12)
+#define M3_DPLL_DIV_19                  (0 << 8)
+#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/*
+ * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
+ */
+#define M2_DPLL_MULT_12                 (55 << 12)
+#define M2_DPLL_DIV_12                  (1 << 8)
+#define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
+ * relock time issue */
+/* Core frequency changed from 330/165 to 329/164 MHz*/
+#define M2_DPLL_MULT_13                 (76 << 12)
+#define M2_DPLL_DIV_13                  (2 << 8)
+#define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+#define M2_DPLL_MULT_19                 (17 << 12)
+#define M2_DPLL_DIV_19                  (0 << 8)
+#define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/* boot (boot) */
+#define MB_DPLL_MULT                    (1 << 12)
+#define MB_DPLL_DIV                     (0 << 8)
+#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
+
+#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
+
+#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
+
+/*
+ * 2430 - chassis (sedna)
+ * 165 (ratio1) same as above #2
+ * 150 (ratio1)
+ * 133 (ratio2) same as above #4
+ * 110 (ratio2) same as above #3
+ * 104 (ratio2)
+ * boot (boot)
+ */
+
+/* PRCM I target DPLL = 2*330MHz = 660MHz */
+#define MI_DPLL_MULT_12                 (55 << 12)
+#define MI_DPLL_DIV_12                  (1 << 8)
+#define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+/*
+ * 2420 Equivalent - mode registers
+ * PRCM II , target DPLL = 2*300MHz = 600MHz
+ */
+#define MII_DPLL_MULT_12                (50 << 12)
+#define MII_DPLL_DIV_12                 (1 << 8)
+#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define MII_DPLL_MULT_13                (300 << 12)
+#define MII_DPLL_DIV_13                 (12 << 8)
+#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+/* PRCM III target DPLL = 2*266 = 532MHz*/
+#define MIII_DPLL_MULT_12               (133 << 12)
+#define MIII_DPLL_DIV_12                (5 << 8)
+#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
+                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define MIII_DPLL_MULT_13               (266 << 12)
+#define MIII_DPLL_DIV_13                (12 << 8)
+#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
+                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+/* PRCM VII (boot bypass) */
+#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
+#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
+
+/* High and low operation value */
+#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
+#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
+
+/* MPU speed defines */
+#define S12M    12000000
+#define S13M    13000000
+#define S19M    19200000
+#define S26M    26000000
+#define S100M   100000000
+#define S133M   133000000
+#define S150M   150000000
+#define S164M   164000000
+#define S165M   165000000
+#define S199M   199000000
+#define S200M   200000000
+#define S266M   266000000
+#define S300M   300000000
+#define S329M   329000000
+#define S330M   330000000
+#define S399M   399000000
+#define S400M   400000000
+#define S532M   532000000
+#define S600M   600000000
+#define S658M   658000000
+#define S660M   660000000
+#define S798M   798000000
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used.    Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set.    The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+static struct prcm_config rate_table[] = {
+        /* PRCM I - FAST */
+        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
+                RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - FAST */
+        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - FAST */
+        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - SLOW */
+        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - SLOW */
+        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM #4 - ratio2 (ES2.1) - FAST */
+        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - FAST */
+        {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - FAST */
+        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - FAST */
+        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM #4 - ratio1 (ES2.1) - SLOW */
+        {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - SLOW */
+        {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - SLOW */
+        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - SLOW*/
+        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
+
+/*-------------------------------------------------------------------------
+ * 24xx clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In many
+ *      cases the parent is selectable. The get/set parent calls will also
+ *      switch sources.
+ *
+ *      Many some clocks say always_enabled, but they can be auto idled for
+ *      power savings. They will always be available upon clock request.
+ *
+ *      Several sources are given initial rates which may be wrong, this will
+ *      be fixed up in the init func.
+ *
+ *      Things are broadly separated below by clock domains. It is
+ *      noteworthy that most periferals have dependencies on multiple clock
+ *      domains. Many get their interface clocks from the L4 domain, but get
+ *      functional clocks from fixed sources or other core domain derived
+ *      clocks.
+ *-------------------------------------------------------------------------*/
+
+/* Base external input clocks */
+static struct clk func_32k_ck = {
+        .name           = "func_32k_ck",
+        .rate           = 32000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &propagate_rate,
+};
+
+/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
+static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
+        .name           = "osc_ck",
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES,
+        .enable         = &omap2_enable_osc_ck,
+        .disable        = &omap2_disable_osc_ck,
+        .recalc         = &omap2_osc_clk_recalc,
+};
+
+/* With out modem likely 12MHz, with modem likely 13MHz */
+static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
+        .name           = "sys_ck",             /* ~ ref_clk also */
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &omap2_sys_clk_recalc,
+};
+
+static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
+        .name           = "alt_ck",
+        .rate           = 54000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &propagate_rate,
+};
+
+/*
+ * Analog domain root source clocks
+ */
+
+/* dpll_ck, is broken out in to special cases through clksel */
+/* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
+ * deal with this
+ */
+
+static const struct dpll_data dpll_dd = {
+        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
+        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+};
+
+static struct clk dpll_ck = {
+        .name           = "dpll_ck",
+        .parent         = &sys_ck,              /* Can be func_32k also */
+        .dpll_data      = &dpll_dd,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_dpll_recalc,
+        .set_rate       = &omap2_reprogram_dpll,
+};
+
+static struct clk apll96_ck = {
+        .name           = "apll96_ck",
+        .parent         = &sys_ck,
+        .rate           = 96000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+        .enable         = &omap2_clk_fixed_enable,
+        .disable        = &omap2_clk_fixed_disable,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk apll54_ck = {
+        .name           = "apll54_ck",
+        .parent         = &sys_ck,
+        .rate           = 54000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+        .enable         = &omap2_clk_fixed_enable,
+        .disable        = &omap2_clk_fixed_disable,
+        .recalc         = &propagate_rate,
+};
+
+/*
+ * PRCM digital base sources
+ */
+
+/* func_54m_ck */
+
+static const struct clksel_rate func_54m_apll54_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_54m_clksel[] = {
+        { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
+        { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
+        { .parent = NULL },
+};
+
+static struct clk func_54m_ck = {
+        .name           = "func_54m_ck",
+        .parent         = &apll54_ck,   /* can also be alt_clk */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_54M_SOURCE,
+        .clksel         = func_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .parent         = &dpll_ck,             /* can also be 32k */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+/* func_96m_ck */
+static const struct clksel_rate func_96m_apll96_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_96m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_96m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
+        { .parent = &alt_ck,    .rates = func_96m_alt_rates },
+        { .parent = NULL }
+};
+
+/* The parent of this clock is not selectable on 2420. */
+static struct clk func_96m_ck = {
+        .name           = "func_96m_ck",
+        .parent         = &apll96_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2430_96M_SOURCE,
+        .clksel         = func_96m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* func_48m_ck */
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_48m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+        { .parent = &alt_ck, .rates = func_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk func_48m_ck = {
+        .name           = "func_48m_ck",
+        .parent         = &apll96_ck,    /* 96M or Alt */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_48M_SOURCE,
+        .clksel         = func_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk func_12m_ck = {
+        .name           = "func_12m_ck",
+        .parent         = &func_48m_ck,
+        .fixed_div      = 4,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* Secure timer, only available in secure mode */
+static struct clk wdt1_osc_ck = {
+        .name           = "ck_wdt1_osc",
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * The common_clkout* clksel_rate structs are common to
+ * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
+ * sys_clkout2_* are 2420-only, so the
+ * clksel_rate flags fields are inaccurate for those clocks. This is
+ * harmless since access to those clocks are gated by the struct clk
+ * flags fields, which mark them as 2420-only.
+ */
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+        { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
+        { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
+        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk sys_clkout_src = {
+        .name           = "sys_clkout_src",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES,
+        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate common_clkout_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout_clksel[] = {
+        { .parent = &sys_clkout_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+
+static struct clk sys_clkout = {
+        .name           = "sys_clkout",
+        .parent         = &sys_clkout_src,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
+        .clksel         = sys_clkout_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2_src = {
+        .name           = "sys_clkout2_src",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
+        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .parent         = &sys_clkout2_src,
+        .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk emul_ck = {
+        .name           = "emul_ck",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
+        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+
+};
+
+/*
+ * MPU clock domain
+ *      Clocks:
+ *              MPU_FCLK, MPU_ICLK
+ *              INT_M_FCLK, INT_M_I_CLK
+ *
+ * - Individual clocks are hardware managed.
+ * - Base divider comes from: CM_CLKSEL_MPU
+ *
+ */
+static const struct clksel_rate mpu_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+
+static const struct clksel mpu_clksel[] = {
+        { .parent = &core_ck, .rates = mpu_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk mpu_ck = {    /* Control cpu */
+        .name           = "mpu_ck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
+        .clksel         = mpu_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
+ * Clocks:
+ *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
+ *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
+ *
+ * Won't be too specific here. The core clock comes into this block
+ * it is divided then tee'ed. One branch goes directly to xyz enable
+ * controls. The other branch gets further divided by 2 then possibly
+ * routed into a synchronizer and out of clocks abc.
+ */
+static const struct clksel_rate dsp_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+        { .parent = &core_ck, .rates = dsp_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* DSP interface clock */
+static const struct clksel_rate dsp_irate_ick_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X },
+        { .div = 0 },
+};
+
+static const struct clksel dsp_irate_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+        { .parent = NULL }
+};
+
+/*
+ * This clock does not exist as such in the TRM, but is added to
+ * separate source selection from  XXX
+ */
+static struct clk dsp_irate_ick = {
+        .name           = "dsp_irate_ick",
+        .parent         = &dsp_fck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+                                CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_irate_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate             = &omap2_clksel_set_rate
+};
+
+/* 2420 only */
+static struct clk dsp_ick = {
+        .name           = "dsp_ick",     /* apparently ipi and isp */
+        .parent         = &dsp_irate_ick,
+        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
+};
+
+/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
+static struct clk iva2_1_ick = {
+        .name           = "iva2_1_ick",
+        .parent         = &dsp_irate_ick,
+        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+};
+
+static struct clk iva1_ifck = {
+        .name           = "iva1_ifck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
+                                RATE_PROPAGATES | DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* IVA1 mpu/int/i/f clocks are /2 of parent */
+static struct clk iva1_mpu_int_ifck = {
+        .name           = "iva1_mpu_int_ifck",
+        .parent         = &iva1_ifck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/*
+ * L3 clock domain
+ * L3 clocks are used for both interface and functional clocks to
+ * multiple entities. Some of these clocks are completely managed
+ * by hardware, and some others allow software control. Hardware
+ * managed ones general are based on directly CLK_REQ signals and
+ * various auto idle settings. The functional spec sets many of these
+ * as 'tie-high' for their enables.
+ *
+ * I-CLOCKS:
+ *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
+ *      CAM, HS-USB.
+ * F-CLOCK
+ *      SSI.
+ *
+ * GPMC memories and SDRC have timing and clock sensitive registers which
+ * may very well need notification when the clock changes. Currently for low
+ * operating points, these are taken care of in sleep.S.
+ */
+static const struct clksel_rate core_l3_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel core_l3_clksel[] = {
+        { .parent = &core_ck, .rates = core_l3_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
+        .name           = "core_l3_ck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
+        .clksel         = core_l3_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* usb_l4_ick */
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {        /* FS-USB interface clock */
+        .name           = "usb_l4_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
+        .clksel         = usb_l4_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * SSI is in L3 management domain, its direct parent is core not l3,
+ * many core power domain entities are grouped into the L3 clock
+ * domain.
+ * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
+ *
+ * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
+ */
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_243X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_sst_fck = {
+        .name           = "ssi_fck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_sst_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * GFX clock domain
+ *      Clocks:
+ * GFX_FCLK, GFX_ICLK
+ * GFX_CG1(2d), GFX_CG2(3d)
+ *
+ * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
+ * The 2d and 3d clocks run at a hardware determined
+ * divided value of fclk.
+ *
+ */
+/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
+
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
+static const struct clksel gfx_fck_clksel[] = {
+        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+        { .parent = NULL },
+};
+
+static struct clk gfx_3d_fck = {
+        .name           = "gfx_3d_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_2d_fck = {
+        .name           = "gfx_2d_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_ick = {
+        .name           = "gfx_ick",            /* From l3 */
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * Modem clock domain (2430)
+ *      CLOCKS:
+ *              MDM_OSC_CLK
+ *              MDM_ICLK
+ * These clocks are usable in chassis mode only.
+ */
+static const struct clksel_rate mdm_ick_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 6, .val = 6, .flags = RATE_IN_243X },
+        { .div = 9, .val = 9, .flags = RATE_IN_243X },
+        { .div = 0 }
+};
+
+static const struct clksel mdm_ick_clksel[] = {
+        { .parent = &core_ck, .rates = mdm_ick_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk mdm_ick = {           /* used both as a ick and fck */
+        .name           = "mdm_ick",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
+        .clksel         = mdm_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk mdm_osc_ck = {
+        .name           = "mdm_osc_ck",
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * L4 clock management domain
+ *
+ * This domain contains lots of interface clocks from the L4 interface, some
+ * functional clocks.   Fixed APLL functional source clocks are managed in
+ * this domain.
+ */
+static const struct clksel_rate l4_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel l4_clksel[] = {
+        { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ck = {             /* used both as an ick and fck */
+        .name           = "l4_ck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
+        .clksel         = l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * DSS clock domain
+ * CLOCKs:
+ * DSS_L4_ICLK, DSS_L3_ICLK,
+ * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
+ *
+ * DSS is both initiator and target.
+ */
+/* XXX Add RATE_NOT_VALIDATED */
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+        { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
+        { .parent = &core_ck, .rates = dss1_fck_core_rates },
+        { .parent = NULL },
+};
+
+static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
+        .name           = "dss_ick",
+        .parent         = &l4_ck,       /* really both l3 and l4 */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss1_fck = {
+        .name           = "dss1_fck",
+        .parent         = &core_ck,             /* Core or sys */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
+        .clksel         = dss1_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel dss2_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
+        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+        { .parent = NULL }
+};
+
+static struct clk dss2_fck = {          /* Alt clk used in power management */
+        .name           = "dss2_fck",
+        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
+        .clksel         = dss2_fck_clksel,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_54m_fck = {       /* Alt clk used in power management */
+        .name           = "dss_54m_fck",        /* 54m tv clk */
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+ * here will likely have an L4 interface parent, and may have multiple
+ * functional clock parents.
+ */
+static const struct clksel_rate gpt_alt_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,      .rates = gpt_sys_rates },
+        { .parent = &alt_ck,      .rates = gpt_alt_rates },
+        { .parent = NULL },
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .id             = 1,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .id             = 2,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .id             = 3,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .id             = 3,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpios_ick = {
+        .name           = "gpios_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpios_fck = {
+        .name           = "gpios_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_ick = {
+        .name           = "mpu_wdt_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_fck = {
+        .name           = "mpu_wdt_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sync_32k_ick = {
+        .name           = "sync_32k_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_ick = {
+        .name           = "cam_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_fck = {
+        .name           = "cam_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt4_ick = {
+        .name           = "wdt4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt4_fck = {
+        .name           = "wdt4_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc_ick = {
+        .name           = "mmc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc_fck = {
+        .name           = "mmc_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_fck = {
+        .name           = "fac_fck",
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk eac_ick = {
+        .name           = "eac_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk eac_fck = {
+        .name           = "eac_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .id             = 2,
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2chs2_fck = {
+        .name           = "i2chs_fck",
+        .id             = 2,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2chs1_fck = {
+        .name           = "i2chs_fck",
+        .id             = 1,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdma_fck = {
+        .name           = "sdma_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdma_ick = {
+        .name           = "sdma_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk vlynq_ick = {
+        .name           = "vlynq_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_242X },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 3, .val = 3, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 9, .val = 9, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 18, .val = 18, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+        { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+        { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk vlynq_fck = {
+        .name           = "vlynq_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
+        .clksel         = vlynq_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des_ick = {
+        .name           = "des_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha_ick = {
+        .name           = "sha_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes_ick = {
+        .name           = "aes_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_fck = {
+        .name           = "usb_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhs_ick = {
+        .name           = "usbhs_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .id             = 1,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .id             = 2,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+        .name           = "gpio5_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mdm_intc_ick = {
+        .name           = "mdm_intc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchsdb1_fck = {
+        .name           = "mmchsdb_fck",
+        .id             = 1,
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchsdb2_fck = {
+        .name           = "mmchsdb_fck",
+        .id             = 2,
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * This clock is a composite clock which does entire set changes then
+ * forces a rebalance. It keys on the MPU speed, but it really could
+ * be any key speed part of a set in the rate table.
+ *
+ * to really change a set, you need memory table sets which get changed
+ * in sram, pre-notifiers & post notifiers, changing the top set, without
+ * having low level display recalc's won't work... this is why dpm notifiers
+ * work, isr's off, walk a list of clocks already _off_ and not messing with
+ * the bus.
+ *
+ * This clock should have no parent. It embodies the entire upper level
+ * active set. A parent will mess up some of the init also.
+ */
+static struct clk virt_prcm_set = {
+        .name           = "virt_prcm_set",
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
+        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+
+static struct clk *onchip_24xx_clks[] __initdata = {
+        /* external root sources */
+        &func_32k_ck,
+        &osc_ck,
+        &sys_ck,
+        &alt_ck,
+        /* internal analog sources */
+        &dpll_ck,
+        &apll96_ck,
+        &apll54_ck,
+        /* internal prcm root sources */
+        &func_54m_ck,
+        &core_ck,
+        &func_96m_ck,
+        &func_48m_ck,
+        &func_12m_ck,
+        &wdt1_osc_ck,
+        &sys_clkout_src,
+        &sys_clkout,
+        &sys_clkout2_src,
+        &sys_clkout2,
+        &emul_ck,
+        /* mpu domain clocks */
+        &mpu_ck,
+        /* dsp domain clocks */
+        &dsp_fck,
+        &dsp_irate_ick,
+        &dsp_ick,               /* 242x */
+        &iva2_1_ick,            /* 243x */
+        &iva1_ifck,             /* 242x */
+        &iva1_mpu_int_ifck,     /* 242x */
+        /* GFX domain clocks */
+        &gfx_3d_fck,
+        &gfx_2d_fck,
+        &gfx_ick,
+        /* Modem domain clocks */
+        &mdm_ick,
+        &mdm_osc_ck,
+        /* DSS domain clocks */
+        &dss_ick,
+        &dss1_fck,
+        &dss2_fck,
+        &dss_54m_fck,
+        /* L3 domain clocks */
+        &core_l3_ck,
+        &ssi_ssr_sst_fck,
+        &usb_l4_ick,
+        /* L4 domain clocks */
+        &l4_ck,                 /* used as both core_l4 and wu_l4 */
+        &ssi_l4_ick,
+        /* virtual meta-group clock */
+        &virt_prcm_set,
+        /* general l4 interface ck, multi-parent functional clk */
+        &gpt1_ick,
+        &gpt1_fck,
+        &gpt2_ick,
+        &gpt2_fck,
+        &gpt3_ick,
+        &gpt3_fck,
+        &gpt4_ick,
+        &gpt4_fck,
+        &gpt5_ick,
+        &gpt5_fck,
+        &gpt6_ick,
+        &gpt6_fck,
+        &gpt7_ick,
+        &gpt7_fck,
+        &gpt8_ick,
+        &gpt8_fck,
+        &gpt9_ick,
+        &gpt9_fck,
+        &gpt10_ick,
+        &gpt10_fck,
+        &gpt11_ick,
+        &gpt11_fck,
+        &gpt12_ick,
+        &gpt12_fck,
+        &mcbsp1_ick,
+        &mcbsp1_fck,
+        &mcbsp2_ick,
+        &mcbsp2_fck,
+        &mcbsp3_ick,
+        &mcbsp3_fck,
+        &mcbsp4_ick,
+        &mcbsp4_fck,
+        &mcbsp5_ick,
+        &mcbsp5_fck,
+        &mcspi1_ick,
+        &mcspi1_fck,
+        &mcspi2_ick,
+        &mcspi2_fck,
+        &mcspi3_ick,
+        &mcspi3_fck,
+        &uart1_ick,
+        &uart1_fck,
+        &uart2_ick,
+        &uart2_fck,
+        &uart3_ick,
+        &uart3_fck,
+        &gpios_ick,
+        &gpios_fck,
+        &mpu_wdt_ick,
+        &mpu_wdt_fck,
+        &sync_32k_ick,
+        &wdt1_ick,
+        &omapctrl_ick,
+        &icr_ick,
+        &cam_fck,
+        &cam_ick,
+        &mailboxes_ick,
+        &wdt4_ick,
+        &wdt4_fck,
+        &wdt3_ick,
+        &wdt3_fck,
+        &mspro_ick,
+        &mspro_fck,
+        &mmc_ick,
+        &mmc_fck,
+        &fac_ick,
+        &fac_fck,
+        &eac_ick,
+        &eac_fck,
+        &hdq_ick,
+        &hdq_fck,
+        &i2c1_ick,
+        &i2c1_fck,
+        &i2chs1_fck,
+        &i2c2_ick,
+        &i2c2_fck,
+        &i2chs2_fck,
+        &gpmc_fck,
+        &sdma_fck,
+        &sdma_ick,
+        &vlynq_ick,
+        &vlynq_fck,
+        &sdrc_ick,
+        &des_ick,
+        &sha_ick,
+        &rng_ick,
+        &aes_ick,
+        &pka_ick,
+        &usb_fck,
+        &usbhs_ick,
+        &mmchs1_ick,
+        &mmchs1_fck,
+        &mmchs2_ick,
+        &mmchs2_fck,
+        &gpio5_ick,
+        &gpio5_fck,
+        &mdm_intc_ick,
+        &mmchsdb1_fck,
+        &mmchsdb2_fck,
+};
+
+#endif
+
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
new file mode 100644
index 000000000000..b42bdd6079a5
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -0,0 +1,235 @@
+/*
+ * OMAP3-specific clock framework functions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/* CM_CLKEN_PLL*.EN* bit values */
+#define DPLL_LOCKED             0x7
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+static void omap3_dpll_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_dpll_rate(clk);
+
+        propagate_rate(clk);
+}
+
+/**
+ * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
+ * @clk: DPLL output struct clk
+ *
+ * Using parent clock DPLL data, look up DPLL state.  If locked, set our
+ * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
+ */
+static void omap3_clkoutx2_recalc(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+        struct clk *pclk;
+
+        /* Walk up the parents of clk, looking for a DPLL */
+        pclk = clk->parent;
+        while (pclk && !pclk->dpll_data)
+                pclk = pclk->parent;
+
+        /* clk does not have a DPLL as a parent? */
+        WARN_ON(!pclk);
+
+        dd = pclk->dpll_data;
+
+        WARN_ON(!dd->control_reg || !dd->enable_mask);
+
+        v = __raw_readl(dd->control_reg) & dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+        if (v != DPLL_LOCKED)
+                clk->rate = clk->parent->rate;
+        else
+                clk->rate = clk->parent->rate * 2;
+
+        if (clk->flags & RATE_PROPAGATES)
+                propagate_rate(clk);
+}
+
+/*
+ * As it is structured now, this will prevent an OMAP2/3 multiboot
+ * kernel from compiling.  This will need further attention.
+ */
+#if defined(CONFIG_ARCH_OMAP3)
+
+static struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        /* REVISIT: Not ready for 343x */
+#if 0
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+#endif
+}
+
+/* REVISIT: Move this init stuff out into clock.c */
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        if (!mpurate)
+                return -EINVAL;
+
+        /* REVISIT: not yet ready for 343x */
+#if 0
+        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+        /* struct prcm_config *prcm; */
+        struct clk **clkp;
+        /* u32 clkrate; */
+        u32 cpu_clkflg;
+
+        /* REVISIT: Ultimately this will be used for multiboot */
+#if 0
+        if (cpu_is_omap242x()) {
+                cpu_mask = RATE_IN_242X;
+                cpu_clkflg = CLOCK_IN_OMAP242X;
+                clkp = onchip_24xx_clks;
+        } else if (cpu_is_omap2430()) {
+                cpu_mask = RATE_IN_243X;
+                cpu_clkflg = CLOCK_IN_OMAP243X;
+                clkp = onchip_24xx_clks;
+        }
+#endif
+        if (cpu_is_omap34xx()) {
+                cpu_mask = RATE_IN_343X;
+                cpu_clkflg = CLOCK_IN_OMAP343X;
+                clkp = onchip_34xx_clks;
+
+                /*
+                 * Update this if there are further clock changes between ES2
+                 * and production parts
+                 */
+                if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
+                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
+                        cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
+                } else {
+                        cpu_mask |= RATE_IN_3430ES2;
+                        cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
+                }
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (clkp = onchip_34xx_clks;
+             clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
+             clkp++) {
+                if ((*clkp)->flags & cpu_clkflg)
+                        clk_register(*clkp);
+        }
+
+        /* REVISIT: Not yet ready for OMAP3 */
+#if 0
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                         break;
+        }
+        curr_prcm_set = prcm;
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
+        /* REVISIT: not yet ready for 343x */
+#if 0
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+#endif
+        return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
new file mode 100644
index 000000000000..cf4644a94b9b
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -0,0 +1,3009 @@
+/*
+ * OMAP3 clock framework
+ *
+ * Virtual clocks are introduced as a convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+
+#include <asm/arch/control.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+
+static void omap3_dpll_recalc(struct clk *clk);
+static void omap3_clkoutx2_recalc(struct clk *clk);
+
+/*
+ * DPLL1 supplies clock to the MPU.
+ * DPLL2 supplies clock to the IVA2.
+ * DPLL3 supplies CORE domain clocks.
+ * DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
+ */
+
+/* PRM CLOCKS */
+
+/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
+static struct clk omap_32k_fck = {
+        .name           = "omap_32k_fck",
+        .rate           = 32768,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk secure_32k_fck = {
+        .name           = "secure_32k_fck",
+        .rate           = 32768,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* Virtual source clocks for osc_sys_ck */
+static struct clk virt_12m_ck = {
+        .name           = "virt_12m_ck",
+        .rate           = 12000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_13m_ck = {
+        .name           = "virt_13m_ck",
+        .rate           = 13000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_16_8m_ck = {
+        .name           = "virt_16_8m_ck",
+        .rate           = 16800000,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_19_2m_ck = {
+        .name           = "virt_19_2m_ck",
+        .rate           = 19200000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_26m_ck = {
+        .name           = "virt_26m_ck",
+        .rate           = 26000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_38_4m_ck = {
+        .name           = "virt_38_4m_ck",
+        .rate           = 38400000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static const struct clksel_rate osc_sys_12m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_13m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_16_8m_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_19_2m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_26m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_38_4m_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel osc_sys_clksel[] = {
+        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
+        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
+        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
+        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
+        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
+        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
+        { .parent = NULL },
+};
+
+/* Oscillator clock */
+/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
+static struct clk osc_sys_ck = {
+        .name           = "osc_sys_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSEL,
+        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
+        .clksel         = osc_sys_clksel,
+        /* REVISIT: deal with autoextclkmode? */
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel sys_clksel[] = {
+        { .parent = &osc_sys_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
+/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
+static struct clk sys_ck = {
+        .name           = "sys_ck",
+        .parent         = &osc_sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
+        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
+        .clksel         = sys_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sys_altclk = {
+        .name           = "sys_altclk",
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* Optional external clock input for some McBSPs */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* PRM EXTERNAL CLOCK OUTPUT */
+
+static struct clk sys_clkout1 = {
+        .name           = "sys_clkout1",
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLLS */
+
+/* CM CLOCKS */
+
+static const struct clksel_rate dpll_bypass_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dpll_locked_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate div16_dpll_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 5, .val = 5, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 7, .val = 7, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 9, .val = 9, .flags = RATE_IN_343X },
+        { .div = 10, .val = 10, .flags = RATE_IN_343X },
+        { .div = 11, .val = 11, .flags = RATE_IN_343X },
+        { .div = 12, .val = 12, .flags = RATE_IN_343X },
+        { .div = 13, .val = 13, .flags = RATE_IN_343X },
+        { .div = 14, .val = 14, .flags = RATE_IN_343X },
+        { .div = 15, .val = 15, .flags = RATE_IN_343X },
+        { .div = 16, .val = 16, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+/* DPLL1 */
+/* MPU clock source */
+/* Type: DPLL */
+static const struct dpll_data dpll1_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll1_ck = {
+        .name           = "dpll1_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll1_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed.
+ */
+static struct clk dpll1_x2_ck = {
+        .name           = "dpll1_x2_ck",
+        .parent         = &dpll1_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
+static const struct clksel div16_dpll1_x2m2_clksel[] = {
+        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * Does not exist in the TRM - needed to separate the M2 divider from
+ * bypass selection in mpu_ck
+ */
+static struct clk dpll1_x2m2_ck = {
+        .name           = "dpll1_x2m2_ck",
+        .parent         = &dpll1_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll1_x2m2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL2 */
+/* IVA2 clock source */
+/* Type: DPLL */
+
+static const struct dpll_data dpll2_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll2_ck = {
+        .name           = "dpll2_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll2_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll2_m2x2_clksel[] = {
+        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
+ * or CLKOUTX2. CLKOUT seems most plausible.
+ */
+static struct clk dpll2_m2_ck = {
+        .name           = "dpll2_m2_ck",
+        .parent         = &dpll2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll2_m2x2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL3 */
+/* Source clock for all interfaces and for some device fclks */
+/* Type: DPLL */
+static const struct dpll_data dpll3_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll3_ck = {
+        .name           = "dpll3_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll3_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+        .name           = "dpll3_x2_ck",
+        .parent         = &dpll3_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_dpll3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+        { .div = 0 },
+};
+
+static const struct clksel div31_dpll3m2_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
+        { .parent = NULL }
+};
+
+/*
+ * DPLL3 output M2
+ * REVISIT: This DPLL output divider must be changed in SRAM, so until
+ * that code is ready, this should remain a 'read-only' clksel clock.
+ */
+static struct clk dpll3_m2_ck = {
+        .name           = "dpll3_m2_ck",
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div31_dpll3m2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel core_ck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = core_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel dpll3_m2x2_ck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll3_m2x2_ck = {
+        .name           = "dpll3_m2x2_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = dpll3_m2x2_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static const struct clksel div16_dpll3_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll3_m3x2_ck */
+static struct clk dpll3_m3_ck = {
+        .name           = "dpll3_m3_ck",
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
+        .clksel         = div16_dpll3_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll3_m3x2_ck = {
+        .name           = "dpll3_m3x2_ck",
+        .parent         = &dpll3_m3_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel emu_core_alwon_ck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk emu_core_alwon_ck = {
+        .name           = "emu_core_alwon_ck",
+        .parent         = &dpll3_m3x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = emu_core_alwon_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static const struct dpll_data dpll4_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll4_ck = {
+        .name           = "dpll4_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll4_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+        .name           = "dpll4_x2_ck",
+        .parent         = &dpll4_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel div16_dpll4_clksel[] = {
+        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll4_m2x2_ck */
+static struct clk dpll4_m2_ck = {
+        .name           = "dpll4_m2_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+        .clksel_mask    = OMAP3430_DIV_96M_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m2x2_ck = {
+        .name           = "dpll4_m2x2_ck",
+        .parent         = &dpll4_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_96m_alwon_fck = {
+        .name           = "omap_96m_alwon_fck",
+        .parent         = &dpll4_m2x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = omap_96m_alwon_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                 PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_96m_fck = {
+        .name           = "omap_96m_fck",
+        .parent         = &omap_96m_alwon_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel cm_96m_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .parent         = &dpll4_m2x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = cm_96m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m3x2_ck */
+static struct clk dpll4_m3_ck = {
+        .name           = "dpll4_m3_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m3x2_ck = {
+        .name           = "dpll4_m3x2_ck",
+        .parent         = &dpll4_m3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel virt_omap_54m_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk virt_omap_54m_fck = {
+        .name           = "virt_omap_54m_fck",
+        .parent         = &dpll4_m3x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = virt_omap_54m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_54m_clksel[] = {
+        { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
+        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_54m_fck = {
+        .name           = "omap_54m_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_54M,
+        .clksel         = omap_54m_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_48m_96md2_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_48m_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_48m_fck = {
+        .name           = "omap_48m_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_48M,
+        .clksel         = omap_48m_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_12m_fck = {
+        .name           = "omap_12m_fck",
+        .parent         = &omap_48m_fck,
+        .fixed_div      = 4,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* This virstual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
+        .name           = "dpll4_m4_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m4x2_ck = {
+        .name           = "dpll4_m4x2_ck",
+        .parent         = &dpll4_m4_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m5x2_ck */
+static struct clk dpll4_m5_ck = {
+        .name           = "dpll4_m5_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m5x2_ck = {
+        .name           = "dpll4_m5x2_ck",
+        .parent         = &dpll4_m5_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m6x2_ck */
+static struct clk dpll4_m6_ck = {
+        .name           = "dpll4_m6_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m6x2_ck = {
+        .name           = "dpll4_m6x2_ck",
+        .parent         = &dpll4_m6_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_per_alwon_ck = {
+        .name           = "emu_per_alwon_ck",
+        .parent         = &dpll4_m6x2_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static const struct dpll_data dpll5_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll5_ck = {
+        .name           = "dpll5_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll5_dd,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll5_clksel[] = {
+        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll5_m2_ck = {
+        .name           = "dpll5_m2_ck",
+        .parent         = &dpll5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
+        .clksel         = div16_dpll5_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel omap_120m_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_120m_fck = {
+        .name           = "omap_120m_fck",
+        .parent         = &dpll5_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+        .clksel         = omap_120m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM EXTERNAL CLOCK OUTPUTS */
+
+static const struct clksel_rate clkout2_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel clkout2_src_clksel[] = {
+        { .parent = &core_ck,             .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
+        { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk clkout2_src_ck = {
+        .name           = "clkout2_src_ck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
+        .clksel         = clkout2_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate sys_clkout2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 4, .val = 2, .flags = RATE_IN_343X },
+        { .div = 8, .val = 3, .flags = RATE_IN_343X },
+        { .div = 16, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
+        { .parent = NULL },
+};
+
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM OUTPUT CLOCKS */
+
+static struct clk corex2_fck = {
+        .name           = "corex2_fck",
+        .parent         = &dpll3_m2x2_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL power domain clock controls */
+
+static const struct clksel div2_core_clksel[] = {
+        { .parent = &core_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
+static struct clk dpll1_fck = {
+        .name           = "dpll1_fck",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * MPU clksel:
+ * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll1_fck'
+ */
+static const struct clksel mpu_clksel[] = {
+        { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
+        { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk mpu_ck = {
+        .name           = "mpu_ck",
+        .parent         = &dpll1_x2m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = mpu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
+static const struct clksel_rate arm_fck_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel arm_fck_clksel[] = {
+        { .parent = &mpu_ck, .rates = arm_fck_rates },
+        { .parent = NULL }
+};
+
+static struct clk arm_fck = {
+        .name           = "arm_fck",
+        .parent         = &mpu_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = arm_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * REVISIT: This clock is never specifically defined in the 3430 TRM,
+ * although it is referenced - so this is a guess
+ */
+static struct clk emu_mpu_alwon_ck = {
+        .name           = "emu_mpu_alwon_ck",
+        .parent         = &mpu_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll2_fck = {
+        .name           = "dpll2_fck",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * IVA2 clksel:
+ * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll2_fck'
+ */
+
+static const struct clksel iva2_clksel[] = {
+        { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
+        { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk iva2_ck = {
+        .name           = "iva2_ck",
+        .parent         = &dpll2_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
+        .clksel         = iva2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* Common interface clocks */
+
+static struct clk l3_ick = {
+        .name           = "l3_ick",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel div2_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ick = {
+        .name           = "l4_ick",
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
+        .clksel         = div2_l3_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+
+};
+
+static const struct clksel div2_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk rm_ick = {
+        .name           = "rm_ick",
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
+        .clksel         = div2_l4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* GFX power domain */
+
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
+
+static const struct clksel gfx_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = gfx_l3_rates },
+        { .parent = NULL }
+};
+
+static struct clk gfx_l3_fck = {
+        .name           = "gfx_l3_fck",
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_l3_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gfx_l3_ick = {
+        .name           = "gfx_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg1_ck = {
+        .name           = "gfx_cg1_ck",
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg2_ck = {
+        .name           = "gfx_cg2_ck",
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+/* SGX power domain - 3430ES2 only */
+
+static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4, .val = 1, .flags = RATE_IN_343X },
+        { .div = 6, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate sgx_96m_rates[] = {
+        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel sgx_clksel[] = {
+        { .parent = &core_ck,    .rates = sgx_core_rates },
+        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+        { .parent = NULL },
+};
+
+static struct clk sgx_fck = {
+        .name           = "sgx_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
+        .clksel         = sgx_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sgx_ick = {
+        .name           = "sgx_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE power domain */
+
+static struct clk d2d_26m_fck = {
+        .name           = "d2d_26m_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel omap343x_gpt_clksel[] = {
+        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,       .rates = gpt_sys_rates },
+        { .parent = NULL}
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cpefuse_fck = {
+        .name           = "cpefuse_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ts_fck = {
+        .name           = "ts_fck",
+        .parent         = &omap_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_fck = {
+        .name           = "usbtll_fck",
+        .parent         = &omap_120m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE 96M FCLK-derived clocks */
+
+static struct clk core_96m_fck = {
+        .name           = "core_96m_fck",
+        .parent         = &omap_96m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_fck = {
+        .name           = "mmchs_fck",
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+        .name           = "i2c_fck",
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
+ * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
+ */
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_15_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CORE_48M_FCK-derived clocks */
+
+static struct clk core_48m_fck = {
+        .name           = "core_48m_fck",
+        .parent         = &omap_48m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_fck = {
+        .name           = "mcspi_fck",
+        .id             = 4,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .id             = 3,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .id             = 2,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .id             = 1,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fshostusb_fck = {
+        .name           = "fshostusb_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_12M_FCK based clocks */
+
+static struct clk core_12m_fck = {
+        .name           = "core_12m_fck",
+        .parent         = &omap_12m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .parent         = &core_12m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL3-derived clock */
+
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_clksel[] = {
+        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_fck = {
+        .name           = "ssi_ssr_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck = {
+        .name           = "ssi_sst_fck",
+        .parent         = &ssi_ssr_fck,
+        .fixed_div      = 2,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+
+
+/* CORE_L3_ICK based clocks */
+
+static struct clk core_l3_ick = {
+        .name           = "core_l3_ick",
+        .parent         = &l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick = {
+        .name           = "hsotgusb_ick",
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .parent         = &core_l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
+                                ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURITY_L3_ICK based clocks */
+
+static struct clk security_l3_ick = {
+        .name           = "security_l3_ick",
+        .parent         = &l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .parent         = &security_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_L4_ICK based clocks */
+
+static struct clk core_l4_ick = {
+        .name           = "core_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_ick = {
+        .name           = "usbtll_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_ick = {
+        .name           = "mmchs_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes2_ick = {
+        .name           = "aes2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha12_ick = {
+        .name           = "sha12_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des2_ick = {
+        .name           = "des2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_ick = {
+        .name           = "mcspi_ick",
+        .id             = 4,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_ick = {
+        .name           = "i2c_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SSI_L4_ICK based clocks */
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ssi_ick = {
+        .name           = "ssi_ick",
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
+
+static const struct clksel usb_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {
+        .name           = "usb_l4_ick",
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+        .clksel         = usb_l4_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
+
+/* SECURITY_L4_ICK2 based clocks */
+
+static struct clk security_l4_ick2 = {
+        .name           = "security_l4_ick2",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes1_ick = {
+        .name           = "aes1_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha11_ick = {
+        .name           = "sha11_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des1_ick = {
+        .name           = "des1_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DSS */
+static const struct clksel dss1_alwon_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk dss1_alwon_fck = {
+        .name           = "dss1_alwon_fck",
+        .parent         = &dpll4_m4x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = dss1_alwon_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk dss_tv_fck = {
+        .name           = "dss_tv_fck",
+        .parent         = &omap_54m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_96m_fck = {
+        .name           = "dss_96m_fck",
+        .parent         = &omap_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss2_alwon_fck = {
+        .name           = "dss2_alwon_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* CAM */
+
+static const struct clksel cam_mclk_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk cam_mclk = {
+        .name           = "cam_mclk",
+        .parent         = &dpll4_m5x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = cam_mclk_clksel,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cam_l3_ick = {
+        .name           = "cam_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_l4_ick = {
+        .name           = "cam_l4_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* USBHOST - 3430ES2 only */
+
+static struct clk usbhost_120m_fck = {
+        .name           = "usbhost_120m_fck",
+        .parent         = &omap_120m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_48m_fck = {
+        .name           = "usbhost_48m_fck",
+        .parent         = &omap_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_l3_ick = {
+        .name           = "usbhost_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_l4_ick = {
+        .name           = "usbhost_l4_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_sar_fck = {
+        .name           = "usbhost_sar_fck",
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
+        .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* WKUP */
+
+static const struct clksel_rate usim_96m_rates[] = {
+        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
+        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
+        { .div = 10, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate usim_120m_rates[] = {
+        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
+        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
+        { .div = 20, .val = 10, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel usim_clksel[] = {
+        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
+        { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
+        { .parent = &sys_ck,            .rates = div2_rates },
+        { .parent = NULL },
+};
+
+/* 3430ES2 only */
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+        .clksel         = usim_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk wkup_32k_fck = {
+        .name           = "wkup_32k_fck",
+        .parent         = &omap_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_fck = {
+        .name           = "gpio1_fck",
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_fck = {
+        .name           = "wdt2_fck",
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wkup_l4_ick = {
+        .name           = "wkup_l4_ick",
+        .parent         = &sys_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+        .name           = "usim_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_ick = {
+        .name           = "wdt2_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+        .name           = "gpio1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omap_32ksync_ick = {
+        .name           = "omap_32ksync_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+
+
+/* PER clock domain */
+
+static struct clk per_96m_fck = {
+        .name           = "per_96m_fck",
+        .parent         = &omap_96m_alwon_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_48m_fck = {
+        .name           = "per_48m_fck",
+        .parent         = &omap_48m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk per_32k_alwon_fck = {
+        .name           = "per_32k_alwon_fck",
+        .parent         = &omap_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_fck = {
+        .name           = "gpio6_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+        .name           = "gpio5_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_fck = {
+        .name           = "gpio4_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_fck = {
+        .name           = "gpio3_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_fck = {
+        .name           = "gpio2_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_l4_ick = {
+        .name           = "per_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_ick = {
+        .name           = "gpio6_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_ick = {
+        .name           = "gpio4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+        .name           = "gpio3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+        .name           = "gpio2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel mcbsp_234_clksel[] = {
+        { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* EMU clocks */
+
+/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
+
+static const struct clksel_rate emu_src_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_per_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_mpu_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel emu_src_clksel[] = {
+        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
+        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
+        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
+        { .parent = NULL },
+};
+
+/*
+ * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
+ * to switch the source of some of the EMU clocks.
+ * XXX Are there CLKEN bits for these EMU clks?
+ */
+static struct clk emu_src_ck = {
+        .name           = "emu_src_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclk_emu_rates[] = {
+        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclk_fck = {
+        .name           = "pclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
+        .clksel         = pclk_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclkx2_emu_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclkx2_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclkx2_fck = {
+        .name           = "pclkx2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
+        .clksel         = pclkx2_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel atclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk atclk_fck = {
+        .name           = "atclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
+        .clksel         = atclk_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk traceclk_src_fck = {
+        .name           = "traceclk_src_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate traceclk_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel traceclk_clksel[] = {
+        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
+        { .parent = NULL },
+};
+
+static struct clk traceclk_fck = {
+        .name           = "traceclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
+        .clksel         = traceclk_clksel,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* SR clocks */
+
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+        .name           = "sr1_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+        .name           = "sr2_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_l4_ick = {
+        .name           = "sr_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURE_32K_FCK clocks */
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .parent         = &secure_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+        .name           = "wdt1_fck",
+        .parent         = &secure_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk *onchip_34xx_clks[] __initdata = {
+        &omap_32k_fck,
+        &virt_12m_ck,
+        &virt_13m_ck,
+        &virt_16_8m_ck,
+        &virt_19_2m_ck,
+        &virt_26m_ck,
+        &virt_38_4m_ck,
+        &osc_sys_ck,
+        &sys_ck,
+        &sys_altclk,
+        &mcbsp_clks,
+        &sys_clkout1,
+        &dpll1_ck,
+        &dpll1_x2_ck,
+        &dpll1_x2m2_ck,
+        &dpll2_ck,
+        &dpll2_m2_ck,
+        &dpll3_ck,
+        &core_ck,
+        &dpll3_x2_ck,
+        &dpll3_m2_ck,
+        &dpll3_m2x2_ck,
+        &dpll3_m3_ck,
+        &dpll3_m3x2_ck,
+        &emu_core_alwon_ck,
+        &dpll4_ck,
+        &dpll4_x2_ck,
+        &omap_96m_alwon_fck,
+        &omap_96m_fck,
+        &cm_96m_fck,
+        &virt_omap_54m_fck,
+        &omap_54m_fck,
+        &omap_48m_fck,
+        &omap_12m_fck,
+        &dpll4_m2_ck,
+        &dpll4_m2x2_ck,
+        &dpll4_m3_ck,
+        &dpll4_m3x2_ck,
+        &dpll4_m4_ck,
+        &dpll4_m4x2_ck,
+        &dpll4_m5_ck,
+        &dpll4_m5x2_ck,
+        &dpll4_m6_ck,
+        &dpll4_m6x2_ck,
+        &emu_per_alwon_ck,
+        &dpll5_ck,
+        &dpll5_m2_ck,
+        &omap_120m_fck,
+        &clkout2_src_ck,
+        &sys_clkout2,
+        &corex2_fck,
+        &dpll1_fck,
+        &mpu_ck,
+        &arm_fck,
+        &emu_mpu_alwon_ck,
+        &dpll2_fck,
+        &iva2_ck,
+        &l3_ick,
+        &l4_ick,
+        &rm_ick,
+        &gfx_l3_fck,
+        &gfx_l3_ick,
+        &gfx_cg1_ck,
+        &gfx_cg2_ck,
+        &sgx_fck,
+        &sgx_ick,
+        &d2d_26m_fck,
+        &gpt10_fck,
+        &gpt11_fck,
+        &cpefuse_fck,
+        &ts_fck,
+        &usbtll_fck,
+        &core_96m_fck,
+        &mmchs3_fck,
+        &mmchs2_fck,
+        &mspro_fck,
+        &mmchs1_fck,
+        &i2c3_fck,
+        &i2c2_fck,
+        &i2c1_fck,
+        &mcbsp5_fck,
+        &mcbsp1_fck,
+        &core_48m_fck,
+        &mcspi4_fck,
+        &mcspi3_fck,
+        &mcspi2_fck,
+        &mcspi1_fck,
+        &uart2_fck,
+        &uart1_fck,
+        &fshostusb_fck,
+        &core_12m_fck,
+        &hdq_fck,
+        &ssi_ssr_fck,
+        &ssi_sst_fck,
+        &core_l3_ick,
+        &hsotgusb_ick,
+        &sdrc_ick,
+        &gpmc_fck,
+        &security_l3_ick,
+        &pka_ick,
+        &core_l4_ick,
+        &usbtll_ick,
+        &mmchs3_ick,
+        &icr_ick,
+        &aes2_ick,
+        &sha12_ick,
+        &des2_ick,
+        &mmchs2_ick,
+        &mmchs1_ick,
+        &mspro_ick,
+        &hdq_ick,
+        &mcspi4_ick,
+        &mcspi3_ick,
+        &mcspi2_ick,
+        &mcspi1_ick,
+        &i2c3_ick,
+        &i2c2_ick,
+        &i2c1_ick,
+        &uart2_ick,
+        &uart1_ick,
+        &gpt11_ick,
+        &gpt10_ick,
+        &mcbsp5_ick,
+        &mcbsp1_ick,
+        &fac_ick,
+        &mailboxes_ick,
+        &omapctrl_ick,
+        &ssi_l4_ick,
+        &ssi_ick,
+        &usb_l4_ick,
+        &security_l4_ick2,
+        &aes1_ick,
+        &rng_ick,
+        &sha11_ick,
+        &des1_ick,
+        &dss1_alwon_fck,
+        &dss_tv_fck,
+        &dss_96m_fck,
+        &dss2_alwon_fck,
+        &dss_ick,
+        &cam_mclk,
+        &cam_l3_ick,
+        &cam_l4_ick,
+        &usbhost_120m_fck,
+        &usbhost_48m_fck,
+        &usbhost_l3_ick,
+        &usbhost_l4_ick,
+        &usbhost_sar_fck,
+        &usim_fck,
+        &gpt1_fck,
+        &wkup_32k_fck,
+        &gpio1_fck,
+        &wdt2_fck,
+        &wkup_l4_ick,
+        &usim_ick,
+        &wdt2_ick,
+        &wdt1_ick,
+        &gpio1_ick,
+        &omap_32ksync_ick,
+        &gpt12_ick,
+        &gpt1_ick,
+        &per_96m_fck,
+        &per_48m_fck,
+        &uart3_fck,
+        &gpt2_fck,
+        &gpt3_fck,
+        &gpt4_fck,
+        &gpt5_fck,
+        &gpt6_fck,
+        &gpt7_fck,
+        &gpt8_fck,
+        &gpt9_fck,
+        &per_32k_alwon_fck,
+        &gpio6_fck,
+        &gpio5_fck,
+        &gpio4_fck,
+        &gpio3_fck,
+        &gpio2_fck,
+        &wdt3_fck,
+        &per_l4_ick,
+        &gpio6_ick,
+        &gpio5_ick,
+        &gpio4_ick,
+        &gpio3_ick,
+        &gpio2_ick,
+        &wdt3_ick,
+        &uart3_ick,
+        &gpt9_ick,
+        &gpt8_ick,
+        &gpt7_ick,
+        &gpt6_ick,
+        &gpt5_ick,
+        &gpt4_ick,
+        &gpt3_ick,
+        &gpt2_ick,
+        &mcbsp2_ick,
+        &mcbsp3_ick,
+        &mcbsp4_ick,
+        &mcbsp2_fck,
+        &mcbsp3_fck,
+        &mcbsp4_fck,
+        &emu_src_ck,
+        &pclk_fck,
+        &pclkx2_fck,
+        &atclk_fck,
+        &traceclk_src_fck,
+        &traceclk_fck,
+        &sr1_fck,
+        &sr2_fck,
+        &sr_l4_ick,
+        &secure_32k_fck,
+        &gpt12_fck,
+        &wdt1_fck,
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
new file mode 100644
index 000000000000..20ac38100678
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -0,0 +1,401 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Clock Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP24XX_EN_CAM_SHIFT                           31
+#define OMAP24XX_EN_CAM                                 (1 << 31)
+#define OMAP24XX_EN_WDT4_SHIFT                          29
+#define OMAP24XX_EN_WDT4                                (1 << 29)
+#define OMAP2420_EN_WDT3_SHIFT                          28
+#define OMAP2420_EN_WDT3                                (1 << 28)
+#define OMAP24XX_EN_MSPRO_SHIFT                         27
+#define OMAP24XX_EN_MSPRO                               (1 << 27)
+#define OMAP24XX_EN_FAC_SHIFT                           25
+#define OMAP24XX_EN_FAC                                 (1 << 25)
+#define OMAP2420_EN_EAC_SHIFT                           24
+#define OMAP2420_EN_EAC                                 (1 << 24)
+#define OMAP24XX_EN_HDQ_SHIFT                           23
+#define OMAP24XX_EN_HDQ                                 (1 << 23)
+#define OMAP2420_EN_I2C2_SHIFT                          20
+#define OMAP2420_EN_I2C2                                (1 << 20)
+#define OMAP2420_EN_I2C1_SHIFT                          19
+#define OMAP2420_EN_I2C1                                (1 << 19)
+
+/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
+#define OMAP2430_EN_MCBSP5_SHIFT                        5
+#define OMAP2430_EN_MCBSP5                              (1 << 5)
+#define OMAP2430_EN_MCBSP4_SHIFT                        4
+#define OMAP2430_EN_MCBSP4                              (1 << 4)
+#define OMAP2430_EN_MCBSP3_SHIFT                        3
+#define OMAP2430_EN_MCBSP3                              (1 << 3)
+#define OMAP24XX_EN_SSI_SHIFT                           1
+#define OMAP24XX_EN_SSI                                 (1 << 1)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP24XX_EN_MPU_WDT_SHIFT                       3
+#define OMAP24XX_EN_MPU_WDT                             (1 << 3)
+
+/* Bits specific to each register */
+
+/* CM_IDLEST_MPU */
+/* 2430 only */
+#define OMAP2430_ST_MPU                                 (1 << 0)
+
+/* CM_CLKSEL_MPU */
+#define OMAP24XX_CLKSEL_MPU_SHIFT                       0
+#define OMAP24XX_CLKSEL_MPU_MASK                        (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP24XX_AUTOSTATE_MPU                          (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits*/
+#define OMAP24XX_EN_TV_SHIFT                            2
+#define OMAP24XX_EN_TV                                  (1 << 2)
+#define OMAP24XX_EN_DSS2_SHIFT                          1
+#define OMAP24XX_EN_DSS2                                (1 << 1)
+#define OMAP24XX_EN_DSS1_SHIFT                          0
+#define OMAP24XX_EN_DSS1                                (1 << 0)
+
+/* CM_FCLKEN2_CORE specific bits */
+#define OMAP2430_EN_I2CHS2_SHIFT                        20
+#define OMAP2430_EN_I2CHS2                              (1 << 20)
+#define OMAP2430_EN_I2CHS1_SHIFT                        19
+#define OMAP2430_EN_I2CHS1                              (1 << 19)
+#define OMAP2430_EN_MMCHSDB2_SHIFT                      17
+#define OMAP2430_EN_MMCHSDB2                            (1 << 17)
+#define OMAP2430_EN_MMCHSDB1_SHIFT                      16
+#define OMAP2430_EN_MMCHSDB1                            (1 << 16)
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP24XX_EN_MAILBOXES_SHIFT                     30
+#define OMAP24XX_EN_MAILBOXES                           (1 << 30)
+#define OMAP24XX_EN_DSS_SHIFT                           0
+#define OMAP24XX_EN_DSS                                 (1 << 0)
+
+/* CM_ICLKEN2_CORE specific bits */
+
+/* CM_ICLKEN3_CORE */
+/* 2430 only */
+#define OMAP2430_EN_SDRC_SHIFT                          2
+#define OMAP2430_EN_SDRC                                (1 << 2)
+
+/* CM_ICLKEN4_CORE */
+#define OMAP24XX_EN_PKA_SHIFT                           4
+#define OMAP24XX_EN_PKA                                 (1 << 4)
+#define OMAP24XX_EN_AES_SHIFT                           3
+#define OMAP24XX_EN_AES                                 (1 << 3)
+#define OMAP24XX_EN_RNG_SHIFT                           2
+#define OMAP24XX_EN_RNG                                 (1 << 2)
+#define OMAP24XX_EN_SHA_SHIFT                           1
+#define OMAP24XX_EN_SHA                                 (1 << 1)
+#define OMAP24XX_EN_DES_SHIFT                           0
+#define OMAP24XX_EN_DES                                 (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP24XX_ST_MAILBOXES                           (1 << 30)
+#define OMAP24XX_ST_WDT4                                (1 << 29)
+#define OMAP2420_ST_WDT3                                (1 << 28)
+#define OMAP24XX_ST_MSPRO                               (1 << 27)
+#define OMAP24XX_ST_FAC                                 (1 << 25)
+#define OMAP2420_ST_EAC                                 (1 << 24)
+#define OMAP24XX_ST_HDQ                                 (1 << 23)
+#define OMAP24XX_ST_I2C2                                (1 << 20)
+#define OMAP24XX_ST_I2C1                                (1 << 19)
+#define OMAP24XX_ST_MCBSP2                              (1 << 16)
+#define OMAP24XX_ST_MCBSP1                              (1 << 15)
+#define OMAP24XX_ST_DSS                                 (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP2430_ST_MCBSP5                              (1 << 5)
+#define OMAP2430_ST_MCBSP4                              (1 << 4)
+#define OMAP2430_ST_MCBSP3                              (1 << 3)
+#define OMAP24XX_ST_SSI                                 (1 << 1)
+
+/* CM_IDLEST3_CORE */
+/* 2430 only */
+#define OMAP2430_ST_SDRC                                (1 << 2)
+
+/* CM_IDLEST4_CORE */
+#define OMAP24XX_ST_PKA                                 (1 << 4)
+#define OMAP24XX_ST_AES                                 (1 << 3)
+#define OMAP24XX_ST_RNG                                 (1 << 2)
+#define OMAP24XX_ST_SHA                                 (1 << 1)
+#define OMAP24XX_ST_DES                                 (1 << 0)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP24XX_AUTO_CAM                               (1 << 31)
+#define OMAP24XX_AUTO_MAILBOXES                         (1 << 30)
+#define OMAP24XX_AUTO_WDT4                              (1 << 29)
+#define OMAP2420_AUTO_WDT3                              (1 << 28)
+#define OMAP24XX_AUTO_MSPRO                             (1 << 27)
+#define OMAP2420_AUTO_MMC                               (1 << 26)
+#define OMAP24XX_AUTO_FAC                               (1 << 25)
+#define OMAP2420_AUTO_EAC                               (1 << 24)
+#define OMAP24XX_AUTO_HDQ                               (1 << 23)
+#define OMAP24XX_AUTO_UART2                             (1 << 22)
+#define OMAP24XX_AUTO_UART1                             (1 << 21)
+#define OMAP24XX_AUTO_I2C2                              (1 << 20)
+#define OMAP24XX_AUTO_I2C1                              (1 << 19)
+#define OMAP24XX_AUTO_MCSPI2                            (1 << 18)
+#define OMAP24XX_AUTO_MCSPI1                            (1 << 17)
+#define OMAP24XX_AUTO_MCBSP2                            (1 << 16)
+#define OMAP24XX_AUTO_MCBSP1                            (1 << 15)
+#define OMAP24XX_AUTO_GPT12                             (1 << 14)
+#define OMAP24XX_AUTO_GPT11                             (1 << 13)
+#define OMAP24XX_AUTO_GPT10                             (1 << 12)
+#define OMAP24XX_AUTO_GPT9                              (1 << 11)
+#define OMAP24XX_AUTO_GPT8                              (1 << 10)
+#define OMAP24XX_AUTO_GPT7                              (1 << 9)
+#define OMAP24XX_AUTO_GPT6                              (1 << 8)
+#define OMAP24XX_AUTO_GPT5                              (1 << 7)
+#define OMAP24XX_AUTO_GPT4                              (1 << 6)
+#define OMAP24XX_AUTO_GPT3                              (1 << 5)
+#define OMAP24XX_AUTO_GPT2                              (1 << 4)
+#define OMAP2420_AUTO_VLYNQ                             (1 << 3)
+#define OMAP24XX_AUTO_DSS                               (1 << 0)
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP2430_AUTO_MDM_INTC                          (1 << 11)
+#define OMAP2430_AUTO_GPIO5                             (1 << 10)
+#define OMAP2430_AUTO_MCSPI3                            (1 << 9)
+#define OMAP2430_AUTO_MMCHS2                            (1 << 8)
+#define OMAP2430_AUTO_MMCHS1                            (1 << 7)
+#define OMAP2430_AUTO_USBHS                             (1 << 6)
+#define OMAP2430_AUTO_MCBSP5                            (1 << 5)
+#define OMAP2430_AUTO_MCBSP4                            (1 << 4)
+#define OMAP2430_AUTO_MCBSP3                            (1 << 3)
+#define OMAP24XX_AUTO_UART3                             (1 << 2)
+#define OMAP24XX_AUTO_SSI                               (1 << 1)
+#define OMAP24XX_AUTO_USB                               (1 << 0)
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC                              (1 << 2)
+#define OMAP24XX_AUTO_GPMC                              (1 << 1)
+#define OMAP24XX_AUTO_SDMA                              (1 << 0)
+
+/* CM_AUTOIDLE4_CORE */
+#define OMAP24XX_AUTO_PKA                               (1 << 4)
+#define OMAP24XX_AUTO_AES                               (1 << 3)
+#define OMAP24XX_AUTO_RNG                               (1 << 2)
+#define OMAP24XX_AUTO_SHA                               (1 << 1)
+#define OMAP24XX_AUTO_DES                               (1 << 0)
+
+/* CM_CLKSEL1_CORE */
+#define OMAP24XX_CLKSEL_USB_SHIFT                       25
+#define OMAP24XX_CLKSEL_USB_MASK                        (0x7 << 25)
+#define OMAP24XX_CLKSEL_SSI_SHIFT                       20
+#define OMAP24XX_CLKSEL_SSI_MASK                        (0x1f << 20)
+#define OMAP2420_CLKSEL_VLYNQ_SHIFT                     15
+#define OMAP2420_CLKSEL_VLYNQ_MASK                      (0x1f << 15)
+#define OMAP24XX_CLKSEL_DSS2_SHIFT                      13
+#define OMAP24XX_CLKSEL_DSS2_MASK                       (0x1 << 13)
+#define OMAP24XX_CLKSEL_DSS1_SHIFT                      8
+#define OMAP24XX_CLKSEL_DSS1_MASK                       (0x1f << 8)
+#define OMAP24XX_CLKSEL_L4_SHIFT                        5
+#define OMAP24XX_CLKSEL_L4_MASK                         (0x3 << 5)
+#define OMAP24XX_CLKSEL_L3_SHIFT                        0
+#define OMAP24XX_CLKSEL_L3_MASK                         (0x1f << 0)
+
+/* CM_CLKSEL2_CORE */
+#define OMAP24XX_CLKSEL_GPT12_SHIFT                     22
+#define OMAP24XX_CLKSEL_GPT12_MASK                      (0x3 << 22)
+#define OMAP24XX_CLKSEL_GPT11_SHIFT                     20
+#define OMAP24XX_CLKSEL_GPT11_MASK                      (0x3 << 20)
+#define OMAP24XX_CLKSEL_GPT10_SHIFT                     18
+#define OMAP24XX_CLKSEL_GPT10_MASK                      (0x3 << 18)
+#define OMAP24XX_CLKSEL_GPT9_SHIFT                      16
+#define OMAP24XX_CLKSEL_GPT9_MASK                       (0x3 << 16)
+#define OMAP24XX_CLKSEL_GPT8_SHIFT                      14
+#define OMAP24XX_CLKSEL_GPT8_MASK                       (0x3 << 14)
+#define OMAP24XX_CLKSEL_GPT7_SHIFT                      12
+#define OMAP24XX_CLKSEL_GPT7_MASK                       (0x3 << 12)
+#define OMAP24XX_CLKSEL_GPT6_SHIFT                      10
+#define OMAP24XX_CLKSEL_GPT6_MASK                       (0x3 << 10)
+#define OMAP24XX_CLKSEL_GPT5_SHIFT                      8
+#define OMAP24XX_CLKSEL_GPT5_MASK                       (0x3 << 8)
+#define OMAP24XX_CLKSEL_GPT4_SHIFT                      6
+#define OMAP24XX_CLKSEL_GPT4_MASK                       (0x3 << 6)
+#define OMAP24XX_CLKSEL_GPT3_SHIFT                      4
+#define OMAP24XX_CLKSEL_GPT3_MASK                       (0x3 << 4)
+#define OMAP24XX_CLKSEL_GPT2_SHIFT                      2
+#define OMAP24XX_CLKSEL_GPT2_MASK                       (0x3 << 2)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP24XX_AUTOSTATE_DSS                          (1 << 2)
+#define OMAP24XX_AUTOSTATE_L4                           (1 << 1)
+#define OMAP24XX_AUTOSTATE_L3                           (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP24XX_EN_3D_SHIFT                            2
+#define OMAP24XX_EN_3D                                  (1 << 2)
+#define OMAP24XX_EN_2D_SHIFT                            1
+#define OMAP24XX_EN_2D                                  (1 << 1)
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP24XX_AUTOSTATE_GFX                          (1 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP2430_EN_ICR_SHIFT                           6
+#define OMAP2430_EN_ICR                                 (1 << 6)
+#define OMAP24XX_EN_OMAPCTRL_SHIFT                      5
+#define OMAP24XX_EN_OMAPCTRL                            (1 << 5)
+#define OMAP24XX_EN_WDT1_SHIFT                          4
+#define OMAP24XX_EN_WDT1                                (1 << 4)
+#define OMAP24XX_EN_32KSYNC_SHIFT                       1
+#define OMAP24XX_EN_32KSYNC                             (1 << 1)
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP2430_ST_ICR                                 (1 << 6)
+#define OMAP24XX_ST_OMAPCTRL                            (1 << 5)
+#define OMAP24XX_ST_WDT1                                (1 << 4)
+#define OMAP24XX_ST_MPU_WDT                             (1 << 3)
+#define OMAP24XX_ST_32KSYNC                             (1 << 1)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP24XX_AUTO_OMAPCTRL                          (1 << 5)
+#define OMAP24XX_AUTO_WDT1                              (1 << 4)
+#define OMAP24XX_AUTO_MPU_WDT                           (1 << 3)
+#define OMAP24XX_AUTO_GPIOS                             (1 << 2)
+#define OMAP24XX_AUTO_32KSYNC                           (1 << 1)
+#define OMAP24XX_AUTO_GPT1                              (1 << 0)
+
+/* CM_CLKSEL_WKUP */
+#define OMAP24XX_CLKSEL_GPT1_SHIFT                      0
+#define OMAP24XX_CLKSEL_GPT1_MASK                       (0x3 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP24XX_EN_54M_PLL_SHIFT                       6
+#define OMAP24XX_EN_54M_PLL_MASK                        (0x3 << 6)
+#define OMAP24XX_EN_96M_PLL_SHIFT                       2
+#define OMAP24XX_EN_96M_PLL_MASK                        (0x3 << 2)
+#define OMAP24XX_EN_DPLL_SHIFT                          0
+#define OMAP24XX_EN_DPLL_MASK                           (0x3 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP24XX_ST_54M_APLL                            (1 << 9)
+#define OMAP24XX_ST_96M_APLL                            (1 << 8)
+#define OMAP24XX_ST_54M_CLK                             (1 << 6)
+#define OMAP24XX_ST_12M_CLK                             (1 << 5)
+#define OMAP24XX_ST_48M_CLK                             (1 << 4)
+#define OMAP24XX_ST_96M_CLK                             (1 << 2)
+#define OMAP24XX_ST_CORE_CLK_SHIFT                      0
+#define OMAP24XX_ST_CORE_CLK_MASK                       (0x3 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP24XX_AUTO_54M_SHIFT                         6
+#define OMAP24XX_AUTO_54M_MASK                          (0x3 << 6)
+#define OMAP24XX_AUTO_96M_SHIFT                         2
+#define OMAP24XX_AUTO_96M_MASK                          (0x3 << 2)
+#define OMAP24XX_AUTO_DPLL_SHIFT                        0
+#define OMAP24XX_AUTO_DPLL_MASK                         (0x3 << 0)
+
+/* CM_CLKSEL1_PLL */
+#define OMAP2430_MAXDPLLFASTLOCK_SHIFT                  28
+#define OMAP2430_MAXDPLLFASTLOCK_MASK                   (0x7 << 28)
+#define OMAP24XX_APLLS_CLKIN_SHIFT                      23
+#define OMAP24XX_APLLS_CLKIN_MASK                       (0x7 << 23)
+#define OMAP24XX_DPLL_MULT_SHIFT                        12
+#define OMAP24XX_DPLL_MULT_MASK                         (0x3ff << 12)
+#define OMAP24XX_DPLL_DIV_SHIFT                         8
+#define OMAP24XX_DPLL_DIV_MASK                          (0xf << 8)
+#define OMAP24XX_54M_SOURCE_SHIFT                       5
+#define OMAP24XX_54M_SOURCE                             (1 << 5)
+#define OMAP2430_96M_SOURCE_SHIFT                       4
+#define OMAP2430_96M_SOURCE                             (1 << 4)
+#define OMAP24XX_48M_SOURCE_SHIFT                       3
+#define OMAP24XX_48M_SOURCE                             (1 << 3)
+#define OMAP2430_ALTCLK_SOURCE_SHIFT                    0
+#define OMAP2430_ALTCLK_SOURCE_MASK                     (0x7 << 0)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP24XX_CORE_CLK_SRC_SHIFT                     0
+#define OMAP24XX_CORE_CLK_SRC_MASK                      (0x3 << 0)
+
+/* CM_FCLKEN_DSP */
+#define OMAP2420_EN_IVA_COP_SHIFT                       10
+#define OMAP2420_EN_IVA_COP                             (1 << 10)
+#define OMAP2420_EN_IVA_MPU_SHIFT                       8
+#define OMAP2420_EN_IVA_MPU                             (1 << 8)
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT             0
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP                   (1 << 0)
+
+/* CM_ICLKEN_DSP */
+#define OMAP2420_EN_DSP_IPI_SHIFT                       1
+#define OMAP2420_EN_DSP_IPI                             (1 << 1)
+
+/* CM_IDLEST_DSP */
+#define OMAP2420_ST_IVA                                 (1 << 8)
+#define OMAP2420_ST_IPI                                 (1 << 1)
+#define OMAP24XX_ST_DSP                                 (1 << 0)
+
+/* CM_AUTOIDLE_DSP */
+#define OMAP2420_AUTO_DSP_IPI                           (1 << 1)
+
+/* CM_CLKSEL_DSP */
+#define OMAP2420_SYNC_IVA                               (1 << 13)
+#define OMAP2420_CLKSEL_IVA_SHIFT                       8
+#define OMAP2420_CLKSEL_IVA_MASK                        (0x1f << 8)
+#define OMAP24XX_SYNC_DSP                               (1 << 7)
+#define OMAP24XX_CLKSEL_DSP_IF_SHIFT                    5
+#define OMAP24XX_CLKSEL_DSP_IF_MASK                     (0x3 << 5)
+#define OMAP24XX_CLKSEL_DSP_SHIFT                       0
+#define OMAP24XX_CLKSEL_DSP_MASK                        (0x1f << 0)
+
+/* CM_CLKSTCTRL_DSP */
+#define OMAP2420_AUTOSTATE_IVA                          (1 << 8)
+#define OMAP24XX_AUTOSTATE_DSP                          (1 << 0)
+
+/* CM_FCLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_EN_OSC_SHIFT                           1
+#define OMAP2430_EN_OSC                                 (1 << 1)
+
+/* CM_ICLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT             0
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM                   (1 << 0)
+
+/* CM_IDLEST_MDM specific bits */
+/* 2430 only */
+
+/* CM_AUTOIDLE_MDM */
+/* 2430 only */
+#define OMAP2430_AUTO_OSC                               (1 << 1)
+#define OMAP2430_AUTO_MDM                               (1 << 0)
+
+/* CM_CLKSEL_MDM */
+/* 2430 only */
+#define OMAP2430_SYNC_MDM                               (1 << 4)
+#define OMAP2430_CLKSEL_MDM_SHIFT                       0
+#define OMAP2430_CLKSEL_MDM_MASK                        (0xf << 0)
+
+/* CM_CLKSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_AUTOSTATE_MDM                          (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
new file mode 100644
index 000000000000..9249129a5f46
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -0,0 +1,673 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Clock Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP3430ES2_EN_MMC3_MASK                        (1 << 30)
+#define OMAP3430ES2_EN_MMC3_SHIFT                       30
+#define OMAP3430_EN_MSPRO                               (1 << 23)
+#define OMAP3430_EN_MSPRO_SHIFT                         23
+#define OMAP3430_EN_HDQ                                 (1 << 22)
+#define OMAP3430_EN_HDQ_SHIFT                           22
+#define OMAP3430ES1_EN_FSHOSTUSB                        (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT                  5
+#define OMAP3430ES1_EN_D2D                              (1 << 3)
+#define OMAP3430ES1_EN_D2D_SHIFT                        3
+#define OMAP3430_EN_SSI                                 (1 << 0)
+#define OMAP3430_EN_SSI_SHIFT                           0
+
+/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+#define OMAP3430ES2_EN_USBTLL_SHIFT                     2
+#define OMAP3430ES2_EN_USBTLL_MASK                      (1 << 2)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP3430_EN_WDT2                                (1 << 5)
+#define OMAP3430_EN_WDT2_SHIFT                          5
+
+/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
+#define OMAP3430_EN_CAM                                 (1 << 0)
+#define OMAP3430_EN_CAM_SHIFT                           0
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
+#define OMAP3430_EN_WDT3                                (1 << 12)
+#define OMAP3430_EN_WDT3_SHIFT                          12
+
+/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
+#define OMAP3430_OVERRIDE_ENABLE                        (1 << 19)
+
+
+/* Bits specific to each register */
+
+/* CM_FCLKEN_IVA2 */
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2                 (1 << 0)
+
+/* CM_CLKEN_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT               8
+#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK                (0x3 << 8)
+#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT                4
+#define OMAP3430_IVA2_DPLL_FREQSEL_MASK                 (0xf << 4)
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT          3
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK           (1 << 3)
+#define OMAP3430_EN_IVA2_DPLL_SHIFT                     0
+#define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
+
+/* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2                                (1 << 0)
+
+/* CM_IDLEST_PLL_IVA2 */
+#define OMAP3430_ST_IVA2_CLK                            (1 << 0)
+
+/* CM_AUTOIDLE_PLL_IVA2 */
+#define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
+#define OMAP3430_AUTO_IVA2_DPLL_MASK                    (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_IVA2 */
+#define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
+#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
+#define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
+#define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
+#define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
+#define OMAP3430_IVA2_DPLL_DIV_MASK                     (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT             0
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK              (0x1f << 0)
+
+/* CM_CLKSTCTRL_IVA2 */
+#define OMAP3430_CLKTRCTRL_IVA2_SHIFT                   0
+#define OMAP3430_CLKTRCTRL_IVA2_MASK                    (0x3 << 0)
+
+/* CM_CLKSTST_IVA2 */
+#define OMAP3430_CLKACTIVITY_IVA2                       (1 << 0)
+
+/* CM_REVISION specific bits */
+
+/* CM_SYSCONFIG specific bits */
+
+/* CM_CLKEN_PLL_MPU */
+#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT                8
+#define OMAP3430_MPU_DPLL_RAMPTIME_MASK                 (0x3 << 8)
+#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT                 4
+#define OMAP3430_MPU_DPLL_FREQSEL_MASK                  (0xf << 4)
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT           3
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK            (1 << 3)
+#define OMAP3430_EN_MPU_DPLL_SHIFT                      0
+#define OMAP3430_EN_MPU_DPLL_MASK                       (0x7 << 0)
+
+/* CM_IDLEST_MPU */
+#define OMAP3430_ST_MPU                                 (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK                             (1 << 0)
+#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
+
+/* CM_AUTOIDLE_PLL_MPU */
+#define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0
+#define OMAP3430_AUTO_MPU_DPLL_MASK                     (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_MPU */
+#define OMAP3430_MPU_CLK_SRC_SHIFT                      19
+#define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
+#define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
+#define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
+#define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
+#define OMAP3430_MPU_DPLL_DIV_MASK                      (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_MPU */
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT              0
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK               (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP3430_CLKTRCTRL_MPU_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_MPU_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_MPU */
+#define OMAP3430_CLKACTIVITY_MPU                        (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits */
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP3430_EN_ICR                                 (1 << 29)
+#define OMAP3430_EN_ICR_SHIFT                           29
+#define OMAP3430_EN_AES2                                (1 << 28)
+#define OMAP3430_EN_AES2_SHIFT                          28
+#define OMAP3430_EN_SHA12                               (1 << 27)
+#define OMAP3430_EN_SHA12_SHIFT                         27
+#define OMAP3430_EN_DES2                                (1 << 26)
+#define OMAP3430_EN_DES2_SHIFT                          26
+#define OMAP3430ES1_EN_FAC                              (1 << 8)
+#define OMAP3430ES1_EN_FAC_SHIFT                        8
+#define OMAP3430_EN_MAILBOXES                           (1 << 7)
+#define OMAP3430_EN_MAILBOXES_SHIFT                     7
+#define OMAP3430_EN_OMAPCTRL                            (1 << 6)
+#define OMAP3430_EN_OMAPCTRL_SHIFT                      6
+#define OMAP3430_EN_SDRC                                (1 << 1)
+#define OMAP3430_EN_SDRC_SHIFT                          1
+
+/* CM_ICLKEN2_CORE */
+#define OMAP3430_EN_PKA                                 (1 << 4)
+#define OMAP3430_EN_PKA_SHIFT                           4
+#define OMAP3430_EN_AES1                                (1 << 3)
+#define OMAP3430_EN_AES1_SHIFT                          3
+#define OMAP3430_EN_RNG                                 (1 << 2)
+#define OMAP3430_EN_RNG_SHIFT                           2
+#define OMAP3430_EN_SHA11                               (1 << 1)
+#define OMAP3430_EN_SHA11_SHIFT                         1
+#define OMAP3430_EN_DES1                                (1 << 0)
+#define OMAP3430_EN_DES1_SHIFT                          0
+
+/* CM_FCLKEN3_CORE specific bits */
+#define OMAP3430ES2_EN_TS_SHIFT                         1
+#define OMAP3430ES2_EN_TS_MASK                          (1 << 1)
+#define OMAP3430ES2_EN_CPEFUSE_SHIFT                    0
+#define OMAP3430ES2_EN_CPEFUSE_MASK                     (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP3430_ST_ICR                                 (1 << 29)
+#define OMAP3430_ST_AES2                                (1 << 28)
+#define OMAP3430_ST_SHA12                               (1 << 27)
+#define OMAP3430_ST_DES2                                (1 << 26)
+#define OMAP3430_ST_MSPRO                               (1 << 23)
+#define OMAP3430_ST_HDQ                                 (1 << 22)
+#define OMAP3430ES1_ST_FAC                              (1 << 8)
+#define OMAP3430ES1_ST_MAILBOXES                        (1 << 7)
+#define OMAP3430_ST_OMAPCTRL                            (1 << 6)
+#define OMAP3430_ST_SDMA                                (1 << 2)
+#define OMAP3430_ST_SDRC                                (1 << 1)
+#define OMAP3430_ST_SSI                                 (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP3430_ST_PKA                                 (1 << 4)
+#define OMAP3430_ST_AES1                                (1 << 3)
+#define OMAP3430_ST_RNG                                 (1 << 2)
+#define OMAP3430_ST_SHA11                               (1 << 1)
+#define OMAP3430_ST_DES1                                (1 << 0)
+
+/* CM_IDLEST3_CORE */
+#define OMAP3430ES2_ST_USBTLL_SHIFT                     2
+#define OMAP3430ES2_ST_USBTLL_MASK                      (1 << 2)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_AES2                              (1 << 28)
+#define OMAP3430_AUTO_AES2_SHIFT                        28
+#define OMAP3430_AUTO_SHA12                             (1 << 27)
+#define OMAP3430_AUTO_SHA12_SHIFT                       27
+#define OMAP3430_AUTO_DES2                              (1 << 26)
+#define OMAP3430_AUTO_DES2_SHIFT                        26
+#define OMAP3430_AUTO_MMC2                              (1 << 25)
+#define OMAP3430_AUTO_MMC2_SHIFT                        25
+#define OMAP3430_AUTO_MMC1                              (1 << 24)
+#define OMAP3430_AUTO_MMC1_SHIFT                        24
+#define OMAP3430_AUTO_MSPRO                             (1 << 23)
+#define OMAP3430_AUTO_MSPRO_SHIFT                       23
+#define OMAP3430_AUTO_HDQ                               (1 << 22)
+#define OMAP3430_AUTO_HDQ_SHIFT                         22
+#define OMAP3430_AUTO_MCSPI4                            (1 << 21)
+#define OMAP3430_AUTO_MCSPI4_SHIFT                      21
+#define OMAP3430_AUTO_MCSPI3                            (1 << 20)
+#define OMAP3430_AUTO_MCSPI3_SHIFT                      20
+#define OMAP3430_AUTO_MCSPI2                            (1 << 19)
+#define OMAP3430_AUTO_MCSPI2_SHIFT                      19
+#define OMAP3430_AUTO_MCSPI1                            (1 << 18)
+#define OMAP3430_AUTO_MCSPI1_SHIFT                      18
+#define OMAP3430_AUTO_I2C3                              (1 << 17)
+#define OMAP3430_AUTO_I2C3_SHIFT                        17
+#define OMAP3430_AUTO_I2C2                              (1 << 16)
+#define OMAP3430_AUTO_I2C2_SHIFT                        16
+#define OMAP3430_AUTO_I2C1                              (1 << 15)
+#define OMAP3430_AUTO_I2C1_SHIFT                        15
+#define OMAP3430_AUTO_UART2                             (1 << 14)
+#define OMAP3430_AUTO_UART2_SHIFT                       14
+#define OMAP3430_AUTO_UART1                             (1 << 13)
+#define OMAP3430_AUTO_UART1_SHIFT                       13
+#define OMAP3430_AUTO_GPT11                             (1 << 12)
+#define OMAP3430_AUTO_GPT11_SHIFT                       12
+#define OMAP3430_AUTO_GPT10                             (1 << 11)
+#define OMAP3430_AUTO_GPT10_SHIFT                       11
+#define OMAP3430_AUTO_MCBSP5                            (1 << 10)
+#define OMAP3430_AUTO_MCBSP5_SHIFT                      10
+#define OMAP3430_AUTO_MCBSP1                            (1 << 9)
+#define OMAP3430_AUTO_MCBSP1_SHIFT                      9
+#define OMAP3430ES1_AUTO_FAC                            (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_SHIFT                      8
+#define OMAP3430_AUTO_MAILBOXES                         (1 << 7)
+#define OMAP3430_AUTO_MAILBOXES_SHIFT                   7
+#define OMAP3430_AUTO_OMAPCTRL                          (1 << 6)
+#define OMAP3430_AUTO_OMAPCTRL_SHIFT                    6
+#define OMAP3430ES1_AUTO_FSHOSTUSB                      (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT                5
+#define OMAP3430_AUTO_HSOTGUSB                          (1 << 4)
+#define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
+#define OMAP3430ES1_AUTO_D2D                            (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_SHIFT                      3
+#define OMAP3430_AUTO_SSI                               (1 << 0)
+#define OMAP3430_AUTO_SSI_SHIFT                         0
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP3430_AUTO_PKA                               (1 << 4)
+#define OMAP3430_AUTO_PKA_SHIFT                         4
+#define OMAP3430_AUTO_AES1                              (1 << 3)
+#define OMAP3430_AUTO_AES1_SHIFT                        3
+#define OMAP3430_AUTO_RNG                               (1 << 2)
+#define OMAP3430_AUTO_RNG_SHIFT                         2
+#define OMAP3430_AUTO_SHA11                             (1 << 1)
+#define OMAP3430_AUTO_SHA11_SHIFT                       1
+#define OMAP3430_AUTO_DES1                              (1 << 0)
+#define OMAP3430_AUTO_DES1_SHIFT                        0
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP3430ES2_AUTO_USBTLL_SHIFT                   2
+#define OMAP3430ES2_AUTO_USBTLL_MASK                    (1 << 2)
+
+/* CM_CLKSEL_CORE */
+#define OMAP3430_CLKSEL_SSI_SHIFT                       8
+#define OMAP3430_CLKSEL_SSI_MASK                        (0xf << 8)
+#define OMAP3430_CLKSEL_GPT11_MASK                      (1 << 7)
+#define OMAP3430_CLKSEL_GPT11_SHIFT                     7
+#define OMAP3430_CLKSEL_GPT10_MASK                      (1 << 6)
+#define OMAP3430_CLKSEL_GPT10_SHIFT                     6
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT              4
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK               (0x3 << 4)
+#define OMAP3430_CLKSEL_L4_SHIFT                        2
+#define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
+#define OMAP3430_CLKSEL_L3_SHIFT                        0
+#define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
+#define OMAP3430ES1_CLKTRCTRL_D2D_MASK                  (0x3 << 4)
+#define OMAP3430_CLKTRCTRL_L4_SHIFT                     2
+#define OMAP3430_CLKTRCTRL_L4_MASK                      (0x3 << 2)
+#define OMAP3430_CLKTRCTRL_L3_SHIFT                     0
+#define OMAP3430_CLKTRCTRL_L3_MASK                      (0x3 << 0)
+
+/* CM_CLKSTST_CORE */
+#define OMAP3430ES1_CLKACTIVITY_D2D                     (1 << 2)
+#define OMAP3430_CLKACTIVITY_L4                         (1 << 1)
+#define OMAP3430_CLKACTIVITY_L3                         (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP3430ES1_EN_3D                               (1 << 2)
+#define OMAP3430ES1_EN_3D_SHIFT                         2
+#define OMAP3430ES1_EN_2D                               (1 << 1)
+#define OMAP3430ES1_EN_2D_SHIFT                         1
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_SLEEPDEP_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT                 0
+#define OMAP3430ES1_CLKTRCTRL_GFX_MASK                  (0x3 << 0)
+
+/* CM_CLKSTST_GFX */
+#define OMAP3430ES1_CLKACTIVITY_GFX                     (1 << 0)
+
+/* CM_FCLKEN_SGX */
+#define OMAP3430ES2_EN_SGX_SHIFT                        1
+#define OMAP3430ES2_EN_SGX_MASK                         (1 << 1)
+
+/* CM_CLKSEL_SGX */
+#define OMAP3430ES2_CLKSEL_SGX_SHIFT                    0
+#define OMAP3430ES2_CLKSEL_SGX_MASK                     (0x7 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+#define OMAP3430ES2_EN_USIMOCP_SHIFT                    9
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP3430_EN_WDT1                                (1 << 4)
+#define OMAP3430_EN_WDT1_SHIFT                          4
+#define OMAP3430_EN_32KSYNC                             (1 << 2)
+#define OMAP3430_EN_32KSYNC_SHIFT                       2
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP3430_ST_WDT2                                (1 << 5)
+#define OMAP3430_ST_WDT1                                (1 << 4)
+#define OMAP3430_ST_32KSYNC                             (1 << 2)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP3430_AUTO_WDT2                              (1 << 5)
+#define OMAP3430_AUTO_WDT2_SHIFT                        5
+#define OMAP3430_AUTO_WDT1                              (1 << 4)
+#define OMAP3430_AUTO_WDT1_SHIFT                        4
+#define OMAP3430_AUTO_GPIO1                             (1 << 3)
+#define OMAP3430_AUTO_GPIO1_SHIFT                       3
+#define OMAP3430_AUTO_32KSYNC                           (1 << 2)
+#define OMAP3430_AUTO_32KSYNC_SHIFT                     2
+#define OMAP3430_AUTO_GPT12                             (1 << 1)
+#define OMAP3430_AUTO_GPT12_SHIFT                       1
+#define OMAP3430_AUTO_GPT1                              (1 << 0)
+#define OMAP3430_AUTO_GPT1_SHIFT                        0
+
+/* CM_CLKSEL_WKUP */
+#define OMAP3430ES2_CLKSEL_USIMOCP_MASK                 (0xf << 3)
+#define OMAP3430_CLKSEL_RM_SHIFT                        1
+#define OMAP3430_CLKSEL_RM_MASK                         (0x3 << 1)
+#define OMAP3430_CLKSEL_GPT1_SHIFT                      0
+#define OMAP3430_CLKSEL_GPT1_MASK                       (1 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT                 31
+#define OMAP3430_PWRDN_CAM_SHIFT                        30
+#define OMAP3430_PWRDN_DSS1_SHIFT                       29
+#define OMAP3430_PWRDN_TV_SHIFT                         28
+#define OMAP3430_PWRDN_96M_SHIFT                        27
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT             24
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK              (0x3 << 24)
+#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT              20
+#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK               (0xf << 20)
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT        19
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK         (1 << 19)
+#define OMAP3430_EN_PERIPH_DPLL_SHIFT                   16
+#define OMAP3430_EN_PERIPH_DPLL_MASK                    (0x7 << 16)
+#define OMAP3430_PWRDN_EMU_CORE_SHIFT                   12
+#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT               8
+#define OMAP3430_CORE_DPLL_RAMPTIME_MASK                (0x3 << 8)
+#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT                4
+#define OMAP3430_CORE_DPLL_FREQSEL_MASK                 (0xf << 4)
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT          3
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK           (1 << 3)
+#define OMAP3430_EN_CORE_DPLL_SHIFT                     0
+#define OMAP3430_EN_CORE_DPLL_MASK                      (0x7 << 0)
+
+/* CM_CLKEN2_PLL */
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT                10
+#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK          (0x3 << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT          4
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK           (0xf << 4)
+#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT    3
+#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT               0
+#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK                (0x7 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP3430_ST_54M_CLK                             (1 << 5)
+#define OMAP3430_ST_12M_CLK                             (1 << 4)
+#define OMAP3430_ST_48M_CLK                             (1 << 3)
+#define OMAP3430_ST_96M_CLK                             (1 << 2)
+#define OMAP3430_ST_PERIPH_CLK                          (1 << 1)
+#define OMAP3430_ST_CORE_CLK                            (1 << 0)
+
+/* CM_IDLEST2_CKGEN */
+#define OMAP3430ES2_ST_120M_CLK_SHIFT                   1
+#define OMAP3430ES2_ST_120M_CLK_MASK                    (1 << 1)
+#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT                0
+#define OMAP3430ES2_ST_PERIPH2_CLK_MASK                 (1 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT                 3
+#define OMAP3430_AUTO_PERIPH_DPLL_MASK                  (0x7 << 3)
+#define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
+#define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
+
+/* CM_CLKSEL1_PLL */
+/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK              (0x1f << 27)
+#define OMAP3430_CORE_DPLL_MULT_SHIFT                   16
+#define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
+#define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
+#define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
+#define OMAP3430_SOURCE_54M                             (1 << 5)
+#define OMAP3430_SOURCE_48M                             (1 << 3)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
+#define OMAP3430_PERIPH_DPLL_MULT_MASK                  (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_DIV_SHIFT                  0
+#define OMAP3430_PERIPH_DPLL_DIV_MASK                   (0x7f << 0)
+
+/* CM_CLKSEL3_PLL */
+#define OMAP3430_DIV_96M_SHIFT                          0
+#define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
+
+/* CM_CLKSEL4_PLL */
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT             8
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK              (0x7ff << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT              0
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK               (0x7f << 0)
+
+/* CM_CLKSEL5_PLL */
+#define OMAP3430ES2_DIV_120M_SHIFT                      0
+#define OMAP3430ES2_DIV_120M_MASK                       (0x1f << 0)
+
+/* CM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT2_EN_SHIFT                       7
+#define OMAP3430_CLKOUT2_EN                             (1 << 7)
+#define OMAP3430_CLKOUT2_DIV_SHIFT                      3
+#define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
+#define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
+#define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
+
+/* CM_FCLKEN_DSS */
+#define OMAP3430_EN_TV                                  (1 << 2)
+#define OMAP3430_EN_TV_SHIFT                            2
+#define OMAP3430_EN_DSS2                                (1 << 1)
+#define OMAP3430_EN_DSS2_SHIFT                          1
+#define OMAP3430_EN_DSS1                                (1 << 0)
+#define OMAP3430_EN_DSS1_SHIFT                          0
+
+/* CM_ICLKEN_DSS */
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS                   (1 << 0)
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
+
+/* CM_IDLEST_DSS */
+#define OMAP3430_ST_DSS                                 (1 << 0)
+
+/* CM_AUTOIDLE_DSS */
+#define OMAP3430_AUTO_DSS                               (1 << 0)
+#define OMAP3430_AUTO_DSS_SHIFT                         0
+
+/* CM_CLKSEL_DSS */
+#define OMAP3430_CLKSEL_TV_SHIFT                        8
+#define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
+#define OMAP3430_CLKSEL_DSS1_SHIFT                      0
+#define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
+
+/* CM_SLEEPDEP_DSS specific bits */
+
+/* CM_CLKSTCTRL_DSS */
+#define OMAP3430_CLKTRCTRL_DSS_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_DSS_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_DSS */
+#define OMAP3430_CLKACTIVITY_DSS                        (1 << 0)
+
+/* CM_FCLKEN_CAM specific bits */
+
+/* CM_ICLKEN_CAM specific bits */
+
+/* CM_IDLEST_CAM */
+#define OMAP3430_ST_CAM                                 (1 << 0)
+
+/* CM_AUTOIDLE_CAM */
+#define OMAP3430_AUTO_CAM                               (1 << 0)
+#define OMAP3430_AUTO_CAM_SHIFT                         0
+
+/* CM_CLKSEL_CAM */
+#define OMAP3430_CLKSEL_CAM_SHIFT                       0
+#define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
+
+/* CM_SLEEPDEP_CAM specific bits */
+
+/* CM_CLKSTCTRL_CAM */
+#define OMAP3430_CLKTRCTRL_CAM_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_CAM_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_CAM */
+#define OMAP3430_CLKACTIVITY_CAM                        (1 << 0)
+
+/* CM_FCLKEN_PER specific bits */
+
+/* CM_ICLKEN_PER specific bits */
+
+/* CM_IDLEST_PER */
+#define OMAP3430_ST_WDT3                                (1 << 12)
+#define OMAP3430_ST_MCBSP4                              (1 << 2)
+#define OMAP3430_ST_MCBSP3                              (1 << 1)
+#define OMAP3430_ST_MCBSP2                              (1 << 0)
+
+/* CM_AUTOIDLE_PER */
+#define OMAP3430_AUTO_GPIO6                             (1 << 17)
+#define OMAP3430_AUTO_GPIO6_SHIFT                       17
+#define OMAP3430_AUTO_GPIO5                             (1 << 16)
+#define OMAP3430_AUTO_GPIO5_SHIFT                       16
+#define OMAP3430_AUTO_GPIO4                             (1 << 15)
+#define OMAP3430_AUTO_GPIO4_SHIFT                       15
+#define OMAP3430_AUTO_GPIO3                             (1 << 14)
+#define OMAP3430_AUTO_GPIO3_SHIFT                       14
+#define OMAP3430_AUTO_GPIO2                             (1 << 13)
+#define OMAP3430_AUTO_GPIO2_SHIFT                       13
+#define OMAP3430_AUTO_WDT3                              (1 << 12)
+#define OMAP3430_AUTO_WDT3_SHIFT                        12
+#define OMAP3430_AUTO_UART3                             (1 << 11)
+#define OMAP3430_AUTO_UART3_SHIFT                       11
+#define OMAP3430_AUTO_GPT9                              (1 << 10)
+#define OMAP3430_AUTO_GPT9_SHIFT                        10
+#define OMAP3430_AUTO_GPT8                              (1 << 9)
+#define OMAP3430_AUTO_GPT8_SHIFT                        9
+#define OMAP3430_AUTO_GPT7                              (1 << 8)
+#define OMAP3430_AUTO_GPT7_SHIFT                        8
+#define OMAP3430_AUTO_GPT6                              (1 << 7)
+#define OMAP3430_AUTO_GPT6_SHIFT                        7
+#define OMAP3430_AUTO_GPT5                              (1 << 6)
+#define OMAP3430_AUTO_GPT5_SHIFT                        6
+#define OMAP3430_AUTO_GPT4                              (1 << 5)
+#define OMAP3430_AUTO_GPT4_SHIFT                        5
+#define OMAP3430_AUTO_GPT3                              (1 << 4)
+#define OMAP3430_AUTO_GPT3_SHIFT                        4
+#define OMAP3430_AUTO_GPT2                              (1 << 3)
+#define OMAP3430_AUTO_GPT2_SHIFT                        3
+#define OMAP3430_AUTO_MCBSP4                            (1 << 2)
+#define OMAP3430_AUTO_MCBSP4_SHIFT                      2
+#define OMAP3430_AUTO_MCBSP3                            (1 << 1)
+#define OMAP3430_AUTO_MCBSP3_SHIFT                      1
+#define OMAP3430_AUTO_MCBSP2                            (1 << 0)
+#define OMAP3430_AUTO_MCBSP2_SHIFT                      0
+
+/* CM_CLKSEL_PER */
+#define OMAP3430_CLKSEL_GPT9_MASK                       (1 << 7)
+#define OMAP3430_CLKSEL_GPT9_SHIFT                      7
+#define OMAP3430_CLKSEL_GPT8_MASK                       (1 << 6)
+#define OMAP3430_CLKSEL_GPT8_SHIFT                      6
+#define OMAP3430_CLKSEL_GPT7_MASK                       (1 << 5)
+#define OMAP3430_CLKSEL_GPT7_SHIFT                      5
+#define OMAP3430_CLKSEL_GPT6_MASK                       (1 << 4)
+#define OMAP3430_CLKSEL_GPT6_SHIFT                      4
+#define OMAP3430_CLKSEL_GPT5_MASK                       (1 << 3)
+#define OMAP3430_CLKSEL_GPT5_SHIFT                      3
+#define OMAP3430_CLKSEL_GPT4_MASK                       (1 << 2)
+#define OMAP3430_CLKSEL_GPT4_SHIFT                      2
+#define OMAP3430_CLKSEL_GPT3_MASK                       (1 << 1)
+#define OMAP3430_CLKSEL_GPT3_SHIFT                      1
+#define OMAP3430_CLKSEL_GPT2_MASK                       (1 << 0)
+#define OMAP3430_CLKSEL_GPT2_SHIFT                      0
+
+/* CM_SLEEPDEP_PER specific bits */
+#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2                (1 << 2)
+
+/* CM_CLKSTCTRL_PER */
+#define OMAP3430_CLKTRCTRL_PER_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_PER_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_PER */
+#define OMAP3430_CLKACTIVITY_PER                        (1 << 0)
+
+/* CM_CLKSEL1_EMU */
+#define OMAP3430_DIV_DPLL4_SHIFT                        24
+#define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
+#define OMAP3430_DIV_DPLL3_SHIFT                        16
+#define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
+#define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11
+#define OMAP3430_CLKSEL_TRACECLK_MASK                   (0x7 << 11)
+#define OMAP3430_CLKSEL_PCLK_SHIFT                      8
+#define OMAP3430_CLKSEL_PCLK_MASK                       (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLKX2_SHIFT                    6
+#define OMAP3430_CLKSEL_PCLKX2_MASK                     (0x3 << 6)
+#define OMAP3430_CLKSEL_ATCLK_SHIFT                     4
+#define OMAP3430_CLKSEL_ATCLK_MASK                      (0x3 << 4)
+#define OMAP3430_TRACE_MUX_CTRL_SHIFT                   2
+#define OMAP3430_TRACE_MUX_CTRL_MASK                    (0x3 << 2)
+#define OMAP3430_MUX_CTRL_SHIFT                         0
+#define OMAP3430_MUX_CTRL_MASK                          (0x3 << 0)
+
+/* CM_CLKSTCTRL_EMU */
+#define OMAP3430_CLKTRCTRL_EMU_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_EMU_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_EMU */
+#define OMAP3430_CLKACTIVITY_EMU                        (1 << 0)
+
+/* CM_CLKSEL2_EMU specific bits */
+#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT               8
+#define OMAP3430_CORE_DPLL_EMU_MULT_MASK                (0x7ff << 8)
+#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT                0
+#define OMAP3430_CORE_DPLL_EMU_DIV_MASK                 (0x7f << 0)
+
+/* CM_CLKSEL3_EMU specific bits */
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT             8
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK              (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT              0
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK               (0x7f << 0)
+
+/* CM_POLCTRL */
+#define OMAP3430_CLKOUT2_POL                            (1 << 0)
+
+/* CM_IDLEST_NEON */
+#define OMAP3430_ST_NEON                                (1 << 0)
+
+/* CM_CLKSTCTRL_NEON */
+#define OMAP3430_CLKTRCTRL_NEON_SHIFT                   0
+#define OMAP3430_CLKTRCTRL_NEON_MASK                    (0x3 << 0)
+
+/* CM_FCLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST2_SHIFT                   1
+#define OMAP3430ES2_EN_USBHOST2_MASK                    (1 << 1)
+#define OMAP3430ES2_EN_USBHOST1_SHIFT                   0
+#define OMAP3430ES2_EN_USBHOST1_MASK                    (1 << 0)
+
+/* CM_ICLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST_SHIFT                    0
+#define OMAP3430ES2_EN_USBHOST_MASK                     (1 << 0)
+
+/* CM_IDLEST_USBHOST */
+
+/* CM_AUTOIDLE_USBHOST */
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
+#define OMAP3430ES2_AUTO_USBHOST_MASK                   (1 << 0)
+
+/* CM_SLEEPDEP_USBHOST */
+#define OMAP3430ES2_EN_MPU_SHIFT                        1
+#define OMAP3430ES2_EN_MPU_MASK                         (1 << 1)
+#define OMAP3430ES2_EN_IVA2_SHIFT                       2
+#define OMAP3430ES2_EN_IVA2_MASK                        (1 << 2)
+
+/* CM_CLKSTCTRL_USBHOST */
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT             0
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK              (3 << 0)
+
+
+
+#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
new file mode 100644
index 000000000000..8489f3029fed
--- /dev/null
+++ b/arch/arm/mach-omap2/cm.h
@@ -0,0 +1,124 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+#define __ARCH_ASM_MACH_OMAP2_CM_H
+
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_CM_REGADDR(module, reg)                                    \
+        (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
+#else
+#define OMAP2420_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+#define OMAP34XX_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+
+#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific CM registers from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* Common between 24xx and 34xx */
+
+#define CM_FCLKEN                                       0x0000
+#define CM_FCLKEN1                                      CM_FCLKEN
+#define CM_CLKEN                                        CM_FCLKEN
+#define CM_ICLKEN                                       0x0010
+#define CM_ICLKEN1                                      CM_ICLKEN
+#define CM_ICLKEN2                                      0x0014
+#define CM_ICLKEN3                                      0x0018
+#define CM_IDLEST                                       0x0020
+#define CM_IDLEST1                                      CM_IDLEST
+#define CM_IDLEST2                                      0x0024
+#define CM_AUTOIDLE                                     0x0030
+#define CM_AUTOIDLE1                                    CM_AUTOIDLE
+#define CM_AUTOIDLE2                                    0x0034
+#define CM_AUTOIDLE3                                    0x0038
+#define CM_CLKSEL                                       0x0040
+#define CM_CLKSEL1                                      CM_CLKSEL
+#define CM_CLKSEL2                                      0x0044
+#define CM_CLKSTCTRL                                    0x0048
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_CM_FCLKEN2                             0x0004
+#define OMAP24XX_CM_ICLKEN4                             0x001c
+#define OMAP24XX_CM_AUTOIDLE4                           0x003c
+
+#define OMAP2430_CM_IDLEST3                             0x0028
+
+#define OMAP3430_CM_CLKEN_PLL                           0x0004
+#define OMAP3430ES2_CM_CLKEN2                           0x0004
+#define OMAP3430ES2_CM_FCLKEN3                          0x0008
+#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST                             0x004c
+#define OMAP3430ES2_CM_CLKSEL4                          0x004c
+#define OMAP3430ES2_CM_CLKSEL5                          0x0050
+#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
+#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+        __raw_writel(val, OMAP_CM_REGADDR(module, idx));
+}
+
+static inline u32 cm_read_mod_reg(s16 module, s16 idx)
+{
+        return __raw_readl(OMAP_CM_REGADDR(module, idx));
+}
+#endif
+
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT                           0
+#define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT                               0
+#define OMAP_EN_GFX                                     (1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX                                     (1 << 0)
+
+
+#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
new file mode 100644
index 000000000000..a5d86a49c213
--- /dev/null
+++ b/arch/arm/mach-omap2/control.c
@@ -0,0 +1,74 @@
+/*
+ * OMAP2/3 System Control Module register access
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/control.h>
+
+static u32 omap2_ctrl_base;
+
+#define OMAP_CTRL_REGADDR(reg)  (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
+                                                                + (reg))
+
+void omap_ctrl_base_set(u32 base)
+{
+        omap2_ctrl_base = base;
+}
+
+u32 omap_ctrl_base_get(void)
+{
+        return omap2_ctrl_base;
+}
+
+u8 omap_ctrl_readb(u16 offset)
+{
+        return __raw_readb(OMAP_CTRL_REGADDR(offset));
+}
+
+u16 omap_ctrl_readw(u16 offset)
+{
+        return __raw_readw(OMAP_CTRL_REGADDR(offset));
+}
+
+u32 omap_ctrl_readl(u16 offset)
+{
+        return __raw_readl(OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writeb(u8 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writew(u16 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writel(u32 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writel(val, OMAP_CTRL_REGADDR(offset));
+}
+
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5a4cc2076a7d..02cede295e89 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -69,7 +69,7 @@ static void __iomem *gpmc_base =
 static void __iomem *gpmc_cs_base =
         (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
 
-static struct clk *gpmc_l3_clk;
+static struct clk *gpmc_fck;
 
 static void gpmc_write_reg(int idx, u32 val)
 {
@@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx)
         return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
 }
 
-/* TODO: Add support for gpmc_fck to clock framework and use it */
 unsigned long gpmc_get_fclk_period(void)
 {
         /* In picoseconds */
-        return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
+        return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
 }
 
 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -398,8 +397,11 @@ void __init gpmc_init(void)
 {
         u32 l;
 
-        gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
-        BUG_ON(IS_ERR(gpmc_l3_clk));
+        gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck))
+                WARN_ON(1);
+        else
+                clk_enable(gpmc_fck);
 
         l = gpmc_read_reg(GPMC_REVISION);
         printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 3e5d8cd4ea4f..12479081881a 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -27,11 +27,16 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
 
-#include "prcm-regs.h"
+#include "prm.h"
+
 #include "memory.h"
+#include "sdrc.h"
 
+unsigned long omap2_sdrc_base;
+unsigned long omap2_sms_base;
 
 static struct memory_timings mem_timings;
+static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
 
 u32 omap2_memory_get_slow_dll_ctrl(void)
 {
@@ -48,12 +53,60 @@ u32 omap2_memory_get_type(void)
         return mem_timings.m_type;
 }
 
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+        /* dlla and dllb are a set */
+        u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+
+        if ((dll_state & (1 << 2)) == (1 << 2))
+                return 1;
+        else
+                return 0;
+}
+
+/*
+ * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
+ * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
+ * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ */
+u32 omap2_reprogram_sdrc(u32 level, u32 force)
+{
+        u32 dll_ctrl, m_type;
+        u32 prev = curr_perf_level;
+        unsigned long flags;
+
+        if ((curr_perf_level == level) && !force)
+                return prev;
+
+        if (level == CORE_CLK_SRC_DPLL) {
+                dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+        } else if (level == CORE_CLK_SRC_DPLL_X2) {
+                dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+        } else {
+                return prev;
+        }
+
+        m_type = omap2_memory_get_type();
+
+        local_irq_save(flags);
+        __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+        omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
+        curr_perf_level = level;
+        local_irq_restore(flags);
+
+        return prev;
+}
+
 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
 {
         unsigned long dll_cnt;
         u32 fast_dll = 0;
 
-        mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
+        mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
 
         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
          * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -73,11 +126,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
                 mem_timings.dll_mode = M_LOCK;
 
         if (mem_timings.base_cs == 0) {
-                fast_dll = SDRC_DLLA_CTRL;
-                dll_cnt = SDRC_DLLA_STATUS & 0xff00;
+                fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
+                dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
         } else {
-                fast_dll = SDRC_DLLB_CTRL;
-                dll_cnt = SDRC_DLLB_STATUS & 0xff00;
+                fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
+                dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
         }
         if (force_lock_to_unlock_mode) {
                 fast_dll &= ~0xff00;
@@ -106,14 +159,13 @@ void __init omap2_init_memory(void)
 {
         u32 l;
 
-        l = SMS_SYSCONFIG;
+        l = sms_read_reg(SMS_SYSCONFIG);
         l &= ~(0x3 << 3);
         l |= (0x2 << 3);
-        SMS_SYSCONFIG = l;
+        sms_write_reg(l, SMS_SYSCONFIG);
 
-        l = SDRC_SYSCONFIG;
+        l = sdrc_read_reg(SDRC_SYSCONFIG);
         l &= ~(0x3 << 3);
         l |= (0x2 << 3);
-        SDRC_SYSCONFIG = l;
-
+        sdrc_write_reg(l, SDRC_SYSCONFIG);
 }
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index d212eea83a05..9a280b50a893 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
 extern u32 omap2_memory_get_slow_dll_ctrl(void);
 extern u32 omap2_memory_get_fast_dll_ctrl(void);
 extern u32 omap2_memory_get_type(void);
+u32 omap2_dll_force_needed(void);
+u32 omap2_reprogram_sdrc(u32 level, u32 force);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 05750975d746..930770012a75 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,11 +1,12 @@
 /*
  * linux/arch/arm/mach-omap2/mux.c
  *
- * OMAP1 pin multiplexing configurations
+ * OMAP2 pin multiplexing configurations
  *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,13 +29,17 @@
 #include <asm/io.h>
 #include <linux/spinlock.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
+static struct omap_mux_cfg arch_mux_cfg;
+
 /* NOTE: See mux.h for the enumeration */
 
-struct pin_config __initdata_or_module omap24xx_pins[] = {
+#ifdef CONFIG_ARCH_OMAP24XX
+static struct pin_config __initdata_or_module omap24xx_pins[] = {
 /*
  *      description                     mux     mux     pull    pull    debug
  *                                      offset  mode    ena     type
@@ -77,7 +82,12 @@ MUX_CFG_24XX("AA12_242X_GPIO17",	0x0e9,	3,	0,	0,	1)
 MUX_CFG_24XX("AA8_242X_GPIO58",         0x0ea,  3,      0,      0,      1)
 MUX_CFG_24XX("Y20_24XX_GPIO60",         0x12c,  3,      0,      0,      1)
 MUX_CFG_24XX("W4__24XX_GPIO74",         0x0f2,  3,      0,      0,      1)
+MUX_CFG_24XX("N15_24XX_GPIO85",         0x103,  3,      0,      0,      1)
 MUX_CFG_24XX("M15_24XX_GPIO92",         0x10a,  3,      0,      0,      1)
+MUX_CFG_24XX("P20_24XX_GPIO93",         0x10b,  3,      0,      0,      1)
+MUX_CFG_24XX("P18_24XX_GPIO95",         0x10d,  3,      0,      0,      1)
+MUX_CFG_24XX("M18_24XX_GPIO96",         0x10e,  3,      0,      0,      1)
+MUX_CFG_24XX("L14_24XX_GPIO97",         0x10f,  3,      0,      0,      1)
 MUX_CFG_24XX("J15_24XX_GPIO99",         0x113,  3,      1,      1,      1)
 MUX_CFG_24XX("V14_24XX_GPIO117",        0x128,  3,      1,      0,      1)
 MUX_CFG_24XX("P14_24XX_GPIO125",        0x140,  3,      1,      1,      1)
@@ -102,9 +112,6 @@ MUX_CFG_24XX("G4_242X_DMAREQ3",		0x073,	2,	0,	0,	1)
 MUX_CFG_24XX("D3_242X_DMAREQ4",         0x072,  2,      0,      0,      1)
 MUX_CFG_24XX("E3_242X_DMAREQ5",         0x071,  2,      0,      0,      1)
 
-/* TSC IRQ */
-MUX_CFG_24XX("P20_24XX_TSC_IRQ",        0x108,  0,      0,      0,      1)
-
 /* UART3 */
 MUX_CFG_24XX("K15_24XX_UART3_TX",       0x118,  0,      0,      0,      1)
 MUX_CFG_24XX("K14_24XX_UART3_RX",       0x119,  0,      0,      0,      1)
@@ -167,12 +174,108 @@ MUX_CFG_24XX("B3__24XX_KBR5",		0x30,	3,	1,	1,	1)
 MUX_CFG_24XX("AA4_24XX_KBC2",           0xe7,   3,      0,      0,      1)
 MUX_CFG_24XX("B13_24XX_KBC6",           0x110,  3,      0,      0,      1)
 
+/* 2430 USB */
+MUX_CFG_24XX("AD9_2430_USB0_PUEN",      0x133,  4,      0,      0,      1)
+MUX_CFG_24XX("Y11_2430_USB0_VP",        0x134,  4,      0,      0,      1)
+MUX_CFG_24XX("AD7_2430_USB0_VM",        0x135,  4,      0,      0,      1)
+MUX_CFG_24XX("AE7_2430_USB0_RCV",       0x136,  4,      0,      0,      1)
+MUX_CFG_24XX("AD4_2430_USB0_TXEN",      0x137,  4,      0,      0,      1)
+MUX_CFG_24XX("AF9_2430_USB0_SE0",       0x138,  4,      0,      0,      1)
+MUX_CFG_24XX("AE6_2430_USB0_DAT",       0x139,  4,      0,      0,      1)
+MUX_CFG_24XX("AD24_2430_USB1_SE0",      0x107,  2,      0,      0,      1)
+MUX_CFG_24XX("AB24_2430_USB1_RCV",      0x108,  2,      0,      0,      1)
+MUX_CFG_24XX("Y25_2430_USB1_TXEN",      0x109,  2,      0,      0,      1)
+MUX_CFG_24XX("AA26_2430_USB1_DAT",      0x10A,  2,      0,      0,      1)
+
+/* 2430 HS-USB */
+MUX_CFG_24XX("AD9_2430_USB0HS_DATA3",   0x133,  0,      0,      0,      1)
+MUX_CFG_24XX("Y11_2430_USB0HS_DATA4",   0x134,  0,      0,      0,      1)
+MUX_CFG_24XX("AD7_2430_USB0HS_DATA5",   0x135,  0,      0,      0,      1)
+MUX_CFG_24XX("AE7_2430_USB0HS_DATA6",   0x136,  0,      0,      0,      1)
+MUX_CFG_24XX("AD4_2430_USB0HS_DATA2",   0x137,  0,      0,      0,      1)
+MUX_CFG_24XX("AF9_2430_USB0HS_DATA0",   0x138,  0,      0,      0,      1)
+MUX_CFG_24XX("AE6_2430_USB0HS_DATA1",   0x139,  0,      0,      0,      1)
+MUX_CFG_24XX("AE8_2430_USB0HS_CLK",     0x13A,  0,      0,      0,      1)
+MUX_CFG_24XX("AD8_2430_USB0HS_DIR",     0x13B,  0,      0,      0,      1)
+MUX_CFG_24XX("AE5_2430_USB0HS_STP",     0x13c,  0,      1,      1,      1)
+MUX_CFG_24XX("AE9_2430_USB0HS_NXT",     0x13D,  0,      0,      0,      1)
+MUX_CFG_24XX("AC7_2430_USB0HS_DATA7",   0x13E,  0,      0,      0,      1)
+
+/* 2430 McBSP */
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX",    0x012E, 1,      0,      0,      1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX",    0x012F, 1,      0,      0,      1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX",     0x0130, 1,      0,      0,      1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR",     0x0131, 1,      0,      0,      1)
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0,      0,      0,      1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0,      0,      0,      1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0,      0,      0,      1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0,      0,      0,      1)
 };
 
-int __init omap2_mux_init(void)
+#define OMAP24XX_PINS_SZ        ARRAY_SIZE(omap24xx_pins)
+
+#else
+#define omap24xx_pins           NULL
+#define OMAP24XX_PINS_SZ        0
+#endif  /* CONFIG_ARCH_OMAP24XX */
+
+#define OMAP24XX_PULL_ENA       (1 << 3)
+#define OMAP24XX_PULL_UP        (1 << 4)
+
+#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
+void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
 {
-        omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
+        u16 orig;
+        u8 warn = 0, debug = 0;
+
+        orig = omap_ctrl_readb(cfg->mux_reg);
+
+#ifdef  CONFIG_OMAP_MUX_DEBUG
+        debug = cfg->debug;
+#endif
+        warn = (orig != reg);
+        if (debug || warn)
+                printk(KERN_WARNING
+                        "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
+                        cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
+                        orig, reg);
+}
+#else
+#define omap2_cfg_debug(x, y)   do {} while (0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP24XX
+int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
+{
+        static DEFINE_SPINLOCK(mux_spin_lock);
+        unsigned long flags;
+        u8 reg = 0;
+
+        spin_lock_irqsave(&mux_spin_lock, flags);
+        reg |= cfg->mask & 0x7;
+        if (cfg->pull_val)
+                reg |= OMAP24XX_PULL_ENA;
+        if (cfg->pu_pd_val)
+                reg |= OMAP24XX_PULL_UP;
+        omap2_cfg_debug(cfg, reg);
+        omap_ctrl_writeb(reg, cfg->mux_reg);
+        spin_unlock_irqrestore(&mux_spin_lock, flags);
+
         return 0;
 }
+#else
+#define omap24xx_cfg_reg        0
+#endif
+
+int __init omap2_mux_init(void)
+{
+        if (cpu_is_omap24xx()) {
+                arch_mux_cfg.pins       = omap24xx_pins;
+                arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
+        }
+
+        return omap_mux_register(&arch_mux_cfg);
+}
 
 #endif
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
deleted file mode 100644
index 2494091a078b..000000000000
--- a/arch/arm/mach-omap2/pm-domain.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/pm-domain.c
- *
- * Power domain functions for OMAP2
- *
- * Copyright (C) 2006 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * Some code based on earlier OMAP2 sample PM code
- * Copyright (C) 2005 Texas Instruments, Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/io.h>
-
-#include "prcm-regs.h"
-
-/* Power domain offsets */
-#define PM_MPU_OFFSET                   0x100
-#define PM_CORE_OFFSET                  0x200
-#define PM_GFX_OFFSET                   0x300
-#define PM_WKUP_OFFSET                  0x400           /* Autoidle only */
-#define PM_PLL_OFFSET                   0x500           /* Autoidle only */
-#define PM_DSP_OFFSET                   0x800
-#define PM_MDM_OFFSET                   0xc00
-
-/* Power domain wake-up dependency control register */
-#define PM_WKDEP_OFFSET                 0xc8
-#define         EN_MDM                  (1 << 5)
-#define         EN_WKUP                 (1 << 4)
-#define         EN_GFX                  (1 << 3)
-#define         EN_DSP                  (1 << 2)
-#define         EN_MPU                  (1 << 1)
-#define         EN_CORE                 (1 << 0)
-
-/* Core power domain state transition control register */
-#define PM_PWSTCTRL_OFFSET              0xe0
-#define         FORCESTATE              (1 << 18)       /* Only for DSP & GFX */
-#define         MEM4RETSTATE            (1 << 6)
-#define         MEM3RETSTATE            (1 << 5)
-#define         MEM2RETSTATE            (1 << 4)
-#define         MEM1RETSTATE            (1 << 3)
-#define         LOGICRETSTATE           (1 << 2)        /* Logic is retained */
-#define         POWERSTATE_OFF          0x3
-#define         POWERSTATE_RETENTION    0x1
-#define         POWERSTATE_ON           0x0
-
-/* Power domain state register */
-#define PM_PWSTST_OFFSET                0xe4
-
-/* Hardware supervised state transition control register */
-#define CM_CLKSTCTRL_OFFSET             0x48
-#define         AUTOSTAT_MPU            (1 << 0)        /* MPU */
-#define         AUTOSTAT_DSS            (1 << 2)        /* Core */
-#define         AUTOSTAT_L4             (1 << 1)        /* Core */
-#define         AUTOSTAT_L3             (1 << 0)        /* Core */
-#define         AUTOSTAT_GFX            (1 << 0)        /* GFX */
-#define         AUTOSTAT_IVA            (1 << 8)        /* 2420 IVA in DSP domain */
-#define         AUTOSTAT_DSP            (1 << 0)        /* DSP */
-#define         AUTOSTAT_MDM            (1 << 0)        /* MDM */
-
-/* Automatic control of interface clock idling */
-#define CM_AUTOIDLE1_OFFSET             0x30
-#define CM_AUTOIDLE2_OFFSET             0x34            /* Core only */
-#define CM_AUTOIDLE3_OFFSET             0x38            /* Core only */
-#define CM_AUTOIDLE4_OFFSET             0x3c            /* Core only */
-#define         AUTO_54M(x)             (((x) & 0x3) << 6)
-#define         AUTO_96M(x)             (((x) & 0x3) << 2)
-#define         AUTO_DPLL(x)            (((x) & 0x3) << 0)
-#define         AUTO_STOPPED            0x3
-#define         AUTO_BYPASS_FAST        0x2             /* DPLL only */
-#define         AUTO_BYPASS_LOW_POWER   0x1             /* DPLL only */
-#define         AUTO_DISABLED           0x0
-
-/* Voltage control PRCM_VOLTCTRL bits */
-#define         AUTO_EXTVOLT            (1 << 15)
-#define         FORCE_EXTVOLT           (1 << 14)
-#define         SETOFF_LEVEL(x)         (((x) & 0x3) << 12)
-#define         MEMRETCTRL              (1 << 8)
-#define         SETRET_LEVEL(x)         (((x) & 0x3) << 6)
-#define         VOLT_LEVEL(x)           (((x) & 0x3) << 0)
-
-#define OMAP24XX_PRCM_VBASE     IO_ADDRESS(OMAP24XX_PRCM_BASE)
-#define prcm_readl(r)           __raw_readl(OMAP24XX_PRCM_VBASE + (r))
-#define prcm_writel(v, r)       __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
-
-static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
-{
-        return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
-}
-
-static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
-}
-
-static u32 pmdomain_get_powerstate(int domain_offset)
-{
-        return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_powerstate(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autocontrol(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autoidle1(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle2(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle3(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle4(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
-}
-
-static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
-}
-
-/*
- * Configures power management domains to idle clocks automatically.
- */
-void pmdomain_set_autoidle(void)
-{
-        u32 val;
-
-        /* Set PLL auto stop for 54M, 96M & DPLL */
-        pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
-                                     AUTO_96M(AUTO_STOPPED) |
-                                     AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
-
-        /* External clock input control
-         * REVISIT: Should this be in clock framework?
-         */
-        PRCM_CLKSRC_CTRL |= (0x3 << 3);
-
-        /* Configure number of 32KHz clock cycles for sys_clk */
-        PRCM_CLKSSETUP = 0x00ff;
-
-        /* Configure automatic voltage transition */
-        PRCM_VOLTSETUP = 0;
-        val = PRCM_VOLTCTRL;
-        val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
-        val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
-        PRCM_VOLTCTRL = val;
-
-        /* Disable emulation tools functional clock */
-        PRCM_CLKEMUL_CTRL = 0x0;
-
-        /* Set core memory retention state */
-        val = pmdomain_get_powerstate(PM_CORE_OFFSET);
-        if (cpu_is_omap2420()) {
-                val &= ~(0x7 << 3);
-                val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
-        } else {
-                val &= ~(0xf << 3);
-                val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
-                        MEM1RETSTATE);
-        }
-        pmdomain_set_powerstate(val, PM_CORE_OFFSET);
-
-        /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
-        val = SMS_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3) | (1 << 0);
-        SMS_SYSCONFIG |= val;
-
-        val = SDRC_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3);
-        SDRC_SYSCONFIG = val;
-
-        /* Configure L3 interface for smart idle.
-         * REVISIT: Enable autoidle bit0 ?
-         */
-        val = GPMC_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3) | (1 << 0);
-        GPMC_SYSCONFIG = val;
-
-        pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
-                                PM_MPU_OFFSET);
-        pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
-        if (!cpu_is_omap2420())
-                pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
-
-        /* Assume suspend function has saved the state for DSP and GFX */
-        pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
-        pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
-
-#if 0
-        /* REVISIT: Internal USB needs special handling */
-        force_standby_usb();
-        if (cpu_is_omap2430())
-                force_hsmmc();
-        sdram_self_refresh_on_idle_req(1);
-#endif
-
-        /* Enable clock auto control for all domains.
-         * Note that CORE domain includes also DSS, L4 & L3.
-         */
-        pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
-        pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
-        pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
-                                       PM_CORE_OFFSET);
-        if (cpu_is_omap2420())
-                pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
-                                               PM_DSP_OFFSET);
-        else {
-                pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
-                pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
-        }
-
-        /* Enable clock autoidle for all domains */
-        pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
-        if (cpu_is_omap2420()) {
-                pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
-        } else {
-                pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
-                pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
-        }
-        pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
-        pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
-}
-
-/*
- * Initializes power domains by removing wake-up dependencies and powering
- * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
- * must re-enable DSP and GFX when used.
- */
-void __init pmdomain_init(void)
-{
-        /* Remove all domain wakeup dependencies */
-        pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
-        pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
-        pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
-        pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
-        if (cpu_is_omap2430())
-                pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
-
-        /* Power down DSP and GFX */
-        pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
-        pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
-}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index baf7d82b458b..aad781dcf1b1 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -23,6 +23,7 @@
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/delay.h>
+#include <linux/clk.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -36,8 +37,6 @@
 #include <asm/arch/sram.h>
 #include <asm/arch/pm.h>
 
-#include "prcm-regs.h"
-
 static struct clk *vclk;
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
@@ -78,251 +77,8 @@ static int omap2_pm_prepare(void)
         return 0;
 }
 
-#define INT0_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) |    \
-                        OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) |     \
-                        OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
-
-#define INT1_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
-
-#define INT2_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) |     \
-                        OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) |      \
-                        OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
-
-#define preg(reg)       printk("%s\t(0x%p):\t0x%08x\n", #reg, &reg, reg);
-
-static void omap2_pm_debug(char * desc)
-{
-        printk("%s:\n", desc);
-
-        preg(CM_CLKSTCTRL_MPU);
-        preg(CM_CLKSTCTRL_CORE);
-        preg(CM_CLKSTCTRL_GFX);
-        preg(CM_CLKSTCTRL_DSP);
-        preg(CM_CLKSTCTRL_MDM);
-
-        preg(PM_PWSTCTRL_MPU);
-        preg(PM_PWSTCTRL_CORE);
-        preg(PM_PWSTCTRL_GFX);
-        preg(PM_PWSTCTRL_DSP);
-        preg(PM_PWSTCTRL_MDM);
-
-        preg(PM_PWSTST_MPU);
-        preg(PM_PWSTST_CORE);
-        preg(PM_PWSTST_GFX);
-        preg(PM_PWSTST_DSP);
-        preg(PM_PWSTST_MDM);
-
-        preg(CM_AUTOIDLE1_CORE);
-        preg(CM_AUTOIDLE2_CORE);
-        preg(CM_AUTOIDLE3_CORE);
-        preg(CM_AUTOIDLE4_CORE);
-        preg(CM_AUTOIDLE_WKUP);
-        preg(CM_AUTOIDLE_PLL);
-        preg(CM_AUTOIDLE_DSP);
-        preg(CM_AUTOIDLE_MDM);
-
-        preg(CM_ICLKEN1_CORE);
-        preg(CM_ICLKEN2_CORE);
-        preg(CM_ICLKEN3_CORE);
-        preg(CM_ICLKEN4_CORE);
-        preg(CM_ICLKEN_GFX);
-        preg(CM_ICLKEN_WKUP);
-        preg(CM_ICLKEN_DSP);
-        preg(CM_ICLKEN_MDM);
-
-        preg(CM_IDLEST1_CORE);
-        preg(CM_IDLEST2_CORE);
-        preg(CM_IDLEST3_CORE);
-        preg(CM_IDLEST4_CORE);
-        preg(CM_IDLEST_GFX);
-        preg(CM_IDLEST_WKUP);
-        preg(CM_IDLEST_CKGEN);
-        preg(CM_IDLEST_DSP);
-        preg(CM_IDLEST_MDM);
-
-        preg(RM_RSTST_MPU);
-        preg(RM_RSTST_GFX);
-        preg(RM_RSTST_WKUP);
-        preg(RM_RSTST_DSP);
-        preg(RM_RSTST_MDM);
-
-        preg(PM_WKDEP_MPU);
-        preg(PM_WKDEP_CORE);
-        preg(PM_WKDEP_GFX);
-        preg(PM_WKDEP_DSP);
-        preg(PM_WKDEP_MDM);
-
-        preg(CM_FCLKEN_WKUP);
-        preg(CM_ICLKEN_WKUP);
-        preg(CM_IDLEST_WKUP);
-        preg(CM_AUTOIDLE_WKUP);
-        preg(CM_CLKSEL_WKUP);
-
-        preg(PM_WKEN_WKUP);
-        preg(PM_WKST_WKUP);
-}
-
-static inline void omap2_pm_save_registers(void)
-{
-        /* Save interrupt registers */
-        OMAP24XX_SAVE(INTC_MIR0);
-        OMAP24XX_SAVE(INTC_MIR1);
-        OMAP24XX_SAVE(INTC_MIR2);
-
-        /* Save power control registers */
-        OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
-
-        /* Save power state registers */
-        OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
-        OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
-        OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
-        OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
-        OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
-
-        /* Save autoidle registers */
-        OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
-        OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
-        OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
-        OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
-
-        /* Save idle state registers */
-        OMAP24XX_SAVE(CM_IDLEST1_CORE);
-        OMAP24XX_SAVE(CM_IDLEST2_CORE);
-        OMAP24XX_SAVE(CM_IDLEST3_CORE);
-        OMAP24XX_SAVE(CM_IDLEST4_CORE);
-        OMAP24XX_SAVE(CM_IDLEST_GFX);
-        OMAP24XX_SAVE(CM_IDLEST_WKUP);
-        OMAP24XX_SAVE(CM_IDLEST_CKGEN);
-        OMAP24XX_SAVE(CM_IDLEST_DSP);
-        OMAP24XX_SAVE(CM_IDLEST_MDM);
-
-        /* Save clock registers */
-        OMAP24XX_SAVE(CM_FCLKEN1_CORE);
-        OMAP24XX_SAVE(CM_FCLKEN2_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN1_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN2_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN3_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN4_CORE);
-}
-
-static inline void omap2_pm_restore_registers(void)
-{
-        /* Restore clock state registers */
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
-
-        /* Restore power state registers */
-        OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
-
-        /* Restore idle state registers */
-        OMAP24XX_RESTORE(CM_IDLEST1_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST2_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST3_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST4_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST_GFX);
-        OMAP24XX_RESTORE(CM_IDLEST_WKUP);
-        OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
-        OMAP24XX_RESTORE(CM_IDLEST_DSP);
-        OMAP24XX_RESTORE(CM_IDLEST_MDM);
-
-        /* Restore autoidle registers */
-        OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
-
-        /* Restore clock registers */
-        OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
-        OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
-
-        /* REVISIT: Clear interrupts here */
-
-        /* Restore interrupt registers */
-        OMAP24XX_RESTORE(INTC_MIR0);
-        OMAP24XX_RESTORE(INTC_MIR1);
-        OMAP24XX_RESTORE(INTC_MIR2);
-}
-
 static int omap2_pm_suspend(void)
 {
-        int processor_type = 0;
-
-        /* REVISIT: 0x21 or 0x26? */
-        if (cpu_is_omap2420())
-                processor_type = 0x21;
-
-        if (!processor_type)
-                return -ENOTSUPP;
-
-        local_irq_disable();
-        local_fiq_disable();
-
-        omap2_pm_save_registers();
-
-        /* Disable interrupts except for the wake events */
-        INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
-        INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
-        INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
-
-        pmdomain_set_autoidle();
-
-        /* Clear old wake-up events */
-        PM_WKST1_CORE = 0;
-        PM_WKST2_CORE = 0;
-        PM_WKST_WKUP = 0;
-
-        /* Enable wake-up events */
-        PM_WKEN1_CORE = (1 << 22) | (1 << 21);  /* UART1 & 2 */
-        PM_WKEN2_CORE = (1 << 2);               /* UART3 */
-        PM_WKEN_WKUP = (1 << 2) | (1 << 0);     /* GPIO & GPT1 */
-
-        /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
-         * in the SRAM suspend code */
-        CM_FCLKEN1_CORE = 0;
-        CM_FCLKEN2_CORE = 0;
-        CM_ICLKEN1_CORE = 0;
-        CM_ICLKEN3_CORE = 0;
-        CM_ICLKEN4_CORE = 0;
-
-        omap2_pm_debug("Status before suspend");
-
-        /* Must wait for serial buffers to clear */
-        mdelay(200);
-
-        /* Jump to SRAM suspend code
-         * REVISIT: When is this SDRC_DLLB_CTRL?
-         */
-        omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
-
-        /* Back from sleep */
-        omap2_pm_restore_registers();
-
-        local_fiq_enable();
-        local_irq_enable();
-
         return 0;
 }
 
@@ -357,30 +113,6 @@ static struct platform_suspend_ops omap_pm_ops = {
 
 int __init omap2_pm_init(void)
 {
-        printk("Power Management for TI OMAP.\n");
-
-        vclk = clk_get(NULL, "virt_prcm_set");
-        if (IS_ERR(vclk)) {
-                printk(KERN_ERR "Could not get PM vclk\n");
-                return -ENODEV;
-        }
-
-        /*
-         * We copy the assembler sleep/wakeup routines to SRAM.
-         * These routines need to be in SRAM as that's the only
-         * memory the MPU can see when it wakes up.
-         */
-        omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
-                                         omap24xx_idle_loop_suspend_sz);
-
-        omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
-                                            omap24xx_cpu_suspend_sz);
-
-        suspend_set_ops(&omap_pm_ops);
-        pm_idle = omap2_pm_idle;
-
-        pmdomain_init();
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
new file mode 100644
index 000000000000..cacb34086e35
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -0,0 +1,317 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+
+/*
+ * OMAP2/3 PRCM base and module definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
+#define OCP_MOD                                         0x000
+#define MPU_MOD                                         0x100
+#define CORE_MOD                                        0x200
+#define GFX_MOD                                         0x300
+#define WKUP_MOD                                        0x400
+#define PLL_MOD                                         0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_DSP_MOD                                0x800
+
+#define OMAP2430_MDM_MOD                                0xc00
+
+/* IVA2 module is < base on 3430 */
+#define OMAP3430_IVA2_MOD                               -0x800
+#define OMAP3430ES2_SGX_MOD                             GFX_MOD
+#define OMAP3430_CCR_MOD                                PLL_MOD
+#define OMAP3430_DSS_MOD                                0x600
+#define OMAP3430_CAM_MOD                                0x700
+#define OMAP3430_PER_MOD                                0x800
+#define OMAP3430_EMU_MOD                                0x900
+#define OMAP3430_GR_MOD                                 0xa00
+#define OMAP3430_NEON_MOD                               0xb00
+#define OMAP3430ES2_USBHOST_MOD                         0xc00
+
+
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT                           26
+#define OMAP2420_EN_MMC                                 (1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT                         22
+#define OMAP24XX_EN_UART2                               (1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT                         21
+#define OMAP24XX_EN_UART1                               (1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT                        18
+#define OMAP24XX_EN_MCSPI2                              (1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT                        17
+#define OMAP24XX_EN_MCSPI1                              (1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT                        16
+#define OMAP24XX_EN_MCBSP2                              (1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT                        15
+#define OMAP24XX_EN_MCBSP1                              (1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT                         14
+#define OMAP24XX_EN_GPT12                               (1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT                         13
+#define OMAP24XX_EN_GPT11                               (1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT                         12
+#define OMAP24XX_EN_GPT10                               (1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT                          11
+#define OMAP24XX_EN_GPT9                                (1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT                          10
+#define OMAP24XX_EN_GPT8                                (1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT                          9
+#define OMAP24XX_EN_GPT7                                (1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT                          8
+#define OMAP24XX_EN_GPT6                                (1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT                          7
+#define OMAP24XX_EN_GPT5                                (1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT                          6
+#define OMAP24XX_EN_GPT4                                (1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT                          5
+#define OMAP24XX_EN_GPT3                                (1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT                          4
+#define OMAP24XX_EN_GPT2                                (1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT                         3
+#define OMAP2420_EN_VLYNQ                               (1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT                         10
+#define OMAP2430_EN_GPIO5                               (1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT                        9
+#define OMAP2430_EN_MCSPI3                              (1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT                        8
+#define OMAP2430_EN_MMCHS2                              (1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT                        7
+#define OMAP2430_EN_MMCHS1                              (1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT                         2
+#define OMAP24XX_EN_UART3                               (1 << 2)
+#define OMAP24XX_EN_USB_SHIFT                           0
+#define OMAP24XX_EN_USB                                 (1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT                      11
+#define OMAP2430_EN_MDM_INTC                            (1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT                         6
+#define OMAP2430_EN_USBHS                               (1 << 6)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC                                 (1 << 26)
+#define OMAP24XX_ST_UART2                               (1 << 22)
+#define OMAP24XX_ST_UART1                               (1 << 21)
+#define OMAP24XX_ST_MCSPI2                              (1 << 18)
+#define OMAP24XX_ST_MCSPI1                              (1 << 17)
+#define OMAP24XX_ST_GPT12                               (1 << 14)
+#define OMAP24XX_ST_GPT11                               (1 << 13)
+#define OMAP24XX_ST_GPT10                               (1 << 12)
+#define OMAP24XX_ST_GPT9                                (1 << 11)
+#define OMAP24XX_ST_GPT8                                (1 << 10)
+#define OMAP24XX_ST_GPT7                                (1 << 9)
+#define OMAP24XX_ST_GPT6                                (1 << 8)
+#define OMAP24XX_ST_GPT5                                (1 << 7)
+#define OMAP24XX_ST_GPT4                                (1 << 6)
+#define OMAP24XX_ST_GPT3                                (1 << 5)
+#define OMAP24XX_ST_GPT2                                (1 << 4)
+#define OMAP2420_ST_VLYNQ                               (1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC                            (1 << 11)
+#define OMAP2430_ST_GPIO5                               (1 << 10)
+#define OMAP2430_ST_MCSPI3                              (1 << 9)
+#define OMAP2430_ST_MMCHS2                              (1 << 8)
+#define OMAP2430_ST_MMCHS1                              (1 << 7)
+#define OMAP2430_ST_USBHS                               (1 << 6)
+#define OMAP24XX_ST_UART3                               (1 << 2)
+#define OMAP24XX_ST_USB                                 (1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT                         2
+#define OMAP24XX_EN_GPIOS                               (1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT                          0
+#define OMAP24XX_EN_GPT1                                (1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS                               (1 << 2)
+#define OMAP24XX_ST_GPT1                                (1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM                                 (1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT                              0
+#define OMAP3430_REV_MASK                               (0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE                               (1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC2                                (1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT                          25
+#define OMAP3430_EN_MMC1                                (1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT                          24
+#define OMAP3430_EN_MCSPI4                              (1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT                        21
+#define OMAP3430_EN_MCSPI3                              (1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT                        20
+#define OMAP3430_EN_MCSPI2                              (1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT                        19
+#define OMAP3430_EN_MCSPI1                              (1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT                        18
+#define OMAP3430_EN_I2C3                                (1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT                          17
+#define OMAP3430_EN_I2C2                                (1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT                          16
+#define OMAP3430_EN_I2C1                                (1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT                          15
+#define OMAP3430_EN_UART2                               (1 << 14)
+#define OMAP3430_EN_UART2_SHIFT                         14
+#define OMAP3430_EN_UART1                               (1 << 13)
+#define OMAP3430_EN_UART1_SHIFT                         13
+#define OMAP3430_EN_GPT11                               (1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT                         12
+#define OMAP3430_EN_GPT10                               (1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT                         11
+#define OMAP3430_EN_MCBSP5                              (1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT                        10
+#define OMAP3430_EN_MCBSP1                              (1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT                        9
+#define OMAP3430_EN_FSHOSTUSB                           (1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT                     5
+#define OMAP3430_EN_D2D                                 (1 << 3)
+#define OMAP3430_EN_D2D_SHIFT                           3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB                            (1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT                              4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC2                                (1 << 25)
+#define OMAP3430_ST_MMC1                                (1 << 24)
+#define OMAP3430_ST_MCSPI4                              (1 << 21)
+#define OMAP3430_ST_MCSPI3                              (1 << 20)
+#define OMAP3430_ST_MCSPI2                              (1 << 19)
+#define OMAP3430_ST_MCSPI1                              (1 << 18)
+#define OMAP3430_ST_I2C3                                (1 << 17)
+#define OMAP3430_ST_I2C2                                (1 << 16)
+#define OMAP3430_ST_I2C1                                (1 << 15)
+#define OMAP3430_ST_UART2                               (1 << 14)
+#define OMAP3430_ST_UART1                               (1 << 13)
+#define OMAP3430_ST_GPT11                               (1 << 12)
+#define OMAP3430_ST_GPT10                               (1 << 11)
+#define OMAP3430_ST_MCBSP5                              (1 << 10)
+#define OMAP3430_ST_MCBSP1                              (1 << 9)
+#define OMAP3430_ST_FSHOSTUSB                           (1 << 5)
+#define OMAP3430_ST_HSOTGUSB                            (1 << 4)
+#define OMAP3430_ST_D2D                                 (1 << 3)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPIO1                               (1 << 3)
+#define OMAP3430_EN_GPIO1_SHIFT                         3
+#define OMAP3430_EN_GPT1                                (1 << 0)
+#define OMAP3430_EN_GPT1_SHIFT                          0
+
+/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_SR2                                 (1 << 7)
+#define OMAP3430_EN_SR2_SHIFT                           7
+#define OMAP3430_EN_SR1                                 (1 << 6)
+#define OMAP3430_EN_SR1_SHIFT                           6
+
+/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPT12                               (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT                         1
+
+/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+#define OMAP3430_ST_SR2                                 (1 << 7)
+#define OMAP3430_ST_SR1                                 (1 << 6)
+#define OMAP3430_ST_GPIO1                               (1 << 3)
+#define OMAP3430_ST_GPT12                               (1 << 1)
+#define OMAP3430_ST_GPT1                                (1 << 0)
+
+/*
+ * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ */
+#define OMAP3430_EN_MPU                                 (1 << 1)
+#define OMAP3430_EN_MPU_SHIFT                           1
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+#define OMAP3430_EN_GPIO6                               (1 << 17)
+#define OMAP3430_EN_GPIO6_SHIFT                         17
+#define OMAP3430_EN_GPIO5                               (1 << 16)
+#define OMAP3430_EN_GPIO5_SHIFT                         16
+#define OMAP3430_EN_GPIO4                               (1 << 15)
+#define OMAP3430_EN_GPIO4_SHIFT                         15
+#define OMAP3430_EN_GPIO3                               (1 << 14)
+#define OMAP3430_EN_GPIO3_SHIFT                         14
+#define OMAP3430_EN_GPIO2                               (1 << 13)
+#define OMAP3430_EN_GPIO2_SHIFT                         13
+#define OMAP3430_EN_UART3                               (1 << 11)
+#define OMAP3430_EN_UART3_SHIFT                         11
+#define OMAP3430_EN_GPT9                                (1 << 10)
+#define OMAP3430_EN_GPT9_SHIFT                          10
+#define OMAP3430_EN_GPT8                                (1 << 9)
+#define OMAP3430_EN_GPT8_SHIFT                          9
+#define OMAP3430_EN_GPT7                                (1 << 8)
+#define OMAP3430_EN_GPT7_SHIFT                          8
+#define OMAP3430_EN_GPT6                                (1 << 7)
+#define OMAP3430_EN_GPT6_SHIFT                          7
+#define OMAP3430_EN_GPT5                                (1 << 6)
+#define OMAP3430_EN_GPT5_SHIFT                          6
+#define OMAP3430_EN_GPT4                                (1 << 5)
+#define OMAP3430_EN_GPT4_SHIFT                          5
+#define OMAP3430_EN_GPT3                                (1 << 4)
+#define OMAP3430_EN_GPT3_SHIFT                          4
+#define OMAP3430_EN_GPT2                                (1 << 3)
+#define OMAP3430_EN_GPT2_SHIFT                          3
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ * be ST_* bits instead? */
+#define OMAP3430_EN_MCBSP4                              (1 << 2)
+#define OMAP3430_EN_MCBSP4_SHIFT                        2
+#define OMAP3430_EN_MCBSP3                              (1 << 1)
+#define OMAP3430_EN_MCBSP3_SHIFT                        1
+#define OMAP3430_EN_MCBSP2                              (1 << 0)
+#define OMAP3430_EN_MCBSP2_SHIFT                        0
+
+/* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3430_ST_GPIO6                               (1 << 17)
+#define OMAP3430_ST_GPIO5                               (1 << 16)
+#define OMAP3430_ST_GPIO4                               (1 << 15)
+#define OMAP3430_ST_GPIO3                               (1 << 14)
+#define OMAP3430_ST_GPIO2                               (1 << 13)
+#define OMAP3430_ST_UART3                               (1 << 11)
+#define OMAP3430_ST_GPT9                                (1 << 10)
+#define OMAP3430_ST_GPT8                                (1 << 9)
+#define OMAP3430_ST_GPT7                                (1 << 8)
+#define OMAP3430_ST_GPT6                                (1 << 7)
+#define OMAP3430_ST_GPT5                                (1 << 6)
+#define OMAP3430_ST_GPT4                                (1 << 5)
+#define OMAP3430_ST_GPT3                                (1 << 4)
+#define OMAP3430_ST_GPT2                                (1 << 3)
+
+/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+#define OMAP3430_EN_CORE                                (1 << 0)
+
+#endif
+
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
deleted file mode 100644
index 5e1c4b53ee9d..000000000000
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/prcm-regs.h
- *
- * OMAP24XX Power Reset and Clock Management (PRCM) registers
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
-#define __ARCH_ARM_MACH_OMAP2_PRCM_H
-
-/* SET_PERFORMANCE_LEVEL PARAMETERS */
-#define PRCM_HALF_SPEED 1
-#define PRCM_FULL_SPEED 2
-
-#ifndef __ASSEMBLER__
-
-#define PRCM_REG32(offset)      __REG32(OMAP24XX_PRCM_BASE + (offset))
-
-#define PRCM_REVISION           PRCM_REG32(0x000)
-#define PRCM_SYSCONFIG          PRCM_REG32(0x010)
-#define PRCM_IRQSTATUS_MPU      PRCM_REG32(0x018)
-#define PRCM_IRQENABLE_MPU      PRCM_REG32(0x01C)
-#define PRCM_VOLTCTRL           PRCM_REG32(0x050)
-#define PRCM_VOLTST             PRCM_REG32(0x054)
-#define PRCM_CLKSRC_CTRL        PRCM_REG32(0x060)
-#define PRCM_CLKOUT_CTRL        PRCM_REG32(0x070)
-#define PRCM_CLKEMUL_CTRL       PRCM_REG32(0x078)
-#define PRCM_CLKCFG_CTRL        PRCM_REG32(0x080)
-#define PRCM_CLKCFG_STATUS      PRCM_REG32(0x084)
-#define PRCM_VOLTSETUP          PRCM_REG32(0x090)
-#define PRCM_CLKSSETUP          PRCM_REG32(0x094)
-#define PRCM_POLCTRL            PRCM_REG32(0x098)
-
-/* GENERAL PURPOSE */
-#define GENERAL_PURPOSE1        PRCM_REG32(0x0B0)
-#define GENERAL_PURPOSE2        PRCM_REG32(0x0B4)
-#define GENERAL_PURPOSE3        PRCM_REG32(0x0B8)
-#define GENERAL_PURPOSE4        PRCM_REG32(0x0BC)
-#define GENERAL_PURPOSE5        PRCM_REG32(0x0C0)
-#define GENERAL_PURPOSE6        PRCM_REG32(0x0C4)
-#define GENERAL_PURPOSE7        PRCM_REG32(0x0C8)
-#define GENERAL_PURPOSE8        PRCM_REG32(0x0CC)
-#define GENERAL_PURPOSE9        PRCM_REG32(0x0D0)
-#define GENERAL_PURPOSE10       PRCM_REG32(0x0D4)
-#define GENERAL_PURPOSE11       PRCM_REG32(0x0D8)
-#define GENERAL_PURPOSE12       PRCM_REG32(0x0DC)
-#define GENERAL_PURPOSE13       PRCM_REG32(0x0E0)
-#define GENERAL_PURPOSE14       PRCM_REG32(0x0E4)
-#define GENERAL_PURPOSE15       PRCM_REG32(0x0E8)
-#define GENERAL_PURPOSE16       PRCM_REG32(0x0EC)
-#define GENERAL_PURPOSE17       PRCM_REG32(0x0F0)
-#define GENERAL_PURPOSE18       PRCM_REG32(0x0F4)
-#define GENERAL_PURPOSE19       PRCM_REG32(0x0F8)
-#define GENERAL_PURPOSE20       PRCM_REG32(0x0FC)
-
-/* MPU */
-#define CM_CLKSEL_MPU           PRCM_REG32(0x140)
-#define CM_CLKSTCTRL_MPU        PRCM_REG32(0x148)
-#define RM_RSTST_MPU            PRCM_REG32(0x158)
-#define PM_WKDEP_MPU            PRCM_REG32(0x1C8)
-#define PM_EVGENCTRL_MPU        PRCM_REG32(0x1D4)
-#define PM_EVEGENONTIM_MPU      PRCM_REG32(0x1D8)
-#define PM_EVEGENOFFTIM_MPU     PRCM_REG32(0x1DC)
-#define PM_PWSTCTRL_MPU         PRCM_REG32(0x1E0)
-#define PM_PWSTST_MPU           PRCM_REG32(0x1E4)
-
-/* CORE */
-#define CM_FCLKEN1_CORE         PRCM_REG32(0x200)
-#define CM_FCLKEN2_CORE         PRCM_REG32(0x204)
-#define CM_FCLKEN3_CORE         PRCM_REG32(0x208)
-#define CM_ICLKEN1_CORE         PRCM_REG32(0x210)
-#define CM_ICLKEN2_CORE         PRCM_REG32(0x214)
-#define CM_ICLKEN3_CORE         PRCM_REG32(0x218)
-#define CM_ICLKEN4_CORE         PRCM_REG32(0x21C)
-#define CM_IDLEST1_CORE         PRCM_REG32(0x220)
-#define CM_IDLEST2_CORE         PRCM_REG32(0x224)
-#define CM_IDLEST3_CORE         PRCM_REG32(0x228)
-#define CM_IDLEST4_CORE         PRCM_REG32(0x22C)
-#define CM_AUTOIDLE1_CORE       PRCM_REG32(0x230)
-#define CM_AUTOIDLE2_CORE       PRCM_REG32(0x234)
-#define CM_AUTOIDLE3_CORE       PRCM_REG32(0x238)
-#define CM_AUTOIDLE4_CORE       PRCM_REG32(0x23C)
-#define CM_CLKSEL1_CORE         PRCM_REG32(0x240)
-#define CM_CLKSEL2_CORE         PRCM_REG32(0x244)
-#define CM_CLKSTCTRL_CORE       PRCM_REG32(0x248)
-#define PM_WKEN1_CORE           PRCM_REG32(0x2A0)
-#define PM_WKEN2_CORE           PRCM_REG32(0x2A4)
-#define PM_WKST1_CORE           PRCM_REG32(0x2B0)
-#define PM_WKST2_CORE           PRCM_REG32(0x2B4)
-#define PM_WKDEP_CORE           PRCM_REG32(0x2C8)
-#define PM_PWSTCTRL_CORE        PRCM_REG32(0x2E0)
-#define PM_PWSTST_CORE          PRCM_REG32(0x2E4)
-
-/* GFX */
-#define CM_FCLKEN_GFX           PRCM_REG32(0x300)
-#define CM_ICLKEN_GFX           PRCM_REG32(0x310)
-#define CM_IDLEST_GFX           PRCM_REG32(0x320)
-#define CM_CLKSEL_GFX           PRCM_REG32(0x340)
-#define CM_CLKSTCTRL_GFX        PRCM_REG32(0x348)
-#define RM_RSTCTRL_GFX          PRCM_REG32(0x350)
-#define RM_RSTST_GFX            PRCM_REG32(0x358)
-#define PM_WKDEP_GFX            PRCM_REG32(0x3C8)
-#define PM_PWSTCTRL_GFX         PRCM_REG32(0x3E0)
-#define PM_PWSTST_GFX           PRCM_REG32(0x3E4)
-
-/* WAKE-UP */
-#define CM_FCLKEN_WKUP          PRCM_REG32(0x400)
-#define CM_ICLKEN_WKUP          PRCM_REG32(0x410)
-#define CM_IDLEST_WKUP          PRCM_REG32(0x420)
-#define CM_AUTOIDLE_WKUP        PRCM_REG32(0x430)
-#define CM_CLKSEL_WKUP          PRCM_REG32(0x440)
-#define RM_RSTCTRL_WKUP         PRCM_REG32(0x450)
-#define RM_RSTTIME_WKUP         PRCM_REG32(0x454)
-#define RM_RSTST_WKUP           PRCM_REG32(0x458)
-#define PM_WKEN_WKUP            PRCM_REG32(0x4A0)
-#define PM_WKST_WKUP            PRCM_REG32(0x4B0)
-
-/* CLOCKS */
-#define CM_CLKEN_PLL            PRCM_REG32(0x500)
-#define CM_IDLEST_CKGEN         PRCM_REG32(0x520)
-#define CM_AUTOIDLE_PLL         PRCM_REG32(0x530)
-#define CM_CLKSEL1_PLL          PRCM_REG32(0x540)
-#define CM_CLKSEL2_PLL          PRCM_REG32(0x544)
-
-/* DSP */
-#define CM_FCLKEN_DSP           PRCM_REG32(0x800)
-#define CM_ICLKEN_DSP           PRCM_REG32(0x810)
-#define CM_IDLEST_DSP           PRCM_REG32(0x820)
-#define CM_AUTOIDLE_DSP         PRCM_REG32(0x830)
-#define CM_CLKSEL_DSP           PRCM_REG32(0x840)
-#define CM_CLKSTCTRL_DSP        PRCM_REG32(0x848)
-#define RM_RSTCTRL_DSP          PRCM_REG32(0x850)
-#define RM_RSTST_DSP            PRCM_REG32(0x858)
-#define PM_WKEN_DSP             PRCM_REG32(0x8A0)
-#define PM_WKDEP_DSP            PRCM_REG32(0x8C8)
-#define PM_PWSTCTRL_DSP         PRCM_REG32(0x8E0)
-#define PM_PWSTST_DSP           PRCM_REG32(0x8E4)
-#define PRCM_IRQSTATUS_DSP      PRCM_REG32(0x8F0)
-#define PRCM_IRQENABLE_DSP      PRCM_REG32(0x8F4)
-
-/* IVA */
-#define PRCM_IRQSTATUS_IVA      PRCM_REG32(0x8F8)
-#define PRCM_IRQENABLE_IVA      PRCM_REG32(0x8FC)
-
-/* Modem on 2430 */
-#define CM_FCLKEN_MDM           PRCM_REG32(0xC00)
-#define CM_ICLKEN_MDM           PRCM_REG32(0xC10)
-#define CM_IDLEST_MDM           PRCM_REG32(0xC20)
-#define CM_AUTOIDLE_MDM         PRCM_REG32(0xC30)
-#define CM_CLKSEL_MDM           PRCM_REG32(0xC40)
-#define CM_CLKSTCTRL_MDM        PRCM_REG32(0xC48)
-#define RM_RSTCTRL_MDM          PRCM_REG32(0xC50)
-#define RM_RSTST_MDM            PRCM_REG32(0xC58)
-#define PM_WKEN_MDM             PRCM_REG32(0xCA0)
-#define PM_WKST_MDM             PRCM_REG32(0xCB0)
-#define PM_WKDEP_MDM            PRCM_REG32(0xCC8)
-#define PM_PWSTCTRL_MDM         PRCM_REG32(0xCE0)
-#define PM_PWSTST_MDM           PRCM_REG32(0xCE4)
-
-#define OMAP24XX_L4_IO_BASE     0x48000000
-
-#define DISP_BASE               (OMAP24XX_L4_IO_BASE + 0x50000)
-#define DISP_REG32(offset)      __REG32(DISP_BASE + (offset))
-
-#define OMAP24XX_GPMC_BASE      (L3_24XX_BASE + 0xa000)
-#define GPMC_REG32(offset)      __REG32(OMAP24XX_GPMC_BASE + (offset))
-
-/* FIXME: Move these to timer code */
-#define GPT1_BASE               (0x48028000)
-#define GPT1_REG32(offset)      __REG32(GPT1_BASE + (offset))
-
-/* Misc sysconfig */
-#define DISPC_SYSCONFIG         DISP_REG32(0x410)
-#define SPI_BASE                (OMAP24XX_L4_IO_BASE + 0x98000)
-#define MCSPI1_SYSCONFIG        __REG32(SPI_BASE + 0x10)
-#define MCSPI2_SYSCONFIG        __REG32(SPI_BASE + 0x2000 + 0x10)
-#define MCSPI3_SYSCONFIG        __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
-
-#define CAMERA_MMU_SYSCONFIG    __REG32(DISP_BASE + 0x2C10)
-#define CAMERA_DMA_SYSCONFIG    __REG32(DISP_BASE + 0x282C)
-#define SYSTEM_DMA_SYSCONFIG    __REG32(DISP_BASE + 0x602C)
-#define GPMC_SYSCONFIG          GPMC_REG32(0x010)
-#define MAILBOXES_SYSCONFIG     __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
-#define UART1_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
-#define UART2_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
-#define UART3_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
-#define SDRC_SYSCONFIG          __REG32(OMAP24XX_SDRC_BASE + 0x10)
-#define OMAP24XX_SMS_BASE       (L3_24XX_BASE + 0x8000)
-#define SMS_SYSCONFIG           __REG32(OMAP24XX_SMS_BASE + 0x10)
-#define SSI_SYSCONFIG           __REG32(DISP_BASE + 0x8010)
-
-/* rkw - good cannidates for PM_ to start what nm was trying */
-#define OMAP24XX_GPT2           (OMAP24XX_L4_IO_BASE + 0x2A000)
-#define OMAP24XX_GPT3           (OMAP24XX_L4_IO_BASE + 0x78000)
-#define OMAP24XX_GPT4           (OMAP24XX_L4_IO_BASE + 0x7A000)
-#define OMAP24XX_GPT5           (OMAP24XX_L4_IO_BASE + 0x7C000)
-#define OMAP24XX_GPT6           (OMAP24XX_L4_IO_BASE + 0x7E000)
-#define OMAP24XX_GPT7           (OMAP24XX_L4_IO_BASE + 0x80000)
-#define OMAP24XX_GPT8           (OMAP24XX_L4_IO_BASE + 0x82000)
-#define OMAP24XX_GPT9           (OMAP24XX_L4_IO_BASE + 0x84000)
-#define OMAP24XX_GPT10          (OMAP24XX_L4_IO_BASE + 0x86000)
-#define OMAP24XX_GPT11          (OMAP24XX_L4_IO_BASE + 0x88000)
-#define OMAP24XX_GPT12          (OMAP24XX_L4_IO_BASE + 0x8A000)
-
-/* FIXME: Move these to timer code */
-#define GPTIMER1_SYSCONFIG      GPT1_REG32(0x010)
-#define GPTIMER2_SYSCONFIG      __REG32(OMAP24XX_GPT2 + 0x10)
-#define GPTIMER3_SYSCONFIG      __REG32(OMAP24XX_GPT3 + 0x10)
-#define GPTIMER4_SYSCONFIG      __REG32(OMAP24XX_GPT4 + 0x10)
-#define GPTIMER5_SYSCONFIG      __REG32(OMAP24XX_GPT5 + 0x10)
-#define GPTIMER6_SYSCONFIG      __REG32(OMAP24XX_GPT6 + 0x10)
-#define GPTIMER7_SYSCONFIG      __REG32(OMAP24XX_GPT7 + 0x10)
-#define GPTIMER8_SYSCONFIG      __REG32(OMAP24XX_GPT8 + 0x10)
-#define GPTIMER9_SYSCONFIG      __REG32(OMAP24XX_GPT9 + 0x10)
-#define GPTIMER10_SYSCONFIG     __REG32(OMAP24XX_GPT10 + 0x10)
-#define GPTIMER11_SYSCONFIG     __REG32(OMAP24XX_GPT11 + 0x10)
-#define GPTIMER12_SYSCONFIG     __REG32(OMAP24XX_GPT12 + 0x10)
-
-/* FIXME: Move these to gpio code */
-#define OMAP24XX_GPIO_BASE      0x48018000
-#define GPIOX_BASE(X)           (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
-
-#define GPIO1_SYSCONFIG         __REG32((GPIOX_BASE(1) + 0x10))
-#define GPIO2_SYSCONFIG         __REG32((GPIOX_BASE(2) + 0x10))
-#define GPIO3_SYSCONFIG         __REG32((GPIOX_BASE(3) + 0x10))
-#define GPIO4_SYSCONFIG         __REG32((GPIOX_BASE(4) + 0x10))
-
-#if defined(CONFIG_ARCH_OMAP243X)
-#define GPIO5_SYSCONFIG         __REG32((OMAP24XX_GPIO5_BASE + 0x10))
-#endif
-
-/* GP TIMER 1 */
-#define GPTIMER1_TISTAT         GPT1_REG32(0x014)
-#define GPTIMER1_TISR           GPT1_REG32(0x018)
-#define GPTIMER1_TIER           GPT1_REG32(0x01C)
-#define GPTIMER1_TWER           GPT1_REG32(0x020)
-#define GPTIMER1_TCLR           GPT1_REG32(0x024)
-#define GPTIMER1_TCRR           GPT1_REG32(0x028)
-#define GPTIMER1_TLDR           GPT1_REG32(0x02C)
-#define GPTIMER1_TTGR           GPT1_REG32(0x030)
-#define GPTIMER1_TWPS           GPT1_REG32(0x034)
-#define GPTIMER1_TMAR           GPT1_REG32(0x038)
-#define GPTIMER1_TCAR1          GPT1_REG32(0x03C)
-#define GPTIMER1_TSICR          GPT1_REG32(0x040)
-#define GPTIMER1_TCAR2          GPT1_REG32(0x044)
-
-/* rkw -- base fix up please... */
-#define GPTIMER3_TISR           __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
-
-/* SDRC */
-#define SDRC_DLLA_CTRL          __REG32(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_DLLA_STATUS        __REG32(OMAP24XX_SDRC_BASE + 0x064)
-#define SDRC_DLLB_CTRL          __REG32(OMAP24XX_SDRC_BASE + 0x068)
-#define SDRC_DLLB_STATUS        __REG32(OMAP24XX_SDRC_BASE + 0x06C)
-#define SDRC_POWER              __REG32(OMAP24XX_SDRC_BASE + 0x070)
-#define SDRC_MR_0               __REG32(OMAP24XX_SDRC_BASE + 0x084)
-
-/* GPIO 1 */
-#define GPIO1_BASE              GPIOX_BASE(1)
-#define GPIO1_REG32(offset)     __REG32(GPIO1_BASE + (offset))
-#define GPIO1_IRQENABLE1        GPIO1_REG32(0x01C)
-#define GPIO1_IRQSTATUS1        GPIO1_REG32(0x018)
-#define GPIO1_IRQENABLE2        GPIO1_REG32(0x02C)
-#define GPIO1_IRQSTATUS2        GPIO1_REG32(0x028)
-#define GPIO1_WAKEUPENABLE      GPIO1_REG32(0x020)
-#define GPIO1_RISINGDETECT      GPIO1_REG32(0x048)
-#define GPIO1_DATAIN            GPIO1_REG32(0x038)
-#define GPIO1_OE                GPIO1_REG32(0x034)
-#define GPIO1_DATAOUT           GPIO1_REG32(0x03C)
-
-/* GPIO2 */
-#define GPIO2_BASE              GPIOX_BASE(2)
-#define GPIO2_REG32(offset)     __REG32(GPIO2_BASE + (offset))
-#define GPIO2_IRQENABLE1        GPIO2_REG32(0x01C)
-#define GPIO2_IRQSTATUS1        GPIO2_REG32(0x018)
-#define GPIO2_IRQENABLE2        GPIO2_REG32(0x02C)
-#define GPIO2_IRQSTATUS2        GPIO2_REG32(0x028)
-#define GPIO2_WAKEUPENABLE      GPIO2_REG32(0x020)
-#define GPIO2_RISINGDETECT      GPIO2_REG32(0x048)
-#define GPIO2_DATAIN            GPIO2_REG32(0x038)
-#define GPIO2_OE                GPIO2_REG32(0x034)
-#define GPIO2_DATAOUT           GPIO2_REG32(0x03C)
-#define GPIO2_DEBOUNCENABLE     GPIO2_REG32(0x050)
-#define GPIO2_DEBOUNCINGTIME    GPIO2_REG32(0x054)
-
-/* GPIO 3 */
-#define GPIO3_BASE              GPIOX_BASE(3)
-#define GPIO3_REG32(offset)     __REG32(GPIO3_BASE + (offset))
-#define GPIO3_IRQENABLE1        GPIO3_REG32(0x01C)
-#define GPIO3_IRQSTATUS1        GPIO3_REG32(0x018)
-#define GPIO3_IRQENABLE2        GPIO3_REG32(0x02C)
-#define GPIO3_IRQSTATUS2        GPIO3_REG32(0x028)
-#define GPIO3_WAKEUPENABLE      GPIO3_REG32(0x020)
-#define GPIO3_RISINGDETECT      GPIO3_REG32(0x048)
-#define GPIO3_FALLINGDETECT     GPIO3_REG32(0x04C)
-#define GPIO3_DATAIN            GPIO3_REG32(0x038)
-#define GPIO3_OE                GPIO3_REG32(0x034)
-#define GPIO3_DATAOUT           GPIO3_REG32(0x03C)
-#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
-#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
-
-/* GPIO 4 */
-#define GPIO4_BASE              GPIOX_BASE(4)
-#define GPIO4_REG32(offset)     __REG32(GPIO4_BASE + (offset))
-#define GPIO4_IRQENABLE1        GPIO4_REG32(0x01C)
-#define GPIO4_IRQSTATUS1        GPIO4_REG32(0x018)
-#define GPIO4_IRQENABLE2        GPIO4_REG32(0x02C)
-#define GPIO4_IRQSTATUS2        GPIO4_REG32(0x028)
-#define GPIO4_WAKEUPENABLE      GPIO4_REG32(0x020)
-#define GPIO4_RISINGDETECT      GPIO4_REG32(0x048)
-#define GPIO4_FALLINGDETECT     GPIO4_REG32(0x04C)
-#define GPIO4_DATAIN            GPIO4_REG32(0x038)
-#define GPIO4_OE                GPIO4_REG32(0x034)
-#define GPIO4_DATAOUT           GPIO4_REG32(0x03C)
-#define GPIO4_DEBOUNCENABLE     GPIO4_REG32(0x050)
-#define GPIO4_DEBOUNCINGTIME    GPIO4_REG32(0x054)
-
-#if defined(CONFIG_ARCH_OMAP243X)
-/* GPIO 5 */
-#define GPIO5_REG32(offset)     __REG32((OMAP24XX_GPIO5_BASE + (offset)))
-#define GPIO5_IRQENABLE1        GPIO5_REG32(0x01C)
-#define GPIO5_IRQSTATUS1        GPIO5_REG32(0x018)
-#define GPIO5_IRQENABLE2        GPIO5_REG32(0x02C)
-#define GPIO5_IRQSTATUS2        GPIO5_REG32(0x028)
-#define GPIO5_WAKEUPENABLE      GPIO5_REG32(0x020)
-#define GPIO5_RISINGDETECT      GPIO5_REG32(0x048)
-#define GPIO5_FALLINGDETECT     GPIO5_REG32(0x04C)
-#define GPIO5_DATAIN            GPIO5_REG32(0x038)
-#define GPIO5_OE                GPIO5_REG32(0x034)
-#define GPIO5_DATAOUT           GPIO5_REG32(0x03C)
-#define GPIO5_DEBOUNCENABLE     GPIO5_REG32(0x050)
-#define GPIO5_DEBOUNCINGTIME    GPIO5_REG32(0x054)
-#endif
-
-/* IO CONFIG */
-#define OMAP24XX_CTRL_BASE              (L4_24XX_BASE)
-#define CONTROL_REG32(offset)           __REG32(OMAP24XX_CTRL_BASE + (offset))
-
-#define CONTROL_PADCONF_SPI1_NCS2       CONTROL_REG32(0x104)
-#define CONTROL_PADCONF_SYS_XTALOUT     CONTROL_REG32(0x134)
-#define CONTROL_PADCONF_UART1_RX        CONTROL_REG32(0x0C8)
-#define CONTROL_PADCONF_MCBSP1_DX       CONTROL_REG32(0x10C)
-#define CONTROL_PADCONF_GPMC_NCS4       CONTROL_REG32(0x090)
-#define CONTROL_PADCONF_DSS_D5          CONTROL_REG32(0x0B8)
-#define CONTROL_PADCONF_DSS_D9          CONTROL_REG32(0x0BC)    /* 2420 */
-#define CONTROL_PADCONF_DSS_D13         CONTROL_REG32(0x0C0)
-#define CONTROL_PADCONF_DSS_VSYNC       CONTROL_REG32(0x0CC)
-#define CONTROL_PADCONF_SYS_NIRQW0      CONTROL_REG32(0x0BC)    /* 2430 */
-#define CONTROL_PADCONF_SSI1_FLAG_TX    CONTROL_REG32(0x108)    /* 2430 */
-
-/* CONTROL */
-#define CONTROL_DEVCONF         CONTROL_REG32(0x274)
-#define CONTROL_DEVCONF1        CONTROL_REG32(0x2E8)
-
-/* INTERRUPT CONTROLLER */
-#define INTC_BASE               ((L4_24XX_BASE) + 0xfe000)
-#define INTC_REG32(offset)      __REG32(INTC_BASE + (offset))
-
-#define INTC1_U_BASE            INTC_REG32(0x000)
-#define INTC_MIR0               INTC_REG32(0x084)
-#define INTC_MIR_SET0           INTC_REG32(0x08C)
-#define INTC_MIR_CLEAR0         INTC_REG32(0x088)
-#define INTC_ISR_CLEAR0         INTC_REG32(0x094)
-#define INTC_MIR1               INTC_REG32(0x0A4)
-#define INTC_MIR_SET1           INTC_REG32(0x0AC)
-#define INTC_MIR_CLEAR1         INTC_REG32(0x0A8)
-#define INTC_ISR_CLEAR1         INTC_REG32(0x0B4)
-#define INTC_MIR2               INTC_REG32(0x0C4)
-#define INTC_MIR_SET2           INTC_REG32(0x0CC)
-#define INTC_MIR_CLEAR2         INTC_REG32(0x0C8)
-#define INTC_ISR_CLEAR2         INTC_REG32(0x0D4)
-#define INTC_SIR_IRQ            INTC_REG32(0x040)
-#define INTC_CONTROL            INTC_REG32(0x048)
-#define INTC_ILR11              INTC_REG32(0x12C)       /* PRCM on MPU PIC */
-#define INTC_ILR30              INTC_REG32(0x178)
-#define INTC_ILR31              INTC_REG32(0x17C)
-#define INTC_ILR32              INTC_REG32(0x180)
-#define INTC_ILR37              INTC_REG32(0x194)       /* GPIO4 on MPU PIC */
-#define INTC_SYSCONFIG          INTC_REG32(0x010)       /* GPT1 on MPU PIC */
-
-/* RAM FIREWALL */
-#define RAMFW_BASE              (0x68005000)
-#define RAMFW_REG32(offset)     __REG32(RAMFW_BASE + (offset))
-
-#define RAMFW_REQINFOPERM0      RAMFW_REG32(0x048)
-#define RAMFW_READPERM0         RAMFW_REG32(0x050)
-#define RAMFW_WRITEPERM0        RAMFW_REG32(0x058)
-
-/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
-//#define DEBUG_BOARD_LED_REGISTER 0x04000014
-
-/* GPMC CS0 */
-#define GPMC_CONFIG1_0          GPMC_REG32(0x060)
-#define GPMC_CONFIG2_0          GPMC_REG32(0x064)
-#define GPMC_CONFIG3_0          GPMC_REG32(0x068)
-#define GPMC_CONFIG4_0          GPMC_REG32(0x06C)
-#define GPMC_CONFIG5_0          GPMC_REG32(0x070)
-#define GPMC_CONFIG6_0          GPMC_REG32(0x074)
-#define GPMC_CONFIG7_0          GPMC_REG32(0x078)
-
-/* GPMC CS1 */
-#define GPMC_CONFIG1_1          GPMC_REG32(0x090)
-#define GPMC_CONFIG2_1          GPMC_REG32(0x094)
-#define GPMC_CONFIG3_1          GPMC_REG32(0x098)
-#define GPMC_CONFIG4_1          GPMC_REG32(0x09C)
-#define GPMC_CONFIG5_1          GPMC_REG32(0x0a0)
-#define GPMC_CONFIG6_1          GPMC_REG32(0x0a4)
-#define GPMC_CONFIG7_1          GPMC_REG32(0x0a8)
-
-/* GPMC CS3 */
-#define GPMC_CONFIG1_3          GPMC_REG32(0x0F0)
-#define GPMC_CONFIG2_3          GPMC_REG32(0x0F4)
-#define GPMC_CONFIG3_3          GPMC_REG32(0x0F8)
-#define GPMC_CONFIG4_3          GPMC_REG32(0x0FC)
-#define GPMC_CONFIG5_3          GPMC_REG32(0x100)
-#define GPMC_CONFIG6_3          GPMC_REG32(0x104)
-#define GPMC_CONFIG7_3          GPMC_REG32(0x108)
-
-/* DSS */
-#define DSS_CONTROL             DISP_REG32(0x040)
-#define DISPC_CONTROL           DISP_REG32(0x440)
-#define DISPC_SYSSTATUS         DISP_REG32(0x414)
-#define DISPC_IRQSTATUS         DISP_REG32(0x418)
-#define DISPC_IRQENABLE         DISP_REG32(0x41C)
-#define DISPC_CONFIG            DISP_REG32(0x444)
-#define DISPC_DEFAULT_COLOR0    DISP_REG32(0x44C)
-#define DISPC_DEFAULT_COLOR1    DISP_REG32(0x450)
-#define DISPC_TRANS_COLOR0      DISP_REG32(0x454)
-#define DISPC_TRANS_COLOR1      DISP_REG32(0x458)
-#define DISPC_LINE_NUMBER       DISP_REG32(0x460)
-#define DISPC_TIMING_H          DISP_REG32(0x464)
-#define DISPC_TIMING_V          DISP_REG32(0x468)
-#define DISPC_POL_FREQ          DISP_REG32(0x46C)
-#define DISPC_DIVISOR           DISP_REG32(0x470)
-#define DISPC_SIZE_DIG          DISP_REG32(0x478)
-#define DISPC_SIZE_LCD          DISP_REG32(0x47C)
-#define DISPC_GFX_BA0           DISP_REG32(0x480)
-#define DISPC_GFX_BA1           DISP_REG32(0x484)
-#define DISPC_GFX_POSITION      DISP_REG32(0x488)
-#define DISPC_GFX_SIZE          DISP_REG32(0x48C)
-#define DISPC_GFX_ATTRIBUTES    DISP_REG32(0x4A0)
-#define DISPC_GFX_FIFO_THRESHOLD        DISP_REG32(0x4A4)
-#define DISPC_GFX_ROW_INC       DISP_REG32(0x4AC)
-#define DISPC_GFX_PIXEL_INC     DISP_REG32(0x4B0)
-#define DISPC_GFX_WINDOW_SKIP   DISP_REG32(0x4B4)
-#define DISPC_GFX_TABLE_BA      DISP_REG32(0x4B8)
-#define DISPC_DATA_CYCLE1       DISP_REG32(0x5D4)
-#define DISPC_DATA_CYCLE2       DISP_REG32(0x5D8)
-#define DISPC_DATA_CYCLE3       DISP_REG32(0x5DC)
-
-/* HSUSB Suspend */
-#define HSUSB_CTRL              __REG8(0x480AC001)
-#define USBOTG_POWER            __REG32(0x480AC000)
-
-/* HS MMC */
-#define MMCHS1_SYSCONFIG        __REG32(0x4809C010)
-#define MMCHS2_SYSCONFIG        __REG32(0x480b4010)
-
-#endif  /* __ASSEMBLER__ */
-
-#endif
-
-
-
-
-
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 90f530540c65..b12f423b8595 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,19 +17,27 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include "prcm-regs.h"
+#include <asm/io.h>
+
+#include "prm.h"
+#include "prm-regbits-24xx.h"
 
 extern void omap2_clk_prepare_for_reboot(void);
 
 u32 omap_prcm_get_reset_sources(void)
 {
-        return RM_RSTST_WKUP & 0x7f;
+        return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 
 /* Resets clock rates and reboots the system. Only called from system.h */
 void omap_prcm_arch_reset(char mode)
 {
+        u32 wkup;
         omap2_clk_prepare_for_reboot();
-        RM_RSTCTRL_WKUP |= 2;
+
+        if (cpu_is_omap24xx()) {
+                wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
+                prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
+        }
 }
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
new file mode 100644
index 000000000000..c6d17a3378ec
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -0,0 +1,279 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Power/Reset Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Bits shared between registers */
+
+/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_ST                           (1 << 2)
+#define OMAP24XX_WKUP2_ST                               (1 << 1)
+#define OMAP24XX_WKUP1_ST                               (1 << 0)
+
+/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_EN                           (1 << 2)
+#define OMAP24XX_WKUP2_EN                               (1 << 1)
+#define OMAP24XX_WKUP1_EN                               (1 << 0)
+
+/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
+#define OMAP24XX_EN_MPU                                 (1 << 1)
+#define OMAP24XX_EN_CORE                                (1 << 0)
+
+/*
+ * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
+ * shared bits
+ */
+#define OMAP24XX_MEMONSTATE_SHIFT                       10
+#define OMAP24XX_MEMONSTATE_MASK                        (0x3 << 10)
+#define OMAP24XX_MEMRETSTATE                            (1 << 3)
+
+/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
+#define OMAP24XX_FORCESTATE                             (1 << 18)
+
+/*
+ * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
+ * PM_PWSTST_MDM shared bits
+ */
+#define OMAP24XX_CLKACTIVITY                            (1 << 19)
+
+/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
+#define OMAP24XX_LASTSTATEENTERED_SHIFT                 4
+#define OMAP24XX_LASTSTATEENTERED_MASK                  (0x3 << 4)
+
+/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
+#define OMAP2430_MEMSTATEST_SHIFT                       10
+#define OMAP2430_MEMSTATEST_MASK                        (0x3 << 10)
+
+/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
+#define OMAP24XX_POWERSTATEST_SHIFT                     0
+#define OMAP24XX_POWERSTATEST_MASK                      (0x3 << 0)
+
+
+/* Bits specific to each register */
+
+/* PRCM_REVISION */
+#define OMAP24XX_REV_SHIFT                              0
+#define OMAP24XX_REV_MASK                               (0xff << 0)
+
+/* PRCM_SYSCONFIG */
+#define OMAP24XX_AUTOIDLE                               (1 << 0)
+
+/* PRCM_IRQSTATUS_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_ST                          (1 << 6)
+#define OMAP24XX_TRANSITION_ST                          (1 << 5)
+#define OMAP24XX_EVGENOFF_ST                            (1 << 4)
+#define OMAP24XX_EVGENON_ST                             (1 << 3)
+
+/* PRCM_IRQENABLE_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_EN                          (1 << 6)
+#define OMAP24XX_TRANSITION_EN                          (1 << 5)
+#define OMAP24XX_EVGENOFF_EN                            (1 << 4)
+#define OMAP24XX_EVGENON_EN                             (1 << 3)
+
+/* PRCM_VOLTCTRL */
+#define OMAP24XX_AUTO_EXTVOLT                           (1 << 15)
+#define OMAP24XX_FORCE_EXTVOLT                          (1 << 14)
+#define OMAP24XX_SETOFF_LEVEL_SHIFT                     12
+#define OMAP24XX_SETOFF_LEVEL_MASK                      (0x3 << 12)
+#define OMAP24XX_MEMRETCTRL                             (1 << 8)
+#define OMAP24XX_SETRET_LEVEL_SHIFT                     6
+#define OMAP24XX_SETRET_LEVEL_MASK                      (0x3 << 6)
+#define OMAP24XX_VOLT_LEVEL_SHIFT                       0
+#define OMAP24XX_VOLT_LEVEL_MASK                        (0x3 << 0)
+
+/* PRCM_VOLTST */
+#define OMAP24XX_ST_VOLTLEVEL_SHIFT                     0
+#define OMAP24XX_ST_VOLTLEVEL_MASK                      (0x3 << 0)
+
+/* PRCM_CLKSRC_CTRL specific bits */
+
+/* PRCM_CLKOUT_CTRL */
+#define OMAP2420_CLKOUT2_EN_SHIFT                       15
+#define OMAP2420_CLKOUT2_EN                             (1 << 15)
+#define OMAP2420_CLKOUT2_DIV_SHIFT                      11
+#define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
+#define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
+#define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
+#define OMAP24XX_CLKOUT_EN_SHIFT                        7
+#define OMAP24XX_CLKOUT_EN                              (1 << 7)
+#define OMAP24XX_CLKOUT_DIV_SHIFT                       3
+#define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
+#define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
+#define OMAP24XX_CLKOUT_SOURCE_MASK                     (0x3 << 0)
+
+/* PRCM_CLKEMUL_CTRL */
+#define OMAP24XX_EMULATION_EN_SHIFT                     0
+#define OMAP24XX_EMULATION_EN                           (1 << 0)
+
+/* PRCM_CLKCFG_CTRL */
+#define OMAP24XX_VALID_CONFIG                           (1 << 0)
+
+/* PRCM_CLKCFG_STATUS */
+#define OMAP24XX_CONFIG_STATUS                          (1 << 0)
+
+/* PRCM_VOLTSETUP specific bits */
+
+/* PRCM_CLKSSETUP specific bits */
+
+/* PRCM_POLCTRL */
+#define OMAP2420_CLKOUT2_POL                            (1 << 10)
+#define OMAP24XX_CLKOUT_POL                             (1 << 9)
+#define OMAP24XX_CLKREQ_POL                             (1 << 8)
+#define OMAP2430_USE_POWEROK                            (1 << 2)
+#define OMAP2430_POWEROK_POL                            (1 << 1)
+#define OMAP24XX_EXTVOL_POL                             (1 << 0)
+
+/* RM_RSTST_MPU specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP2430_PM_WKDEP_MPU_EN_MDM                    (1 << 5)
+#define OMAP24XX_PM_WKDEP_MPU_EN_DSP                    (1 << 2)
+
+/* PM_EVGENCTRL_MPU specific bits */
+
+/* PM_EVEGENONTIM_MPU specific bits */
+
+/* PM_EVEGENOFFTIM_MPU specific bits */
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP2430_FORCESTATE                             (1 << 18)
+
+/* PM_PWSTST_MPU specific bits */
+/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_WKEN2_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits*/
+
+/* PM_WKST2_CORE specific bits */
+
+/* PM_WKDEP_CORE specific bits*/
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM                   (1 << 5)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX                   (1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP                   (1 << 2)
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP24XX_MEMORYCHANGE                           (1 << 20)
+#define OMAP24XX_MEM3ONSTATE_SHIFT                      14
+#define OMAP24XX_MEM3ONSTATE_MASK                       (0x3 << 14)
+#define OMAP24XX_MEM2ONSTATE_SHIFT                      12
+#define OMAP24XX_MEM2ONSTATE_MASK                       (0x3 << 12)
+#define OMAP24XX_MEM1ONSTATE_SHIFT                      10
+#define OMAP24XX_MEM1ONSTATE_MASK                       (0x3 << 10)
+#define OMAP24XX_MEM3RETSTATE                           (1 << 5)
+#define OMAP24XX_MEM2RETSTATE                           (1 << 4)
+#define OMAP24XX_MEM1RETSTATE                           (1 << 3)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP24XX_MEM3STATEST_SHIFT                      14
+#define OMAP24XX_MEM3STATEST_MASK                       (0x3 << 14)
+#define OMAP24XX_MEM2STATEST_SHIFT                      12
+#define OMAP24XX_MEM2STATEST_MASK                       (0x3 << 12)
+#define OMAP24XX_MEM1STATEST_SHIFT                      10
+#define OMAP24XX_MEM1STATEST_MASK                       (0x3 << 10)
+
+/* RM_RSTCTRL_GFX */
+#define OMAP24XX_GFX_RST                                (1 << 0)
+
+/* RM_RSTST_GFX specific bits */
+#define OMAP24XX_GFX_SW_RST                             (1 << 4)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+/* 2430 often calls EN_WAKEUP "EN_WKUP" */
+
+/* RM_RSTCTRL_WKUP specific bits */
+
+/* RM_RSTTIME_WKUP specific bits */
+
+/* RM_RSTST_WKUP specific bits */
+/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST                            (1 << 6)
+#define OMAP24XX_SECU_WD_RST                            (1 << 5)
+#define OMAP24XX_MPU_WD_RST                             (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST                          (1 << 3)
+
+/* PM_WKEN_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+
+/* RM_RSTCTRL_DSP */
+#define OMAP2420_RST_IVA                                (1 << 8)
+#define OMAP24XX_RST2_DSP                               (1 << 1)
+#define OMAP24XX_RST1_DSP                               (1 << 0)
+
+/* RM_RSTST_DSP specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP2420_IVA_SW_RST                             (1 << 8)
+#define OMAP24XX_DSP_SW_RST2                            (1 << 5)
+#define OMAP24XX_DSP_SW_RST1                            (1 << 4)
+
+/* PM_WKDEP_DSP specific bits */
+
+/* PM_PWSTCTRL_DSP specific bits */
+/* 2430 only: MEMONSTATE, MEMRETSTATE */
+#define OMAP2420_MEMIONSTATE_SHIFT                      12
+#define OMAP2420_MEMIONSTATE_MASK                       (0x3 << 12)
+#define OMAP2420_MEMIRETSTATE                           (1 << 4)
+
+/* PM_PWSTST_DSP specific bits */
+/* MEMSTATEST is 2430 only */
+#define OMAP2420_MEMISTATEST_SHIFT                      12
+#define OMAP2420_MEMISTATEST_MASK                       (0x3 << 12)
+
+/* PRCM_IRQSTATUS_DSP specific bits */
+
+/* PRCM_IRQENABLE_DSP specific bits */
+
+/* RM_RSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_PWRON1_MDM                             (1 << 1)
+#define OMAP2430_RST1_MDM                               (1 << 0)
+
+/* RM_RSTST_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_MDM_SECU_VIOL                          (1 << 6)
+#define OMAP2430_MDM_SW_PWRON1                          (1 << 5)
+#define OMAP2430_MDM_SW_RST1                            (1 << 4)
+
+/* PM_WKEN_MDM */
+/* 2430 only */
+#define OMAP2430_PM_WKEN_MDM_EN_MDM                     (1 << 0)
+
+/* PM_WKST_MDM specific bits */
+/* 2430 only */
+
+/* PM_WKDEP_MDM specific bits */
+/* 2430 only */
+
+/* PM_PWSTCTRL_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_KILLDOMAINWKUP                         (1 << 19)
+
+/* PM_PWSTST_MDM specific bits */
+/* 2430 only */
+
+/* PRCM_IRQSTATUS_IVA */
+/* 2420 only */
+
+/* PRCM_IRQENABLE_IVA */
+/* 2420 only */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
new file mode 100644
index 000000000000..b4686bc345ca
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -0,0 +1,582 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Power/Reset Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Shared register bits */
+
+/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
+#define OMAP3430_ON_SHIFT                               24
+#define OMAP3430_ON_MASK                                (0xff << 24)
+#define OMAP3430_ONLP_SHIFT                             16
+#define OMAP3430_ONLP_MASK                              (0xff << 16)
+#define OMAP3430_RET_SHIFT                              8
+#define OMAP3430_RET_MASK                               (0xff << 8)
+#define OMAP3430_OFF_SHIFT                              0
+#define OMAP3430_OFF_MASK                               (0xff << 0)
+
+/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
+#define OMAP3430_ERROROFFSET_SHIFT                      24
+#define OMAP3430_ERROROFFSET_MASK                       (0xff << 24)
+#define OMAP3430_ERRORGAIN_SHIFT                        16
+#define OMAP3430_ERRORGAIN_MASK                         (0xff << 16)
+#define OMAP3430_INITVOLTAGE_SHIFT                      8
+#define OMAP3430_INITVOLTAGE_MASK                       (0xff << 8)
+#define OMAP3430_TIMEOUTEN                              (1 << 3)
+#define OMAP3430_INITVDD                                (1 << 2)
+#define OMAP3430_FORCEUPDATE                            (1 << 1)
+#define OMAP3430_VPENABLE                               (1 << 0)
+
+/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
+#define OMAP3430_SMPSWAITTIMEMIN_SHIFT                  8
+#define OMAP3430_SMPSWAITTIMEMIN_MASK                   (0xffff << 8)
+#define OMAP3430_VSTEPMIN_SHIFT                         0
+#define OMAP3430_VSTEPMIN_MASK                          (0xff << 0)
+
+/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
+#define OMAP3430_SMPSWAITTIMEMAX_SHIFT                  8
+#define OMAP3430_SMPSWAITTIMEMAX_MASK                   (0xffff << 8)
+#define OMAP3430_VSTEPMAX_SHIFT                         0
+#define OMAP3430_VSTEPMAX_MASK                          (0xff << 0)
+
+/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
+#define OMAP3430_VDDMAX_SHIFT                           24
+#define OMAP3430_VDDMAX_MASK                            (0xff << 24)
+#define OMAP3430_VDDMIN_SHIFT                           16
+#define OMAP3430_VDDMIN_MASK                            (0xff << 16)
+#define OMAP3430_TIMEOUT_SHIFT                          0
+#define OMAP3430_TIMEOUT_MASK                           (0xffff << 0)
+
+/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
+#define OMAP3430_VPVOLTAGE_SHIFT                        0
+#define OMAP3430_VPVOLTAGE_MASK                         (0xff << 0)
+
+/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
+#define OMAP3430_VPINIDLE                               (1 << 0)
+
+/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
+#define OMAP3430_EN_PER                                 (1 << 7)
+
+/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
+#define OMAP3430_MEMORYCHANGE                           (1 << 3)
+
+/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
+#define OMAP3430_LOGICSTATEST                           (1 << 2)
+
+/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
+#define OMAP3430_LASTLOGICSTATEENTERED                          (1 << 2)
+
+/*
+ * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
+ * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
+ * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
+ */
+#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT                    0
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK                     (0x3 << 0)
+
+/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
+#define OMAP3430_WKUP_ST                                (1 << 0)
+
+/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
+#define OMAP3430_WKUP_EN                                        (1 << 0)
+
+/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
+#define OMAP3430_GRPSEL_MMC2                            (1 << 25)
+#define OMAP3430_GRPSEL_MMC1                            (1 << 24)
+#define OMAP3430_GRPSEL_MCSPI4                          (1 << 21)
+#define OMAP3430_GRPSEL_MCSPI3                          (1 << 20)
+#define OMAP3430_GRPSEL_MCSPI2                          (1 << 19)
+#define OMAP3430_GRPSEL_MCSPI1                          (1 << 18)
+#define OMAP3430_GRPSEL_I2C3                            (1 << 17)
+#define OMAP3430_GRPSEL_I2C2                            (1 << 16)
+#define OMAP3430_GRPSEL_I2C1                            (1 << 15)
+#define OMAP3430_GRPSEL_UART2                           (1 << 14)
+#define OMAP3430_GRPSEL_UART1                           (1 << 13)
+#define OMAP3430_GRPSEL_GPT11                           (1 << 12)
+#define OMAP3430_GRPSEL_GPT10                           (1 << 11)
+#define OMAP3430_GRPSEL_MCBSP5                          (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1                          (1 << 9)
+#define OMAP3430_GRPSEL_HSOTGUSB                        (1 << 4)
+#define OMAP3430_GRPSEL_D2D                             (1 << 3)
+
+/*
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
+ * PM_PWSTCTRL_PER shared bits
+ */
+#define OMAP3430_MEMONSTATE_SHIFT                       16
+#define OMAP3430_MEMONSTATE_MASK                        (0x3 << 16)
+#define OMAP3430_MEMRETSTATE                            (1 << 8)
+
+/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3430_GRPSEL_GPIO6                           (1 << 17)
+#define OMAP3430_GRPSEL_GPIO5                           (1 << 16)
+#define OMAP3430_GRPSEL_GPIO4                           (1 << 15)
+#define OMAP3430_GRPSEL_GPIO3                           (1 << 14)
+#define OMAP3430_GRPSEL_GPIO2                           (1 << 13)
+#define OMAP3430_GRPSEL_UART3                           (1 << 11)
+#define OMAP3430_GRPSEL_GPT9                            (1 << 10)
+#define OMAP3430_GRPSEL_GPT8                            (1 << 9)
+#define OMAP3430_GRPSEL_GPT7                            (1 << 8)
+#define OMAP3430_GRPSEL_GPT6                            (1 << 7)
+#define OMAP3430_GRPSEL_GPT5                            (1 << 6)
+#define OMAP3430_GRPSEL_GPT4                            (1 << 5)
+#define OMAP3430_GRPSEL_GPT3                            (1 << 4)
+#define OMAP3430_GRPSEL_GPT2                            (1 << 3)
+#define OMAP3430_GRPSEL_MCBSP4                          (1 << 2)
+#define OMAP3430_GRPSEL_MCBSP3                          (1 << 1)
+#define OMAP3430_GRPSEL_MCBSP2                          (1 << 0)
+
+/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
+#define OMAP3430_GRPSEL_IO                              (1 << 8)
+#define OMAP3430_GRPSEL_SR2                             (1 << 7)
+#define OMAP3430_GRPSEL_SR1                             (1 << 6)
+#define OMAP3430_GRPSEL_GPIO1                           (1 << 3)
+#define OMAP3430_GRPSEL_GPT12                           (1 << 1)
+#define OMAP3430_GRPSEL_GPT1                            (1 << 0)
+
+/* Bits specific to each register */
+
+/* RM_RSTCTRL_IVA2 */
+#define OMAP3430_RST3_IVA2                              (1 << 2)
+#define OMAP3430_RST2_IVA2                              (1 << 1)
+#define OMAP3430_RST1_IVA2                              (1 << 0)
+
+/* RM_RSTST_IVA2 specific bits */
+#define OMAP3430_EMULATION_VSEQ_RST                     (1 << 13)
+#define OMAP3430_EMULATION_VHWA_RST                     (1 << 12)
+#define OMAP3430_EMULATION_IVA2_RST                     (1 << 11)
+#define OMAP3430_IVA2_SW_RST3                           (1 << 10)
+#define OMAP3430_IVA2_SW_RST2                           (1 << 9)
+#define OMAP3430_IVA2_SW_RST1                           (1 << 8)
+
+/* PM_WKDEP_IVA2 specific bits */
+
+/* PM_PWSTCTRL_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMONSTATE_SHIFT                 22
+#define OMAP3430_L2FLATMEMONSTATE_MASK                  (0x3 << 22)
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT         20
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK          (0x3 << 20)
+#define OMAP3430_L1FLATMEMONSTATE_SHIFT                 18
+#define OMAP3430_L1FLATMEMONSTATE_MASK                  (0x3 << 18)
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT         16
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK          (0x3 << 16)
+#define OMAP3430_L2FLATMEMRETSTATE                      (1 << 11)
+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE              (1 << 10)
+#define OMAP3430_L1FLATMEMRETSTATE                      (1 << 9)
+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE              (1 << 8)
+
+/* PM_PWSTST_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMSTATEST_SHIFT                 10
+#define OMAP3430_L2FLATMEMSTATEST_MASK                  (0x3 << 10)
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT         8
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK          (0x3 << 8)
+#define OMAP3430_L1FLATMEMSTATEST_SHIFT                 6
+#define OMAP3430_L1FLATMEMSTATEST_MASK                  (0x3 << 6)
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT         4
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK          (0x3 << 4)
+
+/* PM_PREPWSTST_IVA2 specific bits */
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT                10
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK                 (0x3 << 10)
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT        8
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK         (0x3 << 8)
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT                6
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK                 (0x3 << 6)
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT        4
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK         (0x3 << 4)
+
+/* PRM_IRQSTATUS_IVA2 specific bits */
+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST        (1 << 2)
+#define OMAP3430_FORCEWKUP_ST                           (1 << 1)
+
+/* PRM_IRQENABLE_IVA2 specific bits */
+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN          (1 << 2)
+#define OMAP3430_FORCEWKUP_EN                                   (1 << 1)
+
+/* PRM_REVISION specific bits */
+
+/* PRM_SYSCONFIG specific bits */
+
+/* PRM_IRQSTATUS_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT            25
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST                  (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_ST                       (1 << 24)
+#define OMAP3430_VC_RAERR_ST                            (1 << 23)
+#define OMAP3430_VC_SAERR_ST                            (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_ST                       (1 << 21)
+#define OMAP3430_VP2_EQVALUE_ST                         (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_ST                       (1 << 19)
+#define OMAP3430_VP2_MAXVDD_ST                          (1 << 18)
+#define OMAP3430_VP2_MINVDD_ST                          (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_ST                   (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_ST                       (1 << 15)
+#define OMAP3430_VP1_EQVALUE_ST                         (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_ST                       (1 << 13)
+#define OMAP3430_VP1_MAXVDD_ST                          (1 << 12)
+#define OMAP3430_VP1_MINVDD_ST                          (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_ST                   (1 << 10)
+#define OMAP3430_IO_ST                                  (1 << 9)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST         (1 << 8)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
+#define OMAP3430_MPU_DPLL_ST                            (1 << 7)
+#define OMAP3430_MPU_DPLL_ST_SHIFT                      7
+#define OMAP3430_PERIPH_DPLL_ST                         (1 << 6)
+#define OMAP3430_PERIPH_DPLL_ST_SHIFT                   6
+#define OMAP3430_CORE_DPLL_ST                           (1 << 5)
+#define OMAP3430_CORE_DPLL_ST_SHIFT                     5
+#define OMAP3430_TRANSITION_ST                          (1 << 4)
+#define OMAP3430_EVGENOFF_ST                            (1 << 3)
+#define OMAP3430_EVGENON_ST                             (1 << 2)
+#define OMAP3430_FS_USB_WKUP_ST                         (1 << 1)
+
+/* PRM_IRQENABLE_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT              25
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN                    (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_EN                               (1 << 24)
+#define OMAP3430_VC_RAERR_EN                                    (1 << 23)
+#define OMAP3430_VC_SAERR_EN                                    (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_EN                               (1 << 21)
+#define OMAP3430_VP2_EQVALUE_EN                                 (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_EN                               (1 << 19)
+#define OMAP3430_VP2_MAXVDD_EN                                  (1 << 18)
+#define OMAP3430_VP2_MINVDD_EN                                  (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_EN                           (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_EN                               (1 << 15)
+#define OMAP3430_VP1_EQVALUE_EN                                 (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_EN                               (1 << 13)
+#define OMAP3430_VP1_MAXVDD_EN                                  (1 << 12)
+#define OMAP3430_VP1_MINVDD_EN                                  (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_EN                           (1 << 10)
+#define OMAP3430_IO_EN                                          (1 << 9)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN           (1 << 8)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT     8
+#define OMAP3430_MPU_DPLL_RECAL_EN                              (1 << 7)
+#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT                        7
+#define OMAP3430_PERIPH_DPLL_RECAL_EN                           (1 << 6)
+#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT                     6
+#define OMAP3430_CORE_DPLL_RECAL_EN                             (1 << 5)
+#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT                       5
+#define OMAP3430_TRANSITION_EN                                  (1 << 4)
+#define OMAP3430_EVGENOFF_EN                                    (1 << 3)
+#define OMAP3430_EVGENON_EN                                     (1 << 2)
+#define OMAP3430_FS_USB_WKUP_EN                                 (1 << 1)
+
+/* RM_RSTST_MPU specific bits */
+#define OMAP3430_EMULATION_MPU_RST                      (1 << 11)
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP3430_PM_WKDEP_MPU_EN_DSS                    (1 << 5)
+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2                   (1 << 2)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP3430_OFFLOADMODE_SHIFT                      3
+#define OMAP3430_OFFLOADMODE_MASK                       (0x3 << 3)
+#define OMAP3430_ONLOADMODE_SHIFT                       1
+#define OMAP3430_ONLOADMODE_MASK                        (0x3 << 1)
+#define OMAP3430_ENABLE                                 (1 << 0)
+
+/* PM_EVGENONTIM_MPU */
+#define OMAP3430_ONTIMEVAL_SHIFT                        0
+#define OMAP3430_ONTIMEVAL_MASK                         (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+#define OMAP3430_OFFTIMEVAL_SHIFT                       0
+#define OMAP3430_OFFTIMEVAL_MASK                        (0xffffffff << 0)
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP3430_L2CACHEONSTATE_SHIFT                   16
+#define OMAP3430_L2CACHEONSTATE_MASK                    (0x3 << 16)
+#define OMAP3430_L2CACHERETSTATE                        (1 << 8)
+#define OMAP3430_LOGICL1CACHERETSTATE                   (1 << 2)
+
+/* PM_PWSTST_MPU specific bits */
+#define OMAP3430_L2CACHESTATEST_SHIFT                   6
+#define OMAP3430_L2CACHESTATEST_MASK                    (0x3 << 6)
+#define OMAP3430_LOGICL1CACHESTATEST                    (1 << 2)
+
+/* PM_PREPWSTST_MPU specific bits */
+#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT          6
+#define OMAP3430_LASTL2CACHESTATEENTERED_MASK           (0x3 << 6)
+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED           (1 << 2)
+
+/* RM_RSTCTRL_CORE */
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON              (1 << 1)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST                   (1 << 0)
+
+/* RM_RSTST_CORE specific bits */
+#define OMAP3430_MODEM_SECURITY_VIOL_RST                (1 << 10)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON        (1 << 9)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST             (1 << 8)
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_MPUGRPSEL1_CORE specific bits */
+#define OMAP3430_GRPSEL_FSHOSTUSB                       (1 << 5)
+
+/* PM_IVA2GRPSEL1_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits */
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP3430_MEM2ONSTATE_SHIFT                      18
+#define OMAP3430_MEM2ONSTATE_MASK                       (0x3 << 18)
+#define OMAP3430_MEM1ONSTATE_SHIFT                      16
+#define OMAP3430_MEM1ONSTATE_MASK                       (0x3 << 16)
+#define OMAP3430_MEM2RETSTATE                           (1 << 9)
+#define OMAP3430_MEM1RETSTATE                           (1 << 8)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP3430_MEM2STATEST_SHIFT                      6
+#define OMAP3430_MEM2STATEST_MASK                       (0x3 << 6)
+#define OMAP3430_MEM1STATEST_SHIFT                      4
+#define OMAP3430_MEM1STATEST_MASK                       (0x3 << 4)
+
+/* PM_PREPWSTST_CORE specific bits */
+#define OMAP3430_LASTMEM2STATEENTERED_SHIFT             6
+#define OMAP3430_LASTMEM2STATEENTERED_MASK              (0x3 << 6)
+#define OMAP3430_LASTMEM1STATEENTERED_SHIFT             4
+#define OMAP3430_LASTMEM1STATEENTERED_MASK              (0x3 << 4)
+
+/* RM_RSTST_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_PWSTST_GFX specific bits */
+
+/* PM_PREPWSTST_GFX specific bits */
+
+/* PM_WKEN_WKUP specific bits */
+#define OMAP3430_EN_IO                                  (1 << 8)
+
+/* PM_MPUGRPSEL_WKUP specific bits */
+
+/* PM_IVA2GRPSEL_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+#define OMAP3430_ST_IO                                  (1 << 8)
+
+/* PRM_CLKSEL */
+#define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
+#define OMAP3430_SYS_CLKIN_SEL_MASK                     (0x7 << 0)
+
+/* PRM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT_EN                              (1 << 7)
+#define OMAP3430_CLKOUT_EN_SHIFT                        7
+
+/* RM_RSTST_DSS specific bits */
+
+/* PM_WKEN_DSS */
+#define OMAP3430_PM_WKEN_DSS_EN_DSS                     (1 << 0)
+
+/* PM_WKDEP_DSS specific bits */
+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_DSS specific bits */
+
+/* PM_PWSTST_DSS specific bits */
+
+/* PM_PREPWSTST_DSS specific bits */
+
+/* RM_RSTST_CAM specific bits */
+
+/* PM_WKDEP_CAM specific bits */
+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_CAM specific bits */
+
+/* PM_PWSTST_CAM specific bits */
+
+/* PM_PREPWSTST_CAM specific bits */
+
+/* PM_PWSTCTRL_USBHOST specific bits */
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT                (1 << 4)
+
+/* RM_RSTST_PER specific bits */
+
+/* PM_WKEN_PER specific bits */
+
+/* PM_MPUGRPSEL_PER specific bits */
+
+/* PM_IVA2GRPSEL_PER specific bits */
+
+/* PM_WKST_PER specific bits */
+
+/* PM_WKDEP_PER specific bits */
+#define OMAP3430_PM_WKDEP_PER_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_PER specific bits */
+
+/* PM_PWSTST_PER specific bits */
+
+/* PM_PREPWSTST_PER specific bits */
+
+/* RM_RSTST_EMU specific bits */
+
+/* PM_PWSTST_EMU specific bits */
+
+/* PRM_VC_SMPS_SA */
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT               16
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK                (0x7f << 16)
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT               0
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK                (0x7f << 0)
+
+/* PRM_VC_SMPS_VOL_RA */
+#define OMAP3430_VOLRA1_SHIFT                           16
+#define OMAP3430_VOLRA1_MASK                            (0xff << 16)
+#define OMAP3430_VOLRA0_SHIFT                           0
+#define OMAP3430_VOLRA0_MASK                            (0xff << 0)
+
+/* PRM_VC_SMPS_CMD_RA */
+#define OMAP3430_CMDRA1_SHIFT                           16
+#define OMAP3430_CMDRA1_MASK                            (0xff << 16)
+#define OMAP3430_CMDRA0_SHIFT                           0
+#define OMAP3430_CMDRA0_MASK                            (0xff << 0)
+
+/* PRM_VC_CMD_VAL_0 specific bits */
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+
+/* PRM_VC_CH_CONF */
+#define OMAP3430_CMD1                                   (1 << 20)
+#define OMAP3430_RACEN1                                 (1 << 19)
+#define OMAP3430_RAC1                                   (1 << 18)
+#define OMAP3430_RAV1                                   (1 << 17)
+#define OMAP3430_PRM_VC_CH_CONF_SA1                     (1 << 16)
+#define OMAP3430_CMD0                                   (1 << 4)
+#define OMAP3430_RACEN0                                 (1 << 3)
+#define OMAP3430_RAC0                                   (1 << 2)
+#define OMAP3430_RAV0                                   (1 << 1)
+#define OMAP3430_PRM_VC_CH_CONF_SA0                     (1 << 0)
+
+/* PRM_VC_I2C_CFG */
+#define OMAP3430_HSMASTER                               (1 << 5)
+#define OMAP3430_SREN                                   (1 << 4)
+#define OMAP3430_HSEN                                   (1 << 3)
+#define OMAP3430_MCODE_SHIFT                            0
+#define OMAP3430_MCODE_MASK                             (0x7 << 0)
+
+/* PRM_VC_BYPASS_VAL */
+#define OMAP3430_VALID                                  (1 << 24)
+#define OMAP3430_DATA_SHIFT                             16
+#define OMAP3430_DATA_MASK                              (0xff << 16)
+#define OMAP3430_REGADDR_SHIFT                          8
+#define OMAP3430_REGADDR_MASK                           (0xff << 8)
+#define OMAP3430_SLAVEADDR_SHIFT                        0
+#define OMAP3430_SLAVEADDR_MASK                         (0x7f << 0)
+
+/* PRM_RSTCTRL */
+#define OMAP3430_RST_DPLL3                              (1 << 2)
+#define OMAP3430_RST_GS                                 (1 << 1)
+
+/* PRM_RSTTIME */
+#define OMAP3430_RSTTIME2_SHIFT                         8
+#define OMAP3430_RSTTIME2_MASK                          (0x1f << 8)
+#define OMAP3430_RSTTIME1_SHIFT                         0
+#define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
+
+/* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST                         (1 << 10)
+#define OMAP3430_ICEPICK_RST                            (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST               (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST               (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST                      (1 << 6)
+#define OMAP3430_SECURE_WD_RST                          (1 << 5)
+#define OMAP3430_MPU_WD_RST                             (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST                      (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST                          (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST                        (1 << 0)
+
+/* PRM_VOLTCTRL */
+#define OMAP3430_SEL_VMODE                              (1 << 4)
+#define OMAP3430_SEL_OFF                                (1 << 3)
+#define OMAP3430_AUTO_OFF                               (1 << 2)
+#define OMAP3430_AUTO_RET                               (1 << 1)
+#define OMAP3430_AUTO_SLEEP                             (1 << 0)
+
+/* PRM_SRAM_PCHARGE */
+#define OMAP3430_PCHARGE_TIME_SHIFT                     0
+#define OMAP3430_PCHARGE_TIME_MASK                      (0xff << 0)
+
+/* PRM_CLKSRC_CTRL */
+#define OMAP3430_SYSCLKDIV_SHIFT                        6
+#define OMAP3430_SYSCLKDIV_MASK                         (0x3 << 6)
+#define OMAP3430_AUTOEXTCLKMODE_SHIFT                   3
+#define OMAP3430_AUTOEXTCLKMODE_MASK                    (0x3 << 3)
+#define OMAP3430_SYSCLKSEL_SHIFT                        0
+#define OMAP3430_SYSCLKSEL_MASK                         (0x3 << 0)
+
+/* PRM_VOLTSETUP1 */
+#define OMAP3430_SETUP_TIME2_SHIFT                      16
+#define OMAP3430_SETUP_TIME2_MASK                       (0xffff << 16)
+#define OMAP3430_SETUP_TIME1_SHIFT                      0
+#define OMAP3430_SETUP_TIME1_MASK                       (0xffff << 0)
+
+/* PRM_VOLTOFFSET */
+#define OMAP3430_OFFSET_TIME_SHIFT                      0
+#define OMAP3430_OFFSET_TIME_MASK                       (0xffff << 0)
+
+/* PRM_CLKSETUP */
+#define OMAP3430_SETUP_TIME_SHIFT                       0
+#define OMAP3430_SETUP_TIME_MASK                        (0xffff << 0)
+
+/* PRM_POLCTRL */
+#define OMAP3430_OFFMODE_POL                            (1 << 3)
+#define OMAP3430_CLKOUT_POL                             (1 << 2)
+#define OMAP3430_CLKREQ_POL                             (1 << 1)
+#define OMAP3430_EXTVOL_POL                             (1 << 0)
+
+/* PRM_VOLTSETUP2 */
+#define OMAP3430_OFFMODESETUPTIME_SHIFT                 0
+#define OMAP3430_OFFMODESETUPTIME_MASK                  (0xffff << 0)
+
+/* PRM_VP1_CONFIG specific bits */
+
+/* PRM_VP1_VSTEPMIN specific bits */
+
+/* PRM_VP1_VSTEPMAX specific bits */
+
+/* PRM_VP1_VLIMITTO specific bits */
+
+/* PRM_VP1_VOLTAGE specific bits */
+
+/* PRM_VP1_STATUS specific bits */
+
+/* PRM_VP2_CONFIG specific bits */
+
+/* PRM_VP2_VSTEPMIN specific bits */
+
+/* PRM_VP2_VSTEPMAX specific bits */
+
+/* PRM_VP2_VLIMITTO specific bits */
+
+/* PRM_VP2_VOLTAGE specific bits */
+
+/* PRM_VP2_STATUS specific bits */
+
+/* RM_RSTST_NEON specific bits */
+
+/* PM_WKDEP_NEON specific bits */
+
+/* PM_PWSTCTRL_NEON specific bits */
+
+/* PM_PWSTST_NEON specific bits */
+
+/* PM_PREPWSTST_NEON specific bits */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
new file mode 100644
index 000000000000..ab7649afd891
--- /dev/null
+++ b/arch/arm/mach-omap2/prm.h
@@ -0,0 +1,316 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
+
+/*
+ * OMAP2/3 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_PRM_REGADDR(module, reg)                                   \
+        (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
+#else
+#define OMAP2420_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+#define OMAP34XX_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global PRM registers
+ * Use prm_{read,write}_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ *
+ */
+
+#define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP24XX_PRCM_VOLTCTRL          OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP24XX_PRCM_CLKCFG_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP24XX_PRCM_CLKCFG_STATUS     OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP24XX_PRCM_VOLTSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP24XX_PRCM_CLKSSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP24XX_PRCM_POLCTRL           OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP3430_PRM_REVISION           OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3430_PRM_SYSCONFIG          OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3430_PRM_VC_CH_CONF         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3430_PRM_RSTCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3430_PRM_RSTTIME            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3430_PRM_RSTST              OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3430_PRM_VOLTCTRL           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3430_PRM_VOLTSETUP1         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3430_PRM_VOLTOFFSET         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3430_PRM_CLKSETUP           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3430_PRM_POLCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3430_PRM_VOLTSETUP2         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3430_PRM_VP1_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3430_PRM_VP1_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3430_PRM_VP2_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3430_PRM_VP2_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3430_PRM_CLKSEL             OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific PRM registers from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
+ * and IRQENABLE bits.)
+ *
+ */
+
+/* Registers appearing on both 24xx and 34xx */
+
+#define RM_RSTCTRL                                      0x0050
+#define RM_RSTTIME                                      0x0054
+#define RM_RSTST                                        0x0058
+
+#define PM_WKEN                                         0x00a0
+#define PM_WKEN1                                        PM_WKEN
+#define PM_WKST                                         0x00b0
+#define PM_WKST1                                        PM_WKST
+#define PM_WKDEP                                        0x00c8
+#define PM_EVGENCTRL                                    0x00d4
+#define PM_EVGENONTIM                                   0x00d8
+#define PM_EVGENOFFTIM                                  0x00dc
+#define PM_PWSTCTRL                                     0x00e0
+#define PM_PWSTST                                       0x00e4
+
+#define OMAP3430_PM_MPUGRPSEL                           0x00a4
+#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+
+#define OMAP3430_PM_IVAGRPSEL                           0x00a8
+#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+
+#define OMAP3430_PM_PREPWSTST                           0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+
+#ifndef __ASSEMBLER__
+
+/* Power/reset management domain register get/set */
+
+static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+        __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
+}
+
+static inline u32 prm_read_mod_reg(s16 module, s16 idx)
+{
+        return __raw_readl(OMAP_PRM_REGADDR(module, idx));
+}
+
+#endif
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT                            0
+#define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT                           0
+#define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT                           0
+#define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT                            6
+#define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT                       3
+#define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT                            0
+#define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT                          3
+#define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT                           1
+#define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
+#define OMAP_ENABLE                                     (1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT                             8
+#define OMAP_RSTTIME2_MASK                              (0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT                             0
+#define OMAP_RSTTIME1_MASK                              (0xff << 0)
+
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3                                  (1 << 2)
+#define OMAP_RST_GS                                     (1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *       PM_PWSTST_NEON
+ */
+#define OMAP_INTRANSITION                               (1 << 20)
+
+
+/*
+ * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *       PM_PWSTST_NEON
+ */
+#define OMAP_POWERSTATEST_SHIFT                         0
+#define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ *       called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST                         (1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST                             (1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST                             (1 << 1)
+#define OMAP_GLOBALCOLD_RST                             (1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ *       PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP                                    (1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE                              (1 << 2)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ *
+ * 2430: PM_PWSTCTRL_MDM shared bits
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ *       PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON shared bits
+ */
+#define OMAP_POWERSTATE_SHIFT                           0
+#define OMAP_POWERSTATE_MASK                            (0x3 << 0)
+
+
+#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
new file mode 100644
index 000000000000..d7f23bc9550a
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -0,0 +1,58 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
+#define __ARCH_ARM_MACH_OMAP2_SDRC_H
+
+/*
+ * OMAP2 SDRC register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <asm/arch/sdrc.h>
+
+#ifndef __ASSEMBLER__
+extern unsigned long omap2_sdrc_base;
+extern unsigned long omap2_sms_base;
+
+#define OMAP_SDRC_REGADDR(reg)                                          \
+                (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
+#define OMAP_SMS_REGADDR(reg)                                           \
+                (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
+
+/* SDRC global register get/set */
+
+static inline void sdrc_write_reg(u32 val, u16 reg)
+{
+        __raw_writel(val, OMAP_SDRC_REGADDR(reg));
+}
+
+static inline u32 sdrc_read_reg(u16 reg)
+{
+        return __raw_readl(OMAP_SDRC_REGADDR(reg));
+}
+
+/* SMS global register get/set */
+
+static inline void sms_write_reg(u32 val, u16 reg)
+{
+        __raw_writel(val, OMAP_SMS_REGADDR(reg));
+}
+
+static inline u32 sms_read_reg(u16 reg)
+{
+        return __raw_readl(OMAP_SMS_REGADDR(reg));
+}
+#else
+#define OMAP242X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
+#define OMAP243X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
+#define OMAP34XX_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+#endif  /* __ASSEMBLER__ */
+
+#endif
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S
index 16247d557853..46ccb9b8b583 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep.S
@@ -26,19 +26,10 @@
 #include <asm/arch/io.h>
 #include <asm/arch/pm.h>
 
-#define A_32KSYNC_CR_V          IO_ADDRESS(OMAP_TIMER32K_BASE+0x10)
-#define A_PRCM_VOLTCTRL_V       IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
-#define A_PRCM_CLKCFG_CTRL_V    IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
-#define A_CM_CLKEN_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
-#define A_CM_IDLEST_CKGEN_V     IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
-#define A_CM_CLKSEL1_PLL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
-#define A_CM_CLKSEL2_PLL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
+#include "sdrc.h"
 
-#define A_SDRC_DLLA_CTRL_V      IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60)
-#define A_SDRC_POWER_V          IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
-#define A_SDRC_RFR_CTRL_V       IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
+/* First address of reserved address space?  apparently valid for OMAP2 & 3 */
 #define A_SDRC0_V               (0xC0000000)
-#define A_SDRC_MANUAL_V         IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
 
         .text
 
@@ -126,17 +117,11 @@ loop2:
         ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
 
 A_SDRC_POWER:
-        .word A_SDRC_POWER_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
 A_SDRC0:
         .word A_SDRC0_V
-A_CM_CLKSEL2_PLL_S:
-        .word A_CM_CLKSEL2_PLL_V
-A_CM_CLKEN_PLL:
-        .word A_CM_CLKEN_PLL_V
 A_SDRC_DLLA_CTRL_S:
-        .word A_SDRC_DLLA_CTRL_V
-A_SDRC_MANUAL_S:
-        .word A_SDRC_MANUAL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
 ENTRY(omap24xx_cpu_suspend_sz)
         .word   . - omap24xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index b27576690f8d..4a9e49140716 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -27,19 +27,11 @@
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
 
-#include "prcm-regs.h"
+#include "sdrc.h"
+#include "prm.h"
+#include "cm.h"
 
-#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
-
-#define CM_CLKSEL2_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V         IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
-#define PRCM_CLKCFG_CTRL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
-#define CM_CLKEN_PLL_V          IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V       IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
-
-#define SDRC_DLLA_CTRL_V        IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V         IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
+#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
 
         .text
 
@@ -131,11 +123,11 @@ volt_delay:
 
 /* relative load constants */
 cm_clksel2_pll:
-        .word CM_CLKSEL2_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 sdrc_dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 prcm_voltctrl:
-        .word PRCM_VOLTCTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
 prcm_mask_val:
         .word 0xFFFF3FFC
 timer_32ksynct_cr:
@@ -225,13 +217,13 @@ volt_delay_c:
         mov     pc, lr                  @ back to caller
 
 ddr_cm_clksel2_pll:
-        .word CM_CLKSEL2_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 ddr_sdrc_dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 ddr_sdrc_rfr_ctrl:
-        .word SDRC_RFR_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 ddr_prcm_voltctrl:
-        .word PRCM_VOLTCTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
 ddr_timer_32ksynct:
@@ -316,17 +308,17 @@ wait_dll_lock:
         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
 set_config:
-        .word PRCM_CLKCFG_CTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
 pll_ctl:
-        .word CM_CLKEN_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
 pll_stat:
-        .word CM_IDLEST_CKGEN_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
 pll_div:
-        .word CM_CLKSEL1_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
 sdrc_rfr:
-        .word SDRC_RFR_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
 ENTRY(sram_set_prcm_sz)
         .word   . - sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 3234deedb946..78d05f203fff 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -3,6 +3,11 @@
  *
  * OMAP2 GP timer support.
  *
+ * Update to use new clocksource/clockevent layers
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * Original driver:
  * Copyright (C) 2005 Nokia Corporation
  * Author: Paul Mundt <paul.mundt@nokia.com>
  *         Juha Yrjölä <juha.yrjola@nokia.com>
@@ -25,24 +30,23 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
 #include <asm/arch/dmtimer.h>
 
 static struct omap_dm_timer *gptimer;
-
-static inline void omap2_gp_timer_start(unsigned long load_val)
-{
-        omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
-        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        omap_dm_timer_start(gptimer);
-}
+static struct clock_event_device clockevent_gpt;
 
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
-        omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        timer_tick();
+        struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
+        struct clock_event_device *evt = &clockevent_gpt;
+
+        omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
 
+        evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
@@ -52,20 +56,138 @@ static struct irqaction omap2_gp_timer_irq = {
         .handler        = omap2_gp_timer_interrupt,
 };
 
-static void __init omap2_gp_timer_init(void)
+static int omap2_gp_timer_set_next_event(unsigned long cycles,
+                                         struct clock_event_device *evt)
 {
-        u32 tick_period;
+        omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
+        omap_dm_timer_start(gptimer);
+
+        return 0;
+}
+
+static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+                                    struct clock_event_device *evt)
+{
+        u32 period;
+
+        omap_dm_timer_stop(gptimer);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
+                period -= 1;
+
+                omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
+                omap_dm_timer_start(gptimer);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device clockevent_gpt = {
+        .name           = "gp timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_next_event = omap2_gp_timer_set_next_event,
+        .set_mode       = omap2_gp_timer_set_mode,
+};
+
+static void __init omap2_gp_clockevent_init(void)
+{
+        u32 tick_rate;
 
-        omap_dm_timer_init();
         gptimer = omap_dm_timer_request_specific(1);
         BUG_ON(gptimer == NULL);
 
+#if defined(CONFIG_OMAP_32K_TIMER)
+        omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
+#else
         omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
-        tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
-        tick_period -= 1;
+#endif
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
 
+        omap2_gp_timer_irq.dev_id = (void *)gptimer;
         setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
-        omap2_gp_timer_start(tick_period);
+        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
+
+        clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
+                                     clockevent_gpt.shift);
+        clockevent_gpt.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+        clockevent_gpt.min_delta_ns =
+                clockevent_delta2ns(1, &clockevent_gpt);
+
+        clockevent_gpt.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&clockevent_gpt);
+}
+
+#ifdef CONFIG_OMAP_32K_TIMER
+/* 
+ * When 32k-timer is enabled, don't use GPTimer for clocksource
+ * instead, just leave default clocksource which uses the 32k
+ * sync counter.  See clocksource setup in see plat-omap/common.c. 
+ */
+
+static inline void __init omap2_gp_clocksource_init(void) {}
+#else
+/*
+ * clocksource
+ */
+static struct omap_dm_timer *gpt_clocksource;
+static cycle_t clocksource_read_cycles(void)
+{
+        return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
+}
+
+static struct clocksource clocksource_gpt = {
+        .name           = "gp timer",
+        .rating         = 300,
+        .read           = clocksource_read_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 24,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/* Setup free-running counter for clocksource */
+static void __init omap2_gp_clocksource_init(void)
+{
+        static struct omap_dm_timer *gpt;
+        u32 tick_rate, tick_period;
+        static char err1[] __initdata = KERN_ERR
+                "%s: failed to request dm-timer\n";
+        static char err2[] __initdata = KERN_ERR
+                "%s: can't register clocksource!\n";
+
+        gpt = omap_dm_timer_request();
+        if (!gpt)
+                printk(err1, clocksource_gpt.name);
+        gpt_clocksource = gpt;
+
+        omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
+        tick_period = (tick_rate / HZ) - 1;
+
+        omap_dm_timer_set_load(gpt, 1, 0);
+        omap_dm_timer_start(gpt);
+
+        clocksource_gpt.mult =
+                clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
+        if (clocksource_register(&clocksource_gpt))
+                printk(err2, clocksource_gpt.name);
+}
+#endif
+
+static void __init omap2_gp_timer_init(void)
+{
+        omap_dm_timer_init();
+
+        omap2_gp_clockevent_init();
+        omap2_gp_clocksource_init();
 }
 
 struct sys_timer omap_timer = {
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
deleted file mode 100644
index 58cc3c0333b6..000000000000
--- a/arch/arm/mach-orion/addr-map.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * arch/arm/mach-orion/addr-map.c
- *
- * Address map functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/hardware.h>
-#include "common.h"
-
-/*
- * The Orion has fully programable address map. There's a separate address
- * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
- * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
- * address decode windows that allow it to access any of the Orion resources.
- *
- * CPU address decoding --
- * Linux assumes that it is the boot loader that already setup the access to
- * DDR and internal registers.
- * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
- * Setup access to various devices located on the device bus interface (e.g.
- * flashes, RTC, etc) should be issued by machine-setup.c according to
- * specific board population (by using orion_setup_cpu_win()).
- *
- * Non-CPU Masters address decoding --
- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
- * banks only (the typical use case).
- * Setup access for each master to DDR is issued by common.c.
- *
- * Note: although orion_setbits() and orion_clrbits() are not atomic
- * no locking is necessary here since code in this file is only called
- * at boot time when there is no concurrency issues.
- */
-
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DDR              0
-#define TARGET_PCI              3
-#define TARGET_PCIE             4
-#define TARGET_DEV_BUS          1
-#define ATTR_DDR_CS(n)          (((n) ==0) ? 0xe :      \
-                                ((n) == 1) ? 0xd :      \
-                                ((n) == 2) ? 0xb :      \
-                                ((n) == 3) ? 0x7 : 0xf)
-#define ATTR_PCIE_MEM           0x59
-#define ATTR_PCIE_IO            0x51
-#define ATTR_PCI_MEM            0x59
-#define ATTR_PCI_IO             0x51
-#define ATTR_DEV_CS0            0x1e
-#define ATTR_DEV_CS1            0x1d
-#define ATTR_DEV_CS2            0x1b
-#define ATTR_DEV_BOOT           0xf
-#define WIN_EN                  1
-
-/*
- * Helpers to get DDR banks info
- */
-#define DDR_BASE_CS(n)          ORION_DDR_REG(0x1500 + ((n) * 8))
-#define DDR_SIZE_CS(n)          ORION_DDR_REG(0x1504 + ((n) * 8))
-#define DDR_MAX_CS              4
-#define DDR_REG_TO_SIZE(reg)    (((reg) | 0xffffff) + 1)
-#define DDR_REG_TO_BASE(reg)    ((reg) & 0xff000000)
-#define DDR_BANK_EN             1
-
-/*
- * CPU Address Decode Windows registers
- */
-#define CPU_WIN_CTRL(n)         ORION_BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n)         ORION_BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n)     ORION_BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n)     ORION_BRIDGE_REG(0x00c | ((n) << 4))
-#define CPU_MAX_WIN             8
-
-/*
- * Use this CPU address decode windows allocation
- */
-#define CPU_WIN_PCIE_IO         0
-#define CPU_WIN_PCI_IO          1
-#define CPU_WIN_PCIE_MEM        2
-#define CPU_WIN_PCI_MEM         3
-#define CPU_WIN_DEV_BOOT        4
-#define CPU_WIN_DEV_CS0         5
-#define CPU_WIN_DEV_CS1         6
-#define CPU_WIN_DEV_CS2         7
-
-/*
- * PCIE Address Decode Windows registers
- */
-#define PCIE_BAR_CTRL(n)        ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
-#define PCIE_BAR_LO(n)          ORION_PCIE_REG(0x0010 + ((n) * 8))
-#define PCIE_BAR_HI(n)          ORION_PCIE_REG(0x0014 + ((n) * 8))
-#define PCIE_WIN_CTRL(n)        (((n) < 5) ? \
-                                        ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
-                                        ORION_PCIE_REG(0x1880))
-#define PCIE_WIN_BASE(n)        (((n) < 5) ? \
-                                        ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
-                                        ORION_PCIE_REG(0x1884))
-#define PCIE_WIN_REMAP(n)       (((n) < 5) ? \
-                                        ORION_PCIE_REG(0x182c + ((n) << 4)) : \
-                                        ORION_PCIE_REG(0x188c))
-#define PCIE_DEFWIN_CTRL        ORION_PCIE_REG(0x18b0)
-#define PCIE_EXPROM_WIN_CTRL    ORION_PCIE_REG(0x18c0)
-#define PCIE_EXPROM_WIN_REMP    ORION_PCIE_REG(0x18c4)
-#define PCIE_MAX_BARS           3
-#define PCIE_MAX_WINS           6
-
-/*
- * Use PCIE BAR '1' for all DDR banks
- */
-#define PCIE_DRAM_BAR           1
-
-/*
- * PCI Address Decode Windows registers
- */
-#define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION_PCI_REG(0xc08) : \
-                                ((n) == 1) ? ORION_PCI_REG(0xd08) :  \
-                                ((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
-                                ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
-                                ((n) == 1) ? ORION_PCI_REG(0xd48) :  \
-                                ((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
-                                ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
-#define PCI_BAR_ENABLE          ORION_PCI_REG(0xc3c)
-#define PCI_CTRL_BASE_LO(n)     ORION_PCI_REG(0x1e00 | ((n) << 4))
-#define PCI_CTRL_BASE_HI(n)     ORION_PCI_REG(0x1e04 | ((n) << 4))
-#define PCI_CTRL_SIZE(n)        ORION_PCI_REG(0x1e08 | ((n) << 4))
-#define PCI_ADDR_DECODE_CTRL    ORION_PCI_REG(0xd3c)
-
-/*
- * PCI configuration heleprs for BAR settings
- */
-#define PCI_CONF_FUNC_BAR_CS(n)         ((n) >> 1)
-#define PCI_CONF_REG_BAR_LO_CS(n)       (((n) & 1) ? 0x18 : 0x10)
-#define PCI_CONF_REG_BAR_HI_CS(n)       (((n) & 1) ? 0x1c : 0x14)
-
-/*
- * Gigabit Ethernet Address Decode Windows registers
- */
-#define ETH_WIN_BASE(win)       ORION_ETH_REG(0x200 + ((win) * 8))
-#define ETH_WIN_SIZE(win)       ORION_ETH_REG(0x204 + ((win) * 8))
-#define ETH_WIN_REMAP(win)      ORION_ETH_REG(0x280 + ((win) * 4))
-#define ETH_WIN_EN              ORION_ETH_REG(0x290)
-#define ETH_WIN_PROT            ORION_ETH_REG(0x294)
-#define ETH_MAX_WIN             6
-#define ETH_MAX_REMAP_WIN       4
-
-/*
- * USB Address Decode Windows registers
- */
-#define USB_WIN_CTRL(i, w)      ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
-                                        : ORION_USB1_REG(0x320 + ((w) << 4)))
-#define USB_WIN_BASE(i, w)      ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
-                                        : ORION_USB1_REG(0x324 + ((w) << 4)))
-#define USB_MAX_WIN             4
-
-/*
- * SATA Address Decode Windows registers
- */
-#define SATA_WIN_CTRL(win)      ORION_SATA_REG(0x30 + ((win) * 0x10))
-#define SATA_WIN_BASE(win)      ORION_SATA_REG(0x34 + ((win) * 0x10))
-#define SATA_MAX_WIN            4
-
-static int __init orion_cpu_win_can_remap(u32 win)
-{
-        u32 dev, rev;
-
-        orion_pcie_id(&dev, &rev);
-        if ((dev == MV88F5281_DEV_ID && win < 4)
-            || (dev == MV88F5182_DEV_ID && win < 2)
-            || (dev == MV88F5181_DEV_ID && win < 2))
-                return 1;
-
-        return 0;
-}
-
-void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
-{
-        u32 win, attr, ctrl;
-
-        switch (target) {
-        case ORION_PCIE_IO:
-                target = TARGET_PCIE;
-                attr = ATTR_PCIE_IO;
-                win = CPU_WIN_PCIE_IO;
-                break;
-        case ORION_PCI_IO:
-                target = TARGET_PCI;
-                attr = ATTR_PCI_IO;
-                win = CPU_WIN_PCI_IO;
-                break;
-        case ORION_PCIE_MEM:
-                target = TARGET_PCIE;
-                attr = ATTR_PCIE_MEM;
-                win = CPU_WIN_PCIE_MEM;
-                break;
-        case ORION_PCI_MEM:
-                target = TARGET_PCI;
-                attr = ATTR_PCI_MEM;
-                win = CPU_WIN_PCI_MEM;
-                break;
-        case ORION_DEV_BOOT:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_BOOT;
-                win = CPU_WIN_DEV_BOOT;
-                break;
-        case ORION_DEV0:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_CS0;
-                win = CPU_WIN_DEV_CS0;
-                break;
-        case ORION_DEV1:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_CS1;
-                win = CPU_WIN_DEV_CS1;
-                break;
-        case ORION_DEV2:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_CS2;
-                win = CPU_WIN_DEV_CS2;
-                break;
-        case ORION_DDR:
-        case ORION_REGS:
-                /*
-                 * Must be mapped by bootloader.
-                 */
-        default:
-                target = attr = win = -1;
-                BUG();
-        }
-
-        base &= 0xffff0000;
-        ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
-                (target << 4) | WIN_EN);
-
-        orion_write(CPU_WIN_BASE(win), base);
-        orion_write(CPU_WIN_CTRL(win), ctrl);
-
-        if (orion_cpu_win_can_remap(win)) {
-                if (remap >= 0) {
-                        orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
-                        orion_write(CPU_WIN_REMAP_HI(win), 0);
-                } else {
-                        orion_write(CPU_WIN_REMAP_LO(win), base);
-                        orion_write(CPU_WIN_REMAP_HI(win), 0);
-                }
-        }
-}
-
-void __init orion_setup_cpu_wins(void)
-{
-        int i;
-
-        /*
-         * First, disable and clear windows
-         */
-        for (i = 0; i < CPU_MAX_WIN; i++) {
-                orion_write(CPU_WIN_BASE(i), 0);
-                orion_write(CPU_WIN_CTRL(i), 0);
-                if (orion_cpu_win_can_remap(i)) {
-                        orion_write(CPU_WIN_REMAP_LO(i), 0);
-                        orion_write(CPU_WIN_REMAP_HI(i), 0);
-                }
-        }
-
-        /*
-         * Setup windows for PCI+PCIe IO+MEM space.
-         */
-        orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
-                                ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
-        orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
-                                ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
-        orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
-                                ORION_PCIE_MEM_SIZE, -1);
-        orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
-                                ORION_PCI_MEM_SIZE, -1);
-}
-
-/*
- * Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
- * WIN[0-3] -> DRAM bank[0-3]
- */
-void __init orion_setup_pcie_wins(void)
-{
-        u32 base, size, i;
-
-        /*
-         * First, disable and clear BARs and windows
-         */
-        for (i = 1; i < PCIE_MAX_BARS; i++) {
-                orion_write(PCIE_BAR_CTRL(i), 0);
-                orion_write(PCIE_BAR_LO(i), 0);
-                orion_write(PCIE_BAR_HI(i), 0);
-        }
-
-        for (i = 0; i < PCIE_MAX_WINS; i++) {
-                orion_write(PCIE_WIN_CTRL(i), 0);
-                orion_write(PCIE_WIN_BASE(i), 0);
-                orion_write(PCIE_WIN_REMAP(i), 0);
-        }
-
-        /*
-         * Setup windows for DDR banks. Count total DDR size on the fly.
-         */
-        base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
-        size = 0;
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                u32 bank_base, bank_size;
-                bank_size = orion_read(DDR_SIZE_CS(i));
-                bank_base = orion_read(DDR_BASE_CS(i));
-                if (bank_size & DDR_BANK_EN) {
-                        bank_size = DDR_REG_TO_SIZE(bank_size);
-                        bank_base = DDR_REG_TO_BASE(bank_base);
-                        orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
-                        orion_write(PCIE_WIN_REMAP(i), 0);
-                        orion_write(PCIE_WIN_CTRL(i),
-                                        ((bank_size-1) & 0xffff0000) |
-                                        (ATTR_DDR_CS(i) << 8) |
-                                        (TARGET_DDR << 4) |
-                                        (PCIE_DRAM_BAR << 1) | WIN_EN);
-                        size += bank_size;
-                }
-        }
-
-        /*
-         * Setup BAR[1] to all DRAM banks
-         */
-        orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
-        orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
-        orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
-                                ((size - 1) & 0xffff0000) | WIN_EN);
-}
-
-void __init orion_setup_pci_wins(void)
-{
-        u32 base, size, i;
-
-        /*
-         * First, disable windows
-         */
-        orion_write(PCI_BAR_ENABLE, 0xffffffff);
-
-        /*
-         * Setup windows for DDR banks.
-         */
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                base = orion_read(DDR_BASE_CS(i));
-                size = orion_read(DDR_SIZE_CS(i));
-                if (size & DDR_BANK_EN) {
-                        u32 bus, dev, func, reg, val;
-                        size = DDR_REG_TO_SIZE(size);
-                        base = DDR_REG_TO_BASE(base);
-                        bus = orion_pci_local_bus_nr();
-                        dev = orion_pci_local_dev_nr();
-                        func = PCI_CONF_FUNC_BAR_CS(i);
-                        reg = PCI_CONF_REG_BAR_LO_CS(i);
-                        orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
-                        orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
-                                        (base & 0xfffff000) | (val & 0xfff));
-                        reg = PCI_CONF_REG_BAR_HI_CS(i);
-                        orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
-                        orion_write(PCI_BAR_SIZE_DDR_CS(i),
-                                        (size - 1) & 0xfffff000);
-                        orion_write(PCI_BAR_REMAP_DDR_CS(i),
-                                        base & 0xfffff000);
-                        orion_clrbits(PCI_BAR_ENABLE, (1 << i));
-                }
-        }
-
-        /*
-         * Disable automatic update of address remaping when writing to BARs
-         */
-        orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
-}
-
-void __init orion_setup_usb_wins(void)
-{
-        int i;
-        u32 usb_if, dev, rev;
-        u32 max_usb_if = 1;
-
-        orion_pcie_id(&dev, &rev);
-        if (dev == MV88F5182_DEV_ID)
-                max_usb_if = 2;
-
-        for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
-                /*
-                 * First, disable and clear windows
-                 */
-                for (i = 0; i < USB_MAX_WIN; i++) {
-                        orion_write(USB_WIN_BASE(usb_if, i), 0);
-                        orion_write(USB_WIN_CTRL(usb_if, i), 0);
-                }
-
-                /*
-                 * Setup windows for DDR banks.
-                 */
-                for (i = 0; i < DDR_MAX_CS; i++) {
-                        u32 base, size;
-                        size = orion_read(DDR_SIZE_CS(i));
-                        base = orion_read(DDR_BASE_CS(i));
-                        if (size & DDR_BANK_EN) {
-                                base = DDR_REG_TO_BASE(base);
-                                size = DDR_REG_TO_SIZE(size);
-                                orion_write(USB_WIN_CTRL(usb_if, i),
-                                                ((size-1) & 0xffff0000) |
-                                                (ATTR_DDR_CS(i) << 8) |
-                                                (TARGET_DDR << 4) | WIN_EN);
-                                orion_write(USB_WIN_BASE(usb_if, i),
-                                                base & 0xffff0000);
-                        }
-                }
-        }
-}
-
-void __init orion_setup_eth_wins(void)
-{
-        int i;
-
-        /*
-         * First, disable and clear windows
-         */
-        for (i = 0; i < ETH_MAX_WIN; i++) {
-                orion_write(ETH_WIN_BASE(i), 0);
-                orion_write(ETH_WIN_SIZE(i), 0);
-                orion_setbits(ETH_WIN_EN, 1 << i);
-                orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
-                if (i < ETH_MAX_REMAP_WIN)
-                        orion_write(ETH_WIN_REMAP(i), 0);
-        }
-
-        /*
-         * Setup windows for DDR banks.
-         */
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                u32 base, size;
-                size = orion_read(DDR_SIZE_CS(i));
-                base = orion_read(DDR_BASE_CS(i));
-                if (size & DDR_BANK_EN) {
-                        base = DDR_REG_TO_BASE(base);
-                        size = DDR_REG_TO_SIZE(size);
-                        orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
-                        orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
-                                        (ATTR_DDR_CS(i) << 8) |
-                                        TARGET_DDR);
-                        orion_clrbits(ETH_WIN_EN, 1 << i);
-                        orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
-                }
-        }
-}
-
-void __init orion_setup_sata_wins(void)
-{
-        int i;
-
-        /*
-         * First, disable and clear windows
-         */
-        for (i = 0; i < SATA_MAX_WIN; i++) {
-                orion_write(SATA_WIN_BASE(i), 0);
-                orion_write(SATA_WIN_CTRL(i), 0);
-        }
-
-        /*
-         * Setup windows for DDR banks.
-         */
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                u32 base, size;
-                size = orion_read(DDR_SIZE_CS(i));
-                base = orion_read(DDR_BASE_CS(i));
-                if (size & DDR_BANK_EN) {
-                        base = DDR_REG_TO_BASE(base);
-                        size = DDR_REG_TO_SIZE(size);
-                        orion_write(SATA_WIN_CTRL(i),
-                                        ((size-1) & 0xffff0000) |
-                                        (ATTR_DDR_CS(i) << 8) |
-                                        (TARGET_DDR << 4) | WIN_EN);
-                        orion_write(SATA_WIN_BASE(i),
-                                        base & 0xffff0000);
-                }
-        }
-}
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h
deleted file mode 100644
index 501497cc2c4d..000000000000
--- a/arch/arm/mach-orion/common.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef __ARCH_ORION_COMMON_H__
-#define __ARCH_ORION_COMMON_H__
-
-/*
- * Basic Orion init functions used early by machine-setup.
- */
-
-void __init orion_map_io(void);
-void __init orion_init_irq(void);
-void __init orion_init(void);
-
-/*
- * Enumerations and functions for Orion windows mapping. Used by Orion core
- * functions to map its interfaces and by the machine-setup to map its on-
- * board devices. Details in /mach-orion/addr-map.c
- */
-
-enum orion_target {
-        ORION_DEV_BOOT = 0,
-        ORION_DEV0,
-        ORION_DEV1,
-        ORION_DEV2,
-        ORION_PCIE_MEM,
-        ORION_PCIE_IO,
-        ORION_PCI_MEM,
-        ORION_PCI_IO,
-        ORION_DDR,
-        ORION_REGS,
-        ORION_MAX_TARGETS
-};
-
-void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
-void orion_setup_cpu_wins(void);
-void orion_setup_eth_wins(void);
-void orion_setup_usb_wins(void);
-void orion_setup_pci_wins(void);
-void orion_setup_pcie_wins(void);
-void orion_setup_sata_wins(void);
-
-/*
- * Shared code used internally by other Orion core functions.
- * (/mach-orion/pci.c)
- */
-
-struct pci_sys_data;
-struct pci_bus;
-
-void orion_pcie_id(u32 *dev, u32 *rev);
-u32 orion_pcie_local_bus_nr(void);
-u32 orion_pci_local_bus_nr(void);
-u32 orion_pci_local_dev_nr(void);
-int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
-struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
-
-/*
- * Valid GPIO pins according to MPP setup, used by machine-setup.
- * (/mach-orion/gpio.c).
- */
-
-void __init orion_gpio_set_valid_pins(u32 pins);
-void gpio_display(void);        /* debug */
-
-/*
- * Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
- */
-extern struct sys_timer orion_timer;
-
-/*
- * Pull in Orion Ethernet platform_data, used by machine-setup
- */
-
-struct mv643xx_eth_platform_data;
-
-void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
-
-/*
- * Orion Sata platform_data, used by machine-setup
- */
-
-struct mv_sata_platform_data;
-
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
-
-struct machine_desc;
-struct meminfo;
-struct tag;
-extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
-                                   char **, struct meminfo *);
-
-#endif /* __ARCH_ORION_COMMON_H__ */
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
deleted file mode 100644
index b109bb46681e..000000000000
--- a/arch/arm/mach-orion/pci.c
+++ /dev/null
@@ -1,557 +0,0 @@
-/*
- * arch/arm/mach-orion/pci.c
- *
- * PCI and PCIE functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-
-/*****************************************************************************
- * Orion has one PCIE controller and one PCI controller.
- *
- * Note1: The local PCIE bus number is '0'. The local PCI bus number
- * follows the scanned PCIE bridged busses, if any.
- *
- * Note2: It is possible for PCI/PCIE agents to access many subsystem's
- * space, by configuring BARs and Address Decode Windows, e.g. flashes on
- * device bus, Orion registers, etc. However this code only enable the
- * access to DDR banks.
- ****************************************************************************/
-
-
-/*****************************************************************************
- * PCIE controller
- ****************************************************************************/
-#define PCIE_CTRL               ORION_PCIE_REG(0x1a00)
-#define PCIE_STAT               ORION_PCIE_REG(0x1a04)
-#define PCIE_DEV_ID             ORION_PCIE_REG(0x0000)
-#define PCIE_CMD_STAT           ORION_PCIE_REG(0x0004)
-#define PCIE_DEV_REV            ORION_PCIE_REG(0x0008)
-#define PCIE_MASK               ORION_PCIE_REG(0x1910)
-#define PCIE_CONF_ADDR          ORION_PCIE_REG(0x18f8)
-#define PCIE_CONF_DATA          ORION_PCIE_REG(0x18fc)
-
-/*
- * PCIE_STAT bits
- */
-#define PCIE_STAT_LINK_DOWN             1
-#define PCIE_STAT_BUS_OFFS              8
-#define PCIE_STAT_BUS_MASK              (0xff << PCIE_STAT_BUS_OFFS)
-#define PCIE_STAT_DEV_OFFS              20
-#define PCIE_STAT_DEV_MASK              (0x1f << PCIE_STAT_DEV_OFFS)
-
-/*
- * PCIE_CONF_ADDR bits
- */
-#define PCIE_CONF_REG(r)                ((((r) & 0xf00) << 24) | ((r) & 0xfc))
-#define PCIE_CONF_FUNC(f)               (((f) & 0x3) << 8)
-#define PCIE_CONF_DEV(d)                (((d) & 0x1f) << 11)
-#define PCIE_CONF_BUS(b)                (((b) & 0xff) << 16)
-#define PCIE_CONF_ADDR_EN               (1 << 31)
-
-/*
- * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
- * and then reading the PCIE_CONF_DATA register. Need to make sure these
- * transactions are atomic.
- */
-static DEFINE_SPINLOCK(orion_pcie_lock);
-
-void orion_pcie_id(u32 *dev, u32 *rev)
-{
-        *dev = orion_read(PCIE_DEV_ID) >> 16;
-        *rev = orion_read(PCIE_DEV_REV) & 0xff;
-}
-
-u32 orion_pcie_local_bus_nr(void)
-{
-        u32 stat = orion_read(PCIE_STAT);
-        return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
-}
-
-static u32 orion_pcie_local_dev_nr(void)
-{
-        u32 stat = orion_read(PCIE_STAT);
-        return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
-}
-
-static u32 orion_pcie_no_link(void)
-{
-        u32 stat = orion_read(PCIE_STAT);
-        return(stat & PCIE_STAT_LINK_DOWN);
-}
-
-static void orion_pcie_set_bus_nr(int nr)
-{
-        orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
-        orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
-}
-
-static void orion_pcie_master_slave_enable(void)
-{
-        orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
-                                          PCI_COMMAND_IO |
-                                          PCI_COMMAND_MEMORY);
-}
-
-static void orion_pcie_enable_interrupts(void)
-{
-        /*
-         * Enable interrupts lines
-         * INTA[24] INTB[25] INTC[26] INTD[27]
-         */
-        orion_setbits(PCIE_MASK, 0xf<<24);
-}
-
-static int orion_pcie_valid_config(u32 bus, u32 dev)
-{
-        /*
-         * Don't go out when trying to access --
-         * 1. our own device
-         * 2. where there's no device connected (no link)
-         * 3. nonexisting devices on local bus
-         */
-
-        if ((orion_pcie_local_bus_nr() == bus) &&
-           (orion_pcie_local_dev_nr() == dev))
-                return 0;
-
-        if (orion_pcie_no_link())
-                return 0;
-
-        if (bus == orion_pcie_local_bus_nr())
-                if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
-                   ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
-                return 0;
-
-        return 1;
-}
-
-static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
-                                                int size, u32 *val)
-{
-        unsigned long flags;
-        unsigned int dev, rev, pcie_addr;
-
-        if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
-                *val = 0xffffffff;
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        }
-
-        spin_lock_irqsave(&orion_pcie_lock, flags);
-
-        orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
-                        PCIE_CONF_DEV(PCI_SLOT(devfn)) |
-                        PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
-                        PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
-
-        orion_pcie_id(&dev, &rev);
-        if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
-                /* extended register space */
-                pcie_addr = ORION_PCIE_WA_VIRT_BASE;
-                pcie_addr |= PCIE_CONF_BUS(bus->number) |
-                        PCIE_CONF_DEV(PCI_SLOT(devfn)) |
-                        PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
-                        PCIE_CONF_REG(where);
-                *val = orion_read(pcie_addr);
-        } else
-                *val = orion_read(PCIE_CONF_DATA);
-
-        if (size == 1)
-                *val = (*val >> (8*(where & 0x3))) & 0xff;
-        else if (size == 2)
-                *val = (*val >> (8*(where & 0x3))) & 0xffff;
-
-        spin_unlock_irqrestore(&orion_pcie_lock, flags);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
-                                                int size, u32 val)
-{
-        unsigned long flags;
-        int ret;
-
-        if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        spin_lock_irqsave(&orion_pcie_lock, flags);
-
-        ret = PCIBIOS_SUCCESSFUL;
-
-        orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
-                        PCIE_CONF_DEV(PCI_SLOT(devfn)) |
-                        PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
-                        PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
-
-        if (size == 4) {
-                __raw_writel(val, PCIE_CONF_DATA);
-        } else if (size == 2) {
-                __raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
-        } else if (size == 1) {
-                __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
-        } else {
-                ret = PCIBIOS_BAD_REGISTER_NUMBER;
-        }
-
-        spin_unlock_irqrestore(&orion_pcie_lock, flags);
-
-        return ret;
-}
-
-struct pci_ops orion_pcie_ops = {
-        .read = orion_pcie_rd_conf,
-        .write = orion_pcie_wr_conf,
-};
-
-
-static int orion_pcie_setup(struct pci_sys_data *sys)
-{
-        struct resource *res;
-
-        /*
-         * Master + Slave enable
-         */
-        orion_pcie_master_slave_enable();
-
-        /*
-         * Enable interrupts lines A-D
-         */
-        orion_pcie_enable_interrupts();
-
-        /*
-         * Request resource
-         */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-        if (!res)
-                panic("orion_pci_setup unable to alloc resources");
-
-        /*
-         * IORESOURCE_IO
-         */
-        res[0].name = "PCI-EX I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION_PCIE_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCIE IO resource failed\n");
-        sys->resource[0] = &res[0];
-
-        /*
-         * IORESOURCE_MEM
-         */
-        res[1].name = "PCI-EX Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = ORION_PCIE_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
-                panic("Request PCIE Memory resource failed\n");
-        sys->resource[1] = &res[1];
-
-        sys->resource[2] = NULL;
-        sys->io_offset = 0;
-
-        return 1;
-}
-
-/*****************************************************************************
- * PCI controller
- ****************************************************************************/
-#define PCI_MODE                ORION_PCI_REG(0xd00)
-#define PCI_CMD                 ORION_PCI_REG(0xc00)
-#define PCI_P2P_CONF            ORION_PCI_REG(0x1d14)
-#define PCI_CONF_ADDR           ORION_PCI_REG(0xc78)
-#define PCI_CONF_DATA           ORION_PCI_REG(0xc7c)
-
-/*
- * PCI_MODE bits
- */
-#define PCI_MODE_64BIT                  (1 << 2)
-#define PCI_MODE_PCIX                   ((1 << 4) | (1 << 5))
-
-/*
- * PCI_CMD bits
- */
-#define PCI_CMD_HOST_REORDER            (1 << 29)
-
-/*
- * PCI_P2P_CONF bits
- */
-#define PCI_P2P_BUS_OFFS                16
-#define PCI_P2P_BUS_MASK                (0xff << PCI_P2P_BUS_OFFS)
-#define PCI_P2P_DEV_OFFS                24
-#define PCI_P2P_DEV_MASK                (0x1f << PCI_P2P_DEV_OFFS)
-
-/*
- * PCI_CONF_ADDR bits
- */
-#define PCI_CONF_REG(reg)               ((reg) & 0xfc)
-#define PCI_CONF_FUNC(func)             (((func) & 0x3) << 8)
-#define PCI_CONF_DEV(dev)               (((dev) & 0x1f) << 11)
-#define PCI_CONF_BUS(bus)               (((bus) & 0xff) << 16)
-#define PCI_CONF_ADDR_EN                (1 << 31)
-
-/*
- * Internal configuration space
- */
-#define PCI_CONF_FUNC_STAT_CMD          0
-#define PCI_CONF_REG_STAT_CMD           4
-#define PCIX_STAT                       0x64
-#define PCIX_STAT_BUS_OFFS              8
-#define PCIX_STAT_BUS_MASK              (0xff << PCIX_STAT_BUS_OFFS)
-
-/*
- * PCI config cycles are done by programming the PCI_CONF_ADDR register
- * and then reading the PCI_CONF_DATA register. Need to make sure these
- * transactions are atomic.
- */
-static DEFINE_SPINLOCK(orion_pci_lock);
-
-u32 orion_pci_local_bus_nr(void)
-{
-        u32 conf = orion_read(PCI_P2P_CONF);
-        return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
-}
-
-u32 orion_pci_local_dev_nr(void)
-{
-        u32 conf = orion_read(PCI_P2P_CONF);
-        return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
-}
-
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
-                                        u32 where, u32 size, u32 *val)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&orion_pci_lock, flags);
-
-        orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
-
-        *val = orion_read(PCI_CONF_DATA);
-
-        if (size == 1)
-                *val = (*val >> (8*(where & 0x3))) & 0xff;
-        else if (size == 2)
-                *val = (*val >> (8*(where & 0x3))) & 0xffff;
-
-        spin_unlock_irqrestore(&orion_pci_lock, flags);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
-                                        u32 where, u32 size, u32 val)
-{
-        unsigned long flags;
-        int ret = PCIBIOS_SUCCESSFUL;
-
-        spin_lock_irqsave(&orion_pci_lock, flags);
-
-        orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
-
-        if (size == 4) {
-                __raw_writel(val, PCI_CONF_DATA);
-        } else if (size == 2) {
-                __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
-        } else if (size == 1) {
-                __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
-        } else {
-                ret = PCIBIOS_BAD_REGISTER_NUMBER;
-        }
-
-        spin_unlock_irqrestore(&orion_pci_lock, flags);
-
-        return ret;
-}
-
-static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
-                                int where, int size, u32 *val)
-{
-        /*
-         * Don't go out for local device
-         */
-        if ((orion_pci_local_bus_nr() == bus->number) &&
-           (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
-                *val = 0xffffffff;
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        }
-
-        return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
-                                        PCI_FUNC(devfn), where, size, val);
-}
-
-static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
-                                int where, int size, u32 val)
-{
-        /*
-         * Don't go out for local device
-         */
-        if ((orion_pci_local_bus_nr() == bus->number) &&
-           (orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
-                                        PCI_FUNC(devfn), where, size, val);
-}
-
-struct pci_ops orion_pci_ops = {
-        .read = orion_pci_rd_conf,
-        .write = orion_pci_wr_conf,
-};
-
-static void orion_pci_set_bus_nr(int nr)
-{
-        u32 p2p = orion_read(PCI_P2P_CONF);
-
-        if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
-                /*
-                 * PCI-X mode
-                 */
-                u32 pcix_status, bus, dev;
-                bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
-                dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
-                orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
-                pcix_status &= ~PCIX_STAT_BUS_MASK;
-                pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
-                orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
-        } else {
-                /*
-                 * PCI Conventional mode
-                 */
-                p2p &= ~PCI_P2P_BUS_MASK;
-                p2p |= (nr << PCI_P2P_BUS_OFFS);
-                orion_write(PCI_P2P_CONF, p2p);
-        }
-}
-
-static void orion_pci_master_slave_enable(void)
-{
-        u32 bus_nr, dev_nr, func, reg, val;
-
-        bus_nr = orion_pci_local_bus_nr();
-        dev_nr = orion_pci_local_dev_nr();
-        func = PCI_CONF_FUNC_STAT_CMD;
-        reg = PCI_CONF_REG_STAT_CMD;
-        orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
-        val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-        orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
-}
-
-static int orion_pci_setup(struct pci_sys_data *sys)
-{
-        struct resource *res;
-
-        /*
-         * Master + Slave enable
-         */
-        orion_pci_master_slave_enable();
-
-        /*
-         * Force ordering
-         */
-        orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
-
-        /*
-         * Request resources
-         */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-        if (!res)
-                panic("orion_pci_setup unable to alloc resources");
-
-        /*
-         * IORESOURCE_IO
-         */
-        res[0].name = "PCI I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION_PCI_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCI IO resource failed\n");
-        sys->resource[0] = &res[0];
-
-        /*
-         * IORESOURCE_MEM
-         */
-        res[1].name = "PCI Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = ORION_PCI_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
-                panic("Request PCI Memory resource failed\n");
-        sys->resource[1] = &res[1];
-
-        sys->resource[2] = NULL;
-        sys->io_offset = 0;
-
-        return 1;
-}
-
-
-/*****************************************************************************
- * General PCIE + PCI
- ****************************************************************************/
-int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
-{
-        int ret = 0;
-
-        if (nr == 0) {
-                /*
-                 * PCIE setup
-                 */
-                orion_pcie_set_bus_nr(0);
-                ret = orion_pcie_setup(sys);
-        } else if (nr == 1) {
-                /*
-                 * PCI setup
-                 */
-                ret = orion_pci_setup(sys);
-        }
-
-        return ret;
-}
-
-struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        struct pci_ops *ops;
-        struct pci_bus *bus;
-
-
-        if (nr == 0) {
-                u32 pci_bus;
-                /*
-                 * PCIE scan
-                 */
-                ops = &orion_pcie_ops;
-                bus = pci_scan_bus(sys->busnr, ops, sys);
-                /*
-                 * Set local PCI bus number to follow PCIE bridges (if any)
-                 */
-                pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
-                orion_pci_set_bus_nr(pci_bus);
-        } else if (nr == 1) {
-                /*
-                 * PCI scan
-                 */
-                ops = &orion_pci_ops;
-                bus = pci_scan_bus(sys->busnr, ops, sys);
-        } else {
-                BUG();
-                bus = NULL;
-        }
-
-        return bus;
-}
diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c
deleted file mode 100644
index bd4262da4f40..000000000000
--- a/arch/arm/mach-orion/time.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * arch/arm/mach-orion/time.c
- *
- * Core time functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/mach/time.h>
-#include <asm/arch/orion.h>
-#include "common.h"
-
-/*
- * Timer0: clock_event_device, Tick.
- * Timer1: clocksource, Free running.
- * WatchDog: Not used.
- *
- * Timers are counting down.
- */
-#define CLOCKEVENT      0
-#define CLOCKSOURCE     1
-
-/*
- * Timers bits
- */
-#define BRIDGE_INT_TIMER(x)     (1 << ((x) + 1))
-#define TIMER_EN(x)             (1 << ((x) * 2))
-#define TIMER_RELOAD_EN(x)      (1 << (((x) * 2) + 1))
-#define BRIDGE_INT_TIMER_WD     (1 << 3)
-#define TIMER_WD_EN             (1 << 4)
-#define TIMER_WD_RELOAD_EN      (1 << 5)
-
-static cycle_t orion_clksrc_read(void)
-{
-        return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
-}
-
-static struct clocksource orion_clksrc = {
-        .name           = "orion_clocksource",
-        .shift          = 20,
-        .rating         = 300,
-        .read           = orion_clksrc_read,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int
-orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
-{
-        unsigned long flags;
-
-        if (delta == 0)
-                return -ETIME;
-
-        local_irq_save(flags);
-
-        /*
-         * Clear and enable timer interrupt bit
-         */
-        orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
-        orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
-
-        /*
-         * Setup new timer value
-         */
-        orion_write(TIMER_VAL(CLOCKEVENT), delta);
-
-        /*
-         * Disable auto reload and kickoff the timer
-         */
-        orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
-        orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static void
-orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        if (mode == CLOCK_EVT_MODE_PERIODIC) {
-                /*
-                 * Setup latch cycles in timer and enable reload interrupt.
-                 */
-                orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
-                orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
-                orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
-                orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
-                                          TIMER_EN(CLOCKEVENT));
-        } else {
-                /*
-                 * Disable timer and interrupt
-                 */
-                orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
-                orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
-                orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
-                                          TIMER_EN(CLOCKEVENT));
-        }
-
-        local_irq_restore(flags);
-}
-
-static struct clock_event_device orion_clkevt = {
-        .name           = "orion_tick",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
-        .rating         = 300,
-        .cpumask        = CPU_MASK_CPU0,
-        .set_next_event = orion_clkevt_next_event,
-        .set_mode       = orion_clkevt_mode,
-};
-
-static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
-{
-        /*
-         * Clear cause bit and do event
-         */
-        orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
-        orion_clkevt.event_handler(&orion_clkevt);
-        return IRQ_HANDLED;
-}
-
-static struct irqaction orion_timer_irq = {
-        .name           = "orion_tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
-        .handler        = orion_timer_interrupt
-};
-
-static void orion_timer_init(void)
-{
-        /*
-         * Setup clocksource free running timer (no interrupt on reload)
-         */
-        orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
-        orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
-        orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
-        orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
-                                  TIMER_EN(CLOCKSOURCE));
-
-        /*
-         * Register clocksource
-         */
-        orion_clksrc.mult =
-                clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
-
-        clocksource_register(&orion_clksrc);
-
-        /*
-         * Connect and enable tick handler
-         */
-        setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
-
-        /*
-         * Register clockevent
-         */
-        orion_clkevt.mult =
-                div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
-        orion_clkevt.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &orion_clkevt);
-        orion_clkevt.min_delta_ns =
-                clockevent_delta2ns(1, &orion_clkevt);
-
-        clockevents_register_device(&orion_clkevt);
-}
-
-struct sys_timer orion_timer = {
-        .init = orion_timer_init,
-};
diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 1dcbb6ac5a30..93debf336155 100644
--- a/arch/arm/mach-orion/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -1,4 +1,4 @@
-if ARCH_ORION
+if ARCH_ORION5X
 
 menu "Orion Implementations"
 
@@ -36,6 +36,14 @@ config MACH_TS209
           Say 'Y' here if you want your kernel to support the
           QNAP TS-109/TS-209 platform.
 
+config MACH_LINKSTATION_PRO
+        bool "Buffalo Linkstation Pro/Live"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation Pro/Live platform. Both v1 and
+          v2 devices are supported.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion5x/Makefile
index f91d937a73e8..9301bf55910b 100644
--- a/arch/arm/mach-orion/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,6 +1,7 @@
-obj-y                           += common.o addr-map.o pci.o gpio.o irq.o time.o
+obj-y                           += common.o addr-map.o pci.o gpio.o irq.o
 obj-$(CONFIG_MACH_DB88F5281)    += db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)    += rd88f5182-setup.o
 obj-$(CONFIG_MACH_KUROBOX_PRO)  += kurobox_pro-setup.o
+obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
 obj-$(CONFIG_MACH_DNS323)       += dns323-setup.o
 obj-$(CONFIG_MACH_TS209)        += ts209-setup.o
diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot
index 67039c3e0c48..67039c3e0c48 100644
--- a/arch/arm/mach-orion/Makefile.boot
+++ b/arch/arm/mach-orion5x/Makefile.boot
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
new file mode 100644
index 000000000000..6b179371e0a2
--- /dev/null
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -0,0 +1,240 @@
+/*
+ * arch/arm/mach-orion5x/addr-map.c
+ *
+ * Address map functions for Marvell Orion 5x SoCs
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * The Orion has fully programable address map. There's a separate address
+ * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
+ * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
+ * address decode windows that allow it to access any of the Orion resources.
+ *
+ * CPU address decoding --
+ * Linux assumes that it is the boot loader that already setup the access to
+ * DDR and internal registers.
+ * Setup access to PCI and PCI-E IO/MEM space is issued by this file.
+ * Setup access to various devices located on the device bus interface (e.g.
+ * flashes, RTC, etc) should be issued by machine-setup.c according to
+ * specific board population (by using orion5x_setup_*_win()).
+ *
+ * Non-CPU Masters address decoding --
+ * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
+ * banks only (the typical use case).
+ * Setup access for each master to DDR is issued by common.c.
+ *
+ * Note: although orion_setbits() and orion_clrbits() are not atomic
+ * no locking is necessary here since code in this file is only called
+ * at boot time when there is no concurrency issues.
+ */
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCI              3
+#define TARGET_PCIE             4
+#define ATTR_DDR_CS(n)          (((n) ==0) ? 0xe :      \
+                                ((n) == 1) ? 0xd :      \
+                                ((n) == 2) ? 0xb :      \
+                                ((n) == 3) ? 0x7 : 0xf)
+#define ATTR_PCIE_MEM           0x59
+#define ATTR_PCIE_IO            0x51
+#define ATTR_PCIE_WA            0x79
+#define ATTR_PCI_MEM            0x59
+#define ATTR_PCI_IO             0x51
+#define ATTR_DEV_CS0            0x1e
+#define ATTR_DEV_CS1            0x1d
+#define ATTR_DEV_CS2            0x1b
+#define ATTR_DEV_BOOT           0xf
+#define WIN_EN                  1
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS(n)          ORION5X_DDR_REG(0x1500 + ((n) * 8))
+#define DDR_SIZE_CS(n)          ORION5X_DDR_REG(0x1504 + ((n) * 8))
+#define DDR_MAX_CS              4
+#define DDR_REG_TO_SIZE(reg)    (((reg) | 0xffffff) + 1)
+#define DDR_REG_TO_BASE(reg)    ((reg) & 0xff000000)
+#define DDR_BANK_EN             1
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define CPU_WIN_CTRL(n)         ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
+#define CPU_WIN_BASE(n)         ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
+#define CPU_WIN_REMAP_LO(n)     ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
+#define CPU_WIN_REMAP_HI(n)     ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
+
+/*
+ * Gigabit Ethernet Address Decode Windows registers
+ */
+#define ETH_WIN_BASE(win)       ORION5X_ETH_REG(0x200 + ((win) * 8))
+#define ETH_WIN_SIZE(win)       ORION5X_ETH_REG(0x204 + ((win) * 8))
+#define ETH_WIN_REMAP(win)      ORION5X_ETH_REG(0x280 + ((win) * 4))
+#define ETH_WIN_EN              ORION5X_ETH_REG(0x290)
+#define ETH_WIN_PROT            ORION5X_ETH_REG(0x294)
+#define ETH_MAX_WIN             6
+#define ETH_MAX_REMAP_WIN       4
+
+
+struct mbus_dram_target_info orion5x_mbus_dram_info;
+
+static int __init orion5x_cpu_win_can_remap(int win)
+{
+        u32 dev, rev;
+
+        orion5x_pcie_id(&dev, &rev);
+        if ((dev == MV88F5281_DEV_ID && win < 4)
+            || (dev == MV88F5182_DEV_ID && win < 2)
+            || (dev == MV88F5181_DEV_ID && win < 2))
+                return 1;
+
+        return 0;
+}
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
+        orion5x_write(CPU_WIN_CTRL(win),
+                ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
+
+        if (orion5x_cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+
+                orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
+                orion5x_write(CPU_WIN_REMAP_HI(win), 0);
+        }
+}
+
+void __init orion5x_setup_cpu_mbus_bridge(void)
+{
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                orion5x_write(CPU_WIN_BASE(i), 0);
+                orion5x_write(CPU_WIN_CTRL(i), 0);
+                if (orion5x_cpu_win_can_remap(i)) {
+                        orion5x_write(CPU_WIN_REMAP_LO(i), 0);
+                        orion5x_write(CPU_WIN_REMAP_HI(i), 0);
+                }
+        }
+
+        /*
+         * Setup windows for PCI+PCIe IO+MEM space.
+         */
+        setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
+                TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
+        setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
+                TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
+        setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
+                TARGET_PCIE, ATTR_PCIE_MEM, -1);
+        setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
+                TARGET_PCI, ATTR_PCI_MEM, -1);
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(DDR_BASE_CS(i));
+                u32 size = readl(DDR_SIZE_CS(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &orion5x_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xff000000;
+                        w->size = (size | 0x00ffffff) + 1;
+                }
+        }
+        orion5x_mbus_dram_info.num_cs = cs;
+}
+
+void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
+{
+        setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+}
+
+void __init orion5x_setup_dev0_win(u32 base, u32 size)
+{
+        setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+}
+
+void __init orion5x_setup_dev1_win(u32 base, u32 size)
+{
+        setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+}
+
+void __init orion5x_setup_dev2_win(u32 base, u32 size)
+{
+        setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+}
+
+void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
+{
+        setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
+}
+
+void __init orion5x_setup_eth_wins(void)
+{
+        int i;
+
+        /*
+         * First, disable and clear windows
+         */
+        for (i = 0; i < ETH_MAX_WIN; i++) {
+                orion5x_write(ETH_WIN_BASE(i), 0);
+                orion5x_write(ETH_WIN_SIZE(i), 0);
+                orion5x_setbits(ETH_WIN_EN, 1 << i);
+                orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
+                if (i < ETH_MAX_REMAP_WIN)
+                        orion5x_write(ETH_WIN_REMAP(i), 0);
+        }
+
+        /*
+         * Setup windows for DDR banks.
+         */
+        for (i = 0; i < DDR_MAX_CS; i++) {
+                u32 base, size;
+                size = orion5x_read(DDR_SIZE_CS(i));
+                base = orion5x_read(DDR_BASE_CS(i));
+                if (size & DDR_BANK_EN) {
+                        base = DDR_REG_TO_BASE(base);
+                        size = DDR_REG_TO_SIZE(size);
+                        orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
+                        orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
+                                        (ATTR_DDR_CS(i) << 8) |
+                                        TARGET_DDR);
+                        orion5x_clrbits(ETH_WIN_EN, 1 << i);
+                        orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
+                }
+        }
+}
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion5x/common.c
index bbc2b4ec932c..439c7784af02 100644
--- a/arch/arm/mach-orion/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/common.c
+ * arch/arm/mach-orion5x/common.c
  *
- * Core functions for Marvell Orion System On Chip
+ * Core functions for Marvell Orion 5x SoCs
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -14,64 +14,71 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/mbus.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/ata_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/time.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/ehci-orion.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
 #include "common.h"
 
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
-static struct map_desc orion_io_desc[] __initdata = {
+static struct map_desc orion5x_io_desc[] __initdata = {
         {
-                .virtual        = ORION_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_REGS_PHYS_BASE),
-                .length         = ORION_REGS_SIZE,
+                .virtual        = ORION5X_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
+                .length         = ORION5X_REGS_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = ORION_PCIE_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
-                .length         = ORION_PCIE_IO_SIZE,
+                .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
+                .length         = ORION5X_PCIE_IO_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = ORION_PCI_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
-                .length         = ORION_PCI_IO_SIZE,
+                .virtual        = ORION5X_PCI_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
+                .length         = ORION5X_PCI_IO_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = ORION_PCIE_WA_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
-                .length         = ORION_PCIE_WA_SIZE,
+                .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
+                .length         = ORION5X_PCIE_WA_SIZE,
                 .type           = MT_DEVICE
         },
 };
 
-void __init orion_map_io(void)
+void __init orion5x_map_io(void)
 {
-        iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
+        iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
 }
 
 /*****************************************************************************
  * UART
  ****************************************************************************/
 
-static struct resource orion_uart_resources[] = {
+static struct resource orion5x_uart_resources[] = {
         {
                 .start          = UART0_PHYS_BASE,
                 .end            = UART0_PHYS_BASE + 0xff,
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_ORION_UART0,
-                .end            = IRQ_ORION_UART0,
+                .start          = IRQ_ORION5X_UART0,
+                .end            = IRQ_ORION5X_UART0,
                 .flags          = IORESOURCE_IRQ,
         },
         {
@@ -80,96 +87,102 @@ static struct resource orion_uart_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_ORION_UART1,
-                .end            = IRQ_ORION_UART1,
+                .start          = IRQ_ORION5X_UART1,
+                .end            = IRQ_ORION5X_UART1,
                 .flags          = IORESOURCE_IRQ,
         },
 };
 
-static struct plat_serial8250_port orion_uart_data[] = {
+static struct plat_serial8250_port orion5x_uart_data[] = {
         {
                 .mapbase        = UART0_PHYS_BASE,
                 .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_ORION_UART0,
+                .irq            = IRQ_ORION5X_UART0,
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = ORION_TCLK,
+                .uartclk        = ORION5X_TCLK,
         },
         {
                 .mapbase        = UART1_PHYS_BASE,
                 .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_ORION_UART1,
+                .irq            = IRQ_ORION5X_UART1,
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = ORION_TCLK,
+                .uartclk        = ORION5X_TCLK,
         },
         { },
 };
 
-static struct platform_device orion_uart = {
+static struct platform_device orion5x_uart = {
         .name                   = "serial8250",
         .id                     = PLAT8250_DEV_PLATFORM,
         .dev                    = {
-                .platform_data  = orion_uart_data,
+                .platform_data  = orion5x_uart_data,
         },
-        .resource               = orion_uart_resources,
-        .num_resources          = ARRAY_SIZE(orion_uart_resources),
+        .resource               = orion5x_uart_resources,
+        .num_resources          = ARRAY_SIZE(orion5x_uart_resources),
 };
 
 /*******************************************************************************
  * USB Controller - 2 interfaces
  ******************************************************************************/
 
-static struct resource orion_ehci0_resources[] = {
+static struct resource orion5x_ehci0_resources[] = {
         {
-                .start  = ORION_USB0_PHYS_BASE,
-                .end    = ORION_USB0_PHYS_BASE + SZ_4K,
+                .start  = ORION5X_USB0_PHYS_BASE,
+                .end    = ORION5X_USB0_PHYS_BASE + SZ_4K,
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_ORION_USB0_CTRL,
-                .end    = IRQ_ORION_USB0_CTRL,
+                .start  = IRQ_ORION5X_USB0_CTRL,
+                .end    = IRQ_ORION5X_USB0_CTRL,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct resource orion_ehci1_resources[] = {
+static struct resource orion5x_ehci1_resources[] = {
         {
-                .start  = ORION_USB1_PHYS_BASE,
-                .end    = ORION_USB1_PHYS_BASE + SZ_4K,
+                .start  = ORION5X_USB1_PHYS_BASE,
+                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K,
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_ORION_USB1_CTRL,
-                .end    = IRQ_ORION_USB1_CTRL,
+                .start  = IRQ_ORION5X_USB1_CTRL,
+                .end    = IRQ_ORION5X_USB1_CTRL,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
+static struct orion_ehci_data orion5x_ehci_data = {
+        .dram           = &orion5x_mbus_dram_info,
+};
+
 static u64 ehci_dmamask = 0xffffffffUL;
 
-static struct platform_device orion_ehci0 = {
+static struct platform_device orion5x_ehci0 = {
         .name           = "orion-ehci",
         .id             = 0,
         .dev            = {
                 .dma_mask               = &ehci_dmamask,
                 .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &orion5x_ehci_data,
         },
-        .resource       = orion_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(orion_ehci0_resources),
+        .resource       = orion5x_ehci0_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_ehci0_resources),
 };
 
-static struct platform_device orion_ehci1 = {
+static struct platform_device orion5x_ehci1 = {
         .name           = "orion-ehci",
         .id             = 1,
         .dev            = {
                 .dma_mask               = &ehci_dmamask,
                 .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &orion5x_ehci_data,
         },
-        .resource       = orion_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(orion_ehci1_resources),
+        .resource       = orion5x_ehci1_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_ehci1_resources),
 };
 
 /*****************************************************************************
@@ -177,42 +190,42 @@ static struct platform_device orion_ehci1 = {
  * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
  ****************************************************************************/
 
-static struct resource orion_eth_shared_resources[] = {
+static struct resource orion5x_eth_shared_resources[] = {
         {
-                .start  = ORION_ETH_PHYS_BASE + 0x2000,
-                .end    = ORION_ETH_PHYS_BASE + 0x3fff,
+                .start  = ORION5X_ETH_PHYS_BASE + 0x2000,
+                .end    = ORION5X_ETH_PHYS_BASE + 0x3fff,
                 .flags  = IORESOURCE_MEM,
         },
 };
 
-static struct platform_device orion_eth_shared = {
+static struct platform_device orion5x_eth_shared = {
         .name           = MV643XX_ETH_SHARED_NAME,
         .id             = 0,
         .num_resources  = 1,
-        .resource       = orion_eth_shared_resources,
+        .resource       = orion5x_eth_shared_resources,
 };
 
-static struct resource orion_eth_resources[] = {
+static struct resource orion5x_eth_resources[] = {
         {
                 .name   = "eth irq",
-                .start  = IRQ_ORION_ETH_SUM,
-                .end    = IRQ_ORION_ETH_SUM,
+                .start  = IRQ_ORION5X_ETH_SUM,
+                .end    = IRQ_ORION5X_ETH_SUM,
                 .flags  = IORESOURCE_IRQ,
         }
 };
 
-static struct platform_device orion_eth = {
+static struct platform_device orion5x_eth = {
         .name           = MV643XX_ETH_NAME,
         .id             = 0,
         .num_resources  = 1,
-        .resource       = orion_eth_resources,
+        .resource       = orion5x_eth_resources,
 };
 
-void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
+void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_eth.dev.platform_data = eth_data;
-        platform_device_register(&orion_eth_shared);
-        platform_device_register(&orion_eth);
+        orion5x_eth.dev.platform_data = eth_data;
+        platform_device_register(&orion5x_eth_shared);
+        platform_device_register(&orion5x_eth);
 }
 
 /*****************************************************************************
@@ -220,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
  * (The Orion and Discovery (MV643xx) families share the same I2C controller)
  ****************************************************************************/
 
-static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
+static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
         .freq_m         = 8, /* assumes 166 MHz TCLK */
         .freq_n         = 3,
         .timeout        = 1000, /* Default timeout of 1 second */
 };
 
-static struct resource orion_i2c_resources[] = {
+static struct resource orion5x_i2c_resources[] = {
         {
                 .name   = "i2c base",
                 .start  = I2C_PHYS_BASE,
@@ -235,66 +248,80 @@ static struct resource orion_i2c_resources[] = {
         },
         {
                 .name   = "i2c irq",
-                .start  = IRQ_ORION_I2C,
-                .end    = IRQ_ORION_I2C,
+                .start  = IRQ_ORION5X_I2C,
+                .end    = IRQ_ORION5X_I2C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device orion_i2c = {
+static struct platform_device orion5x_i2c = {
         .name           = MV64XXX_I2C_CTLR_NAME,
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(orion_i2c_resources),
-        .resource       = orion_i2c_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_i2c_resources),
+        .resource       = orion5x_i2c_resources,
         .dev            = {
-                .platform_data = &orion_i2c_pdata,
+                .platform_data = &orion5x_i2c_pdata,
         },
 };
 
 /*****************************************************************************
  * Sata port
  ****************************************************************************/
-static struct resource orion_sata_resources[] = {
+static struct resource orion5x_sata_resources[] = {
         {
                 .name   = "sata base",
-                .start  = ORION_SATA_PHYS_BASE,
-                .end    = ORION_SATA_PHYS_BASE + 0x5000 - 1,
+                .start  = ORION5X_SATA_PHYS_BASE,
+                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
                 .name   = "sata irq",
-                .start  = IRQ_ORION_SATA,
-                .end    = IRQ_ORION_SATA,
+                .start  = IRQ_ORION5X_SATA,
+                .end    = IRQ_ORION5X_SATA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device orion_sata = {
+static struct platform_device orion5x_sata = {
         .name           = "sata_mv",
         .id             = 0,
         .dev            = {
                 .coherent_dma_mask      = 0xffffffff,
         },
-        .num_resources  = ARRAY_SIZE(orion_sata_resources),
-        .resource       = orion_sata_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
+        .resource       = orion5x_sata_resources,
 };
 
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
+void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata.dev.platform_data = sata_data;
-        platform_device_register(&orion_sata);
+        sata_data->dram = &orion5x_mbus_dram_info;
+        orion5x_sata.dev.platform_data = sata_data;
+        platform_device_register(&orion5x_sata);
 }
 
 /*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+
+static void orion5x_timer_init(void)
+{
+        orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
+}
+
+struct sys_timer orion5x_timer = {
+        .init = orion5x_timer_init,
+};
+
+/*****************************************************************************
  * General
  ****************************************************************************/
 
 /*
  * Identify device ID and rev from PCIE configuration header space '0'.
  */
-static void orion_id(u32 *dev, u32 *rev, char **dev_name)
+static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 {
-        orion_pcie_id(dev, rev);
+        orion5x_pcie_id(dev, rev);
 
         if (*dev == MV88F5281_DEV_ID) {
                 if (*rev == MV88F5281_REV_D2) {
@@ -321,33 +348,28 @@ static void orion_id(u32 *dev, u32 *rev, char **dev_name)
         }
 }
 
-void __init orion_init(void)
+void __init orion5x_init(void)
 {
         char *dev_name;
         u32 dev, rev;
 
-        orion_id(&dev, &rev, &dev_name);
-        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
+        orion5x_id(&dev, &rev, &dev_name);
+        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
 
         /*
          * Setup Orion address map
          */
-        orion_setup_cpu_wins();
-        orion_setup_usb_wins();
-        orion_setup_eth_wins();
-        orion_setup_pci_wins();
-        orion_setup_pcie_wins();
-        if (dev == MV88F5182_DEV_ID)
-                orion_setup_sata_wins();
+        orion5x_setup_cpu_mbus_bridge();
+        orion5x_setup_eth_wins();
 
         /*
-         * REgister devices
+         * Register devices.
          */
-        platform_device_register(&orion_uart);
-        platform_device_register(&orion_ehci0);
+        platform_device_register(&orion5x_uart);
+        platform_device_register(&orion5x_ehci0);
         if (dev == MV88F5182_DEV_ID)
-                platform_device_register(&orion_ehci1);
-        platform_device_register(&orion_i2c);
+                platform_device_register(&orion5x_ehci1);
+        platform_device_register(&orion5x_i2c);
 }
 
 /*
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
new file mode 100644
index 000000000000..f4c4c9a72a7c
--- /dev/null
+++ b/arch/arm/mach-orion5x/common.h
@@ -0,0 +1,72 @@
+#ifndef __ARCH_ORION5X_COMMON_H
+#define __ARCH_ORION5X_COMMON_H
+
+/*
+ * Basic Orion init functions used early by machine-setup.
+ */
+
+void orion5x_map_io(void);
+void orion5x_init_irq(void);
+void orion5x_init(void);
+extern struct sys_timer orion5x_timer;
+
+/*
+ * Enumerations and functions for Orion windows mapping. Used by Orion core
+ * functions to map its interfaces and by the machine-setup to map its on-
+ * board devices. Details in /mach-orion/addr-map.c
+ */
+extern struct mbus_dram_target_info orion5x_mbus_dram_info;
+void orion5x_setup_cpu_mbus_bridge(void);
+void orion5x_setup_dev_boot_win(u32 base, u32 size);
+void orion5x_setup_dev0_win(u32 base, u32 size);
+void orion5x_setup_dev1_win(u32 base, u32 size);
+void orion5x_setup_dev2_win(u32 base, u32 size);
+void orion5x_setup_pcie_wa_win(u32 base, u32 size);
+void orion5x_setup_eth_wins(void);
+
+/*
+ * Shared code used internally by other Orion core functions.
+ * (/mach-orion/pci.c)
+ */
+
+struct pci_sys_data;
+struct pci_bus;
+
+void orion5x_pcie_id(u32 *dev, u32 *rev);
+int orion5x_pcie_local_bus_nr(void);
+int orion5x_pci_local_bus_nr(void);
+int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
+struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
+
+/*
+ * Valid GPIO pins according to MPP setup, used by machine-setup.
+ * (/mach-orion/gpio.c).
+ */
+
+void orion5x_gpio_set_valid_pins(u32 pins);
+void gpio_display(void);        /* debug */
+
+/*
+ * Pull in Orion Ethernet platform_data, used by machine-setup
+ */
+
+struct mv643xx_eth_platform_data;
+
+void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
+
+/*
+ * Orion Sata platform_data, used by machine-setup
+ */
+
+struct mv_sata_platform_data;
+
+void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
+
+struct machine_desc;
+struct meminfo;
+struct tag;
+extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
+                                   char **, struct meminfo *);
+
+
+#endif
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 5ef44e1a2d36..872aed372327 100644
--- a/arch/arm/mach-orion/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/db88f5281-setup.c
+ * arch/arm/mach-orion5x/db88f5281-setup.c
  *
  * Marvell Orion-2 Development Board Setup
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -24,8 +24,8 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/orion_nand.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCIE IRQ is connected internally (not GPIO)
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         /*
          * PCI IRQs are connected via GPIOs
@@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = {
         .nr_controllers = 2,
         .preinit        = db88f5281_pci_preinit,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = db88f5281_pci_map_irq,
 };
 
@@ -312,19 +312,16 @@ static void __init db88f5281_init(void)
         /*
          * Basic Orion setup. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup the CPU address decode windows for our on-board devices
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
-                                DB88F5281_NOR_BOOT_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
-                                DB88F5281_7SEG_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
-                                DB88F5281_NOR_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
-                                DB88F5281_NAND_SIZE, -1);
+        orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
+                                DB88F5281_NOR_BOOT_SIZE);
+        orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
+        orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+        orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
 
         /*
          * Setup Multiplexing Pins:
@@ -340,25 +337,25 @@ static void __init db88f5281_init(void)
          * MPP18: UART1_CTS                     MPP19: UART1_RTS
          * MPP-DEV: DEV_D[16:31]
          */
-        orion_write(MPP_0_7_CTRL, 0x00222203);
-        orion_write(MPP_8_15_CTRL, 0x44000000);
-        orion_write(MPP_16_19_CTRL, 0);
-        orion_write(MPP_DEV_CTRL, 0);
+        orion5x_write(MPP_0_7_CTRL, 0x00222203);
+        orion5x_write(MPP_8_15_CTRL, 0x44000000);
+        orion5x_write(MPP_16_19_CTRL, 0);
+        orion5x_write(MPP_DEV_CTRL, 0);
 
-        orion_gpio_set_valid_pins(0x00003fc3);
+        orion5x_gpio_set_valid_pins(0x00003fc3);
 
         platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
-        orion_eth_init(&db88f5281_eth_data);
+        orion5x_eth_init(&db88f5281_eth_data);
 }
 
 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
         /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = db88f5281_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 076e155ad510..d67790ef236e 100644
--- a/arch/arm/mach-orion/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-orion/dns323-setup.c
+ * arch/arm/mach-orion5x/dns323-setup.c
  *
  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
  *
@@ -25,8 +25,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 #define DNS323_GPIO_LED_RIGHT_AMBER     1
@@ -45,8 +44,8 @@
 static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
         /* PCI-E */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         pr_err("%s: requested mapping for unknown bus\n", __func__);
 
@@ -56,8 +55,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci dns323_pci __initdata = {
         .nr_controllers = 1,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = dns323_pci_map_irq,
 };
 
@@ -247,27 +246,25 @@ static void dns323_power_off(void)
 static void __init dns323_init(void)
 {
         /* Setup basic Orion functions. Need to be called early. */
-        orion_init();
+        orion5x_init();
 
         /* setup flash mapping
          * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
-                            DNS323_NOR_BOOT_SIZE, -1);
+        orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
 
         /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
          *
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070,
-                    (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
-        orion_write(MPP_0_7_CTRL, 0);
-        orion_write(MPP_8_15_CTRL, 0);
-        orion_write(MPP_16_19_CTRL, 0);
-        orion_write(MPP_DEV_CTRL, 0);
+        orion5x_write(MPP_0_7_CTRL, 0);
+        orion5x_write(MPP_8_15_CTRL, 0);
+        orion5x_write(MPP_16_19_CTRL, 0);
+        orion5x_write(MPP_DEV_CTRL, 0);
 
         /* Define used GPIO pins
 
@@ -290,7 +287,7 @@ static void __init dns323_init(void)
           | 14 | Out | //unknown//
           | 15 | Out | //unknown//
         */
-        orion_gpio_set_valid_pins(0x07f6);
+        orion5x_gpio_set_valid_pins(0x07f6);
 
         /* register dns323 specific power-off method */
         if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
@@ -306,18 +303,18 @@ static void __init dns323_init(void)
         i2c_register_board_info(0, dns323_i2c_devices,
                                 ARRAY_SIZE(dns323_i2c_devices));
 
-        orion_eth_init(&dns323_eth_data);
+        orion5x_eth_init(&dns323_eth_data);
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
 MACHINE_START(DNS323, "D-Link DNS-323")
         /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = dns323_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
 MACHINE_END
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion5x/gpio.c
index f713818c66a3..8108c316c426 100644
--- a/arch/arm/mach-orion/gpio.c
+++ b/arch/arm/mach-orion5x/gpio.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/gpio.c
+ * arch/arm/mach-orion5x/gpio.c
  *
  * GPIO functions for Marvell Orion System On Chip
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -16,14 +16,15 @@
 #include <linux/spinlock.h>
 #include <linux/bitops.h>
 #include <asm/gpio.h>
-#include <asm/arch/orion.h>
+#include <asm/io.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 static DEFINE_SPINLOCK(gpio_lock);
 static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
 static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
 
-void __init orion_gpio_set_valid_pins(u32 pins)
+void __init orion5x_gpio_set_valid_pins(u32 pins)
 {
         gpio_valid[0] = pins;
 }
@@ -49,7 +50,7 @@ int gpio_direction_input(unsigned pin)
         if (!gpio_label[pin])
                 gpio_label[pin] = "?";
 
-        orion_setbits(GPIO_IO_CONF, 1 << pin);
+        orion5x_setbits(GPIO_IO_CONF, 1 << pin);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -76,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value)
                 gpio_label[pin] = "?";
 
         mask = 1 << pin;
-        orion_clrbits(GPIO_BLINK_EN, mask);
+        orion5x_clrbits(GPIO_BLINK_EN, mask);
         if (value)
-                orion_setbits(GPIO_OUT, mask);
+                orion5x_setbits(GPIO_OUT, mask);
         else
-                orion_clrbits(GPIO_OUT, mask);
-        orion_clrbits(GPIO_IO_CONF, mask);
+                orion5x_clrbits(GPIO_OUT, mask);
+        orion5x_clrbits(GPIO_IO_CONF, mask);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -92,10 +93,10 @@ int gpio_get_value(unsigned pin)
 {
         int val, mask = 1 << pin;
 
-        if (orion_read(GPIO_IO_CONF) & mask)
-                val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
+        if (orion5x_read(GPIO_IO_CONF) & mask)
+                val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL);
         else
-                val = orion_read(GPIO_OUT);
+                val = orion5x_read(GPIO_OUT);
 
         return val & mask;
 }
@@ -108,32 +109,32 @@ void gpio_set_value(unsigned pin, int value)
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        orion_clrbits(GPIO_BLINK_EN, mask);
+        orion5x_clrbits(GPIO_BLINK_EN, mask);
         if (value)
-                orion_setbits(GPIO_OUT, mask);
+                orion5x_setbits(GPIO_OUT, mask);
         else
-                orion_clrbits(GPIO_OUT, mask);
+                orion5x_clrbits(GPIO_OUT, mask);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
 }
 EXPORT_SYMBOL(gpio_set_value);
 
-void orion_gpio_set_blink(unsigned pin, int blink)
+void orion5x_gpio_set_blink(unsigned pin, int blink)
 {
         unsigned long flags;
         int mask = 1 << pin;
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        orion_clrbits(GPIO_OUT, mask);
+        orion5x_clrbits(GPIO_OUT, mask);
         if (blink)
-                orion_setbits(GPIO_BLINK_EN, mask);
+                orion5x_setbits(GPIO_BLINK_EN, mask);
         else
-                orion_clrbits(GPIO_BLINK_EN, mask);
+                orion5x_clrbits(GPIO_BLINK_EN, mask);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
 }
-EXPORT_SYMBOL(orion_gpio_set_blink);
+EXPORT_SYMBOL(orion5x_gpio_set_blink);
 
 int gpio_request(unsigned pin, const char *label)
 {
@@ -187,39 +188,39 @@ void gpio_display(void)
                         printk("GPIO, free\n");
                 } else {
                         printk("GPIO, used by %s, ", gpio_label[i]);
-                        if (orion_read(GPIO_IO_CONF) & (1 << i)) {
+                        if (orion5x_read(GPIO_IO_CONF) & (1 << i)) {
                                 printk("input, active %s, level %s, edge %s\n",
-                                ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
-                                ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
-                                ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
+                                ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
+                                ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
+                                ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
                         } else {
-                                printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1);
+                                printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1);
                         }
                 }
         }
 
         printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL));
+                                MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL));
         printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL));
+                                MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL));
         printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL));
+                                MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL));
         printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL));
+                                MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL));
         printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
-                                GPIO_OUT, orion_read(GPIO_OUT));
+                                GPIO_OUT, orion5x_read(GPIO_OUT));
         printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
-                                GPIO_IO_CONF, orion_read(GPIO_IO_CONF));
+                                GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF));
         printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
-                                GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN));
+                                GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN));
         printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
-                                GPIO_IN_POL, orion_read(GPIO_IN_POL));
+                                GPIO_IN_POL, orion5x_read(GPIO_IN_POL));
         printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
-                                GPIO_DATA_IN, orion_read(GPIO_DATA_IN));
+                                GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN));
         printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK));
+                                GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK));
         printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE));
+                                GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE));
         printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK));
+                                GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK));
 }
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion5x/irq.c
index df7e12ad378b..dd21f38c5d37 100644
--- a/arch/arm/mach-orion/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/irq.c
+ * arch/arm/mach-orion5x/irq.c
  *
  * Core IRQ functions for Marvell Orion System On Chip
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
  * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -14,7 +14,9 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/gpio.h>
-#include <asm/arch/orion.h>
+#include <asm/io.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/irq.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -42,46 +44,46 @@
  *        polarity    LEVEL          mask
  *
  ****************************************************************************/
-static void orion_gpio_irq_ack(u32 irq)
+static void orion5x_gpio_irq_ack(u32 irq)
 {
         int pin = irq_to_gpio(irq);
         if (irq_desc[irq].status & IRQ_LEVEL)
                 /*
                  * Mask bit for level interrupt
                  */
-                orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+                orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
         else
                 /*
                  * Clear casue bit for egde interrupt
                  */
-                orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
+                orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
 }
 
-static void orion_gpio_irq_mask(u32 irq)
+static void orion5x_gpio_irq_mask(u32 irq)
 {
         int pin = irq_to_gpio(irq);
         if (irq_desc[irq].status & IRQ_LEVEL)
-                orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+                orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
         else
-                orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
+                orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
 }
 
-static void orion_gpio_irq_unmask(u32 irq)
+static void orion5x_gpio_irq_unmask(u32 irq)
 {
         int pin = irq_to_gpio(irq);
         if (irq_desc[irq].status & IRQ_LEVEL)
-                orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
+                orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
         else
-                orion_setbits(GPIO_EDGE_MASK, 1 << pin);
+                orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
 }
 
-static int orion_gpio_set_irq_type(u32 irq, u32 type)
+static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
 {
         int pin = irq_to_gpio(irq);
         struct irq_desc *desc;
 
-        if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
-                printk(KERN_ERR "orion_gpio_set_irq_type failed "
+        if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
+                printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
                                 "(irq %d, pin %d).\n", irq, pin);
                 return -EINVAL;
         }
@@ -92,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
         case IRQT_HIGH:
                 desc->handle_irq = handle_level_irq;
                 desc->status |= IRQ_LEVEL;
-                orion_clrbits(GPIO_IN_POL, (1 << pin));
+                orion5x_clrbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_LOW:
                 desc->handle_irq = handle_level_irq;
                 desc->status |= IRQ_LEVEL;
-                orion_setbits(GPIO_IN_POL, (1 << pin));
+                orion5x_setbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_RISING:
                 desc->handle_irq = handle_edge_irq;
                 desc->status &= ~IRQ_LEVEL;
-                orion_clrbits(GPIO_IN_POL, (1 << pin));
+                orion5x_clrbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_FALLING:
                 desc->handle_irq = handle_edge_irq;
                 desc->status &= ~IRQ_LEVEL;
-                orion_setbits(GPIO_IN_POL, (1 << pin));
+                orion5x_setbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_BOTHEDGE:
                 desc->handle_irq = handle_edge_irq;
@@ -115,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
                 /*
                  * set initial polarity based on current input level
                  */
-                if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
+                if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
                     & (1 << pin))
-                        orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
+                        orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
                 else
-                        orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
+                        orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
 
                 break;
         default:
@@ -133,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
         return 0;
 }
 
-static struct irq_chip orion_gpio_irq_chip = {
+static struct irq_chip orion5x_gpio_irq_chip = {
         .name           = "Orion-IRQ-GPIO",
-        .ack            = orion_gpio_irq_ack,
-        .mask           = orion_gpio_irq_mask,
-        .unmask         = orion_gpio_irq_unmask,
-        .set_type       = orion_gpio_set_irq_type,
+        .ack            = orion5x_gpio_irq_ack,
+        .mask           = orion5x_gpio_irq_mask,
+        .unmask         = orion5x_gpio_irq_unmask,
+        .set_type       = orion5x_gpio_set_irq_type,
 };
 
-static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         u32 cause, offs, pin;
 
-        BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
-        offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
-        cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
-                (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
+        BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
+        offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
+        cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
+                (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
 
         for (pin = offs; pin < offs + 8; pin++) {
                 if (cause & (1 << pin)) {
@@ -156,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                         desc = irq_desc + irq;
                         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
                                 /* Swap polarity (race with GPIO line) */
-                                u32 polarity = orion_read(GPIO_IN_POL);
+                                u32 polarity = orion5x_read(GPIO_IN_POL);
                                 polarity ^= 1 << pin;
-                                orion_write(GPIO_IN_POL, polarity);
+                                orion5x_write(GPIO_IN_POL, polarity);
                         }
                         desc_handle_irq(irq, desc);
                 }
         }
 }
 
-static void __init orion_init_gpio_irq(void)
+static void __init orion5x_init_gpio_irq(void)
 {
         int i;
         struct irq_desc *desc;
@@ -173,69 +175,37 @@ static void __init orion_init_gpio_irq(void)
         /*
          * Mask and clear GPIO IRQ interrupts
          */
-        orion_write(GPIO_LEVEL_MASK, 0x0);
-        orion_write(GPIO_EDGE_MASK, 0x0);
-        orion_write(GPIO_EDGE_CAUSE, 0x0);
+        orion5x_write(GPIO_LEVEL_MASK, 0x0);
+        orion5x_write(GPIO_EDGE_MASK, 0x0);
+        orion5x_write(GPIO_EDGE_CAUSE, 0x0);
 
         /*
          * Register chained level handlers for GPIO IRQs by default.
          * User can use set_type() if he wants to use edge types handlers.
          */
-        for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
+        for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
+                set_irq_chip(i, &orion5x_gpio_irq_chip);
                 set_irq_handler(i, handle_level_irq);
                 desc = irq_desc + i;
                 desc->status |= IRQ_LEVEL;
                 set_irq_flags(i, IRQF_VALID);
         }
-        set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
 }
 
 /*****************************************************************************
  * Orion Main IRQ
  ****************************************************************************/
-static void orion_main_irq_mask(u32 irq)
+static void __init orion5x_init_main_irq(void)
 {
-        orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
+        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
 }
 
-static void orion_main_irq_unmask(u32 irq)
+void __init orion5x_init_irq(void)
 {
-        orion_setbits(MAIN_IRQ_MASK, 1 << irq);
-}
-
-static struct irq_chip orion_main_irq_chip = {
-        .name           = "Orion-IRQ-Main",
-        .ack            = orion_main_irq_mask,
-        .mask           = orion_main_irq_mask,
-        .unmask         = orion_main_irq_unmask,
-};
-
-static void __init orion_init_main_irq(void)
-{
-        int i;
-
-        /*
-         * Mask and clear Main IRQ interrupts
-         */
-        orion_write(MAIN_IRQ_MASK, 0x0);
-        orion_write(MAIN_IRQ_CAUSE, 0x0);
-
-        /*
-         * Register level handler for Main IRQs
-         */
-        for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
-                set_irq_chip(i, &orion_main_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-}
-
-void __init orion_init_irq(void)
-{
-        orion_init_main_irq();
-        orion_init_gpio_irq();
+        orion5x_init_main_irq();
+        orion5x_init_gpio_irq();
 }
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 785a07bdf1e2..91413455beba 100644
--- a/arch/arm/mach-orion/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -1,10 +1,10 @@
 /*
- * arch/arm/mach-orion/kurobox_pro-setup.c
+ * arch/arm/mach-orion5x/kurobox_pro-setup.c
  *
  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -22,8 +22,8 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/orion_nand.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCI isn't used on the Kuro
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
         else
                 printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
 
@@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci kurobox_pro_pci __initdata = {
         .nr_controllers = 1,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = kurobox_pro_pci_map_irq,
 };
 
@@ -178,31 +178,25 @@ static struct mv_sata_platform_data kurobox_pro_sata_data = {
  * General Setup
  ****************************************************************************/
 
-static struct platform_device *kurobox_pro_devices[] __initdata = {
-        &kurobox_pro_nor_flash,
-        &kurobox_pro_nand_flash,
-};
-
 static void __init kurobox_pro_init(void)
 {
         /*
          * Setup basic Orion functions. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup the CPU address decode windows for our devices
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
-                                KUROBOX_PRO_NOR_BOOT_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE,
-                                KUROBOX_PRO_NAND_SIZE, -1);
+        orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
+                                KUROBOX_PRO_NOR_BOOT_SIZE);
+        orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
+
         /*
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-                (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /*
          * Setup Multiplexing Pins --
@@ -219,26 +213,44 @@ static void __init kurobox_pro_init(void)
          * MPP[15] SATA 1 active indication
          * MPP[16-19] Not used
          */
-        orion_write(MPP_0_7_CTRL, 0x44220003);
-        orion_write(MPP_8_15_CTRL, 0x55550000);
-        orion_write(MPP_16_19_CTRL, 0x0);
+        orion5x_write(MPP_0_7_CTRL, 0x44220003);
+        orion5x_write(MPP_8_15_CTRL, 0x55550000);
+        orion5x_write(MPP_16_19_CTRL, 0x0);
 
-        orion_gpio_set_valid_pins(0x0000000c);
+        orion5x_gpio_set_valid_pins(0x0000000c);
 
-        platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
+        platform_device_register(&kurobox_pro_nor_flash);
+        if (machine_is_kurobox_pro())
+                platform_device_register(&kurobox_pro_nand_flash);
         i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
-        orion_eth_init(&kurobox_pro_eth_data);
-        orion_sata_init(&kurobox_pro_sata_data);
+        orion5x_eth_init(&kurobox_pro_eth_data);
+        orion5x_sata_init(&kurobox_pro_sata_data);
 }
 
+#ifdef CONFIG_MACH_KUROBOX_PRO
 MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = kurobox_pro_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_PRO
+MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
+        /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
new file mode 100644
index 000000000000..fdf99fca85b3
--- /dev/null
+++ b/arch/arm/mach-orion5x/pci.c
@@ -0,0 +1,559 @@
+/*
+ * arch/arm/mach-orion5x/pci.c
+ *
+ * PCI and PCIe functions for Marvell Orion System On Chip
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+#include "common.h"
+
+/*****************************************************************************
+ * Orion has one PCIe controller and one PCI controller.
+ *
+ * Note1: The local PCIe bus number is '0'. The local PCI bus number
+ * follows the scanned PCIe bridged busses, if any.
+ *
+ * Note2: It is possible for PCI/PCIe agents to access many subsystem's
+ * space, by configuring BARs and Address Decode Windows, e.g. flashes on
+ * device bus, Orion registers, etc. However this code only enable the
+ * access to DDR banks.
+ ****************************************************************************/
+
+
+/*****************************************************************************
+ * PCIe controller
+ ****************************************************************************/
+#define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+
+void __init orion5x_pcie_id(u32 *dev, u32 *rev)
+{
+        *dev = orion_pcie_dev_id(PCIE_BASE);
+        *rev = orion_pcie_rev(PCIE_BASE);
+}
+
+int __init orion5x_pcie_local_bus_nr(void)
+{
+        return orion_pcie_get_local_bus_nr(PCIE_BASE);
+}
+
+static int pcie_valid_config(int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access --
+         * 1. nonexisting device on local bus
+         * 2. where there's no device connected (no link)
+         */
+        if (bus == 0 && dev == 0)
+                return 1;
+
+        if (!orion_pcie_link_up(PCIE_BASE))
+                return 0;
+
+        if (bus == 0 && dev != 1)
+                return 0;
+
+        return 1;
+}
+
+
+/*
+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(orion5x_pcie_lock);
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        spin_lock_irqsave(&orion5x_pcie_lock, flags);
+        ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
+
+        return ret;
+}
+
+static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
+                           int where, int size, u32 *val)
+{
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /*
+         * We only support access to the non-extended configuration
+         * space when using the WA access method (or we would have to
+         * sacrifice 256M of CPU virtual address space.)
+         */
+        if (where >= 0x100) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+                                    bus, devfn, where, size, val);
+
+        return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        spin_lock_irqsave(&orion5x_pcie_lock, flags);
+        ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+
+
+static int __init pcie_setup(struct pci_sys_data *sys)
+{
+        struct resource *res;
+        int dev;
+
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
+
+        /*
+         * Check whether to apply Orion-1/Orion-NAS PCIe config
+         * read transaction workaround.
+         */
+        dev = orion_pcie_dev_id(PCIE_BASE);
+        if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
+                printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
+                                   "read transaction workaround\n");
+                pcie_ops.read = pcie_rd_conf_wa;
+        }
+
+        /*
+         * Request resources.
+         */
+        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("pcie_setup unable to alloc resources");
+
+        /*
+         * IORESOURCE_IO
+         */
+        res[0].name = "PCIe I/O Space";
+        res[0].flags = IORESOURCE_IO;
+        res[0].start = ORION5X_PCIE_IO_BUS_BASE;
+        res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
+        if (request_resource(&ioport_resource, &res[0]))
+                panic("Request PCIe IO resource failed\n");
+        sys->resource[0] = &res[0];
+
+        /*
+         * IORESOURCE_MEM
+         */
+        res[1].name = "PCIe Memory Space";
+        res[1].flags = IORESOURCE_MEM;
+        res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
+        res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, &res[1]))
+                panic("Request PCIe Memory resource failed\n");
+        sys->resource[1] = &res[1];
+
+        sys->resource[2] = NULL;
+        sys->io_offset = 0;
+
+        return 1;
+}
+
+/*****************************************************************************
+ * PCI controller
+ ****************************************************************************/
+#define PCI_MODE                ORION5X_PCI_REG(0xd00)
+#define PCI_CMD                 ORION5X_PCI_REG(0xc00)
+#define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
+#define PCI_CONF_ADDR           ORION5X_PCI_REG(0xc78)
+#define PCI_CONF_DATA           ORION5X_PCI_REG(0xc7c)
+
+/*
+ * PCI_MODE bits
+ */
+#define PCI_MODE_64BIT                  (1 << 2)
+#define PCI_MODE_PCIX                   ((1 << 4) | (1 << 5))
+
+/*
+ * PCI_CMD bits
+ */
+#define PCI_CMD_HOST_REORDER            (1 << 29)
+
+/*
+ * PCI_P2P_CONF bits
+ */
+#define PCI_P2P_BUS_OFFS                16
+#define PCI_P2P_BUS_MASK                (0xff << PCI_P2P_BUS_OFFS)
+#define PCI_P2P_DEV_OFFS                24
+#define PCI_P2P_DEV_MASK                (0x1f << PCI_P2P_DEV_OFFS)
+
+/*
+ * PCI_CONF_ADDR bits
+ */
+#define PCI_CONF_REG(reg)               ((reg) & 0xfc)
+#define PCI_CONF_FUNC(func)             (((func) & 0x3) << 8)
+#define PCI_CONF_DEV(dev)               (((dev) & 0x1f) << 11)
+#define PCI_CONF_BUS(bus)               (((bus) & 0xff) << 16)
+#define PCI_CONF_ADDR_EN                (1 << 31)
+
+/*
+ * Internal configuration space
+ */
+#define PCI_CONF_FUNC_STAT_CMD          0
+#define PCI_CONF_REG_STAT_CMD           4
+#define PCIX_STAT                       0x64
+#define PCIX_STAT_BUS_OFFS              8
+#define PCIX_STAT_BUS_MASK              (0xff << PCIX_STAT_BUS_OFFS)
+
+/*
+ * PCI Address Decode Windows registers
+ */
+#define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
+                                ((n) == 1) ? ORION5X_PCI_REG(0xd08) :  \
+                                ((n) == 2) ? ORION5X_PCI_REG(0xc0c) :  \
+                                ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
+#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) :  \
+                                ((n) == 1) ? ORION5X_PCI_REG(0xd48) :  \
+                                ((n) == 2) ? ORION5X_PCI_REG(0xc4c) :  \
+                                ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
+#define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
+#define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
+
+/*
+ * PCI configuration helpers for BAR settings
+ */
+#define PCI_CONF_FUNC_BAR_CS(n)         ((n) >> 1)
+#define PCI_CONF_REG_BAR_LO_CS(n)       (((n) & 1) ? 0x18 : 0x10)
+#define PCI_CONF_REG_BAR_HI_CS(n)       (((n) & 1) ? 0x1c : 0x14)
+
+/*
+ * PCI config cycles are done by programming the PCI_CONF_ADDR register
+ * and then reading the PCI_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(orion5x_pci_lock);
+
+int orion5x_pci_local_bus_nr(void)
+{
+        u32 conf = orion5x_read(PCI_P2P_CONF);
+        return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
+}
+
+static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
+                                        u32 where, u32 size, u32 *val)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&orion5x_pci_lock, flags);
+
+        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
+                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+
+        *val = orion5x_read(PCI_CONF_DATA);
+
+        if (size == 1)
+                *val = (*val >> (8*(where & 0x3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8*(where & 0x3))) & 0xffff;
+
+        spin_unlock_irqrestore(&orion5x_pci_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
+                                        u32 where, u32 size, u32 val)
+{
+        unsigned long flags;
+        int ret = PCIBIOS_SUCCESSFUL;
+
+        spin_lock_irqsave(&orion5x_pci_lock, flags);
+
+        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
+                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+
+        if (size == 4) {
+                __raw_writel(val, PCI_CONF_DATA);
+        } else if (size == 2) {
+                __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
+        } else if (size == 1) {
+                __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
+        } else {
+                ret = PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        spin_unlock_irqrestore(&orion5x_pci_lock, flags);
+
+        return ret;
+}
+
+static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
+                                int where, int size, u32 *val)
+{
+        /*
+         * Don't go out for local device
+         */
+        if (bus->number == orion5x_pci_local_bus_nr() &&
+            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
+                                        PCI_FUNC(devfn), where, size, val);
+}
+
+static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
+                                int where, int size, u32 val)
+{
+        if (bus->number == orion5x_pci_local_bus_nr() &&
+            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
+                                        PCI_FUNC(devfn), where, size, val);
+}
+
+static struct pci_ops pci_ops = {
+        .read = orion5x_pci_rd_conf,
+        .write = orion5x_pci_wr_conf,
+};
+
+static void __init orion5x_pci_set_bus_nr(int nr)
+{
+        u32 p2p = orion5x_read(PCI_P2P_CONF);
+
+        if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
+                /*
+                 * PCI-X mode
+                 */
+                u32 pcix_status, bus, dev;
+                bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
+                dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
+                orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
+                pcix_status &= ~PCIX_STAT_BUS_MASK;
+                pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
+                orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
+        } else {
+                /*
+                 * PCI Conventional mode
+                 */
+                p2p &= ~PCI_P2P_BUS_MASK;
+                p2p |= (nr << PCI_P2P_BUS_OFFS);
+                orion5x_write(PCI_P2P_CONF, p2p);
+        }
+}
+
+static void __init orion5x_pci_master_slave_enable(void)
+{
+        int bus_nr, func, reg;
+        u32 val;
+
+        bus_nr = orion5x_pci_local_bus_nr();
+        func = PCI_CONF_FUNC_STAT_CMD;
+        reg = PCI_CONF_REG_STAT_CMD;
+        orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
+        val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+        orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
+}
+
+static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
+{
+        u32 win_enable;
+        int bus;
+        int i;
+
+        /*
+         * First, disable windows.
+         */
+        win_enable = 0xffffffff;
+        orion5x_write(PCI_BAR_ENABLE, win_enable);
+
+        /*
+         * Setup windows for DDR banks.
+         */
+        bus = orion5x_pci_local_bus_nr();
+
+        for (i = 0; i < dram->num_cs; i++) {
+                struct mbus_dram_window *cs = dram->cs + i;
+                u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
+                u32 reg;
+                u32 val;
+
+                /*
+                 * Write DRAM bank base address register.
+                 */
+                reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
+                orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
+                val = (cs->base & 0xfffff000) | (val & 0xfff);
+                orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
+
+                /*
+                 * Write DRAM bank size register.
+                 */
+                reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
+                orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
+                orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
+                                (cs->size - 1) & 0xfffff000);
+                orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
+                                cs->base & 0xfffff000);
+
+                /*
+                 * Enable decode window for this chip select.
+                 */
+                win_enable &= ~(1 << cs->cs_index);
+        }
+
+        /*
+         * Re-enable decode windows.
+         */
+        orion5x_write(PCI_BAR_ENABLE, win_enable);
+
+        /*
+         * Disable automatic update of address remaping when writing to BARs.
+         */
+        orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
+}
+
+static int __init pci_setup(struct pci_sys_data *sys)
+{
+        struct resource *res;
+
+        /*
+         * Point PCI unit MBUS decode windows to DRAM space.
+         */
+        orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
+
+        /*
+         * Master + Slave enable
+         */
+        orion5x_pci_master_slave_enable();
+
+        /*
+         * Force ordering
+         */
+        orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
+
+        /*
+         * Request resources
+         */
+        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("pci_setup unable to alloc resources");
+
+        /*
+         * IORESOURCE_IO
+         */
+        res[0].name = "PCI I/O Space";
+        res[0].flags = IORESOURCE_IO;
+        res[0].start = ORION5X_PCI_IO_BUS_BASE;
+        res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
+        if (request_resource(&ioport_resource, &res[0]))
+                panic("Request PCI IO resource failed\n");
+        sys->resource[0] = &res[0];
+
+        /*
+         * IORESOURCE_MEM
+         */
+        res[1].name = "PCI Memory Space";
+        res[1].flags = IORESOURCE_MEM;
+        res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
+        res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, &res[1]))
+                panic("Request PCI Memory resource failed\n");
+        sys->resource[1] = &res[1];
+
+        sys->resource[2] = NULL;
+        sys->io_offset = 0;
+
+        return 1;
+}
+
+
+/*****************************************************************************
+ * General PCIe + PCI
+ ****************************************************************************/
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+
+int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
+{
+        int ret = 0;
+
+        if (nr == 0) {
+                orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
+                ret = pcie_setup(sys);
+        } else if (nr == 1) {
+                orion5x_pci_set_bus_nr(sys->busnr);
+                ret = pci_setup(sys);
+        }
+
+        return ret;
+}
+
+struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+
+        if (nr == 0) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else if (nr == 1) {
+                bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+
+        return bus;
+}
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index e851b8ca5ac6..37e8b2dc3ed5 100644
--- a/arch/arm/mach-orion/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/rd88f5182-setup.c
+ * arch/arm/mach-orion5x/rd88f5182-setup.c
  *
  * Marvell Orion-NAS Reference Design Setup
  *
  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -24,8 +24,7 @@
 #include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -176,8 +175,8 @@ static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCI-E isn't used on the RD2
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         /*
          * PCI IRQs are connected via GPIOs
@@ -197,8 +196,8 @@ static struct hw_pci rd88f5182_pci __initdata = {
         .nr_controllers = 2,
         .preinit        = rd88f5182_pci_preinit,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = rd88f5182_pci_map_irq,
 };
 
@@ -250,22 +249,20 @@ static void __init rd88f5182_init(void)
         /*
          * Setup basic Orion functions. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup the CPU address decode windows for our devices
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
-                                RD88F5182_NOR_BOOT_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
-                                RD88F5182_NOR_SIZE, -1);
+        orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
+                                RD88F5182_NOR_BOOT_SIZE);
+        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
 
         /*
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-                (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /*
          * Setup Multiplexing Pins --
@@ -291,25 +288,25 @@ static void __init rd88f5182_init(void)
          * MPP[25] USB 0 over current enable
          */
 
-        orion_write(MPP_0_7_CTRL, 0x00000003);
-        orion_write(MPP_8_15_CTRL, 0x55550000);
-        orion_write(MPP_16_19_CTRL, 0x5555);
+        orion5x_write(MPP_0_7_CTRL, 0x00000003);
+        orion5x_write(MPP_8_15_CTRL, 0x55550000);
+        orion5x_write(MPP_16_19_CTRL, 0x5555);
 
-        orion_gpio_set_valid_pins(0x000000fb);
+        orion5x_gpio_set_valid_pins(0x000000fb);
 
         platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
         i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
-        orion_eth_init(&rd88f5182_eth_data);
-        orion_sata_init(&rd88f5182_sata_data);
+        orion5x_eth_init(&rd88f5182_eth_data);
+        orion5x_sata_init(&rd88f5182_sata_data);
 }
 
 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5182_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 45764dad16d0..fd43863a86f6 100644
--- a/arch/arm/mach-orion/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -26,8 +26,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
@@ -145,8 +144,8 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCIE IRQ is connected internally (not GPIO)
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         /*
          * PCI IRQs are connected via GPIOs
@@ -165,8 +164,8 @@ static struct hw_pci qnap_ts209_pci __initdata = {
         .nr_controllers = 2,
         .preinit        = qnap_ts209_pci_preinit,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = qnap_ts209_pci_map_irq,
 };
 
@@ -189,6 +188,87 @@ static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
         .force_phy_addr = 1,
 };
 
+static int __init parse_hex_nibble(char n)
+{
+        if (n >= '0' && n <= '9')
+                return n - '0';
+
+        if (n >= 'A' && n <= 'F')
+                return n - 'A' + 10;
+
+        if (n >= 'a' && n <= 'f')
+                return n - 'a' + 10;
+
+        return -1;
+}
+
+static int __init parse_hex_byte(const char *b)
+{
+        int hi;
+        int lo;
+
+        hi = parse_hex_nibble(b[0]);
+        lo = parse_hex_nibble(b[1]);
+
+        if (hi < 0 || lo < 0)
+                return -1;
+
+        return (hi << 4) | lo;
+}
+
+static int __init check_mac_addr(const char *addr_str)
+{
+        u_int8_t addr[6];
+        int i;
+
+        for (i = 0; i < 6; i++) {
+                int byte;
+
+                /*
+                 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
+                 */
+                if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
+                        return -1;
+
+                byte = parse_hex_byte(addr_str + (i * 3));
+                if (byte < 0)
+                        return -1;
+                addr[i] = byte;
+        }
+
+        printk(KERN_INFO "ts209: found ethernet mac address ");
+        for (i = 0; i < 6; i++)
+                printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
+
+        memcpy(qnap_ts209_eth_data.mac_addr, addr, 6);
+
+        return 0;
+}
+
+/*
+ * The 'NAS Config' flash partition has an ext2 filesystem which
+ * contains a file that has the ethernet MAC address in plain text
+ * (format "xx:xx:xx:xx:xx:xx\n".)
+ */
+static void __init ts209_find_mac_addr(void)
+{
+        unsigned long addr;
+
+        for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
+                char *nor_page;
+                int ret = 0;
+
+                nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024);
+                if (nor_page != NULL) {
+                        ret = check_mac_addr(nor_page);
+                        iounmap(nor_page);
+                }
+
+                if (ret == 0)
+                        break;
+        }
+}
+
 /*****************************************************************************
  * RTC S35390A on I2C bus
  ****************************************************************************/
@@ -262,21 +342,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = {
 static void qnap_ts209_power_off(void)
 {
         /* 19200 baud divisor */
-        const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200));
+        const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
 
         pr_info("%s: triggering power-off...\n", __func__);
 
         /* hijack uart1 and reset into sane state (19200,8n1) */
-        orion_write(UART1_REG(LCR), 0x83);
-        orion_write(UART1_REG(DLL), divisor & 0xff);
-        orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
-        orion_write(UART1_REG(LCR), 0x03);
-        orion_write(UART1_REG(IER), 0x00);
-        orion_write(UART1_REG(FCR), 0x00);
-        orion_write(UART1_REG(MCR), 0x00);
+        orion5x_write(UART1_REG(LCR), 0x83);
+        orion5x_write(UART1_REG(DLL), divisor & 0xff);
+        orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
+        orion5x_write(UART1_REG(LCR), 0x03);
+        orion5x_write(UART1_REG(IER), 0x00);
+        orion5x_write(UART1_REG(FCR), 0x00);
+        orion5x_write(UART1_REG(MCR), 0x00);
 
         /* send the power-off command 'A' to PIC */
-        orion_write(UART1_REG(TX), 'A');
+        orion5x_write(UART1_REG(TX), 'A');
 }
 
 static void __init qnap_ts209_init(void)
@@ -284,20 +364,19 @@ static void __init qnap_ts209_init(void)
         /*
          * Setup basic Orion functions. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup flash mapping
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE,
-                            QNAP_TS209_NOR_BOOT_SIZE, -1);
+        orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
+                            QNAP_TS209_NOR_BOOT_SIZE);
 
         /*
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-                (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /*
          * Setup Multiplexing Pins --
@@ -322,10 +401,10 @@ static void __init qnap_ts209_init(void)
          * MPP[22] USB 0 over current
          * MPP[23-25] Reserved
          */
-        orion_write(MPP_0_7_CTRL, 0x3);
-        orion_write(MPP_8_15_CTRL, 0x55550000);
-        orion_write(MPP_16_19_CTRL, 0x5500);
-        orion_gpio_set_valid_pins(0x3cc0fff);
+        orion5x_write(MPP_0_7_CTRL, 0x3);
+        orion5x_write(MPP_8_15_CTRL, 0x55550000);
+        orion5x_write(MPP_16_19_CTRL, 0x5500);
+        orion5x_gpio_set_valid_pins(0x3cc0fff);
 
         /* register ts209 specific power-off method */
         pm_power_off = qnap_ts209_power_off;
@@ -344,18 +423,20 @@ static void __init qnap_ts209_init(void)
                 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
         i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
 
-        orion_eth_init(&qnap_ts209_eth_data);
-        orion_sata_init(&qnap_ts209_sata_data);
+        ts209_find_mac_addr();
+        orion5x_eth_init(&qnap_ts209_eth_data);
+
+        orion5x_sata_init(&qnap_ts209_sata_data);
 }
 
 MACHINE_START(TS209, "QNAP TS-109/TS-209")
         /* Maintainer:  Byron Bradley <byron.bbradley@gmail.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts209_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
 MACHINE_END
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
index 8e00ed43fb95..a5268c3ac5a7 100644
--- a/arch/arm/mach-pnx4008/clock.c
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -21,7 +21,6 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 
-#include <asm/semaphore.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
index 1ab84ced7b5a..ef179cab80e2 100644
--- a/arch/arm/mach-pnx4008/gpio.c
+++ b/arch/arm/mach-pnx4008/gpio.c
@@ -17,7 +17,6 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <asm/semaphore.h>
 #include <asm/io.h>
 #include <asm/arch/platform.h>
 #include <asm/arch/gpio.h>
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 0908bea0f609..5da7a6820492 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -23,6 +23,12 @@ endif
 choice
         prompt "Select target board"
 
+config ARCH_GUMSTIX
+        bool "Gumstix XScale boards"
+        help
+          Say Y here if you intend to run this kernel on a
+          Gumstix Full Function Minature Computer.
+
 config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform"
         select PXA25x
@@ -160,6 +166,20 @@ endchoice
 
 endif
 
+if ARCH_GUMSTIX
+
+choice
+        prompt "Select target Gumstix board"
+
+config MACH_GUMSTIX_F
+        bool "Basix, Connex, ws-200ax, ws-400ax systems"
+        select PXA25x
+
+endchoice
+
+endif
+
+
 if MACH_TRIZEPS4
 
 choice
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 6e0c4f5b5ae6..7cdcb459ea9d 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -5,13 +5,14 @@
 # Common support (must be linked before board specific support)
 obj-y                           += clock.o devices.o generic.o irq.o dma.o \
                                    time.o gpio.o
-obj-$(CONFIG_PXA25x)            += pxa25x.o
-obj-$(CONFIG_PXA27x)            += pxa27x.o
-obj-$(CONFIG_PXA3xx)            += pxa3xx.o mfp.o smemc.o
+obj-$(CONFIG_PXA25x)            += pxa25x.o mfp-pxa2xx.o
+obj-$(CONFIG_PXA27x)            += pxa27x.o mfp-pxa2xx.o
+obj-$(CONFIG_PXA3xx)            += pxa3xx.o mfp-pxa3xx.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 
 # Specific board support
+obj-$(CONFIG_ARCH_GUMSTIX)      += gumstix.o
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index df5ae2710ab1..e97dc59813c8 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -13,6 +13,7 @@
 #include <linux/delay.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/hardware.h>
 
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
index fcda7d5cb693..ac7f05f9f3eb 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -23,6 +23,7 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/cm-x270.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/mach-types.h>
 
 #include <asm/hardware/it8152.h>
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index ecdbc96a4de1..6d4416a4f378 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -30,6 +30,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri.c
index 6db54e31c397..43bf5a183e90 100644
--- a/arch/arm/mach-pxa/colibri.c
+++ b/arch/arm/mach-pxa/colibri.c
@@ -29,6 +29,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/colibri.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 9292576b83b3..259ca821e464 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -36,6 +36,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 392c38717362..0a85f706e887 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/corgi.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
index 31706224a04c..eccc45d21f75 100644
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -21,6 +21,7 @@
 
 #include <asm/arch/ssp.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/regs-ssp.h>
 #include "sharpsl.h"
 
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index bfccb80ac8ef..d6c05b6eab35 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -11,6 +11,8 @@
 #include <asm/arch/irda.h>
 #include <asm/arch/i2c.h>
 #include <asm/arch/ohci.h>
+#include <asm/arch/pxa27x_keypad.h>
+#include <asm/arch/camera.h>
 
 #include "devices.h"
 
@@ -396,6 +398,31 @@ struct platform_device pxa25x_device_assp = {
 
 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 
+static struct resource pxa27x_resource_keypad[] = {
+        [0] = {
+                .start  = 0x41500000,
+                .end    = 0x4150004c,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_KEYPAD,
+                .end    = IRQ_KEYPAD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa27x_device_keypad = {
+        .name           = "pxa27x-keypad",
+        .id             = -1,
+        .resource       = pxa27x_resource_keypad,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_keypad),
+};
+
+void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
+{
+        pxa_register_device(&pxa27x_device_keypad, info);
+}
+
 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource pxa27x_resource_ohci[] = {
@@ -540,6 +567,37 @@ struct platform_device pxa27x_device_ssp3 = {
         .resource       = pxa27x_resource_ssp3,
         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
 };
+
+static struct resource pxa27x_resource_camera[] = {
+        [0] = {
+                .start  = 0x50000000,
+                .end    = 0x50000fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_CAMERA,
+                .end    = IRQ_CAMERA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
+
+static struct platform_device pxa27x_device_camera = {
+        .name           = "pxa27x-camera",
+        .id             = 0, /* This is used to put cameras on this interface */
+        .dev            = {
+                .dma_mask               = &pxa27x_dma_mask_camera,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_camera),
+        .resource       = pxa27x_resource_camera,
+};
+
+void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
+{
+        pxa_register_device(&pxa27x_device_camera, info);
+}
 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
 
 #ifdef CONFIG_PXA3xx
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 96c7c8909068..fcab017f27ee 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -14,6 +14,7 @@ extern struct platform_device pxa_device_rtc;
 
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
+extern struct platform_device pxa27x_device_keypad;
 
 extern struct platform_device pxa25x_device_ssp;
 extern struct platform_device pxa25x_device_nssp;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 3bb31314429a..edc4f07a230d 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -23,6 +23,7 @@
 #include <asm/mach/arch.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 80721c610d41..331f29b2d0cd 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -19,14 +19,8 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/string.h>
-#include <linux/sysdev.h>
 
 #include <asm/hardware.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
@@ -134,59 +128,3 @@ void __init pxa_map_io(void)
         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
         get_clk_frequency_khz(1);
 }
-
-#ifdef CONFIG_PM
-
-static unsigned long saved_gplr[4];
-static unsigned long saved_gpdr[4];
-static unsigned long saved_grer[4];
-static unsigned long saved_gfer[4];
-
-static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
-{
-        int i, gpio;
-
-        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
-                saved_gplr[i] = GPLR(gpio);
-                saved_gpdr[i] = GPDR(gpio);
-                saved_grer[i] = GRER(gpio);
-                saved_gfer[i] = GFER(gpio);
-
-                /* Clear GPIO transition detect bits */
-                GEDR(gpio) = GEDR(gpio);
-        }
-        return 0;
-}
-
-static int pxa_gpio_resume(struct sys_device *dev)
-{
-        int i, gpio;
-
-        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
-                /* restore level with set/clear */
-                GPSR(gpio) = saved_gplr[i];
-                GPCR(gpio) = ~saved_gplr[i];
-
-                GRER(gpio) = saved_grer[i];
-                GFER(gpio) = saved_gfer[i];
-                GPDR(gpio) = saved_gpdr[i];
-        }
-        return 0;
-}
-#else
-#define pxa_gpio_suspend        NULL
-#define pxa_gpio_resume         NULL
-#endif
-
-struct sysdev_class pxa_gpio_sysclass = {
-        .name           = "gpio",
-        .suspend        = pxa_gpio_suspend,
-        .resume         = pxa_gpio_resume,
-};
-
-static int __init pxa_gpio_init(void)
-{
-        return sysdev_class_register(&pxa_gpio_sysclass);
-}
-
-core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index b3d10b0e52a0..5bb7ae757831 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,14 +9,13 @@
  * published by the Free Software Foundation.
  */
 
+typedef int (*set_wake_t)(unsigned int, unsigned int);
+
 struct sys_timer;
 
 extern struct sys_timer pxa_timer;
-extern void __init pxa_init_irq_low(void);
-extern void __init pxa_init_irq_high(void);
-extern void __init pxa_init_irq_gpio(int gpio_nr);
-extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
-extern void __init pxa_init_gpio(int gpio_nr);
+extern void __init pxa_init_irq(int irq_nr, set_wake_t fn);
+extern void __init pxa_init_gpio(int gpio_nr, set_wake_t fn);
 extern void __init pxa25x_init_irq(void);
 extern void __init pxa27x_init_irq(void);
 extern void __init pxa3xx_init_irq(void);
@@ -30,6 +29,8 @@ extern int pxa_last_gpio;
         mi->bank[__nr].size = (__size), \
         mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
 
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
 #ifdef CONFIG_PXA25x
 extern unsigned pxa25x_get_clk_frequency_khz(int);
 extern unsigned pxa25x_get_memclk_frequency_10khz(void);
@@ -56,3 +57,4 @@ extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
 
 extern struct sysdev_class pxa_irq_sysclass;
 extern struct sysdev_class pxa_gpio_sysclass;
+extern struct sysdev_class pxa3xx_mfp_sysclass;
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
index 8638dd7dd076..7d3e16970be0 100644
--- a/arch/arm/mach-pxa/gpio.c
+++ b/arch/arm/mach-pxa/gpio.c
@@ -14,11 +14,14 @@
 
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/sysdev.h>
 
 #include <asm/gpio.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 #include "generic.h"
 
@@ -129,69 +132,283 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
                 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
 }
 
+#define GPIO_CHIP(_n)                                                   \
+        [_n] = {                                                        \
+                .regbase = GPIO##_n##_BASE,                             \
+                .chip = {                                               \
+                        .label            = "gpio-" #_n,                \
+                        .direction_input  = pxa_gpio_direction_input,   \
+                        .direction_output = pxa_gpio_direction_output,  \
+                        .get              = pxa_gpio_get,               \
+                        .set              = pxa_gpio_set,               \
+                        .base             = (_n) * 32,                  \
+                        .ngpio            = 32,                         \
+                },                                                      \
+        }
+
 static struct pxa_gpio_chip pxa_gpio_chip[] = {
-        [0] = {
-                .regbase = GPIO0_BASE,
-                .chip = {
-                        .label            = "gpio-0",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 0,
-                        .ngpio            = 32,
-                },
-        },
-        [1] = {
-                .regbase = GPIO1_BASE,
-                .chip = {
-                        .label            = "gpio-1",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 32,
-                        .ngpio            = 32,
-                },
-        },
-        [2] = {
-                .regbase = GPIO2_BASE,
-                .chip = {
-                        .label            = "gpio-2",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 64,
-                        .ngpio            = 32, /* 21 for PXA25x */
-                },
-        },
+        GPIO_CHIP(0),
+        GPIO_CHIP(1),
+        GPIO_CHIP(2),
 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-        [3] = {
-                .regbase = GPIO3_BASE,
-                .chip = {
-                        .label            = "gpio-3",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 96,
-                        .ngpio            = 32,
-                },
-        },
+        GPIO_CHIP(3),
 #endif
 };
 
-void __init pxa_init_gpio(int gpio_nr)
+/*
+ * PXA GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * Use this instead of directly setting GRER/GFER.
+ */
+
+static unsigned long GPIO_IRQ_rising_edge[4];
+static unsigned long GPIO_IRQ_falling_edge[4];
+static unsigned long GPIO_IRQ_mask[4];
+
+/*
+ * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
+ * function of a GPIO, and GPDRx cannot be altered once configured. It
+ * is attributed as "occupied" here (I know this terminology isn't
+ * accurate, you are welcome to propose a better one :-)
+ */
+static int __gpio_is_occupied(unsigned gpio)
+{
+        if (cpu_is_pxa25x() || cpu_is_pxa27x())
+                return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
+        else
+                return 0;
+}
+
+static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+        int gpio, idx;
+
+        gpio = IRQ_TO_GPIO(irq);
+        idx = gpio >> 5;
+
+        if (type == IRQ_TYPE_PROBE) {
+                /* Don't mess with enabled GPIOs using preconfigured edges or
+                 * GPIOs set to alternate function or to output during probe
+                 */
+                if ((GPIO_IRQ_rising_edge[idx] |
+                     GPIO_IRQ_falling_edge[idx] |
+                     GPDR(gpio)) & GPIO_bit(gpio))
+                        return 0;
+
+                if (__gpio_is_occupied(gpio))
+                        return 0;
+
+                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        }
+
+        GPDR(gpio) &= ~GPIO_bit(gpio);
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                __set_bit(gpio, GPIO_IRQ_rising_edge);
+        else
+                __clear_bit(gpio, GPIO_IRQ_rising_edge);
+
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                __set_bit(gpio, GPIO_IRQ_falling_edge);
+        else
+                __clear_bit(gpio, GPIO_IRQ_falling_edge);
+
+        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
+        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
+
+        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
+                ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
+                ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
+        return 0;
+}
+
+/*
+ * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
+ */
+
+static void pxa_ack_low_gpio(unsigned int irq)
+{
+        GEDR0 = (1 << (irq - IRQ_GPIO0));
+}
+
+static void pxa_mask_low_gpio(unsigned int irq)
+{
+        ICMR &= ~(1 << (irq - PXA_IRQ(0)));
+}
+
+static void pxa_unmask_low_gpio(unsigned int irq)
+{
+        ICMR |= 1 << (irq - PXA_IRQ(0));
+}
+
+static struct irq_chip pxa_low_gpio_chip = {
+        .name           = "GPIO-l",
+        .ack            = pxa_ack_low_gpio,
+        .mask           = pxa_mask_low_gpio,
+        .unmask         = pxa_unmask_low_gpio,
+        .set_type       = pxa_gpio_irq_type,
+};
+
+/*
+ * Demux handler for GPIO>=2 edge detect interrupts
+ */
+
+#define GEDR_BITS       (sizeof(gedr) * BITS_PER_BYTE)
+
+static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int loop, bit, n;
+        unsigned long gedr[4];
+
+        do {
+                gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
+                gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
+                gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
+                gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
+
+                GEDR0 = gedr[0]; GEDR1 = gedr[1];
+                GEDR2 = gedr[2]; GEDR3 = gedr[3];
+
+                loop = 0;
+                bit = find_first_bit(gedr, GEDR_BITS);
+                while (bit < GEDR_BITS) {
+                        loop = 1;
+
+                        n = PXA_GPIO_IRQ_BASE + bit;
+                        desc_handle_irq(n, irq_desc + n);
+
+                        bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
+                }
+        } while (loop);
+}
+
+static void pxa_ack_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq - IRQ_GPIO(2) + 2;
+        GEDR(gpio) = GPIO_bit(gpio);
+}
+
+static void pxa_mask_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq - IRQ_GPIO(2) + 2;
+        __clear_bit(gpio, GPIO_IRQ_mask);
+        GRER(gpio) &= ~GPIO_bit(gpio);
+        GFER(gpio) &= ~GPIO_bit(gpio);
+}
+
+static void pxa_unmask_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq - IRQ_GPIO(2) + 2;
+        int idx = gpio >> 5;
+        __set_bit(gpio, GPIO_IRQ_mask);
+        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
+        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
+}
+
+static struct irq_chip pxa_muxed_gpio_chip = {
+        .name           = "GPIO",
+        .ack            = pxa_ack_muxed_gpio,
+        .mask           = pxa_mask_muxed_gpio,
+        .unmask         = pxa_unmask_muxed_gpio,
+        .set_type       = pxa_gpio_irq_type,
+};
+
+void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
 {
-        int i;
+        int irq, i, gpio;
+
+        pxa_last_gpio = gpio_nr - 1;
+
+        /* clear all GPIO edge detects */
+        for (i = 0; i < gpio_nr; i += 32) {
+                GFER(i) = 0;
+                GRER(i) = 0;
+                GEDR(i) = GEDR(i);
+        }
+
+        /* GPIO 0 and 1 must have their mask bit always set */
+        GPIO_IRQ_mask[0] = 3;
+
+        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
+                set_irq_chip(irq, &pxa_low_gpio_chip);
+                set_irq_handler(irq, handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
+                set_irq_chip(irq, &pxa_muxed_gpio_chip);
+                set_irq_handler(irq, handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        /* Install handler for GPIO>=2 edge detect interrupts */
+        set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
+
+        pxa_low_gpio_chip.set_wake = fn;
+        pxa_muxed_gpio_chip.set_wake = fn;
 
         /* add a GPIO chip for each register bank.
          * the last PXA25x register only contains 21 GPIOs
          */
-        for (i = 0; i < gpio_nr; i += 32) {
-                if (i+32 > gpio_nr)
-                        pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i;
-                gpiochip_add(&pxa_gpio_chip[i/32].chip);
+        for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
+                if (gpio + 32 > gpio_nr)
+                        pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
+                gpiochip_add(&pxa_gpio_chip[i].chip);
         }
 }
+
+#ifdef CONFIG_PM
+
+static unsigned long saved_gplr[4];
+static unsigned long saved_gpdr[4];
+static unsigned long saved_grer[4];
+static unsigned long saved_gfer[4];
+
+static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+        int i, gpio;
+
+        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+                saved_gplr[i] = GPLR(gpio);
+                saved_gpdr[i] = GPDR(gpio);
+                saved_grer[i] = GRER(gpio);
+                saved_gfer[i] = GFER(gpio);
+
+                /* Clear GPIO transition detect bits */
+                GEDR(gpio) = GEDR(gpio);
+        }
+        return 0;
+}
+
+static int pxa_gpio_resume(struct sys_device *dev)
+{
+        int i, gpio;
+
+        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+                /* restore level with set/clear */
+                GPSR(gpio) = saved_gplr[i];
+                GPCR(gpio) = ~saved_gplr[i];
+
+                GRER(gpio) = saved_grer[i];
+                GFER(gpio) = saved_gfer[i];
+                GPDR(gpio) = saved_gpdr[i];
+        }
+        return 0;
+}
+#else
+#define pxa_gpio_suspend        NULL
+#define pxa_gpio_resume         NULL
+#endif
+
+struct sysdev_class pxa_gpio_sysclass = {
+        .name           = "gpio",
+        .suspend        = pxa_gpio_suspend,
+        .resume         = pxa_gpio_resume,
+};
+
+static int __init pxa_gpio_init(void)
+{
+        return sysdev_class_register(&pxa_gpio_sysclass);
+}
+
+core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
new file mode 100644
index 000000000000..f01d18544133
--- /dev/null
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -0,0 +1,147 @@
+/*
+ *  linux/arch/arm/mach-pxa/gumstix.c
+ *
+ *  Support for the Gumstix motherboards.
+ *
+ *  Original Author:    Craig Hughes
+ *  Created:    Feb 14, 2008
+ *  Copyright:  Craig Hughes
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  Implemented based on lubbock.c by Nicolas Pitre and code from Craig
+ *  Hughes
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/udc.h>
+#include <asm/arch/gumstix.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
+
+#include "generic.h"
+
+static struct resource flash_resource = {
+        .start  = 0x00000000,
+        .end    = SZ_64M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct mtd_partition gumstix_partitions[] = {
+        {
+                .name =         "Bootloader",
+                .size =         0x00040000,
+                .offset =       0,
+                .mask_flags =   MTD_WRITEABLE  /* force read-only */
+        } , {
+                .name =         "rootfs",
+                .size =         MTDPART_SIZ_FULL,
+                .offset =       MTDPART_OFS_APPEND
+        }
+};
+
+static struct flash_platform_data gumstix_flash_data = {
+        .map_name       = "cfi_probe",
+        .parts          = gumstix_partitions,
+        .nr_parts       = ARRAY_SIZE(gumstix_partitions),
+        .width          = 2,
+};
+
+static struct platform_device gumstix_flash_device = {
+        .name           = "pxa2xx-flash",
+        .id             = 0,
+        .dev = {
+                .platform_data = &gumstix_flash_data,
+        },
+        .resource = &flash_resource,
+        .num_resources = 1,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &gumstix_flash_device,
+};
+
+#ifdef CONFIG_MMC_PXA
+static struct pxamci_platform_data gumstix_mci_platform_data;
+
+static int gumstix_mci_init(struct device *dev, irq_handler_t detect_int,
+                                void *data)
+{
+        pxa_gpio_mode(GPIO6_MMCCLK_MD);
+        pxa_gpio_mode(GPIO53_MMCCLK_MD);
+        pxa_gpio_mode(GPIO8_MMCCS0_MD);
+
+        return 0;
+}
+
+static struct pxamci_platform_data gumstix_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init           = gumstix_mci_init,
+};
+
+static void __init gumstix_mmc_init(void)
+{
+        pxa_set_mci_info(&gumstix_mci_platform_data);
+}
+#else
+static void __init gumstix_mmc_init(void)
+{
+        printk(KERN_INFO "Gumstix mmc disabled\n");
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET_PXA2XX
+static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = {
+        .gpio_vbus              = GPIO_GUMSTIX_USB_GPIOn,
+        .gpio_pullup            = GPIO_GUMSTIX_USB_GPIOx,
+};
+
+static void __init gumstix_udc_init(void)
+{
+        pxa_set_udc_info(&gumstix_udc_info);
+}
+#else
+static void gumstix_udc_init(void)
+{
+        printk(KERN_INFO "Gumstix udc is disabled\n");
+}
+#endif
+
+static void __init gumstix_init(void)
+{
+        gumstix_udc_init();
+        gumstix_mmc_init();
+        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+MACHINE_START(GUMSTIX, "Gumstix")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100, /* match u-boot bi_boot_params */
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = gumstix_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 0a9434432c55..2637633f9166 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -32,6 +32,7 @@
 #include <asm/mach/map.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/idp.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/bitfield.h>
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 36c6a68beca2..a9a0c3fab159 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mach-pxa/irq.c
  *
- *  Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
+ *  Generic PXA IRQ handling
  *
  *  Author:     Nicolas Pitre
  *  Created:    Jun 15, 2001
@@ -21,308 +21,58 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 #include "generic.h"
 
+#define IRQ_BIT(n)      (((n) - PXA_IRQ(0)) & 0x1f)
+#define _ICMR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
+#define _ICLR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
 
 /*
  * This is for peripheral IRQs internal to the PXA chip.
  */
 
-static void pxa_mask_low_irq(unsigned int irq)
+static int pxa_internal_irq_nr;
+
+static void pxa_mask_irq(unsigned int irq)
 {
-        ICMR &= ~(1 << irq);
+        _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
 }
 
-static void pxa_unmask_low_irq(unsigned int irq)
+static void pxa_unmask_irq(unsigned int irq)
 {
-        ICMR |= (1 << irq);
+        _ICMR(irq) |= 1 << IRQ_BIT(irq);
 }
 
-static struct irq_chip pxa_internal_chip_low = {
+static struct irq_chip pxa_internal_irq_chip = {
         .name           = "SC",
-        .ack            = pxa_mask_low_irq,
-        .mask           = pxa_mask_low_irq,
-        .unmask         = pxa_unmask_low_irq,
+        .ack            = pxa_mask_irq,
+        .mask           = pxa_mask_irq,
+        .unmask         = pxa_unmask_irq,
 };
 
-void __init pxa_init_irq_low(void)
+void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 {
         int irq;
 
-        /* disable all IRQs */
-        ICMR = 0;
+        pxa_internal_irq_nr = irq_nr;
 
-        /* all IRQs are IRQ, not FIQ */
-        ICLR = 0;
+        for (irq = 0; irq < irq_nr; irq += 32) {
+                _ICMR(irq) = 0; /* disable all IRQs */
+                _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
+        }
 
         /* only unmasked interrupts kick us out of idle */
         ICCR = 1;
 
-        for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
-                set_irq_chip(irq, &pxa_internal_chip_low);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-}
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-
-/*
- * This is for the second set of internal IRQs as found on the PXA27x.
- */
-
-static void pxa_mask_high_irq(unsigned int irq)
-{
-        ICMR2 &= ~(1 << (irq - 32));
-}
-
-static void pxa_unmask_high_irq(unsigned int irq)
-{
-        ICMR2 |= (1 << (irq - 32));
-}
-
-static struct irq_chip pxa_internal_chip_high = {
-        .name           = "SC-hi",
-        .ack            = pxa_mask_high_irq,
-        .mask           = pxa_mask_high_irq,
-        .unmask         = pxa_unmask_high_irq,
-};
-
-void __init pxa_init_irq_high(void)
-{
-        int irq;
-
-        ICMR2 = 0;
-        ICLR2 = 0;
-
-        for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
-                set_irq_chip(irq, &pxa_internal_chip_high);
+        for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
+                set_irq_chip(irq, &pxa_internal_irq_chip);
                 set_irq_handler(irq, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
-}
-#endif
-
-/*
- * PXA GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * Use this instead of directly setting GRER/GFER.
- */
-
-static long GPIO_IRQ_rising_edge[4];
-static long GPIO_IRQ_falling_edge[4];
-static long GPIO_IRQ_mask[4];
-
-static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-        int gpio, idx;
-
-        gpio = IRQ_TO_GPIO(irq);
-        idx = gpio >> 5;
-
-        if (type == IRQT_PROBE) {
-            /* Don't mess with enabled GPIOs using preconfigured edges or
-               GPIOs set to alternate function or to output during probe */
-                if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
-                    GPIO_bit(gpio))
-                        return 0;
-                if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
-                        return 0;
-                type = __IRQT_RISEDGE | __IRQT_FALEDGE;
-        }
-
-        /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
-
-        pxa_gpio_mode(gpio | GPIO_IN);
-
-        if (type & __IRQT_RISEDGE) {
-                /* printk("rising "); */
-                __set_bit (gpio, GPIO_IRQ_rising_edge);
-        } else {
-                __clear_bit (gpio, GPIO_IRQ_rising_edge);
-        }
-
-        if (type & __IRQT_FALEDGE) {
-                /* printk("falling "); */
-                __set_bit (gpio, GPIO_IRQ_falling_edge);
-        } else {
-                __clear_bit (gpio, GPIO_IRQ_falling_edge);
-        }
-
-        /* printk("edges\n"); */
-
-        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-        return 0;
-}
-
-/*
- * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
- */
-
-static void pxa_ack_low_gpio(unsigned int irq)
-{
-        GEDR0 = (1 << (irq - IRQ_GPIO0));
-}
-
-static struct irq_chip pxa_low_gpio_chip = {
-        .name           = "GPIO-l",
-        .ack            = pxa_ack_low_gpio,
-        .mask           = pxa_mask_low_irq,
-        .unmask         = pxa_unmask_low_irq,
-        .set_type       = pxa_gpio_irq_type,
-};
-
-/*
- * Demux handler for GPIO>=2 edge detect interrupts
- */
-
-static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int mask;
-        int loop;
-
-        do {
-                loop = 0;
-
-                mask = GEDR0 & GPIO_IRQ_mask[0] & ~3;
-                if (mask) {
-                        GEDR0 = mask;
-                        irq = IRQ_GPIO(2);
-                        desc = irq_desc + irq;
-                        mask >>= 2;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-
-                mask = GEDR1 & GPIO_IRQ_mask[1];
-                if (mask) {
-                        GEDR1 = mask;
-                        irq = IRQ_GPIO(32);
-                        desc = irq_desc + irq;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-
-                mask = GEDR2 & GPIO_IRQ_mask[2];
-                if (mask) {
-                        GEDR2 = mask;
-                        irq = IRQ_GPIO(64);
-                        desc = irq_desc + irq;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-
-                mask = GEDR3 & GPIO_IRQ_mask[3];
-                if (mask) {
-                        GEDR3 = mask;
-                        irq = IRQ_GPIO(96);
-                        desc = irq_desc + irq;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-        } while (loop);
-}
-
-static void pxa_ack_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        GEDR(gpio) = GPIO_bit(gpio);
-}
-
-static void pxa_mask_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        __clear_bit(gpio, GPIO_IRQ_mask);
-        GRER(gpio) &= ~GPIO_bit(gpio);
-        GFER(gpio) &= ~GPIO_bit(gpio);
-}
-
-static void pxa_unmask_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        int idx = gpio >> 5;
-        __set_bit(gpio, GPIO_IRQ_mask);
-        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-}
-
-static struct irq_chip pxa_muxed_gpio_chip = {
-        .name           = "GPIO",
-        .ack            = pxa_ack_muxed_gpio,
-        .mask           = pxa_mask_muxed_gpio,
-        .unmask         = pxa_unmask_muxed_gpio,
-        .set_type       = pxa_gpio_irq_type,
-};
-
-void __init pxa_init_irq_gpio(int gpio_nr)
-{
-        int irq, i;
-
-        pxa_last_gpio = gpio_nr - 1;
-
-        /* clear all GPIO edge detects */
-        for (i = 0; i < gpio_nr; i += 32) {
-                GFER(i) = 0;
-                GRER(i) = 0;
-                GEDR(i) = GEDR(i);
-        }
-
-        /* GPIO 0 and 1 must have their mask bit always set */
-        GPIO_IRQ_mask[0] = 3;
-
-        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
-                set_irq_chip(irq, &pxa_low_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
 
-        for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
-                set_irq_chip(irq, &pxa_muxed_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
-
-        /* Install handler for GPIO>=2 edge detect interrupts */
-        set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
-        set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
-
-        pxa_init_gpio(gpio_nr);
-}
-
-void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
-{
-        pxa_internal_chip_low.set_wake = set_wake;
-#ifdef CONFIG_PXA27x
-        pxa_internal_chip_high.set_wake = set_wake;
-#endif
-        pxa_low_gpio_chip.set_wake = set_wake;
-        pxa_muxed_gpio_chip.set_wake = set_wake;
+        pxa_internal_irq_chip.set_wake = fn;
 }
 
 #ifdef CONFIG_PM
@@ -330,19 +80,11 @@ static unsigned long saved_icmr[2];
 
 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 {
-        switch (dev->id) {
-        case 0:
-                saved_icmr[0] = ICMR;
-                ICMR = 0;
-                break;
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-        case 1:
-                saved_icmr[1] = ICMR2;
-                ICMR2 = 0;
-                break;
-#endif
-        default:
-                return -EINVAL;
+        int i, irq = PXA_IRQ(0);
+
+        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
+                saved_icmr[i] = _ICMR(irq);
+                _ICMR(irq) = 0;
         }
 
         return 0;
@@ -350,22 +92,14 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 
 static int pxa_irq_resume(struct sys_device *dev)
 {
-        switch (dev->id) {
-        case 0:
-                ICMR = saved_icmr[0];
-                ICLR = 0;
-                ICCR = 1;
-                break;
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-        case 1:
-                ICMR2 = saved_icmr[1];
-                ICLR2 = 0;
-                break;
-#endif
-        default:
-                return -EINVAL;
+        int i, irq = PXA_IRQ(0);
+
+        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
+                _ICMR(irq) = saved_icmr[i];
+                _ICLR(irq) = 0;
         }
 
+        ICCR = 1;
         return 0;
 }
 #else
diff --git a/arch/arm/mach-pxa/leds-trizeps4.c b/arch/arm/mach-pxa/leds-trizeps4.c
index 2271d20ffeda..21880daabafe 100644
--- a/arch/arm/mach-pxa/leds-trizeps4.c
+++ b/arch/arm/mach-pxa/leds-trizeps4.c
@@ -18,6 +18,7 @@
 #include <asm/leds.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/trizeps4.h>
 
 #include "leds.h"
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 0a4b54c21314..03396063b561 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -37,12 +37,11 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ssp.h>
+#include <asm/arch/pxa27x_keypad.h>
 #include <asm/arch/littleton.h>
 
 #include "generic.h"
 
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
-
 /* Littleton MFP configurations */
 static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
         /* LCD */
@@ -76,6 +75,21 @@ static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
 
         /* Debug Ethernet */
         GPIO90_GPIO,
+
+        /* Keypad */
+        GPIO107_KP_DKIN_0,
+        GPIO108_KP_DKIN_1,
+        GPIO115_KP_MKIN_0,
+        GPIO116_KP_MKIN_1,
+        GPIO117_KP_MKIN_2,
+        GPIO118_KP_MKIN_3,
+        GPIO119_KP_MKIN_4,
+        GPIO120_KP_MKIN_5,
+        GPIO121_KP_MKOUT_0,
+        GPIO122_KP_MKOUT_1,
+        GPIO123_KP_MKOUT_2,
+        GPIO124_KP_MKOUT_3,
+        GPIO125_KP_MKOUT_4,
 };
 
 static struct resource smc91x_resources[] = {
@@ -300,6 +314,54 @@ static void littleton_init_lcd(void)
 static inline void littleton_init_lcd(void) {};
 #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
 
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int littleton_matrix_key_map[] = {
+        /* KEY(row, col, key_code) */
+        KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
+        KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7),
+        KEY(1, 2, KEY_8), KEY(2, 2, KEY_9),
+
+        KEY(0, 3, KEY_KPASTERISK),      /* * */
+        KEY(2, 3, KEY_KPDOT),           /* # */
+
+        KEY(5, 4, KEY_ENTER),
+
+        KEY(5, 0, KEY_UP),
+        KEY(5, 1, KEY_DOWN),
+        KEY(5, 2, KEY_LEFT),
+        KEY(5, 3, KEY_RIGHT),
+        KEY(3, 2, KEY_HOME),
+        KEY(4, 1, KEY_END),
+        KEY(3, 3, KEY_BACK),
+
+        KEY(4, 0, KEY_SEND),
+        KEY(4, 2, KEY_VOLUMEUP),
+        KEY(4, 3, KEY_VOLUMEDOWN),
+
+        KEY(3, 0, KEY_F22),     /* soft1 */
+        KEY(3, 1, KEY_F23),     /* soft2 */
+};
+
+static struct pxa27x_keypad_platform_data littleton_keypad_info = {
+        .matrix_key_rows        = 6,
+        .matrix_key_cols        = 5,
+        .matrix_key_map         = littleton_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(littleton_matrix_key_map),
+
+        .enable_rotary0         = 1,
+        .rotary0_up_key         = KEY_UP,
+        .rotary0_down_key       = KEY_DOWN,
+
+        .debounce_interval      = 30,
+};
+static void __init littleton_init_keypad(void)
+{
+        pxa_set_keypad_info(&littleton_keypad_info);
+}
+#else
+static inline void littleton_init_keypad(void) {}
+#endif
+
 static void __init littleton_init(void)
 {
         /* initialize MFP configurations */
@@ -312,6 +374,7 @@ static void __init littleton_init(void)
         platform_device_register(&smc91x_device);
 
         littleton_init_lcd();
+        littleton_init_keypad();
 }
 
 MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index afa62ffe3ad5..a20e4b1649d6 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -39,6 +39,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/lpd270.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index e7ae4bb3e361..ca209c443f34 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -42,6 +42,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/lubbock.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/irda.h>
@@ -51,6 +52,40 @@
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long lubbock_pin_config[] __initdata = {
+        GPIO15_nCS_1,   /* CS1 - Flash */
+        GPIO79_nCS_3,   /* CS3 - SMC ethernet */
+
+        /* SSP data pins */
+        GPIO23_SSP1_SCLK,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO8_MMC_CS0,
+
+        /* wakeup */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
+};
 
 #define LUB_MISC_WR             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
 
@@ -186,26 +221,6 @@ static struct platform_device sa1111_device = {
         .resource       = sa1111_resources,
 };
 
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .name   = "smc91x-regs",
-                .start  = 0x0c000c00,
-                .end    = 0x0c0fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = LUBBOCK_ETH_IRQ,
-                .end    = LUBBOCK_ETH_IRQ,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
-        },
-        [2] = {
-                .name   = "smc91x-attrib",
-                .start  = 0x0e000000,
-                .end    = 0x0e0fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
 /* ADS7846 is connected through SSP ... and if your board has J5 populated,
  * you can select it to replace the ucb1400 by switching the touchscreen cable
  * (to J5) and poking board registers (as done below).  Else it's only useful
@@ -261,6 +276,26 @@ static struct spi_board_info spi_board_info[] __initdata = { {
 },
 };
 
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .name   = "smc91x-regs",
+                .start  = 0x0c000c00,
+                .end    = 0x0c0fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = LUBBOCK_ETH_IRQ,
+                .end    = LUBBOCK_ETH_IRQ,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+        [2] = {
+                .name   = "smc91x-attrib",
+                .start  = 0x0e000000,
+                .end    = 0x0e0fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
@@ -404,10 +439,6 @@ static int lubbock_mci_init(struct device *dev,
                 irq_handler_t detect_int,
                 void *data)
 {
-        /* setup GPIO for PXA25x MMC controller */
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-
         /* detect card insert/eject */
         mmc_detect_int = detect_int;
         init_timer(&mmc_timer);
@@ -457,6 +488,8 @@ static void __init lubbock_init(void)
 {
         int flashboot = (LUB_CONF_SWITCHES & 1);
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));
+
         pxa_set_udc_info(&udc_info);
         set_pxa_fb_info(&sharp_lm8v31);
         pxa_set_mci_info(&lubbock_mci_platform_data);
@@ -489,46 +522,6 @@ static void __init lubbock_map_io(void)
         pxa_map_io();
         iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
 
-        /* SSP data pins */
-        pxa_gpio_mode(GPIO23_SCLK_MD);
-        pxa_gpio_mode(GPIO25_STXD_MD);
-        pxa_gpio_mode(GPIO26_SRXD_MD);
-
-        /* This enables the BTUART */
-        pxa_gpio_mode(GPIO42_BTRXD_MD);
-        pxa_gpio_mode(GPIO43_BTTXD_MD);
-        pxa_gpio_mode(GPIO44_BTCTS_MD);
-        pxa_gpio_mode(GPIO45_BTRTS_MD);
-
-        GPSR(GPIO48_nPOE) =
-                GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) |
-                GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) |
-                GPIO_bit(GPIO52_nPCE_1) |
-                GPIO_bit(GPIO53_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO52_nPCE_1_MD);
-        pxa_gpio_mode(GPIO53_nPCE_2_MD);
-        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-
-        /* This is for the SMC chip select */
-        pxa_gpio_mode(GPIO79_nCS_3_MD);
-
-        /* setup sleep mode values */
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x00008000;
-        PGSR1 = 0x003F0202;
-        PGSR2 = 0x0001C000;
         PCFR |= PCFR_OPDE;
 }
 
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index d98ef7ada2f8..d70be75bd199 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -16,24 +16,106 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/mfd/htc-egpio.h>
+#include <linux/mfd/htc-pasic3.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include <linux/pda_power.h>
 
 #include <asm/gpio.h>
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/arch/magician.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxafb.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/ohci.h>
 
 #include "generic.h"
 
+static unsigned long magician_pin_config[] = {
+
+        /* SDRAM and Static Memory I/O Signals */
+        GPIO20_nSDCS_2,
+        GPIO21_nSDCS_3,
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,   /* PASIC3 */
+        GPIO79_nCS_3,   /* EGPIO CPLD */
+        GPIO80_nCS_4,
+        GPIO33_nCS_5,
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+
+        /* PWM 0 */
+        GPIO16_PWM0_OUT,
+
+        /* I2S */
+        GPIO28_I2S_BITCLK_OUT,
+        GPIO29_I2S_SDATA_IN,
+        GPIO31_I2S_SYNC,
+        GPIO113_I2S_SYSCLK,
+
+        /* SSP 2 */
+        GPIO19_SSP2_SCLK,
+        GPIO14_SSP2_SFRM,
+        GPIO89_SSP2_TXD,
+        GPIO88_SSP2_RXD,
+
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* QCI */
+        GPIO12_CIF_DD_7,
+        GPIO17_CIF_DD_6,
+        GPIO50_CIF_DD_3,
+        GPIO51_CIF_DD_2,
+        GPIO52_CIF_DD_4,
+        GPIO53_CIF_MCLK,
+        GPIO54_CIF_PCLK,
+        GPIO55_CIF_DD_1,
+        GPIO81_CIF_DD_0,
+        GPIO82_CIF_DD_5,
+        GPIO84_CIF_FV,
+        GPIO85_CIF_LV,
+};
+
 /*
  * IRDA
  */
@@ -83,8 +165,64 @@ static struct platform_device gpio_keys = {
         .id   = -1,
 };
 
+
+/*
+ * EGPIO (Xilinx CPLD)
+ *
+ * 7 32-bit aligned 8-bit registers: 3x output, 1x irq, 3x input
+ */
+
+static struct resource egpio_resources[] = {
+        [0] = {
+                .start = PXA_CS3_PHYS,
+                .end   = PXA_CS3_PHYS + 0x20,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+                .end   = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct htc_egpio_chip egpio_chips[] = {
+        [0] = {
+                .reg_start = 0,
+                .gpio_base = MAGICIAN_EGPIO(0, 0),
+                .num_gpios = 24,
+                .direction = HTC_EGPIO_OUTPUT,
+                .initial_values = 0x40, /* EGPIO_MAGICIAN_GSM_RESET */
+        },
+        [1] = {
+                .reg_start = 4,
+                .gpio_base = MAGICIAN_EGPIO(4, 0),
+                .num_gpios = 24,
+                .direction = HTC_EGPIO_INPUT,
+        },
+};
+
+static struct htc_egpio_platform_data egpio_info = {
+        .reg_width    = 8,
+        .bus_width    = 32,
+        .irq_base     = IRQ_BOARD_START,
+        .num_irqs     = 4,
+        .ack_register = 3,
+        .chip         = egpio_chips,
+        .num_chips    = ARRAY_SIZE(egpio_chips),
+};
+
+static struct platform_device egpio = {
+        .name          = "htc-egpio",
+        .id            = -1,
+        .resource      = egpio_resources,
+        .num_resources = ARRAY_SIZE(egpio_resources),
+        .dev = {
+                .platform_data = &egpio_info,
+        },
+};
+
 /*
- * LCD - Toppoly TD028STEB1
+ * LCD - Toppoly TD028STEB1 or Samsung LTP280QV
  */
 
 static struct pxafb_mode_info toppoly_modes[] = {
@@ -103,12 +241,99 @@ static struct pxafb_mode_info toppoly_modes[] = {
         },
 };
 
+static struct pxafb_mode_info samsung_modes[] = {
+        {
+                .pixclock     = 96153,
+                .bpp          = 16,
+                .xres         = 240,
+                .yres         = 320,
+                .hsync_len    = 8,
+                .vsync_len    = 4,
+                .left_margin  = 9,
+                .upper_margin = 4,
+                .right_margin = 9,
+                .lower_margin = 4,
+                .sync         = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+        },
+};
+
+static void toppoly_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+        pr_debug("Toppoly LCD power\n");
+
+        if (on) {
+                pr_debug("on\n");
+                gpio_set_value(EGPIO_MAGICIAN_TOPPOLY_POWER, 1);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1);
+                udelay(2000);
+                gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
+                udelay(2000);
+                /* FIXME: enable LCDC here */
+                udelay(2000);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1);
+                udelay(2000);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1);
+        } else {
+                pr_debug("off\n");
+                msleep(15);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0);
+                udelay(500);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0);
+                udelay(1000);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0);
+                gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
+        }
+}
+
+static void samsung_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+        pr_debug("Samsung LCD power\n");
+
+        if (on) {
+                pr_debug("on\n");
+                if (system_rev < 3)
+                        gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 1);
+                else
+                        gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
+                mdelay(10);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1);
+                mdelay(10);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1);
+                mdelay(30);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1);
+                mdelay(10);
+        } else {
+                pr_debug("off\n");
+                mdelay(10);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0);
+                mdelay(30);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0);
+                mdelay(10);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0);
+                mdelay(10);
+                if (system_rev < 3)
+                        gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 0);
+                else
+                        gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
+        }
+}
+
 static struct pxafb_mach_info toppoly_info = {
-        .modes       = toppoly_modes,
-        .num_modes   = 1,
-        .fixed_modes = 1,
-        .lccr0       = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
-        .lccr3       = LCCR3_PixRsEdg,
+        .modes           = toppoly_modes,
+        .num_modes       = 1,
+        .fixed_modes     = 1,
+        .lccr0           = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3           = LCCR3_PixRsEdg,
+        .pxafb_lcd_power = toppoly_lcd_power,
+};
+
+static struct pxafb_mach_info samsung_info = {
+        .modes           = samsung_modes,
+        .num_modes       = 1,
+        .fixed_modes     = 1,
+        .lccr0           = LCCR0_LDDALT | LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3           = LCCR3_PixFlEdg,
+        .pxafb_lcd_power = samsung_lcd_power,
 };
 
 /*
@@ -120,9 +345,18 @@ static void magician_set_bl_intensity(int intensity)
         if (intensity) {
                 PWM_CTRL0 = 1;
                 PWM_PERVAL0 = 0xc8;
-                PWM_PWDUTY0 = intensity;
+                if (intensity > 0xc7) {
+                        PWM_PWDUTY0 = intensity - 0x48;
+                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
+                } else {
+                        PWM_PWDUTY0 = intensity;
+                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
+                }
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1);
                 pxa_set_cken(CKEN_PWM0, 1);
         } else {
+                /* PWM_PWDUTY0 = intensity; */
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0);
                 pxa_set_cken(CKEN_PWM0, 0);
         }
 }
@@ -130,18 +364,215 @@ static void magician_set_bl_intensity(int intensity)
 static struct generic_bl_info backlight_info = {
         .default_intensity = 0x64,
         .limit_mask        = 0x0b,
-        .max_intensity     = 0xc7,
+        .max_intensity     = 0xc7+0x48,
         .set_bl_intensity  = magician_set_bl_intensity,
 };
 
 static struct platform_device backlight = {
-        .name = "corgi-bl",
+        .name = "generic-bl",
         .dev  = {
                 .platform_data = &backlight_info,
         },
         .id   = -1,
 };
 
+/*
+ * LEDs
+ */
+
+struct gpio_led gpio_leds[] = {
+        {
+                .name = "magician::vibra",
+                .default_trigger = "none",
+                .gpio = GPIO22_MAGICIAN_VIBRA_EN,
+        },
+        {
+                .name = "magician::phone_bl",
+                .default_trigger = "none",
+                .gpio = GPIO103_MAGICIAN_LED_KP,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds = gpio_leds,
+        .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name = "leds-gpio",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &gpio_led_info,
+        },
+};
+
+static struct pasic3_led pasic3_leds[] = {
+        {
+                .led = {
+                        .name            = "magician:red",
+                        .default_trigger = "ds2760-battery.0-charging",
+                },
+                .hw_num = 0,
+                .bit2   = PASIC3_BIT2_LED0,
+                .mask   = PASIC3_MASK_LED0,
+        },
+        {
+                .led = {
+                        .name            = "magician:green",
+                        .default_trigger = "ds2760-battery.0-charging-or-full",
+                },
+                .hw_num = 1,
+                .bit2   = PASIC3_BIT2_LED1,
+                .mask   = PASIC3_MASK_LED1,
+        },
+        {
+                .led = {
+                        .name            = "magician:blue",
+                        .default_trigger = "bluetooth",
+                },
+                .hw_num = 2,
+                .bit2   = PASIC3_BIT2_LED2,
+                .mask   = PASIC3_MASK_LED2,
+        },
+};
+
+static struct platform_device pasic3;
+
+static struct pasic3_leds_machinfo __devinit pasic3_leds_info = {
+        .num_leds   = ARRAY_SIZE(pasic3_leds),
+        .power_gpio = EGPIO_MAGICIAN_LED_POWER,
+        .leds       = pasic3_leds,
+};
+
+/*
+ * PASIC3 with DS1WM
+ */
+
+static struct resource pasic3_resources[] = {
+        [0] = {
+                .start  = PXA_CS2_PHYS,
+                .end    = PXA_CS2_PHYS + 0x1b,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */
+        [1] = {
+                .start  = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .end    = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct pasic3_platform_data pasic3_platform_data = {
+        .bus_shift  = 2,
+        .led_pdata  = &pasic3_leds_info,
+        .clock_rate = 4000000,
+};
+
+static struct platform_device pasic3 = {
+        .name           = "pasic3",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pasic3_resources),
+        .resource       = pasic3_resources,
+        .dev = {
+                .platform_data = &pasic3_platform_data,
+        },
+};
+
+/*
+ * External power
+ */
+
+static int magician_is_ac_online(void)
+{
+        return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_AC);
+}
+
+static int magician_is_usb_online(void)
+{
+        return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_USB);
+}
+
+static void magician_set_charge(int flags)
+{
+        gpio_set_value(GPIO30_MAGICIAN_nCHARGE_EN, !flags);
+        gpio_set_value(EGPIO_MAGICIAN_CHARGE_EN, flags);
+}
+
+static char *magician_supplicants[] = {
+        "ds2760-battery.0", "backup-battery"
+};
+
+static struct pda_power_pdata power_supply_info = {
+        .is_ac_online    = magician_is_ac_online,
+        .is_usb_online   = magician_is_usb_online,
+        .set_charge      = magician_set_charge,
+        .supplied_to     = magician_supplicants,
+        .num_supplicants = ARRAY_SIZE(magician_supplicants),
+};
+
+static struct resource power_supply_resources[] = {
+        [0] = {
+                .name  = "ac",
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAGICIAN_AC,
+                .end   = IRQ_MAGICIAN_AC,
+        },
+        [1] = {
+                .name  = "usb",
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAGICIAN_AC,
+                .end   = IRQ_MAGICIAN_AC,
+        },
+};
+
+static struct platform_device power_supply = {
+        .name = "pda-power",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &power_supply_info,
+        },
+        .resource      = power_supply_resources,
+        .num_resources = ARRAY_SIZE(power_supply_resources),
+};
+
+
+/*
+ * MMC/SD
+ */
+
+static int magician_mci_init(struct device *dev,
+                                irq_handler_t detect_irq, void *data)
+{
+        return request_irq(IRQ_MAGICIAN_SD, detect_irq,
+                                IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+                                "MMC card detect", data);
+}
+
+static void magician_mci_setpower(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *pdata = dev->platform_data;
+
+        gpio_set_value(EGPIO_MAGICIAN_SD_POWER, (1 << vdd) & pdata->ocr_mask);
+}
+
+static int magician_mci_get_ro(struct device *dev)
+{
+        return (!gpio_get_value(EGPIO_MAGICIAN_nSD_READONLY));
+}
+
+static void magician_mci_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_MAGICIAN_SD, data);
+}
+
+static struct pxamci_platform_data magician_mci_info = {
+        .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init     = magician_mci_init,
+        .get_ro   = magician_mci_get_ro,
+        .setpower = magician_mci_setpower,
+        .exit     = magician_mci_exit,
+};
+
 
 /*
  * USB OHCI
@@ -166,6 +597,11 @@ static struct pxaohci_platform_data magician_ohci_info = {
  * StrataFlash
  */
 
+static void magician_set_vpp(struct map_info *map, int vpp)
+{
+        gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
+}
+
 #define PXA_CS_SIZE             0x04000000
 
 static struct resource strataflash_resource = {
@@ -176,13 +612,14 @@ static struct resource strataflash_resource = {
 
 static struct physmap_flash_data strataflash_data = {
         .width = 4,
+        .set_vpp = magician_set_vpp,
 };
 
 static struct platform_device strataflash = {
         .name          = "physmap-flash",
         .id            = -1,
-        .num_resources = 1,
         .resource      = &strataflash_resource,
+        .num_resources = 1,
         .dev = {
                 .platform_data = &strataflash_data,
         },
@@ -194,16 +631,43 @@ static struct platform_device strataflash = {
 
 static struct platform_device *devices[] __initdata = {
         &gpio_keys,
+        &egpio,
         &backlight,
+        &pasic3,
+        &power_supply,
         &strataflash,
+        &leds_gpio,
 };
 
 static void __init magician_init(void)
 {
+        void __iomem *cpld;
+        int lcd_select;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
+
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        pxa_set_i2c_info(NULL);
+        pxa_set_mci_info(&magician_mci_info);
         pxa_set_ohci_info(&magician_ohci_info);
         pxa_set_ficp_info(&magician_ficp_info);
-        set_pxa_fb_info(&toppoly_info);
+
+        /* Check LCD type we have */
+        cpld = ioremap_nocache(PXA_CS3_PHYS, 0x1000);
+        if (cpld) {
+                u8 board_id = __raw_readb(cpld+0x14);
+                system_rev = board_id & 0x7;
+                lcd_select = board_id & 0x8;
+                iounmap(cpld);
+                pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly");
+                if (lcd_select && (system_rev < 3))
+                        pxa_gpio_mode(GPIO75_MAGICIAN_SAMSUNG_POWER_MD);
+                pxa_gpio_mode(GPIO104_MAGICIAN_LCD_POWER_1_MD);
+                pxa_gpio_mode(GPIO105_MAGICIAN_LCD_POWER_2_MD);
+                pxa_gpio_mode(GPIO106_MAGICIAN_LCD_POWER_3_MD);
+                set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info);
+        } else
+                pr_err("LCD detection: CPLD mapping failed\n");
 }
 
 
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 72a436fb9a29..18d47cfa2a18 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -24,6 +24,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/backlight.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -40,16 +42,94 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/mainstone.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
+#include <asm/arch/i2c.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/ohci.h>
+#include <asm/arch/pxa27x_keypad.h>
 
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long mainstone_pin_config[] = {
+        /* Chip Select */
+        GPIO15_nCS_1,
+
+        /* LCD - 16bpp Active TFT */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+        GPIO16_PWM0_OUT,        /* Backlight */
+
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO112_MMC_CMD,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+
+        /* USB Host Port 1 */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* AC97 */
+        GPIO45_AC97_SYSCLK,
+
+        /* Keypad */
+        GPIO93_KP_DKIN_0        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO94_KP_DKIN_1        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO95_KP_DKIN_2        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO100_KP_MKIN_0       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_MKIN_4        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO99_KP_MKIN_5        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
+        GPIO96_KP_MKOUT_6,
+
+        /* GPIO */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
+};
 
 static unsigned long mainstone_irq_enabled;
 
@@ -278,13 +358,13 @@ static int mainstone_backlight_update_status(struct backlight_device *bl)
             bl->props.fb_blank != FB_BLANK_UNBLANK)
                 brightness = 0;
 
-        if (brightness != 0) {
-                pxa_gpio_mode(GPIO16_PWM0_MD);
+        if (brightness != 0)
                 pxa_set_cken(CKEN_PWM0, 1);
-        }
+
         PWM_CTRL0 = 0;
         PWM_PWDUTY0 = brightness;
         PWM_PERVAL0 = bl->props.max_brightness;
+
         if (brightness == 0)
                 pxa_set_cken(CKEN_PWM0, 0);
         return 0; /* pointless return value */
@@ -362,16 +442,6 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
 {
         int err;
 
-        /*
-         * setup GPIO for PXA27x MMC controller
-         */
-        pxa_gpio_mode(GPIO32_MMCCLK_MD);
-        pxa_gpio_mode(GPIO112_MMCCMD_MD);
-        pxa_gpio_mode(GPIO92_MMCDAT0_MD);
-        pxa_gpio_mode(GPIO109_MMCDAT1_MD);
-        pxa_gpio_mode(GPIO110_MMCDAT2_MD);
-        pxa_gpio_mode(GPIO111_MMCDAT3_MD);
-
         /* make sure SD/Memory Stick multiplexer's signals
          * are routed to MMC controller
          */
@@ -434,19 +504,39 @@ static struct pxaficp_platform_data mainstone_ficp_platform_data = {
         .transceiver_mode = mainstone_irda_transceiver_mode,
 };
 
+static struct gpio_keys_button gpio_keys_button[] = {
+        [0] = {
+                .desc   = "wakeup",
+                .code   = KEY_SUSPEND,
+                .type   = EV_KEY,
+                .gpio   = 1,
+                .wakeup = 1,
+        },
+};
+
+static struct gpio_keys_platform_data mainstone_gpio_keys = {
+        .buttons        = gpio_keys_button,
+        .nbuttons       = 1,
+};
+
+static struct platform_device mst_gpio_keys_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &mainstone_gpio_keys,
+        },
+};
+
 static struct platform_device *platform_devices[] __initdata = {
         &smc91x_device,
         &mst_audio_device,
         &mst_flash_device[0],
         &mst_flash_device[1],
+        &mst_gpio_keys_device,
 };
 
 static int mainstone_ohci_init(struct device *dev)
 {
-        /* setup Port1 GPIO pin. */
-        pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);  /* USBHPWR1 */
-        pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
-
         /* Set the Power Control Polarity Low and Power Sense
            Polarity Low to active low. */
         UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
@@ -460,10 +550,63 @@ static struct pxaohci_platform_data mainstone_ohci_platform_data = {
         .init           = mainstone_ohci_init,
 };
 
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int mainstone_matrix_keys[] = {
+        KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
+        KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
+        KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
+        KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L),
+        KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O),
+        KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R),
+        KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U),
+        KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X),
+        KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z),
+
+        KEY(0, 4, KEY_DOT),     /* . */
+        KEY(1, 4, KEY_CLOSE),   /* @ */
+        KEY(4, 4, KEY_SLASH),
+        KEY(5, 4, KEY_BACKSLASH),
+        KEY(0, 5, KEY_HOME),
+        KEY(1, 5, KEY_LEFTSHIFT),
+        KEY(2, 5, KEY_SPACE),
+        KEY(3, 5, KEY_SPACE),
+        KEY(4, 5, KEY_ENTER),
+        KEY(5, 5, KEY_BACKSPACE),
+
+        KEY(0, 6, KEY_UP),
+        KEY(1, 6, KEY_DOWN),
+        KEY(2, 6, KEY_LEFT),
+        KEY(3, 6, KEY_RIGHT),
+        KEY(4, 6, KEY_SELECT),
+};
+
+struct pxa27x_keypad_platform_data mainstone_keypad_info = {
+        .matrix_key_rows        = 6,
+        .matrix_key_cols        = 7,
+        .matrix_key_map         = mainstone_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(mainstone_matrix_keys),
+
+        .enable_rotary0         = 1,
+        .rotary0_up_key         = KEY_UP,
+        .rotary0_down_key       = KEY_DOWN,
+
+        .debounce_interval      = 30,
+};
+
+static void __init mainstone_init_keypad(void)
+{
+        pxa_set_keypad_info(&mainstone_keypad_info);
+}
+#else
+static inline void mainstone_init_keypad(void) {}
+#endif
+
 static void __init mainstone_init(void)
 {
         int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
+
         mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
         mst_flash_data[1].width = 4;
 
@@ -480,31 +623,6 @@ static void __init mainstone_init(void)
          */
         ARB_CNTRL = ARB_CORE_PARK | 0x234;
 
-        /*
-         * On Mainstone, we route AC97_SYSCLK via GPIO45 to
-         * the audio daughter card
-         */
-        pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
-
-        GPSR(GPIO48_nPOE) =
-                GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) |
-                GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) |
-                GPIO_bit(GPIO85_nPCE_1) |
-                GPIO_bit(GPIO54_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO85_nPCE_1_MD);
-        pxa_gpio_mode(GPIO54_nPCE_2_MD);
-        pxa_gpio_mode(GPIO79_pSKTSEL_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
         /* reading Mainstone's "Virtual Configuration Register"
@@ -520,6 +638,9 @@ static void __init mainstone_init(void)
         pxa_set_mci_info(&mainstone_mci_platform_data);
         pxa_set_ficp_info(&mainstone_ficp_platform_data);
         pxa_set_ohci_info(&mainstone_ohci_platform_data);
+        pxa_set_i2c_info(NULL);
+
+        mainstone_init_keypad();
 }
 
 
@@ -537,23 +658,9 @@ static void __init mainstone_map_io(void)
         pxa_map_io();
         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
 
-        /* initialize sleep mode regs (wake-up sources, etc) */
-        PGSR0 = 0x00008800;
-        PGSR1 = 0x00000002;
-        PGSR2 = 0x0001FC00;
-        PGSR3 = 0x00001F81;
-        PWER  = 0xC0000002;
-        PRER  = 0x00000002;
-        PFER  = 0x00000002;
         /*      for use I SRAM as framebuffer.  */
         PSLR |= 0xF04;
         PCFR = 0x66;
-        /*      For Keypad wakeup.      */
-        KPC &=~KPC_ASACT;
-        KPC |=KPC_AS;
-        PKWR  = 0x000FD000;
-        /*      Need read PKWR back after set it.       */
-        PKWR;
 }
 
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
new file mode 100644
index 000000000000..22097a1707cc
--- /dev/null
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -0,0 +1,245 @@
+/*
+ *  linux/arch/arm/mach-pxa/mfp-pxa2xx.c
+ *
+ *  PXA2xx pin mux configuration support
+ *
+ *  The GPIOs on PXA2xx can be configured as one of many alternate
+ *  functions, this is by concept samilar to the MFP configuration
+ *  on PXA3xx,  what's more important, the low power pin state and
+ *  wakeup detection are also supported by the same framework.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/mfp-pxa2xx.h>
+
+#include "generic.h"
+
+#define PGSR(x)         __REG2(0x40F00020, ((x) & 0x60) >> 3)
+
+#define PWER_WE35       (1 << 24)
+
+struct gpio_desc {
+        unsigned        valid           : 1;
+        unsigned        can_wakeup      : 1;
+        unsigned        keypad_gpio     : 1;
+        unsigned int    mask; /* bit mask in PWER or PKWR */
+        unsigned long   config;
+};
+
+static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
+
+static int __mfp_config_gpio(unsigned gpio, unsigned long c)
+{
+        unsigned long gafr, mask = GPIO_bit(gpio);
+        int fn;
+
+        fn = MFP_AF(c);
+        if (fn > 3)
+                return -EINVAL;
+
+        /* alternate function and direction */
+        gafr = GAFR(gpio) & ~(0x3 << ((gpio & 0xf) * 2));
+        GAFR(gpio) = gafr |  (fn  << ((gpio & 0xf) * 2));
+
+        if (c & MFP_DIR_OUT)
+                GPDR(gpio) |= mask;
+        else
+                GPDR(gpio) &= ~mask;
+
+        /* low power state */
+        switch (c & MFP_LPM_STATE_MASK) {
+        case MFP_LPM_DRIVE_HIGH:
+                PGSR(gpio) |= mask;
+                break;
+        case MFP_LPM_DRIVE_LOW:
+                PGSR(gpio) &= ~mask;
+                break;
+        case MFP_LPM_INPUT:
+                break;
+        default:
+                pr_warning("%s: invalid low power state for GPIO%d\n",
+                                __func__, gpio);
+                return -EINVAL;
+        }
+
+        /* give early warning if MFP_LPM_CAN_WAKEUP is set on the
+         * configurations of those pins not able to wakeup
+         */
+        if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
+                pr_warning("%s: GPIO%d unable to wakeup\n",
+                                __func__, gpio);
+                return -EINVAL;
+        }
+
+        if ((c & MFP_LPM_CAN_WAKEUP) && (c & MFP_DIR_OUT)) {
+                pr_warning("%s: output GPIO%d unable to wakeup\n",
+                                __func__, gpio);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
+{
+        unsigned long flags;
+        unsigned long *c;
+        int i, gpio;
+
+        for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
+
+                gpio = mfp_to_gpio(MFP_PIN(*c));
+
+                if (!gpio_desc[gpio].valid) {
+                        pr_warning("%s: GPIO%d is invalid pin\n",
+                                __func__, gpio);
+                        continue;
+                }
+
+                local_irq_save(flags);
+
+                gpio_desc[gpio].config = *c;
+                __mfp_config_gpio(gpio, *c);
+
+                local_irq_restore(flags);
+        }
+}
+
+int gpio_set_wake(unsigned int gpio, unsigned int on)
+{
+        struct gpio_desc *d;
+        unsigned long c;
+
+        if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
+                return -EINVAL;
+
+        d = &gpio_desc[gpio];
+        c = d->config;
+
+        if (!d->valid)
+                return -EINVAL;
+
+        if (d->keypad_gpio)
+                return -EINVAL;
+
+        if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
+                if (on) {
+                        PWER |= d->mask;
+
+                        if (c & MFP_LPM_EDGE_RISE)
+                                PRER |= d->mask;
+                        else
+                                PRER &= ~d->mask;
+
+                        if (c & MFP_LPM_EDGE_FALL)
+                                PFER |= d->mask;
+                        else
+                                PFER &= ~d->mask;
+                } else {
+                        PWER &= ~d->mask;
+                        PRER &= ~d->mask;
+                        PFER &= ~d->mask;
+                }
+        }
+        return 0;
+}
+
+#ifdef CONFIG_PXA25x
+static int __init pxa25x_mfp_init(void)
+{
+        int i;
+
+        if (cpu_is_pxa25x()) {
+                for (i = 0; i <= 84; i++)
+                        gpio_desc[i].valid = 1;
+
+                for (i = 0; i <= 15; i++) {
+                        gpio_desc[i].can_wakeup = 1;
+                        gpio_desc[i].mask = GPIO_bit(i);
+                }
+        }
+
+        return 0;
+}
+postcore_initcall(pxa25x_mfp_init);
+#endif /* CONFIG_PXA25x */
+
+#ifdef CONFIG_PXA27x
+static int pxa27x_pkwr_gpio[] = {
+        13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94,
+        95, 96, 97, 98, 99, 100, 101, 102
+};
+
+int keypad_set_wake(unsigned int on)
+{
+        unsigned int i, gpio, mask = 0;
+
+        if (!on) {
+                PKWR = 0;
+                return 0;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
+
+                gpio = pxa27x_pkwr_gpio[i];
+
+                if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP)
+                        mask |= gpio_desc[gpio].mask;
+        }
+
+        PKWR = mask;
+        return 0;
+}
+
+static int __init pxa27x_mfp_init(void)
+{
+        int i, gpio;
+
+        if (cpu_is_pxa27x()) {
+                for (i = 0; i <= 120; i++) {
+                        /* skip GPIO2, 5, 6, 7, 8, they are not
+                         * valid pins allow configuration
+                         */
+                        if (i == 2 || i == 5 || i == 6 ||
+                            i == 7 || i == 8)
+                                continue;
+
+                        gpio_desc[i].valid = 1;
+                }
+
+                /* Keypad GPIOs */
+                for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
+                        gpio = pxa27x_pkwr_gpio[i];
+                        gpio_desc[gpio].can_wakeup = 1;
+                        gpio_desc[gpio].keypad_gpio = 1;
+                        gpio_desc[gpio].mask = 1 << i;
+                }
+
+                /* Overwrite GPIO13 as a PWER wakeup source */
+                for (i = 0; i <= 15; i++) {
+                        /* skip GPIO2, 5, 6, 7, 8 */
+                        if (GPIO_bit(i) & 0x1e4)
+                                continue;
+
+                        gpio_desc[i].can_wakeup = 1;
+                        gpio_desc[i].mask = GPIO_bit(i);
+                }
+
+                gpio_desc[35].can_wakeup = 1;
+                gpio_desc[35].mask = PWER_WE35;
+        }
+
+        return 0;
+}
+postcore_initcall(pxa27x_mfp_init);
+#endif /* CONFIG_PXA27x */
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp-pxa3xx.c
index f5809adce298..b84c3ba7a8d6 100644
--- a/arch/arm/mach-pxa/mfp.c
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c
@@ -234,22 +234,22 @@ static int pxa3xx_mfp_resume(struct sys_device *d)
 
         return 0;
 }
+#else
+#define pxa3xx_mfp_suspend      NULL
+#define pxa3xx_mfp_resume       NULL
+#endif
 
-static struct sysdev_class mfp_sysclass = {
+struct sysdev_class pxa3xx_mfp_sysclass = {
         .name           = "mfp",
         .suspend        = pxa3xx_mfp_suspend,
         .resume         = pxa3xx_mfp_resume,
 };
 
-static struct sys_device mfp_device = {
-        .id             = 0,
-        .cls            = &mfp_sysclass,
-};
-
 static int __init mfp_init_devicefs(void)
 {
-        sysdev_class_register(&mfp_sysclass);
-        return sysdev_register(&mfp_device);
+        if (cpu_is_pxa3xx())
+                return sysdev_class_register(&pxa3xx_mfp_sysclass);
+
+        return 0;
 }
-device_initcall(mfp_init_devicefs);
-#endif
+postcore_initcall(mfp_init_devicefs);
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index c14696b9979d..3b945eb0aee3 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -29,6 +29,7 @@
 #include <asm/mach/arch.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx_spi.h>
 #include <asm/arch/pcm027.h>
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 3dda16a20049..e6be9d0aeccf 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -23,8 +23,16 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/ide.h>
+#include <linux/i2c.h>
+
+#include <media/soc_camera.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/camera.h>
 #include <asm/mach/map.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pcm990_baseboard.h>
@@ -258,6 +266,76 @@ static struct pxaohci_platform_data pcm990_ohci_platform_data = {
 };
 
 /*
+ * PXA27x Camera specific stuff
+ */
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+static int pcm990_pxacamera_init(struct device *dev)
+{
+        pxa_gpio_mode(GPIO98_CIF_DD_0_MD);
+        pxa_gpio_mode(GPIO105_CIF_DD_1_MD);
+        pxa_gpio_mode(GPIO104_CIF_DD_2_MD);
+        pxa_gpio_mode(GPIO103_CIF_DD_3_MD);
+        pxa_gpio_mode(GPIO95_CIF_DD_4_MD);
+        pxa_gpio_mode(GPIO94_CIF_DD_5_MD);
+        pxa_gpio_mode(GPIO93_CIF_DD_6_MD);
+        pxa_gpio_mode(GPIO108_CIF_DD_7_MD);
+        pxa_gpio_mode(GPIO107_CIF_DD_8_MD);
+        pxa_gpio_mode(GPIO106_CIF_DD_9_MD);
+        pxa_gpio_mode(GPIO42_CIF_MCLK_MD);
+        pxa_gpio_mode(GPIO45_CIF_PCLK_MD);
+        pxa_gpio_mode(GPIO43_CIF_FV_MD);
+        pxa_gpio_mode(GPIO44_CIF_LV_MD);
+
+        return 0;
+}
+
+/*
+ * CICR4: PCLK_EN:      Pixel clock is supplied by the sensor
+ *      MCLK_EN:        Master clock is generated by PXA
+ *      PCP:            Data sampled on the falling edge of pixel clock
+ */
+struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
+        .init   = pcm990_pxacamera_init,
+        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 |
+                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/,
+        .mclk_10khz = 1000,
+};
+
+#include <linux/i2c/pca953x.h>
+
+static struct pca953x_platform_data pca9536_data = {
+        .gpio_base      = NR_BUILTIN_GPIO + 1,
+};
+
+static struct soc_camera_link iclink[] = {
+        {
+                .bus_id = 0, /* Must match with the camera ID above */
+                .gpio   = NR_BUILTIN_GPIO + 1,
+        }, {
+                .bus_id = 0, /* Must match with the camera ID above */
+        }
+};
+
+/* Board I2C devices. */
+static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
+        {
+                /* Must initialize before the camera(s) */
+                I2C_BOARD_INFO("pca953x", 0x41),
+                .type = "pca9536",
+                .platform_data = &pca9536_data,
+        }, {
+                I2C_BOARD_INFO("mt9v022", 0x48),
+                .type = "mt9v022",
+                .platform_data = &iclink[0], /* With extender */
+        }, {
+                I2C_BOARD_INFO("mt9m001", 0x5d),
+                .type = "mt9m001",
+                .platform_data = &iclink[0], /* With extender */
+        },
+};
+#endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
+
+/*
  * AC97 support
  * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
  */
@@ -326,5 +404,14 @@ void __init pcm990_baseboard_init(void)
         /* USB host */
         pxa_set_ohci_info(&pcm990_ohci_platform_data);
 
+        pxa_set_i2c_info(NULL);
+
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+        pxa_set_camera_info(&pcm990_pxacamera_platform_data);
+
+        i2c_register_board_info(0, pcm990_i2c_devices,
+                ARRAY_SIZE(pcm990_i2c_devices));
+#endif
+
         printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
 }
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 209eabf0ed3e..ca5ac196b47b 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -32,6 +32,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/irda.h>
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 599e53fcc2c5..d9b5450aee5b 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -26,6 +26,7 @@
 #include <asm/hardware.h>
 #include <asm/arch/irqs.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/dma.h>
 
@@ -129,6 +130,8 @@ static struct clk pxa25x_clks[] = {
         INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
         INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
 
+        INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
+
         /*
         INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
         INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
@@ -228,24 +231,10 @@ static inline void pxa25x_init_pm(void) {}
 static int pxa25x_set_wake(unsigned int irq, unsigned int on)
 {
         int gpio = IRQ_TO_GPIO(irq);
-        uint32_t gpio_bit, mask = 0;
-
-        if (gpio >= 0 && gpio <= 15) {
-                gpio_bit = GPIO_bit(gpio);
-                mask = gpio_bit;
-                if (on) {
-                        if (GRER(gpio) | gpio_bit)
-                                PRER |= gpio_bit;
-                        else
-                                PRER &= ~gpio_bit;
-
-                        if (GFER(gpio) | gpio_bit)
-                                PFER |= gpio_bit;
-                        else
-                                PFER &= ~gpio_bit;
-                }
-                goto set_pwer;
-        }
+        uint32_t mask = 0;
+
+        if (gpio >= 0 && gpio < 85)
+                return gpio_set_wake(gpio, on);
 
         if (irq == IRQ_RTCAlrm) {
                 mask = PWER_RTC;
@@ -265,9 +254,8 @@ set_pwer:
 
 void __init pxa25x_init_irq(void)
 {
-        pxa_init_irq_low();
-        pxa_init_irq_gpio(85);
-        pxa_init_irq_set_wake(pxa25x_set_wake);
+        pxa_init_irq(32, pxa25x_set_wake);
+        pxa_init_gpio(85, pxa25x_set_wake);
 }
 
 static struct platform_device *pxa25x_devices[] __initdata = {
@@ -325,4 +313,4 @@ static int __init pxa25x_init(void)
         return ret;
 }
 
-subsys_initcall(pxa25x_init);
+postcore_initcall(pxa25x_init);
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 46a951c3e5a0..7a2449dd0fd4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -23,6 +23,7 @@
 #include <asm/arch/irqs.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/dma.h>
@@ -151,12 +152,15 @@ static struct clk pxa27x_clks[] = {
 
         INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
         INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
-        INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
+        INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
 
         INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
         INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
         INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
 
+        INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
+        INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
+
         /*
         INIT_CKEN("PWMCLK",  PWM0, 13000000, 0, NULL),
         INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
@@ -283,37 +287,16 @@ static inline void pxa27x_init_pm(void) {}
 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
  * handles the simple cases, not the WEMUX2 and WEMUX3 options
  */
-#define PXA27x_GPIO_NOWAKE_MASK \
-        ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
-#define WAKEMASK(gpio) \
-        (((gpio) <= 15) \
-                 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
-                 : ((gpio == 35) ? (1 << 24) : 0))
-
 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 {
         int gpio = IRQ_TO_GPIO(irq);
         uint32_t mask;
 
-        if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
-                if (WAKEMASK(gpio) == 0)
-                        return -EINVAL;
-
-                mask = WAKEMASK(gpio);
-
-                if (on) {
-                        if (GRER(gpio) | GPIO_bit(gpio))
-                                PRER |= mask;
-                        else
-                                PRER &= ~mask;
+        if (gpio >= 0 && gpio < 128)
+                return gpio_set_wake(gpio, on);
 
-                        if (GFER(gpio) | GPIO_bit(gpio))
-                                PFER |= mask;
-                        else
-                                PFER &= ~mask;
-                }
-                goto set_pwer;
-        }
+        if (irq == IRQ_KEYPAD)
+                return keypad_set_wake(on);
 
         switch (irq) {
         case IRQ_RTCAlrm:
@@ -326,7 +309,6 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on)
                 return -EINVAL;
         }
 
-set_pwer:
         if (on)
                 PWER |= mask;
         else
@@ -337,10 +319,8 @@ set_pwer:
 
 void __init pxa27x_init_irq(void)
 {
-        pxa_init_irq_low();
-        pxa_init_irq_high();
-        pxa_init_irq_gpio(128);
-        pxa_init_irq_set_wake(pxa27x_set_wake);
+        pxa_init_irq(34, pxa27x_set_wake);
+        pxa_init_gpio(128, pxa27x_set_wake);
 }
 
 /*
@@ -386,10 +366,6 @@ static struct platform_device *devices[] __initdata = {
 
 static struct sys_device pxa27x_sysdev[] = {
         {
-                .id     = 0,
-                .cls    = &pxa_irq_sysclass,
-        }, {
-                .id     = 1,
                 .cls    = &pxa_irq_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
@@ -420,4 +396,4 @@ static int __init pxa27x_init(void)
         return ret;
 }
 
-subsys_initcall(pxa27x_init);
+postcore_initcall(pxa27x_init);
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 35f25fdaeba3..dde355e88fa1 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -110,6 +110,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void)
 }
 
 /*
+ * Return the current AC97 clock frequency.
+ */
+static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+{
+        unsigned long rate = 312000000;
+        unsigned long ac97_div;
+
+        ac97_div = AC97_DIV;
+
+        /* This may loose precision for some rates but won't for the
+         * standard 24.576MHz.
+         */
+        rate /= (ac97_div >> 12) & 0x7fff;
+        rate *= (ac97_div & 0xfff);
+
+        return rate;
+}
+
+/*
  * Return the current HSIO bus clock frequency
  */
 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
@@ -156,6 +175,27 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
         .getrate        = clk_pxa3xx_hsio_getrate,
 };
 
+static const struct clkops clk_pxa3xx_ac97_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_ac97_getrate,
+};
+
+static void clk_pout_enable(struct clk *clk)
+{
+        OSCC |= OSCC_PEN;
+}
+
+static void clk_pout_disable(struct clk *clk)
+{
+        OSCC &= ~OSCC_PEN;
+}
+
+static const struct clkops clk_pout_ops = {
+        .enable         = clk_pout_enable,
+        .disable        = clk_pout_disable,
+};
+
 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev)  \
         {                                               \
                 .name   = _name,                        \
@@ -175,8 +215,16 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
         }
 
 static struct clk pxa3xx_clks[] = {
-        PXA3xx_CK("LCDCLK", LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
-        PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+        {
+                .name           = "CLK_POUT",
+                .ops            = &clk_pout_ops,
+                .rate           = 13000000,
+                .delay          = 70,
+        },
+
+        PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
+        PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+        PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
 
         PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
         PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
@@ -185,6 +233,7 @@ static struct clk pxa3xx_clks[] = {
         PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
         PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
         PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
+        PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
 
         PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
         PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
@@ -305,8 +354,10 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state)
         /*
          * Don't sleep if no wakeup sources are defined
          */
-        if (wakeup_src == 0)
+        if (wakeup_src == 0) {
+                printk(KERN_ERR "Not suspending: no wakeup sources\n");
                 return;
+        }
 
         switch (state) {
         case PM_SUSPEND_STANDBY:
@@ -446,15 +497,9 @@ static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 
         return 0;
 }
-
-static void pxa3xx_init_irq_pm(void)
-{
-        pxa_init_irq_set_wake(pxa3xx_set_wake);
-}
-
 #else
 static inline void pxa3xx_init_pm(void) {}
-static inline void pxa3xx_init_irq_pm(void) {}
+#define pxa3xx_set_wake NULL
 #endif
 
 void __init pxa3xx_init_irq(void)
@@ -465,10 +510,8 @@ void __init pxa3xx_init_irq(void)
         value |= (1 << 6);
         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 
-        pxa_init_irq_low();
-        pxa_init_irq_high();
-        pxa_init_irq_gpio(128);
-        pxa3xx_init_irq_pm();
+        pxa_init_irq(56, pxa3xx_set_wake);
+        pxa_init_gpio(128, NULL);
 }
 
 /*
@@ -490,11 +533,9 @@ static struct platform_device *devices[] __initdata = {
 
 static struct sys_device pxa3xx_sysdev[] = {
         {
-                .id     = 0,
                 .cls    = &pxa_irq_sysclass,
         }, {
-                .id     = 1,
-                .cls    = &pxa_irq_sysclass,
+                .cls    = &pxa3xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
         },
@@ -532,4 +573,4 @@ static int __init pxa3xx_init(void)
         return ret;
 }
 
-subsys_initcall(pxa3xx_init);
+postcore_initcall(pxa3xx_init);
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index f9d1b61e1185..34cd585075b0 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -26,6 +26,7 @@
 #include <asm/mach-types.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/sharpsl.h>
 #include "sharpsl.h"
 
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 9e7773fca01c..62a02c3927c5 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -37,6 +37,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/ohci.h>
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 745a4dc7acdd..7a7f5f947cc5 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/spitz.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index f99112d50b41..6458f6d371d9 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/gpio.h>
 
 #include <asm/setup.h>
 #include <asm/memory.h>
@@ -32,7 +33,9 @@
 #include <asm/system.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/irda.h>
+#include <asm/arch/i2c.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
 
@@ -47,6 +50,110 @@
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long tosa_pin_config[] = {
+        GPIO78_nCS_2, /* Scoop */
+        GPIO80_nCS_4, /* tg6393xb */
+        GPIO33_nCS_5, /* Scoop */
+
+        // GPIO76 CARD_VCC_ON1
+
+        GPIO19_GPIO, /* Reset out */
+        GPIO1_RST | WAKEUP_ON_EDGE_FALL,
+
+        GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* WAKE_UP */
+        GPIO2_GPIO | WAKEUP_ON_EDGE_BOTH, /* AC_IN */
+        GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* RECORD */
+        GPIO4_GPIO | WAKEUP_ON_EDGE_FALL, /* SYNC */
+        GPIO20_GPIO, /* EAR_IN */
+        GPIO22_GPIO, /* On */
+
+        GPIO5_GPIO, /* USB_IN */
+        GPIO32_GPIO, /* Pen IRQ */
+
+        GPIO7_GPIO, /* Jacket Detect */
+        GPIO14_GPIO, /* BAT0_CRG */
+        GPIO12_GPIO, /* BAT1_CRG */
+        GPIO17_GPIO, /* BAT0_LOW */
+        GPIO84_GPIO, /* BAT1_LOW */
+        GPIO38_GPIO, /* BAT_LOCK */
+
+        GPIO11_3_6MHz,
+        GPIO15_GPIO, /* TC6393XB IRQ */
+        GPIO18_RDY,
+        GPIO27_GPIO, /* LCD Sync */
+
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO8_MMC_CS0,
+        GPIO9_GPIO, /* Detect */
+        // GPIO10 nSD_INT
+
+        /* CF */
+        GPIO13_GPIO, /* CD_IRQ */
+        GPIO21_GPIO, /* Main Slot IRQ */
+        GPIO36_GPIO, /* Jacket Slot IRQ */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* AC97 */
+        GPIO31_AC97_SYNC,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        // GPIO79 nAUD_IRQ
+
+        /* FFUART */
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+        GPIO37_FFUART_DSR,
+        GPIO39_FFUART_TXD,
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+
+        /* IrDA */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* Keybd */
+        GPIO58_GPIO,
+        GPIO59_GPIO,
+        GPIO60_GPIO,
+        GPIO61_GPIO,
+        GPIO62_GPIO,
+        GPIO63_GPIO,
+        GPIO64_GPIO,
+        GPIO65_GPIO,
+        GPIO66_GPIO,
+        GPIO67_GPIO,
+        GPIO68_GPIO,
+        GPIO69_GPIO,
+        GPIO70_GPIO,
+        GPIO71_GPIO,
+        GPIO72_GPIO,
+        GPIO73_GPIO,
+        GPIO74_GPIO,
+        GPIO75_GPIO,
+
+        /* SPI */
+        GPIO81_SSP2_CLK_OUT,
+        GPIO82_SSP2_FRM_OUT,
+        GPIO83_SSP2_TXD,
+};
+
 /*
  * SCOOP Device
  */
@@ -60,11 +167,10 @@ static struct resource tosa_scoop_resources[] = {
 
 static struct scoop_config tosa_scoop_setup = {
         .io_dir         = TOSA_SCOOP_IO_DIR,
-        .io_out         = TOSA_SCOOP_IO_OUT,
-
+        .gpio_base      = TOSA_SCOOP_GPIO_BASE,
 };
 
-struct platform_device tosascoop_device = {
+static struct platform_device tosascoop_device = {
         .name           = "sharp-scoop",
         .id             = 0,
         .dev            = {
@@ -88,10 +194,10 @@ static struct resource tosa_scoop_jc_resources[] = {
 
 static struct scoop_config tosa_scoop_jc_setup = {
         .io_dir         = TOSA_SCOOP_JC_IO_DIR,
-        .io_out         = TOSA_SCOOP_JC_IO_OUT,
+        .gpio_base      = TOSA_SCOOP_JC_GPIO_BASE,
 };
 
-struct platform_device tosascoop_jc_device = {
+static struct platform_device tosascoop_jc_device = {
         .name           = "sharp-scoop",
         .id             = 1,
         .dev            = {
@@ -118,50 +224,16 @@ static struct scoop_pcmcia_dev tosa_pcmcia_scoop[] = {
 },
 };
 
-static void tosa_pcmcia_init(void)
-{
-        /* Setup default state of GPIO outputs
-           before we enable them as outputs. */
-        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
-                GPIO_bit(GPIO53_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-        pxa_gpio_mode(GPIO52_nPCE_1_MD);
-        pxa_gpio_mode(GPIO53_nPCE_2_MD);
-        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-}
-
 static struct scoop_pcmcia_config tosa_pcmcia_config = {
         .devs         = &tosa_pcmcia_scoop[0],
         .num_devs     = 2,
-        .pcmcia_init  = tosa_pcmcia_init,
 };
 
 /*
  * USB Device Controller
  */
-static void tosa_udc_command(int cmd)
-{
-        switch(cmd)     {
-                case PXA2XX_UDC_CMD_CONNECT:
-                        set_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
-                        break;
-                case PXA2XX_UDC_CMD_DISCONNECT:
-                        reset_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
-                        break;
-        }
-}
-
 static struct pxa2xx_udc_mach_info udc_info __initdata = {
-        .udc_command            = tosa_udc_command,
+        .gpio_pullup            = TOSA_GPIO_USB_PULLUP,
         .gpio_vbus              = TOSA_GPIO_USB_IN,
         .gpio_vbus_inverted     = 1,
 };
@@ -175,19 +247,44 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
 {
         int err;
 
-        /* setup GPIO for PXA25x MMC controller */
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-        pxa_gpio_mode(TOSA_GPIO_nSD_DETECT | GPIO_IN);
-
         tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
 
         err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int,
                           IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                                 "MMC/SD card detect", data);
-        if (err)
+        if (err) {
                 printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+                goto err_irq;
+        }
 
+        err = gpio_request(TOSA_GPIO_SD_WP, "sd_wp");
+        if (err) {
+                printk(KERN_ERR "tosa_mci_init: can't request SD_WP gpio\n");
+                goto err_gpio_wp;
+        }
+        err = gpio_direction_input(TOSA_GPIO_SD_WP);
+        if (err)
+                goto err_gpio_wp_dir;
+
+        err = gpio_request(TOSA_GPIO_PWR_ON, "sd_pwr");
+        if (err) {
+                printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n");
+                goto err_gpio_pwr;
+        }
+        err = gpio_direction_output(TOSA_GPIO_PWR_ON, 0);
+        if (err)
+                goto err_gpio_pwr_dir;
+
+        return 0;
+
+err_gpio_pwr_dir:
+        gpio_free(TOSA_GPIO_PWR_ON);
+err_gpio_pwr:
+err_gpio_wp_dir:
+        gpio_free(TOSA_GPIO_SD_WP);
+err_gpio_wp:
+        free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
+err_irq:
         return err;
 }
 
@@ -196,19 +293,21 @@ static void tosa_mci_setpower(struct device *dev, unsigned int vdd)
         struct pxamci_platform_data* p_d = dev->platform_data;
 
         if (( 1 << vdd) & p_d->ocr_mask) {
-                set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+                gpio_set_value(TOSA_GPIO_PWR_ON, 1);
         } else {
-                reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+                gpio_set_value(TOSA_GPIO_PWR_ON, 0);
         }
 }
 
 static int tosa_mci_get_ro(struct device *dev)
 {
-        return (read_scoop_reg(&tosascoop_device.dev, SCOOP_GPWR)&TOSA_SCOOP_SD_WP);
+        return gpio_get_value(TOSA_GPIO_SD_WP);
 }
 
 static void tosa_mci_exit(struct device *dev, void *data)
 {
+        gpio_free(TOSA_GPIO_PWR_ON);
+        gpio_free(TOSA_GPIO_SD_WP);
         free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
 }
 
@@ -223,21 +322,36 @@ static struct pxamci_platform_data tosa_mci_platform_data = {
 /*
  * Irda
  */
-static void tosa_irda_transceiver_mode(struct device *dev, int mode)
+static int tosa_irda_startup(struct device *dev)
 {
-        if (mode & IR_OFF) {
-                reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
-                pxa_gpio_mode(GPIO47_STTXD|GPIO_DFLT_LOW);
-                pxa_gpio_mode(GPIO47_STTXD|GPIO_OUT);
-        } else {
-                pxa_gpio_mode(GPIO47_STTXD_MD);
-                set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
+        int ret;
+
+        ret = gpio_request(TOSA_GPIO_IR_POWERDWN, "IrDA powerdown");
+        if (ret)
+                return ret;
+
+        ret = gpio_direction_output(TOSA_GPIO_IR_POWERDWN, 0);
+        if (ret)
+                gpio_free(TOSA_GPIO_IR_POWERDWN);
+
+        return ret;
         }
+
+static void tosa_irda_shutdown(struct device *dev)
+{
+        gpio_free(TOSA_GPIO_IR_POWERDWN);
+}
+
+static void tosa_irda_transceiver_mode(struct device *dev, int mode)
+{
+        gpio_set_value(TOSA_GPIO_IR_POWERDWN, !(mode & IR_OFF));
 }
 
 static struct pxaficp_platform_data tosa_ficp_platform_data = {
         .transceiver_cap  = IR_SIRMODE | IR_OFF,
         .transceiver_mode = tosa_irda_transceiver_mode,
+        .startup = tosa_irda_startup,
+        .shutdown = tosa_irda_shutdown,
 };
 
 /*
@@ -249,12 +363,28 @@ static struct platform_device tosakbd_device = {
 };
 
 static struct gpio_keys_button tosa_gpio_keys[] = {
+        /*
+         * Two following keys are directly tied to "ON" button of tosa. Why?
+         * The first one can be used as a wakeup source, the second can't;
+         * also the first one is OR of ac_powered and on_button.
+         */
+        {
+                .type   = EV_PWR,
+                .code   = KEY_RESERVED,
+                .gpio   = TOSA_GPIO_POWERON,
+                .desc   = "Poweron",
+                .wakeup = 1,
+                .active_low = 1,
+        },
         {
                 .type   = EV_PWR,
                 .code   = KEY_SUSPEND,
                 .gpio   = TOSA_GPIO_ON_KEY,
                 .desc   = "On key",
-                .wakeup = 1,
+                /*
+                 * can't be used as wakeup
+                 * .wakeup      = 1,
+                 */
                 .active_low = 1,
         },
         {
@@ -291,9 +421,40 @@ static struct platform_device tosa_gpio_keys_device = {
 /*
  * Tosa LEDs
  */
+static struct gpio_led tosa_gpio_leds[] = {
+        {
+                .name                   = "tosa:amber:charge",
+                .default_trigger        = "main-battery-charging",
+                .gpio                   = TOSA_GPIO_CHRG_ERR_LED,
+        },
+        {
+                .name                   = "tosa:green:mail",
+                .default_trigger        = "nand-disk",
+                .gpio                   = TOSA_GPIO_NOTE_LED,
+        },
+        {
+                .name                   = "tosa:dual:wlan",
+                .default_trigger        = "none",
+                .gpio                   = TOSA_GPIO_WLAN_LED,
+        },
+        {
+                .name                   = "tosa:blue:bluetooth",
+                .default_trigger        = "none",
+                .gpio                   = TOSA_GPIO_BT_LED,
+        },
+};
+
+static struct gpio_led_platform_data tosa_gpio_leds_platform_data = {
+        .leds           = tosa_gpio_leds,
+        .num_leds       = ARRAY_SIZE(tosa_gpio_leds),
+};
+
 static struct platform_device tosaled_device = {
-    .name   = "tosa-led",
-    .id     = -1,
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &tosa_gpio_leds_platform_data,
+        },
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -326,20 +487,13 @@ static void tosa_restart(char mode)
 
 static void __init tosa_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
+        gpio_set_wake(MFP_PIN_GPIO1, 1);
+        /* We can't pass to gpio-keys since it will drop the Reset altfunc */
+
         pm_power_off = tosa_poweroff;
         arm_pm_restart = tosa_restart;
 
-        pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN);
-        pxa_gpio_mode(TOSA_GPIO_TC6393_INT | GPIO_IN);
-        pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN);
-
-        /* setup sleep mode values */
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x00000000;
-        PGSR1 = 0x00FF0002;
-        PGSR2 = 0x00014000;
         PCFR |= PCFR_OPDE;
 
         /* enable batt_fault */
@@ -348,6 +502,7 @@ static void __init tosa_init(void)
         pxa_set_mci_info(&tosa_mci_platform_data);
         pxa_set_udc_info(&udc_info);
         pxa_set_ficp_info(&tosa_ficp_platform_data);
+        pxa_set_i2c_info(NULL);
         platform_scoop_config = &tosa_pcmcia_config;
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index f207fcd30cd7..931885d86b91 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -41,6 +41,7 @@
 #include <asm/mach/flash.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/trizeps4.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index afd2cbfca0d9..dbb546216be1 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -26,6 +26,7 @@
 #include <asm/arch/pxafb.h>
 #include <asm/arch/zylonite.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pxa27x_keypad.h>
 
 #include "generic.h"
 
@@ -35,6 +36,8 @@ struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
 int gpio_backlight;
 int gpio_eth_irq;
 
+int wm9713_irq;
+
 int lcd_id;
 int lcd_orientation;
 
@@ -249,6 +252,71 @@ static void __init zylonite_init_mmc(void)
 static inline void zylonite_init_mmc(void) {}
 #endif
 
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int zylonite_matrix_key_map[] = {
+        /* KEY(row, col, key_code) */
+        KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D),
+        KEY(1, 0, KEY_E), KEY(1, 1, KEY_F), KEY(1, 2, KEY_G), KEY(1, 5, KEY_H),
+        KEY(2, 0, KEY_I), KEY(2, 1, KEY_J), KEY(2, 2, KEY_K), KEY(2, 5, KEY_L),
+        KEY(3, 0, KEY_M), KEY(3, 1, KEY_N), KEY(3, 2, KEY_O), KEY(3, 5, KEY_P),
+        KEY(5, 0, KEY_Q), KEY(5, 1, KEY_R), KEY(5, 2, KEY_S), KEY(5, 5, KEY_T),
+        KEY(6, 0, KEY_U), KEY(6, 1, KEY_V), KEY(6, 2, KEY_W), KEY(6, 5, KEY_X),
+        KEY(7, 1, KEY_Y), KEY(7, 2, KEY_Z),
+
+        KEY(4, 4, KEY_0), KEY(1, 3, KEY_1), KEY(4, 1, KEY_2), KEY(1, 4, KEY_3),
+        KEY(2, 3, KEY_4), KEY(4, 2, KEY_5), KEY(2, 4, KEY_6), KEY(3, 3, KEY_7),
+        KEY(4, 3, KEY_8), KEY(3, 4, KEY_9),
+
+        KEY(4, 5, KEY_SPACE),
+        KEY(5, 3, KEY_KPASTERISK),      /* * */
+        KEY(5, 4, KEY_KPDOT),           /* #" */
+
+        KEY(0, 7, KEY_UP),
+        KEY(1, 7, KEY_DOWN),
+        KEY(2, 7, KEY_LEFT),
+        KEY(3, 7, KEY_RIGHT),
+        KEY(2, 6, KEY_HOME),
+        KEY(3, 6, KEY_END),
+        KEY(6, 4, KEY_DELETE),
+        KEY(6, 6, KEY_BACK),
+        KEY(6, 3, KEY_CAPSLOCK),        /* KEY_LEFTSHIFT), */
+
+        KEY(4, 6, KEY_ENTER),           /* scroll push */
+        KEY(5, 7, KEY_ENTER),           /* keypad action */
+
+        KEY(0, 4, KEY_EMAIL),
+        KEY(5, 6, KEY_SEND),
+        KEY(4, 0, KEY_CALENDAR),
+        KEY(7, 6, KEY_RECORD),
+        KEY(6, 7, KEY_VOLUMEUP),
+        KEY(7, 7, KEY_VOLUMEDOWN),
+
+        KEY(0, 6, KEY_F22),     /* soft1 */
+        KEY(1, 6, KEY_F23),     /* soft2 */
+        KEY(0, 3, KEY_AUX),     /* contact */
+};
+
+static struct pxa27x_keypad_platform_data zylonite_keypad_info = {
+        .matrix_key_rows        = 8,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = zylonite_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(zylonite_matrix_key_map),
+
+        .enable_rotary0         = 1,
+        .rotary0_up_key         = KEY_UP,
+        .rotary0_down_key       = KEY_DOWN,
+
+        .debounce_interval      = 30,
+};
+
+static void __init zylonite_init_keypad(void)
+{
+        pxa_set_keypad_info(&zylonite_keypad_info);
+}
+#else
+static inline void zylonite_init_keypad(void) {}
+#endif
+
 static void __init zylonite_init(void)
 {
         /* board-processor specific initialization */
@@ -265,6 +333,7 @@ static void __init zylonite_init(void)
 
         zylonite_init_lcd();
         zylonite_init_mmc();
+        zylonite_init_keypad();
 }
 
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 6ac04c09b0e9..324fb9daae28 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -21,7 +21,7 @@
 #include <asm/arch/mfp-pxa300.h>
 #include <asm/arch/zylonite.h>
 
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+#include "generic.h"
 
 /* PXA300/PXA310 common configurations */
 static mfp_cfg_t common_mfp_cfg[] __initdata = {
@@ -69,6 +69,9 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
         GPIO27_AC97_SDATA_OUT,
         GPIO28_AC97_SYNC,
 
+        /* WM9713 IRQ */
+        GPIO26_GPIO,
+
         /* Keypad */
         GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
         GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
@@ -203,6 +206,9 @@ void __init zylonite_pxa300_init(void)
                 /* MMC card detect & write protect for controller 0 */
                 zylonite_mmc_slot[0].gpio_cd  = EXT_GPIO(0);
                 zylonite_mmc_slot[0].gpio_wp  = EXT_GPIO(2);
+
+                /* WM9713 IRQ */
+                wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO26);
         }
 
         if (cpu_is_pxa300()) {
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index dfa79992b8ab..193d07903b06 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -21,7 +21,7 @@
 #include <asm/arch/mfp-pxa320.h>
 #include <asm/arch/zylonite.h>
 
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+#include "generic.h"
 
 static mfp_cfg_t mfp_cfg[] __initdata = {
         /* LCD */
@@ -68,6 +68,9 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
         GPIO39_AC97_BITCLK,
         GPIO40_AC97_nACRESET,
 
+        /* WM9713 IRQ */
+        GPIO15_GPIO,
+
         /* I2C */
         GPIO32_I2C_SCL,
         GPIO33_I2C_SDA,
@@ -190,5 +193,8 @@ void __init zylonite_pxa320_init(void)
                 /* MMC card detect & write protect for controller 0 */
                 zylonite_mmc_slot[0].gpio_cd  = mfp_to_gpio(MFP_PIN_GPIO1);
                 zylonite_mmc_slot[0].gpio_wp  = mfp_to_gpio(MFP_PIN_GPIO5);
+
+                /* WM9713 IRQ */
+                wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO15);
         }
 }
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 39b3bb7f1020..5ccde7cf39e8 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -10,7 +10,6 @@ config MACH_REALVIEW_EB
 config REALVIEW_EB_ARM11MP
         bool "Support ARM11MPCore tile"
         depends on MACH_REALVIEW_EB
-        select CACHE_L2X0
         help
           Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -24,4 +23,18 @@ config REALVIEW_EB_ARM11MP_REVB
           kernel built with this option enabled is not compatible with
           other revisions of the ARM11MPCore tile.
 
+config MACH_REALVIEW_PB11MP
+        bool "Support RealView/PB11MPCore platform"
+        select ARM_GIC
+        help
+          Include support for the ARM(R) RealView MPCore Platform Baseboard.
+          PB11MPCore is a platform with an on-board ARM11MPCore and has
+          support for PCI-E and Compact Flash.
+
+config MACH_REALVIEW_PB1176
+        bool "Support RealView/PB1176 platform"
+        select ARM_GIC
+        help
+          Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
+
 endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index ca1e390c3c28..d2ae077431dd 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -4,5 +4,7 @@
 
 obj-y                                   := core.o clock.o
 obj-$(CONFIG_MACH_REALVIEW_EB)          += realview_eb.o
+obj-$(CONFIG_MACH_REALVIEW_PB11MP)      += realview_pb11mp.o
+obj-$(CONFIG_MACH_REALVIEW_PB1176)      += realview_pb1176.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c
index 21325a4da9da..3e706c57833a 100644
--- a/arch/arm/mach-realview/clock.c
+++ b/arch/arm/mach-realview/clock.c
@@ -16,7 +16,6 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 
-#include <asm/semaphore.h>
 #include <asm/hardware/icst307.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 98aefc9f4df3..131990d196f5 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -109,22 +109,21 @@ static struct flash_platform_data realview_flash_data = {
         .set_vpp                = realview_flash_set_vpp,
 };
 
-static struct resource realview_flash_resource = {
-        .start                  = REALVIEW_FLASH_BASE,
-        .end                    = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
-        .flags                  = IORESOURCE_MEM,
-};
-
 struct platform_device realview_flash_device = {
         .name                   = "armflash",
         .id                     = 0,
         .dev                    = {
                 .platform_data  = &realview_flash_data,
         },
-        .num_resources          = 1,
-        .resource               = &realview_flash_resource,
 };
 
+int realview_flash_register(struct resource *res, u32 num)
+{
+        realview_flash_device.resource = res;
+        realview_flash_device.num_resources = num;
+        return platform_device_register(&realview_flash_device);
+}
+
 static struct resource realview_i2c_resource = {
         .start          = REALVIEW_I2C_BASE,
         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
@@ -445,10 +444,10 @@ void realview_leds_event(led_event_t ledevt)
 /*
  * Where is the timer (VA)?
  */
-#define TIMER0_VA_BASE           __io_address(REALVIEW_TIMER0_1_BASE)
-#define TIMER1_VA_BASE          (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
-#define TIMER2_VA_BASE           __io_address(REALVIEW_TIMER2_3_BASE)
-#define TIMER3_VA_BASE          (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
+void __iomem *timer0_va_base;
+void __iomem *timer1_va_base;
+void __iomem *timer2_va_base;
+void __iomem *timer3_va_base;
 
 /*
  * How long is the timer interval?
@@ -475,7 +474,7 @@ static void timer_set_mode(enum clock_event_mode mode,
 
         switch(mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
+                writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
 
                 ctrl = TIMER_CTRL_PERIODIC;
                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
@@ -491,16 +490,16 @@ static void timer_set_mode(enum clock_event_mode mode,
                 ctrl = 0;
         }
 
-        writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
+        writel(ctrl, timer0_va_base + TIMER_CTRL);
 }
 
 static int timer_set_next_event(unsigned long evt,
                                 struct clock_event_device *unused)
 {
-        unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
+        unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
 
-        writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
-        writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
+        writel(evt, timer0_va_base + TIMER_LOAD);
+        writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
 
         return 0;
 }
@@ -536,7 +535,7 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
         struct clock_event_device *evt = &timer0_clockevent;
 
         /* clear the interrupt */
-        writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
+        writel(1, timer0_va_base + TIMER_INTCLR);
 
         evt->event_handler(evt);
 
@@ -551,7 +550,7 @@ static struct irqaction realview_timer_irq = {
 
 static cycle_t realview_get_cycles(void)
 {
-        return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
+        return ~readl(timer3_va_base + TIMER_VALUE);
 }
 
 static struct clocksource clocksource_realview = {
@@ -566,11 +565,11 @@ static struct clocksource clocksource_realview = {
 static void __init realview_clocksource_init(void)
 {
         /* setup timer 0 as free-running clocksource */
-        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-        writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
-        writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
+        writel(0, timer3_va_base + TIMER_CTRL);
+        writel(0xffffffff, timer3_va_base + TIMER_LOAD);
+        writel(0xffffffff, timer3_va_base + TIMER_VALUE);
         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
-                TIMER3_VA_BASE + TIMER_CTRL);
+                timer3_va_base + TIMER_CTRL);
 
         clocksource_realview.mult =
                 clocksource_khz2mult(1000, clocksource_realview.shift);
@@ -607,10 +606,10 @@ void __init realview_timer_init(unsigned int timer_irq)
         /*
          * Initialise to a known state (all timers off)
          */
-        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+        writel(0, timer0_va_base + TIMER_CTRL);
+        writel(0, timer1_va_base + TIMER_CTRL);
+        writel(0, timer2_va_base + TIMER_CTRL);
+        writel(0, timer3_va_base + TIMER_CTRL);
 
         /* 
          * Make irqs happen for the system timer
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 492a14c0d604..33dbbb41a663 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -55,8 +55,13 @@ extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *twd_base_addr;
 extern unsigned int twd_size;
 #endif
+extern void __iomem *timer0_va_base;
+extern void __iomem *timer1_va_base;
+extern void __iomem *timer2_va_base;
+extern void __iomem *timer3_va_base;
 
 extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
+extern int realview_flash_register(struct resource *res, u32 num);
 
 #endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index de2b7159557d..3e57428affee 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -15,11 +15,14 @@
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/arm_scu.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/scu.h>
+
 extern void realview_secondary_startup(void);
 
 /*
@@ -31,9 +34,15 @@ volatile int __cpuinitdata pen_release = -1;
 static unsigned int __init get_core_count(void)
 {
         unsigned int ncores;
+        void __iomem *scu_base = 0;
+
+        if (machine_is_realview_eb() && core_tile_eb11mp())
+                scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+        else if (machine_is_realview_pb11mp())
+                scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
 
-        if (machine_is_realview_eb() && core_tile_eb11mp()) {
-                ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG);
+        if (scu_base) {
+                ncores = __raw_readl(scu_base + SCU_CONFIG);
                 ncores = (ncores & 0x03) + 1;
         } else
                 ncores = 1;
@@ -41,6 +50,26 @@ static unsigned int __init get_core_count(void)
         return ncores;
 }
 
+/*
+ * Setup the SCU
+ */
+static void scu_enable(void)
+{
+        u32 scu_ctrl;
+        void __iomem *scu_base;
+
+        if (machine_is_realview_eb() && core_tile_eb11mp())
+                scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+        else if (machine_is_realview_pb11mp())
+                scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
+        else
+                BUG();
+
+        scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+        scu_ctrl |= 1;
+        __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
+}
+
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
@@ -57,7 +86,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+        if (machine_is_realview_eb() && core_tile_eb11mp())
+                gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+        else if (machine_is_realview_pb11mp())
+                gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
 
         /*
          * let the primary processor know we're out of the
@@ -198,7 +230,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
          * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
          * realview_timer_init
          */
-        if (machine_is_realview_eb() && core_tile_eb11mp())
+        if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
+            machine_is_realview_pb11mp())
                 local_timer_setup(cpu);
 #endif
 
@@ -210,11 +243,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                 cpu_set(i, cpu_present_map);
 
         /*
-         * Do we need any more CPUs? If so, then let them know where
-         * to start. Note that, on modern versions of MILO, the "poke"
-         * doesn't actually do anything until each individual core is
-         * sent a soft interrupt to get it out of WFI
+         * Initialise the SCU if there are more than one CPU and let
+         * them know where to start. Note that, on modern versions of
+         * MILO, the "poke" doesn't actually do anything until each
+         * individual core is sent a soft interrupt to get it out of
+         * WFI
          */
-        if (max_cpus > 1)
+        if (max_cpus > 1) {
+                scu_enable();
                 poke_milo();
+        }
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 60d9eb810246..5782d83fd886 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -51,13 +51,13 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_GIC_CPU_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_GIC_CPU_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_GIC_DIST_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
@@ -66,20 +66,20 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_TIMER0_1_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_TIMER0_1_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_TIMER2_3_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_TIMER2_3_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         },
 #ifdef CONFIG_DEBUG_LL
         {
-                .virtual        = IO_ADDRESS(REALVIEW_UART0_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_UART0_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }
@@ -136,12 +136,12 @@ static void __init realview_eb_map_io(void)
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
-#define SMC_IRQ         { NO_IRQ, NO_IRQ }
-#define SMC_DMA         { 0, 0 }
+#define EB_SMC_IRQ      { NO_IRQ, NO_IRQ }
+#define EB_SMC_DMA      { 0, 0 }
 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 #define MPMC_DMA        { 0, 0 }
-#define CLCD_IRQ        { IRQ_EB_CLCD, NO_IRQ }
-#define CLCD_DMA        { 0, 0 }
+#define EB_CLCD_IRQ     { IRQ_EB_CLCD, NO_IRQ }
+#define EB_CLCD_DMA     { 0, 0 }
 #define DMAC_IRQ        { IRQ_EB_DMA, NO_IRQ }
 #define DMAC_DMA        { 0, 0 }
 
@@ -150,53 +150,53 @@ static void __init realview_eb_map_io(void)
  */
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 #define SCTL_DMA        { 0, 0 }
-#define WATCHDOG_IRQ    { IRQ_EB_WDOG, NO_IRQ }
-#define WATCHDOG_DMA    { 0, 0 }
-#define GPIO0_IRQ       { IRQ_EB_GPIO0, NO_IRQ }
-#define GPIO0_DMA       { 0, 0 }
+#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
+#define EB_WATCHDOG_DMA { 0, 0 }
+#define EB_GPIO0_IRQ    { IRQ_EB_GPIO0, NO_IRQ }
+#define EB_GPIO0_DMA    { 0, 0 }
 #define GPIO1_IRQ       { IRQ_EB_GPIO1, NO_IRQ }
 #define GPIO1_DMA       { 0, 0 }
-#define RTC_IRQ         { IRQ_EB_RTC, NO_IRQ }
-#define RTC_DMA         { 0, 0 }
+#define EB_RTC_IRQ      { IRQ_EB_RTC, NO_IRQ }
+#define EB_RTC_DMA      { 0, 0 }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
 #define SCI_IRQ         { IRQ_EB_SCI, NO_IRQ }
 #define SCI_DMA         { 7, 6 }
-#define UART0_IRQ       { IRQ_EB_UART0, NO_IRQ }
-#define UART0_DMA       { 15, 14 }
-#define UART1_IRQ       { IRQ_EB_UART1, NO_IRQ }
-#define UART1_DMA       { 13, 12 }
-#define UART2_IRQ       { IRQ_EB_UART2, NO_IRQ }
-#define UART2_DMA       { 11, 10 }
-#define UART3_IRQ       { IRQ_EB_UART3, NO_IRQ }
-#define UART3_DMA       { 0x86, 0x87 }
-#define SSP_IRQ         { IRQ_EB_SSP, NO_IRQ }
-#define SSP_DMA         { 9, 8 }
+#define EB_UART0_IRQ    { IRQ_EB_UART0, NO_IRQ }
+#define EB_UART0_DMA    { 15, 14 }
+#define EB_UART1_IRQ    { IRQ_EB_UART1, NO_IRQ }
+#define EB_UART1_DMA    { 13, 12 }
+#define EB_UART2_IRQ    { IRQ_EB_UART2, NO_IRQ }
+#define EB_UART2_DMA    { 11, 10 }
+#define EB_UART3_IRQ    { IRQ_EB_UART3, NO_IRQ }
+#define EB_UART3_DMA    { 0x86, 0x87 }
+#define EB_SSP_IRQ      { IRQ_EB_SSP, NO_IRQ }
+#define EB_SSP_DMA      { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &realview_mmc0_plat_data);
 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
-AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
+AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
-AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
+AMBA_DEVICE(smc,   "dev:00",  EB_SMC,   NULL);
+AMBA_DEVICE(clcd,  "dev:20",  EB_CLCD,  &clcd_plat_data);
 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
-AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
+AMBA_DEVICE(wdog,  "dev:e1",  EB_WATCHDOG, NULL);
+AMBA_DEVICE(gpio0, "dev:e4",  EB_GPIO0, NULL);
 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
-AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
+AMBA_DEVICE(rtc,   "dev:e8",  EB_RTC,   NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
-AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
-AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
-AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
-AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
+AMBA_DEVICE(uart0, "dev:f1",  EB_UART0, NULL);
+AMBA_DEVICE(uart1, "dev:f2",  EB_UART1, NULL);
+AMBA_DEVICE(uart2, "dev:f3",  EB_UART2, NULL);
+AMBA_DEVICE(ssp0,  "dev:f4",  EB_SSP,   NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -223,11 +223,16 @@ static struct amba_device *amba_devs[] __initdata = {
 /*
  * RealView EB platform devices
  */
+static struct resource realview_eb_flash_resource = {
+        .start                  = REALVIEW_EB_FLASH_BASE,
+        .end                    = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
+        .flags                  = IORESOURCE_MEM,
+};
 
-static struct resource realview_eb_smc91x_resources[] = {
+static struct resource realview_eb_eth_resources[] = {
         [0] = {
-                .start          = REALVIEW_ETH_BASE,
-                .end            = REALVIEW_ETH_BASE + SZ_64K - 1,
+                .start          = REALVIEW_EB_ETH_BASE,
+                .end            = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
@@ -237,13 +242,36 @@ static struct resource realview_eb_smc91x_resources[] = {
         },
 };
 
-static struct platform_device realview_eb_smc91x_device = {
-        .name           = "smc91x",
+static struct platform_device realview_eb_eth_device = {
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(realview_eb_smc91x_resources),
-        .resource       = realview_eb_smc91x_resources,
+        .num_resources  = ARRAY_SIZE(realview_eb_eth_resources),
+        .resource       = realview_eb_eth_resources,
 };
 
+/*
+ * Detect and register the correct Ethernet device. RealView/EB rev D
+ * platforms use the newer SMSC LAN9118 Ethernet chip
+ */
+static int eth_device_register(void)
+{
+        void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
+        u32 idrev;
+
+        if (!eth_addr)
+                return -ENOMEM;
+
+        idrev = readl(eth_addr + 0x50);
+        if ((idrev & 0xFFFF0000) == 0x01180000)
+                /* SMSC LAN9118 chip present */
+                realview_eb_eth_device.name = "smc911x";
+        else
+                /* SMSC 91C111 chip present */
+                realview_eb_eth_device.name = "smc91x";
+
+        iounmap(eth_addr);
+        return platform_device_register(&realview_eb_eth_device);
+}
+
 static void __init gic_init_irq(void)
 {
         if (core_tile_eb11mp()) {
@@ -263,14 +291,14 @@ static void __init gic_init_irq(void)
 
 #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
                 /* board GIC, secondary */
-                gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64);
-                gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE));
+                gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
+                gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
                 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
 #endif
         } else {
                 /* board GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
+                gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
+                gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
                 gic_cpu_init(0, gic_cpu_base_addr);
         }
 }
@@ -301,14 +329,19 @@ static void realview_eb11mp_fixup(void)
         kmi1_device.irq[0]      = IRQ_EB11MP_KMI1;
 
         /* platform devices */
-        realview_eb_smc91x_resources[1].start   = IRQ_EB11MP_ETH;
-        realview_eb_smc91x_resources[1].end     = IRQ_EB11MP_ETH;
+        realview_eb_eth_resources[1].start      = IRQ_EB11MP_ETH;
+        realview_eb_eth_resources[1].end        = IRQ_EB11MP_ETH;
 }
 
 static void __init realview_eb_timer_init(void)
 {
         unsigned int timer_irq;
 
+        timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
+        timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
+        timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
+        timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
+
         if (core_tile_eb11mp()) {
 #ifdef CONFIG_LOCAL_TIMERS
                 twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
@@ -332,16 +365,18 @@ static void __init realview_eb_init(void)
         if (core_tile_eb11mp()) {
                 realview_eb11mp_fixup();
 
+#ifdef CONFIG_CACHE_L2X0
                 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
                  * Bits:  .... ...0 0111 1001 0000 .... .... .... */
                 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
         }
 
         clk_register(&realview_clcd_clk);
 
-        platform_device_register(&realview_flash_device);
-        platform_device_register(&realview_eb_smc91x_device);
+        realview_flash_register(&realview_eb_flash_resource, 1);
         platform_device_register(&realview_i2c_device);
+        eth_device_register();
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
@@ -355,8 +390,8 @@ static void __init realview_eb_init(void)
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_UART0_BASE,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc,
+        .phys_io        = REALVIEW_EB_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = realview_eb_map_io,
         .init_irq       = gic_init_irq,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
new file mode 100644
index 000000000000..cf7f576a5860
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -0,0 +1,292 @@
+/*
+ *  linux/arch/arm/mach-realview/realview_pb1176.c
+ *
+ *  Copyright (C) 2008 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/icst307.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/board-pb1176.h>
+#include <asm/arch/irqs.h>
+
+#include "core.h"
+#include "clock.h"
+
+static struct map_desc realview_pb1176_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_SYS_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SYS_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_SCTL_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SCTL_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_L220_BASE),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        },
+#ifdef CONFIG_DEBUG_LL
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+#endif
+};
+
+static void __init realview_pb1176_map_io(void)
+{
+        iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
+}
+
+/*
+ * RealView PB1176 AMBA devices
+ */
+#define GPIO2_IRQ       { IRQ_PB1176_GPIO2, NO_IRQ }
+#define GPIO2_DMA       { 0, 0 }
+#define GPIO3_IRQ       { IRQ_PB1176_GPIO3, NO_IRQ }
+#define GPIO3_DMA       { 0, 0 }
+#define AACI_IRQ        { IRQ_PB1176_AACI, NO_IRQ }
+#define AACI_DMA        { 0x80, 0x81 }
+#define MMCI0_IRQ       { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
+#define MMCI0_DMA       { 0x84, 0 }
+#define KMI0_IRQ        { IRQ_PB1176_KMI0, NO_IRQ }
+#define KMI0_DMA        { 0, 0 }
+#define KMI1_IRQ        { IRQ_PB1176_KMI1, NO_IRQ }
+#define KMI1_DMA        { 0, 0 }
+#define PB1176_SMC_IRQ  { NO_IRQ, NO_IRQ }
+#define PB1176_SMC_DMA  { 0, 0 }
+#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
+#define MPMC_DMA        { 0, 0 }
+#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
+#define PB1176_CLCD_DMA { 0, 0 }
+#define DMAC_IRQ        { IRQ_PB1176_DMAC, NO_IRQ }
+#define DMAC_DMA        { 0, 0 }
+#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
+#define SCTL_DMA        { 0, 0 }
+#define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
+#define PB1176_WATCHDOG_DMA     { 0, 0 }
+#define PB1176_GPIO0_IRQ        { IRQ_PB1176_GPIO0, NO_IRQ }
+#define PB1176_GPIO0_DMA        { 0, 0 }
+#define GPIO1_IRQ       { IRQ_PB1176_GPIO1, NO_IRQ }
+#define GPIO1_DMA       { 0, 0 }
+#define PB1176_RTC_IRQ  { IRQ_DC1176_RTC, NO_IRQ }
+#define PB1176_RTC_DMA  { 0, 0 }
+#define SCI_IRQ         { IRQ_PB1176_SCI, NO_IRQ }
+#define SCI_DMA         { 7, 6 }
+#define PB1176_UART0_IRQ        { IRQ_DC1176_UART0, NO_IRQ }
+#define PB1176_UART0_DMA        { 15, 14 }
+#define PB1176_UART1_IRQ        { IRQ_DC1176_UART1, NO_IRQ }
+#define PB1176_UART1_DMA        { 13, 12 }
+#define PB1176_UART2_IRQ        { IRQ_DC1176_UART2, NO_IRQ }
+#define PB1176_UART2_DMA        { 11, 10 }
+#define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
+#define PB1176_UART3_DMA        { 0x86, 0x87 }
+#define PB1176_SSP_IRQ          { IRQ_PB1176_SSP, NO_IRQ }
+#define PB1176_SSP_DMA          { 9, 8 }
+
+/* FPGA Primecells */
+AMBA_DEVICE(aaci,       "fpga:04",      AACI,           NULL);
+AMBA_DEVICE(mmc0,       "fpga:05",      MMCI0,          &realview_mmc0_plat_data);
+AMBA_DEVICE(kmi0,       "fpga:06",      KMI0,           NULL);
+AMBA_DEVICE(kmi1,       "fpga:07",      KMI1,           NULL);
+AMBA_DEVICE(uart3,      "fpga:09",      PB1176_UART3,   NULL);
+
+/* DevChip Primecells */
+AMBA_DEVICE(smc,        "dev:00",       PB1176_SMC,     NULL);
+AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
+AMBA_DEVICE(wdog,       "dev:e1",       PB1176_WATCHDOG,        NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB1176_GPIO0,   NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(rtc,        "dev:e8",       PB1176_RTC,     NULL);
+AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
+AMBA_DEVICE(uart0,      "dev:f1",       PB1176_UART0,   NULL);
+AMBA_DEVICE(uart1,      "dev:f2",       PB1176_UART1,   NULL);
+AMBA_DEVICE(uart2,      "dev:f3",       PB1176_UART2,   NULL);
+AMBA_DEVICE(ssp0,       "dev:f4",       PB1176_SSP,     NULL);
+
+/* Primecells on the NEC ISSP chip */
+AMBA_DEVICE(clcd,       "issp:20",      PB1176_CLCD,    &clcd_plat_data);
+//AMBA_DEVICE(dmac,     "issp:30",      PB1176_DMAC,    NULL);
+
+static struct amba_device *amba_devs[] __initdata = {
+//      &dmac_device,
+        &uart0_device,
+        &uart1_device,
+        &uart2_device,
+        &uart3_device,
+        &smc_device,
+        &clcd_device,
+        &sctl_device,
+        &wdog_device,
+        &gpio0_device,
+        &gpio1_device,
+        &gpio2_device,
+        &rtc_device,
+        &sci0_device,
+        &ssp0_device,
+        &aaci_device,
+        &mmc0_device,
+        &kmi0_device,
+        &kmi1_device,
+};
+
+/*
+ * RealView PB1176 platform devices
+ */
+static struct resource realview_pb1176_flash_resource = {
+        .start                  = REALVIEW_PB1176_FLASH_BASE,
+        .end                    = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
+        .flags                  = IORESOURCE_MEM,
+};
+
+static struct resource realview_pb1176_smsc911x_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PB1176_ETH_BASE,
+                .end            = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_PB1176_ETH,
+                .end            = IRQ_PB1176_ETH,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device realview_pb1176_smsc911x_device = {
+        .name           = "smc911x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(realview_pb1176_smsc911x_resources),
+        .resource       = realview_pb1176_smsc911x_resources,
+};
+
+static void __init gic_init_irq(void)
+{
+        /* ARM1176 DevChip GIC, primary */
+        gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
+        gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
+        gic_cpu_init(0, gic_cpu_base_addr);
+
+        /* board GIC, secondary */
+        gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
+        gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
+        gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
+}
+
+static void __init realview_pb1176_timer_init(void)
+{
+        timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE);
+        timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20;
+        timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
+        timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
+
+        realview_timer_init(IRQ_DC1176_TIMER0);
+}
+
+static struct sys_timer realview_pb1176_timer = {
+        .init           = realview_pb1176_timer_init,
+};
+
+static void __init realview_pb1176_init(void)
+{
+        int i;
+
+#ifdef CONFIG_CACHE_L2X0
+        /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
+        l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
+#endif
+
+        clk_register(&realview_clcd_clk);
+
+        realview_flash_register(&realview_pb1176_flash_resource, 1);
+        platform_device_register(&realview_pb1176_smsc911x_device);
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+
+#ifdef CONFIG_LEDS
+        leds_event = realview_leds_event;
+#endif
+}
+
+MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .phys_io        = REALVIEW_PB1176_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .map_io         = realview_pb1176_map_io,
+        .init_irq       = gic_init_irq,
+        .timer          = &realview_pb1176_timer,
+        .init_machine   = realview_pb1176_init,
+MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
new file mode 100644
index 000000000000..f7ce1c5a178a
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -0,0 +1,342 @@
+/*
+ *  linux/arch/arm/mach-realview/realview_pb11mp.c
+ *
+ *  Copyright (C) 2008 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/icst307.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/irqs.h>
+
+#include "core.h"
+#include "clock.h"
+
+static struct map_desc realview_pb11mp_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_SYS_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SYS_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_SCTL_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SCTL_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        },
+#ifdef CONFIG_DEBUG_LL
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+#endif
+};
+
+static void __init realview_pb11mp_map_io(void)
+{
+        iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
+}
+
+/*
+ * RealView PB11MPCore AMBA devices
+ */
+
+#define GPIO2_IRQ               { IRQ_PB11MP_GPIO2, NO_IRQ }
+#define GPIO2_DMA               { 0, 0 }
+#define GPIO3_IRQ               { IRQ_PB11MP_GPIO3, NO_IRQ }
+#define GPIO3_DMA               { 0, 0 }
+#define AACI_IRQ                { IRQ_TC11MP_AACI, NO_IRQ }
+#define AACI_DMA                { 0x80, 0x81 }
+#define MMCI0_IRQ               { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
+#define MMCI0_DMA               { 0x84, 0 }
+#define KMI0_IRQ                { IRQ_TC11MP_KMI0, NO_IRQ }
+#define KMI0_DMA                { 0, 0 }
+#define KMI1_IRQ                { IRQ_TC11MP_KMI1, NO_IRQ }
+#define KMI1_DMA                { 0, 0 }
+#define PB11MP_SMC_IRQ          { NO_IRQ, NO_IRQ }
+#define PB11MP_SMC_DMA          { 0, 0 }
+#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
+#define MPMC_DMA                { 0, 0 }
+#define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD, NO_IRQ }
+#define PB11MP_CLCD_DMA         { 0, 0 }
+#define DMAC_IRQ                { IRQ_PB11MP_DMAC, NO_IRQ }
+#define DMAC_DMA                { 0, 0 }
+#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
+#define SCTL_DMA                { 0, 0 }
+#define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG, NO_IRQ }
+#define PB11MP_WATCHDOG_DMA     { 0, 0 }
+#define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0, NO_IRQ }
+#define PB11MP_GPIO0_DMA        { 0, 0 }
+#define GPIO1_IRQ               { IRQ_PB11MP_GPIO1, NO_IRQ }
+#define GPIO1_DMA               { 0, 0 }
+#define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC, NO_IRQ }
+#define PB11MP_RTC_DMA          { 0, 0 }
+#define SCI_IRQ                 { IRQ_PB11MP_SCI, NO_IRQ }
+#define SCI_DMA                 { 7, 6 }
+#define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0, NO_IRQ }
+#define PB11MP_UART0_DMA        { 15, 14 }
+#define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1, NO_IRQ }
+#define PB11MP_UART1_DMA        { 13, 12 }
+#define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2, NO_IRQ }
+#define PB11MP_UART2_DMA        { 11, 10 }
+#define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3, NO_IRQ }
+#define PB11MP_UART3_DMA        { 0x86, 0x87 }
+#define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP, NO_IRQ }
+#define PB11MP_SSP_DMA          { 9, 8 }
+
+/* FPGA Primecells */
+AMBA_DEVICE(aaci,       "fpga:04",      AACI,           NULL);
+AMBA_DEVICE(mmc0,       "fpga:05",      MMCI0,          &realview_mmc0_plat_data);
+AMBA_DEVICE(kmi0,       "fpga:06",      KMI0,           NULL);
+AMBA_DEVICE(kmi1,       "fpga:07",      KMI1,           NULL);
+AMBA_DEVICE(uart3,      "fpga:09",      PB11MP_UART3,   NULL);
+
+/* DevChip Primecells */
+AMBA_DEVICE(smc,        "dev:00",       PB11MP_SMC,     NULL);
+AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
+AMBA_DEVICE(wdog,       "dev:e1",       PB11MP_WATCHDOG, NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB11MP_GPIO0,   NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(rtc,        "dev:e8",       PB11MP_RTC,     NULL);
+AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
+AMBA_DEVICE(uart0,      "dev:f1",       PB11MP_UART0,   NULL);
+AMBA_DEVICE(uart1,      "dev:f2",       PB11MP_UART1,   NULL);
+AMBA_DEVICE(uart2,      "dev:f3",       PB11MP_UART2,   NULL);
+AMBA_DEVICE(ssp0,       "dev:f4",       PB11MP_SSP,     NULL);
+
+/* Primecells on the NEC ISSP chip */
+AMBA_DEVICE(clcd,       "issp:20",      PB11MP_CLCD,    &clcd_plat_data);
+AMBA_DEVICE(dmac,       "issp:30",      DMAC,           NULL);
+
+static struct amba_device *amba_devs[] __initdata = {
+        &dmac_device,
+        &uart0_device,
+        &uart1_device,
+        &uart2_device,
+        &uart3_device,
+        &smc_device,
+        &clcd_device,
+        &sctl_device,
+        &wdog_device,
+        &gpio0_device,
+        &gpio1_device,
+        &gpio2_device,
+        &rtc_device,
+        &sci0_device,
+        &ssp0_device,
+        &aaci_device,
+        &mmc0_device,
+        &kmi0_device,
+        &kmi1_device,
+};
+
+/*
+ * RealView PB11MPCore platform devices
+ */
+static struct resource realview_pb11mp_flash_resource[] = {
+        [0] = {
+                .start          = REALVIEW_PB11MP_FLASH0_BASE,
+                .end            = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = REALVIEW_PB11MP_FLASH1_BASE,
+                .end            = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct resource realview_pb11mp_smsc911x_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PB11MP_ETH_BASE,
+                .end            = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_TC11MP_ETH,
+                .end            = IRQ_TC11MP_ETH,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device realview_pb11mp_smsc911x_device = {
+        .name           = "smc911x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(realview_pb11mp_smsc911x_resources),
+        .resource       = realview_pb11mp_smsc911x_resources,
+};
+
+struct resource realview_pb11mp_cf_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PB11MP_CF_BASE,
+                .end            = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = REALVIEW_PB11MP_CF_MEM_BASE,
+                .end            = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start          = -1,           /* FIXME: Find correct irq */
+                .end            = -1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device realview_pb11mp_cf_device = {
+        .name           = "compactflash",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(realview_pb11mp_cf_resources),
+        .resource       = realview_pb11mp_cf_resources,
+};
+
+static void __init gic_init_irq(void)
+{
+        unsigned int pldctrl;
+
+        /* new irq mode with no DCC */
+        writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
+        pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
+        pldctrl |= 2 << 22;
+        writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
+        writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
+
+        /* ARM11MPCore test chip GIC, primary */
+        gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
+        gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
+        gic_cpu_init(0, gic_cpu_base_addr);
+
+        /* board GIC, secondary */
+        gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
+        gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
+        gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
+}
+
+static void __init realview_pb11mp_timer_init(void)
+{
+        timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
+        timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
+        timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
+        timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
+
+#ifdef CONFIG_LOCAL_TIMERS
+        twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE);
+        twd_size = REALVIEW_TC11MP_TWD_SIZE;
+#endif
+        realview_timer_init(IRQ_TC11MP_TIMER0_1);
+}
+
+static struct sys_timer realview_pb11mp_timer = {
+        .init           = realview_pb11mp_timer_init,
+};
+
+static void __init realview_pb11mp_init(void)
+{
+        int i;
+
+#ifdef CONFIG_CACHE_L2X0
+        /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+         * Bits:  .... ...0 0111 1001 0000 .... .... .... */
+        l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
+
+        clk_register(&realview_clcd_clk);
+
+        realview_flash_register(realview_pb11mp_flash_resource,
+                                ARRAY_SIZE(realview_pb11mp_flash_resource));
+        platform_device_register(&realview_pb11mp_smsc911x_device);
+        platform_device_register(&realview_i2c_device);
+        platform_device_register(&realview_pb11mp_cf_device);
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+
+#ifdef CONFIG_LEDS
+        leds_event = realview_leds_event;
+#endif
+}
+
+MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .phys_io        = REALVIEW_PB11MP_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .map_io         = realview_pb11mp_map_io,
+        .init_irq       = gic_init_irq,
+        .timer          = &realview_pb11mp_timer,
+        .init_machine   = realview_pb11mp_init,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index e2079cf9266f..cd3dc0834b3b 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -97,6 +97,13 @@ config BAST_PC104_IRQ
           Say Y here to enable the PC104 IRQ routing on the
           Simtec BAST (EB2410ITX)
 
+config MACH_TCT_HAMMER
+        bool "TCT Hammer Board"
+        select CPU_S3C2410
+        help
+           Say Y here if you are using the TinCanTools Hammer Board
+           <http://www.tincantools.com>
+
 config MACH_VR1000
         bool "Thorcom VR1000"
         select PM_SIMTEC if PM
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 3e7a85594d9c..cabc13ce09e4 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -27,5 +27,6 @@ obj-$(CONFIG_ARCH_BAST)		+= mach-bast.o usb-simtec.o
 obj-$(CONFIG_MACH_OTOM)         += mach-otom.o
 obj-$(CONFIG_MACH_AML_M5900)    += mach-amlm5900.o
 obj-$(CONFIG_BAST_PC104_IRQ)    += bast-irq.o
+obj-$(CONFIG_MACH_TCT_HAMMER)   += mach-tct_hammer.o
 obj-$(CONFIG_MACH_VR1000)       += mach-vr1000.o usb-simtec.o
 obj-$(CONFIG_MACH_QT2410)       += mach-qt2410.o
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 66175471fff3..661a2358ac22 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/dm9000.h>
@@ -236,6 +237,36 @@ static struct platform_device bast_device_nor = {
 
 /* NAND Flash on BAST board */
 
+#ifdef CONFIG_PM
+static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
+{
+        /* ensure that an nRESET is not generated on resume. */
+        s3c2410_gpio_setpin(S3C2410_GPA21, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
+
+        return 0;
+}
+
+static int bast_pm_resume(struct sys_device *sd)
+{
+        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
+        return 0;
+}
+
+#else
+#define bast_pm_suspend NULL
+#define bast_pm_resume NULL
+#endif
+
+static struct sysdev_class bast_pm_sysclass = {
+        .name           = "mach-bast",
+        .suspend        = bast_pm_suspend,
+        .resume         = bast_pm_resume,
+};
+
+static struct sys_device bast_pm_sysdev = {
+        .cls            = &bast_pm_sysclass,
+};
 
 static int smartmedia_map[] = { 0 };
 static int chip0_map[] = { 1 };
@@ -561,10 +592,10 @@ static void __init bast_map_io(void)
 {
         /* initialise the clocks */
 
-        s3c24xx_dclk0.parent = NULL;
+        s3c24xx_dclk0.parent = &clk_upll;
         s3c24xx_dclk0.rate   = 12*1000*1000;
 
-        s3c24xx_dclk1.parent = NULL;
+        s3c24xx_dclk1.parent = &clk_upll;
         s3c24xx_dclk1.rate   = 24*1000*1000;
 
         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
@@ -586,6 +617,9 @@ static void __init bast_map_io(void)
 
 static void __init bast_init(void)
 {
+        sysdev_class_register(&bast_pm_sysclass);
+        sysdev_register(&bast_pm_sysdev);
+
         s3c24xx_fb_set_platdata(&bast_fb_info);
         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 }
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
new file mode 100644
index 000000000000..d90d445ccfb4
--- /dev/null
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -0,0 +1,160 @@
+/* linux/arch/arm/mach-s3c2410/mach-tct_hammer.c
+ *
+ * Copyright (c) 2007 TinCanTools
+ *      David Anders <danders@amltd.com>
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * @History:
+ * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ ***********************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+#ifdef CONFIG_MTD_PARTITIONS
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+
+static struct resource tct_hammer_nor_resource = {
+                .start = 0x00000000,
+                .end   = 0x01000000 - 1,
+                .flags = IORESOURCE_MEM,
+};
+
+static struct mtd_partition tct_hammer_mtd_partitions[] = {
+        {
+                .name           = "System",
+                .size           = 0x240000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,  /* force read-only */
+        }, {
+                .name           = "JFFS2",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = MTDPART_OFS_APPEND,
+        }
+};
+
+static struct physmap_flash_data tct_hammer_flash_data = {
+        .width          = 2,
+        .parts          = tct_hammer_mtd_partitions,
+        .nr_parts       = ARRAY_SIZE(tct_hammer_mtd_partitions),
+};
+
+static struct platform_device tct_hammer_device_nor = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev = {
+                        .platform_data = &tct_hammer_flash_data,
+                },
+        .num_resources  = 1,
+        .resource       = &tct_hammer_nor_resource,
+};
+
+#endif
+
+static struct map_desc tct_hammer_iodesc[] __initdata = {
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        }
+};
+
+
+static struct platform_device *tct_hammer_devices[] __initdata = {
+        &s3c_device_adc,
+        &s3c_device_wdt,
+        &s3c_device_i2c,
+        &s3c_device_usb,
+        &s3c_device_rtc,
+        &s3c_device_usbgadget,
+        &s3c_device_sdi,
+#ifdef CONFIG_MTD_PARTITIONS
+        &tct_hammer_device_nor,
+#endif
+};
+
+static void __init tct_hammer_map_io(void)
+{
+        s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
+        s3c24xx_init_clocks(0);
+        s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
+}
+
+static void __init tct_hammer_init(void)
+{
+        platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
+}
+
+MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .map_io         = tct_hammer_map_io,
+        .init_irq       = s3c24xx_init_irq,
+        .init_machine   = tct_hammer_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 3aade7b78fe5..c56423373ff3 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -393,7 +393,7 @@ static void __init vr1000_map_io(void)
 {
         /* initialise clock sources */
 
-        s3c24xx_dclk0.parent = NULL;
+        s3c24xx_dclk0.parent = &clk_upll;
         s3c24xx_dclk0.rate   = 12*1000*1000;
 
         s3c24xx_dclk1.parent = NULL;
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index abf1599c9f97..98a0de924c22 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -175,7 +175,7 @@ void __init s3c2412_init_clocks(int xtal)
         /* work out clock scalings */
 
         hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
-        hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
+        hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
         pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
 
         /* print brieft summary of clocks, etc */
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 3d3dfa95db8e..47258915a2f9 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -413,10 +413,10 @@ static void __init anubis_map_io(void)
 {
         /* initialise the clocks */
 
-        s3c24xx_dclk0.parent = NULL;
+        s3c24xx_dclk0.parent = &clk_upll;
         s3c24xx_dclk0.rate   = 12*1000*1000;
 
-        s3c24xx_dclk1.parent = NULL;
+        s3c24xx_dclk1.parent = &clk_upll;
         s3c24xx_dclk1.rate   = 24*1000*1000;
 
         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 78af7664988b..8a8acdbd072d 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -18,6 +18,7 @@
 #include <linux/device.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
+#include <linux/clk.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -344,10 +345,10 @@ static void __init osiris_map_io(void)
 
         /* initialise the clocks */
 
-        s3c24xx_dclk0.parent = NULL;
+        s3c24xx_dclk0.parent = &clk_upll;
         s3c24xx_dclk0.rate   = 12*1000*1000;
 
-        s3c24xx_dclk1.parent = NULL;
+        s3c24xx_dclk1.parent = &clk_upll;
         s3c24xx_dclk1.rate   = 24*1000*1000;
 
         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 7a61e8d33ab7..8e0244631d65 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o
+obj-y := clock.o generic.o gpio.o irq.o dma.o time.o #nmi-oopser.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 5c84c604ed86..0c2fa1c4fb4c 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -139,37 +139,6 @@ unsigned long long sched_clock(void)
         return v;
 }
 
-int gpio_direction_input(unsigned gpio)
-{
-        unsigned long flags;
-
-        if (gpio > GPIO_MAX)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        GPDR &= ~GPIO_GPIO(gpio);
-        local_irq_restore(flags);
-        return 0;
-}
-
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-        unsigned long flags;
-
-        if (gpio > GPIO_MAX)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        gpio_set_value(gpio, value);
-        GPDR |= GPIO_GPIO(gpio);
-        local_irq_restore(flags);
-        return 0;
-}
-
-EXPORT_SYMBOL(gpio_direction_output);
-
 /*
  * Default power-off for SA1100
  */
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index f085d68e568e..793c2e6c991f 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -9,6 +9,7 @@ struct sys_timer;
 extern struct sys_timer sa1100_timer;
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
+extern void __init sa1100_init_gpio(void);
 
 #define SET_BANK(__nr,__start,__size) \
         mi->bank[__nr].start = (__start), \
diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c
new file mode 100644
index 000000000000..372f1f4f54a1
--- /dev/null
+++ b/arch/arm/mach-sa1100/gpio.c
@@ -0,0 +1,65 @@
+/*
+ * linux/arch/arm/mach-sa1100/gpio.c
+ *
+ * Generic SA-1100 GPIO handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/gpio.h>
+#include <asm/hardware.h>
+#include "generic.h"
+
+static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return GPLR & GPIO_GPIO(offset);
+}
+
+static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        if (value)
+                GPSR = GPIO_GPIO(offset);
+        else
+                GPCR = GPIO_GPIO(offset);
+}
+
+static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        GPDR &= ~GPIO_GPIO(offset);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        sa1100_gpio_set(chip, offset, value);
+        GPDR |= GPIO_GPIO(offset);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static struct gpio_chip sa1100_gpio_chip = {
+        .label                  = "gpio",
+        .direction_input        = sa1100_direction_input,
+        .direction_output       = sa1100_direction_output,
+        .set                    = sa1100_gpio_set,
+        .get                    = sa1100_gpio_get,
+        .base                   = 0,
+        .ngpio                  = GPIO_MAX + 1,
+};
+
+void __init sa1100_init_gpio(void)
+{
+        gpiochip_add(&sa1100_gpio_chip);
+}
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3dc17d7bf38e..fa0403af7eec 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -347,4 +347,6 @@ void __init sa1100_init_irq(void)
          */
         set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
         set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
+
+        sa1100_init_gpio();
 }
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index c2677368d6af..a9799cb35b74 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -13,67 +13,69 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/timex.h>
-#include <linux/signal.h>
-#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
 #include <asm/hardware.h>
 
-#define RTC_DEF_DIVIDER         (32768 - 1)
-#define RTC_DEF_TRIM            0
+#define MIN_OSCR_DELTA 2
 
-static int sa1100_set_rtc(void)
+static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
 {
-        unsigned long current_time = xtime.tv_sec;
+        struct clock_event_device *c = dev_id;
 
-        if (RTSR & RTSR_ALE) {
-                /* make sure not to forward the clock over an alarm */
-                unsigned long alarm = RTAR;
-                if (current_time >= alarm && alarm >= RCNR)
-                        return -ERESTARTSYS;
-        }
-        RCNR = current_time;
-        return 0;
-}
+        /* Disarm the compare/match, signal the event. */
+        OIER &= ~OIER_E0;
+        OSSR = OSSR_M0;
+        c->event_handler(c);
 
-#ifdef CONFIG_NO_IDLE_HZ
-static unsigned long initial_match;
-static int match_posponed;
-#endif
+        return IRQ_HANDLED;
+}
 
-static irqreturn_t
-sa1100_timer_interrupt(int irq, void *dev_id)
+static int
+sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
 {
-        unsigned int next_match;
+        unsigned long flags, next, oscr;
 
-#ifdef CONFIG_NO_IDLE_HZ
-        if (match_posponed) {
-                match_posponed = 0;
-                OSMR0 = initial_match;
-        }
-#endif
+        raw_local_irq_save(flags);
+        OIER |= OIER_E0;
+        next = OSCR + delta;
+        OSMR0 = next;
+        oscr = OSCR;
+        raw_local_irq_restore(flags);
 
-        /*
-         * Loop until we get ahead of the free running timer.
-         * This ensures an exact clock tick count and time accuracy.
-         * Since IRQs are disabled at this point, coherence between
-         * lost_ticks(updated in do_timer()) and the match reg value is
-         * ensured, hence we can use do_gettimeofday() from interrupt
-         * handlers.
-         */
-        do {
-                timer_tick();
-                OSSR = OSSR_M0;  /* Clear match on timer 0 */
-                next_match = (OSMR0 += LATCH);
-        } while ((signed long)(next_match - OSCR) <= 0);
+        return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
+}
 
-        return IRQ_HANDLED;
+static void
+sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
+{
+        unsigned long flags;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                raw_local_irq_save(flags);
+                OIER &= ~OIER_E0;
+                OSSR = OSSR_M0;
+                raw_local_irq_restore(flags);
+                break;
+
+        case CLOCK_EVT_MODE_RESUME:
+        case CLOCK_EVT_MODE_PERIODIC:
+                break;
+        }
 }
 
-static struct irqaction sa1100_timer_irq = {
-        .name           = "SA11xx Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = sa1100_timer_interrupt,
+static struct clock_event_device ckevt_sa1100_osmr0 = {
+        .name           = "osmr0",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .rating         = 200,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_next_event = sa1100_osmr0_set_next_event,
+        .set_mode       = sa1100_osmr0_set_mode,
 };
 
 static cycle_t sa1100_read_oscr(void)
@@ -90,62 +92,34 @@ static struct clocksource cksrc_sa1100_oscr = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static struct irqaction sa1100_timer_irq = {
+        .name           = "ost0",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = sa1100_ost0_interrupt,
+        .dev_id         = &ckevt_sa1100_osmr0,
+};
+
 static void __init sa1100_timer_init(void)
 {
-        unsigned long flags;
-
-        set_rtc = sa1100_set_rtc;
-
         OIER = 0;               /* disable any timer interrupts */
         OSSR = 0xf;             /* clear status on all timers */
-        setup_irq(IRQ_OST0, &sa1100_timer_irq);
-        local_irq_save(flags);
-        OIER = OIER_E0;         /* enable match on timer 0 to cause interrupts */
-        OSMR0 = OSCR + LATCH;   /* set initial match */
-        local_irq_restore(flags);
+
+        ckevt_sa1100_osmr0.mult =
+                div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
+        ckevt_sa1100_osmr0.max_delta_ns =
+                clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
+        ckevt_sa1100_osmr0.min_delta_ns =
+                clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
 
         cksrc_sa1100_oscr.mult =
                 clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
 
-        clocksource_register(&cksrc_sa1100_oscr);
-}
-
-#ifdef CONFIG_NO_IDLE_HZ
-static int sa1100_dyn_tick_enable_disable(void)
-{
-        /* nothing to do */
-        return 0;
-}
-
-static void sa1100_dyn_tick_reprogram(unsigned long ticks)
-{
-        if (ticks > 1) {
-                initial_match = OSMR0;
-                OSMR0 = initial_match + ticks * LATCH;
-                match_posponed = 1;
-        }
-}
+        setup_irq(IRQ_OST0, &sa1100_timer_irq);
 
-static irqreturn_t
-sa1100_dyn_tick_handler(int irq, void *dev_id)
-{
-        if (match_posponed) {
-                match_posponed = 0;
-                OSMR0 = initial_match;
-                if ((signed long)(initial_match - OSCR) <= 0)
-                        return sa1100_timer_interrupt(irq, dev_id);
-        }
-        return IRQ_NONE;
+        clocksource_register(&cksrc_sa1100_oscr);
+        clockevents_register_device(&ckevt_sa1100_osmr0);
 }
 
-static struct dyn_tick_timer sa1100_dyn_tick = {
-        .enable         = sa1100_dyn_tick_enable_disable,
-        .disable        = sa1100_dyn_tick_enable_disable,
-        .reprogram      = sa1100_dyn_tick_reprogram,
-        .handler        = sa1100_dyn_tick_handler,
-};
-#endif
-
 #ifdef CONFIG_PM
 unsigned long osmr[4], oier;
 
@@ -181,7 +155,4 @@ struct sys_timer sa1100_timer = {
         .init           = sa1100_timer_init,
         .suspend        = sa1100_timer_suspend,
         .resume         = sa1100_timer_resume,
-#ifdef CONFIG_NO_IDLE_HZ
-        .dyn_tick       = &sa1100_dyn_tick,
-#endif
 };
diff --git a/arch/arm/mach-versatile/clock.c b/arch/arm/mach-versatile/clock.c
index 9858c96560e2..9336508ec0b2 100644
--- a/arch/arm/mach-versatile/clock.c
+++ b/arch/arm/mach-versatile/clock.c
@@ -17,7 +17,6 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 
-#include <asm/semaphore.h>
 #include <asm/hardware/icst307.h>
 
 #include "clock.h"
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 76348f060f27..746cbb7c8e95 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -18,6 +18,7 @@ config CPU_ARM610
         select CPU_CP15_MMU
         select CPU_COPY_V3 if MMU
         select CPU_TLB_V3 if MMU
+        select CPU_PABRT_NOIFAR
         help
           The ARM610 is the successor to the ARM3 processor
           and was produced by VLSI Technology Inc.
@@ -49,6 +50,7 @@ config CPU_ARM710
         select CPU_CP15_MMU
         select CPU_COPY_V3 if MMU
         select CPU_TLB_V3 if MMU
+        select CPU_PABRT_NOIFAR
         help
           A 32-bit RISC microprocessor based on the ARM7 processor core
           designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -64,6 +66,7 @@ config CPU_ARM720T
         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
         select CPU_32v4T
         select CPU_ABRT_LV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -113,6 +116,7 @@ config CPU_ARM920T
         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -135,6 +139,7 @@ config CPU_ARM922T
         default y if ARCH_LH7A40X || ARCH_KS8695
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -155,6 +160,7 @@ config CPU_ARM925T
         default y if ARCH_OMAP15XX
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -175,6 +181,7 @@ config CPU_ARM926T
         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
         select CPU_32v5
         select CPU_ABRT_EV5TJ
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU
@@ -226,6 +233,7 @@ config CPU_ARM1020
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -244,6 +252,7 @@ config CPU_ARM1020E
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -257,6 +266,7 @@ config CPU_ARM1022
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU # can probably do better
@@ -275,6 +285,7 @@ config CPU_ARM1026
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU # can probably do better
@@ -293,6 +304,7 @@ config CPU_SA110
         select CPU_32v3 if ARCH_RPC
         select CPU_32v4 if !ARCH_RPC
         select CPU_ABRT_EV4
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WB
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -314,6 +326,7 @@ config CPU_SA1100
         default y
         select CPU_32v4
         select CPU_ABRT_EV4
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WB
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -326,6 +339,7 @@ config CPU_XSCALE
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_TLB_V4WBI if MMU
@@ -345,10 +359,11 @@ config CPU_XSC3
 # Feroceon
 config CPU_FEROCEON
         bool
-        depends on ARCH_ORION
+        depends on ARCH_ORION5X
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU
@@ -366,11 +381,12 @@ config CPU_FEROCEON_OLD_ID
 # ARMv6
 config CPU_V6
         bool "Support ARM V6 processor"
-        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
+        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
         default y if ARCH_MX3
         default y if ARCH_MSM7X00A
         select CPU_32v6
         select CPU_ABRT_EV6
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V6
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
@@ -393,10 +409,11 @@ config CPU_32v6K
 # ARMv7
 config CPU_V7
         bool "Support ARM V7 processor"
-        depends on ARCH_INTEGRATOR
+        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
         select CPU_32v6K
         select CPU_32v7
         select CPU_ABRT_EV7
+        select CPU_PABRT_IFAR
         select CPU_CACHE_V7
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
@@ -458,6 +475,12 @@ config CPU_ABRT_EV6
 config CPU_ABRT_EV7
         bool
 
+config CPU_PABRT_IFAR
+        bool
+
+config CPU_PABRT_NOIFAR
+        bool
+
 # The cache model
 config CPU_CACHE_V3
         bool
@@ -572,6 +595,13 @@ config ARM_THUMB
 
           If you don't know what this all is, saying Y is a safe choice.
 
+config ARM_THUMBEE
+        bool "Enable ThumbEE CPU extension"
+        depends on CPU_V7
+        help
+          Say Y here if you have a CPU with the ThumbEE extension and code to
+          make use of it. Say N for code that can run on CPUs without ThumbEE.
+
 config CPU_BIG_ENDIAN
         bool "Build big-endian kernel"
         depends on ARCH_SUPPORTS_BIG_ENDIAN
@@ -671,5 +701,9 @@ config OUTER_CACHE
         default n
 
 config CACHE_L2X0
-        bool
+        bool "Enable the L2x0 outer cache controller"
+        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
+        default y
         select OUTER_CACHE
+        help
+          This option enables the L2x0 PrimeCell.
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index ec00f26bffa4..b657f1719af0 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -48,8 +48,6 @@ void show_mem(void)
 
         printk("Mem-info:\n");
         show_free_areas();
-        printk("Free swap:       %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
-
         for_each_online_node(node) {
                 pg_data_t *n = NODE_DATA(node);
                 struct page *map = n->node_mem_map - n->node_start_pfn;
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 700c04d6996e..32fd7ea533f2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -478,6 +478,7 @@ arm1020_processor_functions:
         .word   cpu_arm1020_dcache_clean_area
         .word   cpu_arm1020_switch_mm
         .word   cpu_arm1020_set_pte_ext
+        .word   pabort_noifar
         .size   arm1020_processor_functions, . - arm1020_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 1cc206ab5eae..fe2b0ae70274 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -459,6 +459,7 @@ arm1020e_processor_functions:
         .word   cpu_arm1020e_dcache_clean_area
         .word   cpu_arm1020e_switch_mm
         .word   cpu_arm1020e_set_pte_ext
+        .word   pabort_noifar
         .size   arm1020e_processor_functions, . - arm1020e_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index aff0ea08e2f8..06dde678e19d 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -442,6 +442,7 @@ arm1022_processor_functions:
         .word   cpu_arm1022_dcache_clean_area
         .word   cpu_arm1022_switch_mm
         .word   cpu_arm1022_set_pte_ext
+        .word   pabort_noifar
         .size   arm1022_processor_functions, . - arm1022_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 65e43a109085..f5506e6e681e 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -437,6 +437,7 @@ arm1026_processor_functions:
         .word   cpu_arm1026_dcache_clean_area
         .word   cpu_arm1026_switch_mm
         .word   cpu_arm1026_set_pte_ext
+        .word   pabort_noifar
         .size   arm1026_processor_functions, . - arm1026_processor_functions
 
         .section .rodata
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 123a7dc7a433..14b6a95c8d45 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -300,6 +300,7 @@ ENTRY(arm6_processor_functions)
                 .word   cpu_arm6_dcache_clean_area
                 .word   cpu_arm6_switch_mm
                 .word   cpu_arm6_set_pte_ext
+                .word   pabort_noifar
                 .size   arm6_processor_functions, . - arm6_processor_functions
 
 /*
@@ -316,6 +317,7 @@ ENTRY(arm7_processor_functions)
                 .word   cpu_arm7_dcache_clean_area
                 .word   cpu_arm7_switch_mm
                 .word   cpu_arm7_set_pte_ext
+                .word   pabort_noifar
                 .size   arm7_processor_functions, . - arm7_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index dc763be43362..ca5e7aac2da7 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -205,6 +205,7 @@ ENTRY(arm720_processor_functions)
                 .word   cpu_arm720_dcache_clean_area
                 .word   cpu_arm720_switch_mm
                 .word   cpu_arm720_set_pte_ext
+                .word   pabort_noifar
                 .size   arm720_processor_functions, . - arm720_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 75c945ed6c4d..0170d4f466ea 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -424,6 +424,7 @@ arm920_processor_functions:
         .word   cpu_arm920_dcache_clean_area
         .word   cpu_arm920_switch_mm
         .word   cpu_arm920_set_pte_ext
+        .word   pabort_noifar
         .size   arm920_processor_functions, . - arm920_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index ffb751b877ff..b7952493d404 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -428,6 +428,7 @@ arm922_processor_functions:
         .word   cpu_arm922_dcache_clean_area
         .word   cpu_arm922_switch_mm
         .word   cpu_arm922_set_pte_ext
+        .word   pabort_noifar
         .size   arm922_processor_functions, . - arm922_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 44c2c997819f..e2988eba4cf6 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -491,6 +491,7 @@ arm925_processor_functions:
         .word   cpu_arm925_dcache_clean_area
         .word   cpu_arm925_switch_mm
         .word   cpu_arm925_set_pte_ext
+        .word   pabort_noifar
         .size   arm925_processor_functions, . - arm925_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 194ef48968e6..62f7d1dfe016 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -444,6 +444,7 @@ arm926_processor_functions:
         .word   cpu_arm926_dcache_clean_area
         .word   cpu_arm926_switch_mm
         .word   cpu_arm926_set_pte_ext
+        .word   pabort_noifar
         .size   arm926_processor_functions, . - arm926_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index fa0dc7e6f0ea..2f169b28e938 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -430,6 +430,7 @@ feroceon_processor_functions:
         .word   cpu_feroceon_dcache_clean_area
         .word   cpu_feroceon_switch_mm
         .word   cpu_feroceon_set_pte_ext
+        .word   pabort_noifar
         .size   feroceon_processor_functions, . - feroceon_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 6e226e12989f..4db3d6299a2b 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -223,6 +223,7 @@ ENTRY(sa110_processor_functions)
         .word   cpu_sa110_dcache_clean_area
         .word   cpu_sa110_switch_mm
         .word   cpu_sa110_set_pte_ext
+        .word   pabort_noifar
         .size   sa110_processor_functions, . - sa110_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 9afb11d089fe..3cdef043760f 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -238,6 +238,7 @@ ENTRY(sa1100_processor_functions)
         .word   cpu_sa1100_dcache_clean_area
         .word   cpu_sa1100_switch_mm
         .word   cpu_sa1100_set_pte_ext
+        .word   pabort_noifar
         .size   sa1100_processor_functions, . - sa1100_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index eb42e5b94863..bf760ea2f789 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -17,10 +17,6 @@
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
-#ifdef CONFIG_SMP
-#include <asm/hardware/arm_scu.h>
-#endif
-
 #include "proc-macros.S"
 
 #define D_CACHE_LINE_SIZE       32
@@ -187,20 +183,10 @@ cpu_v6_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-        /* Set up the SCU on core 0 only */
-        mrc     p15, 0, r0, c0, c0, 5           @ CPU core number
-        ands    r0, r0, #15
-        ldreq   r0, =SCU_BASE
-        ldreq   r5, [r0, #SCU_CTRL]
-        orreq   r5, r5, #1
-        streq   r5, [r0, #SCU_CTRL]
-
-#ifndef CONFIG_CPU_DCACHE_DISABLE
         mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
         orr     r0, r0, #0x20
         mcr     p15, 0, r0, c1, c0, 1
 #endif
-#endif
 
         mov     r0, #0
         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
@@ -240,6 +226,7 @@ ENTRY(v6_processor_functions)
         .word   cpu_v6_dcache_clean_area
         .word   cpu_v6_switch_mm
         .word   cpu_v6_set_pte_ext
+        .word   pabort_noifar
         .size   v6_processor_functions, . - v6_processor_functions
 
         .type   cpu_arch_name, #object
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index e0acc5ae6f6f..a1d7331cd64c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -212,6 +212,7 @@ ENTRY(v7_processor_functions)
         .word   cpu_v7_dcache_clean_area
         .word   cpu_v7_switch_mm
         .word   cpu_v7_set_pte_ext
+        .word   pabort_ifar
         .size   v7_processor_functions, . - v7_processor_functions
 
         .type   cpu_arch_name, #object
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 016690b9d564..1a6d89823dff 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -534,6 +534,7 @@ ENTRY(xscale_processor_functions)
         .word   cpu_xscale_dcache_clean_area
         .word   cpu_xscale_switch_mm
         .word   cpu_xscale_set_pte_ext
+        .word   pabort_noifar
         .size   xscale_processor_functions, . - xscale_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 98d01517b563..d9bc15a69e5d 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -24,6 +24,7 @@
 #include <asm/hardware.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/iop3xx.h>
+#include <asm/mach-types.h>
 
 // #define DEBUG
 
@@ -209,8 +210,11 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
         res[1].flags = IORESOURCE_MEM;
         request_resource(&iomem_resource, &res[1]);
 
-        sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
-        sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;
+        /*
+         * Use whatever translation is already setup.
+         */
+        sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
+        sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
 
         sys->resource[0] = &res[0];
         sys->resource[1] = &res[1];
@@ -250,11 +254,11 @@ void __init iop3xx_atu_setup(void)
         *IOP3XX_IATVR2 = PHYS_OFFSET;
 
         /* Outbound window 0 */
-        *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
+        *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
         *IOP3XX_OUMWTVR0 = 0;
 
         /* Outbound window 1 */
-        *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
+        *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE;
         *IOP3XX_OUMWTVR1 = 0;
 
         /* BAR 3 ( Disabled ) */
@@ -265,7 +269,7 @@ void __init iop3xx_atu_setup(void)
 
         /* Setup the I/O Bar
          */
-        *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
+        *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
 
         /* Enable inbound and outbound cycles
          */
@@ -322,34 +326,59 @@ void __init iop3xx_atu_disable(void)
 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
 int init_atu;
 
-void __init iop3xx_pci_preinit(void)
+int iop3xx_get_init_atu(void) {
+        /* check if default has been overridden */
+        if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
+                return init_atu;
+        else
+                return IOP3XX_INIT_ATU_DISABLE;
+}
+
+static void __init iop3xx_atu_debug(void)
 {
-        if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
-                iop3xx_atu_disable();
-                iop3xx_atu_setup();
-        }
+        DBG("PCI: Intel IOP3xx PCI init.\n");
+        DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
+                *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
+        DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
+                *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
+        DBG("PCI: Outbound IO window: PCI 0x%08x\n",
+                *IOP3XX_OIOWTVR);
+
+        DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
+        DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
+                *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
+        DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
+        DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
+
+        DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
 
-        DBG("PCI:  Intel 803xx PCI init code.\n");
         DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
-        DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
-                        *IOP3XX_OMWTVR0,
-                        *IOP3XX_OIOWTVR);
         DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
-        DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
-                        *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
-        DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
-        DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
-                        *IOP3XX_IABAR1, *IOP3XX_IALR1);
-        DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
-                        *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
-        DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
-                        *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
-        DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
-                        *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
 
         hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
 }
 
+/* for platforms that might be host-bus-adapters */
+void __init iop3xx_pci_preinit_cond(void)
+{
+        if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
+                iop3xx_atu_disable();
+                iop3xx_atu_setup();
+                iop3xx_atu_debug();
+        }
+}
+
+void __init iop3xx_pci_preinit(void)
+{
+        iop3xx_atu_disable();
+        iop3xx_atu_setup();
+        iop3xx_atu_debug();
+}
+
 /* allow init_atu to be user overridden */
 static int __init iop3xx_init_atu_setup(char *str)
 {
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 03a65c0dfb60..bb6e12738fb3 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,7 +4,7 @@ menu "Freescale MXC Implementations"
 
 choice
         prompt "MXC/iMX System Type"
-        default 0
+        default ARCH_MX3
 
 config ARCH_MX3
         bool "MX3-based"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 66ad9c2b6d64..f96dc0362068 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -4,7 +4,3 @@
 
 # Common support
 obj-y := irq.o
-
-obj-m :=
-obj-n :=
-obj-  :=
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 87d253bc3d3c..2ad5a6917b3f 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -19,21 +19,13 @@
 #include <asm/mach/irq.h>
 #include <asm/arch/common.h>
 
-/*!
- * Disable interrupt number "irq" in the AVIC
- *
- * @param  irq          interrupt source number
- */
+/* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
         __raw_writel(irq, AVIC_INTDISNUM);
 }
 
-/*!
- * Enable interrupt number "irq" in the AVIC
- *
- * @param  irq          interrupt source number
- */
+/* Enable interrupt number "irq" in the AVIC */
 static void mxc_unmask_irq(unsigned int irq)
 {
         __raw_writel(irq, AVIC_INTENNUM);
@@ -45,7 +37,7 @@ static struct irq_chip mxc_avic_chip = {
         .unmask = mxc_unmask_irq,
 };
 
-/*!
+/*
  * This function initializes the AVIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
  * to the kernel for each interrupt source.
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 8f56c255d1ee..bc639a30d6d1 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,8 +9,6 @@ obj-m :=
 obj-n :=
 obj-  :=
 
-obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
-
 # OCPI interconnect support for 1710, 1610 and 5912
 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 0a603242f367..72d34a23a2ec 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -23,7 +23,6 @@
 #include <linux/platform_device.h>
 
 #include <asm/io.h>
-#include <asm/semaphore.h>
 
 #include <asm/arch/clock.h>
 
@@ -304,6 +303,23 @@ void propagate_rate(struct clk * tclk)
         }
 }
 
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clocks, node) {
+                if (unlikely(!clkp->parent) && likely((u32)clkp->recalc))
+                        clkp->recalc(clkp);
+        }
+}
+
 int clk_register(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
@@ -358,6 +374,30 @@ void clk_allow_idle(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_allow_idle);
 
+void clk_enable_init_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clocks, node) {
+                if (clkp->flags & ENABLE_ON_INIT)
+                        clk_enable(clkp);
+        }
+}
+EXPORT_SYMBOL(clk_enable_init_clocks);
+
+#ifdef CONFIG_CPU_FREQ
+void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (arch_clock->clk_init_cpufreq_table)
+                arch_clock->clk_init_cpufreq_table(table);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_init_cpufreq_table);
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
@@ -396,3 +436,4 @@ int __init clk_init(struct clk_functions * custom_clocks)
 
         return 0;
 }
+
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 4f0f9c4e938e..bd1cef2c3c14 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -27,11 +27,16 @@
 #include <asm/setup.h>
 
 #include <asm/arch/board.h>
+#include <asm/arch/control.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/fpga.h>
 
 #include <asm/arch/clock.h>
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+# include "../mach-omap2/sdrc.h"
+#endif
+
 #define NO_LENGTH_CHECK 0xffffffff
 
 unsigned char omap_bootloader_tag[512];
@@ -171,8 +176,8 @@ console_initcall(omap_add_serial_console);
 
 #if defined(CONFIG_ARCH_OMAP16XX)
 #define TIMER_32K_SYNCHRONIZED          0xfffbc410
-#elif defined(CONFIG_ARCH_OMAP24XX)
-#define TIMER_32K_SYNCHRONIZED          (OMAP24XX_32KSYNCT_BASE + 0x10)
+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#define TIMER_32K_SYNCHRONIZED          (OMAP2_32KSYNCT_BASE + 0x10)
 #endif
 
 #ifdef  TIMER_32K_SYNCHRONIZED
@@ -193,12 +198,35 @@ static struct clocksource clocksource_32k = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+/*
+ * Rounds down to nearest nsec.
+ */
+unsigned long long omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
+{
+        return cyc2ns(&clocksource_32k, ticks_32k);
+}
+
+/*
+ * Returns current time from boot in nsecs. It's OK for this to wrap
+ * around for now, as it's just a relative time stamp.
+ */
+unsigned long long sched_clock(void)
+{
+        return omap_32k_ticks_to_nsecs(omap_32k_read());
+}
+
 static int __init omap_init_clocksource_32k(void)
 {
         static char err[] __initdata = KERN_ERR
                         "%s: can't register clocksource!\n";
 
-        if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
+        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
+                struct clk *sync_32k_ick;
+
+                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
+                if (sync_32k_ick)
+                        clk_enable(sync_32k_ick);
+
                 clocksource_32k.mult = clocksource_hz2mult(32768,
                                             clocksource_32k.shift);
 
@@ -210,3 +238,33 @@ static int __init omap_init_clocksource_32k(void)
 arch_initcall(omap_init_clocksource_32k);
 
 #endif  /* TIMER_32K_SYNCHRONIZED */
+
+/* Global address base setup code */
+
+#if defined(CONFIG_ARCH_OMAP2420)
+void __init omap2_set_globals_242x(void)
+{
+        omap2_sdrc_base = OMAP2420_SDRC_BASE;
+        omap2_sms_base = OMAP2420_SMS_BASE;
+        omap_ctrl_base_set(OMAP2420_CTRL_BASE);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2430)
+void __init omap2_set_globals_243x(void)
+{
+        omap2_sdrc_base = OMAP243X_SDRC_BASE;
+        omap2_sms_base = OMAP243X_SMS_BASE;
+        omap_ctrl_base_set(OMAP243X_CTRL_BASE);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3430)
+void __init omap2_set_globals_343x(void)
+{
+        omap2_sdrc_base = OMAP343X_SDRC_BASE;
+        omap2_sms_base = OMAP343X_SMS_BASE;
+        omap_ctrl_base_set(OMAP343X_CTRL_BASE);
+}
+#endif
+
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8c78e4e57b5c..1903a3491ee9 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -136,7 +136,6 @@ struct gpio_bank {
         u16 irq;
         u16 virtual_irq_start;
         int method;
-        u32 reserved_map;
 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         u32 suspend_wakeup;
         u32 saved_wakeup;
@@ -149,7 +148,9 @@ struct gpio_bank {
         u32 saved_fallingdetect;
         u32 saved_risingdetect;
 #endif
+        u32 level_mask;
         spinlock_t lock;
+        struct gpio_chip chip;
 };
 
 #define METHOD_MPUIO            0
@@ -538,10 +539,9 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
         }
 
-        /*
-         * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
-         * level triggering requested.
-         */
+        bank->level_mask =
+                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 }
 #endif
 
@@ -652,6 +652,12 @@ static int gpio_irq_type(unsigned irq, unsigned type)
                 irq_desc[irq].status |= type;
         }
         spin_unlock_irqrestore(&bank->lock, flags);
+
+        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+                __set_irq_handler_unlocked(irq, handle_level_irq);
+        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+                __set_irq_handler_unlocked(irq, handle_edge_irq);
+
         return retval;
 }
 
@@ -903,19 +909,17 @@ int omap_request_gpio(int gpio)
 {
         struct gpio_bank *bank;
         unsigned long flags;
+        int status;
 
         if (check_gpio(gpio) < 0)
                 return -EINVAL;
 
+        status = gpio_request(gpio, NULL);
+        if (status < 0)
+                return status;
+
         bank = get_gpio_bank(gpio);
         spin_lock_irqsave(&bank->lock, flags);
-        if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
-                printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
-                dump_stack();
-                spin_unlock_irqrestore(&bank->lock, flags);
-                return -1;
-        }
-        bank->reserved_map |= (1 << get_gpio_index(gpio));
 
         /* Set trigger to none. You need to enable the desired trigger with
          * request_irq() or set_irq_type().
@@ -945,10 +949,11 @@ void omap_free_gpio(int gpio)
                 return;
         bank = get_gpio_bank(gpio);
         spin_lock_irqsave(&bank->lock, flags);
-        if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
+        if (unlikely(!gpiochip_is_requested(&bank->chip,
+                                get_gpio_index(gpio)))) {
+                spin_unlock_irqrestore(&bank->lock, flags);
                 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
                 dump_stack();
-                spin_unlock_irqrestore(&bank->lock, flags);
                 return;
         }
 #ifdef CONFIG_ARCH_OMAP16XX
@@ -965,9 +970,9 @@ void omap_free_gpio(int gpio)
                 __raw_writel(1 << get_gpio_index(gpio), reg);
         }
 #endif
-        bank->reserved_map &= ~(1 << get_gpio_index(gpio));
         _reset_gpio(bank, gpio);
         spin_unlock_irqrestore(&bank->lock, flags);
+        gpio_free(gpio);
 }
 
 /*
@@ -1022,12 +1027,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                         isr &= 0x0000ffff;
 
                 if (cpu_class_is_omap2()) {
-                        level_mask =
-                                __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0) |
-                                __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                        level_mask &= enabled;
+                        level_mask = bank->level_mask & enabled;
                 }
 
                 /* clear edge sensitive interrupts before handler(s) are
@@ -1052,51 +1052,13 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 gpio_irq = bank->virtual_irq_start;
                 for (; isr != 0; isr >>= 1, gpio_irq++) {
                         struct irq_desc *d;
-                        int irq_mask;
+
                         if (!(isr & 1))
                                 continue;
                         d = irq_desc + gpio_irq;
-                        /* Don't run the handler if it's already running
-                         * or was disabled lazely.
-                         */
-                        if (unlikely((d->depth ||
-                                      (d->status & IRQ_INPROGRESS)))) {
-                                irq_mask = 1 <<
-                                        (gpio_irq - bank->virtual_irq_start);
-                                /* The unmasking will be done by
-                                 * enable_irq in case it is disabled or
-                                 * after returning from the handler if
-                                 * it's already running.
-                                 */
-                                _enable_gpio_irqbank(bank, irq_mask, 0);
-                                if (!d->depth) {
-                                        /* Level triggered interrupts
-                                         * won't ever be reentered
-                                         */
-                                        BUG_ON(level_mask & irq_mask);
-                                        d->status |= IRQ_PENDING;
-                                }
-                                continue;
-                        }
 
                         desc_handle_irq(gpio_irq, d);
-
-                        if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
-                                irq_mask = 1 <<
-                                        (gpio_irq - bank->virtual_irq_start);
-                                d->status &= ~IRQ_PENDING;
-                                _enable_gpio_irqbank(bank, irq_mask, 1);
-                                retrigger |= irq_mask;
-                        }
                 }
-
-                if (cpu_class_is_omap2()) {
-                        /* clear level sensitive interrupts after handler(s) */
-                        _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
-                        _clear_gpio_irqbank(bank, isr_saved & level_mask);
-                        _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
-                }
-
         }
         /* if bank has any level sensitive GPIO pin interrupt
         configured, we must unmask the bank interrupt only after
@@ -1135,6 +1097,14 @@ static void gpio_unmask_irq(unsigned int irq)
 {
         unsigned int gpio = irq - IH_GPIO_BASE;
         struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int irq_mask = 1 << get_gpio_index(gpio);
+
+        /* For level-triggered GPIOs, the clearing must be done after
+         * the HW source is cleared, thus after the handler has run */
+        if (bank->level_mask & irq_mask) {
+                _set_gpio_irqenable(bank, gpio, 0);
+                _clear_gpio_irqstatus(bank, gpio);
+        }
 
         _set_gpio_irqenable(bank, gpio, 1);
 }
@@ -1266,6 +1236,53 @@ static inline void mpuio_init(void) {}
 
 /*---------------------------------------------------------------------*/
 
+/* REVISIT these are stupid implementations!  replace by ones that
+ * don't switch on METHOD_* and which mostly avoid spinlocks
+ */
+
+static int gpio_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct gpio_bank *bank;
+        unsigned long flags;
+
+        bank = container_of(chip, struct gpio_bank, chip);
+        spin_lock_irqsave(&bank->lock, flags);
+        _set_gpio_direction(bank, offset, 1);
+        spin_unlock_irqrestore(&bank->lock, flags);
+        return 0;
+}
+
+static int gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return omap_get_gpio_datain(chip->base + offset);
+}
+
+static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct gpio_bank *bank;
+        unsigned long flags;
+
+        bank = container_of(chip, struct gpio_bank, chip);
+        spin_lock_irqsave(&bank->lock, flags);
+        _set_gpio_dataout(bank, offset, value);
+        _set_gpio_direction(bank, offset, 0);
+        spin_unlock_irqrestore(&bank->lock, flags);
+        return 0;
+}
+
+static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct gpio_bank *bank;
+        unsigned long flags;
+
+        bank = container_of(chip, struct gpio_bank, chip);
+        spin_lock_irqsave(&bank->lock, flags);
+        _set_gpio_dataout(bank, offset, value);
+        spin_unlock_irqrestore(&bank->lock, flags);
+}
+
+/*---------------------------------------------------------------------*/
+
 static int initialized;
 #if !defined(CONFIG_ARCH_OMAP3)
 static struct clk * gpio_ick;
@@ -1293,6 +1310,7 @@ static struct lock_class_key gpio_lock_class;
 static int __init _omap_gpio_init(void)
 {
         int i;
+        int gpio = 0;
         struct gpio_bank *bank;
 #if defined(CONFIG_ARCH_OMAP3)
         char clk_name[11];
@@ -1423,7 +1441,6 @@ static int __init _omap_gpio_init(void)
                 int j, gpio_count = 16;
 
                 bank = &gpio_bank[i];
-                bank->reserved_map = 0;
                 bank->base = IO_ADDRESS(bank->base);
                 spin_lock_init(&bank->lock);
                 if (bank_is_mpuio(bank))
@@ -1461,6 +1478,26 @@ static int __init _omap_gpio_init(void)
                         gpio_count = 32;
                 }
 #endif
+
+                /* REVISIT eventually switch from OMAP-specific gpio structs
+                 * over to the generic ones
+                 */
+                bank->chip.direction_input = gpio_input;
+                bank->chip.get = gpio_get;
+                bank->chip.direction_output = gpio_output;
+                bank->chip.set = gpio_set;
+                if (bank_is_mpuio(bank)) {
+                        bank->chip.label = "mpuio";
+                        bank->chip.base = OMAP_MPUIO(0);
+                } else {
+                        bank->chip.label = "gpio";
+                        bank->chip.base = gpio;
+                        gpio += gpio_count;
+                }
+                bank->chip.ngpio = gpio_count;
+
+                gpiochip_add(&bank->chip);
+
                 for (j = bank->virtual_irq_start;
                      j < bank->virtual_irq_start + gpio_count; j++) {
                         lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
@@ -1757,8 +1794,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 
                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
                         unsigned        irq, value, is_in, irqstat;
+                        const char      *label;
 
-                        if (!(bank->reserved_map & mask))
+                        label = gpiochip_is_requested(&bank->chip, j);
+                        if (!label)
                                 continue;
 
                         irq = bank->virtual_irq_start + j;
@@ -1766,13 +1805,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
                         is_in = gpio_is_input(bank, mask);
 
                         if (bank_is_mpuio(bank))
-                                seq_printf(s, "MPUIO %2d: ", j);
+                                seq_printf(s, "MPUIO %2d ", j);
                         else
-                                seq_printf(s, "GPIO %3d: ", gpio);
-                        seq_printf(s, "%s %s",
+                                seq_printf(s, "GPIO %3d ", gpio);
+                        seq_printf(s, "(%10s): %s %s",
+                                        label,
                                         is_in ? "in " : "out",
                                         value ? "hi"  : "lo");
 
+/* FIXME for at least omap2, show pullup/pulldown state */
+
                         irqstat = irq_desc[irq].status;
                         if (is_in && ((bank->suspend_wakeup & mask)
                                         || irqstat & IRQ_TYPE_SENSE_MASK)) {
@@ -1795,10 +1837,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
                                         trigger = "high";
                                         break;
                                 case IRQ_TYPE_NONE:
-                                        trigger = "(unspecified)";
+                                        trigger = "(?)";
                                         break;
                                 }
-                                seq_printf(s, ", irq-%d %s%s",
+                                seq_printf(s, ", irq-%d %-8s%s",
                                                 irq, trigger,
                                                 (bank->suspend_wakeup & mask)
                                                         ? " wakeup" : "");
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 75211f20ccb3..6f3f459731c8 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -3,9 +3,9 @@
  *
  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
  *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -32,21 +32,17 @@
 
 #ifdef CONFIG_OMAP_MUX
 
-#define OMAP24XX_L4_BASE        0x48000000
-#define OMAP24XX_PULL_ENA       (1 << 3)
-#define OMAP24XX_PULL_UP        (1 << 4)
+static struct omap_mux_cfg *mux_cfg;
 
-static struct pin_config * pin_table;
-static unsigned long pin_table_sz;
-
-extern struct pin_config * omap730_pins;
-extern struct pin_config * omap1xxx_pins;
-extern struct pin_config * omap24xx_pins;
-
-int __init omap_mux_register(struct pin_config * pins, unsigned long size)
+int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
 {
-        pin_table = pins;
-        pin_table_sz = size;
+        if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
+                        || !arch_mux_cfg->cfg_reg) {
+                printk(KERN_ERR "Invalid pin table\n");
+                return -EINVAL;
+        }
+
+        mux_cfg = arch_mux_cfg;
 
         return 0;
 }
@@ -56,152 +52,26 @@ int __init omap_mux_register(struct pin_config * pins, unsigned long size)
  */
 int __init_or_module omap_cfg_reg(const unsigned long index)
 {
-        static DEFINE_SPINLOCK(mux_spin_lock);
-
-        unsigned long flags;
-        struct pin_config *cfg;
-        unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
-                pull_orig = 0, pull = 0;
-        unsigned int mask, warn = 0;
+        struct pin_config *reg;
 
-        if (!pin_table)
-                BUG();
+        if (mux_cfg == NULL) {
+                printk(KERN_ERR "Pin mux table not initialized\n");
+                return -ENODEV;
+        }
 
-        if (index >= pin_table_sz) {
+        if (index >= mux_cfg->size) {
                 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
-                       index, pin_table_sz);
+                       index, mux_cfg->size);
                 dump_stack();
                 return -ENODEV;
         }
 
-        cfg = (struct pin_config *)&pin_table[index];
-        if (cpu_is_omap24xx()) {
-                u8 reg = 0;
-
-                reg |= cfg->mask & 0x7;
-                if (cfg->pull_val)
-                        reg |= OMAP24XX_PULL_ENA;
-                if(cfg->pu_pd_val)
-                        reg |= OMAP24XX_PULL_UP;
-#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
-                {
-                        u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
-                        u8 debug = 0;
-
-#ifdef  CONFIG_OMAP_MUX_DEBUG
-                        debug = cfg->debug;
-#endif
-                        warn = (orig != reg);
-                        if (debug || warn)
-                                printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
-                                                cfg->name,
-                                                OMAP24XX_L4_BASE + cfg->mux_reg,
-                                                orig, reg);
-                }
-#endif
-                omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
+        reg = (struct pin_config *)&mux_cfg->pins[index];
 
-                return 0;
-        }
-
-        /* Check the mux register in question */
-        if (cfg->mux_reg) {
-                unsigned        tmp1, tmp2;
-
-                spin_lock_irqsave(&mux_spin_lock, flags);
-                reg_orig = omap_readl(cfg->mux_reg);
-
-                /* The mux registers always seem to be 3 bits long */
-                mask = (0x7 << cfg->mask_offset);
-                tmp1 = reg_orig & mask;
-                reg = reg_orig & ~mask;
-
-                tmp2 = (cfg->mask << cfg->mask_offset);
-                reg |= tmp2;
-
-                if (tmp1 != tmp2)
-                        warn = 1;
-
-                omap_writel(reg, cfg->mux_reg);
-                spin_unlock_irqrestore(&mux_spin_lock, flags);
-        }
-
-        /* Check for pull up or pull down selection on 1610 */
-        if (!cpu_is_omap15xx()) {
-                if (cfg->pu_pd_reg && cfg->pull_val) {
-                        spin_lock_irqsave(&mux_spin_lock, flags);
-                        pu_pd_orig = omap_readl(cfg->pu_pd_reg);
-                        mask = 1 << cfg->pull_bit;
-
-                        if (cfg->pu_pd_val) {
-                                if (!(pu_pd_orig & mask))
-                                        warn = 1;
-                                /* Use pull up */
-                                pu_pd = pu_pd_orig | mask;
-                        } else {
-                                if (pu_pd_orig & mask)
-                                        warn = 1;
-                                /* Use pull down */
-                                pu_pd = pu_pd_orig & ~mask;
-                        }
-                        omap_writel(pu_pd, cfg->pu_pd_reg);
-                        spin_unlock_irqrestore(&mux_spin_lock, flags);
-                }
-        }
-
-        /* Check for an associated pull down register */
-        if (cfg->pull_reg) {
-                spin_lock_irqsave(&mux_spin_lock, flags);
-                pull_orig = omap_readl(cfg->pull_reg);
-                mask = 1 << cfg->pull_bit;
-
-                if (cfg->pull_val) {
-                        if (pull_orig & mask)
-                                warn = 1;
-                        /* Low bit = pull enabled */
-                        pull = pull_orig & ~mask;
-                } else {
-                        if (!(pull_orig & mask))
-                                warn = 1;
-                        /* High bit = pull disabled */
-                        pull = pull_orig | mask;
-                }
-
-                omap_writel(pull, cfg->pull_reg);
-                spin_unlock_irqrestore(&mux_spin_lock, flags);
-        }
-
-        if (warn) {
-#ifdef CONFIG_OMAP_MUX_WARNINGS
-                printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
-#endif
-        }
-
-#ifdef CONFIG_OMAP_MUX_DEBUG
-        if (cfg->debug || warn) {
-                printk("MUX: Setting register %s\n", cfg->name);
-                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
-
-                if (!cpu_is_omap15xx()) {
-                        if (cfg->pu_pd_reg && cfg->pull_val) {
-                                printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                                       cfg->pu_pd_name, cfg->pu_pd_reg,
-                                       pu_pd_orig, pu_pd);
-                        }
-                }
-
-                if (cfg->pull_reg)
-                        printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                               cfg->pull_name, cfg->pull_reg, pull_orig, pull);
-        }
-#endif
+        if (!mux_cfg->cfg_reg)
+                return -ENODEV;
 
-#ifdef CONFIG_OMAP_MUX_ERRORS
-        return warn ? -ETXTBSY : 0;
-#else
-        return 0;
-#endif
+        return mux_cfg->cfg_reg(reg);
 }
 EXPORT_SYMBOL(omap_cfg_reg);
 #else
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index a5aedf964b88..a619475c4b76 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -33,6 +33,7 @@
 #include <asm/system.h>
 #include <asm/hardware.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/usb.h>
 #include <asm/arch/board.h>
@@ -76,7 +77,7 @@
 
 /*-------------------------------------------------------------------------*/
 
-#ifdef  CONFIG_ARCH_OMAP_OTG
+#if     defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG)
 
 static struct otg_transceiver *xceiv;
 
@@ -110,12 +111,48 @@ EXPORT_SYMBOL(otg_set_transceiver);
 
 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
 
+static void omap2_usb_devconf_clear(u8 port, u32 mask)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r &= ~USBTXWRMODEI(port, mask);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb_devconf_set(u8 port, u32 mask)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r |= USBTXWRMODEI(port, mask);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_disable_5pinbitll(void)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_enable_5pinunitll(void)
+{
+        u32 r;
+
+        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
+        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
 static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 {
         u32     syscon1 = 0;
 
         if (cpu_is_omap24xx())
-                CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
 
         if (nwires == 0) {
                 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
@@ -187,19 +224,19 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
         case 3:
                 syscon1 = 2;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(0, USB_BIDIR);
                 break;
         case 4:
                 syscon1 = 1;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(0, USB_BIDIR);
                 break;
         case 6:
                 syscon1 = 3;
                 if (cpu_is_omap24xx()) {
                         omap_cfg_reg(J19_24XX_USB0_VP);
                         omap_cfg_reg(K20_24XX_USB0_VM);
-                        CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR);
+                        omap2_usb_devconf_set(0, USB_UNIDIR);
                 } else {
                         omap_cfg_reg(AA9_USB0_VP);
                         omap_cfg_reg(R9_USB0_VM);
@@ -220,7 +257,7 @@ static u32 __init omap_usb1_init(unsigned nwires)
         if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
                 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
         if (cpu_is_omap24xx())
-                CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
 
         if (nwires == 0)
                 return 0;
@@ -261,17 +298,17 @@ static u32 __init omap_usb1_init(unsigned nwires)
                  * this TLL link is not using DP/DM
                  */
                 syscon1 = 1;
-                CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_set(1, USB_BIDIR_TLL);
                 break;
         case 3:
                 syscon1 = 2;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(1, USB_BIDIR);
                 break;
         case 4:
                 syscon1 = 1;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(1, USB_BIDIR);
                 break;
         case 6:
                 if (cpu_is_omap24xx())
@@ -295,8 +332,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
         u32     syscon1 = 0;
 
         if (cpu_is_omap24xx()) {
-                CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL)
-                                        | USBT2TLL5PI);
+                omap2_usb2_disable_5pinbitll();
                 alt_pingroup = 0;
         }
 
@@ -343,17 +379,17 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                  * this TLL link is not using DP/DM
                  */
                 syscon1 = 1;
-                CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL);
+                omap2_usb_devconf_set(2, USB_BIDIR_TLL);
                 break;
         case 3:
                 syscon1 = 2;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(2, USB_BIDIR);
                 break;
         case 4:
                 syscon1 = 1;
                 if (cpu_is_omap24xx())
-                        CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
+                        omap2_usb_devconf_set(2, USB_BIDIR);
                 break;
         case 5:
                 if (!cpu_is_omap24xx())
@@ -364,8 +400,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
                  * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
                  */
                 syscon1 = 3;
-                CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL)
-                                        | USBT2TLL5PI;
+                omap2_usb2_enable_5pinunitll();
                 break;
         case 6:
                 if (cpu_is_omap24xx())
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
new file mode 100644
index 000000000000..198f3dde2be3
--- /dev/null
+++ b/arch/arm/plat-orion/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y   := irq.o pcie.o time.o
+obj-m   :=
+obj-n   :=
+obj-    :=
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
new file mode 100644
index 000000000000..c5b669d234bc
--- /dev/null
+++ b/arch/arm/plat-orion/irq.c
@@ -0,0 +1,64 @@
+/*
+ * arch/arm/plat-orion/irq.c
+ *
+ * Marvell Orion SoC IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/plat-orion/irq.h>
+
+static void orion_irq_mask(u32 irq)
+{
+        void __iomem *maskaddr = get_irq_chip_data(irq);
+        u32 mask;
+
+        mask = readl(maskaddr);
+        mask &= ~(1 << (irq & 31));
+        writel(mask, maskaddr);
+}
+
+static void orion_irq_unmask(u32 irq)
+{
+        void __iomem *maskaddr = get_irq_chip_data(irq);
+        u32 mask;
+
+        mask = readl(maskaddr);
+        mask |= 1 << (irq & 31);
+        writel(mask, maskaddr);
+}
+
+static struct irq_chip orion_irq_chip = {
+        .name           = "orion_irq",
+        .ack            = orion_irq_mask,
+        .mask           = orion_irq_mask,
+        .unmask         = orion_irq_unmask,
+};
+
+void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
+{
+        unsigned int i;
+
+        /*
+         * Mask all interrupts initially.
+         */
+        writel(0, maskaddr);
+
+        /*
+         * Register IRQ sources.
+         */
+        for (i = 0; i < 32; i++) {
+                unsigned int irq = irq_start + i;
+
+                set_irq_chip(irq, &orion_irq_chip);
+                set_irq_chip_data(irq, maskaddr);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
new file mode 100644
index 000000000000..abfda53f1800
--- /dev/null
+++ b/arch/arm/plat-orion/pcie.c
@@ -0,0 +1,245 @@
+/*
+ * arch/arm/plat-orion/pcie.c
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF         0x0000
+#define PCIE_CMD_OFF            0x0004
+#define PCIE_DEV_REV_OFF        0x0008
+#define PCIE_BAR_LO_OFF(n)      (0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n)      (0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF   0x0128
+#define PCIE_BAR_CTRL_OFF(n)    (0x1804 + ((n - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n)  (0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n)  (0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF      0x1880
+#define PCIE_WIN5_BASE_OFF      0x1884
+#define PCIE_WIN5_REMAP_OFF     0x188c
+#define PCIE_CONF_ADDR_OFF      0x18f8
+#define  PCIE_CONF_ADDR_EN              0x80000000
+#define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
+#define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
+#define  PCIE_CONF_FUNC(f)              (((f) & 0x3) << 8)
+#define PCIE_CONF_DATA_OFF      0x18fc
+#define PCIE_MASK_OFF           0x1910
+#define PCIE_CTRL_OFF           0x1a00
+#define PCIE_STAT_OFF           0x1a04
+#define  PCIE_STAT_DEV_OFFS             20
+#define  PCIE_STAT_DEV_MASK             0x1f
+#define  PCIE_STAT_BUS_OFFS             8
+#define  PCIE_STAT_BUS_MASK             0xff
+#define  PCIE_STAT_LINK_DOWN            1
+
+
+u32 __init orion_pcie_dev_id(void __iomem *base)
+{
+        return readl(base + PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 __init orion_pcie_rev(void __iomem *base)
+{
+        return readl(base + PCIE_DEV_REV_OFF) & 0xff;
+}
+
+int orion_pcie_link_up(void __iomem *base)
+{
+        return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+int orion_pcie_get_local_bus_nr(void __iomem *base)
+{
+        u32 stat = readl(base + PCIE_STAT_OFF);
+
+        return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
+}
+
+void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
+{
+        u32 stat;
+
+        stat = readl(base + PCIE_STAT_OFF);
+        stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
+        stat |= nr << PCIE_STAT_BUS_OFFS;
+        writel(stat, base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init orion_pcie_setup_wins(void __iomem *base,
+                                         struct mbus_dram_target_info *dram)
+{
+        u32 size;
+        int i;
+
+        /*
+         * First, disable and clear BARs and windows.
+         */
+        for (i = 1; i <= 2; i++) {
+                writel(0, base + PCIE_BAR_CTRL_OFF(i));
+                writel(0, base + PCIE_BAR_LO_OFF(i));
+                writel(0, base + PCIE_BAR_HI_OFF(i));
+        }
+
+        for (i = 0; i < 5; i++) {
+                writel(0, base + PCIE_WIN04_CTRL_OFF(i));
+                writel(0, base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+        }
+
+        writel(0, base + PCIE_WIN5_CTRL_OFF);
+        writel(0, base + PCIE_WIN5_BASE_OFF);
+        writel(0, base + PCIE_WIN5_REMAP_OFF);
+
+        /*
+         * Setup windows for DDR banks.  Count total DDR size on the fly.
+         */
+        size = 0;
+        for (i = 0; i < dram->num_cs; i++) {
+                struct mbus_dram_window *cs = dram->cs + i;
+
+                writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+                writel(((cs->size - 1) & 0xffff0000) |
+                        (cs->mbus_attr << 8) |
+                        (dram->mbus_dram_target_id << 4) | 1,
+                                base + PCIE_WIN04_CTRL_OFF(i));
+
+                size += cs->size;
+        }
+
+        /*
+         * Setup BAR[1] to all DRAM banks.
+         */
+        writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
+        writel(0, base + PCIE_BAR_HI_OFF(1));
+        writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
+}
+
+void __init orion_pcie_setup(void __iomem *base,
+                             struct mbus_dram_target_info *dram)
+{
+        u16 cmd;
+        u32 mask;
+
+        /*
+         * Point PCIe unit MBUS decode windows to DRAM space.
+         */
+        orion_pcie_setup_wins(base, dram);
+
+        /*
+         * Master + slave enable.
+         */
+        cmd = readw(base + PCIE_CMD_OFF);
+        cmd |= PCI_COMMAND_IO;
+        cmd |= PCI_COMMAND_MEMORY;
+        cmd |= PCI_COMMAND_MASTER;
+        writew(cmd, base + PCIE_CMD_OFF);
+
+        /*
+         * Enable interrupt lines A-D.
+         */
+        mask = readl(base + PCIE_MASK_OFF);
+        mask |= 0x0f000000;
+        writel(mask, base + PCIE_MASK_OFF);
+}
+
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(base + PCIE_CONF_DATA_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+                           u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(base + PCIE_CONF_DATA_OFF);
+
+        if (bus->number != orion_pcie_get_local_bus_nr(base) ||
+            PCI_FUNC(devfn) != 0)
+                *val = readl(base + PCIE_HEADER_LOG_4_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+                          u32 devfn, int where, int size, u32 *val)
+{
+        *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
+                                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                                PCIE_CONF_REG(where)));
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 val)
+{
+        int ret = PCIBIOS_SUCCESSFUL;
+
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        if (size == 4) {
+                writel(val, base + PCIE_CONF_DATA_OFF);
+        } else if (size == 2) {
+                writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+        } else if (size == 1) {
+                writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+        } else {
+                ret = PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        return ret;
+}
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
new file mode 100644
index 000000000000..28b5285446e8
--- /dev/null
+++ b/arch/arm/plat-orion/time.c
@@ -0,0 +1,203 @@
+/*
+ * arch/arm/plat-orion/time.c
+ *
+ * Marvell Orion SoC timer handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/mach/time.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL              (TIMER_VIRT_BASE + 0x0000)
+#define  TIMER0_EN              0x0001
+#define  TIMER0_RELOAD_EN       0x0002
+#define  TIMER1_EN              0x0004
+#define  TIMER1_RELOAD_EN       0x0008
+#define TIMER0_RELOAD           (TIMER_VIRT_BASE + 0x0010)
+#define TIMER0_VAL              (TIMER_VIRT_BASE + 0x0014)
+#define TIMER1_RELOAD           (TIMER_VIRT_BASE + 0x0018)
+#define TIMER1_VAL              (TIMER_VIRT_BASE + 0x001c)
+
+
+/*
+ * Clocksource handling.
+ */
+static cycle_t orion_clksrc_read(void)
+{
+        return 0xffffffff - readl(TIMER0_VAL);
+}
+
+static struct clocksource orion_clksrc = {
+        .name           = "orion_clocksource",
+        .shift          = 20,
+        .rating         = 300,
+        .read           = orion_clksrc_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+
+/*
+ * Clockevent handling.
+ */
+static int
+orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
+{
+        unsigned long flags;
+        u32 u;
+
+        if (delta == 0)
+                return -ETIME;
+
+        local_irq_save(flags);
+
+        /*
+         * Clear and enable clockevent timer interrupt.
+         */
+        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+        u = readl(BRIDGE_MASK);
+        u |= BRIDGE_INT_TIMER1;
+        writel(u, BRIDGE_MASK);
+
+        /*
+         * Setup new clockevent timer value.
+         */
+        writel(delta, TIMER1_VAL);
+
+        /*
+         * Enable the timer.
+         */
+        u = readl(TIMER_CTRL);
+        u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
+        writel(u, TIMER_CTRL);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void
+orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+        unsigned long flags;
+        u32 u;
+
+        local_irq_save(flags);
+        if (mode == CLOCK_EVT_MODE_PERIODIC) {
+                /*
+                 * Setup timer to fire at 1/HZ intervals.
+                 */
+                writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
+                writel(ticks_per_jiffy - 1, TIMER1_VAL);
+
+                /*
+                 * Enable timer interrupt.
+                 */
+                u = readl(BRIDGE_MASK);
+                writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+                /*
+                 * Enable timer.
+                 */
+                u = readl(TIMER_CTRL);
+                writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+        } else {
+                /*
+                 * Disable timer.
+                 */
+                u = readl(TIMER_CTRL);
+                writel(u & ~TIMER1_EN, TIMER_CTRL);
+
+                /*
+                 * Disable timer interrupt.
+                 */
+                u = readl(BRIDGE_MASK);
+                writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+                /*
+                 * ACK pending timer interrupt.
+                 */
+                writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+        }
+        local_irq_restore(flags);
+}
+
+static struct clock_event_device orion_clkevt = {
+        .name           = "orion_tick",
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 300,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_next_event = orion_clkevt_next_event,
+        .set_mode       = orion_clkevt_mode,
+};
+
+static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
+{
+        /*
+         * ACK timer interrupt and call event handler.
+         */
+        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+        orion_clkevt.event_handler(&orion_clkevt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction orion_timer_irq = {
+        .name           = "orion_tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = orion_timer_interrupt
+};
+
+void __init orion_time_init(unsigned int irq, unsigned int tclk)
+{
+        u32 u;
+
+        ticks_per_jiffy = (tclk + HZ/2) / HZ;
+
+
+        /*
+         * Setup free-running clocksource timer (interrupts
+         * disabled.)
+         */
+        writel(0xffffffff, TIMER0_VAL);
+        writel(0xffffffff, TIMER0_RELOAD);
+        u = readl(BRIDGE_MASK);
+        writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
+        u = readl(TIMER_CTRL);
+        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+        orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
+        clocksource_register(&orion_clksrc);
+
+
+        /*
+         * Setup clockevent timer (interrupt-driven.)
+         */
+        setup_irq(irq, &orion_timer_irq);
+        orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
+        orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
+        orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
+        clockevents_register_device(&orion_clkevt);
+}
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index 99a44746f8f2..d84167fb33b1 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -332,6 +332,58 @@ static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
+static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
+{
+        unsigned long div;
+
+        if ((rate == 0) || !clk->parent)
+                return 0;
+
+        div = clk_get_rate(clk->parent) / rate;
+        if (div < 2)
+                div = 2;
+        else if (div > 16)
+                div = 16;
+
+        return div;
+}
+
+static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
+        unsigned long rate)
+{
+        unsigned long div = s3c24xx_calc_div(clk, rate);
+
+        if (div == 0)
+                return 0;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
+
+        if (div == 0)
+                return -EINVAL;
+
+        if (clk == &s3c24xx_dclk0) {
+                mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
+                        S3C2410_DCLKCON_DCLK0_CMP_MASK;
+                data = S3C2410_DCLKCON_DCLK0_DIV(div) |
+                        S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
+        } else if (clk == &s3c24xx_dclk1) {
+                mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
+                        S3C2410_DCLKCON_DCLK1_CMP_MASK;
+                data = S3C2410_DCLKCON_DCLK1_DIV(div) |
+                        S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
+        } else
+                return -EINVAL;
+
+        clk->rate = clk_get_rate(clk->parent) / div;
+        __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
+                S3C24XX_DCLKCON);
+        return clk->rate;
+}
 
 static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
 {
@@ -378,6 +430,8 @@ struct clk s3c24xx_dclk0 = {
         .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
         .enable         = s3c24xx_dclk_enable,
         .set_parent     = s3c24xx_dclk_setparent,
+        .set_rate       = s3c24xx_set_dclk_rate,
+        .round_rate     = s3c24xx_round_dclk_rate,
 };
 
 struct clk s3c24xx_dclk1 = {
@@ -386,6 +440,8 @@ struct clk s3c24xx_dclk1 = {
         .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
         .enable         = s3c24xx_dclk_enable,
         .set_parent     = s3c24xx_dclk_setparent,
+        .set_rate       = s3c24xx_set_dclk_rate,
+        .round_rate     = s3c24xx_round_dclk_rate,
 };
 
 struct clk s3c24xx_clkout0 = {
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index f513ab083b8f..f5699cadb0c3 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -28,15 +28,19 @@
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 
 #include <asm/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/delay.h>
+#include <asm/cacheflush.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <asm/arch/system-reset.h>
+
 #include <asm/arch/regs-gpio.h>
 #include <asm/plat-s3c/regs-serial.h>
 
@@ -203,6 +207,27 @@ static unsigned long s3c24xx_read_idcode_v4(void)
 #endif
 }
 
+/* Hook for arm_pm_restart to ensure we execute the reset code
+ * with the caches enabled. It seems at least the S3C2440 has a problem
+ * resetting if there is bus activity interrupted by the reset.
+ */
+static void s3c24xx_pm_restart(char mode)
+{
+        if (mode != 's') {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                __cpuc_flush_kern_all();
+                __cpuc_flush_user_all();
+
+                arch_reset(mode);
+                local_irq_restore(flags);
+        }
+
+        /* fallback, or unhandled */
+        arm_machine_restart(mode);
+}
+
 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 {
         unsigned long idcode = 0x0;
@@ -230,6 +255,8 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
                 panic("Unsupported S3C24XX CPU");
         }
 
+        arm_pm_restart = s3c24xx_pm_restart;
+
         (cpu->map_io)(mach_desc, size);
 }
 
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 7ed58c0c24c2..207a8b5a0c4a 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat Jan 26 14:45:34 2008
+# Last update: Sat Apr 19 11:23:38 2008
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -381,13 +381,13 @@ ks8695p			ARCH_KS8695P		KS8695P			363
 se4000                  ARCH_SE4000             SE4000                  364
 quadriceps              ARCH_QUADRICEPS         QUADRICEPS              365
 bronco                  ARCH_BRONCO             BRONCO                  366
-esl_wireless_tab        ARCH_ESL_WIRELESS_TABLETESL_WIRELESS_TABLET     367
+esl_wireless_tab        ARCH_ESL_WIRELESS_TAB   ESL_WIRELESS_TAB        367
 esl_sofcomp             ARCH_ESL_SOFCOMP        ESL_SOFCOMP             368
 s5c7375                 ARCH_S5C7375            S5C7375                 369
 spearhead               ARCH_SPEARHEAD          SPEARHEAD               370
 pantera                 ARCH_PANTERA            PANTERA                 371
 prayoglite              ARCH_PRAYOGLITE         PRAYOGLITE              372
-gumstix                 ARCH_GUMSTIK            GUMSTIK                 373
+gumstix                 ARCH_GUMSTIX            GUMSTIX                 373
 rcube                   ARCH_RCUBE              RCUBE                   374
 rea_olv                 ARCH_REA_OLV            REA_OLV                 375
 pxa_iphone              ARCH_PXA_IPHONE         PXA_IPHONE              376
@@ -1463,7 +1463,7 @@ artemis			MACH_ARTEMIS		ARTEMIS			1462
 htctitan                MACH_HTCTITAN           HTCTITAN                1463
 qranium                 MACH_QRANIUM            QRANIUM                 1464
 adx_wsc2                MACH_ADX_WSC2           ADX_WSC2                1465
-adx_medinet             MACH_ADX_MEDINET        ADX_MEDINET             1466
+adx_medcom              MACH_ADX_MEDINET        ADX_MEDINET             1466
 bboard                  MACH_BBOARD             BBOARD                  1467
 cambria                 MACH_CAMBRIA            CAMBRIA                 1468
 mt7xxx                  MACH_MT7XXX             MT7XXX                  1469
@@ -1611,3 +1611,112 @@ kb9263			MACH_KB9263		KB9263			1612
 mt7108                  MACH_MT7108             MT7108                  1613
 smtr2440                MACH_SMTR2440           SMTR2440                1614
 manao                   MACH_MANAO              MANAO                   1615
+cm_x300                 MACH_CM_X300            CM_X300                 1616
+gulfstream_kp           MACH_GULFSTREAM_KP      GULFSTREAM_KP           1617
+lanreadyfn522           MACH_LANREADYFN522      LANREADYFN522           1618
+arma37                  MACH_ARMA37             ARMA37                  1619
+mendel                  MACH_MENDEL             MENDEL                  1620
+pelco_iliad             MACH_PELCO_ILIAD        PELCO_ILIAD             1621
+unit2p                  MACH_UNIT2P             UNIT2P                  1622
+inc20otter              MACH_INC20OTTER         INC20OTTER              1623
+at91sam9g20ek           MACH_AT91SAM9G20EK      AT91SAM9G20EK           1624
+sc_ge2                  MACH_STORCENTER         STORCENTER              1625
+smdk6410                MACH_SMDK6410           SMDK6410                1626
+u300                    MACH_U300               U300                    1627
+u500                    MACH_U500               U500                    1628
+ds9260                  MACH_DS9260             DS9260                  1629
+riverrock               MACH_RIVERROCK          RIVERROCK               1630
+scibath                 MACH_SCIBATH            SCIBATH                 1631
+at91sam7se              MACH_AT91SAM7SE512EK    AT91SAM7SE512EK         1632
+wrt350n_v2              MACH_WRT350N_V2         WRT350N_V2              1633
+multimedia              MACH_MULTIMEDIA         MULTIMEDIA              1634
+marvin                  MACH_MARVIN             MARVIN                  1635
+x500                    MACH_X500               X500                    1636
+awlug4lcu               MACH_AWLUG4LCU          AWLUG4LCU               1637
+palermoc                MACH_PALERMOC           PALERMOC                1638
+omap_ldp                MACH_OMAP_LDP           OMAP_LDP                1639
+ip500                   MACH_IP500              IP500                   1640
+mx35ads                 MACH_MACH_MX35ADS       MACH_MX35ADS            1641
+ase2                    MACH_ASE2               ASE2                    1642
+mx35evb                 MACH_MX35EVB            MX35EVB                 1643
+aml_m8050               MACH_AML_M8050          AML_M8050               1644
+mx35_3ds                MACH_MX35_3DS           MX35_3DS                1645
+mars                    MACH_MARS               MARS                    1646
+ntosd_644xa             MACH_NTOSD_644XA        NTOSD_644XA             1647
+badger                  MACH_BADGER             BADGER                  1648
+trizeps4wl              MACH_TRIZEPS4WL         TRIZEPS4WL              1649
+trizeps5                MACH_TRIZEPS5           TRIZEPS5                1650
+marlin                  MACH_MARLIN             MARLIN                  1651
+ts7800                  MACH_TS7800             TS7800                  1652
+hpipaq214               MACH_HPIPAQ214          HPIPAQ214               1653
+at572d940dcm            MACH_AT572D940DCM       AT572D940DCM            1654
+ne1board                MACH_NE1BOARD           NE1BOARD                1655
+zante                   MACH_ZANTE              ZANTE                   1656
+sffsdr                  MACH_SFFSDR             SFFSDR                  1657
+tw2662                  MACH_TW2662             TW2662                  1658
+vf10xx                  MACH_VF10XX             VF10XX                  1659
+zoran43xx               MACH_ZORAN43XX          ZORAN43XX               1660
+sonix926                MACH_SONIX926           SONIX926                1661
+celestialsemi           MACH_CELESTIALSEMI      CELESTIALSEMI           1662
+cc9m2443                MACH_CC9M2443           CC9M2443                1663
+tw5334                  MACH_TW5334             TW5334                  1664
+omap_htcartemis         MACH_HTCARTEMIS         HTCARTEMIS              1665
+nal_hlite               MACH_NAL_HLITE          NAL_HLITE               1666
+htcvogue                MACH_HTCVOGUE           HTCVOGUE                1667
+smartweb                MACH_SMARTWEB           SMARTWEB                1668
+mv86xx                  MACH_MV86XX             MV86XX                  1669
+mv87xx                  MACH_MV87XX             MV87XX                  1670
+songyoungho             MACH_SONGYOUNGHO        SONGYOUNGHO             1671
+younghotema             MACH_YOUNGHOTEMA        YOUNGHOTEMA             1672
+pcm037                  MACH_PCM037             PCM037                  1673
+mmvp                    MACH_MMVP               MMVP                    1674
+mmap                    MACH_MMAP               MMAP                    1675
+ptid2410                MACH_PTID2410           PTID2410                1676
+james_926               MACH_JAMES_926          JAMES_926               1677
+fm6000                  MACH_FM6000             FM6000                  1678
+db88f6281_bp            MACH_DB88F6281_BP       DB88F6281_BP            1680
+rd88f6192_nas           MACH_RD88F6192_NAS      RD88F6192_NAS           1681
+rd88f6281               MACH_RD88F6281          RD88F6281               1682
+db78x00_bp              MACH_DB78X00_BP         DB78X00_BP              1683
+smdk2416                MACH_SMDK2416           SMDK2416                1685
+oce_spider_si           MACH_OCE_SPIDER_SI      OCE_SPIDER_SI           1686
+oce_spider_sk           MACH_OCE_SPIDER_SK      OCE_SPIDER_SK           1687
+rovern6                 MACH_ROVERN6            ROVERN6                 1688
+pelco_evolution         MACH_PELCO_EVOLUTION    PELCO_EVOLUTION         1689
+wbd111                  MACH_WBD111             WBD111                  1690
+elaracpe                MACH_ELARACPE           ELARACPE                1691
+mabv3                   MACH_MABV3              MABV3                   1692
+mv2120                  MACH_MV2120             MV2120                  1693
+csb737                  MACH_CSB737             CSB737                  1695
+mx51_3ds                MACH_MX51_3DS           MX51_3DS                1696
+g900                    MACH_G900               G900                    1697
+apf27                   MACH_APF27              APF27                   1698
+ggus2000                MACH_GGUS2000           GGUS2000                1699
+omap_2430_mimic         MACH_OMAP_2430_MIMIC    OMAP_2430_MIMIC         1700
+imx27lite               MACH_IMX27LITE          IMX27LITE               1701
+almex                   MACH_ALMEX              ALMEX                   1702
+control                 MACH_CONTROL            CONTROL                 1703
+mba2410                 MACH_MBA2410            MBA2410                 1704
+volcano                 MACH_VOLCANO            VOLCANO                 1705
+zenith                  MACH_ZENITH             ZENITH                  1706
+muchip                  MACH_MUCHIP             MUCHIP                  1707
+magellan                MACH_MAGELLAN           MAGELLAN                1708
+usb_a9260               MACH_USB_A9260          USB_A9260               1709
+usb_a9263               MACH_USB_A9263          USB_A9263               1710
+qil_a9260               MACH_QIL_A9260          QIL_A9260               1711
+cme9210                 MACH_CME9210            CME9210                 1712
+hczh4                   MACH_HCZH4              HCZH4                   1713
+spearbasic              MACH_SPEARBASIC         SPEARBASIC              1714
+dep2440                 MACH_DEP2440            DEP2440                 1715
+hdl_gxr                 MACH_HDL_GXR            HDL_GXR                 1716
+hdl_gt                  MACH_HDL_GT             HDL_GT                  1717
+hdl_4g                  MACH_HDL_4G             HDL_4G                  1718
+s3c6000                 MACH_S3C6000            S3C6000                 1719
+mmsp2_mdk               MACH_MMSP2_MDK          MMSP2_MDK               1720
+mpx220                  MACH_MPX220             MPX220                  1721
+kzm_arm11_01            MACH_KZM_ARM11_01       KZM_ARM11_01            1722
+htc_polaris             MACH_HTC_POLARIS        HTC_POLARIS             1723
+htc_kaiser              MACH_HTC_KAISER         HTC_KAISER              1724
+lg_ks20                 MACH_LG_KS20            LG_KS20                 1725
+hhgps                   MACH_HHGPS              HHGPS                   1726
+nokia_n810_wimax        MACH_NOKIA_N810_WIMAX   NOKIA_N810_WIMAX        1727
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 28e0caf4156c..09ad7995080c 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -47,6 +47,9 @@ config RWSEM_GENERIC_SPINLOCK
 config GENERIC_TIME
         def_bool y
 
+config GENERIC_CLOCKEVENTS
+        def_bool y
+
 config RWSEM_XCHGADD_ALGORITHM
         def_bool n
 
@@ -70,6 +73,8 @@ source "init/Kconfig"
 
 menu "System Type and features"
 
+source "kernel/time/Kconfig"
+
 config SUBARCH_AVR32B
         bool
 config MMU
diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
index 8cf16d7a7040..5f31702d6b1c 100644
--- a/arch/avr32/kernel/entry-avr32b.S
+++ b/arch/avr32/kernel/entry-avr32b.S
@@ -741,26 +741,6 @@ irq_level\level:
 
         .section .irq.text,"ax",@progbits
 
-.global cpu_idle_sleep
-cpu_idle_sleep:
-        mask_interrupts
-        get_thread_info r8
-        ld.w    r9, r8[TI_flags]
-        bld     r9, TIF_NEED_RESCHED
-        brcs    cpu_idle_enable_int_and_exit
-        sbr     r9, TIF_CPU_GOING_TO_SLEEP
-        st.w    r8[TI_flags], r9
-        unmask_interrupts
-        sleep 0
-cpu_idle_skip_sleep:
-        mask_interrupts
-        ld.w    r9, r8[TI_flags]
-        cbr     r9, TIF_CPU_GOING_TO_SLEEP
-        st.w    r8[TI_flags], r9
-cpu_idle_enable_int_and_exit:
-        unmask_interrupts
-        retal   r12
-
         .global irq_level0
         .global irq_level1
         .global irq_level2
diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
index 7f4af0b1e111..6cf9df176274 100644
--- a/arch/avr32/kernel/process.c
+++ b/arch/avr32/kernel/process.c
@@ -18,11 +18,11 @@
 #include <asm/sysreg.h>
 #include <asm/ocd.h>
 
+#include <asm/arch/pm.h>
+
 void (*pm_power_off)(void) = NULL;
 EXPORT_SYMBOL(pm_power_off);
 
-extern void cpu_idle_sleep(void);
-
 /*
  * This file handles the architecture-dependent parts of process handling..
  */
@@ -54,6 +54,8 @@ void machine_halt(void)
 
 void machine_power_off(void)
 {
+        if (pm_power_off)
+                pm_power_off();
 }
 
 void machine_restart(char *cmd)
diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
index 36a46c3ae308..00a9862380ff 100644
--- a/arch/avr32/kernel/time.c
+++ b/arch/avr32/kernel/time.c
@@ -1,16 +1,12 @@
 /*
  * Copyright (C) 2004-2007 Atmel Corporation
  *
- * Based on MIPS implementation arch/mips/kernel/time.c
- *   Copyright 2001 MontaVista Software Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
 #include <linux/clk.h>
-#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <linux/time.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
@@ -27,207 +23,133 @@
 #include <asm/io.h>
 #include <asm/sections.h>
 
-/* how many counter cycles in a jiffy? */
-static u32 cycles_per_jiffy;
+#include <asm/arch/pm.h>
 
-/* the count value for the next timer interrupt */
-static u32 expirelo;
 
-cycle_t __weak read_cycle_count(void)
+static cycle_t read_cycle_count(void)
 {
         return (cycle_t)sysreg_read(COUNT);
 }
 
-struct clocksource __weak clocksource_avr32 = {
-        .name           = "avr32",
-        .rating         = 350,
+/*
+ * The architectural cycle count registers are a fine clocksource unless
+ * the system idle loop use sleep states like "idle":  the CPU cycles
+ * measured by COUNT (and COMPARE) don't happen during sleep states.
+ * Their duration also changes if cpufreq changes the CPU clock rate.
+ * So we rate the clocksource using COUNT as very low quality.
+ */
+static struct clocksource counter = {
+        .name           = "avr32_counter",
+        .rating         = 50,
         .read           = read_cycle_count,
         .mask           = CLOCKSOURCE_MASK(32),
         .shift          = 16,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
-
-struct irqaction timer_irqaction = {
-        .handler        = timer_interrupt,
-        .flags          = IRQF_DISABLED,
-        .name           = "timer",
-};
-
-/*
- * By default we provide the null RTC ops
- */
-static unsigned long null_rtc_get_time(void)
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
 {
-        return mktime(2007, 1, 1, 0, 0, 0);
-}
-
-static int null_rtc_set_time(unsigned long sec)
-{
-        return 0;
-}
+        struct clock_event_device *evdev = dev_id;
 
-static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
-static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
-
-static void avr32_timer_ack(void)
-{
-        u32 count;
-
-        /* Ack this timer interrupt and set the next one */
-        expirelo += cycles_per_jiffy;
-        /* setting COMPARE to 0 stops the COUNT-COMPARE */
-        if (expirelo == 0) {
-                sysreg_write(COMPARE, expirelo + 1);
-        } else {
-                sysreg_write(COMPARE, expirelo);
-        }
+        /*
+         * Disable the interrupt until the clockevent subsystem
+         * reprograms it.
+         */
+        sysreg_write(COMPARE, 0);
 
-        /* Check to see if we have missed any timer interrupts */
-        count = sysreg_read(COUNT);
-        if ((count - expirelo) < 0x7fffffff) {
-                expirelo = count + cycles_per_jiffy;
-                sysreg_write(COMPARE, expirelo);
-        }
+        evdev->event_handler(evdev);
+        return IRQ_HANDLED;
 }
 
-int __weak avr32_hpt_init(void)
-{
-        int ret;
-        unsigned long mult, shift, count_hz;
-
-        count_hz = clk_get_rate(boot_cpu_data.clk);
-        shift = clocksource_avr32.shift;
-        mult = clocksource_hz2mult(count_hz, shift);
-        clocksource_avr32.mult = mult;
-
-        {
-                u64 tmp;
-
-                tmp = TICK_NSEC;
-                tmp <<= shift;
-                tmp += mult / 2;
-                do_div(tmp, mult);
-
-                cycles_per_jiffy = tmp;
-        }
+static struct irqaction timer_irqaction = {
+        .handler        = timer_interrupt,
+        .flags          = IRQF_TIMER | IRQF_DISABLED,
+        .name           = "avr32_comparator",
+};
 
-        ret = setup_irq(0, &timer_irqaction);
-        if (ret) {
-                pr_debug("timer: could not request IRQ 0: %d\n", ret);
-                return -ENODEV;
-        }
+static int comparator_next_event(unsigned long delta,
+                struct clock_event_device *evdev)
+{
+        unsigned long   flags;
 
-        printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
-                        "%lu.%03lu MHz\n",
-                        ((count_hz + 500) / 1000) / 1000,
-                        ((count_hz + 500) / 1000) % 1000);
+        raw_local_irq_save(flags);
 
-        return 0;
-}
+        /* The time to read COUNT then update COMPARE must be less
+         * than the min_delta_ns value for this clockevent source.
+         */
+        sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
 
-/*
- * Taken from MIPS c0_hpt_timer_init().
- *
- * The reason COUNT is written twice is probably to make sure we don't get any
- * timer interrupts while we are messing with the counter.
- */
-int __weak avr32_hpt_start(void)
-{
-        u32 count = sysreg_read(COUNT);
-        expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
-        sysreg_write(COUNT, expirelo - cycles_per_jiffy);
-        sysreg_write(COMPARE, expirelo);
-        sysreg_write(COUNT, count);
+        raw_local_irq_restore(flags);
 
         return 0;
 }
 
-/*
- * local_timer_interrupt() does profiling and process accounting on a
- * per-CPU basis.
- *
- * In UP mode, it is invoked from the (global) timer_interrupt.
- */
-void local_timer_interrupt(int irq, void *dev_id)
+static void comparator_mode(enum clock_event_mode mode,
+                struct clock_event_device *evdev)
 {
-        if (current->pid)
-                profile_tick(CPU_PROFILING);
-        update_process_times(user_mode(get_irq_regs()));
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+                pr_debug("%s: start\n", evdev->name);
+                /* FALLTHROUGH */
+        case CLOCK_EVT_MODE_RESUME:
+                cpu_disable_idle_sleep();
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                sysreg_write(COMPARE, 0);
+                pr_debug("%s: stop\n", evdev->name);
+                cpu_enable_idle_sleep();
+                break;
+        default:
+                BUG();
+        }
 }
 
-irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
-{
-        /* ack timer interrupt and try to set next interrupt */
-        avr32_timer_ack();
-
-        /*
-         * Call the generic timer interrupt handler
-         */
-        write_seqlock(&xtime_lock);
-        do_timer(1);
-        write_sequnlock(&xtime_lock);
-
-        /*
-         * In UP mode, we call local_timer_interrupt() to do profiling
-         * and process accounting.
-         *
-         * SMP is not supported yet.
-         */
-        local_timer_interrupt(irq, dev_id);
-
-        return IRQ_HANDLED;
-}
+static struct clock_event_device comparator = {
+        .name           = "avr32_comparator",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 16,
+        .rating         = 50,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_next_event = comparator_next_event,
+        .set_mode       = comparator_mode,
+};
 
 void __init time_init(void)
 {
+        unsigned long counter_hz;
         int ret;
 
-        /*
-         * Make sure we don't get any COMPARE interrupts before we can
-         * handle them.
-         */
-        sysreg_write(COMPARE, 0);
-
-        xtime.tv_sec = rtc_get_time();
+        xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
         xtime.tv_nsec = 0;
 
         set_normalized_timespec(&wall_to_monotonic,
                                 -xtime.tv_sec, -xtime.tv_nsec);
 
-        ret = avr32_hpt_init();
-        if (ret) {
-                pr_debug("timer: failed setup: %d\n", ret);
-                return;
-        }
+        /* figure rate for counter */
+        counter_hz = clk_get_rate(boot_cpu_data.clk);
+        counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
 
-        ret = clocksource_register(&clocksource_avr32);
+        ret = clocksource_register(&counter);
         if (ret)
                 pr_debug("timer: could not register clocksource: %d\n", ret);
 
-        ret = avr32_hpt_start();
-        if (ret) {
-                pr_debug("timer: failed starting: %d\n", ret);
-                return;
-        }
-}
+        /* setup COMPARE clockevent */
+        comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
+        comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
+        comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
 
-static struct sysdev_class timer_class = {
-        .name = "timer",
-};
+        sysreg_write(COMPARE, 0);
+        timer_irqaction.dev_id = &comparator;
 
-static struct sys_device timer_device = {
-        .id     = 0,
-        .cls    = &timer_class,
-};
+        ret = setup_irq(0, &timer_irqaction);
+        if (ret)
+                pr_debug("timer: could not request IRQ 0: %d\n", ret);
+        else {
+                clockevents_register_device(&comparator);
 
-static int __init init_timer_sysfs(void)
-{
-        int err = sysdev_class_register(&timer_class);
-        if (!err)
-                err = sysdev_register(&timer_device);
-        return err;
+                pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
+                                ((counter_hz + 500) / 1000) / 1000,
+                                ((counter_hz + 500) / 1000) % 1000);
+        }
 }
-
-device_initcall(init_timer_sysfs);
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
index 5e9f8217befc..e89009439e4a 100644
--- a/arch/avr32/mach-at32ap/Makefile
+++ b/arch/avr32/mach-at32ap/Makefile
@@ -1,4 +1,3 @@
 obj-y                           += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
-obj-$(CONFIG_CPU_AT32AP700X)    += at32ap700x.o
-obj-$(CONFIG_CPU_AT32AP700X)    += time-tc.o
+obj-$(CONFIG_CPU_AT32AP700X)    += at32ap700x.o pm-at32ap700x.o
 obj-$(CONFIG_CPU_FREQ_AT32AP)   += cpufreq.o
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 7678fee9a885..0f24b4f85c17 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -6,11 +6,13 @@
  * published by the Free Software Foundation.
  */
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/fb.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/spi/spi.h>
+#include <linux/usb/atmel_usba_udc.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -98,6 +100,9 @@ unsigned long at32ap7000_osc_rates[3] = {
         [2] = 12000000,
 };
 
+static struct clk osc0;
+static struct clk osc1;
+
 static unsigned long osc_get_rate(struct clk *clk)
 {
         return at32ap7000_osc_rates[clk->index];
@@ -107,9 +112,6 @@ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 {
         unsigned long div, mul, rate;
 
-        if (!(control & PM_BIT(PLLEN)))
-                return 0;
-
         div = PM_BFEXT(PLLDIV, control) + 1;
         mul = PM_BFEXT(PLLMUL, control) + 1;
 
@@ -120,6 +122,71 @@ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
         return rate;
 }
 
+static long pll_set_rate(struct clk *clk, unsigned long rate,
+                         u32 *pll_ctrl)
+{
+        unsigned long mul;
+        unsigned long mul_best_fit = 0;
+        unsigned long div;
+        unsigned long div_min;
+        unsigned long div_max;
+        unsigned long div_best_fit = 0;
+        unsigned long base;
+        unsigned long pll_in;
+        unsigned long actual = 0;
+        unsigned long rate_error;
+        unsigned long rate_error_prev = ~0UL;
+        u32 ctrl;
+
+        /* Rate must be between 80 MHz and 200 Mhz. */
+        if (rate < 80000000UL || rate > 200000000UL)
+                return -EINVAL;
+
+        ctrl = PM_BF(PLLOPT, 4);
+        base = clk->parent->get_rate(clk->parent);
+
+        /* PLL input frequency must be between 6 MHz and 32 MHz. */
+        div_min = DIV_ROUND_UP(base, 32000000UL);
+        div_max = base / 6000000UL;
+
+        if (div_max < div_min)
+                return -EINVAL;
+
+        for (div = div_min; div <= div_max; div++) {
+                pll_in = (base + div / 2) / div;
+                mul = (rate + pll_in / 2) / pll_in;
+
+                if (mul == 0)
+                        continue;
+
+                actual = pll_in * mul;
+                rate_error = abs(actual - rate);
+
+                if (rate_error < rate_error_prev) {
+                        mul_best_fit = mul;
+                        div_best_fit = div;
+                        rate_error_prev = rate_error;
+                }
+
+                if (rate_error == 0)
+                        break;
+        }
+
+        if (div_best_fit == 0)
+                return -EINVAL;
+
+        ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
+        ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
+        ctrl |= PM_BF(PLLCOUNT, 16);
+
+        if (clk->parent == &osc1)
+                ctrl |= PM_BIT(PLLOSC);
+
+        *pll_ctrl = ctrl;
+
+        return actual;
+}
+
 static unsigned long pll0_get_rate(struct clk *clk)
 {
         u32 control;
@@ -129,6 +196,41 @@ static unsigned long pll0_get_rate(struct clk *clk)
         return pll_get_rate(clk, control);
 }
 
+static void pll1_mode(struct clk *clk, int enabled)
+{
+        unsigned long timeout;
+        u32 status;
+        u32 ctrl;
+
+        ctrl = pm_readl(PLL1);
+
+        if (enabled) {
+                if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
+                        pr_debug("clk %s: failed to enable, rate not set\n",
+                                        clk->name);
+                        return;
+                }
+
+                ctrl |= PM_BIT(PLLEN);
+                pm_writel(PLL1, ctrl);
+
+                /* Wait for PLL lock. */
+                for (timeout = 10000; timeout; timeout--) {
+                        status = pm_readl(ISR);
+                        if (status & PM_BIT(LOCK1))
+                                break;
+                        udelay(10);
+                }
+
+                if (!(status & PM_BIT(LOCK1)))
+                        printk(KERN_ERR "clk %s: timeout waiting for lock\n",
+                                        clk->name);
+        } else {
+                ctrl &= ~PM_BIT(PLLEN);
+                pm_writel(PLL1, ctrl);
+        }
+}
+
 static unsigned long pll1_get_rate(struct clk *clk)
 {
         u32 control;
@@ -138,6 +240,49 @@ static unsigned long pll1_get_rate(struct clk *clk)
         return pll_get_rate(clk, control);
 }
 
+static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+        u32 ctrl = 0;
+        unsigned long actual_rate;
+
+        actual_rate = pll_set_rate(clk, rate, &ctrl);
+
+        if (apply) {
+                if (actual_rate != rate)
+                        return -EINVAL;
+                if (clk->users > 0)
+                        return -EBUSY;
+                pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
+                                clk->name, rate, actual_rate);
+                pm_writel(PLL1, ctrl);
+        }
+
+        return actual_rate;
+}
+
+static int pll1_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 ctrl;
+
+        if (clk->users > 0)
+                return -EBUSY;
+
+        ctrl = pm_readl(PLL1);
+        WARN_ON(ctrl & PM_BIT(PLLEN));
+
+        if (parent == &osc0)
+                ctrl &= ~PM_BIT(PLLOSC);
+        else if (parent == &osc1)
+                ctrl |= PM_BIT(PLLOSC);
+        else
+                return -EINVAL;
+
+        pm_writel(PLL1, ctrl);
+        clk->parent = parent;
+
+        return 0;
+}
+
 /*
  * The AT32AP7000 has five primary clock sources: One 32kHz
  * oscillator, two crystal oscillators and two PLLs.
@@ -166,7 +311,10 @@ static struct clk pll0 = {
 };
 static struct clk pll1 = {
         .name           = "pll1",
+        .mode           = pll1_mode,
         .get_rate       = pll1_get_rate,
+        .set_rate       = pll1_set_rate,
+        .set_parent     = pll1_set_parent,
         .parent         = &osc0,
 };
 
@@ -605,19 +753,32 @@ static inline void set_ebi_sfr_bits(u32 mask)
 }
 
 /* --------------------------------------------------------------------
- *  System Timer/Counter (TC)
+ *  Timer/Counter (TC)
  * -------------------------------------------------------------------- */
-static struct resource at32_systc0_resource[] = {
+
+static struct resource at32_tcb0_resource[] = {
         PBMEM(0xfff00c00),
         IRQ(22),
 };
-struct platform_device at32_systc0_device = {
-        .name           = "systc",
+static struct platform_device at32_tcb0_device = {
+        .name           = "atmel_tcb",
         .id             = 0,
-        .resource       = at32_systc0_resource,
-        .num_resources  = ARRAY_SIZE(at32_systc0_resource),
+        .resource       = at32_tcb0_resource,
+        .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 };
-DEV_CLK(pclk, at32_systc0, pbb, 3);
+DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
+
+static struct resource at32_tcb1_resource[] = {
+        PBMEM(0xfff01000),
+        IRQ(23),
+};
+static struct platform_device at32_tcb1_device = {
+        .name           = "atmel_tcb",
+        .id             = 1,
+        .resource       = at32_tcb1_resource,
+        .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
+};
+DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 
 /* --------------------------------------------------------------------
  *  PIO
@@ -669,7 +830,8 @@ void __init at32_add_system_devices(void)
         platform_device_register(&pdc_device);
         platform_device_register(&dmaca0_device);
 
-        platform_device_register(&at32_systc0_device);
+        platform_device_register(&at32_tcb0_device);
+        platform_device_register(&at32_tcb1_device);
 
         platform_device_register(&pio0_device);
         platform_device_register(&pio1_device);
@@ -989,7 +1151,9 @@ static struct clk atmel_twi0_pclk = {
         .index          = 2,
 };
 
-struct platform_device *__init at32_add_device_twi(unsigned int id)
+struct platform_device *__init at32_add_device_twi(unsigned int id,
+                                                    struct i2c_board_info *b,
+                                                    unsigned int n)
 {
         struct platform_device *pdev;
 
@@ -1009,6 +1173,9 @@ struct platform_device *__init at32_add_device_twi(unsigned int id)
 
         atmel_twi0_pclk.dev = &pdev->dev;
 
+        if (b)
+                i2c_register_board_info(id, b, n);
+
         platform_device_add(pdev);
         return pdev;
 
@@ -1351,9 +1518,39 @@ static struct clk usba0_hclk = {
         .index          = 6,
 };
 
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
+        [idx] = {                                               \
+                .name           = nam,                          \
+                .index          = idx,                          \
+                .fifo_size      = maxpkt,                       \
+                .nr_banks       = maxbk,                        \
+                .can_dma        = dma,                          \
+                .can_isoc       = isoc,                         \
+        }
+
+static struct usba_ep_data at32_usba_ep[] __initdata = {
+        EP("ep0",     0,   64, 1, 0, 0),
+        EP("ep1",     1,  512, 2, 1, 1),
+        EP("ep2",     2,  512, 2, 1, 1),
+        EP("ep3-int", 3,   64, 3, 1, 0),
+        EP("ep4-int", 4,   64, 3, 1, 0),
+        EP("ep5",     5, 1024, 3, 1, 1),
+        EP("ep6",     6, 1024, 3, 1, 1),
+};
+
+#undef EP
+
 struct platform_device *__init
 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
 {
+        /*
+         * pdata doesn't have room for any endpoints, so we need to
+         * append room for the ones we need right after it.
+         */
+        struct {
+                struct usba_platform_data pdata;
+                struct usba_ep_data ep[7];
+        } usba_data;
         struct platform_device *pdev;
 
         if (id != 0)
@@ -1367,13 +1564,20 @@ at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
                                           ARRAY_SIZE(usba0_resource)))
                 goto out_free_pdev;
 
-        if (data) {
-                if (platform_device_add_data(pdev, data, sizeof(*data)))
-                        goto out_free_pdev;
+        if (data)
+                usba_data.pdata.vbus_pin = data->vbus_pin;
+        else
+                usba_data.pdata.vbus_pin = -EINVAL;
+
+        data = &usba_data.pdata;
+        data->num_ep = ARRAY_SIZE(at32_usba_ep);
+        memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
 
-                if (data->vbus_pin != GPIO_PIN_NONE)
-                        at32_select_gpio(data->vbus_pin, 0);
-        }
+        if (platform_device_add_data(pdev, data, sizeof(usba_data)))
+                goto out_free_pdev;
+
+        if (data->vbus_pin >= 0)
+                at32_select_gpio(data->vbus_pin, 0);
 
         usba0_pclk.dev = &pdev->dev;
         usba0_hclk.dev = &pdev->dev;
@@ -1694,7 +1898,8 @@ struct clk *at32_clock_list[] = {
         &pio2_mck,
         &pio3_mck,
         &pio4_mck,
-        &at32_systc0_pclk,
+        &at32_tcb0_t0_clk,
+        &at32_tcb1_t0_clk,
         &atmel_usart0_usart,
         &atmel_usart1_usart,
         &atmel_usart2_usart,
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index 0b286cd53028..097cf4e84052 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -13,7 +13,6 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 
-#include <asm/intc.h>
 #include <asm/io.h>
 
 #include "intc.h"
diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
new file mode 100644
index 000000000000..949e2485e278
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
@@ -0,0 +1,66 @@
+/*
+ * Low-level Power Management code.
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/arch/pm.h>
+
+        .section .bss, "wa", @nobits
+        .global disable_idle_sleep
+        .type   disable_idle_sleep, @object
+disable_idle_sleep:
+        .int    4
+        .size   disable_idle_sleep, . - disable_idle_sleep
+
+        /* Keep this close to the irq handlers */
+        .section .irq.text, "ax", @progbits
+
+        /*
+         * void cpu_enter_idle(void)
+         *
+         * Put the CPU into "idle" mode, in which it will consume
+         * significantly less power.
+         *
+         * If an interrupt comes along in the window between
+         * unmask_interrupts and the sleep instruction below, the
+         * interrupt code will adjust the return address so that we
+         * never execute the sleep instruction. This is required
+         * because the AP7000 doesn't unmask interrupts when entering
+         * sleep modes; later CPUs may not need this workaround.
+         */
+        .global cpu_enter_idle
+        .type   cpu_enter_idle, @function
+cpu_enter_idle:
+        mask_interrupts
+        get_thread_info r8
+        ld.w    r9, r8[TI_flags]
+        bld     r9, TIF_NEED_RESCHED
+        brcs    .Lret_from_sleep
+        sbr     r9, TIF_CPU_GOING_TO_SLEEP
+        st.w    r8[TI_flags], r9
+        unmask_interrupts
+        sleep   CPU_SLEEP_IDLE
+        .size   cpu_idle_sleep, . - cpu_idle_sleep
+
+        /*
+         * Common return path for PM functions that don't run from
+         * SRAM.
+         */
+        .global cpu_idle_skip_sleep
+        .type   cpu_idle_skip_sleep, @function
+cpu_idle_skip_sleep:
+        mask_interrupts
+        ld.w    r9, r8[TI_flags]
+        cbr     r9, TIF_CPU_GOING_TO_SLEEP
+        st.w    r8[TI_flags], r9
+.Lret_from_sleep:
+        unmask_interrupts
+        retal   r12
+        .size   cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
diff --git a/arch/avr32/mach-at32ap/time-tc.c b/arch/avr32/mach-at32ap/time-tc.c
deleted file mode 100644
index 10265863c982..000000000000
--- a/arch/avr32/mach-at32ap/time-tc.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Atmel Corporation
- *
- * Based on MIPS implementation arch/mips/kernel/time.c
- *   Copyright 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/clocksource.h>
-#include <linux/time.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/sysdev.h>
-#include <linux/err.h>
-
-#include <asm/div64.h>
-#include <asm/sysreg.h>
-#include <asm/io.h>
-#include <asm/sections.h>
-
-#include <asm/arch/time.h>
-
-/* how many counter cycles in a jiffy? */
-static u32 cycles_per_jiffy;
-
-/* the count value for the next timer interrupt */
-static u32 expirelo;
-
-/* the I/O registers of the TC module */
-static void __iomem *ioregs;
-
-cycle_t read_cycle_count(void)
-{
-        return (cycle_t)timer_read(ioregs, 0, CV);
-}
-
-struct clocksource clocksource_avr32 = {
-        .name           = "avr32",
-        .rating         = 342,
-        .read           = read_cycle_count,
-        .mask           = CLOCKSOURCE_MASK(16),
-        .shift          = 16,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void avr32_timer_ack(void)
-{
-        u16 count = expirelo;
-
-        /* Ack this timer interrupt and set the next one, use a u16
-         * variable so it will wrap around correctly */
-        count += cycles_per_jiffy;
-        expirelo = count;
-        timer_write(ioregs, 0, RC, expirelo);
-
-        /* Check to see if we have missed any timer interrupts */
-        count = timer_read(ioregs, 0, CV);
-        if ((count - expirelo) < 0x7fff) {
-                expirelo = count + cycles_per_jiffy;
-                timer_write(ioregs, 0, RC, expirelo);
-        }
-}
-
-u32 avr32_hpt_read(void)
-{
-        return timer_read(ioregs, 0, CV);
-}
-
-static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
-{
-        unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
-        unsigned int divs[] = { 4, 8, 16, 32 };
-        int divs_size = ARRAY_SIZE(divs);
-        int i = 0;
-        unsigned long count_hz;
-        unsigned long shift;
-        unsigned long mult;
-        int clock_div = -1;
-        u64 tmp;
-
-        shift = clocksource_avr32.shift;
-
-        do {
-                count_hz = clk_get_rate(pclk) / divs[i];
-                mult = clocksource_hz2mult(count_hz, shift);
-                clocksource_avr32.mult = mult;
-
-                tmp = TICK_NSEC;
-                tmp <<= shift;
-                tmp += mult / 2;
-                do_div(tmp, mult);
-
-                cycles_per_jiffy = tmp;
-        } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
-
-        clock_div = i + 1;
-
-        if (clock_div > divs_size) {
-                pr_debug("timer: could not calculate clock divider\n");
-                return -EFAULT;
-        }
-
-        /* Set the clock divider */
-        timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
-
-        return 0;
-}
-
-int avr32_hpt_init(unsigned int count)
-{
-        struct resource *regs;
-        struct clk *pclk;
-        int irq = -1;
-        int ret = 0;
-
-        ret = -ENXIO;
-
-        irq = platform_get_irq(&at32_systc0_device, 0);
-        if (irq < 0) {
-                pr_debug("timer: could not get irq\n");
-                goto out_error;
-        }
-
-        pclk = clk_get(&at32_systc0_device.dev, "pclk");
-        if (IS_ERR(pclk)) {
-                pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
-                goto out_error;
-        }
-        clk_enable(pclk);
-
-        regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
-        if (!regs) {
-                pr_debug("timer: could not get resource\n");
-                goto out_error_clk;
-        }
-
-        ioregs = ioremap(regs->start, regs->end - regs->start + 1);
-        if (!ioregs) {
-                pr_debug("timer: could not get ioregs\n");
-                goto out_error_clk;
-        }
-
-        ret = avr32_timer_calc_div_and_set_jiffies(pclk);
-        if (ret)
-                goto out_error_io;
-
-        ret = setup_irq(irq, &timer_irqaction);
-        if (ret) {
-                pr_debug("timer: could not request irq %d: %d\n",
-                                irq, ret);
-                goto out_error_io;
-        }
-
-        expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
-                * cycles_per_jiffy;
-
-        /* Enable clock and interrupts on RC compare */
-        timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
-        timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
-        /* Set cycles to first interrupt */
-        timer_write(ioregs, 0,  RC, expirelo);
-
-        printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
-                        ioregs, irq);
-
-        return 0;
-
-out_error_io:
-        iounmap(ioregs);
-out_error_clk:
-        clk_put(pclk);
-out_error:
-        return ret;
-}
-
-int avr32_hpt_start(void)
-{
-        timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
-        return 0;
-}
-
-irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
-        unsigned int sr = timer_read(ioregs, 0, SR);
-
-        if (sr & TIMER_BIT(SR_CPCS)) {
-                /* ack timer interrupt and try to set next interrupt */
-                avr32_timer_ack();
-
-                /*
-                 * Call the generic timer interrupt handler
-                 */
-                write_seqlock(&xtime_lock);
-                do_timer(1);
-                write_sequnlock(&xtime_lock);
-
-                /*
-                 * In UP mode, we call local_timer_interrupt() to do profiling
-                 * and process accounting.
-                 *
-                 * SMP is not supported yet.
-                 */
-                local_timer_interrupt(irq, dev_id);
-
-                return IRQ_HANDLED;
-        }
-
-        return IRQ_NONE;
-}
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index 480760bde63f..0e64ddc45e37 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -34,9 +34,6 @@ struct page *empty_zero_page;
  */
 unsigned long mmu_context_cache = NO_CONTEXT;
 
-#define START_PFN       (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
-#define MAX_LOW_PFN     (NODE_DATA(0)->bdata->node_low_pfn)
-
 void show_mem(void)
 {
         int total = 0, reserved = 0, cached = 0;
diff --git a/arch/avr32/oprofile/op_model_avr32.c b/arch/avr32/oprofile/op_model_avr32.c
index e2f876bfc86b..df42325c7f81 100644
--- a/arch/avr32/oprofile/op_model_avr32.c
+++ b/arch/avr32/oprofile/op_model_avr32.c
@@ -16,7 +16,6 @@
 #include <linux/sched.h>
 #include <linux/types.h>
 
-#include <asm/intc.h>
 #include <asm/sysreg.h>
 #include <asm/system.h>
 
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 9bdc8f99183a..715b3945e4c7 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -39,8 +39,7 @@
 /* This is an NTP setting */
 #define TICK_SIZE (tick_nsec / 1000)
 
-static void time_sched_init(irqreturn_t(*timer_routine)
-                        (int, void *));
+static void time_sched_init(irq_handler_t timer_routine);
 static unsigned long gettimeoffset(void);
 
 static struct irqaction bfin_timer_irq = {
@@ -64,7 +63,7 @@ static struct irqaction bfin_timer_irq = {
 #define TIME_SCALE 1
 
 static void
-time_sched_init(irqreturn_t(*timer_routine) (int, void *))
+time_sched_init(irq_handler_t timer_routine)
 {
         u32 tcount;
 
diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c
index 779c3cca206c..b11bb50a197a 100644
--- a/arch/ia64/kernel/salinfo.c
+++ b/arch/ia64/kernel/salinfo.c
@@ -44,8 +44,8 @@
 #include <linux/smp.h>
 #include <linux/timer.h>
 #include <linux/vmalloc.h>
+#include <linux/semaphore.h>
 
-#include <asm/semaphore.h>
 #include <asm/sal.h>
 #include <asm/uaccess.h>
 
diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
index 4b0d1538e7e5..8cc0c4753d89 100644
--- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c
+++ b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
@@ -37,7 +37,6 @@
 
 #include <asm/processor.h>
 #include <asm/topology.h>
-#include <asm/semaphore.h>
 #include <asm/uaccess.h>
 #include <asm/sal.h>
 #include <asm/sn/io.h>
diff --git a/arch/m68k/atari/stram.c b/arch/m68k/atari/stram.c
index 0055a6c06f75..04c69ffbea71 100644
--- a/arch/m68k/atari/stram.c
+++ b/arch/m68k/atari/stram.c
@@ -29,7 +29,6 @@
 #include <asm/atarihw.h>
 #include <asm/atari_stram.h>
 #include <asm/io.h>
-#include <asm/semaphore.h>
 
 #undef DEBUG
 
diff --git a/arch/m68k/sun3/intersil.c b/arch/m68k/sun3/intersil.c
index db359d7402a6..0116d208d300 100644
--- a/arch/m68k/sun3/intersil.c
+++ b/arch/m68k/sun3/intersil.c
@@ -15,7 +15,6 @@
 
 #include <asm/errno.h>
 #include <asm/system.h>
-#include <asm/semaphore.h>
 #include <asm/rtc.h>
 #include <asm/intersil.h>
 
diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c
index 3ba830651c58..984e561f0f7a 100644
--- a/arch/mips/sgi-ip27/ip27-console.c
+++ b/arch/mips/sgi-ip27/ip27-console.c
@@ -8,7 +8,6 @@
 #include <linux/init.h>
 
 #include <asm/page.h>
-#include <asm/semaphore.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/sn0/hub.h>
 #include <asm/sn/klconfig.h>
diff --git a/arch/parisc/kernel/sys_parisc32.c b/arch/parisc/kernel/sys_parisc32.c
index 50bbf33ee00c..71efd6a28e2a 100644
--- a/arch/parisc/kernel/sys_parisc32.c
+++ b/arch/parisc/kernel/sys_parisc32.c
@@ -49,7 +49,6 @@
 
 #include <asm/types.h>
 #include <asm/uaccess.h>
-#include <asm/semaphore.h>
 #include <asm/mmu_context.h>
 
 #include "sys32.h"
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 1189d8d6170d..4bb2e9310a56 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -49,6 +49,19 @@ config IRQ_PER_CPU
         bool
         default y
 
+config STACKTRACE_SUPPORT
+        bool
+        default y
+
+config TRACE_IRQFLAGS_SUPPORT
+        bool
+        depends on PPC64
+        default y
+
+config LOCKDEP_SUPPORT
+        bool
+        default y
+
 config RWSEM_GENERIC_SPINLOCK
         bool
 
@@ -81,6 +94,11 @@ config GENERIC_FIND_NEXT_BIT
         bool
         default y
 
+config GENERIC_GPIO
+        bool
+        help
+          Generic GPIO API support
+
 config ARCH_NO_VIRT_TO_BUS
         def_bool PPC64
 
@@ -91,6 +109,7 @@ config PPC
         select HAVE_OPROFILE
         select HAVE_KPROBES
         select HAVE_KRETPROBES
+        select HAVE_LMB
 
 config EARLY_PRINTK
         bool
@@ -210,15 +229,6 @@ source kernel/Kconfig.hz
 source kernel/Kconfig.preempt
 source "fs/Kconfig.binfmt"
 
-# We optimistically allocate largepages from the VM, so make the limit
-# large enough (16MB). This badly named config option is actually
-# max order + 1
-config FORCE_MAX_ZONEORDER
-        int
-        depends on PPC64
-        default "9" if PPC_64K_PAGES
-        default "13"
-
 config HUGETLB_PAGE_SIZE_VARIABLE
         bool
         depends on HUGETLB_PAGE
@@ -307,6 +317,16 @@ config CRASH_DUMP
 
           Don't change this unless you know what you are doing.
 
+config PHYP_DUMP
+        bool "Hypervisor-assisted dump (EXPERIMENTAL)"
+        depends on PPC_PSERIES && EXPERIMENTAL
+        help
+          Hypervisor-assisted dump is meant to be a kdump replacement
+          offering robustness and speed not possible without system
+          hypervisor assistence.
+
+          If unsure, say "N"
+
 config PPCBUG_NVRAM
         bool "Enable reading PPCBUG NVRAM during boot" if PPLUS || LOPEC
         default y if PPC_PREP
@@ -381,6 +401,26 @@ config PPC_64K_PAGES
           while on hardware with such support, it will be used to map
           normal application pages.
 
+config FORCE_MAX_ZONEORDER
+        int "Maximum zone order"
+        default "9" if PPC_64K_PAGES
+        default "13" if PPC64 && !PPC_64K_PAGES
+        default "11"
+        help
+          The kernel memory allocator divides physically contiguous memory
+          blocks into "zones", where each zone is a power of two number of
+          pages.  This option selects the largest power of two that the kernel
+          keeps in the memory allocator.  If you need to allocate very large
+          blocks of physically contiguous memory, then you may need to
+          increase this value.
+
+          This config option is actually maximum order plus one. For example,
+          a value of 11 means that the largest free memory block is 2^10 pages.
+
+          The page size is not necessarily 4KB.  For example, on 64-bit
+          systems, 64KB pages can be enabled via CONFIG_PPC_64K_PAGES.  Keep
+          this in mind when choosing a value for this option.
+
 config PPC_SUBPAGE_PROT
         bool "Support setting protections for 4k subpages"
         depends on PPC_64K_PAGES
@@ -490,6 +530,14 @@ config FSL_PCI
         bool
         select PPC_INDIRECT_PCI
 
+config 4xx_SOC
+        bool
+
+config FSL_LBC
+        bool
+        help
+          Freescale Localbus support
+
 # Yes MCA RS/6000s exist but Linux-PPC does not currently support any
 config MCA
         bool
@@ -663,22 +711,6 @@ config CONSISTENT_SIZE
         hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL
         default "0x00200000" if NOT_COHERENT_CACHE
 
-config BOOT_LOAD_BOOL
-        bool "Set the boot link/load address"
-        depends on ADVANCED_OPTIONS && !PPC_MULTIPLATFORM
-        help
-          This option allows you to set the initial load address of the zImage
-          or zImage.initrd file.  This can be useful if you are on a board
-          which has a small amount of memory.
-
-          Say N here unless you know what you are doing.
-
-config BOOT_LOAD
-        hex "Link/load address for booting" if BOOT_LOAD_BOOL
-        default "0x00400000" if 40x || 8xx || 8260
-        default "0x01000000" if 44x
-        default "0x00800000"
-
 config PIN_TLB
         bool "Pinned Kernel TLBs (860 ONLY)"
         depends on ADVANCED_OPTIONS && 8xx
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index db7cc34c24d4..a86d8d853214 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -269,7 +269,7 @@ config PPC_EARLY_DEBUG_CPM_ADDR
         hex "CPM UART early debug transmit descriptor address"
         depends on PPC_EARLY_DEBUG_CPM
         default "0xfa202008" if PPC_EP88XC
-        default "0xf0000008" if CPM2
+        default "0xf0001ff8" if CPM2
         default "0xff002008" if CPM1
         help
           This specifies the address of the transmit descriptor
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index ab5cfe8ef988..e2ec4a91ccef 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -71,13 +71,11 @@ endif
 
 LDFLAGS_vmlinux := -Bstatic
 
-CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
-AFLAGS-$(CONFIG_PPC32)  := -Iarch/$(ARCH)
 CFLAGS-$(CONFIG_PPC64)  := -mminimal-toc -mtraceback=none  -mcall-aixdesc
-CFLAGS-$(CONFIG_PPC32)  := -Iarch/$(ARCH) -ffixed-r2 -mmultiple
-KBUILD_CPPFLAGS += $(CPPFLAGS-y)
-KBUILD_AFLAGS   += $(AFLAGS-y)
-KBUILD_CFLAGS   += -msoft-float -pipe $(CFLAGS-y)
+CFLAGS-$(CONFIG_PPC32)  := -ffixed-r2 -mmultiple
+KBUILD_CPPFLAGS += -Iarch/$(ARCH)
+KBUILD_AFLAGS   += -Iarch/$(ARCH)
+KBUILD_CFLAGS   += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
 CPP             = $(CC) -E $(KBUILD_CFLAGS)
 
 CHECKFLAGS      += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
@@ -164,7 +162,7 @@ boot := arch/$(ARCH)/boot
 $(BOOT_TARGETS): vmlinux
         $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
 
-bootwrapper_install:
+bootwrapper_install %.dtb:
         $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
 
 define archhelp
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 1aded8f759d0..5ba50c673390 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -40,6 +40,7 @@ $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
+$(obj)/virtex405-head.o: BOOTCFLAGS += -mcpu=405
 
 
 zlib       := inffast.c inflate.c inftrees.c
@@ -64,7 +65,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
                 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
                 fixed-head.S ep88xc.c ep405.c \
                 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
-                cuboot-warp.c cuboot-85xx-cpm2.c
+                cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
+                virtex405-head.S
 src-boot := $(src-wlib) $(src-plat) empty.c
 
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -192,7 +194,7 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
 image-$(CONFIG_PPC_EFIKA)               += zImage.chrp
 image-$(CONFIG_PPC_PMAC)                += zImage.pmac
 image-$(CONFIG_PPC_HOLLY)               += zImage.holly
-image-$(CONFIG_PPC_PRPMC2800)           += zImage.prpmc2800
+image-$(CONFIG_PPC_PRPMC2800)           += dtbImage.prpmc2800
 image-$(CONFIG_PPC_ISERIES)             += zImage.iseries
 image-$(CONFIG_DEFAULT_UIMAGE)          += uImage
 
@@ -216,6 +218,7 @@ image-$(CONFIG_RAINIER)			+= cuImage.rainier
 image-$(CONFIG_TAISHAN)                 += cuImage.taishan
 image-$(CONFIG_KATMAI)                  += cuImage.katmai
 image-$(CONFIG_WARP)                    += cuImage.warp
+image-$(CONFIG_YOSEMITE)                += cuImage.yosemite
 
 # Board ports in arch/powerpc/platform/8xx/Kconfig
 image-$(CONFIG_PPC_MPC86XADS)           += cuImage.mpc866ads
@@ -255,6 +258,7 @@ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
 image-$(CONFIG_TQM8560)                 += cuImage.tqm8560
 image-$(CONFIG_SBC8548)                 += cuImage.sbc8548
 image-$(CONFIG_SBC8560)                 += cuImage.sbc8560
+image-$(CONFIG_KSI8560)                 += cuImage.ksi8560
 
 # Board ports in arch/powerpc/platform/embedded6xx/Kconfig
 image-$(CONFIG_STORCENTER)              += cuImage.storcenter
@@ -285,11 +289,11 @@ $(obj)/zImage.%: vmlinux $(wrapperbits)
         $(call if_changed,wrap,$*)
 
 # dtbImage% - a dtbImage is a zImage with an embedded device tree blob
-$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(dtstree)/%.dts
-        $(call if_changed,wrap,$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz)
+$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(obj)/%.dtb
+        $(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 
-$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(dtstree)/%.dts
-        $(call if_changed,wrap,$*,$(dtstree)/$*.dts)
+$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
+        $(call if_changed,wrap,$*,,$(obj)/$*.dtb)
 
 # This cannot be in the root of $(src) as the zImage rule always adds a $(obj)
 # prefix
@@ -302,14 +306,24 @@ $(obj)/zImage.iseries: vmlinux
 $(obj)/uImage: vmlinux $(wrapperbits)
         $(call if_changed,wrap,uboot)
 
-$(obj)/cuImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
-        $(call if_changed,wrap,cuboot-$*,$(dtstree)/$*.dts)
+$(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+        $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb)
 
-$(obj)/treeImage.initrd.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
-        $(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz)
+$(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+        $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 
-$(obj)/treeImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
-        $(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts)
+$(obj)/simpleImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+        $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb)
+
+$(obj)/treeImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+        $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
+
+$(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+        $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
+
+# Rule to build device tree blobs
+$(obj)/%.dtb: $(dtstree)/%.dts $(obj)/dtc
+        $(obj)/dtc -O dtb -o $(obj)/$*.dtb -b 0 $(DTS_FLAGS) $(dtstree)/$*.dts
 
 # If there isn't a platform selected then just strip the vmlinux.
 ifeq (,$(image-y))
@@ -326,7 +340,7 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
 
 # anything not in $(targets)
 clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* treeImage.* \
-        otheros.bld
+        otheros.bld *.dtb
 
 # clean up files cached by wrapper
 clean-kernel := vmlinux.strip vmlinux.bin
diff --git a/arch/powerpc/boot/bamboo.c b/arch/powerpc/boot/bamboo.c
index 54b33f1500e2..b82cacbc60db 100644
--- a/arch/powerpc/boot/bamboo.c
+++ b/arch/powerpc/boot/bamboo.c
@@ -33,7 +33,8 @@ static void bamboo_fixups(void)
         ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
         ibm4xx_sdram_fixup_memsize();
         ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
-        dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
+        dt_fixup_mac_address_by_alias("ethernet0", bamboo_mac0);
+        dt_fixup_mac_address_by_alias("ethernet1", bamboo_mac1);
 }
 
 void bamboo_init(void *mac0, void *mac1)
diff --git a/arch/powerpc/boot/cpm-serial.c b/arch/powerpc/boot/cpm-serial.c
index 28296facb2ae..19dc15abe43d 100644
--- a/arch/powerpc/boot/cpm-serial.c
+++ b/arch/powerpc/boot/cpm-serial.c
@@ -11,6 +11,7 @@
 #include "types.h"
 #include "io.h"
 #include "ops.h"
+#include "page.h"
 
 struct cpm_scc {
         u32 gsmrl;
@@ -42,6 +43,22 @@ struct cpm_param {
         u16 tbase;
         u8 rfcr;
         u8 tfcr;
+        u16 mrblr;
+        u32 rstate;
+        u8 res1[4];
+        u16 rbptr;
+        u8 res2[6];
+        u32 tstate;
+        u8 res3[4];
+        u16 tbptr;
+        u8 res4[6];
+        u16 maxidl;
+        u16 idlc;
+        u16 brkln;
+        u16 brkec;
+        u16 brkcr;
+        u16 rmask;
+        u8 res5[4];
 };
 
 struct cpm_bd {
@@ -54,10 +71,10 @@ static void *cpcr;
 static struct cpm_param *param;
 static struct cpm_smc *smc;
 static struct cpm_scc *scc;
-struct cpm_bd *tbdf, *rbdf;
+static struct cpm_bd *tbdf, *rbdf;
 static u32 cpm_cmd;
-static u8 *muram_start;
-static u32 muram_offset;
+static void *cbd_addr;
+static u32 cbd_offset;
 
 static void (*do_cmd)(int op);
 static void (*enable_port)(void);
@@ -119,20 +136,25 @@ static int cpm_serial_open(void)
 
         out_8(&param->rfcr, 0x10);
         out_8(&param->tfcr, 0x10);
-
-        rbdf = (struct cpm_bd *)muram_start;
-        rbdf->addr = (u8 *)(rbdf + 2);
+        out_be16(&param->mrblr, 1);
+        out_be16(&param->maxidl, 0);
+        out_be16(&param->brkec, 0);
+        out_be16(&param->brkln, 0);
+        out_be16(&param->brkcr, 0);
+
+        rbdf = cbd_addr;
+        rbdf->addr = (u8 *)rbdf - 1;
         rbdf->sc = 0xa000;
         rbdf->len = 1;
 
         tbdf = rbdf + 1;
-        tbdf->addr = (u8 *)(rbdf + 2) + 1;
+        tbdf->addr = (u8 *)rbdf - 2;
         tbdf->sc = 0x2000;
         tbdf->len = 1;
 
         sync();
-        out_be16(&param->rbase, muram_offset);
-        out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd));
+        out_be16(&param->rbase, cbd_offset);
+        out_be16(&param->tbase, cbd_offset + sizeof(struct cpm_bd));
 
         do_cmd(CPM_CMD_INIT_RX_TX);
 
@@ -175,10 +197,12 @@ static unsigned char cpm_serial_getc(void)
 
 int cpm_console_init(void *devp, struct serial_console_data *scdp)
 {
-        void *reg_virt[2];
-        int is_smc = 0, is_cpm2 = 0, n;
-        unsigned long reg_phys;
+        void *vreg[2];
+        u32 reg[2];
+        int is_smc = 0, is_cpm2 = 0;
         void *parent, *muram;
+        void *muram_addr;
+        unsigned long muram_offset, muram_size;
 
         if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
                 is_smc = 1;
@@ -202,63 +226,64 @@ int cpm_console_init(void *devp, struct serial_console_data *scdp)
         else
                 do_cmd = cpm1_cmd;
 
-        n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4);
-        if (n < 4)
+        if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
                 return -1;
 
-        n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt));
-        if (n < (int)sizeof(reg_virt)) {
-                for (n = 0; n < 2; n++) {
-                        if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
-                                return -1;
-
-                        reg_virt[n] = (void *)reg_phys;
-                }
-        }
+        if (dt_get_virtual_reg(devp, vreg, 2) < 2)
+                return -1;
 
         if (is_smc)
-                smc = reg_virt[0];
+                smc = vreg[0];
         else
-                scc = reg_virt[0];
+                scc = vreg[0];
 
-        param = reg_virt[1];
+        param = vreg[1];
 
         parent = get_parent(devp);
         if (!parent)
                 return -1;
 
-        n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt));
-        if (n < (int)sizeof(reg_virt)) {
-                if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
-                        return -1;
-
-                reg_virt[0] = (void *)reg_phys;
-        }
-
-        cpcr = reg_virt[0];
+        if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
+                return -1;
 
         muram = finddevice("/soc/cpm/muram/data");
         if (!muram)
                 return -1;
 
         /* For bootwrapper-compatible device trees, we assume that the first
-         * entry has at least 18 bytes, and that #address-cells/#data-cells
+         * entry has at least 128 bytes, and that #address-cells/#data-cells
          * is one for both parent and child.
          */
 
-        n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt));
-        if (n < (int)sizeof(reg_virt)) {
-                if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
-                        return -1;
+        if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
+                return -1;
 
-                reg_virt[0] = (void *)reg_phys;
-        }
+        if (getprop(muram, "reg", reg, 8) < 8)
+                return -1;
 
-        muram_start = reg_virt[0];
+        muram_offset = reg[0];
+        muram_size = reg[1];
 
-        n = getprop(muram, "reg", &muram_offset, 4);
-        if (n < 4)
-                return -1;
+        /* Store the buffer descriptors at the end of the first muram chunk.
+         * For SMC ports on CPM2-based platforms, relocate the parameter RAM
+         * just before the buffer descriptors.
+         */
+
+        cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
+
+        if (is_cpm2 && is_smc) {
+                u16 *smc_base = (u16 *)param;
+                u16 pram_offset;
+
+                pram_offset = cbd_offset - 64;
+                pram_offset = _ALIGN_DOWN(pram_offset, 64);
+
+                disable_port();
+                out_be16(smc_base, pram_offset);
+                param = muram_addr - muram_offset + pram_offset;
+        }
+
+        cbd_addr = muram_addr - muram_offset + cbd_offset;
 
         scdp->open = cpm_serial_open;
         scdp->putc = cpm_serial_putc;
diff --git a/arch/powerpc/boot/cuboot-pq2.c b/arch/powerpc/boot/cuboot-pq2.c
index f56ac6cae9f3..9c7d13428293 100644
--- a/arch/powerpc/boot/cuboot-pq2.c
+++ b/arch/powerpc/boot/cuboot-pq2.c
@@ -128,7 +128,7 @@ static void fixup_pci(void)
         u8 *soc_regs;
         int i, len;
         void *node, *parent_node;
-        u32 naddr, nsize, mem_log2;
+        u32 naddr, nsize, mem_pow2, mem_mask;
 
         node = finddevice("/pci");
         if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
@@ -141,7 +141,7 @@ static void fixup_pci(void)
 
         soc_regs = (u8 *)fsl_get_immr();
         if (!soc_regs)
-                goto err;
+                goto unhandled;
 
         dt_get_reg_format(node, &naddr, &nsize);
         if (naddr != 3 || nsize != 2)
@@ -153,7 +153,7 @@ static void fixup_pci(void)
 
         dt_get_reg_format(parent_node, &naddr, &nsize);
         if (naddr != 1 || nsize != 1)
-                goto err;
+                goto unhandled;
 
         len = getprop(node, "ranges", pci_ranges_buf,
                       sizeof(pci_ranges_buf));
@@ -170,14 +170,20 @@ static void fixup_pci(void)
         }
 
         if (!mem || !mmio || !io)
-                goto err;
+                goto unhandled;
+        if (mem->size[1] != mmio->size[1])
+                goto unhandled;
+        if (mem->size[1] & (mem->size[1] - 1))
+                goto unhandled;
+        if (io->size[1] & (io->size[1] - 1))
+                goto unhandled;
 
         if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
                 mem_base = mem;
         else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
                 mem_base = mmio;
         else
-                goto err;
+                goto unhandled;
 
         out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
         out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
@@ -201,8 +207,9 @@ static void fixup_pci(void)
         out_le32(&pci_regs[0][58], 0);
         out_le32(&pci_regs[0][60], 0);
 
-        mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
-        out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
+        mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
+        mem_mask = ~(mem_pow2 - 1) >> 12;
+        out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
 
         /* If PCI is disabled, drive RST high to enable. */
         if (!(in_le32(&pci_regs[0][32]) & 1)) {
@@ -228,7 +235,11 @@ static void fixup_pci(void)
         return;
 
 err:
-        printf("Bad PCI node\r\n");
+        printf("Bad PCI node -- using existing firmware setup.\r\n");
+        return;
+
+unhandled:
+        printf("Unsupported PCI node -- using existing firmware setup.\r\n");
 }
 
 static void pq2_platform_fixups(void)
diff --git a/arch/powerpc/boot/cuboot-rainier.c b/arch/powerpc/boot/cuboot-rainier.c
index cf452b66dce8..0a3fddee54df 100644
--- a/arch/powerpc/boot/cuboot-rainier.c
+++ b/arch/powerpc/boot/cuboot-rainier.c
@@ -42,7 +42,8 @@ static void rainier_fixups(void)
         ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
         ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
         ibm4xx_denali_fixup_memsize();
-        dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
+        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+        dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
 }
 
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
diff --git a/arch/powerpc/boot/cuboot-sequoia.c b/arch/powerpc/boot/cuboot-sequoia.c
index f555575a44de..caf8f2e842ea 100644
--- a/arch/powerpc/boot/cuboot-sequoia.c
+++ b/arch/powerpc/boot/cuboot-sequoia.c
@@ -42,7 +42,8 @@ static void sequoia_fixups(void)
         ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
         ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
         ibm4xx_denali_fixup_memsize();
-        dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
+        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+        dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
 }
 
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
diff --git a/arch/powerpc/boot/cuboot-taishan.c b/arch/powerpc/boot/cuboot-taishan.c
index b55b80467eed..9bc906a754dd 100644
--- a/arch/powerpc/boot/cuboot-taishan.c
+++ b/arch/powerpc/boot/cuboot-taishan.c
@@ -40,7 +40,8 @@ static void taishan_fixups(void)
 
         ibm4xx_sdram_fixup_memsize();
 
-        dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
+        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+        dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
 
         ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
 }
diff --git a/arch/powerpc/boot/cuboot-warp.c b/arch/powerpc/boot/cuboot-warp.c
index 3db93e85e9ea..eb108a877492 100644
--- a/arch/powerpc/boot/cuboot-warp.c
+++ b/arch/powerpc/boot/cuboot-warp.c
@@ -24,7 +24,7 @@ static void warp_fixups(void)
         ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
         ibm4xx_sdram_fixup_memsize();
         ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
-        dt_fixup_mac_addresses(&bd.bi_enetaddr);
+        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
 }
 
 
diff --git a/arch/powerpc/boot/cuboot-yosemite.c b/arch/powerpc/boot/cuboot-yosemite.c
new file mode 100644
index 000000000000..cc6e338c5d0d
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-yosemite.c
@@ -0,0 +1,44 @@
+/*
+ * Old U-boot compatibility for Yosemite
+ *
+ * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Copyright 2008 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "4xx.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_4xx
+#define TARGET_44x
+#include "ppcboot.h"
+
+static bd_t bd;
+
+static void yosemite_fixups(void)
+{
+        unsigned long sysclk = 66666666;
+
+        ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
+        ibm4xx_sdram_fixup_memsize();
+        ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
+        dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+        dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+                unsigned long r6, unsigned long r7)
+{
+        CUBOOT_INIT();
+        platform_ops.fixups = yosemite_fixups;
+        platform_ops.exit = ibm44x_dbcr_reset;
+        fdt_init(_dtb_start);
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/devtree.c b/arch/powerpc/boot/devtree.c
index 60f561e307a9..5d12336dc360 100644
--- a/arch/powerpc/boot/devtree.c
+++ b/arch/powerpc/boot/devtree.c
@@ -350,3 +350,23 @@ int dt_is_compatible(void *node, const char *compat)
 
         return 0;
 }
+
+int dt_get_virtual_reg(void *node, void **addr, int nres)
+{
+        unsigned long xaddr;
+        int n;
+
+        n = getprop(node, "virtual-reg", addr, nres * 4);
+        if (n > 0)
+                return n / 4;
+
+        for (n = 0; n < nres; n++) {
+                if (!dt_xlate_reg(node, n, &xaddr, NULL))
+                        break;
+
+                addr[n] = (void *)xaddr;
+        }
+
+        return n;
+}
+
diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts
index 7dc37c9a7446..ba2521bdaab1 100644
--- a/arch/powerpc/boot/dts/bamboo.dts
+++ b/arch/powerpc/boot/dts/bamboo.dts
@@ -204,7 +204,6 @@
                         };
 
                         EMAC0: ethernet@ef600e00 {
-                                linux,network-index = <0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
                                 interrupt-parent = <&UIC1>;
@@ -225,7 +224,6 @@
                         };
 
                         EMAC1: ethernet@ef600f00 {
-                                linux,network-index = <1>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
                                 interrupt-parent = <&UIC1>;
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
new file mode 100644
index 000000000000..6f3d38a1554f
--- /dev/null
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -0,0 +1,402 @@
+/*
+ * Device Tree Source for AMCC Canyonlands (460EX)
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        model = "amcc,canyonlands";
+        compatible = "amcc,canyonlands";
+        dcr-parent = <&/cpus/cpu@0>;
+
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+                serial0 = &UART0;
+                serial1 = &UART1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,460EX";
+                        reg = <0>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+                        timebase-frequency = <0>; /* Filled in by U-Boot */
+                        i-cache-line-size = <20>;
+                        d-cache-line-size = <20>;
+                        i-cache-size = <8000>;
+                        d-cache-size = <8000>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0>; /* Filled in by U-Boot */
+        };
+
+        UIC0: interrupt-controller0 {
+                compatible = "ibm,uic-460ex","ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0c0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+
+        UIC1: interrupt-controller1 {
+                compatible = "ibm,uic-460ex","ibm,uic";
+                interrupt-controller;
+                cell-index = <1>;
+                dcr-reg = <0d0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <1e 4 1f 4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC2: interrupt-controller2 {
+                compatible = "ibm,uic-460ex","ibm,uic";
+                interrupt-controller;
+                cell-index = <2>;
+                dcr-reg = <0e0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <a 4 b 4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC3: interrupt-controller3 {
+                compatible = "ibm,uic-460ex","ibm,uic";
+                interrupt-controller;
+                cell-index = <3>;
+                dcr-reg = <0f0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <10 4 11 4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        SDR0: sdr {
+                compatible = "ibm,sdr-460ex";
+                dcr-reg = <00e 002>;
+        };
+
+        CPR0: cpr {
+                compatible = "ibm,cpr-460ex";
+                dcr-reg = <00c 002>;
+        };
+
+        plb {
+                compatible = "ibm,plb-460ex", "ibm,plb4";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by U-Boot */
+
+                SDRAM0: sdram {
+                        compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
+                        dcr-reg = <010 2>;
+                };
+
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
+                        dcr-reg = <180 62>;
+                        num-tx-chans = <2>;
+                        num-rx-chans = <10>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&UIC2>;
+                        interrupts = <  /*TXEOB*/ 6 4
+                                        /*RXEOB*/ 7 4
+                                        /*SERR*/  3 4
+                                        /*TXDE*/  4 4
+                                        /*RXDE*/  5 4>;
+                };
+
+                POB0: opb {
+                        compatible = "ibm,opb-460ex", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <b0000000 4 b0000000 50000000>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+
+                        EBC0: ebc {
+                                compatible = "ibm,ebc-460ex", "ibm,ebc";
+                                dcr-reg = <012 2>;
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                interrupts = <6 4>;
+                                interrupt-parent = <&UIC1>;
+                        };
+
+                        UART0: serial@ef600300 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600300 8>;
+                                virtual-reg = <ef600300>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1 4>;
+                        };
+
+                        UART1: serial@ef600400 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600400 8>;
+                                virtual-reg = <ef600400>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <1 4>;
+                        };
+
+                        UART2: serial@ef600500 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600500 8>;
+                                virtual-reg = <ef600500>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1d 4>;
+                        };
+
+                        UART3: serial@ef600600 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600600 8>;
+                                virtual-reg = <ef600600>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1e 4>;
+                        };
+
+                        IIC0: i2c@ef600700 {
+                                compatible = "ibm,iic-460ex", "ibm,iic";
+                                reg = <ef600700 14>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <2 4>;
+                        };
+
+                        IIC1: i2c@ef600800 {
+                                compatible = "ibm,iic-460ex", "ibm,iic";
+                                reg = <ef600800 14>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <3 4>;
+                        };
+
+                        ZMII0: emac-zmii@ef600d00 {
+                                compatible = "ibm,zmii-460ex", "ibm,zmii";
+                                reg = <ef600d00 c>;
+                        };
+
+                        RGMII0: emac-rgmii@ef601500 {
+                                compatible = "ibm,rgmii-460ex", "ibm,rgmii";
+                                reg = <ef601500 8>;
+                                has-mdio;
+                        };
+
+                        TAH0: emac-tah@ef601350 {
+                                compatible = "ibm,tah-460ex", "ibm,tah";
+                                reg = <ef601350 30>;
+                        };
+
+                        TAH1: emac-tah@ef601450 {
+                                compatible = "ibm,tah-460ex", "ibm,tah";
+                                reg = <ef601450 30>;
+                        };
+
+                        EMAC0: ethernet@ef600e00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460ex", "ibm,emac4";
+                                interrupt-parent = <&EMAC0>;
+                                interrupts = <0 1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0 &UIC2 10 4
+                                                 /*Wake*/   1 &UIC2 14 4>;
+                                reg = <ef600e00 70>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0>;
+                                mal-rx-channel = <0>;
+                                cell-index = <0>;
+                                max-frame-size = <2328>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rgmii";
+                                phy-map = <00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <0>;
+                                tah-device = <&TAH0>;
+                                tah-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+
+                        EMAC1: ethernet@ef600f00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460ex", "ibm,emac4";
+                                interrupt-parent = <&EMAC1>;
+                                interrupts = <0 1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0 &UIC2 11 4
+                                                 /*Wake*/   1 &UIC2 15 4>;
+                                reg = <ef600f00 70>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <1>;
+                                mal-rx-channel = <8>;
+                                cell-index = <1>;
+                                max-frame-size = <2328>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rgmii";
+                                phy-map = <00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <1>;
+                                tah-device = <&TAH1>;
+                                tah-channel = <1>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+                };
+
+                PCIX0: pci@c0ec00000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
+                        primary;
+                        large-inbound-windows;
+                        enable-msi-hole;
+                        reg = <c 0ec00000   8   /* Config space access */
+                               0 0 0            /* no IACK cycles */
+                               c 0ed00000   4   /* Special cycles */
+                               c 0ec80000 100   /* Internal registers */
+                               c 0ec80100  fc>; /* Internal messaging registers */
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed
+                         */
+                        ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
+                                  01000000 0 00000000 0000000c 08000000 0 00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                        /* This drives busses 0 to 0x3f */
+                        bus-range = <0 3f>;
+
+                        /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+                        interrupt-map-mask = <0000 0 0 0>;
+                        interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
+                };
+
+                PCIE0: pciex@d00000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+                        primary;
+                        port = <0>; /* port number */
+                        reg = <d 00000000 20000000      /* Config space access */
+                               c 08010000 00001000>;    /* Registers */
+                        dcr-reg = <100 020>;
+                        sdr-base = <300>;
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed
+                         */
+                        ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
+                                  01000000 0 00000000 0000000f 80000000 0 00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                        /* This drives busses 40 to 0x7f */
+                        bus-range = <40 7f>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0000 0 0 7>;
+                        interrupt-map = <
+                                0000 0 0 1 &UIC3 c 4 /* swizzled int A */
+                                0000 0 0 2 &UIC3 d 4 /* swizzled int B */
+                                0000 0 0 3 &UIC3 e 4 /* swizzled int C */
+                                0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
+                };
+
+                PCIE1: pciex@d20000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+                        primary;
+                        port = <1>; /* port number */
+                        reg = <d 20000000 20000000      /* Config space access */
+                               c 08011000 00001000>;    /* Registers */
+                        dcr-reg = <120 020>;
+                        sdr-base = <340>;
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed
+                         */
+                        ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
+                                  01000000 0 00000000 0000000f 80010000 0 00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                        /* This drives busses 80 to 0xbf */
+                        bus-range = <80 bf>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0000 0 0 7>;
+                        interrupt-map = <
+                                0000 0 0 1 &UIC3 10 4 /* swizzled int A */
+                                0000 0 0 2 &UIC3 11 4 /* swizzled int B */
+                                0000 0 0 3 &UIC3 12 4 /* swizzled int C */
+                                0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index 0b000cb7ed8b..5079dc890e0e 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -241,7 +241,6 @@
                         };
 
                         EMAC0: ethernet@40000800 {
-                                linux,network-index = <0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440gp", "ibm,emac";
                                 interrupt-parent = <&UIC1>;
@@ -261,7 +260,6 @@
                                 zmii-channel = <0>;
                         };
                         EMAC1: ethernet@40000900 {
-                                linux,network-index = <1>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440gp", "ibm,emac";
                                 interrupt-parent = <&UIC1>;
diff --git a/arch/powerpc/boot/dts/ep8248e.dts b/arch/powerpc/boot/dts/ep8248e.dts
index 5d2fb76a72c1..756758fb5b7b 100644
--- a/arch/powerpc/boot/dts/ep8248e.dts
+++ b/arch/powerpc/boot/dts/ep8248e.dts
@@ -121,8 +121,7 @@
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 0x1100 0x1140
-                                               0xec0 0x9800 0x800>;
+                                        reg = <0 0x2000 0x9800 0x800>;
                                 };
                         };
 
@@ -138,7 +137,7 @@
                                 device_type = "serial";
                                 compatible = "fsl,mpc8248-smc-uart",
                                              "fsl,cpm2-smc-uart";
-                                reg = <0x11a80 0x20 0x1100 0x40>;
+                                reg = <0x11a80 0x20 0x87fc 2>;
                                 interrupts = <4 8>;
                                 interrupt-parent = <&PIC>;
                                 fsl,cpm-brg = <7>;
diff --git a/arch/powerpc/boot/dts/ep88xc.dts b/arch/powerpc/boot/dts/ep88xc.dts
index 02705f299790..ae57d6240120 100644
--- a/arch/powerpc/boot/dts/ep88xc.dts
+++ b/arch/powerpc/boot/dts/ep88xc.dts
@@ -2,7 +2,7 @@
  * EP88xC Device Tree Source
  *
  * Copyright 2006 MontaVista Software, Inc.
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2008 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -10,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "EP88xC";
@@ -23,44 +24,44 @@
 
                 PowerPC,885@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <d#16>;
-                        i-cache-line-size = <d#16>;
-                        d-cache-size = <d#8192>;
-                        i-cache-size = <d#8192>;
+                        reg = <0x0>;
+                        d-cache-line-size = <16>;
+                        i-cache-line-size = <16>;
+                        d-cache-size = <8192>;
+                        i-cache-size = <8192>;
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
-                        interrupts = <f 2>;     // decrementer interrupt
+                        interrupts = <15 2>;    // decrementer interrupt
                         interrupt-parent = <&PIC>;
                 };
         };
 
         memory {
                 device_type = "memory";
-                reg = <0 0>;
+                reg = <0x0 0x0>;
         };
 
         localbus@fa200100 {
                 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
                 #address-cells = <2>;
                 #size-cells = <1>;
-                reg = <fa200100 40>;
+                reg = <0xfa200100 0x40>;
 
                 ranges = <
-                        0 0 fc000000 04000000
-                        3 0 fa000000 01000000
+                        0x0 0x0 0xfc000000 0x4000000
+                        0x3 0x0 0xfa000000 0x1000000
                 >;
 
                 flash@0,2000000 {
                         compatible = "cfi-flash";
-                        reg = <0 2000000 2000000>;
+                        reg = <0x0 0x2000000 0x2000000>;
                         bank-width = <4>;
                         device-width = <2>;
                 };
 
                 board-control@3,400000 {
-                        reg = <3 400000 10>;
+                        reg = <0x3 0x400000 0x10>;
                         compatible = "fsl,ep88xc-bcsr";
                 };
         };
@@ -70,25 +71,25 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 fa200000 00004000>;
+                ranges = <0x0 0xfa200000 0x4000>;
                 bus-frequency = <0>;
 
                 // Temporary -- will go away once kernel uses ranges for get_immrbase().
-                reg = <fa200000 4000>;
+                reg = <0xfa200000 0x4000>;
 
                 mdio@e00 {
                         compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
-                        reg = <e00 188>;
+                        reg = <0xe00 0x188>;
                         #address-cells = <1>;
                         #size-cells = <0>;
 
                         PHY0: ethernet-phy@0 {
-                                reg = <0>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
 
                         PHY1: ethernet-phy@1 {
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -97,7 +98,7 @@
                         device_type = "network";
                         compatible = "fsl,mpc885-fec-enet",
                                      "fsl,pq1-fec-enet";
-                        reg = <e00 188>;
+                        reg = <0xe00 0x188>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <3 1>;
                         interrupt-parent = <&PIC>;
@@ -109,7 +110,7 @@
                         device_type = "network";
                         compatible = "fsl,mpc885-fec-enet",
                                      "fsl,pq1-fec-enet";
-                        reg = <1e00 188>;
+                        reg = <0x1e00 0x188>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <7 1>;
                         interrupt-parent = <&PIC>;
@@ -120,7 +121,7 @@
                 PIC: interrupt-controller@0 {
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        reg = <0 24>;
+                        reg = <0x0 0x24>;
                         compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
                 };
 
@@ -130,29 +131,29 @@
                         #size-cells = <2>;
                         compatible = "fsl,pq-pcmcia";
                         device_type = "pcmcia";
-                        reg = <80 80>;
+                        reg = <0x80 0x80>;
                         interrupt-parent = <&PIC>;
-                        interrupts = <d 1>;
+                        interrupts = <13 1>;
                 };
 
                 cpm@9c0 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,mpc885-cpm", "fsl,cpm1";
-                        command-proc = <9c0>;
+                        command-proc = <0x9c0>;
                         interrupts = <0>;       // cpm error interrupt
                         interrupt-parent = <&CPM_PIC>;
-                        reg = <9c0 40>;
+                        reg = <0x9c0 0x40>;
                         ranges;
 
                         muram@2000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 2000 2000>;
+                                ranges = <0x0 0x2000 0x2000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 1c00>;
+                                        reg = <0x0 0x1c00>;
                                 };
                         };
 
@@ -160,7 +161,7 @@
                                 compatible = "fsl,mpc885-brg",
                                              "fsl,cpm1-brg",
                                              "fsl,cpm-brg";
-                                reg = <9f0 10>;
+                                reg = <0x9f0 0x10>;
                         };
 
                         CPM_PIC: interrupt-controller@930 {
@@ -168,7 +169,7 @@
                                 #interrupt-cells = <1>;
                                 interrupts = <5 2 0 2>;
                                 interrupt-parent = <&PIC>;
-                                reg = <930 20>;
+                                reg = <0x930 0x20>;
                                 compatible = "fsl,mpc885-cpm-pic",
                                              "fsl,cpm1-pic";
                         };
@@ -178,11 +179,11 @@
                                 device_type = "serial";
                                 compatible = "fsl,mpc885-smc-uart",
                                              "fsl,cpm1-smc-uart";
-                                reg = <a80 10 3e80 40>;
+                                reg = <0xa80 0x10 0x3e80 0x40>;
                                 interrupts = <4>;
                                 interrupt-parent = <&CPM_PIC>;
                                 fsl,cpm-brg = <1>;
-                                fsl,cpm-command = <0090>;
+                                fsl,cpm-command = <0x90>;
                                 linux,planetcore-label = "SMC1";
                         };
 
@@ -191,11 +192,11 @@
                                 device_type = "serial";
                                 compatible = "fsl,mpc885-scc-uart",
                                              "fsl,cpm1-scc-uart";
-                                reg = <a20 20 3d00 80>;
-                                interrupts = <1d>;
+                                reg = <0xa20 0x20 0x3d00 0x80>;
+                                interrupts = <29>;
                                 interrupt-parent = <&CPM_PIC>;
                                 fsl,cpm-brg = <2>;
-                                fsl,cpm-command = <0040>;
+                                fsl,cpm-command = <0x40>;
                                 linux,planetcore-label = "SCC2";
                         };
 
@@ -204,9 +205,9 @@
                                 #size-cells = <0>;
                                 compatible = "fsl,mpc885-usb",
                                              "fsl,cpm1-usb";
-                                reg = <a00 18 1c00 80>;
+                                reg = <0xa00 0x18 0x1c00 0x80>;
                                 interrupt-parent = <&CPM_PIC>;
-                                interrupts = <1e>;
+                                interrupts = <30>;
                                 fsl,cpm-command = <0000>;
                         };
                 };
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
new file mode 100644
index 000000000000..958a5ca53d35
--- /dev/null
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -0,0 +1,467 @@
+/*
+ * Device Tree Source for AMCC Glacier (460GT)
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        model = "amcc,glacier";
+        compatible = "amcc,glacier", "amcc,canyonlands";
+        dcr-parent = <&/cpus/cpu@0>;
+
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+                ethernet2 = &EMAC2;
+                ethernet3 = &EMAC3;
+                serial0 = &UART0;
+                serial1 = &UART1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,460GT";
+                        reg = <0>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+                        timebase-frequency = <0>; /* Filled in by U-Boot */
+                        i-cache-line-size = <20>;
+                        d-cache-line-size = <20>;
+                        i-cache-size = <8000>;
+                        d-cache-size = <8000>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0>; /* Filled in by U-Boot */
+        };
+
+        UIC0: interrupt-controller0 {
+                compatible = "ibm,uic-460gt","ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0c0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+
+        UIC1: interrupt-controller1 {
+                compatible = "ibm,uic-460gt","ibm,uic";
+                interrupt-controller;
+                cell-index = <1>;
+                dcr-reg = <0d0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <1e 4 1f 4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC2: interrupt-controller2 {
+                compatible = "ibm,uic-460gt","ibm,uic";
+                interrupt-controller;
+                cell-index = <2>;
+                dcr-reg = <0e0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <a 4 b 4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        UIC3: interrupt-controller3 {
+                compatible = "ibm,uic-460gt","ibm,uic";
+                interrupt-controller;
+                cell-index = <3>;
+                dcr-reg = <0f0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <10 4 11 4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        SDR0: sdr {
+                compatible = "ibm,sdr-460gt";
+                dcr-reg = <00e 002>;
+        };
+
+        CPR0: cpr {
+                compatible = "ibm,cpr-460gt";
+                dcr-reg = <00c 002>;
+        };
+
+        plb {
+                compatible = "ibm,plb-460gt", "ibm,plb4";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by U-Boot */
+
+                SDRAM0: sdram {
+                        compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
+                        dcr-reg = <010 2>;
+                };
+
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
+                        dcr-reg = <180 62>;
+                        num-tx-chans = <4>;
+                        num-rx-chans = <20>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&UIC2>;
+                        interrupts = <  /*TXEOB*/ 6 4
+                                        /*RXEOB*/ 7 4
+                                        /*SERR*/  3 4
+                                        /*TXDE*/  4 4
+                                        /*RXDE*/  5 4>;
+                        desc-base-addr-high = <8>;
+                };
+
+                POB0: opb {
+                        compatible = "ibm,opb-460gt", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <b0000000 4 b0000000 50000000>;
+                        clock-frequency = <0>; /* Filled in by U-Boot */
+
+                        EBC0: ebc {
+                                compatible = "ibm,ebc-460gt", "ibm,ebc";
+                                dcr-reg = <012 2>;
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                interrupts = <6 4>;
+                                interrupt-parent = <&UIC1>;
+                        };
+
+                        UART0: serial@ef600300 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600300 8>;
+                                virtual-reg = <ef600300>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1 4>;
+                        };
+
+                        UART1: serial@ef600400 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600400 8>;
+                                virtual-reg = <ef600400>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <1 4>;
+                        };
+
+                        UART2: serial@ef600500 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600500 8>;
+                                virtual-reg = <ef600500>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1d 4>;
+                        };
+
+                        UART3: serial@ef600600 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600600 8>;
+                                virtual-reg = <ef600600>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1e 4>;
+                        };
+
+                        IIC0: i2c@ef600700 {
+                                compatible = "ibm,iic-460gt", "ibm,iic";
+                                reg = <ef600700 14>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <2 4>;
+                        };
+
+                        IIC1: i2c@ef600800 {
+                                compatible = "ibm,iic-460gt", "ibm,iic";
+                                reg = <ef600800 14>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <3 4>;
+                        };
+
+                        ZMII0: emac-zmii@ef600d00 {
+                                compatible = "ibm,zmii-460gt", "ibm,zmii";
+                                reg = <ef600d00 c>;
+                        };
+
+                        RGMII0: emac-rgmii@ef601500 {
+                                compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+                                reg = <ef601500 8>;
+                                has-mdio;
+                        };
+
+                        RGMII1: emac-rgmii@ef601600 {
+                                compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+                                reg = <ef601600 8>;
+                                has-mdio;
+                        };
+
+                        TAH0: emac-tah@ef601350 {
+                                compatible = "ibm,tah-460gt", "ibm,tah";
+                                reg = <ef601350 30>;
+                        };
+
+                        TAH1: emac-tah@ef601450 {
+                                compatible = "ibm,tah-460gt", "ibm,tah";
+                                reg = <ef601450 30>;
+                        };
+
+                        EMAC0: ethernet@ef600e00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                interrupt-parent = <&EMAC0>;
+                                interrupts = <0 1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0 &UIC2 10 4
+                                                 /*Wake*/   1 &UIC2 14 4>;
+                                reg = <ef600e00 70>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0>;
+                                mal-rx-channel = <0>;
+                                cell-index = <0>;
+                                max-frame-size = <2328>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rgmii";
+                                phy-map = <00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <0>;
+                                tah-device = <&TAH0>;
+                                tah-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+
+                        EMAC1: ethernet@ef600f00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                interrupt-parent = <&EMAC1>;
+                                interrupts = <0 1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0 &UIC2 11 4
+                                                 /*Wake*/   1 &UIC2 15 4>;
+                                reg = <ef600f00 70>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <1>;
+                                mal-rx-channel = <8>;
+                                cell-index = <1>;
+                                max-frame-size = <2328>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rgmii";
+                                phy-map = <00000000>;
+                                rgmii-device = <&RGMII0>;
+                                rgmii-channel = <1>;
+                                tah-device = <&TAH1>;
+                                tah-channel = <1>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+
+                        EMAC2: ethernet@ef601100 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                interrupt-parent = <&EMAC2>;
+                                interrupts = <0 1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0 &UIC2 12 4
+                                                 /*Wake*/   1 &UIC2 16 4>;
+                                reg = <ef601100 70>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <2>;
+                                mal-rx-channel = <10>;
+                                cell-index = <2>;
+                                max-frame-size = <2328>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rgmii";
+                                phy-map = <00000000>;
+                                rgmii-device = <&RGMII1>;
+                                rgmii-channel = <0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+
+                        EMAC3: ethernet@ef601200 {
+                                device_type = "network";
+                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                interrupt-parent = <&EMAC3>;
+                                interrupts = <0 1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0 &UIC2 13 4
+                                                 /*Wake*/   1 &UIC2 17 4>;
+                                reg = <ef601200 70>;
+                                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <3>;
+                                mal-rx-channel = <18>;
+                                cell-index = <3>;
+                                max-frame-size = <2328>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rgmii";
+                                phy-map = <00000000>;
+                                rgmii-device = <&RGMII1>;
+                                rgmii-channel = <1>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                                mdio-device = <&EMAC0>;
+                        };
+                };
+
+                PCIX0: pci@c0ec00000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
+                        primary;
+                        large-inbound-windows;
+                        enable-msi-hole;
+                        reg = <c 0ec00000   8   /* Config space access */
+                               0 0 0            /* no IACK cycles */
+                               c 0ed00000   4   /* Special cycles */
+                               c 0ec80000 100   /* Internal registers */
+                               c 0ec80100  fc>; /* Internal messaging registers */
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed
+                         */
+                        ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
+                                  01000000 0 00000000 0000000c 08000000 0 00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                        /* This drives busses 0 to 0x3f */
+                        bus-range = <0 3f>;
+
+                        /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+                        interrupt-map-mask = <0000 0 0 0>;
+                        interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
+                };
+
+                PCIE0: pciex@d00000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+                        primary;
+                        port = <0>; /* port number */
+                        reg = <d 00000000 20000000      /* Config space access */
+                               c 08010000 00001000>;    /* Registers */
+                        dcr-reg = <100 020>;
+                        sdr-base = <300>;
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed
+                         */
+                        ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
+                                  01000000 0 00000000 0000000f 80000000 0 00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                        /* This drives busses 40 to 0x7f */
+                        bus-range = <40 7f>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0000 0 0 7>;
+                        interrupt-map = <
+                                0000 0 0 1 &UIC3 c 4 /* swizzled int A */
+                                0000 0 0 2 &UIC3 d 4 /* swizzled int B */
+                                0000 0 0 3 &UIC3 e 4 /* swizzled int C */
+                                0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
+                };
+
+                PCIE1: pciex@d20000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+                        primary;
+                        port = <1>; /* port number */
+                        reg = <d 20000000 20000000      /* Config space access */
+                               c 08011000 00001000>;    /* Registers */
+                        dcr-reg = <120 020>;
+                        sdr-base = <340>;
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed
+                         */
+                        ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
+                                  01000000 0 00000000 0000000f 80010000 0 00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                        /* This drives busses 80 to 0xbf */
+                        bus-range = <80 bf>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0000 0 0 7>;
+                        interrupt-map = <
+                                0000 0 0 1 &UIC3 10 4 /* swizzled int A */
+                                0000 0 0 2 &UIC3 11 4 /* swizzled int B */
+                                0000 0 0 3 &UIC3 12 4 /* swizzled int C */
+                                0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts
index ae68fefc01b6..b5d95ac24dbf 100644
--- a/arch/powerpc/boot/dts/haleakala.dts
+++ b/arch/powerpc/boot/dts/haleakala.dts
@@ -12,7 +12,7 @@
         #address-cells = <1>;
         #size-cells = <1>;
         model = "amcc,haleakala";
-        compatible = "amcc,kilauea";
+        compatible = "amcc,haleakala", "amcc,kilauea";
         dcr-parent = <&/cpus/cpu@0>;
 
         aliases {
@@ -218,7 +218,7 @@
                                 mal-tx-channel = <0>;
                                 mal-rx-channel = <0>;
                                 cell-index = <0>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index fc86e5a3afc4..cc2873a531d2 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -212,7 +212,7 @@
                                 mal-tx-channel = <0>;
                                 mal-rx-channel = <0>;
                                 cell-index = <0>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "gmii";
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 8baef61f31cd..48c9a6e71f1a 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -219,7 +219,7 @@
                                 mal-tx-channel = <0>;
                                 mal-rx-channel = <0>;
                                 cell-index = <0>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
@@ -247,7 +247,7 @@
                                 mal-tx-channel = <1>;
                                 mal-rx-channel = <1>;
                                 cell-index = <1>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
new file mode 100644
index 000000000000..f869ce3ca0b7
--- /dev/null
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -0,0 +1,267 @@
+/*
+ * Device Tree Source for Emerson KSI8560
+ *
+ * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
+ *
+ * Based on mpc8560ads.dts
+ *
+ * 2008 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+        model = "KSI8560";
+        compatible = "emerson,KSI8560";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8560@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <0x8000>;                /* L1, 32K */
+                        i-cache-size = <0x8000>;                /* L1, 32K */
+                        timebase-frequency = <0>;               /* From U-boot */
+                        bus-frequency = <0>;                    /* From U-boot */
+                        clock-frequency = <0>;                  /* From U-boot */
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;                  /* Fixed by bootwrapper */
+        };
+
+        soc@fdf00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                ranges = <0x00000000 0xfdf00000 0x00100000>;
+                bus-frequency = <0>;                            /* Fixed by bootwrapper */
+
+                memory-controller@2000 {
+                        compatible = "fsl,8540-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <0x12 0x2>;
+                };
+
+                l2-cache-controller@20000 {
+                        compatible = "fsl,8540-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <0x20>;               /* 32 bytes */
+                        cache-size = <0x40000>;                 /* L2, 256K */
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <0x10 0x2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <0x2b 0x2>;
+                        interrupt-parent = <&MPIC>;
+                        dfsrr;
+                };
+
+                mdio@24520 {                                    /* For TSECs */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-mdio";
+                        reg = <0x24520 0x20>;
+
+                        PHY1: ethernet-phy@1 {
+                                interrupt-parent = <&MPIC>;
+                                reg = <0x1>;
+                                device_type = "ethernet-phy";
+                        };
+
+                        PHY2: ethernet-phy@2 {
+                                interrupt-parent = <&MPIC>;
+                                reg = <0x2>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+
+                enet0: ethernet@24000 {
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        /* Mac address filled in by bootwrapper */
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
+                        interrupt-parent = <&MPIC>;
+                        phy-handle = <&PHY1>;
+                };
+
+                enet1: ethernet@25000 {
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        /* Mac address filled in by bootwrapper */
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
+                        interrupt-parent = <&MPIC>;
+                        phy-handle = <&PHY2>;
+                };
+
+                MPIC: pic@40000 {
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0x40000 0x40000>;
+                        device_type = "open-pic";
+                };
+
+                cpm@919c0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
+                        reg = <0x919c0 0x30>;
+                        ranges;
+
+                        muram@80000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x0 0x80000 0x10000>;
+
+                                data@0 {
+                                        compatible = "fsl,cpm-muram-data";
+                                        reg = <0x0 0x4000 0x9000 0x2000>;
+                                };
+                        };
+
+                        brg@919f0 {
+                                compatible = "fsl,mpc8560-brg",
+                                             "fsl,cpm2-brg",
+                                             "fsl,cpm-brg";
+                                reg = <0x919f0 0x10 0x915f0 0x10>;
+                                clock-frequency = <165000000>;  /* 166MHz */
+                        };
+
+                        CPMPIC: pic@90c00 {
+                                #address-cells = <0>;
+                                #interrupt-cells = <2>;
+                                interrupt-controller;
+                                interrupts = <0x2e 0x2>;
+                                interrupt-parent = <&MPIC>;
+                                reg = <0x90c00 0x80>;
+                                compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
+                        };
+
+                        serial@91a00 {
+                                device_type = "serial";
+                                compatible = "fsl,mpc8560-scc-uart",
+                                             "fsl,cpm2-scc-uart";
+                                reg = <0x91a00 0x20 0x88000 0x100>;
+                                fsl,cpm-brg = <1>;
+                                fsl,cpm-command = <0x800000>;
+                                current-speed = <0x1c200>;
+                                interrupts = <0x28 0x8>;
+                                interrupt-parent = <&CPMPIC>;
+                        };
+
+                        serial@91a20 {
+                                device_type = "serial";
+                                compatible = "fsl,mpc8560-scc-uart",
+                                             "fsl,cpm2-scc-uart";
+                                reg = <0x91a20 0x20 0x88100 0x100>;
+                                fsl,cpm-brg = <2>;
+                                fsl,cpm-command = <0x4a00000>;
+                                current-speed = <0x1c200>;
+                                interrupts = <0x29 0x8>;
+                                interrupt-parent = <&CPMPIC>;
+                        };
+
+                        mdio@90d00 {                            /* For FCCs */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,cpm2-mdio-bitbang";
+                                reg = <0x90d00 0x14>;
+                                fsl,mdio-pin = <24>;
+                                fsl,mdc-pin = <25>;
+
+                                PHY0: ethernet-phy@0 {
+                                        interrupt-parent = <&MPIC>;
+                                        reg = <0x0>;
+                                        device_type = "ethernet-phy";
+                                };
+                        };
+
+                        enet2: ethernet@91300 {
+                                device_type = "network";
+                                compatible = "fsl,mpc8560-fcc-enet",
+                                             "fsl,cpm2-fcc-enet";
+                                reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>;
+                                /* Mac address filled in by bootwrapper */
+                                local-mac-address = [ 00 00 00 00 00 00 ];
+                                fsl,cpm-command = <0x12000300>;
+                                interrupts = <0x20 0x8>;
+                                interrupt-parent = <&CPMPIC>;
+                                phy-handle = <&PHY0>;
+                        };
+                };
+        };
+
+        localbus@fdf05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8560-localbus";
+                reg = <0xfdf05000 0x68>;
+
+                ranges = <0x0 0x0 0xe0000000 0x00800000
+                          0x4 0x0 0xe8080000 0x00080000>;
+
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "jedec-flash";
+                        reg = <0x0 0x0 0x800000>;
+                        bank-width = <0x2>;
+
+                        partition@0 {
+                                label = "Primary Kernel";
+                                reg = <0x0 0x180000>;
+                        };
+                        partition@180000 {
+                                label = "Primary Filesystem";
+                                reg = <0x180000 0x580000>;
+                        };
+                        partition@700000 {
+                                label = "Monitor";
+                                reg = <0x300000 0x100000>;
+                                read-only;
+                        };
+                };
+
+                cpld@4,0 {
+                        compatible = "emerson,KSI8560-cpld";
+                        reg = <0x4 0x0 0x80000>;
+                };
+        };
+
+
+        chosen {
+                linux,stdout-path = "/soc/cpm/serial@91a00";
+        };
+};
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 446958854519..2e5a1a1812b6 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -7,6 +7,7 @@
  * Based on sandpoint.dts
  *
  * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright 2008 Freescale Semiconductor, Inc.
  *
  * This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
 
  */
 
+/dts-v1/;
+
 / {
         model = "KuroboxHD";
         compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
 
                 PowerPC,603e { /* Really 8241 */
                         device_type = "cpu";
-                        reg = <0>;
-                        clock-frequency = <bebc200>;    /* Fixed by bootloader */
-                        timebase-frequency = <1743000>; /* Fixed by bootloader */
+                        reg = <0x0>;
+                        clock-frequency = <200000000>;  /* Fixed by bootloader */
+                        timebase-frequency = <24391680>; /* Fixed by bootloader */
                         bus-frequency = <0>;            /* Fixed by bootloader */
                         /* Following required by dtc but not used */
-                        i-cache-size = <4000>;
-                        d-cache-size = <4000>;
+                        i-cache-size = <0x4000>;
+                        d-cache-size = <0x4000>;
                 };
         };
 
         memory {
                 device_type = "memory";
-                reg = <00000000 04000000>;
+                reg = <0x0 0x4000000>;
         };
 
         soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
                 device_type = "soc";
                 compatible = "mpc10x";
                 store-gathering = <0>; /* 0 == off, !0 == on */
-                reg = <80000000 00100000>;
-                ranges = <80000000 80000000 70000000    /* pci mem space */
-                          fc000000 fc000000 00100000    /* EUMB */
-                          fe000000 fe000000 00c00000    /* pci i/o space */
-                          fec00000 fec00000 00300000    /* pci cfg regs */
-                          fef00000 fef00000 00100000>;  /* pci iack */
+                reg = <0x80000000 0x100000>;
+                ranges = <0x80000000 0x80000000 0x70000000      /* pci mem space */
+                          0xfc000000 0xfc000000 0x100000        /* EUMB */
+                          0xfe000000 0xfe000000 0xc00000        /* pci i/o space */
+                          0xfec00000 0xfec00000 0x300000        /* pci cfg regs */
+                          0xfef00000 0xfef00000 0x100000>;      /* pci iack */
 
                 i2c@80003000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <80003000 1000>;
+                        reg = <0x80003000 0x1000>;
                         interrupts = <5 2>;
                         interrupt-parent = <&mpic>;
 
                         rtc@32 {
                                 device_type = "rtc";
                                 compatible = "ricoh,rs5c372a";
-                                reg = <32>;
+                                reg = <0x32>;
                         };
                 };
 
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <80004500 8>;
-                        clock-frequency = <5d08d88>;
-                        current-speed = <2580>;
+                        reg = <0x80004500 0x8>;
+                        clock-frequency = <97553800>;
+                        current-speed = <9600>;
                         interrupts = <9 0>;
                         interrupt-parent = <&mpic>;
                 };
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <80004600 8>;
-                        clock-frequency = <5d08d88>;
-                        current-speed = <e100>;
-                        interrupts = <a 0>;
+                        reg = <0x80004600 0x8>;
+                        clock-frequency = <97553800>;
+                        current-speed = <57600>;
+                        interrupts = <10 0>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
                         device_type = "open-pic";
                         compatible = "chrp,open-pic";
                         interrupt-controller;
-                        reg = <80040000 40000>;
+                        reg = <0x80040000 0x40000>;
                 };
 
                 pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
                         #interrupt-cells = <1>;
                         device_type = "pci";
                         compatible = "mpc10x-pci";
-                        reg = <fec00000 400000>;
-                        ranges = <01000000 0        0 fe000000 0 00c00000
-                                  02000000 0 80000000 80000000 0 70000000>;
-                        bus-range = <0 ff>;
-                        clock-frequency = <7f28155>;
+                        reg = <0xfec00000 0x400000>;
+                        ranges = <0x1000000 0x0        0x0 0xfe000000 0x0 0xc00000
+                                  0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
+                        bus-range = <0 255>;
+                        clock-frequency = <133333333>;
                         interrupt-parent = <&mpic>;
-                        interrupt-map-mask = <f800 0 0 7>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                         interrupt-map = <
                                 /* IDSEL 11 - IRQ0 ETH */
-                                5800 0 0 1 &mpic 0 1
-                                5800 0 0 2 &mpic 1 1
-                                5800 0 0 3 &mpic 2 1
-                                5800 0 0 4 &mpic 3 1
+                                0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
+                                0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
                                 /* IDSEL 12 - IRQ1 IDE0 */
-                                6000 0 0 1 &mpic 1 1
-                                6000 0 0 2 &mpic 2 1
-                                6000 0 0 3 &mpic 3 1
-                                6000 0 0 4 &mpic 0 1
+                                0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
                                 /* IDSEL 14 - IRQ3 USB2.0 */
-                                7000 0 0 1 &mpic 3 1
-                                7000 0 0 2 &mpic 3 1
-                                7000 0 0 3 &mpic 3 1
-                                7000 0 0 4 &mpic 3 1
+                                0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
+                                0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
                         >;
                 };
         };
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index 8443c85b7b30..e4916e69ad31 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -7,6 +7,7 @@
  * Based on sandpoint.dts
  *
  * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright 2008 Freescale Semiconductor, Inc.
  *
  * This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
 
  */
 
+/dts-v1/;
+
 / {
         model = "KuroboxHG";
         compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
 
                 PowerPC,603e { /* Really 8241 */
                         device_type = "cpu";
-                        reg = <0>;
-                        clock-frequency = <fdad680>;    /* Fixed by bootloader */
-                        timebase-frequency = <1F04000>; /* Fixed by bootloader */
+                        reg = <0x0>;
+                        clock-frequency = <266000000>;  /* Fixed by bootloader */
+                        timebase-frequency = <32522240>; /* Fixed by bootloader */
                         bus-frequency = <0>;            /* Fixed by bootloader */
                         /* Following required by dtc but not used */
-                        i-cache-size = <4000>;
-                        d-cache-size = <4000>;
+                        i-cache-size = <0x4000>;
+                        d-cache-size = <0x4000>;
                 };
         };
 
         memory {
                 device_type = "memory";
-                reg = <00000000 08000000>;
+                reg = <0x0 0x8000000>;
         };
 
         soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
                 device_type = "soc";
                 compatible = "mpc10x";
                 store-gathering = <0>; /* 0 == off, !0 == on */
-                reg = <80000000 00100000>;
-                ranges = <80000000 80000000 70000000    /* pci mem space */
-                          fc000000 fc000000 00100000    /* EUMB */
-                          fe000000 fe000000 00c00000    /* pci i/o space */
-                          fec00000 fec00000 00300000    /* pci cfg regs */
-                          fef00000 fef00000 00100000>;  /* pci iack */
+                reg = <0x80000000 0x100000>;
+                ranges = <0x80000000 0x80000000 0x70000000      /* pci mem space */
+                          0xfc000000 0xfc000000 0x100000        /* EUMB */
+                          0xfe000000 0xfe000000 0xc00000        /* pci i/o space */
+                          0xfec00000 0xfec00000 0x300000        /* pci cfg regs */
+                          0xfef00000 0xfef00000 0x100000>;      /* pci iack */
 
                 i2c@80003000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <80003000 1000>;
+                        reg = <0x80003000 0x1000>;
                         interrupts = <5 2>;
                         interrupt-parent = <&mpic>;
 
                         rtc@32 {
                                 device_type = "rtc";
                                 compatible = "ricoh,rs5c372a";
-                                reg = <32>;
+                                reg = <0x32>;
                         };
                 };
 
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <80004500 8>;
-                        clock-frequency = <7c044a8>;
-                        current-speed = <2580>;
+                        reg = <0x80004500 0x8>;
+                        clock-frequency = <130041000>;
+                        current-speed = <9600>;
                         interrupts = <9 0>;
                         interrupt-parent = <&mpic>;
                 };
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <80004600 8>;
-                        clock-frequency = <7c044a8>;
-                        current-speed = <e100>;
-                        interrupts = <a 0>;
+                        reg = <0x80004600 0x8>;
+                        clock-frequency = <130041000>;
+                        current-speed = <57600>;
+                        interrupts = <10 0>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
                         device_type = "open-pic";
                         compatible = "chrp,open-pic";
                         interrupt-controller;
-                        reg = <80040000 40000>;
+                        reg = <0x80040000 0x40000>;
                 };
 
                 pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
                         #interrupt-cells = <1>;
                         device_type = "pci";
                         compatible = "mpc10x-pci";
-                        reg = <fec00000 400000>;
-                        ranges = <01000000 0        0 fe000000 0 00c00000
-                                  02000000 0 80000000 80000000 0 70000000>;
-                        bus-range = <0 ff>;
-                        clock-frequency = <7f28155>;
+                        reg = <0xfec00000 0x400000>;
+                        ranges = <0x1000000 0x0        0x0 0xfe000000 0x0 0xc00000
+                                  0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
+                        bus-range = <0 255>;
+                        clock-frequency = <133333333>;
                         interrupt-parent = <&mpic>;
-                        interrupt-map-mask = <f800 0 0 7>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                         interrupt-map = <
                                 /* IDSEL 11 - IRQ0 ETH */
-                                5800 0 0 1 &mpic 0 1
-                                5800 0 0 2 &mpic 1 1
-                                5800 0 0 3 &mpic 2 1
-                                5800 0 0 4 &mpic 3 1
+                                0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
+                                0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
                                 /* IDSEL 12 - IRQ1 IDE0 */
-                                6000 0 0 1 &mpic 1 1
-                                6000 0 0 2 &mpic 2 1
-                                6000 0 0 3 &mpic 3 1
-                                6000 0 0 4 &mpic 0 1
+                                0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
                                 /* IDSEL 14 - IRQ3 USB2.0 */
-                                7000 0 0 1 &mpic 3 1
-                                7000 0 0 2 &mpic 3 1
-                                7000 0 0 3 &mpic 3 1
-                                7000 0 0 4 &mpic 3 1
+                                0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
+                                0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
                         >;
                 };
         };
diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts
index 710c01168179..84cc5e72ddd8 100644
--- a/arch/powerpc/boot/dts/makalu.dts
+++ b/arch/powerpc/boot/dts/makalu.dts
@@ -219,7 +219,7 @@
                                 mal-tx-channel = <0>;
                                 mal-rx-channel = <0>;
                                 cell-index = <0>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
@@ -247,7 +247,7 @@
                                 mal-tx-channel = <1>;
                                 mal-rx-channel = <1>;
                                 cell-index = <1>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index 8fb542387436..4936349b87cd 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -1,7 +1,7 @@
 /*
  * MPC7448HPC2 (Taiga) board Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  * 2006 Roy Zang <Roy Zang at freescale.com>.
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -10,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "mpc7448hpc2";
@@ -23,11 +24,11 @@
                                 
                 PowerPC,7448@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K bytes
-                        i-cache-size = <8000>;          // L1, 32K bytes
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K bytes
+                        i-cache-size = <0x8000>;                // L1, 32K bytes
                         timebase-frequency = <0>;       // 33 MHz, from uboot
                         clock-frequency = <0>;          // From U-Boot
                         bus-frequency = <0>;            // From U-Boot
@@ -36,7 +37,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 20000000        // DDR2   512M at 0
+                reg = <0x0 0x20000000   // DDR2   512M at 0
                        >;
         };
 
@@ -44,14 +45,14 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "tsi-bridge";
-                ranges = <00000000 c0000000 00010000>;
-                reg = <c0000000 00010000>;
+                ranges = <0x0 0xc0000000 0x10000>;
+                reg = <0xc0000000 0x10000>;
                 bus-frequency = <0>;
 
                 i2c@7000 {
                         interrupt-parent = <&mpic>;
-                        interrupts = <E 0>;
-                        reg = <7000 400>;
+                        interrupts = <14 0>;
+                        reg = <0x7000 0x400>;
                         device_type = "i2c";
                         compatible  = "tsi108-i2c";
                 };
@@ -59,20 +60,20 @@
                 MDIO: mdio@6000 {
                         device_type = "mdio";
                         compatible = "tsi108-mdio";
-                        reg = <6000 50>;
+                        reg = <0x6000 0x50>;
                         #address-cells = <1>;
                         #size-cells = <0>;
 
                         phy8: ethernet-phy@8 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1>;
-                                reg = <8>;
+                                reg = <0x8>;
                         };
 
                         phy9: ethernet-phy@9 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1>;
-                                reg = <9>;
+                                reg = <0x9>;
                         };
 
                 };
@@ -82,9 +83,9 @@
                         #size-cells = <0>;
                         device_type = "network";
                         compatible = "tsi108-ethernet";
-                        reg = <6000 200>;
+                        reg = <0x6000 0x200>;
                         address = [ 00 06 D2 00 00 01 ];
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                         interrupt-parent = <&mpic>;
                         mdio-handle = <&MDIO>;
                         phy-handle = <&phy8>;
@@ -96,9 +97,9 @@
                         #size-cells = <0>;
                         device_type = "network";
                         compatible = "tsi108-ethernet";
-                        reg = <6400 200>;
+                        reg = <0x6400 0x200>;
                         address = [ 00 06 D2 00 00 02 ];
-                        interrupts = <11 2>;
+                        interrupts = <17 2>;
                         interrupt-parent = <&mpic>;
                         mdio-handle = <&MDIO>;
                         phy-handle = <&phy9>;
@@ -107,18 +108,18 @@
                 serial@7808 {
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <7808 200>;
-                        clock-frequency = <3f6b5a00>;
-                        interrupts = <c 0>;
+                        reg = <0x7808 0x200>;
+                        clock-frequency = <1064000000>;
+                        interrupts = <12 0>;
                         interrupt-parent = <&mpic>;
                 };
 
                 serial@7c08 {
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <7c08 200>;
-                        clock-frequency = <3f6b5a00>;
-                        interrupts = <d 0>;
+                        reg = <0x7c08 0x200>;
+                        clock-frequency = <1064000000>;
+                        interrupts = <13 0>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -127,7 +128,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <7400 400>;
+                        reg = <0x7400 0x400>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
@@ -138,39 +139,39 @@
                         #interrupt-cells = <1>;
                         #size-cells = <2>;
                         #address-cells = <3>;
-                        reg = <1000 1000>;
+                        reg = <0x1000 0x1000>;
                         bus-range = <0 0>;
-                        ranges = <02000000 0 e0000000 e0000000 0 1A000000       
-                                  01000000 0 00000000 fa000000 0 00010000>;
-                        clock-frequency = <7f28154>;
+                        ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000    
+                                  0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
+                        clock-frequency = <133333332>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <17 2>;
-                        interrupt-map-mask = <f800 0 0 7>;
+                        interrupts = <23 2>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                         interrupt-map = <
 
                                 /* IDSEL 0x11 */
-                                0800 0 0 1 &RT0 24 0
-                                0800 0 0 2 &RT0 25 0
-                                0800 0 0 3 &RT0 26 0
-                                0800 0 0 4 &RT0 27 0
+                                0x800 0x0 0x0 0x1 &RT0 0x24 0x0
+                                0x800 0x0 0x0 0x2 &RT0 0x25 0x0
+                                0x800 0x0 0x0 0x3 &RT0 0x26 0x0
+                                0x800 0x0 0x0 0x4 &RT0 0x27 0x0
 
                                 /* IDSEL 0x12 */
-                                1000 0 0 1 &RT0 25 0
-                                1000 0 0 2 &RT0 26 0
-                                1000 0 0 3 &RT0 27 0
-                                1000 0 0 4 &RT0 24 0
+                                0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
+                                0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
+                                0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
+                                0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
 
                                 /* IDSEL 0x13 */
-                                1800 0 0 1 &RT0 26 0
-                                1800 0 0 2 &RT0 27 0
-                                1800 0 0 3 &RT0 24 0
-                                1800 0 0 4 &RT0 25 0
+                                0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
+                                0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
+                                0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
+                                0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
 
                                 /* IDSEL 0x14 */
-                                2000 0 0 1 &RT0 27 0
-                                2000 0 0 2 &RT0 24 0
-                                2000 0 0 3 &RT0 25 0
-                                2000 0 0 4 &RT0 26 0
+                                0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
+                                0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
+                                0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
+                                0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
                                 >;
 
                         RT0: router@1180 {
@@ -180,7 +181,7 @@
                                 #address-cells = <0>;
                                 #interrupt-cells = <2>;
                                 big-endian;
-                                interrupts = <17 2>;
+                                interrupts = <23 2>;
                                 interrupt-parent = <&mpic>;
                         };
                 };
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 7285ca1325fd..46e2da30c3dd 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8272 ADS Device Tree Source
  *
- * Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005,2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,8 @@
  * option) any later version.
  */
 
+/dts-v1/;
+
 / {
         model = "MPC8272ADS";
         compatible = "fsl,mpc8272ads";
@@ -21,11 +23,11 @@
 
                 PowerPC,8272@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <d#32>;
-                        i-cache-line-size = <d#32>;
-                        d-cache-size = <d#16384>;
-                        i-cache-size = <d#16384>;
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <16384>;
+                        i-cache-size = <16384>;
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
@@ -34,7 +36,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0 0>;
+                reg = <0x0 0x0>;
         };
 
         localbus@f0010100 {
@@ -42,21 +44,21 @@
                              "fsl,pq2-localbus";
                 #address-cells = <2>;
                 #size-cells = <1>;
-                reg = <f0010100 40>;
+                reg = <0xf0010100 0x40>;
 
-                ranges = <0 0 fe000000 02000000
-                          1 0 f4500000 00008000
-                          3 0 f8200000 00008000>;
+                ranges = <0x0 0x0 0xfe000000 0x2000000
+                          0x1 0x0 0xf4500000 0x8000
+                          0x3 0x0 0xf8200000 0x8000>;
 
                 flash@0,0 {
                         compatible = "jedec-flash";
-                        reg = <0 0 2000000>;
+                        reg = <0x0 0x0 0x2000000>;
                         bank-width = <4>;
                         device-width = <1>;
                 };
 
                 board-control@1,0 {
-                        reg = <1 0 20>;
+                        reg = <0x1 0x0 0x20>;
                         compatible = "fsl,mpc8272ads-bcsr";
                 };
 
@@ -65,46 +67,46 @@
                                      "fsl,pq2ads-pci-pic";
                         #interrupt-cells = <1>;
                         interrupt-controller;
-                        reg = <3 0 8>;
+                        reg = <0x3 0x0 0x8>;
                         interrupt-parent = <&PIC>;
-                        interrupts = <14 8>;
+                        interrupts = <20 8>;
                 };
         };
 
 
         pci@f0010800 {
                 device_type = "pci";
-                reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+                reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
                 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                clock-frequency = <d#66666666>;
-                interrupt-map-mask = <f800 0 0 7>;
+                clock-frequency = <66666666>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                                  /* IDSEL 0x16 */
-                                 b000 0 0 1 &PCI_PIC 0
-                                 b000 0 0 2 &PCI_PIC 1
-                                 b000 0 0 3 &PCI_PIC 2
-                                 b000 0 0 4 &PCI_PIC 3
+                                 0xb000 0x0 0x0 0x1 &PCI_PIC 0
+                                 0xb000 0x0 0x0 0x2 &PCI_PIC 1
+                                 0xb000 0x0 0x0 0x3 &PCI_PIC 2
+                                 0xb000 0x0 0x0 0x4 &PCI_PIC 3
 
                                  /* IDSEL 0x17 */
-                                 b800 0 0 1 &PCI_PIC 4
-                                 b800 0 0 2 &PCI_PIC 5
-                                 b800 0 0 3 &PCI_PIC 6
-                                 b800 0 0 4 &PCI_PIC 7
+                                 0xb800 0x0 0x0 0x1 &PCI_PIC 4
+                                 0xb800 0x0 0x0 0x2 &PCI_PIC 5
+                                 0xb800 0x0 0x0 0x3 &PCI_PIC 6
+                                 0xb800 0x0 0x0 0x4 &PCI_PIC 7
 
                                  /* IDSEL 0x18 */
-                                 c000 0 0 1 &PCI_PIC 8
-                                 c000 0 0 2 &PCI_PIC 9
-                                 c000 0 0 3 &PCI_PIC a
-                                 c000 0 0 4 &PCI_PIC b>;
+                                 0xc000 0x0 0x0 0x1 &PCI_PIC 8
+                                 0xc000 0x0 0x0 0x2 &PCI_PIC 9
+                                 0xc000 0x0 0x0 0x3 &PCI_PIC 10
+                                 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
 
                 interrupt-parent = <&PIC>;
-                interrupts = <12 8>;
-                ranges = <42000000 0 80000000 80000000 0 20000000
-                          02000000 0 a0000000 a0000000 0 20000000
-                          01000000 0 00000000 f6000000 0 02000000>;
+                interrupts = <18 8>;
+                ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
         };
 
         soc@f0000000 {
@@ -112,26 +114,26 @@
                 #size-cells = <1>;
                 device_type = "soc";
                 compatible = "fsl,mpc8272", "fsl,pq2-soc";
-                ranges = <00000000 f0000000 00053000>;
+                ranges = <0x0 0xf0000000 0x53000>;
 
                 // Temporary -- will go away once kernel uses ranges for get_immrbase().
-                reg = <f0000000 00053000>;
+                reg = <0xf0000000 0x53000>;
 
                 cpm@119c0 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
-                        reg = <119c0 30>;
+                        reg = <0x119c0 0x30>;
                         ranges;
 
                         muram@0 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 0 10000>;
+                                ranges = <0x0 0x0 0x10000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 2000 9800 800>;
+                                        reg = <0x0 0x2000 0x9800 0x800>;
                                 };
                         };
 
@@ -139,29 +141,29 @@
                                 compatible = "fsl,mpc8272-brg",
                                              "fsl,cpm2-brg",
                                              "fsl,cpm-brg";
-                                reg = <119f0 10 115f0 10>;
+                                reg = <0x119f0 0x10 0x115f0 0x10>;
                         };
 
                         serial@11a00 {
                                 device_type = "serial";
                                 compatible = "fsl,mpc8272-scc-uart",
                                              "fsl,cpm2-scc-uart";
-                                reg = <11a00 20 8000 100>;
-                                interrupts = <28 8>;
+                                reg = <0x11a00 0x20 0x8000 0x100>;
+                                interrupts = <40 8>;
                                 interrupt-parent = <&PIC>;
                                 fsl,cpm-brg = <1>;
-                                fsl,cpm-command = <00800000>;
+                                fsl,cpm-command = <0x800000>;
                         };
 
                         serial@11a60 {
                                 device_type = "serial";
                                 compatible = "fsl,mpc8272-scc-uart",
                                              "fsl,cpm2-scc-uart";
-                                reg = <11a60 20 8300 100>;
-                                interrupts = <2b 8>;
+                                reg = <0x11a60 0x20 0x8300 0x100>;
+                                interrupts = <43 8>;
                                 interrupt-parent = <&PIC>;
                                 fsl,cpm-brg = <4>;
-                                fsl,cpm-command = <0ce00000>;
+                                fsl,cpm-command = <0xce00000>;
                         };
 
                         mdio@10d40 {
@@ -169,23 +171,23 @@
                                 compatible = "fsl,mpc8272ads-mdio-bitbang",
                                              "fsl,mpc8272-mdio-bitbang",
                                              "fsl,cpm2-mdio-bitbang";
-                                reg = <10d40 14>;
+                                reg = <0x10d40 0x14>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                fsl,mdio-pin = <12>;
-                                fsl,mdc-pin = <13>;
+                                fsl,mdio-pin = <18>;
+                                fsl,mdc-pin = <19>;
 
                                 PHY0: ethernet-phy@0 {
                                         interrupt-parent = <&PIC>;
-                                        interrupts = <17 8>;
-                                        reg = <0>;
+                                        interrupts = <23 8>;
+                                        reg = <0x0>;
                                         device_type = "ethernet-phy";
                                 };
 
                                 PHY1: ethernet-phy@1 {
                                         interrupt-parent = <&PIC>;
-                                        interrupts = <17 8>;
-                                        reg = <3>;
+                                        interrupts = <23 8>;
+                                        reg = <0x3>;
                                         device_type = "ethernet-phy";
                                 };
                         };
@@ -194,33 +196,33 @@
                                 device_type = "network";
                                 compatible = "fsl,mpc8272-fcc-enet",
                                              "fsl,cpm2-fcc-enet";
-                                reg = <11300 20 8400 100 11390 1>;
+                                reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
-                                interrupts = <20 8>;
+                                interrupts = <32 8>;
                                 interrupt-parent = <&PIC>;
                                 phy-handle = <&PHY0>;
                                 linux,network-index = <0>;
-                                fsl,cpm-command = <12000300>;
+                                fsl,cpm-command = <0x12000300>;
                         };
 
                         ethernet@11320 {
                                 device_type = "network";
                                 compatible = "fsl,mpc8272-fcc-enet",
                                              "fsl,cpm2-fcc-enet";
-                                reg = <11320 20 8500 100 113b0 1>;
+                                reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
-                                interrupts = <21 8>;
+                                interrupts = <33 8>;
                                 interrupt-parent = <&PIC>;
                                 phy-handle = <&PHY1>;
                                 linux,network-index = <1>;
-                                fsl,cpm-command = <16200300>;
+                                fsl,cpm-command = <0x16200300>;
                         };
                 };
 
                 PIC: interrupt-controller@10c00 {
                         #interrupt-cells = <2>;
                         interrupt-controller;
-                        reg = <10c00 80>;
+                        reg = <0x10c00 0x80>;
                         compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
                 };
 
@@ -232,14 +234,14 @@
                                      "fsl,talitos-sec2",
                                      "fsl,talitos",
                                      "talitos";
-                        reg = <30000 10000>;
-                        interrupts = <b 8>;
+                        reg = <0x30000 0x10000>;
+                        interrupts = <11 8>;
                         interrupt-parent = <&PIC>;
                         num-channels = <4>;
-                        channel-fifo-len = <18>;
-                        exec-units-mask = <0000007e>;
+                        channel-fifo-len = <24>;
+                        exec-units-mask = <0x7e>;
 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
-                        descriptor-types-mask = <01010ebf>;
+                        descriptor-types-mask = <0x1010ebf>;
                 };
         };
 
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 9bb408371bcd..539e02fb3526 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -255,9 +255,7 @@
                 enet0: ucc@2200 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <3>;
-                        device-id = <3>;
                         reg = <0x2200 0x200>;
                         interrupts = <34>;
                         interrupt-parent = <&qeic>;
@@ -271,9 +269,7 @@
                 enet1: ucc@3200 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <4>;
-                        device-id = <4>;
                         reg = <0x3200 0x200>;
                         interrupts = <35>;
                         interrupt-parent = <&qeic>;
@@ -287,8 +283,7 @@
                 ucc@2400 {
                         device_type = "serial";
                         compatible = "ucc_uart";
-                        model = "UCC";
-                        device-id = <5>;        /* The UCC number, 1-7*/
+                        cell-index = <5>;       /* The UCC number, 1-7*/
                         port-number = <0>;      /* Which ttyQEx device */
                         soft-uart;              /* We need Soft-UART */
                         reg = <0x2400 0x200>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 94f93d209de8..179c81c6a7ac 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -208,9 +208,7 @@
                 enet0: ucc@3000 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <2>;
-                        device-id = <2>;
                         reg = <0x3000 0x200>;
                         interrupts = <33>;
                         interrupt-parent = <&qeic>;
@@ -224,9 +222,7 @@
                 enet1: ucc@2200 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <3>;
-                        device-id = <3>;
                         reg = <0x2200 0x200>;
                         interrupts = <34>;
                         interrupt-parent = <&qeic>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 55f03e8dc97f..8160ff24e87e 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -257,9 +257,7 @@
                 enet0: ucc@2000 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <1>;
-                        device-id = <1>;
                         reg = <0x2000 0x200>;
                         interrupts = <32>;
                         interrupt-parent = <&qeic>;
@@ -274,9 +272,7 @@
                 enet1: ucc@3000 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <2>;
-                        device-id = <2>;
                         reg = <0x3000 0x200>;
                         interrupts = <33>;
                         interrupt-parent = <&qeic>;
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 975248491b7b..18033ed0b535 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8540 ADS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "MPC8540ADS";
@@ -31,11 +32,11 @@
 
                 PowerPC,8540@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;       //  33 MHz, from uboot
                         bus-frequency = <0>;    // 166 MHz
                         clock-frequency = <0>;  // 825 MHz, from uboot
@@ -44,31 +45,31 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 08000000>;      // 128M at 0x0
+                reg = <0x0 0x8000000>;  // 128M at 0x0
         };
 
         soc8540@e0000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 e0000000 00100000>;
-                reg = <e0000000 00100000>;      // CCSRBAR 1M
+                ranges = <0x0 0xe0000000 0x100000>;
+                reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
                 bus-frequency = <0>;
 
                 memory-controller@2000 {
                         compatible = "fsl,8540-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,8540-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <40000>;   // L2, 256K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 i2c@3000 {
@@ -76,8 +77,8 @@
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <3000 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -86,24 +87,24 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@0 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <0>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                         phy3: ethernet-phy@3 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <7 1>;
-                                reg = <3>;
+                                reg = <0x3>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -113,9 +114,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy0>;
                 };
@@ -125,9 +126,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <25000 1000>;
+                        reg = <0x25000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <23 2 24 2 28 2>;
+                        interrupts = <35 2 36 2 40 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy1>;
                 };
@@ -137,9 +138,9 @@
                         device_type = "network";
                         model = "FEC";
                         compatible = "gianfar";
-                        reg = <26000 1000>;
+                        reg = <0x26000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <29 2>;
+                        interrupts = <41 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy3>;
                 };
@@ -148,9 +149,9 @@
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4500 100>;       // reg base, size
+                        reg = <0x4500 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -158,9 +159,9 @@
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4600 100>;       // reg base, size
+                        reg = <0x4600 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
                 mpic: pic@40000 {
@@ -168,7 +169,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
@@ -177,90 +178,90 @@
 
         pci0: pci@e0008000 {
                 cell-index = <0>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x02 */
-                        1000 0 0 1 &mpic 1 1
-                        1000 0 0 2 &mpic 2 1
-                        1000 0 0 3 &mpic 3 1
-                        1000 0 0 4 &mpic 4 1
+                        0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                         /* IDSEL 0x03 */
-                        1800 0 0 1 &mpic 4 1
-                        1800 0 0 2 &mpic 1 1
-                        1800 0 0 3 &mpic 2 1
-                        1800 0 0 4 &mpic 3 1
+                        0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+                        0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x04 */
-                        2000 0 0 1 &mpic 3 1
-                        2000 0 0 2 &mpic 4 1
-                        2000 0 0 3 &mpic 1 1
-                        2000 0 0 4 &mpic 2 1
+                        0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x05 */
-                        2800 0 0 1 &mpic 2 1
-                        2800 0 0 2 &mpic 3 1
-                        2800 0 0 3 &mpic 4 1
-                        2800 0 0 4 &mpic 1 1
+                        0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x0c */
-                        6000 0 0 1 &mpic 1 1
-                        6000 0 0 2 &mpic 2 1
-                        6000 0 0 3 &mpic 3 1
-                        6000 0 0 4 &mpic 4 1
+                        0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                         /* IDSEL 0x0d */
-                        6800 0 0 1 &mpic 4 1
-                        6800 0 0 2 &mpic 1 1
-                        6800 0 0 3 &mpic 2 1
-                        6800 0 0 4 &mpic 3 1
+                        0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+                        0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x0e */
-                        7000 0 0 1 &mpic 3 1
-                        7000 0 0 2 &mpic 4 1
-                        7000 0 0 3 &mpic 1 1
-                        7000 0 0 4 &mpic 2 1
+                        0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x0f */
-                        7800 0 0 1 &mpic 2 1
-                        7800 0 0 2 &mpic 3 1
-                        7800 0 0 3 &mpic 4 1
-                        7800 0 0 4 &mpic 1 1
+                        0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x12 */
-                        9000 0 0 1 &mpic 1 1
-                        9000 0 0 2 &mpic 2 1
-                        9000 0 0 3 &mpic 3 1
-                        9000 0 0 4 &mpic 4 1
+                        0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                         /* IDSEL 0x13 */
-                        9800 0 0 1 &mpic 4 1
-                        9800 0 0 2 &mpic 1 1
-                        9800 0 0 3 &mpic 2 1
-                        9800 0 0 4 &mpic 3 1
+                        0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+                        0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x14 */
-                        a000 0 0 1 &mpic 3 1
-                        a000 0 0 2 &mpic 4 1
-                        a000 0 0 3 &mpic 1 1
-                        a000 0 0 4 &mpic 2 1
+                        0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x15 */
-                        a800 0 0 1 &mpic 2 1
-                        a800 0 0 2 &mpic 3 1
-                        a800 0 0 3 &mpic 4 1
-                        a800 0 0 4 &mpic 1 1>;
+                        0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
+                interrupts = <24 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 80000000 80000000 0 20000000
-                          01000000 0 00000000 e2000000 0 00100000>;
-                clock-frequency = <3f940aa>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0008000 1000>;
+                reg = <0xe0008000 0x1000>;
                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
                 device_type = "pci";
         };
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fa8d9aaad157..663c7c50ca45 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8541 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "MPC8541CDS";
@@ -31,11 +32,11 @@
 
                 PowerPC,8541@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;       //  33 MHz, from uboot
                         bus-frequency = <0>;    // 166 MHz
                         clock-frequency = <0>;  // 825 MHz, from uboot
@@ -44,31 +45,31 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 08000000>;      // 128M at 0x0
+                reg = <0x0 0x8000000>;  // 128M at 0x0
         };
 
         soc8541@e0000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 e0000000 00100000>;
-                reg = <e0000000 00001000>;      // CCSRBAR 1M
+                ranges = <0x0 0xe0000000 0x100000>;
+                reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                 bus-frequency = <0>;
 
                 memory-controller@2000 {
                         compatible = "fsl,8541-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,8541-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <40000>;   // L2, 256K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 i2c@3000 {
@@ -76,8 +77,8 @@
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <3000 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -86,18 +87,18 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@0 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <0>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -107,9 +108,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy0>;
                 };
@@ -119,9 +120,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <25000 1000>;
+                        reg = <0x25000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <23 2 24 2 28 2>;
+                        interrupts = <35 2 36 2 40 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy1>;
                 };
@@ -130,9 +131,9 @@
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4500 100>;       // reg base, size
+                        reg = <0x4500 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -140,9 +141,9 @@
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4600 100>;       // reg base, size
+                        reg = <0x4600 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -151,7 +152,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
@@ -161,17 +162,17 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
-                        reg = <919c0 30>;
+                        reg = <0x919c0 0x30>;
                         ranges;
 
                         muram@80000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 80000 10000>;
+                                ranges = <0x0 0x80000 0x10000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 2000 9000 1000>;
+                                        reg = <0x0 0x2000 0x9000 0x1000>;
                                 };
                         };
 
@@ -179,16 +180,16 @@
                                 compatible = "fsl,mpc8541-brg",
                                              "fsl,cpm2-brg",
                                              "fsl,cpm-brg";
-                                reg = <919f0 10 915f0 10>;
+                                reg = <0x919f0 0x10 0x915f0 0x10>;
                         };
 
                         cpmpic: pic@90c00 {
                                 interrupt-controller;
                                 #address-cells = <0>;
                                 #interrupt-cells = <2>;
-                                interrupts = <2e 2>;
+                                interrupts = <46 2>;
                                 interrupt-parent = <&mpic>;
-                                reg = <90c00 80>;
+                                reg = <0x90c00 0x80>;
                                 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
                         };
                 };
@@ -196,68 +197,68 @@
 
         pci0: pci@e0008000 {
                 cell-index = <0>;
-                interrupt-map-mask = <1f800 0 0 7>;
+                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x10 */
-                        08000 0 0 1 &mpic 0 1
-                        08000 0 0 2 &mpic 1 1
-                        08000 0 0 3 &mpic 2 1
-                        08000 0 0 4 &mpic 3 1
+                        0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x11 */
-                        08800 0 0 1 &mpic 0 1
-                        08800 0 0 2 &mpic 1 1
-                        08800 0 0 3 &mpic 2 1
-                        08800 0 0 4 &mpic 3 1
+                        0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x12 (Slot 1) */
-                        09000 0 0 1 &mpic 0 1
-                        09000 0 0 2 &mpic 1 1
-                        09000 0 0 3 &mpic 2 1
-                        09000 0 0 4 &mpic 3 1
+                        0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x13 (Slot 2) */
-                        09800 0 0 1 &mpic 1 1
-                        09800 0 0 2 &mpic 2 1
-                        09800 0 0 3 &mpic 3 1
-                        09800 0 0 4 &mpic 0 1
+                        0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                         /* IDSEL 0x14 (Slot 3) */
-                        0a000 0 0 1 &mpic 2 1
-                        0a000 0 0 2 &mpic 3 1
-                        0a000 0 0 3 &mpic 0 1
-                        0a000 0 0 4 &mpic 1 1
+                        0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x15 (Slot 4) */
-                        0a800 0 0 1 &mpic 3 1
-                        0a800 0 0 2 &mpic 0 1
-                        0a800 0 0 3 &mpic 1 1
-                        0a800 0 0 4 &mpic 2 1
+                        0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* Bus 1 (Tundra Bridge) */
                         /* IDSEL 0x12 (ISA bridge) */
-                        19000 0 0 1 &mpic 0 1
-                        19000 0 0 2 &mpic 1 1
-                        19000 0 0 3 &mpic 2 1
-                        19000 0 0 4 &mpic 3 1>;
+                        0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
+                interrupts = <24 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 80000000 80000000 0 20000000
-                          01000000 0 00000000 e2000000 0 00100000>;
-                clock-frequency = <3f940aa>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0008000 1000>;
+                reg = <0xe0008000 0x1000>;
                 compatible = "fsl,mpc8540-pci";
                 device_type = "pci";
 
                 i8259@19000 {
                         interrupt-controller;
                         device_type = "interrupt-controller";
-                        reg = <19000 0 0 0 1>;
+                        reg = <0x19000 0x0 0x0 0x0 0x1>;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
                         compatible = "chrp,iic";
@@ -268,24 +269,24 @@
 
         pci1: pci@e0009000 {
                 cell-index = <1>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x15 */
-                        a800 0 0 1 &mpic b 1
-                        a800 0 0 2 &mpic b 1
-                        a800 0 0 3 &mpic b 1
-                        a800 0 0 4 &mpic b 1>;
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
                 interrupt-parent = <&mpic>;
-                interrupts = <19 2>;
+                interrupts = <25 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 a0000000 a0000000 0 20000000
-                          01000000 0 00000000 e3000000 0 00100000>;
-                clock-frequency = <3f940aa>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0009000 1000>;
+                reg = <0xe0009000 0x1000>;
                 compatible = "fsl,mpc8540-pci";
                 device_type = "pci";
         };
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 688af9d06382..6a0d8db96d97 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8544 DS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 / {
         model = "MPC8544DS";
         compatible = "MPC8544DS", "MPC85xxDS";
@@ -27,17 +28,16 @@
         };
 
         cpus {
-                #cpus = <1>;
                 #address-cells = <1>;
                 #size-cells = <0>;
 
                 PowerPC,8544@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
@@ -46,7 +46,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 00000000>;      // Filled by U-Boot
+                reg = <0x0 0x0>;        // Filled by U-Boot
         };
 
         soc8544@e0000000 {
@@ -54,24 +54,24 @@
                 #size-cells = <1>;
                 device_type = "soc";
 
-                ranges = <00000000 e0000000 00100000>;
-                reg = <e0000000 00001000>;      // CCSRBAR 1M
+                ranges = <0x0 0xe0000000 0x100000>;
+                reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                 bus-frequency = <0>;            // Filled out by uboot.
 
                 memory-controller@2000 {
                         compatible = "fsl,8544-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,8544-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <40000>;   // L2, 256K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 i2c@3000 {
@@ -79,8 +79,8 @@
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <3000 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -90,8 +90,8 @@
                         #size-cells = <0>;
                         cell-index = <1>;
                         compatible = "fsl-i2c";
-                        reg = <3100 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -100,30 +100,71 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@0 {
                                 interrupt-parent = <&mpic>;
-                                interrupts = <a 1>;
-                                reg = <0>;
+                                interrupts = <10 1>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
-                                interrupts = <a 1>;
-                                reg = <1>;
+                                interrupts = <10 1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                 };
 
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8544-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8544-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8544-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8544-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
                 enet0: ethernet@24000 {
                         cell-index = <0>;
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy0>;
                         phy-connection-type = "rgmii-id";
@@ -134,9 +175,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <26000 1000>;
+                        reg = <0x26000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1f 2 20 2 21 2>;
+                        interrupts = <31 2 32 2 33 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy1>;
                         phy-connection-type = "rgmii-id";
@@ -146,9 +187,9 @@
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4500 100>;
+                        reg = <0x4500 0x100>;
                         clock-frequency = <0>;
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -156,15 +197,15 @@
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4600 100>;
+                        reg = <0x4600 0x100>;
                         clock-frequency = <0>;
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
                 global-utilities@e0000 {        //global utilities block
                         compatible = "fsl,mpc8548-guts";
-                        reg = <e0000 1000>;
+                        reg = <0xe0000 0x1000>;
                         fsl,has-rstcr;
                 };
 
@@ -173,7 +214,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
@@ -184,32 +225,32 @@
                 cell-index = <0>;
                 compatible = "fsl,mpc8540-pci";
                 device_type = "pci";
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x11 J17 Slot 1 */
-                        8800 0 0 1 &mpic 2 1
-                        8800 0 0 2 &mpic 3 1
-                        8800 0 0 3 &mpic 4 1
-                        8800 0 0 4 &mpic 1 1
+                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x12 J16 Slot 2 */
 
-                        9000 0 0 1 &mpic 3 1
-                        9000 0 0 2 &mpic 4 1
-                        9000 0 0 3 &mpic 2 1
-                        9000 0 0 4 &mpic 1 1>;
+                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 c0000000 c0000000 0 20000000
-                          01000000 0 00000000 e1000000 0 00010000>;
-                clock-frequency = <3f940aa>;
+                interrupts = <24 2>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0008000 1000>;
+                reg = <0xe0008000 0x1000>;
         };
 
         pci1: pcie@e0009000 {
@@ -219,33 +260,33 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0009000 1000>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 80000000 80000000 0 20000000
-                          01000000 0 00000000 e1010000 0 00010000>;
-                clock-frequency = <1fca055>;
+                reg = <0xe0009000 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
+                clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <1a 2>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupts = <26 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 4 1
-                        0000 0 0 2 &mpic 5 1
-                        0000 0 0 3 &mpic 6 1
-                        0000 0 0 4 &mpic 7 1
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
                         >;
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 80000000
-                                  02000000 0 80000000
-                                  0 20000000
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00010000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
                 };
         };
 
@@ -256,33 +297,33 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e000a000 1000>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 a0000000 a0000000 0 10000000
-                          01000000 0 00000000 e1020000 0 00010000>;
-                clock-frequency = <1fca055>;
+                reg = <0xe000a000 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+                          0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
+                clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <19 2>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupts = <25 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 0 1
-                        0000 0 0 2 &mpic 1 1
-                        0000 0 0 3 &mpic 2 1
-                        0000 0 0 4 &mpic 3 1
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
                         >;
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 a0000000
-                                  02000000 0 a0000000
-                                  0 10000000
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x10000000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00010000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
                 };
         };
 
@@ -293,72 +334,72 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e000b000 1000>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 b0000000 b0000000 0 00100000
-                          01000000 0 00000000 b0100000 0 00100000>;
-                clock-frequency = <1fca055>;
+                reg = <0xe000b000 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
+                          0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
+                clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <1b 2>;
-                interrupt-map-mask = <ff00 0 0 1>;
+                interrupts = <27 2>;
+                interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
                 interrupt-map = <
                         // IDSEL 0x1c  USB
-                        e000 0 0 1 &i8259 c 2
-                        e100 0 0 2 &i8259 9 2
-                        e200 0 0 3 &i8259 a 2
-                        e300 0 0 4 &i8259 b 2
+                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 
                         // IDSEL 0x1d  Audio
-                        e800 0 0 1 &i8259 6 2
+                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 
                         // IDSEL 0x1e Legacy
-                        f000 0 0 1 &i8259 7 2
-                        f100 0 0 1 &i8259 7 2
+                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 
                         // IDSEL 0x1f IDE/SATA
-                        f800 0 0 1 &i8259 e 2
-                        f900 0 0 1 &i8259 5 2
+                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
                 >;
 
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 b0000000
-                                  02000000 0 b0000000
-                                  0 00100000
+                        ranges = <0x2000000 0x0 0xb0000000
+                                  0x2000000 0x0 0xb0000000
+                                  0x0 0x100000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00100000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
 
                         uli1575@0 {
-                                reg = <0 0 0 0 0>;
+                                reg = <0x0 0x0 0x0 0x0 0x0>;
                                 #size-cells = <2>;
                                 #address-cells = <3>;
-                                ranges = <02000000 0 b0000000
-                                          02000000 0 b0000000
-                                          0 00100000
+                                ranges = <0x2000000 0x0 0xb0000000
+                                          0x2000000 0x0 0xb0000000
+                                          0x0 0x100000
 
-                                          01000000 0 00000000
-                                          01000000 0 00000000
-                                          0 00100000>;
+                                          0x1000000 0x0 0x0
+                                          0x1000000 0x0 0x0
+                                          0x0 0x100000>;
                                 isa@1e {
                                         device_type = "isa";
                                         #interrupt-cells = <2>;
                                         #size-cells = <1>;
                                         #address-cells = <2>;
-                                        reg = <f000 0 0 0 0>;
-                                        ranges = <1 0
-                                                  01000000 0 0
-                                                  00001000>;
+                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                        ranges = <0x1 0x0
+                                                  0x1000000 0x0 0x0
+                                                  0x1000>;
                                         interrupt-parent = <&i8259>;
 
                                         i8259: interrupt-controller@20 {
-                                                reg = <1 20 2
-                                                       1 a0 2
-                                                       1 4d0 2>;
+                                                reg = <0x1 0x20 0x2
+                                                       0x1 0xa0 0x2
+                                                       0x1 0x4d0 0x2>;
                                                 interrupt-controller;
                                                 device_type = "interrupt-controller";
                                                 #address-cells = <0>;
@@ -371,28 +412,28 @@
                                         i8042@60 {
                                                 #size-cells = <0>;
                                                 #address-cells = <1>;
-                                                reg = <1 60 1 1 64 1>;
-                                                interrupts = <1 3 c 3>;
+                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                                interrupts = <1 3 12 3>;
                                                 interrupt-parent = <&i8259>;
 
                                                 keyboard@0 {
-                                                        reg = <0>;
+                                                        reg = <0x0>;
                                                         compatible = "pnpPNP,303";
                                                 };
 
                                                 mouse@1 {
-                                                        reg = <1>;
+                                                        reg = <0x1>;
                                                         compatible = "pnpPNP,f03";
                                                 };
                                         };
 
                                         rtc@70 {
                                                 compatible = "pnpPNP,b00";
-                                                reg = <1 70 2>;
+                                                reg = <0x1 0x70 0x2>;
                                         };
 
                                         gpio@400 {
-                                                reg = <1 400 80>;
+                                                reg = <0x1 0x400 0x80>;
                                         };
                                 };
                         };
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 1f470c6a1c63..fa298a8c81cc 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8548 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "MPC8548CDS";
@@ -36,11 +37,11 @@
 
                 PowerPC,8548@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;       //  33 MHz, from uboot
                         bus-frequency = <0>;    // 166 MHz
                         clock-frequency = <0>;  // 825 MHz, from uboot
@@ -49,31 +50,31 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 08000000>;      // 128M at 0x0
+                reg = <0x0 0x8000000>;  // 128M at 0x0
         };
 
         soc8548@e0000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <00000000 e0000000 00100000>;
-                reg = <e0000000 00001000>;      // CCSRBAR
+                ranges = <0x0 0xe0000000 0x100000>;
+                reg = <0xe0000000 0x1000>;      // CCSRBAR
                 bus-frequency = <0>;
 
                 memory-controller@2000 {
                         compatible = "fsl,8548-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,8548-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <80000>;   // L2, 512K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2, 512K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 i2c@3000 {
@@ -81,8 +82,8 @@
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <3000 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -92,8 +93,8 @@
                         #size-cells = <0>;
                         cell-index = <1>;
                         compatible = "fsl-i2c";
-                        reg = <3100 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -102,30 +103,30 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@0 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <0>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                         phy2: ethernet-phy@2 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <2>;
+                                reg = <0x2>;
                                 device_type = "ethernet-phy";
                         };
                         phy3: ethernet-phy@3 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <3>;
+                                reg = <0x3>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -135,9 +136,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy0>;
                 };
@@ -147,9 +148,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <25000 1000>;
+                        reg = <0x25000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <23 2 24 2 28 2>;
+                        interrupts = <35 2 36 2 40 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy1>;
                 };
@@ -160,9 +161,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <26000 1000>;
+                        reg = <0x26000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1f 2 20 2 21 2>;
+                        interrupts = <31 2 32 2 33 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy2>;
                 };
@@ -172,9 +173,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <27000 1000>;
+                        reg = <0x27000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <25 2 26 2 27 2>;
+                        interrupts = <37 2 38 2 39 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy3>;
                 };
@@ -184,9 +185,9 @@
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4500 100>;       // reg base, size
+                        reg = <0x4500 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -194,15 +195,15 @@
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4600 100>;       // reg base, size
+                        reg = <0x4600 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
                 global-utilities@e0000 {        //global utilities reg
                         compatible = "fsl,mpc8548-guts";
-                        reg = <e0000 1000>;
+                        reg = <0xe0000 0x1000>;
                         fsl,has-rstcr;
                 };
 
@@ -211,7 +212,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
@@ -220,139 +221,139 @@
 
         pci0: pci@e0008000 {
                 cell-index = <0>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x4 (PCIX Slot 2) */
-                        02000 0 0 1 &mpic 0 1
-                        02000 0 0 2 &mpic 1 1
-                        02000 0 0 3 &mpic 2 1
-                        02000 0 0 4 &mpic 3 1
+                        0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x5 (PCIX Slot 3) */
-                        02800 0 0 1 &mpic 1 1
-                        02800 0 0 2 &mpic 2 1
-                        02800 0 0 3 &mpic 3 1
-                        02800 0 0 4 &mpic 0 1
+                        0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                         /* IDSEL 0x6 (PCIX Slot 4) */
-                        03000 0 0 1 &mpic 2 1
-                        03000 0 0 2 &mpic 3 1
-                        03000 0 0 3 &mpic 0 1
-                        03000 0 0 4 &mpic 1 1
+                        0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x8 (PCIX Slot 5) */
-                        04000 0 0 1 &mpic 0 1
-                        04000 0 0 2 &mpic 1 1
-                        04000 0 0 3 &mpic 2 1
-                        04000 0 0 4 &mpic 3 1
+                        0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0xC (Tsi310 bridge) */
-                        06000 0 0 1 &mpic 0 1
-                        06000 0 0 2 &mpic 1 1
-                        06000 0 0 3 &mpic 2 1
-                        06000 0 0 4 &mpic 3 1
+                        0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x14 (Slot 2) */
-                        0a000 0 0 1 &mpic 0 1
-                        0a000 0 0 2 &mpic 1 1
-                        0a000 0 0 3 &mpic 2 1
-                        0a000 0 0 4 &mpic 3 1
+                        0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x15 (Slot 3) */
-                        0a800 0 0 1 &mpic 1 1
-                        0a800 0 0 2 &mpic 2 1
-                        0a800 0 0 3 &mpic 3 1
-                        0a800 0 0 4 &mpic 0 1
+                        0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                         /* IDSEL 0x16 (Slot 4) */
-                        0b000 0 0 1 &mpic 2 1
-                        0b000 0 0 2 &mpic 3 1
-                        0b000 0 0 3 &mpic 0 1
-                        0b000 0 0 4 &mpic 1 1
+                        0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x18 (Slot 5) */
-                        0c000 0 0 1 &mpic 0 1
-                        0c000 0 0 2 &mpic 1 1
-                        0c000 0 0 3 &mpic 2 1
-                        0c000 0 0 4 &mpic 3 1
+                        0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
-                        0E000 0 0 1 &mpic 0 1
-                        0E000 0 0 2 &mpic 1 1
-                        0E000 0 0 3 &mpic 2 1
-                        0E000 0 0 4 &mpic 3 1>;
+                        0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
+                interrupts = <24 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 80000000 80000000 0 10000000
-                          01000000 0 00000000 e2000000 0 00800000>;
-                clock-frequency = <3f940aa>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0008000 1000>;
+                reg = <0xe0008000 0x1000>;
                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
                 device_type = "pci";
 
                 pci_bridge@1c {
-                        interrupt-map-mask = <f800 0 0 7>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                         interrupt-map = <
 
                                 /* IDSEL 0x00 (PrPMC Site) */
-                                0000 0 0 1 &mpic 0 1
-                                0000 0 0 2 &mpic 1 1
-                                0000 0 0 3 &mpic 2 1
-                                0000 0 0 4 &mpic 3 1
+                                0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                                0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                 /* IDSEL 0x04 (VIA chip) */
-                                2000 0 0 1 &mpic 0 1
-                                2000 0 0 2 &mpic 1 1
-                                2000 0 0 3 &mpic 2 1
-                                2000 0 0 4 &mpic 3 1
+                                0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+                                0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                 /* IDSEL 0x05 (8139) */
-                                2800 0 0 1 &mpic 1 1
+                                0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 
                                 /* IDSEL 0x06 (Slot 6) */
-                                3000 0 0 1 &mpic 2 1
-                                3000 0 0 2 &mpic 3 1
-                                3000 0 0 3 &mpic 0 1
-                                3000 0 0 4 &mpic 1 1
+                                0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+                                0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+                                0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+                                0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                                 /* IDESL 0x07 (Slot 7) */
-                                3800 0 0 1 &mpic 3 1
-                                3800 0 0 2 &mpic 0 1
-                                3800 0 0 3 &mpic 1 1
-                                3800 0 0 4 &mpic 2 1>;
+                                0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
+                                0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
+                                0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
+                                0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 
-                        reg = <e000 0 0 0 0>;
+                        reg = <0xe000 0x0 0x0 0x0 0x0>;
                         #interrupt-cells = <1>;
                         #size-cells = <2>;
                         #address-cells = <3>;
-                        ranges = <02000000 0 80000000
-                                  02000000 0 80000000
-                                  0 20000000
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00080000>;
-                        clock-frequency = <1fca055>;
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x80000>;
+                        clock-frequency = <33333333>;
 
                         isa@4 {
                                 device_type = "isa";
                                 #interrupt-cells = <2>;
                                 #size-cells = <1>;
                                 #address-cells = <2>;
-                                reg = <2000 0 0 0 0>;
-                                ranges = <1 0 01000000 0 0 00001000>;
+                                reg = <0x2000 0x0 0x0 0x0 0x0>;
+                                ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
                                 interrupt-parent = <&i8259>;
 
                                 i8259: interrupt-controller@20 {
                                         interrupt-controller;
                                         device_type = "interrupt-controller";
-                                        reg = <1 20 2
-                                               1 a0 2
-                                               1 4d0 2>;
+                                        reg = <0x1 0x20 0x2
+                                               0x1 0xa0 0x2
+                                               0x1 0x4d0 0x2>;
                                         #address-cells = <0>;
                                         #interrupt-cells = <2>;
                                         compatible = "chrp,iic";
@@ -362,7 +363,7 @@
 
                                 rtc@70 {
                                         compatible = "pnpPNP,b00";
-                                        reg = <1 70 2>;
+                                        reg = <0x1 0x70 0x2>;
                                 };
                         };
                 };
@@ -370,64 +371,64 @@
 
         pci1: pci@e0009000 {
                 cell-index = <1>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x15 */
-                        a800 0 0 1 &mpic b 1
-                        a800 0 0 2 &mpic 1 1
-                        a800 0 0 3 &mpic 2 1
-                        a800 0 0 4 &mpic 3 1>;
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                 interrupt-parent = <&mpic>;
-                interrupts = <19 2>;
+                interrupts = <25 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 90000000 90000000 0 10000000
-                          01000000 0 00000000 e2800000 0 00800000>;
-                clock-frequency = <3f940aa>;
+                ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+                          0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0009000 1000>;
+                reg = <0xe0009000 0x1000>;
                 compatible = "fsl,mpc8540-pci";
                 device_type = "pci";
         };
 
         pci2: pcie@e000a000 {
                 cell-index = <2>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x0 (PEX) */
-                        00000 0 0 1 &mpic 0 1
-                        00000 0 0 2 &mpic 1 1
-                        00000 0 0 3 &mpic 2 1
-                        00000 0 0 4 &mpic 3 1>;
+                        00000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        00000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        00000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                 interrupt-parent = <&mpic>;
-                interrupts = <1a 2>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 a0000000 a0000000 0 20000000
-                          01000000 0 00000000 e3000000 0 08000000>;
-                clock-frequency = <1fca055>;
+                interrupts = <26 2>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
+                clock-frequency = <33333333>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e000a000 1000>;
+                reg = <0xe000a000 0x1000>;
                 compatible = "fsl,mpc8548-pcie";
                 device_type = "pci";
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 a0000000
-                                  02000000 0 a0000000
-                                  0 20000000
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 08000000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x8000000>;
                 };
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 4538f3c38862..b025c566c10d 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8555 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "MPC8555CDS";
@@ -31,11 +32,11 @@
 
                 PowerPC,8555@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;       //  33 MHz, from uboot
                         bus-frequency = <0>;    // 166 MHz
                         clock-frequency = <0>;  // 825 MHz, from uboot
@@ -44,31 +45,31 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 08000000>;      // 128M at 0x0
+                reg = <0x0 0x8000000>;  // 128M at 0x0
         };
 
         soc8555@e0000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 e0000000 00100000>;
-                reg = <e0000000 00001000>;      // CCSRBAR 1M
+                ranges = <0x0 0xe0000000 0x100000>;
+                reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                 bus-frequency = <0>;
 
                 memory-controller@2000 {
                         compatible = "fsl,8555-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,8555-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <40000>;   // L2, 256K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 i2c@3000 {
@@ -76,8 +77,8 @@
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <3000 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -86,18 +87,18 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@0 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <0>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -107,9 +108,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy0>;
                 };
@@ -119,9 +120,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <25000 1000>;
+                        reg = <0x25000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <23 2 24 2 28 2>;
+                        interrupts = <35 2 36 2 40 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy1>;
                 };
@@ -130,9 +131,9 @@
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4500 100>;       // reg base, size
+                        reg = <0x4500 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -140,9 +141,9 @@
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4600 100>;       // reg base, size
+                        reg = <0x4600 0x100>;   // reg base, size
                         clock-frequency = <0>;  // should we fill in in uboot?
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -151,7 +152,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
@@ -161,17 +162,17 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
-                        reg = <919c0 30>;
+                        reg = <0x919c0 0x30>;
                         ranges;
 
                         muram@80000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 80000 10000>;
+                                ranges = <0x0 0x80000 0x10000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 2000 9000 1000>;
+                                        reg = <0x0 0x2000 0x9000 0x1000>;
                                 };
                         };
 
@@ -179,16 +180,16 @@
                                 compatible = "fsl,mpc8555-brg",
                                              "fsl,cpm2-brg",
                                              "fsl,cpm-brg";
-                                reg = <919f0 10 915f0 10>;
+                                reg = <0x919f0 0x10 0x915f0 0x10>;
                         };
 
                         cpmpic: pic@90c00 {
                                 interrupt-controller;
                                 #address-cells = <0>;
                                 #interrupt-cells = <2>;
-                                interrupts = <2e 2>;
+                                interrupts = <46 2>;
                                 interrupt-parent = <&mpic>;
-                                reg = <90c00 80>;
+                                reg = <0x90c00 0x80>;
                                 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
                         };
                 };
@@ -196,68 +197,68 @@
 
         pci0: pci@e0008000 {
                 cell-index = <0>;
-                interrupt-map-mask = <1f800 0 0 7>;
+                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x10 */
-                        08000 0 0 1 &mpic 0 1
-                        08000 0 0 2 &mpic 1 1
-                        08000 0 0 3 &mpic 2 1
-                        08000 0 0 4 &mpic 3 1
+                        0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x11 */
-                        08800 0 0 1 &mpic 0 1
-                        08800 0 0 2 &mpic 1 1
-                        08800 0 0 3 &mpic 2 1
-                        08800 0 0 4 &mpic 3 1
+                        0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x12 (Slot 1) */
-                        09000 0 0 1 &mpic 0 1
-                        09000 0 0 2 &mpic 1 1
-                        09000 0 0 3 &mpic 2 1
-                        09000 0 0 4 &mpic 3 1
+                        0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                         /* IDSEL 0x13 (Slot 2) */
-                        09800 0 0 1 &mpic 1 1
-                        09800 0 0 2 &mpic 2 1
-                        09800 0 0 3 &mpic 3 1
-                        09800 0 0 4 &mpic 0 1
+                        0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                         /* IDSEL 0x14 (Slot 3) */
-                        0a000 0 0 1 &mpic 2 1
-                        0a000 0 0 2 &mpic 3 1
-                        0a000 0 0 3 &mpic 0 1
-                        0a000 0 0 4 &mpic 1 1
+                        0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x15 (Slot 4) */
-                        0a800 0 0 1 &mpic 3 1
-                        0a800 0 0 2 &mpic 0 1
-                        0a800 0 0 3 &mpic 1 1
-                        0a800 0 0 4 &mpic 2 1
+                        0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* Bus 1 (Tundra Bridge) */
                         /* IDSEL 0x12 (ISA bridge) */
-                        19000 0 0 1 &mpic 0 1
-                        19000 0 0 2 &mpic 1 1
-                        19000 0 0 3 &mpic 2 1
-                        19000 0 0 4 &mpic 3 1>;
+                        0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
+                interrupts = <24 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 80000000 80000000 0 20000000
-                          01000000 0 00000000 e2000000 0 00100000>;
-                clock-frequency = <3f940aa>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0008000 1000>;
+                reg = <0xe0008000 0x1000>;
                 compatible = "fsl,mpc8540-pci";
                 device_type = "pci";
 
                 i8259@19000 {
                         interrupt-controller;
                         device_type = "interrupt-controller";
-                        reg = <19000 0 0 0 1>;
+                        reg = <0x19000 0x0 0x0 0x0 0x1>;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
                         compatible = "chrp,iic";
@@ -268,24 +269,24 @@
 
         pci1: pci@e0009000 {
                 cell-index = <1>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x15 */
-                        a800 0 0 1 &mpic b 1
-                        a800 0 0 2 &mpic b 1
-                        a800 0 0 3 &mpic b 1
-                        a800 0 0 4 &mpic b 1>;
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
                 interrupt-parent = <&mpic>;
-                interrupts = <19 2>;
+                interrupts = <25 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 a0000000 a0000000 0 20000000
-                          01000000 0 00000000 e3000000 0 00100000>;
-                clock-frequency = <3f940aa>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0009000 1000>;
+                reg = <0xe0009000 0x1000>;
                 compatible = "fsl,mpc8540-pci";
                 device_type = "pci";
         };
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 639ce8a709a6..0cc16ab305d1 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8560 ADS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "MPC8560ADS";
@@ -32,74 +33,74 @@
 
                 PowerPC,8560@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
-                        timebase-frequency = <04ead9a0>;
-                        bus-frequency = <13ab6680>;
-                        clock-frequency = <312c8040>;
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
+                        timebase-frequency = <82500000>;
+                        bus-frequency = <330000000>;
+                        clock-frequency = <825000000>;
                 };
         };
 
         memory {
                 device_type = "memory";
-                reg = <00000000 10000000>;
+                reg = <0x0 0x10000000>;
         };
 
         soc8560@e0000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 e0000000 00100000>;
-                reg = <e0000000 00000200>;
-                bus-frequency = <13ab6680>;
+                ranges = <0x0 0xe0000000 0x100000>;
+                reg = <0xe0000000 0x200>;
+                bus-frequency = <330000000>;
 
                 memory-controller@2000 {
                         compatible = "fsl,8540-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,8540-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <40000>;   // L2, 256K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 mdio@24520 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@0 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <0>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1>;
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                         phy2: ethernet-phy@2 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <7 1>;
-                                reg = <2>;
+                                reg = <0x2>;
                                 device_type = "ethernet-phy";
                         };
                         phy3: ethernet-phy@3 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <7 1>;
-                                reg = <3>;
+                                reg = <0x3>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -109,9 +110,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy0>;
                 };
@@ -121,9 +122,9 @@
                         device_type = "network";
                         model = "TSEC";
                         compatible = "gianfar";
-                        reg = <25000 1000>;
+                        reg = <0x25000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <23 2 24 2 28 2>;
+                        interrupts = <35 2 36 2 40 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy1>;
                 };
@@ -132,7 +133,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         device_type = "open-pic";
                 };
 
@@ -140,17 +141,17 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
-                        reg = <919c0 30>;
+                        reg = <0x919c0 0x30>;
                         ranges;
 
                         muram@80000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 80000 10000>;
+                                ranges = <0x0 0x80000 0x10000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 4000 9000 2000>;
+                                        reg = <0x0 0x4000 0x9000 0x2000>;
                                 };
                         };
 
@@ -158,17 +159,17 @@
                                 compatible = "fsl,mpc8560-brg",
                                              "fsl,cpm2-brg",
                                              "fsl,cpm-brg";
-                                reg = <919f0 10 915f0 10>;
-                                clock-frequency = <d#165000000>;
+                                reg = <0x919f0 0x10 0x915f0 0x10>;
+                                clock-frequency = <165000000>;
                         };
 
                         cpmpic: pic@90c00 {
                                 interrupt-controller;
                                 #address-cells = <0>;
                                 #interrupt-cells = <2>;
-                                interrupts = <2e 2>;
+                                interrupts = <46 2>;
                                 interrupt-parent = <&mpic>;
-                                reg = <90c00 80>;
+                                reg = <0x90c00 0x80>;
                                 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
                         };
 
@@ -176,11 +177,11 @@
                                 device_type = "serial";
                                 compatible = "fsl,mpc8560-scc-uart",
                                              "fsl,cpm2-scc-uart";
-                                reg = <91a00 20 88000 100>;
+                                reg = <0x91a00 0x20 0x88000 0x100>;
                                 fsl,cpm-brg = <1>;
-                                fsl,cpm-command = <00800000>;
-                                current-speed = <1c200>;
-                                interrupts = <28 8>;
+                                fsl,cpm-command = <0x800000>;
+                                current-speed = <115200>;
+                                interrupts = <40 8>;
                                 interrupt-parent = <&cpmpic>;
                         };
 
@@ -188,11 +189,11 @@
                                 device_type = "serial";
                                 compatible = "fsl,mpc8560-scc-uart",
                                              "fsl,cpm2-scc-uart";
-                                reg = <91a20 20 88100 100>;
+                                reg = <0x91a20 0x20 0x88100 0x100>;
                                 fsl,cpm-brg = <2>;
-                                fsl,cpm-command = <04a00000>;
-                                current-speed = <1c200>;
-                                interrupts = <29 8>;
+                                fsl,cpm-command = <0x4a00000>;
+                                current-speed = <115200>;
+                                interrupts = <41 8>;
                                 interrupt-parent = <&cpmpic>;
                         };
 
@@ -200,10 +201,10 @@
                                 device_type = "network";
                                 compatible = "fsl,mpc8560-fcc-enet",
                                              "fsl,cpm2-fcc-enet";
-                                reg = <91320 20 88500 100 913b0 1>;
+                                reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
-                                fsl,cpm-command = <16200300>;
-                                interrupts = <21 8>;
+                                fsl,cpm-command = <0x16200300>;
+                                interrupts = <33 8>;
                                 interrupt-parent = <&cpmpic>;
                                 phy-handle = <&phy2>;
                         };
@@ -212,10 +213,10 @@
                                 device_type = "network";
                                 compatible = "fsl,mpc8560-fcc-enet",
                                              "fsl,cpm2-fcc-enet";
-                                reg = <91340 20 88600 100 913d0 1>;
+                                reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
-                                fsl,cpm-command = <1a400300>;
-                                interrupts = <22 8>;
+                                fsl,cpm-command = <0x1a400300>;
+                                interrupts = <34 8>;
                                 interrupt-parent = <&cpmpic>;
                                 phy-handle = <&phy3>;
                         };
@@ -229,87 +230,87 @@
                 #address-cells = <3>;
                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
                 device_type = "pci";
-                reg = <e0008000 1000>;
-                clock-frequency = <3f940aa>;
-                interrupt-map-mask = <f800 0 0 7>;
+                reg = <0xe0008000 0x1000>;
+                clock-frequency = <66666666>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                                 /* IDSEL 0x2 */
-                                 1000 0 0 1 &mpic 1 1
-                                 1000 0 0 2 &mpic 2 1
-                                 1000 0 0 3 &mpic 3 1
-                                 1000 0 0 4 &mpic 4 1
+                                 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                                 /* IDSEL 0x3 */
-                                 1800 0 0 1 &mpic 4 1
-                                 1800 0 0 2 &mpic 1 1
-                                 1800 0 0 3 &mpic 2 1
-                                 1800 0 0 4 &mpic 3 1
+                                 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+                                 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                 /* IDSEL 0x4 */
-                                 2000 0 0 1 &mpic 3 1
-                                 2000 0 0 2 &mpic 4 1
-                                 2000 0 0 3 &mpic 1 1
-                                 2000 0 0 4 &mpic 2 1
+                                 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+                                 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+                                 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                                 /* IDSEL 0x5  */
-                                 2800 0 0 1 &mpic 2 1
-                                 2800 0 0 2 &mpic 3 1
-                                 2800 0 0 3 &mpic 4 1
-                                 2800 0 0 4 &mpic 1 1
+                                 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+                                 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+                                 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+                                 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                                 /* IDSEL 12 */
-                                 6000 0 0 1 &mpic 1 1
-                                 6000 0 0 2 &mpic 2 1
-                                 6000 0 0 3 &mpic 3 1
-                                 6000 0 0 4 &mpic 4 1
+                                 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                                 /* IDSEL 13 */
-                                 6800 0 0 1 &mpic 4 1
-                                 6800 0 0 2 &mpic 1 1
-                                 6800 0 0 3 &mpic 2 1
-                                 6800 0 0 4 &mpic 3 1
+                                 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+                                 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                 /* IDSEL 14*/
-                                 7000 0 0 1 &mpic 3 1
-                                 7000 0 0 2 &mpic 4 1
-                                 7000 0 0 3 &mpic 1 1
-                                 7000 0 0 4 &mpic 2 1
+                                 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+                                 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+                                 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                                 /* IDSEL 15 */
-                                 7800 0 0 1 &mpic 2 1
-                                 7800 0 0 2 &mpic 3 1
-                                 7800 0 0 3 &mpic 4 1
-                                 7800 0 0 4 &mpic 1 1
+                                 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+                                 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+                                 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+                                 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                                 /* IDSEL 18 */
-                                 9000 0 0 1 &mpic 1 1
-                                 9000 0 0 2 &mpic 2 1
-                                 9000 0 0 3 &mpic 3 1
-                                 9000 0 0 4 &mpic 4 1
+                                 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                                 /* IDSEL 19 */
-                                 9800 0 0 1 &mpic 4 1
-                                 9800 0 0 2 &mpic 1 1
-                                 9800 0 0 3 &mpic 2 1
-                                 9800 0 0 4 &mpic 3 1
+                                 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+                                 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                 /* IDSEL 20 */
-                                 a000 0 0 1 &mpic 3 1
-                                 a000 0 0 2 &mpic 4 1
-                                 a000 0 0 3 &mpic 1 1
-                                 a000 0 0 4 &mpic 2 1
+                                 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+                                 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+                                 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                                 /* IDSEL 21 */
-                                 a800 0 0 1 &mpic 2 1
-                                 a800 0 0 2 &mpic 3 1
-                                 a800 0 0 3 &mpic 4 1
-                                 a800 0 0 4 &mpic 1 1>;
+                                 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+                                 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+                                 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+                                 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
+                interrupts = <24 2>;
                 bus-range = <0 0>;
-                ranges = <02000000 0 80000000 80000000 0 20000000
-                          01000000 0 00000000 e2000000 0 01000000>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 97bc048f2158..a025a8ededc5 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8568E MDS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,10 +9,7 @@
  * option) any later version.
  */
 
-
-/*
-/memreserve/    00000000 1000000;
-*/
+/dts-v1/;
 
 / {
         model = "MPC8568EMDS";
@@ -37,11 +34,11 @@
 
                 PowerPC,8568@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
@@ -50,36 +47,36 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 10000000>;
+                reg = <0x0 0x10000000>;
         };
 
         bcsr@f8000000 {
                 device_type = "board-control";
-                reg = <f8000000 8000>;
+                reg = <0xf8000000 0x8000>;
         };
 
         soc8568@e0000000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 e0000000 00100000>;
-                reg = <e0000000 00001000>;
+                ranges = <0x0 0xe0000000 0x100000>;
+                reg = <0xe0000000 0x1000>;
                 bus-frequency = <0>;
 
                 memory-controller@2000 {
                         compatible = "fsl,8568-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,8568-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <80000>;   // L2, 512K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2, 512K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 i2c@3000 {
@@ -87,14 +84,14 @@
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <3000 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
 
                         rtc@68 {
                                 compatible = "dallas,ds1374";
-                                reg = <68>;
+                                reg = <0x68>;
                         };
                 };
 
@@ -103,8 +100,8 @@
                         #size-cells = <0>;
                         cell-index = <1>;
                         compatible = "fsl-i2c";
-                        reg = <3100 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -113,30 +110,30 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@7 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <1 1>;
-                                reg = <7>;
+                                reg = <0x7>;
                                 device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1>;
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                         phy2: ethernet-phy@2 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <1 1>;
-                                reg = <2>;
+                                reg = <0x2>;
                                 device_type = "ethernet-phy";
                         };
                         phy3: ethernet-phy@3 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1>;
-                                reg = <3>;
+                                reg = <0x3>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -146,9 +143,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy2>;
                 };
@@ -158,9 +155,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <25000 1000>;
+                        reg = <0x25000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <23 2 24 2 28 2>;
+                        interrupts = <35 2 36 2 40 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy3>;
                 };
@@ -169,15 +166,15 @@
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4500 100>;
+                        reg = <0x4500 0x100>;
                         clock-frequency = <0>;
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
                 global-utilities@e0000 {        //global utilities block
                         compatible = "fsl,mpc8548-guts";
-                        reg = <e0000 1000>;
+                        reg = <0xe0000 0x1000>;
                         fsl,has-rstcr;
                 };
 
@@ -185,9 +182,9 @@
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4600 100>;
+                        reg = <0x4600 0x100>;
                         clock-frequency = <0>;
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -195,13 +192,13 @@
                         device_type = "crypto";
                         model = "SEC2";
                         compatible = "talitos";
-                        reg = <30000 f000>;
-                        interrupts = <2d 2>;
+                        reg = <0x30000 0xf000>;
+                        interrupts = <45 2>;
                         interrupt-parent = <&mpic>;
                         num-channels = <4>;
-                        channel-fifo-len = <18>;
-                        exec-units-mask = <000000fe>;
-                        descriptor-types-mask = <012b0ebf>;
+                        channel-fifo-len = <24>;
+                        exec-units-mask = <0xfe>;
+                        descriptor-types-mask = <0x12b0ebf>;
                 };
 
                 mpic: pic@40000 {
@@ -209,73 +206,73 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
                 };
 
                 par_io@e0100 {
-                        reg = <e0100 100>;
+                        reg = <0xe0100 0x100>;
                         device_type = "par_io";
                         num-ports = <7>;
 
                         pio1: ucc_pin@01 {
                                 pio-map = <
                         /* port  pin  dir  open_drain  assignment  has_irq */
-                                        4  0a  1  0  2  0       /* TxD0 */
-                                        4  09  1  0  2  0       /* TxD1 */
-                                        4  08  1  0  2  0       /* TxD2 */
-                                        4  07  1  0  2  0       /* TxD3 */
-                                        4  17  1  0  2  0       /* TxD4 */
-                                        4  16  1  0  2  0       /* TxD5 */
-                                        4  15  1  0  2  0       /* TxD6 */
-                                        4  14  1  0  2  0       /* TxD7 */
-                                        4  0f  2  0  2  0       /* RxD0 */
-                                        4  0e  2  0  2  0       /* RxD1 */
-                                        4  0d  2  0  2  0       /* RxD2 */
-                                        4  0c  2  0  2  0       /* RxD3 */
-                                        4  1d  2  0  2  0       /* RxD4 */
-                                        4  1c  2  0  2  0       /* RxD5 */
-                                        4  1b  2  0  2  0       /* RxD6 */
-                                        4  1a  2  0  2  0       /* RxD7 */
-                                        4  0b  1  0  2  0       /* TX_EN */
-                                        4  18  1  0  2  0       /* TX_ER */
-                                        4  10  2  0  2  0       /* RX_DV */
-                                        4  1e  2  0  2  0       /* RX_ER */
-                                        4  11  2  0  2  0       /* RX_CLK */
-                                        4  13  1  0  2  0       /* GTX_CLK */
-                                        1  1f  2  0  3  0>;     /* GTX125 */
+                                        0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
+                                        0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
+                                        0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
+                                        0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
+                                        0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
+                                        0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
+                                        0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
+                                        0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
+                                        0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
+                                        0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
+                                        0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
+                                        0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
+                                        0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
+                                        0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
+                                        0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
+                                        0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
+                                        0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
+                                        0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
+                                        0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
+                                        0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
+                                        0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
+                                        0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
+                                        0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
                         };
 
                         pio2: ucc_pin@02 {
                                 pio-map = <
                         /* port  pin  dir  open_drain  assignment  has_irq */
-                                        5  0a 1  0  2  0   /* TxD0 */
-                                        5  09 1  0  2  0   /* TxD1 */
-                                        5  08 1  0  2  0   /* TxD2 */
-                                        5  07 1  0  2  0   /* TxD3 */
-                                        5  17 1  0  2  0   /* TxD4 */
-                                        5  16 1  0  2  0   /* TxD5 */
-                                        5  15 1  0  2  0   /* TxD6 */
-                                        5  14 1  0  2  0   /* TxD7 */
-                                        5  0f 2  0  2  0   /* RxD0 */
-                                        5  0e 2  0  2  0   /* RxD1 */
-                                        5  0d 2  0  2  0   /* RxD2 */
-                                        5  0c 2  0  2  0   /* RxD3 */
-                                        5  1d 2  0  2  0   /* RxD4 */
-                                        5  1c 2  0  2  0   /* RxD5 */
-                                        5  1b 2  0  2  0   /* RxD6 */
-                                        5  1a 2  0  2  0   /* RxD7 */
-                                        5  0b 1  0  2  0   /* TX_EN */
-                                        5  18 1  0  2  0   /* TX_ER */
-                                        5  10 2  0  2  0   /* RX_DV */
-                                        5  1e 2  0  2  0   /* RX_ER */
-                                        5  11 2  0  2  0   /* RX_CLK */
-                                        5  13 1  0  2  0   /* GTX_CLK */
-                                        1  1f 2  0  3  0   /* GTX125 */
-                                        4  06 3  0  2  0   /* MDIO */
-                                        4  05 1  0  2  0>; /* MDC */
+                                        0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
+                                        0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
+                                        0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
+                                        0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
+                                        0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
+                                        0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
+                                        0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
+                                        0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
+                                        0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
+                                        0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
+                                        0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
+                                        0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
+                                        0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
+                                        0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
+                                        0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
+                                        0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
+                                        0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
+                                        0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
+                                        0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
+                                        0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
+                                        0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
+                                        0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
+                                        0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
+                                        0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
+                                        0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
                         };
                 };
         };
@@ -285,28 +282,28 @@
                 #size-cells = <1>;
                 device_type = "qe";
                 compatible = "fsl,qe";
-                ranges = <0 e0080000 00040000>;
-                reg = <e0080000 480>;
+                ranges = <0x0 0xe0080000 0x40000>;
+                reg = <0xe0080000 0x480>;
                 brg-frequency = <0>;
-                bus-frequency = <179A7B00>;
+                bus-frequency = <396000000>;
 
                 muram@10000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
-                        ranges = <0 00010000 0000c000>;
+                        ranges = <0x0 0x10000 0x10000>;
 
                         data-only@0 {
                                 compatible = "fsl,qe-muram-data",
                                              "fsl,cpm-muram-data";
-                                reg = <0 c000>;
+                                reg = <0x0 0x10000>;
                         };
                 };
 
                 spi@4c0 {
                         cell-index = <0>;
                         compatible = "fsl,spi";
-                        reg = <4c0 40>;
+                        reg = <0x4c0 0x40>;
                         interrupts = <2>;
                         interrupt-parent = <&qeic>;
                         mode = "cpu";
@@ -315,7 +312,7 @@
                 spi@500 {
                         cell-index = <1>;
                         compatible = "fsl,spi";
-                        reg = <500 40>;
+                        reg = <0x500 0x40>;
                         interrupts = <1>;
                         interrupt-parent = <&qeic>;
                         mode = "cpu";
@@ -324,11 +321,9 @@
                 enet2: ucc@2000 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <1>;
-                        device-id = <1>;
-                        reg = <2000 200>;
-                        interrupts = <20>;
+                        reg = <0x2000 0x200>;
+                        interrupts = <32>;
                         interrupt-parent = <&qeic>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         rx-clock-name = "none";
@@ -341,11 +336,9 @@
                 enet3: ucc@3000 {
                         device_type = "network";
                         compatible = "ucc_geth";
-                        model = "UCC";
                         cell-index = <2>;
-                        device-id = <2>;
-                        reg = <3000 200>;
-                        interrupts = <21>;
+                        reg = <0x3000 0x200>;
+                        interrupts = <33>;
                         interrupt-parent = <&qeic>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         rx-clock-name = "none";
@@ -358,7 +351,7 @@
                 mdio@2120 {
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        reg = <2120 18>;
+                        reg = <0x2120 0x18>;
                         compatible = "fsl,ucc-mdio";
 
                         /* These are the same PHYs as on
@@ -366,25 +359,25 @@
                         qe_phy0: ethernet-phy@07 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <1 1>;
-                                reg = <7>;
+                                reg = <0x7>;
                                 device_type = "ethernet-phy";
                         };
                         qe_phy1: ethernet-phy@01 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1>;
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
                         qe_phy2: ethernet-phy@02 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <1 1>;
-                                reg = <2>;
+                                reg = <0x2>;
                                 device_type = "ethernet-phy";
                         };
                         qe_phy3: ethernet-phy@03 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1>;
-                                reg = <3>;
+                                reg = <0x3>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -394,9 +387,9 @@
                         compatible = "fsl,qe-ic";
                         #address-cells = <0>;
                         #interrupt-cells = <1>;
-                        reg = <80 80>;
+                        reg = <0x80 0x80>;
                         big-endian;
-                        interrupts = <2e 2 2e 2>; //high:30 low:30
+                        interrupts = <46 2 46 2>; //high:30 low:30
                         interrupt-parent = <&mpic>;
                 };
 
@@ -404,30 +397,30 @@
 
         pci0: pci@e0008000 {
                 cell-index = <0>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x12 AD18 */
-                        9000 0 0 1 &mpic 5 1
-                        9000 0 0 2 &mpic 6 1
-                        9000 0 0 3 &mpic 7 1
-                        9000 0 0 4 &mpic 4 1
+                        0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                         /* IDSEL 0x13 AD19 */
-                        9800 0 0 1 &mpic 6 1
-                        9800 0 0 2 &mpic 7 1
-                        9800 0 0 3 &mpic 4 1
-                        9800 0 0 4 &mpic 5 1>;
+                        0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
+                        0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
+                        0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 80000000 80000000 0 20000000
-                          01000000 0 00000000 e2000000 0 00800000>;
-                clock-frequency = <3f940aa>;
+                interrupts = <24 2>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+                clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e0008000 1000>;
+                reg = <0xe0008000 0x1000>;
                 compatible = "fsl,mpc8540-pci";
                 device_type = "pci";
         };
@@ -435,39 +428,39 @@
         /* PCI Express */
         pci1: pcie@e000a000 {
                 cell-index = <2>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
 
                         /* IDSEL 0x0 (PEX) */
-                        00000 0 0 1 &mpic 0 1
-                        00000 0 0 2 &mpic 1 1
-                        00000 0 0 3 &mpic 2 1
-                        00000 0 0 4 &mpic 3 1>;
+                        00000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        00000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        00000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                 interrupt-parent = <&mpic>;
-                interrupts = <1a 2>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 a0000000 a0000000 0 10000000
-                          01000000 0 00000000 e2800000 0 00800000>;
-                clock-frequency = <1fca055>;
+                interrupts = <26 2>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+                          0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+                clock-frequency = <33333333>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <e000a000 1000>;
+                reg = <0xe000a000 0x1000>;
                 compatible = "fsl,mpc8548-pcie";
                 device_type = "pci";
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 a0000000
-                                  02000000 0 a0000000
-                                  0 10000000
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x10000000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00800000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x800000>;
                 };
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index db37214aee37..66f27ab613a2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8572 DS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 / {
         model = "fsl,MPC8572DS";
         compatible = "fsl,MPC8572DS";
@@ -33,11 +34,11 @@
 
                 PowerPC,8572@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
@@ -45,11 +46,11 @@
 
                 PowerPC,8572@1 {
                         device_type = "cpu";
-                        reg = <1>;
-                        d-cache-line-size = <20>;       // 32 bytes
-                        i-cache-line-size = <20>;       // 32 bytes
-                        d-cache-size = <8000>;          // L1, 32K
-                        i-cache-size = <8000>;          // L1, 32K
+                        reg = <0x1>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
@@ -58,38 +59,38 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 00000000>;      // Filled by U-Boot
+                reg = <0x0 0x0>;        // Filled by U-Boot
         };
 
         soc8572@ffe00000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <00000000 ffe00000 00100000>;
-                reg = <ffe00000 00001000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
+                ranges = <0x0 0xffe00000 0x100000>;
+                reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                 bus-frequency = <0>;            // Filled out by uboot.
 
                 memory-controller@2000 {
                         compatible = "fsl,mpc8572-memory-controller";
-                        reg = <2000 1000>;
+                        reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 memory-controller@6000 {
                         compatible = "fsl,mpc8572-memory-controller";
-                        reg = <6000 1000>;
+                        reg = <0x6000 0x1000>;
                         interrupt-parent = <&mpic>;
-                        interrupts = <12 2>;
+                        interrupts = <18 2>;
                 };
 
                 l2-cache-controller@20000 {
                         compatible = "fsl,mpc8572-l2-cache-controller";
-                        reg = <20000 1000>;
-                        cache-line-size = <20>; // 32 bytes
-                        cache-size = <80000>;   // L2, 512K
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2, 512K
                         interrupt-parent = <&mpic>;
-                        interrupts = <10 2>;
+                        interrupts = <16 2>;
                 };
 
                 i2c@3000 {
@@ -97,8 +98,8 @@
                         #size-cells = <0>;
                         cell-index = <0>;
                         compatible = "fsl-i2c";
-                        reg = <3000 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -108,8 +109,8 @@
                         #size-cells = <0>;
                         cell-index = <1>;
                         compatible = "fsl-i2c";
-                        reg = <3100 100>;
-                        interrupts = <2b 2>;
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
                 };
@@ -118,27 +119,27 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,gianfar-mdio";
-                        reg = <24520 20>;
+                        reg = <0x24520 0x20>;
 
                         phy0: ethernet-phy@0 {
                                 interrupt-parent = <&mpic>;
-                                interrupts = <a 1>;
-                                reg = <0>;
+                                interrupts = <10 1>;
+                                reg = <0x0>;
                         };
                         phy1: ethernet-phy@1 {
                                 interrupt-parent = <&mpic>;
-                                interrupts = <a 1>;
-                                reg = <1>;
+                                interrupts = <10 1>;
+                                reg = <0x1>;
                         };
                         phy2: ethernet-phy@2 {
                                 interrupt-parent = <&mpic>;
-                                interrupts = <a 1>;
-                                reg = <2>;
+                                interrupts = <10 1>;
+                                reg = <0x2>;
                         };
                         phy3: ethernet-phy@3 {
                                 interrupt-parent = <&mpic>;
-                                interrupts = <a 1>;
-                                reg = <3>;
+                                interrupts = <10 1>;
+                                reg = <0x3>;
                         };
                 };
 
@@ -147,9 +148,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <24000 1000>;
+                        reg = <0x24000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1d 2 1e 2 22 2>;
+                        interrupts = <29 2 30 2 34 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy0>;
                         phy-connection-type = "rgmii-id";
@@ -160,9 +161,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <25000 1000>;
+                        reg = <0x25000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <23 2 24 2 28 2>;
+                        interrupts = <35 2 36 2 40 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy1>;
                         phy-connection-type = "rgmii-id";
@@ -173,9 +174,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <26000 1000>;
+                        reg = <0x26000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <1f 2 20 2 21 2>;
+                        interrupts = <31 2 32 2 33 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy2>;
                         phy-connection-type = "rgmii-id";
@@ -186,9 +187,9 @@
                         device_type = "network";
                         model = "eTSEC";
                         compatible = "gianfar";
-                        reg = <27000 1000>;
+                        reg = <0x27000 0x1000>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <25 2 26 2 27 2>;
+                        interrupts = <37 2 38 2 39 2>;
                         interrupt-parent = <&mpic>;
                         phy-handle = <&phy3>;
                         phy-connection-type = "rgmii-id";
@@ -198,9 +199,9 @@
                         cell-index = <0>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4500 100>;
+                        reg = <0x4500 0x100>;
                         clock-frequency = <0>;
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
@@ -208,15 +209,15 @@
                         cell-index = <1>;
                         device_type = "serial";
                         compatible = "ns16550";
-                        reg = <4600 100>;
+                        reg = <0x4600 0x100>;
                         clock-frequency = <0>;
-                        interrupts = <2a 2>;
+                        interrupts = <42 2>;
                         interrupt-parent = <&mpic>;
                 };
 
                 global-utilities@e0000 {        //global utilities block
                         compatible = "fsl,mpc8572-guts";
-                        reg = <e0000 1000>;
+                        reg = <0xe0000 0x1000>;
                         fsl,has-rstcr;
                 };
 
@@ -225,7 +226,7 @@
                         interrupt-controller;
                         #address-cells = <0>;
                         #interrupt-cells = <2>;
-                        reg = <40000 40000>;
+                        reg = <0x40000 0x40000>;
                         compatible = "chrp,open-pic";
                         device_type = "open-pic";
                         big-endian;
@@ -239,167 +240,167 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <ffe08000 1000>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 80000000 80000000 0 20000000
-                          01000000 0 00000000 ffc00000 0 00010000>;
-                clock-frequency = <1fca055>;
+                reg = <0xffe08000 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
+                clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <18 2>;
-                interrupt-map-mask = <ff00 0 0 7>;
+                interrupts = <24 2>;
+                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x11 func 0 - PCI slot 1 */
-                        8800 0 0 1 &mpic 2 1
-                        8800 0 0 2 &mpic 3 1
-                        8800 0 0 3 &mpic 4 1
-                        8800 0 0 4 &mpic 1 1
+                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x11 func 1 - PCI slot 1 */
-                        8900 0 0 1 &mpic 2 1
-                        8900 0 0 2 &mpic 3 1
-                        8900 0 0 3 &mpic 4 1
-                        8900 0 0 4 &mpic 1 1
+                        0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x11 func 2 - PCI slot 1 */
-                        8a00 0 0 1 &mpic 2 1
-                        8a00 0 0 2 &mpic 3 1
-                        8a00 0 0 3 &mpic 4 1
-                        8a00 0 0 4 &mpic 1 1
+                        0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x11 func 3 - PCI slot 1 */
-                        8b00 0 0 1 &mpic 2 1
-                        8b00 0 0 2 &mpic 3 1
-                        8b00 0 0 3 &mpic 4 1
-                        8b00 0 0 4 &mpic 1 1
+                        0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x11 func 4 - PCI slot 1 */
-                        8c00 0 0 1 &mpic 2 1
-                        8c00 0 0 2 &mpic 3 1
-                        8c00 0 0 3 &mpic 4 1
-                        8c00 0 0 4 &mpic 1 1
+                        0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x11 func 5 - PCI slot 1 */
-                        8d00 0 0 1 &mpic 2 1
-                        8d00 0 0 2 &mpic 3 1
-                        8d00 0 0 3 &mpic 4 1
-                        8d00 0 0 4 &mpic 1 1
+                        0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x11 func 6 - PCI slot 1 */
-                        8e00 0 0 1 &mpic 2 1
-                        8e00 0 0 2 &mpic 3 1
-                        8e00 0 0 3 &mpic 4 1
-                        8e00 0 0 4 &mpic 1 1
+                        0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x11 func 7 - PCI slot 1 */
-                        8f00 0 0 1 &mpic 2 1
-                        8f00 0 0 2 &mpic 3 1
-                        8f00 0 0 3 &mpic 4 1
-                        8f00 0 0 4 &mpic 1 1
+                        0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                         /* IDSEL 0x12 func 0 - PCI slot 2 */
-                        9000 0 0 1 &mpic 3 1
-                        9000 0 0 2 &mpic 4 1
-                        9000 0 0 3 &mpic 1 1
-                        9000 0 0 4 &mpic 2 1
+                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x12 func 1 - PCI slot 2 */
-                        9100 0 0 1 &mpic 3 1
-                        9100 0 0 2 &mpic 4 1
-                        9100 0 0 3 &mpic 1 1
-                        9100 0 0 4 &mpic 2 1
+                        0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x12 func 2 - PCI slot 2 */
-                        9200 0 0 1 &mpic 3 1
-                        9200 0 0 2 &mpic 4 1
-                        9200 0 0 3 &mpic 1 1
-                        9200 0 0 4 &mpic 2 1
+                        0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x12 func 3 - PCI slot 2 */
-                        9300 0 0 1 &mpic 3 1
-                        9300 0 0 2 &mpic 4 1
-                        9300 0 0 3 &mpic 1 1
-                        9300 0 0 4 &mpic 2 1
+                        0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x12 func 4 - PCI slot 2 */
-                        9400 0 0 1 &mpic 3 1
-                        9400 0 0 2 &mpic 4 1
-                        9400 0 0 3 &mpic 1 1
-                        9400 0 0 4 &mpic 2 1
+                        0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x12 func 5 - PCI slot 2 */
-                        9500 0 0 1 &mpic 3 1
-                        9500 0 0 2 &mpic 4 1
-                        9500 0 0 3 &mpic 1 1
-                        9500 0 0 4 &mpic 2 1
+                        0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x12 func 6 - PCI slot 2 */
-                        9600 0 0 1 &mpic 3 1
-                        9600 0 0 2 &mpic 4 1
-                        9600 0 0 3 &mpic 1 1
-                        9600 0 0 4 &mpic 2 1
+                        0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         /* IDSEL 0x12 func 7 - PCI slot 2 */
-                        9700 0 0 1 &mpic 3 1
-                        9700 0 0 2 &mpic 4 1
-                        9700 0 0 3 &mpic 1 1
-                        9700 0 0 4 &mpic 2 1
+                        0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
 
                         // IDSEL 0x1c  USB
-                        e000 0 0 1 &i8259 c 2
-                        e100 0 0 2 &i8259 9 2
-                        e200 0 0 3 &i8259 a 2
-                        e300 0 0 4 &i8259 b 2
+                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 
                         // IDSEL 0x1d  Audio
-                        e800 0 0 1 &i8259 6 2
+                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 
                         // IDSEL 0x1e Legacy
-                        f000 0 0 1 &i8259 7 2
-                        f100 0 0 1 &i8259 7 2
+                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 
                         // IDSEL 0x1f IDE/SATA
-                        f800 0 0 1 &i8259 e 2
-                        f900 0 0 1 &i8259 5 2
+                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 
                         >;
 
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 80000000
-                                  02000000 0 80000000
-                                  0 20000000
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00100000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
                         uli1575@0 {
-                                reg = <0 0 0 0 0>;
+                                reg = <0x0 0x0 0x0 0x0 0x0>;
                                 #size-cells = <2>;
                                 #address-cells = <3>;
-                                ranges = <02000000 0 80000000
-                                          02000000 0 80000000
-                                          0 20000000
+                                ranges = <0x2000000 0x0 0x80000000
+                                          0x2000000 0x0 0x80000000
+                                          0x0 0x20000000
 
-                                          01000000 0 00000000
-                                          01000000 0 00000000
-                                          0 00100000>;
+                                          0x1000000 0x0 0x0
+                                          0x1000000 0x0 0x0
+                                          0x0 0x100000>;
                                 isa@1e {
                                         device_type = "isa";
                                         #interrupt-cells = <2>;
                                         #size-cells = <1>;
                                         #address-cells = <2>;
-                                        reg = <f000 0 0 0 0>;
-                                        ranges = <1 0 01000000 0 0
-                                                  00001000>;
+                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                        ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                                  0x1000>;
                                         interrupt-parent = <&i8259>;
 
                                         i8259: interrupt-controller@20 {
-                                                reg = <1 20 2
-                                                       1 a0 2
-                                                       1 4d0 2>;
+                                                reg = <0x1 0x20 0x2
+                                                       0x1 0xa0 0x2
+                                                       0x1 0x4d0 0x2>;
                                                 interrupt-controller;
                                                 device_type = "interrupt-controller";
                                                 #address-cells = <0>;
@@ -412,29 +413,29 @@
                                         i8042@60 {
                                                 #size-cells = <0>;
                                                 #address-cells = <1>;
-                                                reg = <1 60 1 1 64 1>;
-                                                interrupts = <1 3 c 3>;
+                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                                interrupts = <1 3 12 3>;
                                                 interrupt-parent =
                                                         <&i8259>;
 
                                                 keyboard@0 {
-                                                        reg = <0>;
+                                                        reg = <0x0>;
                                                         compatible = "pnpPNP,303";
                                                 };
 
                                                 mouse@1 {
-                                                        reg = <1>;
+                                                        reg = <0x1>;
                                                         compatible = "pnpPNP,f03";
                                                 };
                                         };
 
                                         rtc@70 {
                                                 compatible = "pnpPNP,b00";
-                                                reg = <1 70 2>;
+                                                reg = <0x1 0x70 0x2>;
                                         };
 
                                         gpio@400 {
-                                                reg = <1 400 80>;
+                                                reg = <0x1 0x400 0x80>;
                                         };
                                 };
                         };
@@ -449,33 +450,33 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <ffe09000 1000>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 a0000000 a0000000 0 20000000
-                          01000000 0 00000000 ffc10000 0 00010000>;
-                clock-frequency = <1fca055>;
+                reg = <0xffe09000 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
+                clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <1a 2>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupts = <26 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 4 1
-                        0000 0 0 2 &mpic 5 1
-                        0000 0 0 3 &mpic 6 1
-                        0000 0 0 4 &mpic 7 1
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
                         >;
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 a0000000
-                                  02000000 0 a0000000
-                                  0 20000000
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00100000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
                 };
         };
 
@@ -486,33 +487,33 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <ffe0a000 1000>;
-                bus-range = <0 ff>;
-                ranges = <02000000 0 c0000000 c0000000 0 20000000
-                          01000000 0 00000000 ffc20000 0 00010000>;
-                clock-frequency = <1fca055>;
+                reg = <0xffe0a000 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
+                clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
-                interrupts = <1b 2>;
-                interrupt-map-mask = <f800 0 0 7>;
+                interrupts = <27 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                         /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 0 1
-                        0000 0 0 2 &mpic 1 1
-                        0000 0 0 3 &mpic 2 1
-                        0000 0 0 4 &mpic 3 1
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
                         >;
                 pcie@0 {
-                        reg = <0 0 0 0 0>;
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
                         #size-cells = <2>;
                         #address-cells = <3>;
                         device_type = "pci";
-                        ranges = <02000000 0 c0000000
-                                  02000000 0 c0000000
-                                  0 20000000
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
 
-                                  01000000 0 00000000
-                                  01000000 0 00000000
-                                  0 00100000>;
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
                 };
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 79385bcd5c5f..7f9b999843ce 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -13,7 +13,7 @@
 
 / {
         model = "MPC8641HPCN";
-        compatible = "mpc86xx";
+        compatible = "fsl,mpc8641hpcn";
         #address-cells = <1>;
         #size-cells = <1>;
 
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index daf9433e906b..765e43c997da 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -2,6 +2,7 @@
  * MPC866 ADS Device Tree Source
  *
  * Copyright 2006 MontaVista Software, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "MPC866ADS";
@@ -22,37 +24,37 @@
 
                 PowerPC,866@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <10>;       // 16 bytes
-                        i-cache-line-size = <10>;       // 16 bytes
-                        d-cache-size = <2000>;          // L1, 8K
-                        i-cache-size = <4000>;          // L1, 16K
+                        reg = <0x0>;
+                        d-cache-line-size = <16>;       // 16 bytes
+                        i-cache-line-size = <16>;       // 16 bytes
+                        d-cache-size = <0x2000>;                // L1, 8K
+                        i-cache-size = <0x4000>;                // L1, 16K
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
-                        interrupts = <f 2>;     // decrementer interrupt
+                        interrupts = <15 2>;    // decrementer interrupt
                         interrupt-parent = <&PIC>;
                 };
         };
 
         memory {
                 device_type = "memory";
-                reg = <00000000 800000>;
+                reg = <0x0 0x800000>;
         };
 
         localbus@ff000100 {
                 compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
                 #address-cells = <2>;
                 #size-cells = <1>;
-                reg = <ff000100 40>;
+                reg = <0xff000100 0x40>;
 
                 ranges = <
-                        1 0 ff080000 00008000
-                        5 0 ff0a0000 00008000
+                        0x1 0x0 0xff080000 0x8000
+                        0x5 0x0 0xff0a0000 0x8000
                 >;
 
                 board-control@1,0 {
-                        reg = <1 0 20 5 300 4>;
+                        reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
                         compatible = "fsl,mpc866ads-bcsr";
                 };
         };
@@ -61,17 +63,17 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 ff000000 00100000>;
-                reg = <ff000000 00000200>;
+                ranges = <0x0 0xff000000 0x100000>;
+                reg = <0xff000000 0x200>;
                 bus-frequency = <0>;
 
                 mdio@e00 {
                         compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
-                        reg = <e00 188>;
+                        reg = <0xe00 0x188>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         PHY: ethernet-phy@f {
-                                reg = <f>;
+                                reg = <0xf>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -80,7 +82,7 @@
                         device_type = "network";
                         compatible = "fsl,mpc866-fec-enet",
                                      "fsl,pq1-fec-enet";
-                        reg = <e00 188>;
+                        reg = <0xe00 0x188>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <3 1>;
                         interrupt-parent = <&PIC>;
@@ -91,7 +93,7 @@
                 PIC: pic@0 {
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        reg = <0 24>;
+                        reg = <0x0 0x24>;
                         compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
                 };
 
@@ -100,7 +102,7 @@
                         #size-cells = <1>;
                         compatible = "fsl,mpc866-cpm", "fsl,cpm1";
                         ranges;
-                        reg = <9c0 40>;
+                        reg = <0x9c0 0x40>;
                         brg-frequency = <0>;
                         interrupts = <0 2>;     // cpm error interrupt
                         interrupt-parent = <&CPM_PIC>;
@@ -108,11 +110,11 @@
                         muram@2000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 2000 2000>;
+                                ranges = <0x0 0x2000 0x2000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 1c00>;
+                                        reg = <0x0 0x1c00>;
                                 };
                         };
 
@@ -120,7 +122,7 @@
                                 compatible = "fsl,mpc866-brg",
                                              "fsl,cpm1-brg",
                                              "fsl,cpm-brg";
-                                reg = <9f0 10>;
+                                reg = <0x9f0 0x10>;
                                 clock-frequency = <0>;
                         };
 
@@ -130,7 +132,7 @@
                                 #interrupt-cells = <1>;
                                 interrupts = <5 2 0 2>;
                                 interrupt-parent = <&PIC>;
-                                reg = <930 20>;
+                                reg = <0x930 0x20>;
                                 compatible = "fsl,mpc866-cpm-pic",
                                              "fsl,cpm1-pic";
                         };
@@ -140,31 +142,31 @@
                                 device_type = "serial";
                                 compatible = "fsl,mpc866-smc-uart",
                                              "fsl,cpm1-smc-uart";
-                                reg = <a80 10 3e80 40>;
+                                reg = <0xa80 0x10 0x3e80 0x40>;
                                 interrupts = <4>;
                                 interrupt-parent = <&CPM_PIC>;
                                 fsl,cpm-brg = <1>;
-                                fsl,cpm-command = <0090>;
+                                fsl,cpm-command = <0x90>;
                         };
 
                         serial@a90 {
                                 device_type = "serial";
                                 compatible = "fsl,mpc866-smc-uart",
                                              "fsl,cpm1-smc-uart";
-                                reg = <a90 10 3f80 40>;
+                                reg = <0xa90 0x10 0x3f80 0x40>;
                                 interrupts = <3>;
                                 interrupt-parent = <&CPM_PIC>;
                                 fsl,cpm-brg = <2>;
-                                fsl,cpm-command = <00d0>;
+                                fsl,cpm-command = <0xd0>;
                         };
 
                         ethernet@a00 {
                                 device_type = "network";
                                 compatible = "fsl,mpc866-scc-enet",
                                              "fsl,cpm1-scc-enet";
-                                reg = <a00 18 3c00 100>;
+                                reg = <0xa00 0x18 0x3c00 0x100>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
-                                interrupts = <1e>;
+                                interrupts = <30>;
                                 interrupt-parent = <&CPM_PIC>;
                                 fsl,cpm-command = <0000>;
                                 linux,network-index = <1>;
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index d84a012c2aaf..9895043722b9 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -2,7 +2,7 @@
  * MPC885 ADS Device Tree Source
  *
  * Copyright 2006 MontaVista Software, Inc.
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2008 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -10,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
         model = "MPC885ADS";
@@ -23,45 +24,45 @@
 
                 PowerPC,885@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <d#16>;
-                        i-cache-line-size = <d#16>;
-                        d-cache-size = <d#8192>;
-                        i-cache-size = <d#8192>;
+                        reg = <0x0>;
+                        d-cache-line-size = <16>;
+                        i-cache-line-size = <16>;
+                        d-cache-size = <8192>;
+                        i-cache-size = <8192>;
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
-                        interrupts = <f 2>;     // decrementer interrupt
+                        interrupts = <15 2>;    // decrementer interrupt
                         interrupt-parent = <&PIC>;
                 };
         };
 
         memory {
                 device_type = "memory";
-                reg = <0 0>;
+                reg = <0x0 0x0>;
         };
 
         localbus@ff000100 {
                 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
                 #address-cells = <2>;
                 #size-cells = <1>;
-                reg = <ff000100 40>;
+                reg = <0xff000100 0x40>;
 
                 ranges = <
-                        0 0 fe000000 00800000
-                        1 0 ff080000 00008000
-                        5 0 ff0a0000 00008000
+                        0x0 0x0 0xfe000000 0x800000
+                        0x1 0x0 0xff080000 0x8000
+                        0x5 0x0 0xff0a0000 0x8000
                 >;
 
                 flash@0,0 {
                         compatible = "jedec-flash";
-                        reg = <0 0 800000>;
+                        reg = <0x0 0x0 0x800000>;
                         bank-width = <4>;
                         device-width = <1>;
                 };
 
                 board-control@1,0 {
-                        reg = <1 0 20 5 300 4>;
+                        reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
                         compatible = "fsl,mpc885ads-bcsr";
                 };
         };
@@ -71,30 +72,30 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
-                ranges = <0 ff000000 00004000>;
+                ranges = <0x0 0xff000000 0x4000>;
                 bus-frequency = <0>;
 
                 // Temporary -- will go away once kernel uses ranges for get_immrbase().
-                reg = <ff000000 4000>;
+                reg = <0xff000000 0x4000>;
 
                 mdio@e00 {
                         compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
-                        reg = <e00 188>;
+                        reg = <0xe00 0x188>;
                         #address-cells = <1>;
                         #size-cells = <0>;
 
                         PHY0: ethernet-phy@0 {
-                                reg = <0>;
+                                reg = <0x0>;
                                 device_type = "ethernet-phy";
                         };
 
                         PHY1: ethernet-phy@1 {
-                                reg = <1>;
+                                reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
 
                         PHY2: ethernet-phy@2 {
-                                reg = <2>;
+                                reg = <0x2>;
                                 device_type = "ethernet-phy";
                         };
                 };
@@ -103,7 +104,7 @@
                         device_type = "network";
                         compatible = "fsl,mpc885-fec-enet",
                                      "fsl,pq1-fec-enet";
-                        reg = <e00 188>;
+                        reg = <0xe00 0x188>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <3 1>;
                         interrupt-parent = <&PIC>;
@@ -115,7 +116,7 @@
                         device_type = "network";
                         compatible = "fsl,mpc885-fec-enet",
                                      "fsl,pq1-fec-enet";
-                        reg = <1e00 188>;
+                        reg = <0x1e00 0x188>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <7 1>;
                         interrupt-parent = <&PIC>;
@@ -126,7 +127,7 @@
                 PIC: interrupt-controller@0 {
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        reg = <0 24>;
+                        reg = <0x0 0x24>;
                         compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
                 };
 
@@ -136,29 +137,29 @@
                         #size-cells = <2>;
                         compatible = "fsl,pq-pcmcia";
                         device_type = "pcmcia";
-                        reg = <80 80>;
+                        reg = <0x80 0x80>;
                         interrupt-parent = <&PIC>;
-                        interrupts = <d 1>;
+                        interrupts = <13 1>;
                 };
 
                 cpm@9c0 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "fsl,mpc885-cpm", "fsl,cpm1";
-                        command-proc = <9c0>;
+                        command-proc = <0x9c0>;
                         interrupts = <0>;       // cpm error interrupt
                         interrupt-parent = <&CPM_PIC>;
-                        reg = <9c0 40>;
+                        reg = <0x9c0 0x40>;
                         ranges;
 
                         muram@2000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 2000 2000>;
+                                ranges = <0x0 0x2000 0x2000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 1c00>;
+                                        reg = <0x0 0x1c00>;
                                 };
                         };
 
@@ -167,7 +168,7 @@
                                              "fsl,cpm1-brg",
                                              "fsl,cpm-brg";
                                 clock-frequency = <0>;
-                                reg = <9f0 10>;
+                                reg = <0x9f0 0x10>;
                         };
 
                         CPM_PIC: interrupt-controller@930 {
@@ -175,7 +176,7 @@
                                 #interrupt-cells = <1>;
                                 interrupts = <5 2 0 2>;
                                 interrupt-parent = <&PIC>;
-                                reg = <930 20>;
+                                reg = <0x930 0x20>;
                                 compatible = "fsl,mpc885-cpm-pic",
                                              "fsl,cpm1-pic";
                         };
@@ -184,34 +185,34 @@
                                 device_type = "serial";
                                 compatible = "fsl,mpc885-smc-uart",
                                              "fsl,cpm1-smc-uart";
-                                reg = <a80 10 3e80 40>;
+                                reg = <0xa80 0x10 0x3e80 0x40>;
                                 interrupts = <4>;
                                 interrupt-parent = <&CPM_PIC>;
                                 fsl,cpm-brg = <1>;
-                                fsl,cpm-command = <0090>;
+                                fsl,cpm-command = <0x90>;
                         };
 
                         serial@a90 {
                                 device_type = "serial";
                                 compatible = "fsl,mpc885-smc-uart",
                                              "fsl,cpm1-smc-uart";
-                                reg = <a90 10 3f80 40>;
+                                reg = <0xa90 0x10 0x3f80 0x40>;
                                 interrupts = <3>;
                                 interrupt-parent = <&CPM_PIC>;
                                 fsl,cpm-brg = <2>;
-                                fsl,cpm-command = <00d0>;
+                                fsl,cpm-command = <0xd0>;
                         };
 
                         ethernet@a40 {
                                 device_type = "network";
                                 compatible = "fsl,mpc885-scc-enet",
                                              "fsl,cpm1-scc-enet";
-                                reg = <a40 18 3e00 100>;
+                                reg = <0xa40 0x18 0x3e00 0x100>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
-                                interrupts = <1c>;
+                                interrupts = <28>;
                                 interrupt-parent = <&CPM_PIC>;
                                 phy-handle = <&PHY2>;
-                                fsl,cpm-command = <0080>;
+                                fsl,cpm-command = <0x80>;
                                 linux,network-index = <2>;
                         };
                 };
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
index 2d564921897a..b2d61091b36d 100644
--- a/arch/powerpc/boot/dts/pq2fads.dts
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -1,7 +1,7 @@
 /*
  * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007,2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,8 @@
  * option) any later version.
  */
 
+/dts-v1/;
+
 / {
         model = "pq2fads";
         compatible = "fsl,pq2fads";
@@ -21,11 +23,11 @@
 
                 cpu@0 {
                         device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <d#32>;
-                        i-cache-line-size = <d#32>;
-                        d-cache-size = <d#16384>;
-                        i-cache-size = <d#16384>;
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <16384>;
+                        i-cache-size = <16384>;
                         timebase-frequency = <0>;
                         clock-frequency = <0>;
                 };
@@ -33,7 +35,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0 0>;
+                reg = <0x0 0x0>;
         };
 
         localbus@f0010100 {
@@ -41,67 +43,67 @@
                              "fsl,pq2-localbus";
                 #address-cells = <2>;
                 #size-cells = <1>;
-                reg = <f0010100 60>;
+                reg = <0xf0010100 0x60>;
 
-                ranges = <0 0 fe000000 00800000
-                          1 0 f4500000 00008000
-                          8 0 f8200000 00008000>;
+                ranges = <0x0 0x0 0xfe000000 0x800000
+                          0x1 0x0 0xf4500000 0x8000
+                          0x8 0x0 0xf8200000 0x8000>;
 
                 flash@0,0 {
                         compatible = "jedec-flash";
-                        reg = <0 0 800000>;
+                        reg = <0x0 0x0 0x800000>;
                         bank-width = <4>;
                         device-width = <1>;
                 };
 
                 bcsr@1,0 {
-                        reg = <1 0 20>;
+                        reg = <0x1 0x0 0x20>;
                         compatible = "fsl,pq2fads-bcsr";
                 };
 
                 PCI_PIC: pic@8,0 {
                         #interrupt-cells = <1>;
                         interrupt-controller;
-                        reg = <8 0 8>;
+                        reg = <0x8 0x0 0x8>;
                         compatible = "fsl,pq2ads-pci-pic";
                         interrupt-parent = <&PIC>;
-                        interrupts = <18 8>;
+                        interrupts = <24 8>;
                 };
         };
 
         pci@f0010800 {
                 device_type = "pci";
-                reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+                reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
                 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                clock-frequency = <d#66000000>;
-                interrupt-map-mask = <f800 0 0 7>;
+                clock-frequency = <66000000>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                 interrupt-map = <
                                 /* IDSEL 0x16 */
-                                 b000 0 0 1 &PCI_PIC 0
-                                 b000 0 0 2 &PCI_PIC 1
-                                 b000 0 0 3 &PCI_PIC 2
-                                 b000 0 0 4 &PCI_PIC 3
+                                 0xb000 0x0 0x0 0x1 &PCI_PIC 0
+                                 0xb000 0x0 0x0 0x2 &PCI_PIC 1
+                                 0xb000 0x0 0x0 0x3 &PCI_PIC 2
+                                 0xb000 0x0 0x0 0x4 &PCI_PIC 3
 
                                 /* IDSEL 0x17 */
-                                 b800 0 0 1 &PCI_PIC 4
-                                 b800 0 0 2 &PCI_PIC 5
-                                 b800 0 0 3 &PCI_PIC 6
-                                 b800 0 0 4 &PCI_PIC 7
+                                 0xb800 0x0 0x0 0x1 &PCI_PIC 4
+                                 0xb800 0x0 0x0 0x2 &PCI_PIC 5
+                                 0xb800 0x0 0x0 0x3 &PCI_PIC 6
+                                 0xb800 0x0 0x0 0x4 &PCI_PIC 7
 
                                 /* IDSEL 0x18 */
-                                 c000 0 0 1 &PCI_PIC 8
-                                 c000 0 0 2 &PCI_PIC 9
-                                 c000 0 0 3 &PCI_PIC a
-                                 c000 0 0 4 &PCI_PIC b>;
+                                 0xc000 0x0 0x0 0x1 &PCI_PIC 8
+                                 0xc000 0x0 0x0 0x2 &PCI_PIC 9
+                                 0xc000 0x0 0x0 0x3 &PCI_PIC 10
+                                 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
 
                 interrupt-parent = <&PIC>;
-                interrupts = <12 8>;
-                ranges = <42000000 0 80000000 80000000 0 20000000
-                          02000000 0 a0000000 a0000000 0 20000000
-                          01000000 0 00000000 f6000000 0 02000000>;
+                interrupts = <18 8>;
+                ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
         };
 
         soc@f0000000 {
@@ -109,27 +111,27 @@
                 #size-cells = <1>;
                 device_type = "soc";
                 compatible = "fsl,mpc8280", "fsl,pq2-soc";
-                ranges = <00000000 f0000000 00053000>;
+                ranges = <0x0 0xf0000000 0x53000>;
 
                 // Temporary -- will go away once kernel uses ranges for get_immrbase().
-                reg = <f0000000 00053000>;
+                reg = <0xf0000000 0x53000>;
 
                 cpm@119c0 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         #interrupt-cells = <2>;
                         compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
-                        reg = <119c0 30>;
+                        reg = <0x119c0 0x30>;
                         ranges;
 
                         muram@0 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 0 10000>;
+                                ranges = <0x0 0x0 0x10000>;
 
                                 data@0 {
                                         compatible = "fsl,cpm-muram-data";
-                                        reg = <0 2000 9800 800>;
+                                        reg = <0x0 0x2000 0x9800 0x800>;
                                 };
                         };
 
@@ -137,53 +139,53 @@
                                 compatible = "fsl,mpc8280-brg",
                                              "fsl,cpm2-brg",
                                              "fsl,cpm-brg";
-                                reg = <119f0 10 115f0 10>;
+                                reg = <0x119f0 0x10 0x115f0 0x10>;
                         };
 
                         serial@11a00 {
                                 device_type = "serial";
                                 compatible = "fsl,mpc8280-scc-uart",
                                              "fsl,cpm2-scc-uart";
-                                reg = <11a00 20 8000 100>;
-                                interrupts = <28 8>;
+                                reg = <0x11a00 0x20 0x8000 0x100>;
+                                interrupts = <40 8>;
                                 interrupt-parent = <&PIC>;
                                 fsl,cpm-brg = <1>;
-                                fsl,cpm-command = <00800000>;
+                                fsl,cpm-command = <0x800000>;
                         };
 
                         serial@11a20 {
                                 device_type = "serial";
                                 compatible = "fsl,mpc8280-scc-uart",
                                              "fsl,cpm2-scc-uart";
-                                reg = <11a20 20 8100 100>;
-                                interrupts = <29 8>;
+                                reg = <0x11a20 0x20 0x8100 0x100>;
+                                interrupts = <41 8>;
                                 interrupt-parent = <&PIC>;
                                 fsl,cpm-brg = <2>;
-                                fsl,cpm-command = <04a00000>;
+                                fsl,cpm-command = <0x4a00000>;
                         };
 
                         ethernet@11320 {
                                 device_type = "network";
                                 compatible = "fsl,mpc8280-fcc-enet",
                                              "fsl,cpm2-fcc-enet";
-                                reg = <11320 20 8500 100 113b0 1>;
-                                interrupts = <21 8>;
+                                reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
+                                interrupts = <33 8>;
                                 interrupt-parent = <&PIC>;
                                 phy-handle = <&PHY0>;
                                 linux,network-index = <0>;
-                                fsl,cpm-command = <16200300>;
+                                fsl,cpm-command = <0x16200300>;
                         };
 
                         ethernet@11340 {
                                 device_type = "network";
                                 compatible = "fsl,mpc8280-fcc-enet",
                                              "fsl,cpm2-fcc-enet";
-                                reg = <11340 20 8600 100 113d0 1>;
-                                interrupts = <22 8>;
+                                reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
+                                interrupts = <34 8>;
                                 interrupt-parent = <&PIC>;
                                 phy-handle = <&PHY1>;
                                 linux,network-index = <1>;
-                                fsl,cpm-command = <1a400300>;
+                                fsl,cpm-command = <0x1a400300>;
                                 local-mac-address = [00 e0 0c 00 79 01];
                         };
 
@@ -194,21 +196,21 @@
                                              "fsl,cpm2-mdio-bitbang";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                reg = <10d40 14>;
+                                reg = <0x10d40 0x14>;
                                 fsl,mdio-pin = <9>;
-                                fsl,mdc-pin = <a>;
+                                fsl,mdc-pin = <10>;
 
                                 PHY0: ethernet-phy@0 {
                                         interrupt-parent = <&PIC>;
-                                        interrupts = <19 2>;
-                                        reg = <0>;
+                                        interrupts = <25 2>;
+                                        reg = <0x0>;
                                         device_type = "ethernet-phy";
                                 };
 
                                 PHY1: ethernet-phy@1 {
                                         interrupt-parent = <&PIC>;
-                                        interrupts = <19 2>;
-                                        reg = <3>;
+                                        interrupts = <25 2>;
+                                        reg = <0x3>;
                                         device_type = "ethernet-phy";
                                 };
                         };
@@ -218,17 +220,17 @@
                                 #size-cells = <0>;
                                 compatible = "fsl,mpc8280-usb",
                                              "fsl,cpm2-usb";
-                                reg = <11b60 18 8b00 100>;
+                                reg = <0x11b60 0x18 0x8b00 0x100>;
                                 interrupt-parent = <&PIC>;
-                                interrupts = <b 8>;
-                                fsl,cpm-command = <2e600000>;
+                                interrupts = <11 8>;
+                                fsl,cpm-command = <0x2e600000>;
                         };
                 };
 
                 PIC: interrupt-controller@10c00 {
                         #interrupt-cells = <2>;
                         interrupt-controller;
-                        reg = <10c00 80>;
+                        reg = <0x10c00 0x80>;
                         compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
                 };
 
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 297dfa53fe9e..1ee6ff43dd57 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -11,6 +11,8 @@
  * if it can determine the exact PrPMC type.
  */
 
+/dts-v1/;
+
 / {
         #address-cells = <1>;
         #size-cells = <1>;
@@ -25,46 +27,46 @@
                 PowerPC,7447 {
                         device_type = "cpu";
                         reg = <0>;
-                        clock-frequency = <2bb0b140>;   /* Default (733 MHz) */
-                        bus-frequency = <7f28155>;      /* 133.333333 MHz */
-                        timebase-frequency = <1fca055>; /* 33.333333 MHz */
-                        i-cache-line-size = <20>;
-                        d-cache-line-size = <20>;
-                        i-cache-size = <8000>;
-                        d-cache-size = <8000>;
+                        clock-frequency = <733333333>;  /* Default */
+                        bus-frequency = <133333333>;
+                        timebase-frequency = <33333333>;
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
                 };
         };
 
         memory {
                 device_type = "memory";
-                reg = <00000000 20000000>;      /* Default (512MB) */
+                reg = <0x0 0x20000000>;                 /* Default (512MB) */
         };
 
-        mv64x60@f1000000 { /* Marvell Discovery */
+        system-controller@f1000000 { /* Marvell Discovery mv64360 */
                 #address-cells = <1>;
                 #size-cells = <1>;
                 model = "mv64360";                      /* Default */
-                compatible = "marvell,mv64x60";
-                clock-frequency = <7f28155>;            /* 133.333333 MHz */
-                reg = <f1000000 00010000>;
-                virtual-reg = <f1000000>;
-                ranges = <88000000 88000000 01000000    /* PCI 0 I/O Space */
-                          80000000 80000000 08000000    /* PCI 0 MEM Space */
-                          a0000000 a0000000 04000000    /* User FLASH */
-                          00000000 f1000000 00010000    /* Bridge's regs */
-                          f2000000 f2000000 00040000>;  /* Integrated SRAM */
+                compatible = "marvell,mv64360";
+                clock-frequency = <133333333>;
+                reg = <0xf1000000 0x10000>;
+                virtual-reg = <0xf1000000>;
+                ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
+                          0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
+                          0xa0000000 0xa0000000 0x4000000 /* User FLASH */
+                          0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
+                          0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
 
                 flash@a0000000 {
                         device_type = "rom";
                         compatible = "direct-mapped";
-                        reg = <a0000000 4000000>; /* Default (64MB) */
+                        reg = <0xa0000000 0x4000000>; /* Default (64MB) */
                         probe-type = "CFI";
                         bank-width = <4>;
-                        partitions = <00000000 00100000 /* RO */
-                                      00100000 00040001 /* RW */
-                                      00140000 00400000 /* RO */
-                                      00540000 039c0000 /* RO */
-                                      03f00000 00100000>; /* RO */
+                        partitions = <0x00000000 0x00100000 /* RO */
+                                      0x00100000 0x00040001 /* RW */
+                                      0x00140000 0x00400000 /* RO */
+                                      0x00540000 0x039c0000 /* RO */
+                                      0x03f00000 0x00100000>; /* RO */
                         partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
                 };
 
@@ -72,171 +74,153 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         device_type = "mdio";
-                        compatible = "marvell,mv64x60-mdio";
-                        ethernet-phy@1 {
+                        compatible = "marvell,mv64360-mdio";
+                        PHY0: ethernet-phy@1 {
                                 device_type = "ethernet-phy";
                                 compatible = "broadcom,bcm5421";
-                                interrupts = <4c>;      /* GPP 12 */
-                                interrupt-parent = <&/mv64x60/pic>;
+                                interrupts = <76>;      /* GPP 12 */
+                                interrupt-parent = <&PIC>;
                                 reg = <1>;
                         };
-                        ethernet-phy@3 {
+                        PHY1: ethernet-phy@3 {
                                 device_type = "ethernet-phy";
                                 compatible = "broadcom,bcm5421";
-                                interrupts = <4c>;      /* GPP 12 */
-                                interrupt-parent = <&/mv64x60/pic>;
+                                interrupts = <76>;      /* GPP 12 */
+                                interrupt-parent = <&PIC>;
                                 reg = <3>;
                         };
                 };
 
-                ethernet@2000 {
-                        reg = <2000 2000>;
-                        eth0 {
+                ethernet-group@2000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "marvell,mv64360-eth-group";
+                        reg = <0x2000 0x2000>;
+                        ethernet@0 {
                                 device_type = "network";
-                                compatible = "marvell,mv64x60-eth";
-                                block-index = <0>;
-                                interrupts = <20>;
-                                interrupt-parent = <&/mv64x60/pic>;
-                                phy = <&/mv64x60/mdio/ethernet-phy@1>;
+                                compatible = "marvell,mv64360-eth";
+                                reg = <0>;
+                                interrupts = <32>;
+                                interrupt-parent = <&PIC>;
+                                phy = <&PHY0>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
                         };
-                        eth1 {
+                        ethernet@1 {
                                 device_type = "network";
-                                compatible = "marvell,mv64x60-eth";
-                                block-index = <1>;
-                                interrupts = <21>;
-                                interrupt-parent = <&/mv64x60/pic>;
-                                phy = <&/mv64x60/mdio/ethernet-phy@3>;
+                                compatible = "marvell,mv64360-eth";
+                                reg = <1>;
+                                interrupts = <33>;
+                                interrupt-parent = <&PIC>;
+                                phy = <&PHY1>;
                                 local-mac-address = [ 00 00 00 00 00 00 ];
                         };
                 };
 
-                sdma@4000 {
-                        device_type = "dma";
-                        compatible = "marvell,mv64x60-sdma";
-                        reg = <4000 c18>;
-                        virtual-reg = <f1004000>;
-                        interrupt-base = <0>;
-                        interrupts = <24>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                SDMA0: sdma@4000 {
+                        compatible = "marvell,mv64360-sdma";
+                        reg = <0x4000 0xc18>;
+                        virtual-reg = <0xf1004000>;
+                        interrupts = <36>;
+                        interrupt-parent = <&PIC>;
                 };
 
-                sdma@6000 {
-                        device_type = "dma";
-                        compatible = "marvell,mv64x60-sdma";
-                        reg = <6000 c18>;
-                        virtual-reg = <f1006000>;
-                        interrupt-base = <0>;
-                        interrupts = <26>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                SDMA1: sdma@6000 {
+                        compatible = "marvell,mv64360-sdma";
+                        reg = <0x6000 0xc18>;
+                        virtual-reg = <0xf1006000>;
+                        interrupts = <38>;
+                        interrupt-parent = <&PIC>;
                 };
 
-                brg@b200 {
-                        compatible = "marvell,mv64x60-brg";
-                        reg = <b200 8>;
+                BRG0: brg@b200 {
+                        compatible = "marvell,mv64360-brg";
+                        reg = <0xb200 0x8>;
                         clock-src = <8>;
-                        clock-frequency = <7ed6b40>;
-                        current-speed = <2580>;
-                        bcr = <0>;
+                        clock-frequency = <133333333>;
+                        current-speed = <9600>;
                 };
 
-                brg@b208 {
-                        compatible = "marvell,mv64x60-brg";
-                        reg = <b208 8>;
+                BRG1: brg@b208 {
+                        compatible = "marvell,mv64360-brg";
+                        reg = <0xb208 0x8>;
                         clock-src = <8>;
-                        clock-frequency = <7ed6b40>;
-                        current-speed = <2580>;
-                        bcr = <0>;
+                        clock-frequency = <133333333>;
+                        current-speed = <9600>;
                 };
 
-                cunit@f200 {
-                        reg = <f200 200>;
+                CUNIT: cunit@f200 {
+                        reg = <0xf200 0x200>;
                 };
 
-                mpscrouting@b400 {
-                        reg = <b400 c>;
+                MPSCROUTING: mpscrouting@b400 {
+                        reg = <0xb400 0xc>;
                 };
 
-                mpscintr@b800 {
-                        reg = <b800 100>;
-                        virtual-reg = <f100b800>;
+                MPSCINTR: mpscintr@b800 {
+                        reg = <0xb800 0x100>;
+                        virtual-reg = <0xf100b800>;
                 };
 
-                mpsc@8000 {
+                MPSC0: mpsc@8000 {
                         device_type = "serial";
-                        compatible = "marvell,mpsc";
-                        reg = <8000 38>;
-                        virtual-reg = <f1008000>;
-                        sdma = <&/mv64x60/sdma@4000>;
-                        brg = <&/mv64x60/brg@b200>;
-                        cunit = <&/mv64x60/cunit@f200>;
-                        mpscrouting = <&/mv64x60/mpscrouting@b400>;
-                        mpscintr = <&/mv64x60/mpscintr@b800>;
-                        block-index = <0>;
-                        max_idle = <28>;
-                        chr_1 = <0>;
-                        chr_2 = <0>;
-                        chr_10 = <3>;
-                        mpcr = <0>;
-                        interrupts = <28>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                        compatible = "marvell,mv64360-mpsc";
+                        reg = <0x8000 0x38>;
+                        virtual-reg = <0xf1008000>;
+                        sdma = <&SDMA0>;
+                        brg = <&BRG0>;
+                        cunit = <&CUNIT>;
+                        mpscrouting = <&MPSCROUTING>;
+                        mpscintr = <&MPSCINTR>;
+                        cell-index = <0>;
+                        interrupts = <40>;
+                        interrupt-parent = <&PIC>;
                 };
 
-                mpsc@9000 {
+                MPSC1: mpsc@9000 {
                         device_type = "serial";
-                        compatible = "marvell,mpsc";
-                        reg = <9000 38>;
-                        virtual-reg = <f1009000>;
-                        sdma = <&/mv64x60/sdma@6000>;
-                        brg = <&/mv64x60/brg@b208>;
-                        cunit = <&/mv64x60/cunit@f200>;
-                        mpscrouting = <&/mv64x60/mpscrouting@b400>;
-                        mpscintr = <&/mv64x60/mpscintr@b800>;
-                        block-index = <1>;
-                        max_idle = <28>;
-                        chr_1 = <0>;
-                        chr_2 = <0>;
-                        chr_10 = <3>;
-                        mpcr = <0>;
-                        interrupts = <2a>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                        compatible = "marvell,mv64360-mpsc";
+                        reg = <0x9000 0x38>;
+                        virtual-reg = <0xf1009000>;
+                        sdma = <&SDMA1>;
+                        brg = <&BRG1>;
+                        cunit = <&CUNIT>;
+                        mpscrouting = <&MPSCROUTING>;
+                        mpscintr = <&MPSCINTR>;
+                        cell-index = <1>;
+                        interrupts = <42>;
+                        interrupt-parent = <&PIC>;
                 };
 
                 wdt@b410 {                      /* watchdog timer */
-                        compatible = "marvell,mv64x60-wdt";
-                        reg = <b410 8>;
-                        timeout = <a>;          /* wdt timeout in seconds */
+                        compatible = "marvell,mv64360-wdt";
+                        reg = <0xb410 0x8>;
                 };
 
                 i2c@c000 {
                         device_type = "i2c";
-                        compatible = "marvell,mv64x60-i2c";
-                        reg = <c000 20>;
-                        virtual-reg = <f100c000>;
-                        freq_m = <8>;
-                        freq_n = <3>;
-                        timeout = <3e8>;                /* 1000 = 1 second */
-                        retries = <1>;
-                        interrupts = <25>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                        compatible = "marvell,mv64360-i2c";
+                        reg = <0xc000 0x20>;
+                        virtual-reg = <0xf100c000>;
+                        interrupts = <37>;
+                        interrupt-parent = <&PIC>;
                 };
 
-                pic {
+                PIC: pic {
                         #interrupt-cells = <1>;
                         #address-cells = <0>;
-                        compatible = "marvell,mv64x60-pic";
-                        reg = <0000 88>;
+                        compatible = "marvell,mv64360-pic";
+                        reg = <0x0 0x88>;
                         interrupt-controller;
                 };
 
                 mpp@f000 {
-                        compatible = "marvell,mv64x60-mpp";
-                        reg = <f000 10>;
+                        compatible = "marvell,mv64360-mpp";
+                        reg = <0xf000 0x10>;
                 };
 
                 gpp@f100 {
-                        compatible = "marvell,mv64x60-gpp";
-                        reg = <f100 20>;
+                        compatible = "marvell,mv64360-gpp";
+                        reg = <0xf100 0x20>;
                 };
 
                 pci@80000000 {
@@ -244,73 +228,75 @@
                         #size-cells = <2>;
                         #interrupt-cells = <1>;
                         device_type = "pci";
-                        compatible = "marvell,mv64x60-pci";
-                        reg = <0cf8 8>;
-                        ranges = <01000000 0        0 88000000 0 01000000
-                                  02000000 0 80000000 80000000 0 08000000>;
-                        bus-range = <0 ff>;
-                        clock-frequency = <3EF1480>;
-                        interrupt-pci-iack = <0c34>;
-                        interrupt-parent = <&/mv64x60/pic>;
-                        interrupt-map-mask = <f800 0 0 7>;
+                        compatible = "marvell,mv64360-pci";
+                        reg = <0xcf8 0x8>;
+                        ranges = <0x01000000 0x0        0x0
+                                        0x88000000 0x0 0x01000000
+                                  0x02000000 0x0 0x80000000
+                                        0x80000000 0x0 0x08000000>;
+                        bus-range = <0 255>;
+                        clock-frequency = <66000000>;
+                        interrupt-pci-iack = <0xc34>;
+                        interrupt-parent = <&PIC>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                         interrupt-map = <
                                 /* IDSEL 0x0a */
-                                5000 0 0 1 &/mv64x60/pic 50
-                                5000 0 0 2 &/mv64x60/pic 51
-                                5000 0 0 3 &/mv64x60/pic 5b
-                                5000 0 0 4 &/mv64x60/pic 5d
+                                0x5000 0 0 1 &PIC 80
+                                0x5000 0 0 2 &PIC 81
+                                0x5000 0 0 3 &PIC 91
+                                0x5000 0 0 4 &PIC 93
 
                                 /* IDSEL 0x0b */
-                                5800 0 0 1 &/mv64x60/pic 5b
-                                5800 0 0 2 &/mv64x60/pic 5d
-                                5800 0 0 3 &/mv64x60/pic 50
-                                5800 0 0 4 &/mv64x60/pic 51
+                                0x5800 0 0 1 &PIC 91
+                                0x5800 0 0 2 &PIC 93
+                                0x5800 0 0 3 &PIC 80
+                                0x5800 0 0 4 &PIC 81
 
                                 /* IDSEL 0x0c */
-                                6000 0 0 1 &/mv64x60/pic 5b
-                                6000 0 0 2 &/mv64x60/pic 5d
-                                6000 0 0 3 &/mv64x60/pic 50
-                                6000 0 0 4 &/mv64x60/pic 51
+                                0x6000 0 0 1 &PIC 91
+                                0x6000 0 0 2 &PIC 93
+                                0x6000 0 0 3 &PIC 80
+                                0x6000 0 0 4 &PIC 81
 
                                 /* IDSEL 0x0d */
-                                6800 0 0 1 &/mv64x60/pic 5d
-                                6800 0 0 2 &/mv64x60/pic 50
-                                6800 0 0 3 &/mv64x60/pic 51
-                                6800 0 0 4 &/mv64x60/pic 5b
+                                0x6800 0 0 1 &PIC 93
+                                0x6800 0 0 2 &PIC 80
+                                0x6800 0 0 3 &PIC 81
+                                0x6800 0 0 4 &PIC 91
                         >;
                 };
 
                 cpu-error@0070 {
-                        compatible = "marvell,mv64x60-cpu-error";
-                        reg = <0070 10 0128 28>;
-                        interrupts = <03>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                        compatible = "marvell,mv64360-cpu-error";
+                        reg = <0x70 0x10 0x128 0x28>;
+                        interrupts = <3>;
+                        interrupt-parent = <&PIC>;
                 };
 
                 sram-ctrl@0380 {
-                        compatible = "marvell,mv64x60-sram-ctrl";
-                        reg = <0380 80>;
-                        interrupts = <0d>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                        compatible = "marvell,mv64360-sram-ctrl";
+                        reg = <0x380 0x80>;
+                        interrupts = <13>;
+                        interrupt-parent = <&PIC>;
                 };
 
                 pci-error@1d40 {
-                        compatible = "marvell,mv64x60-pci-error";
-                        reg = <1d40 40 0c28 4>;
-                        interrupts = <0c>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                        compatible = "marvell,mv64360-pci-error";
+                        reg = <0x1d40 0x40 0xc28 0x4>;
+                        interrupts = <12>;
+                        interrupt-parent = <&PIC>;
                 };
 
                 mem-ctrl@1400 {
-                        compatible = "marvell,mv64x60-mem-ctrl";
-                        reg = <1400 60>;
-                        interrupts = <11>;
-                        interrupt-parent = <&/mv64x60/pic>;
+                        compatible = "marvell,mv64360-mem-ctrl";
+                        reg = <0x1400 0x60>;
+                        interrupts = <17>;
+                        interrupt-parent = <&PIC>;
                 };
         };
 
         chosen {
                 bootargs = "ip=on";
-                linux,stdout-path = "/mv64x60@f1000000/mpsc@8000";
+                linux,stdout-path = &MPSC0;
         };
 };
diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts
index f947c75a2e94..6a8fa7089ea2 100644
--- a/arch/powerpc/boot/dts/rainier.dts
+++ b/arch/powerpc/boot/dts/rainier.dts
@@ -254,7 +254,6 @@
                         };
 
                         EMAC0: ethernet@ef600e00 {
-                                linux,network-index = <0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
                                 interrupt-parent = <&EMAC0>;
@@ -270,7 +269,7 @@
                                 mal-tx-channel = <0>;
                                 mal-rx-channel = <0>;
                                 cell-index = <0>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
@@ -284,7 +283,6 @@
                         };
 
                         EMAC1: ethernet@ef600f00 {
-                                linux,network-index = <1>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
                                 interrupt-parent = <&EMAC1>;
@@ -300,7 +298,7 @@
                                 mal-tx-channel = <1>;
                                 mal-rx-channel = <1>;
                                 cell-index = <1>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
new file mode 100644
index 000000000000..3eebeec157b3
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -0,0 +1,352 @@
+/*
+ * SBC8641D Device Tree Source
+ *
+ * Copyright 2008 Wind River Systems Inc.
+ *
+ * Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "SBC8641D";
+        compatible = "wind,sbc8641";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8641@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;         // L1
+                        i-cache-size = <32768>;         // L1
+                        timebase-frequency = <0>;       // From uboot
+                        bus-frequency = <0>;            // From uboot
+                        clock-frequency = <0>;          // From uboot
+                };
+                PowerPC,8641@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        timebase-frequency = <0>;       // From uboot
+                        bus-frequency = <0>;            // From uboot
+                        clock-frequency = <0>;          // From uboot
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;  // 512M at 0x0
+        };
+
+        localbus@f8005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8641-localbus", "simple-bus";
+                reg = <0xf8005000 0x1000>;
+                interrupts = <19 2>;
+                interrupt-parent = <&mpic>;
+
+                ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
+                          1 0 0xf0000000 0x00010000     // 64KB EEPROM
+                          2 0 0xf1000000 0x00100000     // EPLD (1MB)
+                          3 0 0xe0000000 0x04000000     // 64MB LB SDRAM (CS3)
+                          4 0 0xe4000000 0x04000000     // 64MB LB SDRAM (CS4)
+                          6 0 0xf4000000 0x00100000     // LCD display (1MB)
+                          7 0 0xe8000000 0x04000000>;   // 64MB OneNAND
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x01000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@0 {
+                                label = "dtb";
+                                reg = <0x00000000 0x00100000>;
+                                read-only;
+                        };
+                        partition@300000 {
+                                label = "kernel";
+                                reg = <0x00100000 0x00400000>;
+                                read-only;
+                        };
+                        partition@400000 {
+                                label = "fs";
+                                reg = <0x00500000 0x00a00000>;
+                        };
+                        partition@700000 {
+                                label = "firmware";
+                                reg = <0x00f00000 0x00100000>;
+                                read-only;
+                        };
+                };
+
+                epld@2,0 {
+                        compatible = "wrs,epld-localbus";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        reg = <2 0 0x100000>;
+                        ranges = <0 0 5 0 1     // User switches
+                                  1 0 5 1 1     // Board ID/Rev
+                                  3 0 5 3 1>;   // LEDs
+                };
+        };
+
+        soc@f8000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x00000000 0xf8000000 0x00100000>;
+                reg = <0xf8000000 0x00001000>;  // CCSRBAR
+                bus-frequency = <0>;
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                mdio@24520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-mdio";
+                        reg = <0x24520 0x20>;
+
+                        phy0: ethernet-phy@1f {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <0x1f>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy1: ethernet-phy@0 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <0>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy2: ethernet-phy@1 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <1>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy3: ethernet-phy@2 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <2>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+
+                enet0: ethernet@24000 {
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30  2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                enet1: ethernet@25000 {
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                enet2: ethernet@26000 {
+                        cell-index = <2>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy2>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                enet3: ethernet@27000 {
+                        cell-index = <3>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x27000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <37 2 38 2 39 2>;
+                        interrupt-parent = <&mpic>;
+                        phy-handle = <&phy3>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <28 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                mpic: pic@40000 {
+                        clock-frequency = <0>;
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                        big-endian;
+                };
+
+                global-utilities@e0000 {
+                        compatible = "fsl,mpc8641-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+
+        pci0: pcie@f8008000 {
+                cell-index = <0>;
+                compatible = "fsl,mpc8641-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf8008000 0x1000>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <24 2>;
+                interrupt-map-mask = <0xff00 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0x0000 0 0 1 &mpic 0 1
+                        0x0000 0 0 2 &mpic 1 1
+                        0x0000 0 0 3 &mpic 2 1
+                        0x0000 0 0 4 &mpic 3 1
+                        >;
+
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0x0 0x80000000
+                                  0x02000000 0x0 0x80000000
+                                  0x0 0x20000000
+
+                                  0x01000000 0x0 0x00000000
+                                  0x01000000 0x0 0x00000000
+                                  0x0 0x00100000>;
+                };
+
+        };
+
+        pci1: pcie@f8009000 {
+                cell-index = <1>;
+                compatible = "fsl,mpc8641-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf8009000 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0x0000 0 0 1 &mpic 4 1
+                        0x0000 0 0 2 &mpic 5 1
+                        0x0000 0 0 3 &mpic 6 1
+                        0x0000 0 0 4 &mpic 7 1
+                        >;
+
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0x0 0xa0000000
+                                  0x02000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x01000000 0x0 0x00000000
+                                  0x01000000 0x0 0x00000000
+                                  0x0 0x00100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 8db9515d7dc3..a1ae4d6ec990 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -269,7 +269,6 @@
                         };
 
                         EMAC0: ethernet@ef600e00 {
-                                linux,network-index = <0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440epx", "ibm,emac4";
                                 interrupt-parent = <&EMAC0>;
@@ -285,7 +284,7 @@
                                 mal-tx-channel = <0>;
                                 mal-rx-channel = <0>;
                                 cell-index = <0>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
@@ -299,7 +298,6 @@
                         };
 
                         EMAC1: ethernet@ef600f00 {
-                                linux,network-index = <1>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440epx", "ibm,emac4";
                                 interrupt-parent = <&EMAC1>;
@@ -315,7 +313,7 @@
                                 mal-tx-channel = <1>;
                                 mal-rx-channel = <1>;
                                 cell-index = <1>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 8278068c802c..e808e1c5593a 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -104,6 +104,16 @@
                 // FIXME: anything else?
         };
 
+        L2C0: l2c {
+                compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+                dcr-reg = <20 8                 /* Internal SRAM DCR's */
+                           30 8>;               /* L2 cache DCR's */
+                cache-line-size = <20>;         /* 32 bytes */
+                cache-size = <40000>;           /* L2, 256K */
+                interrupt-parent = <&UIC2>;
+                interrupts = <17 1>;
+        };
+
         plb {
                 compatible = "ibm,plb-440gx", "ibm,plb4";
                 #address-cells = <2>;
@@ -232,10 +242,18 @@
                                 reg = <40000790 8>;
                         };
 
+                        TAH0: emac-tah@40000b50 {
+                                compatible = "ibm,tah-440gx", "ibm,tah";
+                                reg = <40000b50 30>;
+                        };
+
+                        TAH1: emac-tah@40000d50 {
+                                compatible = "ibm,tah-440gx", "ibm,tah";
+                                reg = <40000d50 30>;
+                        };
 
                         EMAC0: ethernet@40000800 {
                                 unused = <1>;
-                                linux,network-index = <2>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440gx", "ibm,emac4";
                                 interrupt-parent = <&UIC1>;
@@ -256,7 +274,6 @@
                         };
                         EMAC1: ethernet@40000900 {
                                 unused = <1>;
-                                linux,network-index = <3>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440gx", "ibm,emac4";
                                 interrupt-parent = <&UIC1>;
@@ -277,7 +294,6 @@
                         };
 
                         EMAC2: ethernet@40000c00 {
-                                linux,network-index = <0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440gx", "ibm,emac4";
                                 interrupt-parent = <&UIC2>;
@@ -288,7 +304,7 @@
                                 mal-tx-channel = <2>;
                                 mal-rx-channel = <2>;
                                 cell-index = <2>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
@@ -297,10 +313,11 @@
                                 rgmii-channel = <0>;
                                 zmii-device = <&ZMII0>;
                                 zmii-channel = <2>;
+                                tah-device = <&TAH0>;
+                                tah-channel = <0>;
                         };
 
                         EMAC3: ethernet@40000e00 {
-                                linux,network-index = <1>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440gx", "ibm,emac4";
                                 interrupt-parent = <&UIC2>;
@@ -311,7 +328,7 @@
                                 mal-tx-channel = <3>;
                                 mal-rx-channel = <3>;
                                 cell-index = <3>;
-                                max-frame-size = <5dc>;
+                                max-frame-size = <2328>;
                                 rx-fifo-size = <1000>;
                                 tx-fifo-size = <800>;
                                 phy-mode = "rgmii";
@@ -320,6 +337,8 @@
                                 rgmii-channel = <1>;
                                 zmii-device = <&ZMII0>;
                                 zmii-channel = <3>;
+                                tah-device = <&TAH1>;
+                                tah-channel = <0>;
                         };
 
 
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
index dcc21b0438e5..a328607c8f84 100644
--- a/arch/powerpc/boot/dts/walnut.dts
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -125,7 +125,6 @@
                         };
 
                         EMAC: ethernet@ef600800 {
-                                linux,network-index = <0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-405gp", "ibm,emac";
                                 interrupt-parent = <&UIC0>;
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index dc1499d30f43..b04a52e22bf5 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -204,7 +204,6 @@
                         };
 
                         EMAC0: ethernet@ef600e00 {
-                                linux,network-index = <0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
                                 interrupt-parent = <&UIC1>;
diff --git a/arch/powerpc/boot/dts/yosemite.dts b/arch/powerpc/boot/dts/yosemite.dts
new file mode 100644
index 000000000000..0d6d332814e0
--- /dev/null
+++ b/arch/powerpc/boot/dts/yosemite.dts
@@ -0,0 +1,304 @@
+/*
+ * Device Tree Source for AMCC Yosemite
+ *
+ * Copyright 2008 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        model = "amcc,yosemite";
+        compatible = "amcc,yosemite","amcc,bamboo";
+        dcr-parent = <&/cpus/cpu@0>;
+
+        aliases {
+                ethernet0 = &EMAC0;
+                ethernet1 = &EMAC1;
+                serial0 = &UART0;
+                serial1 = &UART1;
+                serial2 = &UART2;
+                serial3 = &UART3;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,440EP";
+                        reg = <0>;
+                        clock-frequency = <0>; /* Filled in by zImage */
+                        timebase-frequency = <0>; /* Filled in by zImage */
+                        i-cache-line-size = <20>;
+                        d-cache-line-size = <20>;
+                        i-cache-size = <8000>;
+                        d-cache-size = <8000>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0>; /* Filled in by zImage */
+        };
+
+        UIC0: interrupt-controller0 {
+                compatible = "ibm,uic-440ep","ibm,uic";
+                interrupt-controller;
+                cell-index = <0>;
+                dcr-reg = <0c0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+        };
+
+        UIC1: interrupt-controller1 {
+                compatible = "ibm,uic-440ep","ibm,uic";
+                interrupt-controller;
+                cell-index = <1>;
+                dcr-reg = <0d0 009>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                interrupts = <1e 4 1f 4>; /* cascade */
+                interrupt-parent = <&UIC0>;
+        };
+
+        SDR0: sdr {
+                compatible = "ibm,sdr-440ep";
+                dcr-reg = <00e 002>;
+        };
+
+        CPR0: cpr {
+                compatible = "ibm,cpr-440ep";
+                dcr-reg = <00c 002>;
+        };
+
+        plb {
+                compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges;
+                clock-frequency = <0>; /* Filled in by zImage */
+
+                SDRAM0: sdram {
+                        compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
+                        dcr-reg = <010 2>;
+                };
+
+                DMA0: dma {
+                        compatible = "ibm,dma-440ep", "ibm,dma-440gp";
+                        dcr-reg = <100 027>;
+                };
+
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
+                        dcr-reg = <180 62>;
+                        num-tx-chans = <4>;
+                        num-rx-chans = <2>;
+                        interrupt-parent = <&MAL0>;
+                        interrupts = <0 1 2 3 4>;
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+                                        /*RXEOB*/ 1 &UIC0 b 4
+                                        /*SERR*/  2 &UIC1 0 4
+                                        /*TXDE*/  3 &UIC1 1 4
+                                        /*RXDE*/  4 &UIC1 2 4>;
+                };
+
+                POB0: opb {
+                        compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /* Bamboo is oddball in the 44x world and doesn't use the ERPN
+                         * bits.
+                         */
+                        ranges = <00000000 0 00000000 80000000
+                                  80000000 0 80000000 80000000>;
+                        interrupt-parent = <&UIC1>;
+                        interrupts = <7 4>;
+                        clock-frequency = <0>; /* Filled in by zImage */
+
+                        EBC0: ebc {
+                                compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
+                                dcr-reg = <012 2>;
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                clock-frequency = <0>; /* Filled in by zImage */
+                                interrupts = <5 1>;
+                                interrupt-parent = <&UIC1>;
+                        };
+
+                        UART0: serial@ef600300 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600300 8>;
+                                virtual-reg = <ef600300>;
+                                clock-frequency = <0>; /* Filled in by zImage */
+                                current-speed = <1c200>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0 4>;
+                        };
+
+                        UART1: serial@ef600400 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600400 8>;
+                                virtual-reg = <ef600400>;
+                                clock-frequency = <0>;
+                                current-speed = <0>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <1 4>;
+                        };
+
+                        UART2: serial@ef600500 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600500 8>;
+                                virtual-reg = <ef600500>;
+                                clock-frequency = <0>;
+                                current-speed = <0>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <3 4>;
+                                status = "disabled";
+                        };
+
+                        UART3: serial@ef600600 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <ef600600 8>;
+                                virtual-reg = <ef600600>;
+                                clock-frequency = <0>;
+                                current-speed = <0>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <4 4>;
+                                status = "disabled";
+                        };
+
+                        IIC0: i2c@ef600700 {
+                                compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+                                reg = <ef600700 14>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <2 4>;
+                        };
+
+                        IIC1: i2c@ef600800 {
+                                compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+                                reg = <ef600800 14>;
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <7 4>;
+                        };
+
+                        spi@ef600900 {
+                                compatible = "amcc,spi-440ep";
+                                reg = <ef600900 6>;
+                                interrupts = <8 4>;
+                                interrupt-parent = <&UIC0>;
+                        };
+
+                        ZMII0: emac-zmii@ef600d00 {
+                                compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
+                                reg = <ef600d00 c>;
+                        };
+
+                        EMAC0: ethernet@ef600e00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1c 4 1d 4>;
+                                reg = <ef600e00 70>;
+                                local-mac-address = [000000000000];
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0 1>;
+                                mal-rx-channel = <0>;
+                                cell-index = <0>;
+                                max-frame-size = <5dc>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rmii";
+                                phy-map = <00000000>;
+                                zmii-device = <&ZMII0>;
+                                zmii-channel = <0>;
+                        };
+
+                        EMAC1: ethernet@ef600f00 {
+                                device_type = "network";
+                                compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+                                interrupt-parent = <&UIC1>;
+                                interrupts = <1e 4 1f 4>;
+                                reg = <ef600f00 70>;
+                                local-mac-address = [000000000000];
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <2 3>;
+                                mal-rx-channel = <1>;
+                                cell-index = <1>;
+                                max-frame-size = <5dc>;
+                                rx-fifo-size = <1000>;
+                                tx-fifo-size = <800>;
+                                phy-mode = "rmii";
+                                phy-map = <00000000>;
+                                zmii-device = <&ZMII0>;
+                                zmii-channel = <1>;
+                        };
+
+                        usb@ef601000 {
+                                compatible = "ohci-be";
+                                reg = <ef601000 80>;
+                                interrupts = <8 4 9 4>;
+                                interrupt-parent = < &UIC1 >;
+                        };
+                };
+
+                PCI0: pci@ec000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
+                        primary;
+                        reg = <0 eec00000 8     /* Config space access */
+                               0 eed00000 4     /* IACK */
+                               0 eed00000 4     /* Special cycle */
+                               0 ef400000 40>;  /* Internal registers */
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed. Chip supports a second
+                         * IO range but we don't use it for now
+                         */
+                        ranges = <02000000 0 a0000000 0 a0000000 0 20000000
+                                  01000000 0 00000000 0 e8000000 0 00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                        /* Bamboo has all 4 IRQ pins tied together per slot */
+                        interrupt-map-mask = <f800 0 0 0>;
+                        interrupt-map = <
+                                /* IDSEL 1 */
+                                0800 0 0 0 &UIC0 1c 8
+
+                                /* IDSEL 2 */
+                                1000 0 0 0 &UIC0 1b 8
+
+                                /* IDSEL 3 */
+                                1800 0 0 0 &UIC0 1a 8
+
+                                /* IDSEL 4 */
+                                2000 0 0 0 &UIC0 19 8
+                        >;
+                };
+        };
+
+        chosen {
+                linux,stdout-path = "/plb/opb/serial@ef600300";
+        };
+};
diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c
index f61364c47a76..5532ab3221dd 100644
--- a/arch/powerpc/boot/ebony.c
+++ b/arch/powerpc/boot/ebony.c
@@ -75,7 +75,8 @@ static void ebony_fixups(void)
 
         ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
         ibm4xx_sdram_fixup_memsize();
-        dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
+        dt_fixup_mac_address_by_alias("ethernet0", ebony_mac0);
+        dt_fixup_mac_address_by_alias("ethernet1", ebony_mac1);
         ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
         ebony_flashsel_fixup();
 }
diff --git a/arch/powerpc/boot/libfdt-wrapper.c b/arch/powerpc/boot/libfdt-wrapper.c
index 59016bef1391..c541fd8a95d4 100644
--- a/arch/powerpc/boot/libfdt-wrapper.c
+++ b/arch/powerpc/boot/libfdt-wrapper.c
@@ -35,7 +35,7 @@
 #define check_err(err) \
         ({ \
                 if (BAD_ERROR(err) || ((err < 0) && DEBUG)) \
-                        printf("%s():%d  %s\n\r", __FUNCTION__, __LINE__, \
+                        printf("%s():%d  %s\n\r", __func__, __LINE__, \
                                fdt_strerror(err)); \
                 if (BAD_ERROR(err)) \
                         exit(); \
diff --git a/arch/powerpc/boot/mpc52xx-psc.c b/arch/powerpc/boot/mpc52xx-psc.c
index 1074626e6a37..d4cb4e4e0938 100644
--- a/arch/powerpc/boot/mpc52xx-psc.c
+++ b/arch/powerpc/boot/mpc52xx-psc.c
@@ -51,14 +51,9 @@ static unsigned char psc_getc(void)
 
 int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
 {
-        int n;
-
         /* Get the base address of the psc registers */
-        n = getprop(devp, "virtual-reg", &psc, sizeof(psc));
-        if (n != sizeof(psc)) {
-                if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
-                        return -1;
-        }
+        if (dt_get_virtual_reg(devp, &psc, 1) < 1)
+                return -1;
 
         scdp->open = psc_open;
         scdp->putc = psc_putc;
diff --git a/arch/powerpc/boot/mpsc.c b/arch/powerpc/boot/mpsc.c
index 802ea53790d8..425ad88cce8d 100644
--- a/arch/powerpc/boot/mpsc.c
+++ b/arch/powerpc/boot/mpsc.c
@@ -141,7 +141,7 @@ int mpsc_console_init(void *devp, struct serial_console_data *scdp)
         if (mpscintr_base == NULL)
                 goto err_out;
 
-        n = getprop(devp, "block-index", &v, sizeof(v));
+        n = getprop(devp, "cell-index", &v, sizeof(v));
         if (n != sizeof(v))
                 goto err_out;
         reg_set = (int)v;
diff --git a/arch/powerpc/boot/mv64x60.c b/arch/powerpc/boot/mv64x60.c
index b43259455d4b..d9bb302b91d2 100644
--- a/arch/powerpc/boot/mv64x60.c
+++ b/arch/powerpc/boot/mv64x60.c
@@ -535,7 +535,7 @@ u8 *mv64x60_get_bridge_pbase(void)
         u32 v[2];
         void *devp;
 
-        devp = finddevice("/mv64x60");
+        devp = find_node_by_compatible(NULL, "marvell,mv64360");
         if (devp == NULL)
                 goto err_out;
         if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
@@ -553,7 +553,7 @@ u8 *mv64x60_get_bridge_base(void)
         u32 v;
         void *devp;
 
-        devp = finddevice("/mv64x60");
+        devp = find_node_by_compatible(NULL, "marvell,mv64360");
         if (devp == NULL)
                 goto err_out;
         if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
diff --git a/arch/powerpc/boot/mv64x60_i2c.c b/arch/powerpc/boot/mv64x60_i2c.c
index d085377be3bc..52a3212b6638 100644
--- a/arch/powerpc/boot/mv64x60_i2c.c
+++ b/arch/powerpc/boot/mv64x60_i2c.c
@@ -185,7 +185,7 @@ int mv64x60_i2c_open(void)
         u32 v;
         void *devp;
 
-        devp = finddevice("/mv64x60/i2c");
+        devp = find_node_by_compatible(NULL, "marvell,mv64360-i2c");
         if (devp == NULL)
                 goto err_out;
         if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
diff --git a/arch/powerpc/boot/ns16550.c b/arch/powerpc/boot/ns16550.c
index f8f1b2f31412..aef3bdc89160 100644
--- a/arch/powerpc/boot/ns16550.c
+++ b/arch/powerpc/boot/ns16550.c
@@ -55,15 +55,9 @@ static u8 ns16550_tstc(void)
 int ns16550_console_init(void *devp, struct serial_console_data *scdp)
 {
         int n;
-        unsigned long reg_phys;
 
-        n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base));
-        if (n != sizeof(reg_base)) {
-                if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
-                        return -1;
-
-                reg_base = (void *)reg_phys;
-        }
+        if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1)
+                return -1;
 
         n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift));
         if (n != sizeof(reg_shift))
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index 4b0544b03c64..321e2f5afe71 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -95,6 +95,7 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
 int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
 int dt_is_compatible(void *node, const char *compat);
 void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
+int dt_get_virtual_reg(void *node, void **addr, int nres);
 
 static inline void *finddevice(const char *name)
 {
diff --git a/arch/powerpc/boot/prpmc2800.c b/arch/powerpc/boot/prpmc2800.c
index 05c3245b30d7..da31d6030482 100644
--- a/arch/powerpc/boot/prpmc2800.c
+++ b/arch/powerpc/boot/prpmc2800.c
@@ -344,20 +344,20 @@ static void prpmc2800_bridge_setup(u32 mem_size)
                         acc_bits);
 
         /* Get the cpu -> pci i/o & mem mappings from the device tree */
-        devp = finddevice("/mv64x60/pci@80000000");
+        devp = find_node_by_compatible(NULL, "marvell,mv64360-pci");
         if (devp == NULL)
-                fatal("Error: Missing /mv64x60/pci@80000000"
+                fatal("Error: Missing marvell,mv64360-pci"
                                 " device tree node\n\r");
 
         rc = getprop(devp, "ranges", v, sizeof(v));
         if (rc != sizeof(v))
-                fatal("Error: Can't find /mv64x60/pci@80000000/ranges"
+                fatal("Error: Can't find marvell,mv64360-pci ranges"
                                 " property\n\r");
 
         /* Get the cpu -> pci i/o & mem mappings from the device tree */
-        devp = finddevice("/mv64x60");
+        devp = find_node_by_compatible(NULL, "marvell,mv64360");
         if (devp == NULL)
-                fatal("Error: Missing /mv64x60 device tree node\n\r");
+                fatal("Error: Missing marvell,mv64360 device tree node\n\r");
 
         enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
         enables |= 0x0007fe00; /* Disable all cpu->pci windows */
@@ -429,9 +429,9 @@ static void prpmc2800_fixups(void)
         setprop(devp, "model", model, l);
 
         /* Set /cpus/PowerPC,7447/clock-frequency */
-        devp = finddevice("/cpus/PowerPC,7447");
+        devp = find_node_by_prop_value_str(NULL, "device_type", "cpu");
         if (devp == NULL)
-                fatal("Error: Missing proper /cpus device tree node\n\r");
+                fatal("Error: Missing proper cpu device tree node\n\r");
         v[0] = bip->core_speed;
         setprop(devp, "clock-frequency", &v[0], sizeof(v[0]));
 
@@ -443,16 +443,17 @@ static void prpmc2800_fixups(void)
         v[1] = bip->mem_size;
         setprop(devp, "reg", v, sizeof(v));
 
-        /* Update /mv64x60/model, if this is a mv64362 */
+        /* Update model, if this is a mv64362 */
         if (bip->bridge_type == BRIDGE_TYPE_MV64362) {
-                devp = finddevice("/mv64x60");
+                devp = find_node_by_compatible(NULL, "marvell,mv64360");
                 if (devp == NULL)
-                        fatal("Error: Missing /mv64x60 device tree node\n\r");
+                        fatal("Error: Missing marvell,mv64360"
+                                        " device tree node\n\r");
                 setprop(devp, "model", "mv64362", strlen("mv64362") + 1);
         }
 
         /* Set User FLASH size */
-        devp = finddevice("/mv64x60/flash@a0000000");
+        devp = find_node_by_compatible(NULL, "direct-mapped");
         if (devp == NULL)
                 fatal("Error: Missing User FLASH device tree node\n\r");
         rc = getprop(devp, "reg", v, sizeof(v));
diff --git a/arch/powerpc/boot/ps3-head.S b/arch/powerpc/boot/ps3-head.S
index a55c2735f759..b6fcbaf5027b 100644
--- a/arch/powerpc/boot/ps3-head.S
+++ b/arch/powerpc/boot/ps3-head.S
@@ -27,8 +27,9 @@
 /*
  * __system_reset_overlay - The PS3 first stage entry.
  *
- * The bootwraper build script copies the 0x100 bytes at symbol
- * __system_reset_overlay to offset 0x100 of the rom image.
+ * The bootwraper build script copies the 512 bytes at symbol
+ * __system_reset_overlay to offset 0x100 of the rom image.  This symbol
+ * must occupy 512 or less bytes.
  *
  * The PS3 has a single processor with two threads.
  */
@@ -47,8 +48,6 @@ __system_reset_overlay:
 
         mfspr   r3, 0x88
         cntlzw. r3, r3
-        li      r4, 0
-        li      r5, 0
         beq     1f
 
         /* Secondary goes to __secondary_hold in kernel. */
@@ -57,8 +56,14 @@ __system_reset_overlay:
         mtctr   r4
         bctr
 
-        /* Primary delays then goes to _zimage_start in wrapper. */
 1:
+        /* Save the value at addr zero for a null pointer write check later. */
+
+        li      r4, 0
+        lwz     r3, 0(r4)
+
+        /* Primary delays then goes to _zimage_start in wrapper. */
+
         or      31, 31, 31 /* db16cyc */
         or      31, 31, 31 /* db16cyc */
 
@@ -67,16 +72,18 @@ __system_reset_overlay:
         mtctr   r4
         bctr
 
+        . = __system_reset_overlay + 512
+
 /*
  * __system_reset_kernel - Place holder for the kernel reset vector.
  *
- * The bootwrapper build script copies 0x100 bytes from offset 0x100
+ * The bootwrapper build script copies 512 bytes from offset 0x100
  * of the rom image to the symbol __system_reset_kernel.  At runtime
- * the bootwrapper program copies the 0x100 bytes at __system_reset_kernel
- * to ram address 0x100.  This symbol must occupy 0x100 bytes.
+ * the bootwrapper program copies the 512 bytes at __system_reset_kernel
+ * to ram address 0x100.  This symbol must occupy 512 bytes.
  */
 
         .globl __system_reset_kernel
 __system_reset_kernel:
 
-        . = __system_reset_kernel + 0x100
+        . = __system_reset_kernel + 512
diff --git a/arch/powerpc/boot/ps3.c b/arch/powerpc/boot/ps3.c
index 3b0ac4d006ec..9954d98871d0 100644
--- a/arch/powerpc/boot/ps3.c
+++ b/arch/powerpc/boot/ps3.c
@@ -27,10 +27,10 @@
 #include "page.h"
 #include "ops.h"
 
-extern s64 lv1_panic(u64 in_1);
-extern s64 lv1_get_logical_partition_id(u64 *out_1);
-extern s64 lv1_get_logical_ppe_id(u64 *out_1);
-extern s64 lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3,
+extern int lv1_panic(u64 in_1);
+extern int lv1_get_logical_partition_id(u64 *out_1);
+extern int lv1_get_logical_ppe_id(u64 *out_1);
+extern int lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3,
         u64 in_4, u64 in_5, u64 *out_1, u64 *out_2);
 
 #ifdef DEBUG
@@ -46,6 +46,7 @@ BSS_STACK(4096);
  * edit the command line passed to vmlinux (by setting /chosen/bootargs).
  * The buffer is put in it's own section so that tools may locate it easier.
  */
+
 static char cmdline[COMMAND_LINE_SIZE]
         __attribute__((__section__("__builtin_cmdline")));
 
@@ -75,7 +76,7 @@ static void ps3_exit(void)
 
 static int ps3_repository_read_rm_size(u64 *rm_size)
 {
-        s64 result;
+        int result;
         u64 lpar_id;
         u64 ppe_id;
         u64 v2;
@@ -114,16 +115,17 @@ void ps3_copy_vectors(void)
 {
         extern char __system_reset_kernel[];
 
-        memcpy((void *)0x100, __system_reset_kernel, 0x100);
-        flush_cache((void *)0x100, 0x100);
+        memcpy((void *)0x100, __system_reset_kernel, 512);
+        flush_cache((void *)0x100, 512);
 }
 
-void platform_init(void)
+void platform_init(unsigned long null_check)
 {
         const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */
         void *chosen;
         unsigned long ft_addr;
         u64 rm_size;
+        unsigned long val;
 
         console_ops.write = ps3_console_write;
         platform_ops.exit = ps3_exit;
@@ -151,6 +153,11 @@ void platform_init(void)
 
         printf(" flat tree at 0x%lx\n\r", ft_addr);
 
+        val = *(unsigned long *)0;
+
+        if (val != null_check)
+                printf("null check failed: %lx != %lx\n\r", val, null_check);
+
         ((kernel_entry_t)0)(ft_addr, 0, NULL);
 
         ps3_exit();
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 9960421eb6b9..8b3607cb53fb 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -119,7 +119,7 @@ int serial_console_init(void)
 
         if (dt_is_compatible(devp, "ns16550"))
                 rc = ns16550_console_init(devp, &serial_cd);
-        else if (dt_is_compatible(devp, "marvell,mpsc"))
+        else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
                 rc = mpsc_console_init(devp, &serial_cd);
         else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
                  dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
diff --git a/arch/powerpc/boot/simpleboot.c b/arch/powerpc/boot/simpleboot.c
new file mode 100644
index 000000000000..86cd285bccc6
--- /dev/null
+++ b/arch/powerpc/boot/simpleboot.c
@@ -0,0 +1,84 @@
+/*
+ * The simple platform -- for booting when firmware doesn't supply a device
+ *                        tree or any platform configuration information.
+ *                        All data is extracted from an embedded device tree
+ *                        blob.
+ *
+ * Authors: Scott Wood <scottwood@freescale.com>
+ *          Grant Likely <grant.likely@secretlab.ca>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008 Secret Lab Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "types.h"
+#include "io.h"
+#include "stdio.h"
+#include "libfdt/libfdt.h"
+
+BSS_STACK(4*1024);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+                   unsigned long r6, unsigned long r7)
+{
+        const u32 *na, *ns, *reg, *timebase;
+        u64 memsize64;
+        int node, size, i;
+
+        /* Make sure FDT blob is sane */
+        if (fdt_check_header(_dtb_start) != 0)
+                fatal("Invalid device tree blob\n");
+
+        /* Find the #address-cells and #size-cells properties */
+        node = fdt_path_offset(_dtb_start, "/");
+        if (node < 0)
+                fatal("Cannot find root node\n");
+        na = fdt_getprop(_dtb_start, node, "#address-cells", &size);
+        if (!na || (size != 4))
+                fatal("Cannot find #address-cells property");
+        ns = fdt_getprop(_dtb_start, node, "#size-cells", &size);
+        if (!ns || (size != 4))
+                fatal("Cannot find #size-cells property");
+
+        /* Find the memory range */
+        node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+                                             "memory", sizeof("memory"));
+        if (node < 0)
+                fatal("Cannot find memory node\n");
+        reg = fdt_getprop(_dtb_start, node, "reg", &size);
+        if (size < (*na+*ns) * sizeof(u32))
+                fatal("cannot get memory range\n");
+
+        /* Only interested in memory based at 0 */
+        for (i = 0; i < *na; i++)
+                if (*reg++ != 0)
+                        fatal("Memory range is not based at address 0\n");
+
+        /* get the memsize and trucate it to under 4G on 32 bit machines */
+        memsize64 = 0;
+        for (i = 0; i < *ns; i++)
+                memsize64 = (memsize64 << 32) | *reg++;
+        if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
+                memsize64 = 0xffffffff;
+
+        /* finally, setup the timebase */
+        node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+                                             "cpu", sizeof("cpu"));
+        if (!node)
+                fatal("Cannot find cpu node\n");
+        timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
+        if (timebase && (size == 4))
+                timebase_period_ns = 1000000000 / *timebase;
+
+        /* Now we have the memory size; initialize the heap */
+        simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
+
+        /* prepare the device tree and find the console */
+        fdt_init(_dtb_start);
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/treeboot-walnut.c b/arch/powerpc/boot/treeboot-walnut.c
index 472e36605a52..097974e59fac 100644
--- a/arch/powerpc/boot/treeboot-walnut.c
+++ b/arch/powerpc/boot/treeboot-walnut.c
@@ -68,7 +68,7 @@ static void walnut_fixups(void)
         ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
         ibm4xx_fixup_ebc_ranges("/plb/ebc");
         walnut_flashsel_fixup();
-        dt_fixup_mac_addresses((u8 *) WALNUT_OPENBIOS_MAC_OFF);
+        dt_fixup_mac_address_by_alias("ethernet0", (u8 *) WALNUT_OPENBIOS_MAC_OFF);
 }
 
 void platform_init(void)
diff --git a/arch/powerpc/boot/virtex405-head.S b/arch/powerpc/boot/virtex405-head.S
new file mode 100644
index 000000000000..3edb13f94669
--- /dev/null
+++ b/arch/powerpc/boot/virtex405-head.S
@@ -0,0 +1,30 @@
+#include "ppc_asm.h"
+
+        .text
+        .global _zimage_start
+_zimage_start:
+
+        /* PPC errata 213: needed by Virtex-4 FX */
+        mfccr0  0
+        oris    0,0,0x50000000@h
+        mtccr0  0
+
+        /*
+         * Invalidate the data cache if the data cache is turned off.
+         * - The 405 core does not invalidate the data cache on power-up
+         *   or reset but does turn off the data cache. We cannot assume
+         *   that the cache contents are valid.
+         * - If the data cache is turned on this must have been done by
+         *   a bootloader and we assume that the cache contents are
+         *   valid.
+         */
+        mfdccr  r9
+        cmplwi  r9,0
+        bne     2f
+        lis     r9,0
+        li      r8,256
+        mtctr   r8
+1:      dccci   r0,r9
+        addi    r9,r9,0x20
+        bdnz    1b
+2:      b       _zimage_start_lib
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 8f8b8494d62f..d6c96d9ab291 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -174,7 +174,7 @@ cuboot*)
     *-mpc83*)
         platformo=$object/cuboot-83xx.o
         ;;
-    *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555)
+    *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*)
         platformo=$object/cuboot-85xx-cpm2.o
         ;;
     *-mpc85*|*-tqm8540|*-sbc85*)
@@ -199,6 +199,10 @@ adder875-redboot)
     platformo="$object/fixed-head.o $object/redboot-8xx.o"
     binary=y
     ;;
+simpleboot-virtex405-*)
+    platformo="$object/virtex405-head.o $object/simpleboot.o"
+    binary=y
+    ;;
 esac
 
 vmz="$tmpdir/`basename \"$kernel\"`.$ext"
@@ -226,10 +230,13 @@ if [ -n "$version" ]; then
     uboot_version="-n Linux-$version"
 fi
 
+# physical offset of kernel image
+membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
+
 case "$platform" in
 uboot)
     rm -f "$ofile"
-    mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \
+    mkimage -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
         $uboot_version -d "$vmz" "$ofile"
     if [ -z "$cacheit" ]; then
         rm -f "$vmz"
@@ -298,15 +305,16 @@ treeboot*)
     exit 0
     ;;
 ps3)
-    # The ps3's loader supports loading gzipped binary images from flash
-    # rom to addr zero. The loader enters the image at addr 0x100.  A
-    # bootwrapper overlay is use to arrange for the kernel to be loaded
-    # to addr zero and to have a suitable bootwrapper entry at 0x100.
-    # To construct the rom image, 0x100 bytes from offset 0x100 in the
-    # kernel is copied to the bootwrapper symbol __system_reset_kernel.
-    # The 0x100 bytes at the bootwrapper symbol __system_reset_overlay is
-    # then copied to offset 0x100.  At runtime the bootwrapper program
-    # copies the 0x100 bytes at __system_reset_kernel to addr 0x100.
+    # The ps3's loader supports loading a gzipped binary image from flash
+    # rom to ram addr zero. The loader then enters the system reset
+    # vector at addr 0x100.  A bootwrapper overlay is used to arrange for
+    # a binary image of the kernel to be at addr zero, and yet have a
+    # suitable bootwrapper entry at 0x100.  To construct the final rom
+    # image 512 bytes from offset 0x100 is copied to the bootwrapper
+    # place holder at symbol __system_reset_kernel.  The 512 bytes of the
+    # bootwrapper entry code at symbol __system_reset_overlay is then
+    # copied to offset 0x100.  At runtime the bootwrapper program copies
+    # the data at __system_reset_kernel back to addr 0x100.
 
     system_reset_overlay=0x`${CROSS}nm "$ofile" \
         | grep ' __system_reset_overlay$'       \
@@ -317,7 +325,7 @@ ps3)
         | cut -d' ' -f1`
     system_reset_kernel=`printf "%d" $system_reset_kernel`
     overlay_dest="256"
-    overlay_size="256"
+    overlay_size="512"
 
     ${CROSS}objcopy -O binary "$ofile" "$ofile.bin"
 
diff --git a/arch/powerpc/configs/ep405_defconfig b/arch/powerpc/configs/40x/ep405_defconfig
index e24240a9a047..e24240a9a047 100644
--- a/arch/powerpc/configs/ep405_defconfig
+++ b/arch/powerpc/configs/40x/ep405_defconfig
diff --git a/arch/powerpc/configs/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig
index 2f475391f1d1..2f475391f1d1 100644
--- a/arch/powerpc/configs/kilauea_defconfig
+++ b/arch/powerpc/configs/40x/kilauea_defconfig
diff --git a/arch/powerpc/configs/makalu_defconfig b/arch/powerpc/configs/40x/makalu_defconfig
index 9ef4d8a312c8..9ef4d8a312c8 100644
--- a/arch/powerpc/configs/makalu_defconfig
+++ b/arch/powerpc/configs/40x/makalu_defconfig
diff --git a/arch/powerpc/configs/walnut_defconfig b/arch/powerpc/configs/40x/walnut_defconfig
index 3b2689e5002a..3b2689e5002a 100644
--- a/arch/powerpc/configs/walnut_defconfig
+++ b/arch/powerpc/configs/40x/walnut_defconfig
diff --git a/arch/powerpc/configs/bamboo_defconfig b/arch/powerpc/configs/44x/bamboo_defconfig
index c44db554cdc6..c44db554cdc6 100644
--- a/arch/powerpc/configs/bamboo_defconfig
+++ b/arch/powerpc/configs/44x/bamboo_defconfig
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig
new file mode 100644
index 000000000000..a3b763c45ec6
--- /dev/null
+++ b/arch/powerpc/configs/44x/canyonlands_defconfig
@@ -0,0 +1,721 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc1
+# Thu Feb 21 14:29:28 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_4xx=y
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_PPC_DCR_NATIVE=y
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_DCR=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_LOGBUFFER is not set
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PPC4xx_PCI_EXPRESS=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_BAMBOO is not set
+# CONFIG_EBONY is not set
+# CONFIG_SEQUOIA is not set
+# CONFIG_TAISHAN is not set
+# CONFIG_KATMAI is not set
+# CONFIG_RAINIER is not set
+# CONFIG_WARP is not set
+CONFIG_CANYONLANDS=y
+CONFIG_460EX=y
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_RCU_TRACE=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+CONFIG_SECCOMP=y
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+# CONFIG_MTD is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_NEW_EMAC=y
+CONFIG_IBM_NEW_EMAC_RXB=256
+CONFIG_IBM_NEW_EMAC_TXB=256
+CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_NEW_EMAC_DEBUG is not set
+CONFIG_IBM_NEW_EMAC_ZMII=y
+CONFIG_IBM_NEW_EMAC_RGMII=y
+CONFIG_IBM_NEW_EMAC_TAH=y
+CONFIG_IBM_NEW_EMAC_EMAC4=y
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_DEBUGGER=y
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
diff --git a/arch/powerpc/configs/ebony_defconfig b/arch/powerpc/configs/44x/ebony_defconfig
index 07c8d4ce175a..07c8d4ce175a 100644
--- a/arch/powerpc/configs/ebony_defconfig
+++ b/arch/powerpc/configs/44x/ebony_defconfig
diff --git a/arch/powerpc/configs/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig
index c8804ec01ea4..c8804ec01ea4 100644
--- a/arch/powerpc/configs/katmai_defconfig
+++ b/arch/powerpc/configs/44x/katmai_defconfig
diff --git a/arch/powerpc/configs/rainier_defconfig b/arch/powerpc/configs/44x/rainier_defconfig
index dec18ca73519..dec18ca73519 100644
--- a/arch/powerpc/configs/rainier_defconfig
+++ b/arch/powerpc/configs/44x/rainier_defconfig
diff --git a/arch/powerpc/configs/sequoia_defconfig b/arch/powerpc/configs/44x/sequoia_defconfig
index dd5d6303c396..dd5d6303c396 100644
--- a/arch/powerpc/configs/sequoia_defconfig
+++ b/arch/powerpc/configs/44x/sequoia_defconfig
diff --git a/arch/powerpc/configs/taishan_defconfig b/arch/powerpc/configs/44x/taishan_defconfig
index 087aedce1338..087aedce1338 100644
--- a/arch/powerpc/configs/taishan_defconfig
+++ b/arch/powerpc/configs/44x/taishan_defconfig
diff --git a/arch/powerpc/configs/warp_defconfig b/arch/powerpc/configs/44x/warp_defconfig
index 2313c3e8ef61..2313c3e8ef61 100644
--- a/arch/powerpc/configs/warp_defconfig
+++ b/arch/powerpc/configs/44x/warp_defconfig
diff --git a/arch/powerpc/configs/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
index 7a862a6e3be8..7d18440e398f 100644
--- a/arch/powerpc/configs/mpc8313_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:14 2008
+# Fri Apr 11 11:10:09 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -196,6 +196,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT is not set
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
 # CONFIG_IOMMU_HELPER is not set
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -360,7 +361,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
 
 #
 # User Modules And Translation Layers
@@ -436,7 +437,7 @@ CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_NAND_FSL_ELBC is not set
+CONFIG_MTD_NAND_FSL_ELBC=y
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -1293,6 +1294,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
index 1f57456dd81e..1f57456dd81e 100644
--- a/arch/powerpc/configs/mpc8315_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
diff --git a/arch/powerpc/configs/mpc832x_mds_defconfig b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig
index 50cceda8994f..50cceda8994f 100644
--- a/arch/powerpc/configs/mpc832x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc832x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
index ac913025713e..ac913025713e 100644
--- a/arch/powerpc/configs/mpc832x_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
diff --git a/arch/powerpc/configs/mpc834x_itx_defconfig b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig
index e1de399a7bdd..e1de399a7bdd 100644
--- a/arch/powerpc/configs/mpc834x_itx_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig
diff --git a/arch/powerpc/configs/mpc834x_itxgp_defconfig b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
index b4e39cf82a8c..b4e39cf82a8c 100644
--- a/arch/powerpc/configs/mpc834x_itxgp_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
diff --git a/arch/powerpc/configs/mpc834x_mds_defconfig b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig
index b4e82c0e2be7..b4e82c0e2be7 100644
--- a/arch/powerpc/configs/mpc834x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc836x_mds_defconfig b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
index d50a96eddcdc..d50a96eddcdc 100644
--- a/arch/powerpc/configs/mpc836x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc837x_mds_defconfig b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig
index f377cde785b0..f377cde785b0 100644
--- a/arch/powerpc/configs/mpc837x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc837x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
index a6331769d88f..a6331769d88f 100644
--- a/arch/powerpc/configs/mpc837x_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
diff --git a/arch/powerpc/configs/sbc834x_defconfig b/arch/powerpc/configs/83xx/sbc834x_defconfig
index 1f1518229f6d..1f1518229f6d 100644
--- a/arch/powerpc/configs/sbc834x_defconfig
+++ b/arch/powerpc/configs/83xx/sbc834x_defconfig
diff --git a/arch/powerpc/configs/85xx/ksi8560_defconfig b/arch/powerpc/configs/85xx/ksi8560_defconfig
new file mode 100644
index 000000000000..2d0debcefdbf
--- /dev/null
+++ b/arch/powerpc/configs/85xx/ksi8560_defconfig
@@ -0,0 +1,899 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Mon Feb 11 16:25:19 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_E500=y
+CONFIG_BOOKE=y
+CONFIG_FSL_BOOKE=y
+CONFIG_FSL_EMB_PERFMON=y
+# CONFIG_PHYS_64BIT is not set
+CONFIG_SPE=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_MPC85xx=y
+# CONFIG_MPC8540_ADS is not set
+# CONFIG_MPC8560_ADS is not set
+# CONFIG_MPC85xx_CDS is not set
+# CONFIG_MPC85xx_MDS is not set
+# CONFIG_MPC85xx_DS is not set
+CONFIG_KSI8560=y
+# CONFIG_STX_GP3 is not set
+# CONFIG_TQM8540 is not set
+# CONFIG_TQM8541 is not set
+# CONFIG_TQM8555 is not set
+# CONFIG_TQM8560 is not set
+# CONFIG_SBC8548 is not set
+# CONFIG_SBC8560 is not set
+# CONFIG_IPIC is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPM2=y
+CONFIG_PPC_CPM_NEW_BINDING=y
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_CPM=y
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_RCU_TRACE=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_MATH_EMULATION=y
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_FSL_SOC=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_IDE=y
+CONFIG_IDE_MAX_HWIFS=4
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_FS_ENET=y
+# CONFIG_FS_ENET_HAS_SCC is not set
+CONFIG_FS_ENET_HAS_FCC=y
+CONFIG_FS_ENET_MDIO_FCC=y
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_GIANFAR=y
+CONFIG_GFAR_NAPI=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CPM=y
+CONFIG_SERIAL_CPM_CONSOLE=y
+CONFIG_SERIAL_CPM_SCC1=y
+# CONFIG_SERIAL_CPM_SCC2 is not set
+# CONFIG_SERIAL_CPM_SCC3 is not set
+# CONFIG_SERIAL_CPM_SCC4 is not set
+# CONFIG_SERIAL_CPM_SMC1 is not set
+# CONFIG_SERIAL_CPM_SMC2 is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_KGDB_CONSOLE is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_PPC_CLOCK is not set
+CONFIG_PPC_LIB_RHEAP=y
diff --git a/arch/powerpc/configs/mpc8540_ads_defconfig b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
index b998539da86e..b998539da86e 100644
--- a/arch/powerpc/configs/mpc8540_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
diff --git a/arch/powerpc/configs/mpc8544_ds_defconfig b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig
index 418bcdb5f919..a9f113b243ae 100644
--- a/arch/powerpc/configs/mpc8544_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig
@@ -162,6 +162,7 @@ CONFIG_MPC85xx=y
 # CONFIG_MPC85xx_CDS is not set
 # CONFIG_MPC85xx_MDS is not set
 CONFIG_MPC85xx_DS=y
+# CONFIG_KSI8560 is not set
 # CONFIG_STX_GP3 is not set
 # CONFIG_TQM8540 is not set
 # CONFIG_TQM8541 is not set
@@ -202,6 +203,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT is not set
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_MISC=m
+CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_MATH_EMULATION=y
 # CONFIG_IOMMU_HELPER is not set
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@@ -1255,7 +1257,19 @@ CONFIG_RTC_DRV_CMOS=y
 #
 # on-CPU RTC drivers
 #
-# CONFIG_DMADEVICES is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_FSL_DMA=y
+# CONFIG_FSL_DMA_SELFTEST is not set
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
 
 #
 # Userspace I/O
@@ -1447,6 +1461,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/mpc8560_ads_defconfig b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
index 851ac9115617..851ac9115617 100644
--- a/arch/powerpc/configs/mpc8560_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
diff --git a/arch/powerpc/configs/mpc8568mds_defconfig b/arch/powerpc/configs/85xx/mpc8568mds_defconfig
index 2b866b385607..2b866b385607 100644
--- a/arch/powerpc/configs/mpc8568mds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8568mds_defconfig
diff --git a/arch/powerpc/configs/mpc8572_ds_defconfig b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
index 53aa6f3173a5..53aa6f3173a5 100644
--- a/arch/powerpc/configs/mpc8572_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
diff --git a/arch/powerpc/configs/mpc85xx_cds_defconfig b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
index a469fe918816..a469fe918816 100644
--- a/arch/powerpc/configs/mpc85xx_cds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
diff --git a/arch/powerpc/configs/sbc8548_defconfig b/arch/powerpc/configs/85xx/sbc8548_defconfig
index 67f67978c742..67f67978c742 100644
--- a/arch/powerpc/configs/sbc8548_defconfig
+++ b/arch/powerpc/configs/85xx/sbc8548_defconfig
diff --git a/arch/powerpc/configs/sbc8560_defconfig b/arch/powerpc/configs/85xx/sbc8560_defconfig
index fef605579e29..fef605579e29 100644
--- a/arch/powerpc/configs/sbc8560_defconfig
+++ b/arch/powerpc/configs/85xx/sbc8560_defconfig
diff --git a/arch/powerpc/configs/stx_gp3_defconfig b/arch/powerpc/configs/85xx/stx_gp3_defconfig
index 1d303c49bb0c..1d303c49bb0c 100644
--- a/arch/powerpc/configs/stx_gp3_defconfig
+++ b/arch/powerpc/configs/85xx/stx_gp3_defconfig
diff --git a/arch/powerpc/configs/tqm8540_defconfig b/arch/powerpc/configs/85xx/tqm8540_defconfig
index d39ee3b35bfc..d39ee3b35bfc 100644
--- a/arch/powerpc/configs/tqm8540_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8540_defconfig
diff --git a/arch/powerpc/configs/tqm8541_defconfig b/arch/powerpc/configs/85xx/tqm8541_defconfig
index cbf6ad2d71da..cbf6ad2d71da 100644
--- a/arch/powerpc/configs/tqm8541_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8541_defconfig
diff --git a/arch/powerpc/configs/tqm8555_defconfig b/arch/powerpc/configs/85xx/tqm8555_defconfig
index bbff962c8472..bbff962c8472 100644
--- a/arch/powerpc/configs/tqm8555_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8555_defconfig
diff --git a/arch/powerpc/configs/tqm8560_defconfig b/arch/powerpc/configs/85xx/tqm8560_defconfig
index 63c5ec8b6515..63c5ec8b6515 100644
--- a/arch/powerpc/configs/tqm8560_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8560_defconfig
diff --git a/arch/powerpc/configs/chrp32_defconfig b/arch/powerpc/configs/chrp32_defconfig
index 38b85b211c38..d7fd298bd234 100644
--- a/arch/powerpc/configs/chrp32_defconfig
+++ b/arch/powerpc/configs/chrp32_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 10:33:36 2008
+# Thu Mar 27 13:55:37 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -74,8 +74,6 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=15
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -243,7 +241,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
@@ -1328,6 +1326,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig
index 0f82f66a60f8..a20501f89474 100644
--- a/arch/powerpc/configs/g5_defconfig
+++ b/arch/powerpc/configs/g5_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 10:36:41 2008
+# Thu Mar 27 13:55:43 2008
 #
 CONFIG_PPC64=y
 
@@ -77,8 +77,6 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=17
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -276,7 +274,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
@@ -1596,6 +1594,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/iseries_defconfig b/arch/powerpc/configs/iseries_defconfig
index 8d9a84f50157..b3128fb7ce7e 100644
--- a/arch/powerpc/configs/iseries_defconfig
+++ b/arch/powerpc/configs/iseries_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 10:43:46 2008
+# Thu Mar 27 13:55:45 2008
 #
 CONFIG_PPC64=y
 
@@ -77,8 +77,6 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=17
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -261,7 +259,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
@@ -1065,6 +1063,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/maple_defconfig b/arch/powerpc/configs/maple_defconfig
index 8b810d056440..7a166a39d92d 100644
--- a/arch/powerpc/configs/maple_defconfig
+++ b/arch/powerpc/configs/maple_defconfig
@@ -333,7 +333,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -374,6 +374,7 @@ CONFIG_BLK_DEV_IDEDISK=y
 CONFIG_BLK_DEV_IDECD=y
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
 CONFIG_IDE_TASK_IOCTL=y
 CONFIG_IDE_PROC_FS=y
 
@@ -427,10 +428,129 @@ CONFIG_IDE_ARCH_OBSOLETE_INIT=y
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+CONFIG_SCSI_IPR=y
+CONFIG_SCSI_IPR_TRACE=y
+CONFIG_SCSI_IPR_DUMP=y
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+CONFIG_ATA=y
+CONFIG_ATA_NONSTANDARD=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
@@ -536,6 +656,7 @@ CONFIG_USB_PEGASUS=y
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
@@ -783,12 +904,14 @@ CONFIG_USB_UHCI_HCD=y
 #
 # may also be needed; see USB_STORAGE Help for more information
 #
+# CONFIG_USB_STORAGE is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
 CONFIG_USB_MON=y
 
 #
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 029d2dab7deb..9e0dd8201691 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:25 2008
+# Linux kernel version: 2.6.25-rc9
+# Tue Apr 15 18:07:36 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -201,6 +201,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT is not set
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_MATH_EMULATION=y
 # CONFIG_IOMMU_HELPER is not set
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@@ -353,7 +354,90 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_FSL_ELBC=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
@@ -362,6 +446,7 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=32768
@@ -469,6 +554,15 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -563,6 +657,7 @@ CONFIG_I2C_MPC=y
 # CONFIG_I2C_SIMTEC is not set
 # CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
 # Miscellaneous I2C Chip support
@@ -648,6 +743,11 @@ CONFIG_WATCHDOG=y
 CONFIG_83xx_WDT=y
 
 #
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
 # Sonics Silicon Backplane
 #
 CONFIG_SSB_POSSIBLE=y
@@ -664,6 +764,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
 CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
@@ -686,6 +787,14 @@ CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -715,8 +824,55 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
 # CONFIG_USB_R8A66597_HCD is not set
 
 #
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -792,6 +948,7 @@ CONFIG_TMPFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
@@ -862,6 +1019,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig
index 558b0d348d4f..fca114252ac7 100644
--- a/arch/powerpc/configs/pmac32_defconfig
+++ b/arch/powerpc/configs/pmac32_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 11:05:14 2008
+# Thu Mar 27 13:56:21 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -77,8 +77,6 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -272,7 +270,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 CONFIG_PCCARD=m
 # CONFIG_PCMCIA_DEBUG is not set
@@ -1895,6 +1893,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig
new file mode 100644
index 000000000000..9d0140e3838e
--- /dev/null
+++ b/arch/powerpc/configs/ppc40x_defconfig
@@ -0,0 +1,896 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc9
+# Tue Apr 15 08:46:44 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+CONFIG_40x=y
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_4xx=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_PPC_DCR_NATIVE=y
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_DCR=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+CONFIG_PPC4xx_PCI_EXPRESS=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_EP405=y
+CONFIG_KILAUEA=y
+CONFIG_MAKALU=y
+CONFIG_WALNUT=y
+CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
+CONFIG_405GP=y
+CONFIG_405EX=y
+CONFIG_XILINX_VIRTEX=y
+CONFIG_XILINX_VIRTEX_II_PRO=y
+CONFIG_XILINX_VIRTEX_4_FX=y
+CONFIG_IBM405_ERR77=y
+CONFIG_IBM405_ERR51=y
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_OF_RTC=y
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_4xx_SOC=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+# CONFIG_PCI_LEGACY is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00400000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_NEW_EMAC=y
+CONFIG_IBM_NEW_EMAC_RXB=128
+CONFIG_IBM_NEW_EMAC_TXB=64
+CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_NEW_EMAC_DEBUG is not set
+CONFIG_IBM_NEW_EMAC_ZMII=y
+CONFIG_IBM_NEW_EMAC_RGMII=y
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+CONFIG_IBM_NEW_EMAC_EMAC4=y
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+CONFIG_XILINX_HWICAP=m
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_PPC_CLOCK is not set
diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig
index 57bd775ef777..12f9b5a80220 100644
--- a/arch/powerpc/configs/ppc44x_defconfig
+++ b/arch/powerpc/configs/ppc44x_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc2
-# Fri Feb 15 21:57:35 2008
+# Linux kernel version: 2.6.25-rc6
+# Sat Apr  5 09:35:48 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -79,6 +79,7 @@ CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -113,6 +114,7 @@ CONFIG_SLUB=y
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
 CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -143,7 +145,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
 CONFIG_PPC4xx_PCI_EXPRESS=y
 
 #
@@ -161,12 +162,15 @@ CONFIG_TAISHAN=y
 CONFIG_KATMAI=y
 CONFIG_RAINIER=y
 CONFIG_WARP=y
+CONFIG_CANYONLANDS=y
+CONFIG_YOSEMITE=y
 CONFIG_440EP=y
 CONFIG_440EPX=y
 CONFIG_440GRX=y
 CONFIG_440GP=y
 CONFIG_440GX=y
 CONFIG_440SPe=y
+CONFIG_460EX=y
 CONFIG_IBM440EP_ERR42=y
 # CONFIG_IPIC is not set
 # CONFIG_MPIC is not set
@@ -199,7 +203,6 @@ CONFIG_HZ=250
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-# CONFIG_RCU_TRACE is not set
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 CONFIG_MATH_EMULATION=y
@@ -232,6 +235,7 @@ CONFIG_ISA_DMA_API=y
 #
 CONFIG_ZONE_DMA=y
 CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_4xx_SOC=y
 CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_SYSCALL=y
@@ -678,6 +682,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_INFINIBAND is not set
 # CONFIG_EDAC is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 
 #
 # Userspace I/O
@@ -805,6 +810,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 880ab7ad10c1..970282b1a004 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 11:06:28 2008
+# Thu Mar 27 13:56:24 2008
 #
 CONFIG_PPC64=y
 
@@ -84,8 +84,6 @@ CONFIG_CGROUPS=y
 # CONFIG_CGROUP_NS is not set
 CONFIG_CPUSETS=y
 # CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
 # CONFIG_CGROUP_CPUACCT is not set
 # CONFIG_RESOURCE_COUNTERS is not set
 CONFIG_SYSFS_DEPRECATED=y
@@ -289,6 +287,7 @@ CONFIG_ARCH_HAS_WALK_MEMORY=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
 CONFIG_KEXEC=y
 # CONFIG_CRASH_DUMP is not set
+# CONFIG_PHYP_DUMP is not set
 CONFIG_IRQ_ALL_CPUS=y
 # CONFIG_NUMA is not set
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
@@ -335,7 +334,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
@@ -1881,6 +1880,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index 755aca72b522..3e2593c60b12 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 11:08:01 2008
+# Thu Mar 27 13:56:28 2008
 #
 CONFIG_PPC64=y
 
@@ -83,8 +83,6 @@ CONFIG_CGROUPS=y
 CONFIG_CGROUP_NS=y
 CONFIG_CPUSETS=y
 # CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
 CONFIG_CGROUP_CPUACCT=y
 # CONFIG_RESOURCE_COUNTERS is not set
 CONFIG_SYSFS_DEPRECATED=y
@@ -237,6 +235,7 @@ CONFIG_ARCH_HAS_WALK_MEMORY=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
 CONFIG_KEXEC=y
 # CONFIG_CRASH_DUMP is not set
+# CONFIG_PHYP_DUMP is not set
 CONFIG_IRQ_ALL_CPUS=y
 CONFIG_NUMA=y
 CONFIG_NODES_SHIFT=4
@@ -283,7 +282,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCCARD is not set
 CONFIG_HOTPLUG_PCI=m
@@ -1519,6 +1518,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking
diff --git a/arch/powerpc/configs/sbc8641d_defconfig b/arch/powerpc/configs/sbc8641d_defconfig
new file mode 100644
index 000000000000..3180125aa6c4
--- /dev/null
+++ b/arch/powerpc/configs/sbc8641d_defconfig
@@ -0,0 +1,1342 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc6
+# Thu Apr 10 18:03:25 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_ALTIVEC=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_MULTIPLATFORM is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PPC_83xx is not set
+CONFIG_PPC_86xx=y
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_MPC8641_HPCN is not set
+CONFIG_SBC8641D=y
+# CONFIG_MPC8610_HPCD is not set
+CONFIG_MPC8641=y
+# CONFIG_IPIC is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_IRQ_ALL_CPUS=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+# CONFIG_IP_NF_MATCH_AH is not set
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+# CONFIG_IP_NF_TARGET_TTL is not set
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+# CONFIG_IP6_NF_TARGET_REJECT is not set
+CONFIG_IP6_NF_MANGLE=m
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IP6_NF_RAW=m
+
+#
+# Bridge: Netfilter Configuration
+#
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_RR is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_OF_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_LE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_LINEAR=y
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID10=y
+# CONFIG_MD_RAID456 is not set
+CONFIG_MD_MULTIPATH=y
+CONFIG_MD_FAULTY=y
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_MIRROR=y
+CONFIG_DM_ZERO=y
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_GIANFAR=y
+# CONFIG_GFAR_NAPI is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+CONFIG_ATM_DRIVERS=y
+# CONFIG_ATM_DUMMY is not set
+# CONFIG_ATM_TCP is not set
+# CONFIG_ATM_LANAI is not set
+# CONFIG_ATM_ENI is not set
+# CONFIG_ATM_FIRESTREAM is not set
+# CONFIG_ATM_ZATM is not set
+# CONFIG_ATM_NICSTAR is not set
+# CONFIG_ATM_IDT77252 is not set
+# CONFIG_ATM_AMBASSADOR is not set
+# CONFIG_ATM_HORIZON is not set
+# CONFIG_ATM_IA is not set
+# CONFIG_ATM_FORE200E_MAYBE is not set
+# CONFIG_ATM_HE is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPPOE=m
+CONFIG_PPPOATM=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+CONFIG_SOFT_WATCHDOG=m
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+# CONFIG_REISERFS_FS_SECURITY is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_DEBUG_MASKLOG=y
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=m
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_NFS_DIRECTIO=y
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMB_NLS_REMOTE="cp437"
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_DEBUGGER=y
+# CONFIG_XMON is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+CONFIG_SECURITY_CAPABILITIES=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_WP512=m
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_PPC_CLOCK is not set
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index b9dbfff9afe9..ce1e8d24e747 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_BOOTX_TEXT)	+= btext.o
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_KPROBES)           += kprobes.o
 obj-$(CONFIG_PPC_UDBG_16550)    += legacy_serial.o udbg_16550.o
+obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 
 pci64-$(CONFIG_PPC64)           += pci_dn.o isa-bridge.o
 obj-$(CONFIG_PCI)               += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 4b749c416464..292c6d8db0e1 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -26,8 +26,6 @@
 #ifdef CONFIG_PPC64
 #include <linux/time.h>
 #include <linux/hardirq.h>
-#else
-#include <linux/ptrace.h>
 #endif
 
 #include <asm/io.h>
@@ -46,6 +44,9 @@
 #include <asm/mmu.h>
 #include <asm/hvcall.h>
 #endif
+#ifdef CONFIG_PPC_ISERIES
+#include <asm/iseries/alpaca.h>
+#endif
 
 #define DEFINE(sym, val) \
         asm volatile("\n->" #sym " %0 " #val : : "i" (val))
@@ -60,7 +61,6 @@ int main(void)
         DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
 #else
         DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
-        DEFINE(PTRACE, offsetof(struct task_struct, ptrace));
 #endif /* CONFIG_PPC64 */
 
         DEFINE(KSP, offsetof(struct thread_struct, ksp));
@@ -80,7 +80,6 @@ int main(void)
         DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
         DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));
-        DEFINE(PT_PTRACED, PT_PTRACED);
 #endif
 #ifdef CONFIG_SPE
         DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
@@ -325,6 +324,9 @@ int main(void)
         DEFINE(PAGE_OFFSET_VSID, KERNEL_VSID(PAGE_OFFSET));
         DEFINE(VMALLOC_START_ESID, GET_ESID(VMALLOC_START));
         DEFINE(VMALLOC_START_VSID, KERNEL_VSID(VMALLOC_START));
+
+        /* alpaca */
+        DEFINE(ALPACA_SIZE, sizeof(struct alpaca));
 #endif
 
         DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
diff --git a/arch/powerpc/kernel/btext.c b/arch/powerpc/kernel/btext.c
index 80e2eef05b2e..9f9377745490 100644
--- a/arch/powerpc/kernel/btext.c
+++ b/arch/powerpc/kernel/btext.c
@@ -7,6 +7,7 @@
 #include <linux/string.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/lmb.h>
 
 #include <asm/sections.h>
 #include <asm/prom.h>
@@ -15,7 +16,7 @@
 #include <asm/mmu.h>
 #include <asm/pgtable.h>
 #include <asm/io.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/processor.h>
 #include <asm/udbg.h>
 
diff --git a/arch/powerpc/kernel/cpu_setup_44x.S b/arch/powerpc/kernel/cpu_setup_44x.S
index 6250443ab9c9..5465e8de0e61 100644
--- a/arch/powerpc/kernel/cpu_setup_44x.S
+++ b/arch/powerpc/kernel/cpu_setup_44x.S
@@ -3,7 +3,7 @@
  * Valentine Barshak <vbarshak@ru.mvista.com>
  * MontaVista Software, Inc (c) 2007
  *
- * Based on cpu_setup_6xx code by 
+ * Based on cpu_setup_6xx code by
  * Benjamin Herrenschmidt <benh@kernel.crashing.org>
  *
  * This program is free software; you can redistribute it and/or
@@ -32,6 +32,9 @@ _GLOBAL(__setup_cpu_440grx)
         bl      __fixup_440A_mcheck
         mtlr    r4
         blr
+_GLOBAL(__setup_cpu_460ex)
+_GLOBAL(__setup_cpu_460gt)
+        b       __init_fpu_44x
 _GLOBAL(__setup_cpu_440gx)
 _GLOBAL(__setup_cpu_440spe)
         b       __fixup_440A_mcheck
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 2a8f5cc5184f..26ffb44e2701 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -36,6 +36,8 @@ extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
@@ -1397,6 +1399,30 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_440A,
                 .platform               = "ppc440",
         },
+        { /* 460EX */
+                .pvr_mask               = 0xffff0002,
+                .pvr_value              = 0x13020002,
+                .cpu_name               = "460EX",
+                .cpu_features           = CPU_FTRS_44X,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .cpu_setup              = __setup_cpu_460ex,
+                .machine_check          = machine_check_440A,
+                .platform               = "ppc440",
+        },
+        { /* 460GT */
+                .pvr_mask               = 0xffff0002,
+                .pvr_value              = 0x13020000,
+                .cpu_name               = "460GT",
+                .cpu_features           = CPU_FTRS_44X,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .cpu_setup              = __setup_cpu_460gt,
+                .machine_check          = machine_check_440A,
+                .platform               = "ppc440",
+        },
 #endif /* CONFIG_44x */
 #ifdef CONFIG_FSL_BOOKE
 #ifdef CONFIG_E200
@@ -1512,7 +1538,7 @@ struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
                                 *t = *s;
                         *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
 #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
-                        /* ppc64 and booke expect identify_cpu to also call 
+                        /* ppc64 and booke expect identify_cpu to also call
                          * setup_cpu for that processor. I will consolidate
                          * that at a later time, for now, just use #ifdef.
                          * we also don't need to PTRRELOC the function pointer
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index 571132ed12c1..eae401de3f76 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -24,12 +24,13 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/types.h>
+#include <linux/lmb.h>
 
 #include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/kexec.h>
 #include <asm/kdump.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/firmware.h>
 #include <asm/smp.h>
 #include <asm/system.h>
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 29ff77c468ac..9ee3c5278db0 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -13,8 +13,9 @@
 
 #include <linux/crash_dump.h>
 #include <linux/bootmem.h>
+#include <linux/lmb.h>
 #include <asm/kdump.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/firmware.h>
 #include <asm/uaccess.h>
 
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 69a91bd46115..84c868633068 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -110,9 +110,9 @@ transfer_to_handler:
         stw     r11,PT_REGS(r12)
 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
         /* Check to see if the dbcr0 register is set up to debug.  Use the
-           single-step bit to do this. */
+           internal debug mode bit to do this. */
         lwz     r12,THREAD_DBCR0(r12)
-        andis.  r12,r12,DBCR0_IC@h
+        andis.  r12,r12,DBCR0_IDM@h
         beq+    3f
         /* From user and task is ptraced - load up global dbcr0 */
         li      r12,-1                  /* clear all pending debug events */
@@ -120,6 +120,12 @@ transfer_to_handler:
         lis     r11,global_dbcr0@ha
         tophys(r11,r11)
         addi    r11,r11,global_dbcr0@l
+#ifdef CONFIG_SMP
+        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        lwz     r9,TI_CPU(r9)
+        slwi    r9,r9,3
+        add     r11,r11,r9
+#endif
         lwz     r12,0(r11)
         mtspr   SPRN_DBCR0,r12
         lwz     r12,4(r11)
@@ -238,10 +244,10 @@ ret_from_syscall:
         stw     r11,_CCR(r1)
 syscall_exit_cont:
 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
-        /* If the process has its own DBCR0 value, load it up.  The single
-           step bit tells us that dbcr0 should be loaded. */
+        /* If the process has its own DBCR0 value, load it up.  The internal
+           debug mode bit tells us that dbcr0 should be loaded. */
         lwz     r0,THREAD+THREAD_DBCR0(r2)
-        andis.  r10,r0,DBCR0_IC@h
+        andis.  r10,r0,DBCR0_IDM@h
         bnel-   load_dbcr0
 #endif
 #ifdef CONFIG_44x
@@ -666,10 +672,10 @@ user_exc_return:		/* r10 contains MSR_KERNEL here */
 
 restore_user:
 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
-        /* Check whether this process has its own DBCR0 value.  The single
-           step bit tells us that dbcr0 should be loaded. */
+        /* Check whether this process has its own DBCR0 value.  The internal
+           debug mode bit tells us that dbcr0 should be loaded. */
         lwz     r0,THREAD+THREAD_DBCR0(r2)
-        andis.  r10,r0,DBCR0_IC@h
+        andis.  r10,r0,DBCR0_IDM@h
         bnel-   load_dbcr0
 #endif
 
@@ -879,6 +885,12 @@ load_dbcr0:
         mfspr   r10,SPRN_DBCR0
         lis     r11,global_dbcr0@ha
         addi    r11,r11,global_dbcr0@l
+#ifdef CONFIG_SMP
+        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        lwz     r9,TI_CPU(r9)
+        slwi    r9,r9,3
+        add     r11,r11,r9
+#endif
         stw     r10,0(r11)
         mtspr   SPRN_DBCR0,r0
         lwz     r10,4(r11)
@@ -891,7 +903,7 @@ load_dbcr0:
         .section .bss
         .align  4
 global_dbcr0:
-        .space  8
+        .space  8*NR_CPUS
         .previous
 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
 
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 148a3547c9aa..c0db5b769e55 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -29,6 +29,8 @@
 #include <asm/cputable.h>
 #include <asm/firmware.h>
 #include <asm/bug.h>
+#include <asm/ptrace.h>
+#include <asm/irqflags.h>
 
 /*
  * System calls.
@@ -39,7 +41,7 @@
 
 /* This value is used to mark exception frames on the stack. */
 exception_marker:
-        .tc     ID_72656773_68657265[TC],0x7265677368657265
+        .tc     ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
 
         .section        ".text"
         .align 7
@@ -88,6 +90,14 @@ system_call_common:
         addi    r9,r1,STACK_FRAME_OVERHEAD
         ld      r11,exception_marker@toc(r2)
         std     r11,-16(r9)             /* "regshere" marker */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        bl      .trace_hardirqs_on
+        REST_GPR(0,r1)
+        REST_4GPRS(3,r1)
+        REST_2GPRS(7,r1)
+        addi    r9,r1,STACK_FRAME_OVERHEAD
+        ld      r12,_MSR(r1)
+#endif /* CONFIG_TRACE_IRQFLAGS */
         li      r10,1
         stb     r10,PACASOFTIRQEN(r13)
         stb     r10,PACAHARDIRQEN(r13)
@@ -102,7 +112,7 @@ BEGIN_FW_FTR_SECTION
         b       hardware_interrupt_entry
 2:
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif
+#endif /* CONFIG_PPC_ISERIES */
         mfmsr   r11
         ori     r11,r11,MSR_EE
         mtmsrd  r11,1
@@ -504,6 +514,10 @@ BEGIN_FW_FTR_SECTION
 
         li      r3,0
         stb     r3,PACASOFTIRQEN(r13)   /* ensure we are soft-disabled */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        bl      .trace_hardirqs_off
+        mfmsr   r10
+#endif
         ori     r10,r10,MSR_EE
         mtmsrd  r10                     /* hard-enable again */
         addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -512,7 +526,7 @@ BEGIN_FW_FTR_SECTION
 4:
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
-        stb     r5,PACASOFTIRQEN(r13)
+        TRACE_AND_RESTORE_IRQ(r5);
 
         /* extract EE bit and use it to restore paca->hard_enabled */
         ld      r3,_MSR(r1)
@@ -580,6 +594,16 @@ do_work:
         bne     restore
         /* here we are preempting the current task */
 1:
+#ifdef CONFIG_TRACE_IRQFLAGS
+        bl      .trace_hardirqs_on
+        /* Note: we just clobbered r10 which used to contain the previous
+         * MSR before the hard-disabling done by the caller of do_work.
+         * We don't have that value anymore, but it doesn't matter as
+         * we will hard-enable unconditionally, we can just reload the
+         * current MSR into r10
+         */
+        mfmsr   r10
+#endif /* CONFIG_TRACE_IRQFLAGS */
         li      r0,1
         stb     r0,PACASOFTIRQEN(r13)
         stb     r0,PACAHARDIRQEN(r13)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 0f4fac512020..785af9b56591 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -30,6 +30,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
 
 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
 #define LOAD_BAT(n, reg, RA, RB)        \
@@ -268,8 +269,8 @@ __secondary_hold_acknowledge:
         li      r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
         MTMSRD(r10);                    /* (except for mach check in rtas) */ \
         stw     r0,GPR0(r11);   \
-        lis     r10,0x7265;             /* put exception frame marker */ \
-        addi    r10,r10,0x6773; \
+        lis     r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
+        addi    r10,r10,STACK_FRAME_REGS_MARKER@l; \
         stw     r10,8(r11);     \
         SAVE_4GPRS(3, r11);     \
         SAVE_2GPRS(7, r11)
@@ -763,23 +764,6 @@ load_up_altivec:
         b       fast_exception_return
 
 /*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
-        lwz     r3,_MSR(r1)
-        oris    r3,r3,MSR_VEC@h
-        stw     r3,_MSR(r1)     /* enable use of AltiVec after return */
-        lis     r3,87f@h
-        ori     r3,r3,87f@l
-        mr      r4,r2           /* current */
-        lwz     r5,_NIP(r1)
-        bl      printk
-        b       ret_from_except
-87:     .string "AltiVec used in kernel  (task=%p, pc=%x)  \n"
-        .align  4,0
-
-/*
  * giveup_altivec(tsk)
  * Disable AltiVec for the task given as the argument,
  * and save the AltiVec registers in its thread_struct.
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index ad071a146a8d..b84ec6a2fc94 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -211,7 +211,7 @@ skpinv:	addi	r4,r4,1				/* Increment */
         SET_IVOR(12, WatchdogTimer);
         SET_IVOR(13, DataTLBError);
         SET_IVOR(14, InstructionTLBError);
-        SET_IVOR(15, Debug);
+        SET_IVOR(15, DebugCrit);
 
         /* Establish the interrupt vector base */
         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
@@ -578,7 +578,7 @@ interrupt_base:
         b       InstructionStorage
 
         /* Debug Interrupt */
-        DEBUG_EXCEPTION
+        DEBUG_CRIT_EXCEPTION
 
 /*
  * Local functions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index d3aee08e6814..215973a2c8d5 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -36,8 +36,7 @@
 #include <asm/firmware.h>
 #include <asm/page_64.h>
 #include <asm/exception.h>
-
-#define DO_SOFT_DISABLE
+#include <asm/irqflags.h>
 
 /*
  * We layout physical memory as follows:
@@ -450,8 +449,8 @@ bad_stack:
  */
 fast_exc_return_irq:                    /* restores irq state too */
         ld      r3,SOFTE(r1)
+        TRACE_AND_RESTORE_IRQ(r3);
         ld      r12,_MSR(r1)
-        stb     r3,PACASOFTIRQEN(r13)   /* restore paca->soft_enabled */
         rldicl  r4,r12,49,63            /* get MSR_EE to LSB */
         stb     r4,PACAHARDIRQEN(r13)   /* restore paca->hard_enabled */
         b       1f
@@ -621,7 +620,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
         mtlr    r10
 
         andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
-        beq-    unrecov_slb
+        beq-    2f
 
 .machine        push
 .machine        "power4"
@@ -643,6 +642,22 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
         rfid
         b       .       /* prevent speculative execution */
 
+2:
+#ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
+        b       unrecov_slb
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+#endif /* CONFIG_PPC_ISERIES */
+        mfspr   r11,SPRN_SRR0
+        clrrdi  r10,r13,32
+        LOAD_HANDLER(r10,unrecov_slb)
+        mtspr   SPRN_SRR0,r10
+        mfmsr   r10
+        ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
+        mtspr   SPRN_SRR1,r10
+        rfid
+        b       .
+
 unrecov_slb:
         EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
         DISABLE_INTS
@@ -808,7 +823,7 @@ _STATIC(load_up_altivec)
  * Hash table stuff
  */
         .align  7
-_GLOBAL(do_hash_page)
+_STATIC(do_hash_page)
         std     r3,_DAR(r1)
         std     r4,_DSISR(r1)
 
@@ -820,6 +835,27 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 
         /*
+         * On iSeries, we soft-disable interrupts here, then
+         * hard-enable interrupts so that the hash_page code can spin on
+         * the hash_table_lock without problems on a shared processor.
+         */
+        DISABLE_INTS
+
+        /*
+         * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
+         * and will clobber volatile registers when irq tracing is enabled
+         * so we need to reload them. It may be possible to be smarter here
+         * and move the irq tracing elsewhere but let's keep it simple for
+         * now
+         */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        ld      r3,_DAR(r1)
+        ld      r4,_DSISR(r1)
+        ld      r5,_TRAP(r1)
+        ld      r12,_MSR(r1)
+        clrrdi  r5,r5,4
+#endif /* CONFIG_TRACE_IRQFLAGS */
+        /*
          * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
          * accessing a userspace segment (even from the kernel). We assume
          * kernel addresses always have the high bit set.
@@ -832,13 +868,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
         rlwimi  r4,r5,22+2,31-2,31-2    /* Set _PAGE_EXEC if trap is 0x400 */
 
         /*
-         * On iSeries, we soft-disable interrupts here, then
-         * hard-enable interrupts so that the hash_page code can spin on
-         * the hash_table_lock without problems on a shared processor.
-         */
-        DISABLE_INTS
-
-        /*
          * r3 contains the faulting address
          * r4 contains the required access permissions
          * r5 contains the trap number
@@ -848,7 +877,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
         bl      .hash_page              /* build HPTE if possible */
         cmpdi   r3,0                    /* see if hash_page succeeded */
 
-#ifdef DO_SOFT_DISABLE
 BEGIN_FW_FTR_SECTION
         /*
          * If we had interrupts soft-enabled at the point where the
@@ -860,7 +888,7 @@ BEGIN_FW_FTR_SECTION
          */
         beq     13f
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif
+
 BEGIN_FW_FTR_SECTION
         /*
          * Here we have interrupts hard-disabled, so it is sufficient
@@ -874,11 +902,12 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
 
         /*
          * hash_page couldn't handle it, set soft interrupt enable back
-         * to what it was before the trap.  Note that .local_irq_restore
+         * to what it was before the trap.  Note that .raw_local_irq_restore
          * handles any interrupts pending at this point.
          */
         ld      r3,SOFTE(r1)
-        bl      .local_irq_restore
+        TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
+        bl      .raw_local_irq_restore
         b       11f
 
 /* Here we have a page fault that hash_page can't handle. */
@@ -1477,6 +1506,10 @@ _INIT_STATIC(start_here_multiplatform)
         addi    r2,r2,0x4000
         add     r2,r2,r26
 
+        /* Set initial ptr to current */
+        LOAD_REG_IMMEDIATE(r4, init_task)
+        std     r4,PACACURRENT(r13)
+
         /* Do very early kernel initializations, including initial hash table,
          * stab and slb setup before we turn on relocation.     */
 
@@ -1505,10 +1538,6 @@ _INIT_GLOBAL(start_here_common)
         li      r0,0
         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
 
-        /* ptr to current */
-        LOAD_REG_IMMEDIATE(r4, init_task)
-        std     r4,PACACURRENT(r13)
-
         /* Load the TOC */
         ld      r2,PACATOC(r13)
         std     r1,PACAKSAVE(r13)
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index ba9393f8e77a..aefafc6330c9 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -56,8 +56,17 @@
  * is necessary since the MMU is always on, for Book-E parts, and the stacks
  * are offset from KERNELBASE.
  *
+ * There is some space optimization to be had here if desired.  However
+ * to allow for a common kernel with support for debug exceptions either
+ * going to critical or their own debug level we aren't currently
+ * providing configurations that micro-optimize space usage.
  */
-#define BOOKE_EXCEPTION_STACK_SIZE      (8192)
+#ifdef CONFIG_44x
+#define NUM_EXCEPTION_LVLS      2
+#else
+#define NUM_EXCEPTION_LVLS      3
+#endif
+#define BOOKE_EXCEPTION_STACK_SIZE      (4096 * NUM_EXCEPTION_LVLS)
 
 /* CRIT_SPRG only used in critical exception handling */
 #define CRIT_SPRG       SPRN_SPRG2
@@ -68,7 +77,7 @@
 #define CRIT_STACK_TOP          (exception_stack_top)
 
 /* only on e200 for now */
-#define DEBUG_STACK_TOP         (exception_stack_top - 4096)
+#define DEBUG_STACK_TOP         (exception_stack_top - 8192)
 #define DEBUG_SPRG              SPRN_SPRG6W
 
 #ifdef CONFIG_SMP
@@ -212,9 +221,8 @@ label:
  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
  * the MSR_DE bit set.
  */
-#ifdef CONFIG_E200
-#define DEBUG_EXCEPTION                                                       \
-        START_EXCEPTION(Debug);                                               \
+#define DEBUG_DEBUG_EXCEPTION                                                 \
+        START_EXCEPTION(DebugDebug);                                          \
         DEBUG_EXCEPTION_PROLOG;                                               \
                                                                               \
         /*                                                                    \
@@ -234,8 +242,8 @@ label:
         cmplw   r12,r10;                                                      \
         blt+    2f;                     /* addr below exception vectors */    \
                                                                               \
-        lis     r10,Debug@h;                                                  \
-        ori     r10,r10,Debug@l;                                              \
+        lis     r10,DebugDebug@h;                                             \
+        ori     r10,r10,DebugDebug@l;                                         \
         cmplw   r12,r10;                                                      \
         bgt+    2f;                     /* addr above exception vectors */    \
                                                                               \
@@ -265,9 +273,9 @@ label:
 2:      mfspr   r4,SPRN_DBSR;                                                 \
         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
-#else
-#define DEBUG_EXCEPTION                                                       \
-        START_EXCEPTION(Debug);                                               \
+
+#define DEBUG_CRIT_EXCEPTION                                                  \
+        START_EXCEPTION(DebugCrit);                                           \
         CRITICAL_EXCEPTION_PROLOG;                                            \
                                                                               \
         /*                                                                    \
@@ -287,8 +295,8 @@ label:
         cmplw   r12,r10;                                                      \
         blt+    2f;                     /* addr below exception vectors */    \
                                                                               \
-        lis     r10,Debug@h;                                                  \
-        ori     r10,r10,Debug@l;                                              \
+        lis     r10,DebugCrit@h;                                                      \
+        ori     r10,r10,DebugCrit@l;                                          \
         cmplw   r12,r10;                                                      \
         bgt+    2f;                     /* addr above exception vectors */    \
                                                                               \
@@ -318,7 +326,6 @@ label:
 2:      mfspr   r4,SPRN_DBSR;                                                 \
         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
-#endif
 
 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
         START_EXCEPTION(InstructionStorage)                                   \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index d9cc2c288d9e..4ff744143566 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -68,7 +68,9 @@ _ENTRY(_start);
         mr      r29,r5
         mr      r28,r6
         mr      r27,r7
+        li      r25,0           /* phys kernel start (low) */
         li      r24,0           /* CPU number */
+        li      r23,0           /* phys kernel start (high) */
 
 /* We try to not make any assumptions about how the boot loader
  * setup or used the TLBs.  We invalidate all mappings from the
@@ -167,7 +169,28 @@ skpinv:	addi	r6,r6,1				/* Increment */
         mtspr   SPRN_MAS0,r7
         tlbre
 
-        /* Just modify the entry ID, EPN and RPN for the temp mapping */
+        /* grab and fixup the RPN */
+        mfspr   r6,SPRN_MAS1    /* extract MAS1[SIZE] */
+        rlwinm  r6,r6,25,27,30
+        li      r8,-1
+        addi    r6,r6,10
+        slw     r6,r8,r6        /* convert to mask */
+
+        bl      1f              /* Find our address */
+1:      mflr    r7
+
+        mfspr   r8,SPRN_MAS3
+#ifdef CONFIG_PHYS_64BIT
+        mfspr   r23,SPRN_MAS7
+#endif
+        and     r8,r6,r8
+        subfic  r9,r6,-4096
+        and     r9,r9,r7
+
+        or      r25,r8,r9
+        ori     r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
+
+        /* Just modify the entry ID and EPN for the temp mapping */
         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
         mtspr   SPRN_MAS0,r7
@@ -177,12 +200,10 @@ skpinv:	addi	r6,r6,1				/* Increment */
         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
         mtspr   SPRN_MAS1,r6
         mfspr   r6,SPRN_MAS2
-        lis     r7,PHYSICAL_START@h
+        li      r7,0            /* temp EPN = 0 */
         rlwimi  r7,r6,0,20,31
         mtspr   SPRN_MAS2,r7
-        mfspr   r6,SPRN_MAS3
-        rlwimi  r7,r6,0,20,31
-        mtspr   SPRN_MAS3,r7
+        mtspr   SPRN_MAS3,r8
         tlbwe
 
         xori    r6,r4,1
@@ -232,8 +253,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
         ori     r6,r6,PAGE_OFFSET@l
         rlwimi  r6,r7,0,20,31
         mtspr   SPRN_MAS2,r6
-        li      r7,(MAS3_SX|MAS3_SW|MAS3_SR)
-        mtspr   SPRN_MAS3,r7
+        mtspr   SPRN_MAS3,r8
         tlbwe
 
 /* 7. Jump to KERNELBASE mapping */
@@ -283,7 +303,10 @@ skpinv:	addi	r6,r6,1				/* Increment */
         SET_IVOR(12, WatchdogTimer);
         SET_IVOR(13, DataTLBError);
         SET_IVOR(14, InstructionTLBError);
-        SET_IVOR(15, Debug);
+        SET_IVOR(15, DebugDebug);
+#if defined(CONFIG_E500)
+        SET_IVOR(15, DebugCrit);
+#endif
         SET_IVOR(32, SPEUnavailable);
         SET_IVOR(33, SPEFloatingPointData);
         SET_IVOR(34, SPEFloatingPointRound);
@@ -718,7 +741,10 @@ interrupt_base:
 
 
         /* Debug Interrupt */
-        DEBUG_EXCEPTION
+        DEBUG_DEBUG_EXCEPTION
+#if defined(CONFIG_E500)
+        DEBUG_CRIT_EXCEPTION
+#endif
 
 /*
  * Local functions
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index 2f50bb5d00f9..9971159c8040 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -183,7 +183,7 @@ static int ibmebus_create_devices(const struct of_device_id *matches)
                 ret = ibmebus_create_device(child);
                 if (ret) {
                         printk(KERN_ERR "%s: failed to create device (%i)",
-                               __FUNCTION__, ret);
+                               __func__, ret);
                         of_node_put(child);
                         break;
                 }
@@ -269,7 +269,7 @@ static ssize_t ibmebus_store_probe(struct bus_type *bus,
         if (bus_find_device(&ibmebus_bus_type, NULL, path,
                             ibmebus_match_path)) {
                 printk(KERN_WARNING "%s: %s has already been probed\n",
-                       __FUNCTION__, path);
+                       __func__, path);
                 rc = -EEXIST;
                 goto out;
         }
@@ -279,7 +279,7 @@ static ssize_t ibmebus_store_probe(struct bus_type *bus,
                 of_node_put(dn);
         } else {
                 printk(KERN_WARNING "%s: no such device node: %s\n",
-                       __FUNCTION__, path);
+                       __func__, path);
                 rc = -ENODEV;
         }
 
@@ -308,7 +308,7 @@ static ssize_t ibmebus_store_remove(struct bus_type *bus,
                 return count;
         } else {
                 printk(KERN_WARNING "%s: %s not on the bus\n",
-                       __FUNCTION__, path);
+                       __func__, path);
 
                 kfree(path);
                 return -ENODEV;
@@ -337,14 +337,14 @@ static int __init ibmebus_bus_init(void)
         err = of_bus_type_init(&ibmebus_bus_type, "ibmebus");
         if (err) {
                 printk(KERN_ERR "%s: failed to register IBM eBus.\n",
-                       __FUNCTION__);
+                       __func__);
                 return err;
         }
 
         err = device_register(&ibmebus_bus_device);
         if (err) {
                 printk(KERN_WARNING "%s: device_register returned %i\n",
-                       __FUNCTION__, err);
+                       __func__, err);
                 bus_unregister(&ibmebus_bus_type);
 
                 return err;
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 8f1f4e539c4b..0c663669bc32 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -520,7 +520,7 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name)
         unsigned int order;
 
         if (!tbl || !tbl->it_map) {
-                printk(KERN_ERR "%s: expected TCE map for %s\n", __FUNCTION__,
+                printk(KERN_ERR "%s: expected TCE map for %s\n", __func__,
                                 node_name);
                 return;
         }
@@ -530,7 +530,7 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name)
         for (i = 0; i < (tbl->it_size/64); i++) {
                 if (tbl->it_map[i] != 0) {
                         printk(KERN_WARNING "%s: Unexpected TCEs for %s\n",
-                                __FUNCTION__, node_name);
+                                __func__, node_name);
                         break;
                 }
         }
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 292163f5b39a..425616f92d18 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -114,7 +114,7 @@ static inline void set_soft_enabled(unsigned long enable)
         : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
 }
 
-void local_irq_restore(unsigned long en)
+void raw_local_irq_restore(unsigned long en)
 {
         /*
          * get_paca()->soft_enabled = en;
@@ -174,6 +174,7 @@ void local_irq_restore(unsigned long en)
 
         __hard_irq_enable();
 }
+EXPORT_SYMBOL(raw_local_irq_restore);
 #endif /* CONFIG_PPC64 */
 
 int show_interrupts(struct seq_file *p, void *v)
@@ -310,8 +311,21 @@ void do_IRQ(struct pt_regs *regs)
                                 handler = &__do_IRQ;
                         irqtp->task = curtp->task;
                         irqtp->flags = 0;
+
+                        /* Copy the softirq bits in preempt_count so that the
+                         * softirq checks work in the hardirq context.
+                         */
+                        irqtp->preempt_count =
+                                (irqtp->preempt_count & ~SOFTIRQ_MASK) |
+                                (curtp->preempt_count & SOFTIRQ_MASK);
+
                         call_handle_irq(irq, desc, irqtp, handler);
                         irqtp->task = NULL;
+
+
+                        /* Set any flag that may have been set on the
+                         * alternate stack
+                         */
                         if (irqtp->flags)
                                 set_bits(irqtp->flags, &curtp->flags);
                 } else
@@ -357,7 +371,7 @@ void irq_ctx_init(void)
                 memset((void *)softirq_ctx[i], 0, THREAD_SIZE);
                 tp = softirq_ctx[i];
                 tp->cpu = i;
-                tp->preempt_count = SOFTIRQ_OFFSET;
+                tp->preempt_count = 0;
 
                 memset((void *)hardirq_ctx[i], 0, THREAD_SIZE);
                 tp = hardirq_ctx[i];
diff --git a/arch/powerpc/kernel/isa-bridge.c b/arch/powerpc/kernel/isa-bridge.c
index ee172aa42aa7..289af348978d 100644
--- a/arch/powerpc/kernel/isa-bridge.c
+++ b/arch/powerpc/kernel/isa-bridge.c
@@ -80,13 +80,13 @@ static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
          *                      (size depending on dev->n_addr_cells)
          *   cell 5:            the size of the range
          */
-        if ((range->isa_addr.a_hi && ISA_SPACE_MASK) != ISA_SPACE_IO) {
+        if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO) {
                 range++;
                 rlen -= sizeof(struct isa_range);
                 if (rlen < sizeof(struct isa_range))
                         goto inval_range;
         }
-        if ((range->isa_addr.a_hi && ISA_SPACE_MASK) != ISA_SPACE_IO)
+        if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO)
                 goto inval_range;
 
         isa_addr = range->isa_addr.a_lo;
@@ -99,7 +99,7 @@ static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
          */
         if ((pci_addr != 0) || (isa_addr != 0)) {
                 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
-                       __FUNCTION__);
+                       __func__);
                 return;
         }
 
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index dcb89a88df46..1ffacc698ffb 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -226,7 +226,7 @@ static void parse_system_parameter_string(struct seq_file *m)
         unsigned char *local_buffer = kmalloc(SPLPAR_MAXLENGTH, GFP_KERNEL);
         if (!local_buffer) {
                 printk(KERN_ERR "%s %s kmalloc failure at line %d \n",
-                       __FILE__, __FUNCTION__, __LINE__);
+                       __FILE__, __func__, __LINE__);
                 return;
         }
 
@@ -243,14 +243,14 @@ static void parse_system_parameter_string(struct seq_file *m)
         if (call_status != 0) {
                 printk(KERN_INFO
                        "%s %s Error calling get-system-parameter (0x%x)\n",
-                       __FILE__, __FUNCTION__, call_status);
+                       __FILE__, __func__, call_status);
         } else {
                 int splpar_strlen;
                 int idx, w_idx;
                 char *workbuffer = kzalloc(SPLPAR_MAXLENGTH, GFP_KERNEL);
                 if (!workbuffer) {
                         printk(KERN_ERR "%s %s kmalloc failure at line %d \n",
-                               __FILE__, __FUNCTION__, __LINE__);
+                               __FILE__, __func__, __LINE__);
                         kfree(local_buffer);
                         return;
                 }
@@ -484,10 +484,10 @@ static ssize_t lparcfg_write(struct file *file, const char __user * buf,
         current_weight = (resource >> 5 * 8) & 0xFF;
 
         pr_debug("%s: current_entitled = %lu, current_weight = %u\n",
-                 __FUNCTION__, current_entitled, current_weight);
+                 __func__, current_entitled, current_weight);
 
         pr_debug("%s: new_entitled = %lu, new_weight = %u\n",
-                 __FUNCTION__, *new_entitled_ptr, *new_weight_ptr);
+                 __func__, *new_entitled_ptr, *new_weight_ptr);
 
         retval = plpar_hcall_norets(H_SET_PPP, *new_entitled_ptr,
                                     *new_weight_ptr);
@@ -502,7 +502,7 @@ static ssize_t lparcfg_write(struct file *file, const char __user * buf,
                 retval = -EINVAL;
         } else {
                 printk(KERN_WARNING "%s: received unknown hv return code %ld",
-                       __FUNCTION__, retval);
+                       __func__, retval);
                 retval = -EIO;
         }
 
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index c0c8e8c3ced9..2d202f274e73 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -12,8 +12,9 @@
 #include <linux/kexec.h>
 #include <linux/reboot.h>
 #include <linux/threads.h>
+#include <linux/lmb.h>
 #include <asm/machdep.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 
 void machine_crash_shutdown(struct pt_regs *regs)
 {
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 55f1a25085cd..ac163bd46cfd 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -15,7 +15,6 @@
 #include <asm/ptrace.h>
 #include <asm/page.h>
 #include <asm/lppaca.h>
-#include <asm/iseries/it_lp_reg_save.h>
 #include <asm/paca.h>
 #include <asm/mmu.h>
 
@@ -25,13 +24,13 @@
 extern unsigned long __toc_start;
 
 /*
- * iSeries structure which the hypervisor knows about - this structure
+ * The structure which the hypervisor knows about - this structure
  * should not cross a page boundary.  The vpa_init/register_vpa call
  * is now known to fail if the lppaca structure crosses a page
- * boundary.  The lppaca is also used on POWER5 pSeries boxes.  The
- * lppaca is 640 bytes long, and cannot readily change since the
- * hypervisor knows its layout, so a 1kB alignment will suffice to
- * ensure that it doesn't cross a page boundary.
+ * boundary.  The lppaca is also used on legacy iSeries and POWER5
+ * pSeries boxes.  The lppaca is 640 bytes long, and cannot readily
+ * change since the hypervisor knows its layout, so a 1kB alignment
+ * will suffice to ensure that it doesn't cross a page boundary.
  */
 struct lppaca lppaca[] = {
         [0 ... (NR_CPUS-1)] = {
@@ -66,32 +65,17 @@ struct slb_shadow slb_shadow[] __cacheline_aligned = {
  * processors.  The processor VPD array needs one entry per physical
  * processor (not thread).
  */
-#define PACA_INIT_COMMON(number)                                            \
+#define PACA_INIT(number)                                                   \
+{                                                                           \
         .lppaca_ptr = &lppaca[number],                                      \
         .lock_token = 0x8000,                                               \
         .paca_index = (number),         /* Paca Index */                    \
         .kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL,             \
         .hw_cpu_id = 0xffff,                                                \
-        .slb_shadow_ptr = &slb_shadow[number],
-
-#ifdef CONFIG_PPC_ISERIES
-#define PACA_INIT_ISERIES(number)                                           \
-        .reg_save_ptr = &iseries_reg_save[number],
-
-#define PACA_INIT(number)                                                   \
-{                                                                           \
-        PACA_INIT_COMMON(number)                                            \
-        PACA_INIT_ISERIES(number)                                           \
+        .slb_shadow_ptr = &slb_shadow[number],                              \
+        .__current = &init_task,                                            \
 }
 
-#else
-#define PACA_INIT(number)                                                   \
-{                                                                           \
-        PACA_INIT_COMMON(number)                                            \
-}
-
-#endif
-
 struct paca_struct paca[] = {
         PACA_INIT(0),
 #if NR_CPUS > 1
diff --git a/arch/powerpc/kernel/ppc32.h b/arch/powerpc/kernel/ppc32.h
index 90e562771791..fda05e2211d6 100644
--- a/arch/powerpc/kernel/ppc32.h
+++ b/arch/powerpc/kernel/ppc32.h
@@ -135,4 +135,6 @@ struct ucontext32 {
         struct mcontext32       uc_mcontext;
 };
 
+extern int copy_siginfo_to_user32(struct compat_siginfo __user *d, siginfo_t *s);
+
 #endif  /* _PPC64_PPC32_H */
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 65d14e6ddc3c..09fcb50c45ae 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -44,10 +44,6 @@
 #include <asm/signal.h>
 #include <asm/dcr.h>
 
-#ifdef CONFIG_PPC64
-EXPORT_SYMBOL(local_irq_restore);
-#endif
-
 #ifdef CONFIG_PPC32
 extern void transfer_to_handler(void);
 extern void do_IRQ(struct pt_regs *regs);
@@ -57,7 +53,6 @@ extern void program_check_exception(struct pt_regs *regs);
 extern void single_step_exception(struct pt_regs *regs);
 extern int sys_sigreturn(struct pt_regs *regs);
 
-EXPORT_SYMBOL(empty_zero_page);
 EXPORT_SYMBOL(clear_pages);
 EXPORT_SYMBOL(copy_page);
 EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
@@ -78,6 +73,7 @@ EXPORT_SYMBOL(strncpy);
 EXPORT_SYMBOL(strcat);
 EXPORT_SYMBOL(strlen);
 EXPORT_SYMBOL(strcmp);
+EXPORT_SYMBOL(strncmp);
 
 EXPORT_SYMBOL(csum_partial);
 EXPORT_SYMBOL(csum_partial_copy_generic);
@@ -191,3 +187,4 @@ EXPORT_SYMBOL(intercept_table);
 EXPORT_SYMBOL(__mtdcr);
 EXPORT_SYMBOL(__mfdcr);
 #endif
+EXPORT_SYMBOL(empty_zero_page);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 4ec605521504..703100d5e458 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -868,11 +868,6 @@ int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
         flush_spe_to_thread(current);
         error = do_execve(filename, (char __user * __user *) a1,
                           (char __user * __user *) a2, regs);
-        if (error == 0) {
-                task_lock(current);
-                current->ptrace &= ~PT_DTRACE;
-                task_unlock(current);
-        }
         putname(filename);
 out:
         return error;
@@ -919,20 +914,6 @@ int validate_sp(unsigned long sp, struct task_struct *p,
         return valid_irq_stack(sp, p, nbytes);
 }
 
-#ifdef CONFIG_PPC64
-#define MIN_STACK_FRAME 112     /* same as STACK_FRAME_OVERHEAD, in fact */
-#define FRAME_LR_SAVE   2
-#define INT_FRAME_SIZE  (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD + 288)
-#define REGS_MARKER     0x7265677368657265ul
-#define FRAME_MARKER    12
-#else
-#define MIN_STACK_FRAME 16
-#define FRAME_LR_SAVE   1
-#define INT_FRAME_SIZE  (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
-#define REGS_MARKER     0x72656773ul
-#define FRAME_MARKER    2
-#endif
-
 EXPORT_SYMBOL(validate_sp);
 
 unsigned long get_wchan(struct task_struct *p)
@@ -944,15 +925,15 @@ unsigned long get_wchan(struct task_struct *p)
                 return 0;
 
         sp = p->thread.ksp;
-        if (!validate_sp(sp, p, MIN_STACK_FRAME))
+        if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
                 return 0;
 
         do {
                 sp = *(unsigned long *)sp;
-                if (!validate_sp(sp, p, MIN_STACK_FRAME))
+                if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
                         return 0;
                 if (count > 0) {
-                        ip = ((unsigned long *)sp)[FRAME_LR_SAVE];
+                        ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
                         if (!in_sched_functions(ip))
                                 return ip;
                 }
@@ -981,12 +962,12 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
         lr = 0;
         printk("Call Trace:\n");
         do {
-                if (!validate_sp(sp, tsk, MIN_STACK_FRAME))
+                if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
                         return;
 
                 stack = (unsigned long *) sp;
                 newsp = stack[0];
-                ip = stack[FRAME_LR_SAVE];
+                ip = stack[STACK_FRAME_LR_SAVE];
                 if (!firstframe || ip != lr) {
                         printk("["REG"] ["REG"] ", sp, ip);
                         print_symbol("%s", ip);
@@ -1000,8 +981,8 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
                  * See if this is an exception frame.
                  * We look for the "regshere" marker in the current frame.
                  */
-                if (validate_sp(sp, tsk, INT_FRAME_SIZE)
-                    && stack[FRAME_MARKER] == REGS_MARKER) {
+                if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
+                    && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
                         struct pt_regs *regs = (struct pt_regs *)
                                 (sp + STACK_FRAME_OVERHEAD);
                         printk("--- Exception: %lx", regs->trap);
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index eac97f48b9b8..3bfe7837e820 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -31,10 +31,10 @@
 #include <linux/kexec.h>
 #include <linux/debugfs.h>
 #include <linux/irq.h>
+#include <linux/lmb.h>
 
 #include <asm/prom.h>
 #include <asm/rtas.h>
-#include <asm/lmb.h>
 #include <asm/page.h>
 #include <asm/processor.h>
 #include <asm/irq.h>
@@ -51,6 +51,7 @@
 #include <asm/machdep.h>
 #include <asm/pSeries_reconfig.h>
 #include <asm/pci-bridge.h>
+#include <asm/phyp_dump.h>
 #include <asm/kexec.h>
 
 #ifdef DEBUG
@@ -436,7 +437,7 @@ early_param("mem", early_parse_mem);
  * The device tree may be allocated beyond our memory limit, or inside the
  * crash kernel region for kdump. If so, move it out of the way.
  */
-static void move_device_tree(void)
+static void __init move_device_tree(void)
 {
         unsigned long start, size;
         void *p;
@@ -1040,6 +1041,87 @@ static void __init early_reserve_mem(void)
 #endif
 }
 
+#ifdef CONFIG_PHYP_DUMP
+/**
+ * phyp_dump_calculate_reserve_size() - reserve variable boot area 5% or arg
+ *
+ * Function to find the largest size we need to reserve
+ * during early boot process.
+ *
+ * It either looks for boot param and returns that OR
+ * returns larger of 256 or 5% rounded down to multiples of 256MB.
+ *
+ */
+static inline unsigned long phyp_dump_calculate_reserve_size(void)
+{
+        unsigned long tmp;
+
+        if (phyp_dump_info->reserve_bootvar)
+                return phyp_dump_info->reserve_bootvar;
+
+        /* divide by 20 to get 5% of value */
+        tmp = lmb_end_of_DRAM();
+        do_div(tmp, 20);
+
+        /* round it down in multiples of 256 */
+        tmp = tmp & ~0x0FFFFFFFUL;
+
+        return (tmp > PHYP_DUMP_RMR_END ? tmp : PHYP_DUMP_RMR_END);
+}
+
+/**
+ * phyp_dump_reserve_mem() - reserve all not-yet-dumped mmemory
+ *
+ * This routine may reserve memory regions in the kernel only
+ * if the system is supported and a dump was taken in last
+ * boot instance or if the hardware is supported and the
+ * scratch area needs to be setup. In other instances it returns
+ * without reserving anything. The memory in case of dump being
+ * active is freed when the dump is collected (by userland tools).
+ */
+static void __init phyp_dump_reserve_mem(void)
+{
+        unsigned long base, size;
+        unsigned long variable_reserve_size;
+
+        if (!phyp_dump_info->phyp_dump_configured) {
+                printk(KERN_ERR "Phyp-dump not supported on this hardware\n");
+                return;
+        }
+
+        if (!phyp_dump_info->phyp_dump_at_boot) {
+                printk(KERN_INFO "Phyp-dump disabled at boot time\n");
+                return;
+        }
+
+        variable_reserve_size = phyp_dump_calculate_reserve_size();
+
+        if (phyp_dump_info->phyp_dump_is_active) {
+                /* Reserve *everything* above RMR.Area freed by userland tools*/
+                base = variable_reserve_size;
+                size = lmb_end_of_DRAM() - base;
+
+                /* XXX crashed_ram_end is wrong, since it may be beyond
+                 * the memory_limit, it will need to be adjusted. */
+                lmb_reserve(base, size);
+
+                phyp_dump_info->init_reserve_start = base;
+                phyp_dump_info->init_reserve_size = size;
+        } else {
+                size = phyp_dump_info->cpu_state_size +
+                        phyp_dump_info->hpte_region_size +
+                        variable_reserve_size;
+                base = lmb_end_of_DRAM() - size;
+                lmb_reserve(base, size);
+                phyp_dump_info->init_reserve_start = base;
+                phyp_dump_info->init_reserve_size = size;
+        }
+}
+#else
+static inline void __init phyp_dump_reserve_mem(void) {}
+#endif /* CONFIG_PHYP_DUMP  && CONFIG_PPC_RTAS */
+
+
 void __init early_init_devtree(void *params)
 {
         DBG(" -> early_init_devtree(%p)\n", params);
@@ -1052,6 +1134,11 @@ void __init early_init_devtree(void *params)
         of_scan_flat_dt(early_init_dt_scan_rtas, NULL);
 #endif
 
+#ifdef CONFIG_PHYP_DUMP
+        /* scan tree to see if dump occured during last boot */
+        of_scan_flat_dt(early_init_dt_scan_phyp_dump, NULL);
+#endif
+
         /* Retrieve various informations from the /chosen node of the
          * device-tree, including the platform type, initrd location and
          * size, TCE reserve, and more ...
@@ -1072,6 +1159,7 @@ void __init early_init_devtree(void *params)
         reserve_kdump_trampoline();
         reserve_crashkernel();
         early_reserve_mem();
+        phyp_dump_reserve_mem();
 
         lmb_enforce_memory_limit(memory_limit);
         lmb_analyze();
@@ -1244,12 +1332,14 @@ EXPORT_SYMBOL(of_node_put);
  */
 void of_attach_node(struct device_node *np)
 {
-        write_lock(&devtree_lock);
+        unsigned long flags;
+
+        write_lock_irqsave(&devtree_lock, flags);
         np->sibling = np->parent->child;
         np->allnext = allnodes;
         np->parent->child = np;
         allnodes = np;
-        write_unlock(&devtree_lock);
+        write_unlock_irqrestore(&devtree_lock, flags);
 }
 
 /*
@@ -1260,8 +1350,9 @@ void of_attach_node(struct device_node *np)
 void of_detach_node(struct device_node *np)
 {
         struct device_node *parent;
+        unsigned long flags;
 
-        write_lock(&devtree_lock);
+        write_lock_irqsave(&devtree_lock, flags);
 
         parent = np->parent;
         if (!parent)
@@ -1292,7 +1383,7 @@ void of_detach_node(struct device_node *np)
         of_node_set_flag(np, OF_DETACHED);
 
 out_unlock:
-        write_unlock(&devtree_lock);
+        write_unlock_irqrestore(&devtree_lock, flags);
 }
 
 #ifdef CONFIG_PPC_PSERIES
@@ -1373,20 +1464,21 @@ __initcall(prom_reconfig_setup);
 int prom_add_property(struct device_node* np, struct property* prop)
 {
         struct property **next;
+        unsigned long flags;
 
         prop->next = NULL;      
-        write_lock(&devtree_lock);
+        write_lock_irqsave(&devtree_lock, flags);
         next = &np->properties;
         while (*next) {
                 if (strcmp(prop->name, (*next)->name) == 0) {
                         /* duplicate ! don't insert it */
-                        write_unlock(&devtree_lock);
+                        write_unlock_irqrestore(&devtree_lock, flags);
                         return -1;
                 }
                 next = &(*next)->next;
         }
         *next = prop;
-        write_unlock(&devtree_lock);
+        write_unlock_irqrestore(&devtree_lock, flags);
 
 #ifdef CONFIG_PROC_DEVICETREE
         /* try to add to proc as well if it was initialized */
@@ -1406,9 +1498,10 @@ int prom_add_property(struct device_node* np, struct property* prop)
 int prom_remove_property(struct device_node *np, struct property *prop)
 {
         struct property **next;
+        unsigned long flags;
         int found = 0;
 
-        write_lock(&devtree_lock);
+        write_lock_irqsave(&devtree_lock, flags);
         next = &np->properties;
         while (*next) {
                 if (*next == prop) {
@@ -1421,7 +1514,7 @@ int prom_remove_property(struct device_node *np, struct property *prop)
                 }
                 next = &(*next)->next;
         }
-        write_unlock(&devtree_lock);
+        write_unlock_irqrestore(&devtree_lock, flags);
 
         if (!found)
                 return -ENODEV;
@@ -1447,9 +1540,10 @@ int prom_update_property(struct device_node *np,
                          struct property *oldprop)
 {
         struct property **next;
+        unsigned long flags;
         int found = 0;
 
-        write_lock(&devtree_lock);
+        write_lock_irqsave(&devtree_lock, flags);
         next = &np->properties;
         while (*next) {
                 if (*next == oldprop) {
@@ -1463,7 +1557,7 @@ int prom_update_property(struct device_node *np,
                 }
                 next = &(*next)->next;
         }
-        write_unlock(&devtree_lock);
+        write_unlock_irqrestore(&devtree_lock, flags);
 
         if (!found)
                 return -ENODEV;
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 5ab4c8466cc9..6d6df1e60325 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2240,6 +2240,14 @@ static void __init fixup_device_tree_efika(void)
         if (rv != PROM_ERROR && (strcmp(prop, "chrp") == 0))
                 prom_setprop(node, "/", "device_type", "efika", sizeof("efika"));
 
+        /* CODEGEN,description is exposed in /proc/cpuinfo so
+           fix that too */
+        rv = prom_getprop(node, "CODEGEN,description", prop, sizeof(prop));
+        if (rv != PROM_ERROR && (strstr(prop, "CHRP")))
+                prom_setprop(node, "/", "CODEGEN,description",
+                             "Efika 5200B PowerPC System",
+                             sizeof("Efika 5200B PowerPC System"));
+
         /* Fixup bestcomm interrupts property */
         node = call_prom("finddevice", 1, 1, ADDR("/builtin/bestcomm"));
         if (PHANDLE_VALID(node)) {
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c
index 4c1de6af4c09..9d30e10970ac 100644
--- a/arch/powerpc/kernel/ptrace32.c
+++ b/arch/powerpc/kernel/ptrace32.c
@@ -29,12 +29,15 @@
 #include <linux/security.h>
 #include <linux/signal.h>
 #include <linux/compat.h>
+#include <linux/elf.h>
 
 #include <asm/uaccess.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
 
+#include "ppc32.h"
+
 /*
  * does not yet catch signals sent when the child dies.
  * in exit.c or in signal.c.
@@ -64,6 +67,27 @@ static long compat_ptrace_old(struct task_struct *child, long request,
         return -EPERM;
 }
 
+static int compat_ptrace_getsiginfo(struct task_struct *child, compat_siginfo_t __user *data)
+{
+        siginfo_t lastinfo;
+        int error = -ESRCH;
+
+        read_lock(&tasklist_lock);
+        if (likely(child->sighand != NULL)) {
+                error = -EINVAL;
+                spin_lock_irq(&child->sighand->siglock);
+                if (likely(child->last_siginfo != NULL)) {
+                        lastinfo = *child->last_siginfo;
+                        error = 0;
+                }
+                spin_unlock_irq(&child->sighand->siglock);
+        }
+        read_unlock(&tasklist_lock);
+        if (!error)
+                return copy_siginfo_to_user32(data, &lastinfo);
+        return error;
+}
+
 long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         compat_ulong_t caddr, compat_ulong_t cdata)
 {
@@ -282,6 +306,9 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         0, PT_REGS_COUNT * sizeof(compat_long_t),
                         compat_ptr(data));
 
+        case PTRACE_GETSIGINFO:
+                return compat_ptrace_getsiginfo(child, compat_ptr(data));
+
         case PTRACE_GETFPREGS:
         case PTRACE_SETFPREGS:
         case PTRACE_GETVRREGS:
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 52e95c2158c0..34843c318419 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -22,11 +22,11 @@
 #include <linux/smp.h>
 #include <linux/completion.h>
 #include <linux/cpumask.h>
+#include <linux/lmb.h>
 
 #include <asm/prom.h>
 #include <asm/rtas.h>
 #include <asm/hvcall.h>
-#include <asm/semaphore.h>
 #include <asm/machdep.h>
 #include <asm/firmware.h>
 #include <asm/page.h>
@@ -34,7 +34,6 @@
 #include <asm/system.h>
 #include <asm/delay.h>
 #include <asm/uaccess.h>
-#include <asm/lmb.h>
 #include <asm/udbg.h>
 #include <asm/syscalls.h>
 #include <asm/smp.h>
@@ -507,7 +506,7 @@ int rtas_error_rc(int rtas_rc)
                         break;
                 default:
                         printk(KERN_ERR "%s: unexpected RTAS error %d\n",
-                                        __FUNCTION__, rtas_rc);
+                                        __func__, rtas_rc);
                         rc = -ERANGE;
                         break;
         }
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index 538baf46f15f..627f126d1848 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -807,7 +807,7 @@ int __init rtas_flash_init(void)
                                 rtas_block_ctor);
         if (!flash_block_cache) {
                 printk(KERN_ERR "%s: failed to create block cache\n",
-                                __FUNCTION__);
+                                __func__);
                 rc = -ENOMEM;
                 goto cleanup;
         }
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 433a0a0949fb..3ab88a9dc70d 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -56,21 +56,6 @@ static inline int config_access_valid(struct pci_dn *dn, int where)
         return 0;
 }
 
-static int of_device_available(struct device_node * dn)
-{
-        const char *status;
-
-        status = of_get_property(dn, "status", NULL);
-
-        if (!status)
-                return 1;
-
-        if (!strcmp(status, "okay"))
-                return 1;
-
-        return 0;
-}
-
 int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
 {
         int returnval = -1;
@@ -117,7 +102,7 @@ static int rtas_pci_read_config(struct pci_bus *bus,
         for (dn = busdn->child; dn; dn = dn->sibling) {
                 struct pci_dn *pdn = PCI_DN(dn);
                 if (pdn && pdn->devfn == devfn
-                    && of_device_available(dn))
+                    && of_device_is_available(dn))
                         return rtas_read_config(pdn, where, size, val);
         }
 
@@ -164,7 +149,7 @@ static int rtas_pci_write_config(struct pci_bus *bus,
         for (dn = busdn->child; dn; dn = dn->sibling) {
                 struct pci_dn *pdn = PCI_DN(dn);
                 if (pdn && pdn->devfn == devfn
-                    && of_device_available(dn))
+                    && of_device_is_available(dn))
                         return rtas_write_config(pdn, where, size, val);
         }
         return PCIBIOS_DEVICE_NOT_FOUND;
@@ -326,7 +311,7 @@ int pcibios_remove_root_bus(struct pci_controller *phb)
 
         res = b->resource[0];
         if (!res->flags) {
-                printk(KERN_ERR "%s: no IO resource for PHB %s\n", __FUNCTION__,
+                printk(KERN_ERR "%s: no IO resource for PHB %s\n", __func__,
                                 b->name);
                 return 1;
         }
@@ -334,13 +319,13 @@ int pcibios_remove_root_bus(struct pci_controller *phb)
         rc = pcibios_unmap_io_space(b);
         if (rc) {
                 printk(KERN_ERR "%s: failed to unmap IO on bus %s\n",
-                        __FUNCTION__, b->name);
+                        __func__, b->name);
                 return 1;
         }
 
         if (release_resource(res)) {
                 printk(KERN_ERR "%s: failed to release IO on bus %s\n",
-                                __FUNCTION__, b->name);
+                                __func__, b->name);
                 return 1;
         }
 
@@ -348,13 +333,13 @@ int pcibios_remove_root_bus(struct pci_controller *phb)
                 res = b->resource[i];
                 if (!res->flags && i == 0) {
                         printk(KERN_ERR "%s: no MEM resource for PHB %s\n",
-                                __FUNCTION__, b->name);
+                                __func__, b->name);
                         return 1;
                 }
                 if (res->flags && release_resource(res)) {
                         printk(KERN_ERR
                                "%s: failed to release IO %d on bus %s\n",
-                                __FUNCTION__, i, b->name);
+                                __func__, i, b->name);
                         return 1;
                 }
         }
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 6adb5a1e98bb..db540eab09f4 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -34,6 +34,7 @@
 #include <linux/serial_8250.h>
 #include <linux/debugfs.h>
 #include <linux/percpu.h>
+#include <linux/lmb.h>
 #include <asm/io.h>
 #include <asm/prom.h>
 #include <asm/processor.h>
@@ -56,7 +57,6 @@
 #include <asm/cache.h>
 #include <asm/page.h>
 #include <asm/mmu.h>
-#include <asm/lmb.h>
 #include <asm/xmon.h>
 #include <asm/cputhreads.h>
 
@@ -167,6 +167,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         unsigned short min;
 
         if (cpu_id == NR_CPUS) {
+                struct device_node *root;
+                const char *model = NULL;
 #if defined(CONFIG_SMP) && defined(CONFIG_PPC32)
                 unsigned long bogosum = 0;
                 int i;
@@ -178,6 +180,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 seq_printf(m, "timebase\t: %lu\n", ppc_tb_freq);
                 if (ppc_md.name)
                         seq_printf(m, "platform\t: %s\n", ppc_md.name);
+                root = of_find_node_by_path("/");
+                if (root)
+                        model = of_get_property(root, "model", NULL);
+                if (model)
+                        seq_printf(m, "model\t\t: %s\n", model);
+                of_node_put(root);
+
                 if (ppc_md.show_cpuinfo != NULL)
                         ppc_md.show_cpuinfo(m);
 
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 06d918d94dd1..36f6779c88d4 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -164,6 +164,18 @@ int __init ppc_setup_l2cr(char *str)
 }
 __setup("l2cr=", ppc_setup_l2cr);
 
+/* Checks "l3cr=xxxx" command-line option */
+int __init ppc_setup_l3cr(char *str)
+{
+        if (cpu_has_feature(CPU_FTR_L3CR)) {
+                unsigned long val = simple_strtoul(str, NULL, 0);
+                printk(KERN_INFO "l3cr set to %lx\n", val);
+                _set_L3CR(val);         /* and enable it */
+        }
+        return 1;
+}
+__setup("l3cr=", ppc_setup_l3cr);
+
 #ifdef CONFIG_GENERIC_NVRAM
 
 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
@@ -269,7 +281,7 @@ void __init setup_arch(char **cmdline_p)
         if (ppc_md.panic)
                 setup_panic();
 
-        init_mm.start_code = PAGE_OFFSET;
+        init_mm.start_code = (unsigned long)_stext;
         init_mm.end_code = (unsigned long) _etext;
         init_mm.end_data = (unsigned long) _edata;
         init_mm.brk = klimit;
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 3b1529c103ef..31ada9fdfc5c 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -33,6 +33,8 @@
 #include <linux/serial_8250.h>
 #include <linux/bootmem.h>
 #include <linux/pci.h>
+#include <linux/lockdep.h>
+#include <linux/lmb.h>
 #include <asm/io.h>
 #include <asm/kdump.h>
 #include <asm/prom.h>
@@ -55,7 +57,6 @@
 #include <asm/cache.h>
 #include <asm/page.h>
 #include <asm/mmu.h>
-#include <asm/lmb.h>
 #include <asm/firmware.h>
 #include <asm/xmon.h>
 #include <asm/udbg.h>
@@ -178,6 +179,9 @@ void __init early_setup(unsigned long dt_ptr)
         /* Enable early debugging if any specified (see udbg.h) */
         udbg_early_init();
 
+        /* Initialize lockdep early or else spinlocks will blow */
+        lockdep_init();
+
         DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
 
         /*
@@ -510,7 +514,7 @@ void __init setup_arch(char **cmdline_p)
         if (ppc_md.panic)
                 setup_panic();
 
-        init_mm.start_code = PAGE_OFFSET;
+        init_mm.start_code = (unsigned long)_stext;
         init_mm.end_code = (unsigned long) _etext;
         init_mm.end_data = (unsigned long) _edata;
         init_mm.brk = klimit;
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index d840bc772fd3..ad6943468ee9 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -621,6 +621,18 @@ int copy_siginfo_to_user32(struct compat_siginfo __user *d, siginfo_t *s)
 
 #define copy_siginfo_to_user    copy_siginfo_to_user32
 
+int copy_siginfo_from_user32(siginfo_t *to, struct compat_siginfo __user *from)
+{
+        memset(to, 0, sizeof *to);
+
+        if (copy_from_user(to, from, 3*sizeof(int)) ||
+            copy_from_user(to->_sifields._pad,
+                           from->_sifields._pad, SI_PAD_SIZE32))
+                return -EFAULT;
+
+        return 0;
+}
+
 /*
  * Note: it is necessary to treat pid and sig as unsigned ints, with the
  * corresponding cast to a signed int to insure that the proper conversion
@@ -634,9 +646,10 @@ long compat_sys_rt_sigqueueinfo(u32 pid, u32 sig, compat_siginfo_t __user *uinfo
         int ret;
         mm_segment_t old_fs = get_fs();
 
-        if (copy_from_user (&info, uinfo, 3*sizeof(int)) ||
-            copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE32))
-                return -EFAULT;
+        ret = copy_siginfo_from_user32(&info, uinfo);
+        if (unlikely(ret))
+                return ret;
+
         set_fs (KERNEL_DS);
         /* The __user pointer cast is valid becasuse of the set_fs() */
         ret = sys_rt_sigqueueinfo((int)pid, (int)sig, (siginfo_t __user *) &info);
diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
new file mode 100644
index 000000000000..e3638eeaaae7
--- /dev/null
+++ b/arch/powerpc/kernel/stacktrace.c
@@ -0,0 +1,47 @@
+/*
+ * Stack trace utility
+ *
+ * Copyright 2008 Christoph Hellwig, IBM Corp.
+ *
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+
+/*
+ * Save stack-backtrace addresses into a stack_trace buffer.
+ */
+void save_stack_trace(struct stack_trace *trace)
+{
+        unsigned long sp;
+
+        asm("mr %0,1" : "=r" (sp));
+
+        for (;;) {
+                unsigned long *stack = (unsigned long *) sp;
+                unsigned long newsp, ip;
+
+                if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD))
+                        return;
+
+                newsp = stack[0];
+                ip = stack[STACK_FRAME_LR_SAVE];
+
+                if (!trace->skip)
+                        trace->entries[trace->nr_entries++] = ip;
+                else
+                        trace->skip--;
+
+                if (trace->nr_entries >= trace->max_entries)
+                        return;
+
+                sp = newsp;
+        }
+}
diff --git a/arch/powerpc/kernel/sys_ppc32.c b/arch/powerpc/kernel/sys_ppc32.c
index 4a4f5c6b560b..709f8cb8bfca 100644
--- a/arch/powerpc/kernel/sys_ppc32.c
+++ b/arch/powerpc/kernel/sys_ppc32.c
@@ -47,7 +47,6 @@
 #include <asm/types.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
-#include <asm/semaphore.h>
 #include <asm/time.h>
 #include <asm/mmu_context.h>
 #include <asm/ppc-pci.h>
@@ -368,11 +367,6 @@ long compat_sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
 
         error = compat_do_execve(filename, compat_ptr(a1), compat_ptr(a2), regs);
 
-        if (error == 0) {
-                task_lock(current);
-                current->ptrace &= ~PT_DTRACE;
-                task_unlock(current);
-        }
         putname(filename);
 
 out:
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
index 3b1d5dd65643..e722a4eeb5d0 100644
--- a/arch/powerpc/kernel/syscalls.c
+++ b/arch/powerpc/kernel/syscalls.c
@@ -38,7 +38,6 @@
 #include <linux/personality.h>
 
 #include <asm/uaccess.h>
-#include <asm/semaphore.h>
 #include <asm/syscalls.h>
 #include <asm/time.h>
 #include <asm/unistd.h>
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index d3437c4c4a6f..c21a626af676 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -21,13 +21,14 @@
 #include <linux/elf.h>
 #include <linux/security.h>
 #include <linux/bootmem.h>
+#include <linux/lmb.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/mmu_context.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/cputable.h>
 #include <asm/sections.h>
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index f98867252ee2..b77f8af7ddde 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -139,7 +139,7 @@ static int vio_bus_remove(struct device *dev)
  */
 int vio_register_driver(struct vio_driver *viodrv)
 {
-        printk(KERN_DEBUG "%s: driver %s registering\n", __FUNCTION__,
+        printk(KERN_DEBUG "%s: driver %s registering\n", __func__,
                 viodrv->driver.name);
 
         /* fill in 'struct driver' fields */
@@ -184,7 +184,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
         /* we need the 'device_type' property, in order to match with drivers */
         if (of_node->type == NULL) {
                 printk(KERN_WARNING "%s: node %s missing 'device_type'\n",
-                                __FUNCTION__,
+                                __func__,
                                 of_node->name ? of_node->name : "<unknown>");
                 return NULL;
         }
@@ -192,7 +192,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
         unit_address = of_get_property(of_node, "reg", NULL);
         if (unit_address == NULL) {
                 printk(KERN_WARNING "%s: node %s missing 'reg'\n",
-                                __FUNCTION__,
+                                __func__,
                                 of_node->name ? of_node->name : "<unknown>");
                 return NULL;
         }
@@ -227,7 +227,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
         /* register with generic device framework */
         if (device_register(&viodev->dev)) {
                 printk(KERN_ERR "%s: failed to register device %s\n",
-                                __FUNCTION__, viodev->dev.bus_id);
+                                __func__, viodev->dev.bus_id);
                 /* XXX free TCE table */
                 kfree(viodev);
                 return NULL;
@@ -258,7 +258,7 @@ static int __init vio_bus_init(void)
         err = device_register(&vio_bus_device.dev);
         if (err) {
                 printk(KERN_WARNING "%s: device_register returned %i\n",
-                                __FUNCTION__, err);
+                                __func__, err);
                 return err;
         }
 
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 0afb9e31d2a0..0c3000bf8d75 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -1,11 +1,9 @@
 #ifdef CONFIG_PPC64
-#include <asm/page.h>
 #define PROVIDE32(x)    PROVIDE(__unused__##x)
 #else
-#define PAGE_SIZE       4096
-#define KERNELBASE      CONFIG_KERNEL_START
 #define PROVIDE32(x)    PROVIDE(x)
 #endif
+#include <asm/page.h>
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/cache.h>
 
@@ -33,7 +31,7 @@ SECTIONS
  */
 
         /* Text and gots */
-        .text : {
+        .text : AT(ADDR(.text) - LOAD_OFFSET) {
                 ALIGN_FUNCTION();
                 *(.text.head)
                 _text = .;
@@ -58,7 +56,7 @@ SECTIONS
         RODATA
 
         /* Exception & bug tables */
-        __ex_table : {
+        __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
                 __start___ex_table = .;
                 *(__ex_table)
                 __stop___ex_table = .;
@@ -74,7 +72,7 @@ SECTIONS
         . = ALIGN(PAGE_SIZE);
         __init_begin = .;
 
-        .init.text : {
+        .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
                 _sinittext = .;
                 INIT_TEXT
                 _einittext = .;
@@ -83,11 +81,11 @@ SECTIONS
         /* .exit.text is discarded at runtime, not link time,
          * to deal with references from __bug_table
          */
-        .exit.text : {
+        .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
                 EXIT_TEXT
         }
 
-        .init.data : {
+        .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
                 INIT_DATA
                 __vtop_table_begin = .;
                 *(.vtop_fixup);
@@ -103,19 +101,19 @@ SECTIONS
         }
 
         . = ALIGN(16);
-        .init.setup : {
+        .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
                 __setup_start = .;
                 *(.init.setup)
                 __setup_end = .;
         }
 
-        .initcall.init : {
+        .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
                 __initcall_start = .;
                 INITCALLS
                 __initcall_end = .;
                 }
 
-        .con_initcall.init : {
+        .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
                 __con_initcall_start = .;
                 *(.con_initcall.init)
                 __con_initcall_end = .;
@@ -124,14 +122,14 @@ SECTIONS
         SECURITY_INIT
 
         . = ALIGN(8);
-        __ftr_fixup : {
+        __ftr_fixup : AT(ADDR(__ftr_fixup) - LOAD_OFFSET) {
                 __start___ftr_fixup = .;
                 *(__ftr_fixup)
                 __stop___ftr_fixup = .;
         }
 #ifdef CONFIG_PPC64
         . = ALIGN(8);
-        __fw_ftr_fixup : {
+        __fw_ftr_fixup : AT(ADDR(__fw_ftr_fixup) - LOAD_OFFSET) {
                 __start___fw_ftr_fixup = .;
                 *(__fw_ftr_fixup)
                 __stop___fw_ftr_fixup = .;
@@ -139,14 +137,14 @@ SECTIONS
 #endif
 #ifdef CONFIG_BLK_DEV_INITRD
         . = ALIGN(PAGE_SIZE);
-        .init.ramfs : {
+        .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
                 __initramfs_start = .;
                 *(.init.ramfs)
                 __initramfs_end = .;
         }
 #endif
         . = ALIGN(PAGE_SIZE);
-        .data.percpu : {
+        .data.percpu  : AT(ADDR(.data.percpu) - LOAD_OFFSET) {
                 __per_cpu_start = .;
                 *(.data.percpu)
                 *(.data.percpu.shared_aligned)
@@ -154,7 +152,7 @@ SECTIONS
         }
 
         . = ALIGN(8);
-        .machine.desc : {
+        .machine.desc : AT(ADDR(.machine.desc) - LOAD_OFFSET) {
                 __machine_desc_start = . ;
                 *(.machine.desc)
                 __machine_desc_end = . ;
@@ -172,25 +170,24 @@ SECTIONS
         _sdata = .;
 
 #ifdef CONFIG_PPC32
-        .data    :
-        {
+        .data : AT(ADDR(.data) - LOAD_OFFSET) {
                 DATA_DATA
                 *(.sdata)
                 *(.got.plt) *(.got)
         }
 #else
-        .data : {
+        .data : AT(ADDR(.data) - LOAD_OFFSET) {
                 DATA_DATA
                 *(.data.rel*)
                 *(.toc1)
                 *(.branch_lt)
         }
 
-        .opd : {
+        .opd : AT(ADDR(.opd) - LOAD_OFFSET) {
                 *(.opd)
         }
 
-        .got : {
+        .got : AT(ADDR(.got) - LOAD_OFFSET) {
                 __toc_start = .;
                 *(.got)
                 *(.toc)
@@ -207,26 +204,26 @@ SECTIONS
 #else
         . = ALIGN(16384);
 #endif
-        .data.init_task : {
+        .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) {
                 *(.data.init_task)
         }
 
         . = ALIGN(PAGE_SIZE);
-        .data.page_aligned : {
+        .data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET) {
                 *(.data.page_aligned)
         }
 
-        .data.cacheline_aligned : {
+        .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
                 *(.data.cacheline_aligned)
         }
 
         . = ALIGN(L1_CACHE_BYTES);
-        .data.read_mostly : {
+        .data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET) {
                 *(.data.read_mostly)
         }
 
         . = ALIGN(PAGE_SIZE);
-        __data_nosave : {
+        .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
                 __nosave_begin = .;
                 *(.data.nosave)
                 . = ALIGN(PAGE_SIZE);
@@ -237,7 +234,7 @@ SECTIONS
  * And finally the bss
  */
 
-        .bss : {
+        .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
                 __bss_start = .;
                 *(.sbss) *(.scommon)
                 *(.dynbss)
diff --git a/arch/powerpc/lib/rheap.c b/arch/powerpc/lib/rheap.c
index 22c3b4f53de7..29b2941cada0 100644
--- a/arch/powerpc/lib/rheap.c
+++ b/arch/powerpc/lib/rheap.c
@@ -54,7 +54,7 @@ static int grow(rh_info_t * info, int max_blocks)
 
         new_blocks = max_blocks - info->max_blocks;
 
-        block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_KERNEL);
+        block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_ATOMIC);
         if (block == NULL)
                 return -ENOMEM;
 
@@ -258,7 +258,7 @@ rh_info_t *rh_create(unsigned int alignment)
         if ((alignment & (alignment - 1)) != 0)
                 return ERR_PTR(-EINVAL);
 
-        info = kmalloc(sizeof(*info), GFP_KERNEL);
+        info = kmalloc(sizeof(*info), GFP_ATOMIC);
         if (info == NULL)
                 return ERR_PTR(-ENOMEM);
 
diff --git a/arch/powerpc/lib/string.S b/arch/powerpc/lib/string.S
index c4c622d8e6ac..49eb1f1a2bb4 100644
--- a/arch/powerpc/lib/string.S
+++ b/arch/powerpc/lib/string.S
@@ -75,6 +75,20 @@ _GLOBAL(strcmp)
         beq     1b
         blr
 
+_GLOBAL(strncmp)
+        PPC_LCMPI r5,0
+        beqlr
+        mtctr   r5
+        addi    r5,r3,-1
+        addi    r4,r4,-1
+1:      lbzu    r3,1(r5)
+        cmpwi   1,r3,0
+        lbzu    r0,1(r4)
+        subf.   r3,r0,r3
+        beqlr   1
+        bdnzt   eq,1b
+        blr
+
 _GLOBAL(strlen)
         addi    r4,r3,-1
 1:      lbzu    r0,1(r4)
diff --git a/arch/powerpc/math-emu/fabs.c b/arch/powerpc/math-emu/fabs.c
index 41f0617f3d3a..549baba5948f 100644
--- a/arch/powerpc/math-emu/fabs.c
+++ b/arch/powerpc/math-emu/fabs.c
@@ -9,7 +9,7 @@ fabs(u32 *frD, u32 *frB)
         frD[1] = frB[1];
 
 #ifdef DEBUG
-        printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+        printk("%s: D %p, B %p: ", __func__, frD, frB);
         dump_double(frD);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/fadd.c b/arch/powerpc/math-emu/fadd.c
index fc8836488b64..7befbbf2c332 100644
--- a/arch/powerpc/math-emu/fadd.c
+++ b/arch/powerpc/math-emu/fadd.c
@@ -14,7 +14,7 @@ fadd(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fadds.c b/arch/powerpc/math-emu/fadds.c
index 93025b6c8f3c..2b346b38b480 100644
--- a/arch/powerpc/math-emu/fadds.c
+++ b/arch/powerpc/math-emu/fadds.c
@@ -15,7 +15,7 @@ fadds(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fcmpo.c b/arch/powerpc/math-emu/fcmpo.c
index 4efac394b4cb..36d689044c63 100644
--- a/arch/powerpc/math-emu/fcmpo.c
+++ b/arch/powerpc/math-emu/fcmpo.c
@@ -15,7 +15,7 @@ fcmpo(u32 *ccr, int crfD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p (%08x) %d %p %p\n", __FUNCTION__, ccr, *ccr, crfD, frA, frB);
+        printk("%s: %p (%08x) %d %p %p\n", __func__, ccr, *ccr, crfD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fcmpu.c b/arch/powerpc/math-emu/fcmpu.c
index b7e33176e618..53d93894f2a6 100644
--- a/arch/powerpc/math-emu/fcmpu.c
+++ b/arch/powerpc/math-emu/fcmpu.c
@@ -14,7 +14,7 @@ fcmpu(u32 *ccr, int crfD, void *frA, void *frB)
         long cmp;
 
 #ifdef DEBUG
-        printk("%s: %p (%08x) %d %p %p\n", __FUNCTION__, ccr, *ccr, crfD, frA, frB);
+        printk("%s: %p (%08x) %d %p %p\n", __func__, ccr, *ccr, crfD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fctiw.c b/arch/powerpc/math-emu/fctiw.c
index 3b3c98b840cf..fcd7a95e021d 100644
--- a/arch/powerpc/math-emu/fctiw.c
+++ b/arch/powerpc/math-emu/fctiw.c
@@ -16,7 +16,7 @@ fctiw(u32 *frD, void *frB)
         frD[1] = r;
 
 #ifdef DEBUG
-        printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+        printk("%s: D %p, B %p: ", __func__, frD, frB);
         dump_double(frD);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/fctiwz.c b/arch/powerpc/math-emu/fctiwz.c
index 7717eb6fcfb6..1514d59e146e 100644
--- a/arch/powerpc/math-emu/fctiwz.c
+++ b/arch/powerpc/math-emu/fctiwz.c
@@ -23,7 +23,7 @@ fctiwz(u32 *frD, void *frB)
         __FPU_FPSCR = fpscr;
 
 #ifdef DEBUG
-        printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+        printk("%s: D %p, B %p: ", __func__, frD, frB);
         dump_double(frD);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/fdiv.c b/arch/powerpc/math-emu/fdiv.c
index f2fba825b2d0..18a20fe396b0 100644
--- a/arch/powerpc/math-emu/fdiv.c
+++ b/arch/powerpc/math-emu/fdiv.c
@@ -14,7 +14,7 @@ fdiv(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
@@ -28,13 +28,13 @@ fdiv(void *frD, void *frA, void *frB)
         if (A_c == FP_CLS_ZERO && B_c == FP_CLS_ZERO) {
                 ret |= EFLAG_VXZDZ;
 #ifdef DEBUG
-                printk("%s: FPSCR_VXZDZ raised\n", __FUNCTION__);
+                printk("%s: FPSCR_VXZDZ raised\n", __func__);
 #endif
         }
         if (A_c == FP_CLS_INF && B_c == FP_CLS_INF) {
                 ret |= EFLAG_VXIDI;
 #ifdef DEBUG
-                printk("%s: FPSCR_VXIDI raised\n", __FUNCTION__);
+                printk("%s: FPSCR_VXIDI raised\n", __func__);
 #endif
         }
 
diff --git a/arch/powerpc/math-emu/fdivs.c b/arch/powerpc/math-emu/fdivs.c
index b971196e3175..24feed689c35 100644
--- a/arch/powerpc/math-emu/fdivs.c
+++ b/arch/powerpc/math-emu/fdivs.c
@@ -15,7 +15,7 @@ fdivs(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
@@ -29,13 +29,13 @@ fdivs(void *frD, void *frA, void *frB)
         if (A_c == FP_CLS_ZERO && B_c == FP_CLS_ZERO) {
                 ret |= EFLAG_VXZDZ;
 #ifdef DEBUG
-                printk("%s: FPSCR_VXZDZ raised\n", __FUNCTION__);
+                printk("%s: FPSCR_VXZDZ raised\n", __func__);
 #endif
         }
         if (A_c == FP_CLS_INF && B_c == FP_CLS_INF) {
                 ret |= EFLAG_VXIDI;
 #ifdef DEBUG
-                printk("%s: FPSCR_VXIDI raised\n", __FUNCTION__);
+                printk("%s: FPSCR_VXIDI raised\n", __func__);
 #endif
         }
 
diff --git a/arch/powerpc/math-emu/fmadd.c b/arch/powerpc/math-emu/fmadd.c
index 0a1dbce793e9..dedb465fdc68 100644
--- a/arch/powerpc/math-emu/fmadd.c
+++ b/arch/powerpc/math-emu/fmadd.c
@@ -16,7 +16,7 @@ fmadd(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fmadds.c b/arch/powerpc/math-emu/fmadds.c
index 0f70bba9445e..6bbb56d5502c 100644
--- a/arch/powerpc/math-emu/fmadds.c
+++ b/arch/powerpc/math-emu/fmadds.c
@@ -17,7 +17,7 @@ fmadds(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fmr.c b/arch/powerpc/math-emu/fmr.c
index 28df700c0c7e..bd55384b8196 100644
--- a/arch/powerpc/math-emu/fmr.c
+++ b/arch/powerpc/math-emu/fmr.c
@@ -9,7 +9,7 @@ fmr(u32 *frD, u32 *frB)
         frD[1] = frB[1];
 
 #ifdef DEBUG
-        printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+        printk("%s: D %p, B %p: ", __func__, frD, frB);
         dump_double(frD);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/fmsub.c b/arch/powerpc/math-emu/fmsub.c
index 203fd48a6fec..f311e2c7e67e 100644
--- a/arch/powerpc/math-emu/fmsub.c
+++ b/arch/powerpc/math-emu/fmsub.c
@@ -16,7 +16,7 @@ fmsub(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fmsubs.c b/arch/powerpc/math-emu/fmsubs.c
index 8ce68624c189..81a716d3ee2e 100644
--- a/arch/powerpc/math-emu/fmsubs.c
+++ b/arch/powerpc/math-emu/fmsubs.c
@@ -17,7 +17,7 @@ fmsubs(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fmul.c b/arch/powerpc/math-emu/fmul.c
index 66c7e79aae2e..2f3d32784a04 100644
--- a/arch/powerpc/math-emu/fmul.c
+++ b/arch/powerpc/math-emu/fmul.c
@@ -14,7 +14,7 @@ fmul(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fmuls.c b/arch/powerpc/math-emu/fmuls.c
index 26bc4278271c..962b5883f784 100644
--- a/arch/powerpc/math-emu/fmuls.c
+++ b/arch/powerpc/math-emu/fmuls.c
@@ -15,7 +15,7 @@ fmuls(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fnabs.c b/arch/powerpc/math-emu/fnabs.c
index c6b913d179e0..a7d34f3d9499 100644
--- a/arch/powerpc/math-emu/fnabs.c
+++ b/arch/powerpc/math-emu/fnabs.c
@@ -9,7 +9,7 @@ fnabs(u32 *frD, u32 *frB)
         frD[1] = frB[1];
 
 #ifdef DEBUG
-        printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+        printk("%s: D %p, B %p: ", __func__, frD, frB);
         dump_double(frD);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/fneg.c b/arch/powerpc/math-emu/fneg.c
index fe9a98deff69..1e988cd9c6cc 100644
--- a/arch/powerpc/math-emu/fneg.c
+++ b/arch/powerpc/math-emu/fneg.c
@@ -9,7 +9,7 @@ fneg(u32 *frD, u32 *frB)
         frD[1] = frB[1];
 
 #ifdef DEBUG
-        printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+        printk("%s: D %p, B %p: ", __func__, frD, frB);
         dump_double(frD);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/fnmadd.c b/arch/powerpc/math-emu/fnmadd.c
index 7f312276d920..8cf7827c4fb5 100644
--- a/arch/powerpc/math-emu/fnmadd.c
+++ b/arch/powerpc/math-emu/fnmadd.c
@@ -16,7 +16,7 @@ fnmadd(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fnmadds.c b/arch/powerpc/math-emu/fnmadds.c
index 65454c9c70bc..f1c4f0f0d807 100644
--- a/arch/powerpc/math-emu/fnmadds.c
+++ b/arch/powerpc/math-emu/fnmadds.c
@@ -17,7 +17,7 @@ fnmadds(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fnmsub.c b/arch/powerpc/math-emu/fnmsub.c
index f1ca7482b5f0..98944e6e2601 100644
--- a/arch/powerpc/math-emu/fnmsub.c
+++ b/arch/powerpc/math-emu/fnmsub.c
@@ -16,7 +16,7 @@ fnmsub(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fnmsubs.c b/arch/powerpc/math-emu/fnmsubs.c
index 5c9a09a87dc7..b20f4eb63fb9 100644
--- a/arch/powerpc/math-emu/fnmsubs.c
+++ b/arch/powerpc/math-emu/fnmsubs.c
@@ -17,7 +17,7 @@ fnmsubs(void *frD, void *frA, void *frB, void *frC)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fres.c b/arch/powerpc/math-emu/fres.c
index ec11e46d20af..10ecbd08b79e 100644
--- a/arch/powerpc/math-emu/fres.c
+++ b/arch/powerpc/math-emu/fres.c
@@ -6,7 +6,7 @@ int
 fres(void *frD, void *frB)
 {
 #ifdef DEBUG
-        printk("%s: %p %p\n", __FUNCTION__, frD, frB);
+        printk("%s: %p %p\n", __func__, frD, frB);
 #endif
         return -ENOSYS;
 }
diff --git a/arch/powerpc/math-emu/frsp.c b/arch/powerpc/math-emu/frsp.c
index d879b2a3d0c9..724ccbc0468e 100644
--- a/arch/powerpc/math-emu/frsp.c
+++ b/arch/powerpc/math-emu/frsp.c
@@ -12,7 +12,7 @@ frsp(void *frD, void *frB)
         FP_DECL_D(B);
 
 #ifdef DEBUG
-        printk("%s: D %p, B %p\n", __FUNCTION__, frD, frB);
+        printk("%s: D %p, B %p\n", __func__, frD, frB);
 #endif
 
         __FP_UNPACK_D(B, frB);
diff --git a/arch/powerpc/math-emu/frsqrte.c b/arch/powerpc/math-emu/frsqrte.c
index a11ae1829850..1d0a3a0fd0e6 100644
--- a/arch/powerpc/math-emu/frsqrte.c
+++ b/arch/powerpc/math-emu/frsqrte.c
@@ -6,7 +6,7 @@ int
 frsqrte(void *frD, void *frB)
 {
 #ifdef DEBUG
-        printk("%s: %p %p\n", __FUNCTION__, frD, frB);
+        printk("%s: %p %p\n", __func__, frD, frB);
 #endif
         return 0;
 }
diff --git a/arch/powerpc/math-emu/fsel.c b/arch/powerpc/math-emu/fsel.c
index e36e6e72819a..ecb5f28eb1f3 100644
--- a/arch/powerpc/math-emu/fsel.c
+++ b/arch/powerpc/math-emu/fsel.c
@@ -11,7 +11,7 @@ fsel(u32 *frD, void *frA, u32 *frB, u32 *frC)
         FP_DECL_D(A);
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+        printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fsqrt.c b/arch/powerpc/math-emu/fsqrt.c
index 6f8319f64a8a..38ec2b752e9d 100644
--- a/arch/powerpc/math-emu/fsqrt.c
+++ b/arch/powerpc/math-emu/fsqrt.c
@@ -13,7 +13,7 @@ fsqrt(void *frD, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frB);
+        printk("%s: %p %p %p %p\n", __func__, frD, frB);
 #endif
 
         __FP_UNPACK_D(B, frB);
diff --git a/arch/powerpc/math-emu/fsqrts.c b/arch/powerpc/math-emu/fsqrts.c
index 3b2b1cf55c12..335263e06ee5 100644
--- a/arch/powerpc/math-emu/fsqrts.c
+++ b/arch/powerpc/math-emu/fsqrts.c
@@ -14,7 +14,7 @@ fsqrts(void *frD, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frB);
+        printk("%s: %p %p %p %p\n", __func__, frD, frB);
 #endif
 
         __FP_UNPACK_D(B, frB);
diff --git a/arch/powerpc/math-emu/fsub.c b/arch/powerpc/math-emu/fsub.c
index 956679042bb2..208d20fc52a5 100644
--- a/arch/powerpc/math-emu/fsub.c
+++ b/arch/powerpc/math-emu/fsub.c
@@ -14,7 +14,7 @@ fsub(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/fsubs.c b/arch/powerpc/math-emu/fsubs.c
index 3428117dfe8c..0e61b808c44b 100644
--- a/arch/powerpc/math-emu/fsubs.c
+++ b/arch/powerpc/math-emu/fsubs.c
@@ -15,7 +15,7 @@ fsubs(void *frD, void *frA, void *frB)
         int ret = 0;
 
 #ifdef DEBUG
-        printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+        printk("%s: %p %p %p\n", __func__, frD, frA, frB);
 #endif
 
         __FP_UNPACK_D(A, frA);
diff --git a/arch/powerpc/math-emu/lfd.c b/arch/powerpc/math-emu/lfd.c
index 7d38101c329b..6ec90b57c61a 100644
--- a/arch/powerpc/math-emu/lfd.c
+++ b/arch/powerpc/math-emu/lfd.c
@@ -11,7 +11,7 @@ lfd(void *frD, void *ea)
         if (copy_from_user(frD, ea, sizeof(double)))
                 return -EFAULT;
 #ifdef DEBUG
-        printk("%s: D %p, ea %p: ", __FUNCTION__, frD, ea);
+        printk("%s: D %p, ea %p: ", __func__, frD, ea);
         dump_double(frD);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/lfs.c b/arch/powerpc/math-emu/lfs.c
index c86dee3d7655..6f18ebe3a7ff 100644
--- a/arch/powerpc/math-emu/lfs.c
+++ b/arch/powerpc/math-emu/lfs.c
@@ -14,7 +14,7 @@ lfs(void *frD, void *ea)
         float f;
 
 #ifdef DEBUG
-        printk("%s: D %p, ea %p\n", __FUNCTION__, frD, ea);
+        printk("%s: D %p, ea %p\n", __func__, frD, ea);
 #endif
 
         if (copy_from_user(&f, ea, sizeof(float)))
diff --git a/arch/powerpc/math-emu/mcrfs.c b/arch/powerpc/math-emu/mcrfs.c
index 106dd912914b..41ba247faf89 100644
--- a/arch/powerpc/math-emu/mcrfs.c
+++ b/arch/powerpc/math-emu/mcrfs.c
@@ -10,7 +10,7 @@ mcrfs(u32 *ccr, u32 crfD, u32 crfS)
         u32 value, clear;
 
 #ifdef DEBUG
-        printk("%s: %p (%08x) %d %d\n", __FUNCTION__, ccr, *ccr, crfD, crfS);
+        printk("%s: %p (%08x) %d %d\n", __func__, ccr, *ccr, crfD, crfS);
 #endif
 
         clear = 15 << ((7 - crfS) << 2);
@@ -24,7 +24,7 @@ mcrfs(u32 *ccr, u32 crfD, u32 crfS)
         *ccr |= (value << ((7 - crfD) << 2));
 
 #ifdef DEBUG
-        printk("CR: %08x\n", __FUNCTION__, *ccr);
+        printk("CR: %08x\n", __func__, *ccr);
 #endif
 
         return 0;
diff --git a/arch/powerpc/math-emu/mffs.c b/arch/powerpc/math-emu/mffs.c
index f477c9170e75..b0e2106e6eb6 100644
--- a/arch/powerpc/math-emu/mffs.c
+++ b/arch/powerpc/math-emu/mffs.c
@@ -10,7 +10,7 @@ mffs(u32 *frD)
         frD[1] = __FPU_FPSCR;
 
 #ifdef DEBUG
-        printk("%s: frD %p: %08x.%08x\n", __FUNCTION__, frD, frD[0], frD[1]);
+        printk("%s: frD %p: %08x.%08x\n", __func__, frD, frD[0], frD[1]);
 #endif
 
         return 0;
diff --git a/arch/powerpc/math-emu/mtfsb0.c b/arch/powerpc/math-emu/mtfsb0.c
index 99bfd80f4af3..d3062350ea21 100644
--- a/arch/powerpc/math-emu/mtfsb0.c
+++ b/arch/powerpc/math-emu/mtfsb0.c
@@ -11,7 +11,7 @@ mtfsb0(int crbD)
                 __FPU_FPSCR &= ~(1 << (31 - crbD));
 
 #ifdef DEBUG
-        printk("%s: %d %08lx\n", __FUNCTION__, crbD, __FPU_FPSCR);
+        printk("%s: %d %08lx\n", __func__, crbD, __FPU_FPSCR);
 #endif
 
         return 0;
diff --git a/arch/powerpc/math-emu/mtfsb1.c b/arch/powerpc/math-emu/mtfsb1.c
index 3d9e7ed92d2b..2e948704b56e 100644
--- a/arch/powerpc/math-emu/mtfsb1.c
+++ b/arch/powerpc/math-emu/mtfsb1.c
@@ -11,7 +11,7 @@ mtfsb1(int crbD)
                 __FPU_FPSCR |= (1 << (31 - crbD));
 
 #ifdef DEBUG
-        printk("%s: %d %08lx\n", __FUNCTION__, crbD, __FPU_FPSCR);
+        printk("%s: %d %08lx\n", __func__, crbD, __FPU_FPSCR);
 #endif
 
         return 0;
diff --git a/arch/powerpc/math-emu/mtfsf.c b/arch/powerpc/math-emu/mtfsf.c
index d70cf714994c..48014d8e3af1 100644
--- a/arch/powerpc/math-emu/mtfsf.c
+++ b/arch/powerpc/math-emu/mtfsf.c
@@ -38,7 +38,7 @@ mtfsf(unsigned int FM, u32 *frB)
         __FPU_FPSCR |= (frB[1] & mask);
 
 #ifdef DEBUG
-        printk("%s: %02x %p: %08lx\n", __FUNCTION__, FM, frB, __FPU_FPSCR);
+        printk("%s: %02x %p: %08lx\n", __func__, FM, frB, __FPU_FPSCR);
 #endif
 
         return 0;
diff --git a/arch/powerpc/math-emu/mtfsfi.c b/arch/powerpc/math-emu/mtfsfi.c
index 71df854baa7e..031e20093549 100644
--- a/arch/powerpc/math-emu/mtfsfi.c
+++ b/arch/powerpc/math-emu/mtfsfi.c
@@ -16,7 +16,7 @@ mtfsfi(unsigned int crfD, unsigned int IMM)
         __FPU_FPSCR |= (IMM & 0xf) << ((7 - crfD) << 2);
 
 #ifdef DEBUG
-        printk("%s: %d %x: %08lx\n", __FUNCTION__, crfD, IMM, __FPU_FPSCR);
+        printk("%s: %d %x: %08lx\n", __func__, crfD, IMM, __FPU_FPSCR);
 #endif
 
         return 0;
diff --git a/arch/powerpc/math-emu/stfd.c b/arch/powerpc/math-emu/stfd.c
index 3f8c2558a9e8..33a165c8df0f 100644
--- a/arch/powerpc/math-emu/stfd.c
+++ b/arch/powerpc/math-emu/stfd.c
@@ -7,7 +7,7 @@ stfd(void *frS, void *ea)
 {
 #if 0
 #ifdef DEBUG
-        printk("%s: S %p, ea %p: ", __FUNCTION__, frS, ea);
+        printk("%s: S %p, ea %p: ", __func__, frS, ea);
         dump_double(frS);
         printk("\n");
 #endif
diff --git a/arch/powerpc/math-emu/stfiwx.c b/arch/powerpc/math-emu/stfiwx.c
index 95caaeec6a08..f15a35f67e2c 100644
--- a/arch/powerpc/math-emu/stfiwx.c
+++ b/arch/powerpc/math-emu/stfiwx.c
@@ -6,7 +6,7 @@ int
 stfiwx(u32 *frS, void *ea)
 {
 #ifdef DEBUG
-        printk("%s: %p %p\n", __FUNCTION__, frS, ea);
+        printk("%s: %p %p\n", __func__, frS, ea);
 #endif
 
         if (copy_to_user(ea, &frS[1], sizeof(frS[1])))
diff --git a/arch/powerpc/math-emu/stfs.c b/arch/powerpc/math-emu/stfs.c
index e87ca23c6dc3..8689aa48ef69 100644
--- a/arch/powerpc/math-emu/stfs.c
+++ b/arch/powerpc/math-emu/stfs.c
@@ -15,7 +15,7 @@ stfs(void *frS, void *ea)
         int err;
 
 #ifdef DEBUG
-        printk("%s: S %p, ea %p\n", __FUNCTION__, frS, ea);
+        printk("%s: S %p, ea %p\n", __func__, frS, ea);
 #endif
 
         __FP_UNPACK_D(A, frS);
diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c
index 3899ea97fbdf..cecbbc76f624 100644
--- a/arch/powerpc/mm/40x_mmu.c
+++ b/arch/powerpc/mm/40x_mmu.c
@@ -97,7 +97,7 @@ unsigned long __init mmu_mapin_ram(void)
         phys_addr_t p;
 
         v = KERNELBASE;
-        p = PPC_MEMSTART;
+        p = 0;
         s = total_lowmem;
 
         if (__map_without_ltlbs)
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 04dc08798d3d..953fb919eb06 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -67,7 +67,7 @@ unsigned long __init mmu_mapin_ram(void)
 
         /* Pin in enough TLBs to cover any lowmem not covered by the
          * initial 256M mapping established in head_44x.S */
-        for (addr = PPC_PIN_SIZE; addr < total_lowmem;
+        for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
              addr += PPC_PIN_SIZE)
                 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
 
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 41649a5d3602..1c00e0196f6c 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -6,7 +6,7 @@ ifeq ($(CONFIG_PPC64),y)
 EXTRA_CFLAGS    += -mno-minimal-toc
 endif
 
-obj-y                           := fault.o mem.o lmb.o \
+obj-y                           := fault.o mem.o \
                                    init_$(CONFIG_WORD_SIZE).o \
                                    pgtable_$(CONFIG_WORD_SIZE).o \
                                    mmu_context_$(CONFIG_WORD_SIZE).o
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index c93a966b7e4b..ada249bf9779 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -49,18 +49,15 @@
 #include <asm/mmu.h>
 #include <asm/uaccess.h>
 #include <asm/smp.h>
-#include <asm/bootx.h>
 #include <asm/machdep.h>
 #include <asm/setup.h>
 
+#include "mmu_decl.h"
+
 extern void loadcam_entry(unsigned int index);
 unsigned int tlbcam_index;
 unsigned int num_tlbcam_entries;
 static unsigned long __cam0, __cam1, __cam2;
-extern unsigned long total_lowmem;
-extern unsigned long __max_low_memory;
-extern unsigned long __initial_memory_limit;
-#define MAX_LOW_MEM     CONFIG_LOWMEM_SIZE
 
 #define NUM_TLBCAMS     (16)
 
@@ -165,15 +162,15 @@ void invalidate_tlbcam_entry(int index)
 void __init cam_mapin_ram(unsigned long cam0, unsigned long cam1,
                 unsigned long cam2)
 {
-        settlbcam(0, PAGE_OFFSET, PPC_MEMSTART, cam0, _PAGE_KERNEL, 0);
+        settlbcam(0, PAGE_OFFSET, memstart_addr, cam0, _PAGE_KERNEL, 0);
         tlbcam_index++;
         if (cam1) {
                 tlbcam_index++;
-                settlbcam(1, PAGE_OFFSET+cam0, PPC_MEMSTART+cam0, cam1, _PAGE_KERNEL, 0);
+                settlbcam(1, PAGE_OFFSET+cam0, memstart_addr+cam0, cam1, _PAGE_KERNEL, 0);
         }
         if (cam2) {
                 tlbcam_index++;
-                settlbcam(2, PAGE_OFFSET+cam0+cam1, PPC_MEMSTART+cam0+cam1, cam2, _PAGE_KERNEL, 0);
+                settlbcam(2, PAGE_OFFSET+cam0+cam1, memstart_addr+cam0+cam1, cam2, _PAGE_KERNEL, 0);
         }
 }
 
@@ -196,35 +193,32 @@ unsigned long __init mmu_mapin_ram(void)
 void __init
 adjust_total_lowmem(void)
 {
-        unsigned long max_low_mem = MAX_LOW_MEM;
-        unsigned long cam_max = 0x10000000;
-        unsigned long ram;
+        phys_addr_t max_lowmem_size = __max_low_memory;
+        phys_addr_t cam_max_size = 0x10000000;
+        phys_addr_t ram;
 
-        /* adjust CAM size to max_low_mem */
-        if (max_low_mem < cam_max)
-                cam_max = max_low_mem;
+        /* adjust CAM size to max_lowmem_size */
+        if (max_lowmem_size < cam_max_size)
+                cam_max_size = max_lowmem_size;
 
-        /* adjust lowmem size to max_low_mem */
-        if (max_low_mem < total_lowmem)
-                ram = max_low_mem;
-        else
-                ram = total_lowmem;
+        /* adjust lowmem size to max_lowmem_size */
+        ram = min(max_lowmem_size, total_lowmem);
 
         /* Calculate CAM values */
         __cam0 = 1UL << 2 * (__ilog2(ram) / 2);
-        if (__cam0 > cam_max)
-                __cam0 = cam_max;
+        if (__cam0 > cam_max_size)
+                __cam0 = cam_max_size;
         ram -= __cam0;
         if (ram) {
                 __cam1 = 1UL << 2 * (__ilog2(ram) / 2);
-                if (__cam1 > cam_max)
-                        __cam1 = cam_max;
+                if (__cam1 > cam_max_size)
+                        __cam1 = cam_max_size;
                 ram -= __cam1;
         }
         if (ram) {
                 __cam2 = 1UL << 2 * (__ilog2(ram) / 2);
-                if (__cam2 > cam_max)
-                        __cam2 = cam_max;
+                if (__cam2 > cam_max_size)
+                        __cam2 = cam_max_size;
                 ram -= __cam2;
         }
 
@@ -232,6 +226,6 @@ adjust_total_lowmem(void)
                         " CAM2=%ldMb residual: %ldMb\n",
                         __cam0 >> 20, __cam1 >> 20, __cam2 >> 20,
                         (total_lowmem - __cam0 - __cam1 - __cam2) >> 20);
-        __max_low_memory = max_low_mem = __cam0 + __cam1 + __cam2;
-        __initial_memory_limit = __max_low_memory;
+        __max_low_memory = __cam0 + __cam1 + __cam2;
+        __initial_memory_limit_addr = memstart_addr + __max_low_memory;
 }
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index a83dfa3cf40c..2b5a399f6fa6 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -31,6 +31,7 @@
 #include <linux/cache.h>
 #include <linux/init.h>
 #include <linux/signal.h>
+#include <linux/lmb.h>
 
 #include <asm/processor.h>
 #include <asm/pgtable.h>
@@ -41,7 +42,7 @@
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/machdep.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/abs_addr.h>
 #include <asm/tlbflush.h>
 #include <asm/io.h>
@@ -191,6 +192,29 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
         return ret < 0 ? ret : 0;
 }
 
+#ifdef CONFIG_MEMORY_HOTPLUG
+static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
+                      int psize, int ssize)
+{
+        unsigned long vaddr;
+        unsigned int step, shift;
+
+        shift = mmu_psize_defs[psize].shift;
+        step = 1 << shift;
+
+        if (!ppc_md.hpte_removebolted) {
+                printk(KERN_WARNING "Platform doesn't implement "
+                                "hpte_removebolted\n");
+                return -EINVAL;
+        }
+
+        for (vaddr = vstart; vaddr < vend; vaddr += step)
+                ppc_md.hpte_removebolted(vaddr, psize, ssize);
+
+        return 0;
+}
+#endif /* CONFIG_MEMORY_HOTPLUG */
+
 static int __init htab_dt_scan_seg_sizes(unsigned long node,
                                          const char *uname, int depth,
                                          void *data)
@@ -434,6 +458,12 @@ void create_section_mapping(unsigned long start, unsigned long end)
                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
                         mmu_linear_psize, mmu_kernel_ssize));
 }
+
+int remove_section_mapping(unsigned long start, unsigned long end)
+{
+        return htab_remove_mapping(start, end, mmu_linear_psize,
+                        mmu_kernel_ssize);
+}
 #endif /* CONFIG_MEMORY_HOTPLUG */
 
 static inline void make_bl(unsigned int *insn_addr, void *func)
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 977cb1ee5e72..47325f23c51f 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -30,6 +30,7 @@
 #include <linux/highmem.h>
 #include <linux/initrd.h>
 #include <linux/pagemap.h>
+#include <linux/lmb.h>
 
 #include <asm/pgalloc.h>
 #include <asm/prom.h>
@@ -41,7 +42,6 @@
 #include <asm/machdep.h>
 #include <asm/btext.h>
 #include <asm/tlb.h>
-#include <asm/lmb.h>
 #include <asm/sections.h>
 
 #include "mmu_decl.h"
@@ -59,8 +59,8 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 unsigned long total_memory;
 unsigned long total_lowmem;
 
-unsigned long ppc_memstart;
-unsigned long ppc_memoffset = PAGE_OFFSET;
+phys_addr_t memstart_addr;
+phys_addr_t lowmem_end_addr;
 
 int boot_mapsize;
 #ifdef CONFIG_PPC_PMAC
@@ -95,10 +95,10 @@ int __map_without_ltlbs;
 unsigned long __max_low_memory = MAX_LOW_MEM;
 
 /*
- * limit of what is accessible with initial MMU setup -
+ * address of the limit of what is accessible with initial MMU setup -
  * 256MB usually, but only 16MB on 601.
  */
-unsigned long __initial_memory_limit = 0x10000000;
+phys_addr_t __initial_memory_limit_addr = (phys_addr_t)0x10000000;
 
 /*
  * Check for command-line options that affect what MMU_init will do.
@@ -131,10 +131,10 @@ void __init MMU_init(void)
 
         /* 601 can only access 16MB at the moment */
         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
-                __initial_memory_limit = 0x01000000;
+                __initial_memory_limit_addr = 0x01000000;
         /* 8xx can only access 8MB at the moment */
         if (PVR_VER(mfspr(SPRN_PVR)) == 0x50)
-                __initial_memory_limit = 0x00800000;
+                __initial_memory_limit_addr = 0x00800000;
 
         /* parse args from command line */
         MMU_setup();
@@ -145,8 +145,8 @@ void __init MMU_init(void)
                 printk(KERN_WARNING "Only using first contiguous memory region");
         }
 
-        total_memory = lmb_end_of_DRAM();
-        total_lowmem = total_memory;
+        total_lowmem = total_memory = lmb_end_of_DRAM() - memstart_addr;
+        lowmem_end_addr = memstart_addr + total_lowmem;
 
 #ifdef CONFIG_FSL_BOOKE
         /* Freescale Book-E parts expect lowmem to be mapped by fixed TLB
@@ -157,9 +157,10 @@ void __init MMU_init(void)
 
         if (total_lowmem > __max_low_memory) {
                 total_lowmem = __max_low_memory;
+                lowmem_end_addr = memstart_addr + total_lowmem;
 #ifndef CONFIG_HIGHMEM
                 total_memory = total_lowmem;
-                lmb_enforce_memory_limit(total_lowmem);
+                lmb_enforce_memory_limit(lowmem_end_addr);
                 lmb_analyze();
 #endif /* CONFIG_HIGHMEM */
         }
@@ -184,8 +185,6 @@ void __init MMU_init(void)
         /* Map in I/O resources */
         if (ppc_md.progress)
                 ppc_md.progress("MMU:setio", 0x302);
-        if (ppc_md.setup_io_mappings)
-                ppc_md.setup_io_mappings();
 
         /* Initialize the context management stuff */
         mmu_context_init();
@@ -208,7 +207,7 @@ void __init *early_get_page(void)
                 p = alloc_bootmem_pages(PAGE_SIZE);
         } else {
                 p = __va(lmb_alloc_base(PAGE_SIZE, PAGE_SIZE,
-                                        __initial_memory_limit));
+                                        __initial_memory_limit_addr));
         }
         return p;
 }
@@ -276,7 +275,7 @@ static int __init setup_kcore(void)
 
                 kcore_mem = kmalloc(sizeof(struct kcore_list), GFP_ATOMIC);
                 if (!kcore_mem)
-                        panic("%s: kmalloc failed\n", __FUNCTION__);
+                        panic("%s: kmalloc failed\n", __func__);
 
                 /* must stay under 32 bits */
                 if ( 0xfffffffful - (unsigned long)__va(base) < size) {
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index c0f5cff77035..698bd000f98b 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -38,11 +38,11 @@
 #include <linux/nodemask.h>
 #include <linux/module.h>
 #include <linux/poison.h>
+#include <linux/lmb.h>
 
 #include <asm/pgalloc.h>
 #include <asm/page.h>
 #include <asm/prom.h>
-#include <asm/lmb.h>
 #include <asm/rtas.h>
 #include <asm/io.h>
 #include <asm/mmu_context.h>
@@ -72,8 +72,7 @@
 #warning TASK_SIZE is smaller than it needs to be.
 #endif
 
-/* max amount of RAM to use */
-unsigned long __max_memory;
+phys_addr_t memstart_addr;
 
 void free_initmem(void)
 {
@@ -122,7 +121,7 @@ static int __init setup_kcore(void)
                 /* GFP_ATOMIC to avoid might_sleep warnings during boot */
                 kcore_mem = kmalloc(sizeof(struct kcore_list), GFP_ATOMIC);
                 if (!kcore_mem)
-                        panic("%s: kmalloc failed\n", __FUNCTION__);
+                        panic("%s: kmalloc failed\n", __func__);
 
                 kclist_add(kcore_mem, __va(base), size);
         }
diff --git a/arch/powerpc/mm/lmb.c b/arch/powerpc/mm/lmb.c
deleted file mode 100644
index 4ce23bcf8a57..000000000000
--- a/arch/powerpc/mm/lmb.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * Procedures for maintaining information about logical memory blocks.
- *
- * Peter Bergner, IBM Corp.     June 2001.
- * Copyright (C) 2001 Peter Bergner.
- * 
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/bitops.h>
-#include <asm/types.h>
-#include <asm/page.h>
-#include <asm/prom.h>
-#include <asm/lmb.h>
-#ifdef CONFIG_PPC32
-#include "mmu_decl.h"           /* for __max_low_memory */
-#endif
-
-#undef DEBUG
-
-#ifdef DEBUG
-#include <asm/udbg.h>
-#define DBG(fmt...) udbg_printf(fmt)
-#else
-#define DBG(fmt...)
-#endif
-
-#define LMB_ALLOC_ANYWHERE      0
-
-struct lmb lmb;
-
-void lmb_dump_all(void)
-{
-#ifdef DEBUG
-        unsigned long i;
-
-        DBG("lmb_dump_all:\n");
-        DBG("    memory.cnt               = 0x%lx\n", lmb.memory.cnt);
-        DBG("    memory.size              = 0x%lx\n", lmb.memory.size);
-        for (i=0; i < lmb.memory.cnt ;i++) {
-                DBG("    memory.region[0x%x].base       = 0x%lx\n",
-                            i, lmb.memory.region[i].base);
-                DBG("                 .size     = 0x%lx\n",
-                            lmb.memory.region[i].size);
-        }
-
-        DBG("\n    reserved.cnt   = 0x%lx\n", lmb.reserved.cnt);
-        DBG("    reserved.size    = 0x%lx\n", lmb.reserved.size);
-        for (i=0; i < lmb.reserved.cnt ;i++) {
-                DBG("    reserved.region[0x%x].base       = 0x%lx\n",
-                            i, lmb.reserved.region[i].base);
-                DBG("                 .size     = 0x%lx\n",
-                            lmb.reserved.region[i].size);
-        }
-#endif /* DEBUG */
-}
-
-static unsigned long __init lmb_addrs_overlap(unsigned long base1,
-                unsigned long size1, unsigned long base2, unsigned long size2)
-{
-        return ((base1 < (base2+size2)) && (base2 < (base1+size1)));
-}
-
-static long __init lmb_addrs_adjacent(unsigned long base1, unsigned long size1,
-                unsigned long base2, unsigned long size2)
-{
-        if (base2 == base1 + size1)
-                return 1;
-        else if (base1 == base2 + size2)
-                return -1;
-
-        return 0;
-}
-
-static long __init lmb_regions_adjacent(struct lmb_region *rgn,
-                unsigned long r1, unsigned long r2)
-{
-        unsigned long base1 = rgn->region[r1].base;
-        unsigned long size1 = rgn->region[r1].size;
-        unsigned long base2 = rgn->region[r2].base;
-        unsigned long size2 = rgn->region[r2].size;
-
-        return lmb_addrs_adjacent(base1, size1, base2, size2);
-}
-
-static void __init lmb_remove_region(struct lmb_region *rgn, unsigned long r)
-{
-        unsigned long i;
-
-        for (i = r; i < rgn->cnt - 1; i++) {
-                rgn->region[i].base = rgn->region[i + 1].base;
-                rgn->region[i].size = rgn->region[i + 1].size;
-        }
-        rgn->cnt--;
-}
-
-/* Assumption: base addr of region 1 < base addr of region 2 */
-static void __init lmb_coalesce_regions(struct lmb_region *rgn,
-                unsigned long r1, unsigned long r2)
-{
-        rgn->region[r1].size += rgn->region[r2].size;
-        lmb_remove_region(rgn, r2);
-}
-
-/* This routine called with relocation disabled. */
-void __init lmb_init(void)
-{
-        /* Create a dummy zero size LMB which will get coalesced away later.
-         * This simplifies the lmb_add() code below...
-         */
-        lmb.memory.region[0].base = 0;
-        lmb.memory.region[0].size = 0;
-        lmb.memory.cnt = 1;
-
-        /* Ditto. */
-        lmb.reserved.region[0].base = 0;
-        lmb.reserved.region[0].size = 0;
-        lmb.reserved.cnt = 1;
-}
-
-/* This routine may be called with relocation disabled. */
-void __init lmb_analyze(void)
-{
-        int i;
-
-        lmb.memory.size = 0;
-
-        for (i = 0; i < lmb.memory.cnt; i++)
-                lmb.memory.size += lmb.memory.region[i].size;
-}
-
-/* This routine called with relocation disabled. */
-static long __init lmb_add_region(struct lmb_region *rgn, unsigned long base,
-                                  unsigned long size)
-{
-        unsigned long coalesced = 0;
-        long adjacent, i;
-
-        /* First try and coalesce this LMB with another. */
-        for (i=0; i < rgn->cnt; i++) {
-                unsigned long rgnbase = rgn->region[i].base;
-                unsigned long rgnsize = rgn->region[i].size;
-
-                if ((rgnbase == base) && (rgnsize == size))
-                        /* Already have this region, so we're done */
-                        return 0;
-
-                adjacent = lmb_addrs_adjacent(base,size,rgnbase,rgnsize);
-                if ( adjacent > 0 ) {
-                        rgn->region[i].base -= size;
-                        rgn->region[i].size += size;
-                        coalesced++;
-                        break;
-                }
-                else if ( adjacent < 0 ) {
-                        rgn->region[i].size += size;
-                        coalesced++;
-                        break;
-                }
-        }
-
-        if ((i < rgn->cnt-1) && lmb_regions_adjacent(rgn, i, i+1) ) {
-                lmb_coalesce_regions(rgn, i, i+1);
-                coalesced++;
-        }
-
-        if (coalesced)
-                return coalesced;
-        if (rgn->cnt >= MAX_LMB_REGIONS)
-                return -1;
-
-        /* Couldn't coalesce the LMB, so add it to the sorted table. */
-        for (i = rgn->cnt-1; i >= 0; i--) {
-                if (base < rgn->region[i].base) {
-                        rgn->region[i+1].base = rgn->region[i].base;
-                        rgn->region[i+1].size = rgn->region[i].size;
-                } else {
-                        rgn->region[i+1].base = base;
-                        rgn->region[i+1].size = size;
-                        break;
-                }
-        }
-        rgn->cnt++;
-
-        return 0;
-}
-
-/* This routine may be called with relocation disabled. */
-long __init lmb_add(unsigned long base, unsigned long size)
-{
-        struct lmb_region *_rgn = &(lmb.memory);
-
-        /* On pSeries LPAR systems, the first LMB is our RMO region. */
-        if (base == 0)
-                lmb.rmo_size = size;
-
-        return lmb_add_region(_rgn, base, size);
-
-}
-
-long __init lmb_reserve(unsigned long base, unsigned long size)
-{
-        struct lmb_region *_rgn = &(lmb.reserved);
-
-        BUG_ON(0 == size);
-
-        return lmb_add_region(_rgn, base, size);
-}
-
-long __init lmb_overlaps_region(struct lmb_region *rgn, unsigned long base,
-                                unsigned long size)
-{
-        unsigned long i;
-
-        for (i=0; i < rgn->cnt; i++) {
-                unsigned long rgnbase = rgn->region[i].base;
-                unsigned long rgnsize = rgn->region[i].size;
-                if ( lmb_addrs_overlap(base,size,rgnbase,rgnsize) ) {
-                        break;
-                }
-        }
-
-        return (i < rgn->cnt) ? i : -1;
-}
-
-unsigned long __init lmb_alloc(unsigned long size, unsigned long align)
-{
-        return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE);
-}
-
-unsigned long __init lmb_alloc_base(unsigned long size, unsigned long align,
-                                    unsigned long max_addr)
-{
-        unsigned long alloc;
-
-        alloc = __lmb_alloc_base(size, align, max_addr);
-
-        if (alloc == 0)
-                panic("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n",
-                                size, max_addr);
-
-        return alloc;
-}
-
-unsigned long __init __lmb_alloc_base(unsigned long size, unsigned long align,
-                                    unsigned long max_addr)
-{
-        long i, j;
-        unsigned long base = 0;
-
-        BUG_ON(0 == size);
-
-#ifdef CONFIG_PPC32
-        /* On 32-bit, make sure we allocate lowmem */
-        if (max_addr == LMB_ALLOC_ANYWHERE)
-                max_addr = __max_low_memory;
-#endif
-        for (i = lmb.memory.cnt-1; i >= 0; i--) {
-                unsigned long lmbbase = lmb.memory.region[i].base;
-                unsigned long lmbsize = lmb.memory.region[i].size;
-
-                if (max_addr == LMB_ALLOC_ANYWHERE)
-                        base = _ALIGN_DOWN(lmbbase + lmbsize - size, align);
-                else if (lmbbase < max_addr) {
-                        base = min(lmbbase + lmbsize, max_addr);
-                        base = _ALIGN_DOWN(base - size, align);
-                } else
-                        continue;
-
-                while ((lmbbase <= base) &&
-                       ((j = lmb_overlaps_region(&lmb.reserved, base, size)) >= 0) )
-                        base = _ALIGN_DOWN(lmb.reserved.region[j].base - size,
-                                           align);
-
-                if ((base != 0) && (lmbbase <= base))
-                        break;
-        }
-
-        if (i < 0)
-                return 0;
-
-        lmb_add_region(&lmb.reserved, base, size);
-
-        return base;
-}
-
-/* You must call lmb_analyze() before this. */
-unsigned long __init lmb_phys_mem_size(void)
-{
-        return lmb.memory.size;
-}
-
-unsigned long __init lmb_end_of_DRAM(void)
-{
-        int idx = lmb.memory.cnt - 1;
-
-        return (lmb.memory.region[idx].base + lmb.memory.region[idx].size);
-}
-
-/* You must call lmb_analyze() after this. */
-void __init lmb_enforce_memory_limit(unsigned long memory_limit)
-{
-        unsigned long i, limit;
-        struct lmb_property *p;
-
-        if (! memory_limit)
-                return;
-
-        /* Truncate the lmb regions to satisfy the memory limit. */
-        limit = memory_limit;
-        for (i = 0; i < lmb.memory.cnt; i++) {
-                if (limit > lmb.memory.region[i].size) {
-                        limit -= lmb.memory.region[i].size;
-                        continue;
-                }
-
-                lmb.memory.region[i].size = limit;
-                lmb.memory.cnt = i + 1;
-                break;
-        }
-
-        if (lmb.memory.region[0].size < lmb.rmo_size)
-                lmb.rmo_size = lmb.memory.region[0].size;
-
-        /* And truncate any reserves above the limit also. */
-        for (i = 0; i < lmb.reserved.cnt; i++) {
-                p = &lmb.reserved.region[i];
-
-                if (p->base > memory_limit)
-                        p->size = 0;
-                else if ((p->base + p->size) > memory_limit)
-                        p->size = memory_limit - p->base;
-
-                if (p->size == 0) {
-                        lmb_remove_region(&lmb.reserved, i);
-                        i--;
-                }
-        }
-}
-
-int __init lmb_is_reserved(unsigned long addr)
-{
-        int i;
-
-        for (i = 0; i < lmb.reserved.cnt; i++) {
-                unsigned long upper = lmb.reserved.region[i].base +
-                                      lmb.reserved.region[i].size - 1;
-                if ((addr >= lmb.reserved.region[i].base) && (addr <= upper))
-                        return 1;
-        }
-        return 0;
-}
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index be5c506779a7..16def4dcff6d 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -31,6 +31,7 @@
 #include <linux/initrd.h>
 #include <linux/pagemap.h>
 #include <linux/suspend.h>
+#include <linux/lmb.h>
 
 #include <asm/pgalloc.h>
 #include <asm/prom.h>
@@ -42,7 +43,6 @@
 #include <asm/machdep.h>
 #include <asm/btext.h>
 #include <asm/tlb.h>
-#include <asm/lmb.h>
 #include <asm/sections.h>
 #include <asm/vdso.h>
 
@@ -111,7 +111,7 @@ int memory_add_physaddr_to_nid(u64 start)
 }
 #endif
 
-int __devinit arch_add_memory(int nid, u64 start, u64 size)
+int arch_add_memory(int nid, u64 start, u64 size)
 {
         struct pglist_data *pgdata;
         struct zone *zone;
@@ -175,7 +175,6 @@ void show_mem(void)
 
         printk("Mem-info:\n");
         show_free_areas();
-        printk("Free swap:       %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
         for_each_online_pgdat(pgdat) {
                 unsigned long flags;
                 pgdat_resize_lock(pgdat, &flags);
@@ -217,9 +216,11 @@ void __init do_init_bootmem(void)
         unsigned long total_pages;
         int boot_mapsize;
 
-        max_pfn = total_pages = lmb_end_of_DRAM() >> PAGE_SHIFT;
+        max_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
+        total_pages = (lmb_end_of_DRAM() - memstart_addr) >> PAGE_SHIFT;
 #ifdef CONFIG_HIGHMEM
         total_pages = total_lowmem >> PAGE_SHIFT;
+        max_low_pfn = lowmem_end_addr >> PAGE_SHIFT;
 #endif
 
         /*
@@ -245,18 +246,18 @@ void __init do_init_bootmem(void)
          * present.
          */
 #ifdef CONFIG_HIGHMEM
-        free_bootmem_with_active_regions(0, total_lowmem >> PAGE_SHIFT);
+        free_bootmem_with_active_regions(0, lowmem_end_addr >> PAGE_SHIFT);
 
         /* reserve the sections we're already using */
         for (i = 0; i < lmb.reserved.cnt; i++) {
                 unsigned long addr = lmb.reserved.region[i].base +
                                      lmb_size_bytes(&lmb.reserved, i) - 1;
-                if (addr < total_lowmem)
+                if (addr < lowmem_end_addr)
                         reserve_bootmem(lmb.reserved.region[i].base,
                                         lmb_size_bytes(&lmb.reserved, i),
                                         BOOTMEM_DEFAULT);
-                else if (lmb.reserved.region[i].base < total_lowmem) {
-                        unsigned long adjusted_size = total_lowmem -
+                else if (lmb.reserved.region[i].base < lowmem_end_addr) {
+                        unsigned long adjusted_size = lowmem_end_addr -
                                       lmb.reserved.region[i].base;
                         reserve_bootmem(lmb.reserved.region[i].base,
                                         adjusted_size, BOOTMEM_DEFAULT);
@@ -326,7 +327,7 @@ void __init paging_init(void)
                (top_of_ram - total_ram) >> 20);
         memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
 #ifdef CONFIG_HIGHMEM
-        max_zone_pfns[ZONE_DMA] = total_lowmem >> PAGE_SHIFT;
+        max_zone_pfns[ZONE_DMA] = lowmem_end_addr >> PAGE_SHIFT;
         max_zone_pfns[ZONE_HIGHMEM] = top_of_ram >> PAGE_SHIFT;
 #else
         max_zone_pfns[ZONE_DMA] = top_of_ram >> PAGE_SHIFT;
@@ -381,7 +382,7 @@ void __init mem_init(void)
         {
                 unsigned long pfn, highmem_mapnr;
 
-                highmem_mapnr = total_lowmem >> PAGE_SHIFT;
+                highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT;
                 for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
                         struct page *page = pfn_to_page(pfn);
                         if (lmb_is_reserved(pfn << PAGE_SHIFT))
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index ebfd13dc9d19..04802252a64f 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -48,9 +48,11 @@ extern unsigned int num_tlbcam_entries;
 
 extern unsigned long ioremap_bot;
 extern unsigned long __max_low_memory;
-extern unsigned long __initial_memory_limit;
+extern phys_addr_t __initial_memory_limit_addr;
 extern unsigned long total_memory;
 extern unsigned long total_lowmem;
+extern phys_addr_t memstart_addr;
+extern phys_addr_t lowmem_end_addr;
 
 /* ...and now those things that may be slightly different between processor
  * architectures.  -- Dan
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index a300d254aac6..1efd631211ef 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -17,8 +17,9 @@
 #include <linux/nodemask.h>
 #include <linux/cpu.h>
 #include <linux/notifier.h>
+#include <linux/lmb.h>
 #include <asm/sparsemem.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/system.h>
 #include <asm/smp.h>
 
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index ac3390f81900..64c44bcc68de 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -281,12 +281,13 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
  */
 void __init mapin_ram(void)
 {
-        unsigned long v, p, s, f;
+        unsigned long v, s, f;
+        phys_addr_t p;
         int ktext;
 
         s = mmu_mapin_ram();
         v = KERNELBASE + s;
-        p = PPC_MEMSTART + s;
+        p = memstart_addr + s;
         for (; s < total_lowmem; s += PAGE_SIZE) {
                 ktext = ((char *) v >= _stext && (char *) v < etext);
                 f = ktext ?_PAGE_RAM_TEXT : _PAGE_RAM;
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index 5c45d474cfcc..cef9f156874b 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -26,11 +26,11 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/highmem.h>
+#include <linux/lmb.h>
 
 #include <asm/prom.h>
 #include <asm/mmu.h>
 #include <asm/machdep.h>
-#include <asm/lmb.h>
 
 #include "mmu_decl.h"
 
@@ -82,7 +82,6 @@ unsigned long __init mmu_mapin_ram(void)
 #else
         unsigned long tot, bl, done;
         unsigned long max_size = (256<<20);
-        unsigned long align;
 
         if (__map_without_bats) {
                 printk(KERN_DEBUG "RAM mapped without BATs\n");
@@ -93,19 +92,13 @@ unsigned long __init mmu_mapin_ram(void)
 
         /* Make sure we don't map a block larger than the
            smallest alignment of the physical address. */
-        /* alignment of PPC_MEMSTART */
-        align = ~(PPC_MEMSTART-1) & PPC_MEMSTART;
-        /* set BAT block size to MIN(max_size, align) */
-        if (align && align < max_size)
-                max_size = align;
-
         tot = total_lowmem;
         for (bl = 128<<10; bl < max_size; bl <<= 1) {
                 if (bl * 2 > tot)
                         break;
         }
 
-        setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
+        setbat(2, KERNELBASE, 0, bl, _PAGE_RAM);
         done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
         if ((done < tot) && !bat_addrs[3].limit) {
                 /* use BAT3 to cover a bit more */
@@ -113,7 +106,7 @@ unsigned long __init mmu_mapin_ram(void)
                 for (bl = 128<<10; bl < max_size; bl <<= 1)
                         if (bl * 2 > tot)
                                 break;
-                setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
+                setbat(3, KERNELBASE+done, done, bl, _PAGE_RAM);
                 done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
         }
 
@@ -240,7 +233,7 @@ void __init MMU_init_hw(void)
          */
         if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
         Hash = __va(lmb_alloc_base(Hash_size, Hash_size,
-                                   __initial_memory_limit));
+                                   __initial_memory_limit_addr));
         cacheable_memzero(Hash, Hash_size);
         _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
 
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 50448d5de9d2..efbbd13d93e5 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -12,12 +12,14 @@
  *      2 of the License, or (at your option) any later version.
  */
 
+#include <linux/lmb.h>
+
 #include <asm/pgtable.h>
 #include <asm/mmu.h>
 #include <asm/mmu_context.h>
 #include <asm/paca.h>
 #include <asm/cputable.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/abs_addr.h>
 #include <asm/firmware.h>
 #include <asm/iseries/hv_call.h>
diff --git a/arch/powerpc/oprofile/cell/spu_task_sync.c b/arch/powerpc/oprofile/cell/spu_task_sync.c
index 257b13cb18af..2a9b4a049329 100644
--- a/arch/powerpc/oprofile/cell/spu_task_sync.c
+++ b/arch/powerpc/oprofile/cell/spu_task_sync.c
@@ -68,7 +68,7 @@ static struct cached_info *get_cached_info(struct spu *the_spu, int spu_num)
         if (spu_num >= num_spu_nodes) {
                 printk(KERN_ERR "SPU_PROF: "
                        "%s, line %d: Invalid index %d into spu info cache\n",
-                       __FUNCTION__, __LINE__, spu_num);
+                       __func__, __LINE__, spu_num);
                 ret_info = NULL;
                 goto out;
         }
@@ -115,7 +115,7 @@ prepare_cached_spu_info(struct spu *spu, unsigned long objectId)
         if (!info) {
                 printk(KERN_ERR "SPU_PROF: "
                        "%s, line %d: create vma_map failed\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 retval = -ENOMEM;
                 goto err_alloc;
         }
@@ -123,7 +123,7 @@ prepare_cached_spu_info(struct spu *spu, unsigned long objectId)
         if (!new_map) {
                 printk(KERN_ERR "SPU_PROF: "
                        "%s, line %d: create vma_map failed\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 retval = -ENOMEM;
                 goto err_alloc;
         }
@@ -171,7 +171,7 @@ static int release_cached_info(int spu_index)
                         printk(KERN_ERR "SPU_PROF: "
                                 "%s, line %d: "
                                 "Invalid index %d into spu info cache\n",
-                                __FUNCTION__, __LINE__, spu_index);
+                                __func__, __LINE__, spu_index);
                         goto out;
                 }
                 end = spu_index + 1;
@@ -273,7 +273,7 @@ fail_no_image_cookie:
 
         printk(KERN_ERR "SPU_PROF: "
                 "%s, line %d: Cannot find dcookie for SPU binary\n",
-                __FUNCTION__, __LINE__);
+                __func__, __LINE__);
         goto out;
 }
 
@@ -467,7 +467,7 @@ int spu_sync_stop(void)
         if (ret) {
                 printk(KERN_ERR "SPU_PROF: "
                         "%s, line %d: spu_switch_event_unregister returned %d\n",
-                        __FUNCTION__, __LINE__, ret);
+                        __func__, __LINE__, ret);
                 goto out;
         }
 
diff --git a/arch/powerpc/oprofile/cell/vma_map.c b/arch/powerpc/oprofile/cell/vma_map.c
index 9a932177e70e..fff66662d021 100644
--- a/arch/powerpc/oprofile/cell/vma_map.c
+++ b/arch/powerpc/oprofile/cell/vma_map.c
@@ -72,7 +72,7 @@ vma_map_add(struct vma_to_fileoffset_map *map, unsigned int vma,
                 kzalloc(sizeof(struct vma_to_fileoffset_map), GFP_KERNEL);
         if (!new) {
                 printk(KERN_ERR "SPU_PROF: %s, line %d: malloc failed\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 vma_map_free(map);
                 return NULL;
         }
@@ -134,19 +134,19 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
         if (memcmp(ehdr.e_ident, expected, EI_PAD) != 0) {
                 printk(KERN_ERR "SPU_PROF: "
                        "%s, line %d: Unexpected e_ident parsing SPU ELF\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 goto fail;
         }
         if (ehdr.e_machine != EM_SPU) {
                 printk(KERN_ERR "SPU_PROF: "
                        "%s, line %d: Unexpected e_machine parsing SPU ELF\n",
-                       __FUNCTION__,  __LINE__);
+                       __func__,  __LINE__);
                 goto fail;
         }
         if (ehdr.e_type != ET_EXEC) {
                 printk(KERN_ERR "SPU_PROF: "
                        "%s, line %d: Unexpected e_type parsing SPU ELF\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 goto fail;
         }
         phdr_start = spu_elf_start + ehdr.e_phoff;
@@ -232,7 +232,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
         if (overlay_tbl_offset < 0) {
                 printk(KERN_ERR "SPU_PROF: "
                        "%s, line %d: Error finding SPU overlay table\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 goto fail;
         }
         ovly_table = spu_elf_start + overlay_tbl_offset;
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index 9eed1f68fcab..5ff4de3eb3be 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -216,7 +216,7 @@ static void pm_rtas_reset_signals(u32 node)
                  * failure to stop OProfile.
                  */
                 printk(KERN_WARNING "%s: rtas returned: %d\n",
-                       __FUNCTION__, ret);
+                       __func__, ret);
 }
 
 static int pm_rtas_activate_signals(u32 node, u32 count)
@@ -255,7 +255,7 @@ static int pm_rtas_activate_signals(u32 node, u32 count)
 
                 if (unlikely(ret)) {
                         printk(KERN_WARNING "%s: rtas returned: %d\n",
-                               __FUNCTION__, ret);
+                               __func__, ret);
                         return -EIO;
                 }
         }
@@ -560,7 +560,7 @@ static int cell_reg_setup(struct op_counter_config *ctr,
                 if (unlikely(spu_rtas_token == RTAS_UNKNOWN_SERVICE)) {
                         printk(KERN_ERR
                                "%s: rtas token ibm,cbe-spu-perftools unknown\n",
-                               __FUNCTION__);
+                               __func__);
                         return -EIO;
                 }
         }
@@ -576,7 +576,7 @@ static int cell_reg_setup(struct op_counter_config *ctr,
         if (unlikely(pm_rtas_token == RTAS_UNKNOWN_SERVICE)) {
                 printk(KERN_ERR
                        "%s: rtas token ibm,cbe-perftools unknown\n",
-                       __FUNCTION__);
+                       __func__);
                 return -EIO;
         }
 
@@ -853,7 +853,7 @@ static int pm_rtas_activate_spu_profiling(u32 node)
 
         if (unlikely(ret)) {
                 printk(KERN_WARNING "%s: rtas returned: %d\n",
-                       __FUNCTION__, ret);
+                       __func__, ret);
                 return -EIO;
         }
 
@@ -949,7 +949,7 @@ static int cell_global_start_spu(struct op_counter_config *ctr)
                 if (unlikely(ret != 0)) {
                         printk(KERN_ERR
                                "%s: rtas call ibm,cbe-spu-perftools failed, return = %d\n",
-                               __FUNCTION__, ret);
+                               __func__, ret);
                         rtas_error = -EIO;
                         goto out;
                 }
@@ -1061,7 +1061,7 @@ static void cell_global_stop_spu(void)
                 if (unlikely(rtn_value != 0)) {
                         printk(KERN_ERR
                                "%s: rtas call ibm,cbe-spu-perftools failed, return = %d\n",
-                               __FUNCTION__, rtn_value);
+                               __func__, rtn_value);
                 }
 
                 /* Deactivate the signals */
diff --git a/arch/powerpc/platforms/40x/ep405.c b/arch/powerpc/platforms/40x/ep405.c
index 13d1345026da..ae2e7f67c18e 100644
--- a/arch/powerpc/platforms/40x/ep405.c
+++ b/arch/powerpc/platforms/40x/ep405.c
@@ -29,6 +29,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
 
 static struct device_node *bcsr_node;
 static void __iomem *bcsr_regs;
@@ -119,5 +120,6 @@ define_machine(ep405) {
         .progress               = udbg_progress,
         .init_IRQ               = uic_init_tree,
         .get_irq                = uic_get_irq,
+        .restart                = ppc4xx_reset_system,
         .calibrate_decr         = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/40x/kilauea.c b/arch/powerpc/platforms/40x/kilauea.c
index f9206a7fede0..1dd24ffc0dc1 100644
--- a/arch/powerpc/platforms/40x/kilauea.c
+++ b/arch/powerpc/platforms/40x/kilauea.c
@@ -1,7 +1,7 @@
 /*
  * Kilauea board specific routines
  *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * Copyright 2007-2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * Based on the Walnut code by
  * Josh Boyer <jwboyer@linux.vnet.ibm.com>
@@ -20,6 +20,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id kilauea_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -54,5 +55,6 @@ define_machine(kilauea) {
         .progress                       = udbg_progress,
         .init_IRQ                       = uic_init_tree,
         .get_irq                        = uic_get_irq,
+        .restart                        = ppc4xx_reset_system,
         .calibrate_decr                 = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/40x/makalu.c b/arch/powerpc/platforms/40x/makalu.c
index 4e4df72fc9cd..a6a1d6017b71 100644
--- a/arch/powerpc/platforms/40x/makalu.c
+++ b/arch/powerpc/platforms/40x/makalu.c
@@ -20,6 +20,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id makalu_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -54,5 +55,6 @@ define_machine(makalu) {
         .progress                       = udbg_progress,
         .init_IRQ                       = uic_init_tree,
         .get_irq                        = uic_get_irq,
+        .restart                        = ppc4xx_reset_system,
         .calibrate_decr                 = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
index 0422590040db..fc7fb001276c 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -14,6 +14,7 @@
 #include <asm/prom.h>
 #include <asm/time.h>
 #include <asm/xilinx_intc.h>
+#include <asm/ppc4xx.h>
 
 static struct of_device_id xilinx_of_bus_ids[] __initdata = {
         { .compatible = "xlnx,plb-v46-1.00.a", },
@@ -48,5 +49,6 @@ define_machine(virtex) {
         .probe                  = virtex_probe,
         .init_IRQ               = xilinx_intc_init_tree,
         .get_irq                = xilinx_intc_get_irq,
+        .restart                = ppc4xx_reset_system,
         .calibrate_decr         = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/40x/walnut.c b/arch/powerpc/platforms/40x/walnut.c
index b8b257efeb77..335df91fbee5 100644
--- a/arch/powerpc/platforms/40x/walnut.c
+++ b/arch/powerpc/platforms/40x/walnut.c
@@ -26,6 +26,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id walnut_of_bus[] = {
         { .compatible = "ibm,plb3", },
@@ -61,5 +62,6 @@ define_machine(walnut) {
         .progress               = udbg_progress,
         .init_IRQ               = uic_init_tree,
         .get_irq                = uic_get_irq,
-        .calibrate_decr = generic_calibrate_decr,
+        .restart                = ppc4xx_reset_system,
+        .calibrate_decr         = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/44x.h b/arch/powerpc/platforms/44x/44x.h
index 42eabf87fea3..dbc4d2b4301a 100644
--- a/arch/powerpc/platforms/44x/44x.h
+++ b/arch/powerpc/platforms/44x/44x.h
@@ -3,6 +3,5 @@
 
 extern u8 as1_readb(volatile u8 __iomem  *addr);
 extern void as1_writeb(u8 data, volatile u8 __iomem *addr);
-extern void ppc44x_reset_system(char *cmd);
 
 #endif /* __POWERPC_PLATFORMS_44X_44X_H */
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 1bfb2191010a..6abe91357eee 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -67,6 +67,25 @@ config WARP
           See http://www.pikatechnologies.com/ and follow the "PIKA for Computer
           Telephony Developers" link for more information.
 
+config CANYONLANDS
+        bool "Canyonlands"
+        depends on 44x
+        default n
+        select 460EX
+        select PCI
+        select PPC4xx_PCI_EXPRESS
+        help
+          This option enables support for the AMCC PPC460EX evaluation board.
+
+config YOSEMITE
+        bool "Yosemite"
+        depends on 44x
+        default n
+        select 440EP
+        select PCI
+        help
+          This option enables support for the AMCC PPC440EP evaluation board.
+
 #config LUAN
 #       bool "Luan"
 #       depends on 44x
@@ -122,6 +141,14 @@ config 440SPe
         bool
         select IBM_NEW_EMAC_EMAC4
 
+config 460EX
+        bool
+        select PPC_FPU
+        select IBM_NEW_EMAC_EMAC4
+        select IBM_NEW_EMAC_RGMII
+        select IBM_NEW_EMAC_ZMII
+        select IBM_NEW_EMAC_TAH
+
 # 44x errata/workaround config symbols, selected by the CPU models above
 config IBM440EP_ERR42
         bool
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 0864d4f1cbc2..774165f9acdd 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -1,9 +1,11 @@
-obj-$(CONFIG_44x)       := misc_44x.o
+obj-$(CONFIG_44x)       := misc_44x.o idle.o
 obj-$(CONFIG_EBONY)     += ebony.o
 obj-$(CONFIG_TAISHAN)   += taishan.o
 obj-$(CONFIG_BAMBOO)    += bamboo.o
+obj-$(CONFIG_YOSEMITE)  += bamboo.o
 obj-$(CONFIG_SEQUOIA)   += sequoia.o
 obj-$(CONFIG_KATMAI)    += katmai.o
 obj-$(CONFIG_RAINIER)   += rainier.o
 obj-$(CONFIG_WARP)      += warp.o
 obj-$(CONFIG_WARP)      += warp-nand.o
+obj-$(CONFIG_CANYONLANDS) += canyonlands.o
diff --git a/arch/powerpc/platforms/44x/bamboo.c b/arch/powerpc/platforms/44x/bamboo.c
index fb9a22a7e8d0..cef169e95156 100644
--- a/arch/powerpc/platforms/44x/bamboo.c
+++ b/arch/powerpc/platforms/44x/bamboo.c
@@ -22,8 +22,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id bamboo_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -53,11 +52,11 @@ static int __init bamboo_probe(void)
 }
 
 define_machine(bamboo) {
-        .name                           = "Bamboo",
-        .probe                          = bamboo_probe,
-        .progress                       = udbg_progress,
-        .init_IRQ                       = uic_init_tree,
-        .get_irq                        = uic_get_irq,
-        .restart                        = ppc44x_reset_system,
+        .name                   = "Bamboo",
+        .probe                  = bamboo_probe,
+        .progress               = udbg_progress,
+        .init_IRQ               = uic_init_tree,
+        .get_irq                = uic_get_irq,
+        .restart                = ppc4xx_reset_system,
         .calibrate_decr         = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c
new file mode 100644
index 000000000000..3949289f51df
--- /dev/null
+++ b/arch/powerpc/platforms/44x/canyonlands.c
@@ -0,0 +1,63 @@
+/*
+ * Canyonlands board specific routines
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * Based on the Katmai code by
+ * Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ * Copyright 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ * Copyright 2007 IBM Corporation
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/time.h>
+#include <asm/uic.h>
+#include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
+
+static __initdata struct of_device_id canyonlands_of_bus[] = {
+        { .compatible = "ibm,plb4", },
+        { .compatible = "ibm,opb", },
+        { .compatible = "ibm,ebc", },
+        {},
+};
+
+static int __init canyonlands_device_probe(void)
+{
+        of_platform_bus_probe(NULL, canyonlands_of_bus, NULL);
+
+        return 0;
+}
+machine_device_initcall(canyonlands, canyonlands_device_probe);
+
+static int __init canyonlands_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (!of_flat_dt_is_compatible(root, "amcc,canyonlands"))
+                return 0;
+
+        ppc_pci_flags = PPC_PCI_REASSIGN_ALL_RSRC;
+
+        return 1;
+}
+
+define_machine(canyonlands) {
+        .name                           = "Canyonlands",
+        .probe                          = canyonlands_probe,
+        .progress                       = udbg_progress,
+        .init_IRQ                       = uic_init_tree,
+        .get_irq                        = uic_get_irq,
+        .restart                        = ppc4xx_reset_system,
+        .calibrate_decr                 = generic_calibrate_decr,
+};
diff --git a/arch/powerpc/platforms/44x/ebony.c b/arch/powerpc/platforms/44x/ebony.c
index 1a8d467bff85..a0e8fe4662f6 100644
--- a/arch/powerpc/platforms/44x/ebony.c
+++ b/arch/powerpc/platforms/44x/ebony.c
@@ -26,8 +26,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id ebony_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -66,6 +65,6 @@ define_machine(ebony) {
         .progress               = udbg_progress,
         .init_IRQ               = uic_init_tree,
         .get_irq                = uic_get_irq,
-        .restart                = ppc44x_reset_system,
+        .restart                = ppc4xx_reset_system,
         .calibrate_decr         = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/idle.c b/arch/powerpc/platforms/44x/idle.c
new file mode 100644
index 000000000000..7a81f921fef9
--- /dev/null
+++ b/arch/powerpc/platforms/44x/idle.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2008 IBM Corp. 
+ *
+ * Based on arch/powerpc/platforms/pasemi/idle.c: 
+ * Copyright (C) 2006-2007 PA Semi, Inc
+ *
+ * Added by: Jerone Young <jyoung5@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <linux/of.h>
+#include <linux/kernel.h>
+#include <asm/machdep.h>
+
+static int mode_spin;
+
+static void ppc44x_idle(void)
+{
+        unsigned long msr_save;
+
+        msr_save = mfmsr();
+        /* set wait state MSR */
+        mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE|MSR_DE);
+        isync();
+        /* return to initial state */
+        mtmsr(msr_save);
+        isync();
+}
+
+int __init ppc44x_idle_init(void)
+{
+        if (!mode_spin) {
+                /* If we are not setting spin mode 
+                   then we set to wait mode */
+                ppc_md.power_save = &ppc44x_idle;
+        }
+
+        return 0;
+}
+
+arch_initcall(ppc44x_idle_init);
+
+static int __init idle_param(char *p)
+{ 
+
+        if (!strcmp("spin", p)) {
+                mode_spin = 1;
+                ppc_md.power_save = NULL;
+        }
+
+        return 0;
+}
+
+early_param("idle", idle_param);
diff --git a/arch/powerpc/platforms/44x/katmai.c b/arch/powerpc/platforms/44x/katmai.c
index 11134121f272..44f4b3a00ced 100644
--- a/arch/powerpc/platforms/44x/katmai.c
+++ b/arch/powerpc/platforms/44x/katmai.c
@@ -22,8 +22,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id katmai_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -58,6 +57,6 @@ define_machine(katmai) {
         .progress                       = udbg_progress,
         .init_IRQ                       = uic_init_tree,
         .get_irq                        = uic_get_irq,
-        .restart                        = ppc44x_reset_system,
+        .restart                        = ppc4xx_reset_system,
         .calibrate_decr                 = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/misc_44x.S b/arch/powerpc/platforms/44x/misc_44x.S
index 3bce71d5d756..dc12b8009e48 100644
--- a/arch/powerpc/platforms/44x/misc_44x.S
+++ b/arch/powerpc/platforms/44x/misc_44x.S
@@ -44,14 +44,3 @@ _GLOBAL(as1_writeb)
         sync
         isync
         blr
-
-/*
- * void ppc44x_reset_system(char *cmd)
- *
- * At present, this routine just applies a system reset.
- */
-_GLOBAL(ppc44x_reset_system)
-        mfspr   r13,SPRN_DBCR0
-        oris    r13,r13,DBCR0_RST_SYSTEM@h
-        mtspr   SPRN_DBCR0,r13
-        b       .                       /* Just in case the reset doesn't work */
diff --git a/arch/powerpc/platforms/44x/rainier.c b/arch/powerpc/platforms/44x/rainier.c
index a7fae1cf69c1..4f1ff84c4b63 100644
--- a/arch/powerpc/platforms/44x/rainier.c
+++ b/arch/powerpc/platforms/44x/rainier.c
@@ -22,7 +22,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
-#include "44x.h"
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id rainier_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -57,6 +57,6 @@ define_machine(rainier) {
         .progress                       = udbg_progress,
         .init_IRQ                       = uic_init_tree,
         .get_irq                        = uic_get_irq,
-        .restart                        = ppc44x_reset_system,
+        .restart                        = ppc4xx_reset_system,
         .calibrate_decr                 = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/sequoia.c b/arch/powerpc/platforms/44x/sequoia.c
index d279db42c896..49eb73daacdf 100644
--- a/arch/powerpc/platforms/44x/sequoia.c
+++ b/arch/powerpc/platforms/44x/sequoia.c
@@ -23,7 +23,7 @@
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
 
-#include "44x.h"
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id sequoia_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -58,6 +58,6 @@ define_machine(sequoia) {
         .progress                       = udbg_progress,
         .init_IRQ                       = uic_init_tree,
         .get_irq                        = uic_get_irq,
-        .restart                        = ppc44x_reset_system,
+        .restart                        = ppc4xx_reset_system,
         .calibrate_decr                 = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/taishan.c b/arch/powerpc/platforms/44x/taishan.c
index 28ab7e2e02c3..49c78b2098b4 100644
--- a/arch/powerpc/platforms/44x/taishan.c
+++ b/arch/powerpc/platforms/44x/taishan.c
@@ -29,8 +29,7 @@
 #include <asm/time.h>
 #include <asm/uic.h>
 #include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id taishan_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -68,6 +67,6 @@ define_machine(taishan) {
         .progress               = udbg_progress,
         .init_IRQ               = uic_init_tree,
         .get_irq                = uic_get_irq,
-        .restart                = ppc44x_reset_system,
+        .restart                = ppc4xx_reset_system,
         .calibrate_decr         = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/warp-nand.c b/arch/powerpc/platforms/44x/warp-nand.c
index 84ab78ff8c03..9150318cfc56 100644
--- a/arch/powerpc/platforms/44x/warp-nand.c
+++ b/arch/powerpc/platforms/44x/warp-nand.c
@@ -11,6 +11,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/ndfc.h>
+#include <asm/machdep.h>
 
 #ifdef CONFIG_MTD_NAND_NDFC
 
@@ -100,6 +101,6 @@ static int warp_setup_nand_flash(void)
 
         return 0;
 }
-device_initcall(warp_setup_nand_flash);
+machine_device_initcall(warp, warp_setup_nand_flash);
 
 #endif
diff --git a/arch/powerpc/platforms/44x/warp.c b/arch/powerpc/platforms/44x/warp.c
index da5b7b7599db..39cf6150a72b 100644
--- a/arch/powerpc/platforms/44x/warp.c
+++ b/arch/powerpc/platforms/44x/warp.c
@@ -18,9 +18,7 @@
 #include <asm/udbg.h>
 #include <asm/time.h>
 #include <asm/uic.h>
-
-#include "44x.h"
-
+#include <asm/ppc4xx.h>
 
 static __initdata struct of_device_id warp_of_bus[] = {
         { .compatible = "ibm,plb4", },
@@ -49,7 +47,7 @@ define_machine(warp) {
         .progress       = udbg_progress,
         .init_IRQ       = uic_init_tree,
         .get_irq        = uic_get_irq,
-        .restart        = ppc44x_reset_system,
+        .restart        = ppc4xx_reset_system,
         .calibrate_decr = generic_calibrate_decr,
 };
 
diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c
index 956f459e175c..6d584f4e3c9a 100644
--- a/arch/powerpc/platforms/52xx/lite5200.c
+++ b/arch/powerpc/platforms/52xx/lite5200.c
@@ -63,7 +63,7 @@ lite5200_fix_clock_config(void)
         of_node_put(np);
         if (!cdm) {
                 printk(KERN_ERR "%s() failed; expect abnormal behaviour\n",
-                       __FUNCTION__);
+                       __func__);
                 return;
         }
 
@@ -98,7 +98,7 @@ lite5200_fix_port_config(void)
         of_node_put(np);
         if (!gpio) {
                 printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
-                       __FUNCTION__);
+                       __func__);
                 return;
         }
 
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
index 4fad6c7bf9f1..917ac8891555 100644
--- a/arch/powerpc/platforms/82xx/Kconfig
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -11,7 +11,6 @@ config MPC8272_ADS
         select 8260
         select FSL_SOC
         select PQ2_ADS_PCI_PIC if PCI
-        select PPC_CPM_NEW_BINDING
         help
           This option enables support for the MPC8272 ADS board
 
@@ -22,7 +21,6 @@ config PQ2FADS
         select 8260
         select FSL_SOC
         select PQ2_ADS_PCI_PIC if PCI
-        select PPC_CPM_NEW_BINDING
         help
           This option enables support for the PQ2FADS board
 
@@ -31,7 +29,6 @@ config EP8248E
         select 8272
         select 8260
         select FSL_SOC
-        select PPC_CPM_NEW_BINDING
         select MDIO_BITBANG
         help
           This enables support for the Embedded Planet EP8248E board.
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 2293ae51383d..c00356bdb1dd 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -46,6 +46,7 @@ static void __init mpc837x_rdb_setup_arch(void)
 static struct of_device_id mpc837x_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 68065e62fc3d..88a3b5cabb18 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -16,6 +16,7 @@
 #define MPC83XX_SCCR_USB_DRCM_10   0x00200000
 #define MPC8315_SCCR_USB_MASK      0x00c00000
 #define MPC8315_SCCR_USB_DRCM_11   0x00c00000
+#define MPC8315_SCCR_USB_DRCM_01   0x00400000
 #define MPC837X_SCCR_USB_DRCM_11   0x00c00000
 
 /* system i/o configuration register low */
@@ -37,6 +38,7 @@
 /* USB Control Register */
 #define FSL_USB2_CONTROL_OFFS      0x500
 #define CONTROL_UTMI_PHY_EN        0x00000200
+#define CONTROL_REFSEL_24MHZ       0x00000040
 #define CONTROL_REFSEL_48MHZ       0x00000080
 #define CONTROL_PHY_CLK_SEL_ULPI   0x00000400
 #define CONTROL_OTG_PORT           0x00000020
diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c
index 471fdd8f4108..64bcf0a33c71 100644
--- a/arch/powerpc/platforms/83xx/usb.c
+++ b/arch/powerpc/platforms/83xx/usb.c
@@ -129,7 +129,7 @@ int mpc831x_usb_cfg(void)
         if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
                 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
                                 MPC8315_SCCR_USB_MASK,
-                                MPC8315_SCCR_USB_DRCM_11);
+                                MPC8315_SCCR_USB_DRCM_01);
         else
                 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
                                 MPC83XX_SCCR_USB_MASK,
@@ -164,9 +164,15 @@ int mpc831x_usb_cfg(void)
         /* Using on-chip PHY */
         if (prop && (!strcmp(prop, "utmi_wide") ||
                      !strcmp(prop, "utmi"))) {
-                /* Set UTMI_PHY_EN, REFSEL to 48MHZ */
+                u32 refsel;
+
+                if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
+                        refsel = CONTROL_REFSEL_24MHZ;
+                else
+                        refsel = CONTROL_REFSEL_48MHZ;
+                /* Set UTMI_PHY_EN and REFSEL */
                 out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
-                                CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ);
+                                CONTROL_UTMI_PHY_EN | refsel);
         /* Using external UPLI PHY */
         } else if (prop && !strcmp(prop, "ulpi")) {
                 /* Set PHY_CLK_SEL to ULPI */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 7e76ddbd5821..7ff29d53dc2d 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -19,7 +19,6 @@ config MPC8540_ADS
 config MPC8560_ADS
         bool "Freescale MPC8560 ADS"
         select DEFAULT_UIMAGE
-        select PPC_CPM_NEW_BINDING
         select CPM2
         help
           This option enables support for the MPC 8560 ADS board
@@ -46,6 +45,12 @@ config MPC85xx_DS
         help
           This option enables support for the MPC85xx DS (MPC8544 DS) board
 
+config KSI8560
+        bool "Emerson KSI8560"
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the Emerson KSI8560 board
+
 config STX_GP3
         bool "Silicon Turnkey Express GP3"
         help
@@ -53,14 +58,12 @@ config STX_GP3
           board.
         select CPM2
         select DEFAULT_UIMAGE
-        select PPC_CPM_NEW_BINDING
 
 config TQM8540
         bool "TQ Components TQM8540"
         help
           This option enables support for the TQ Components TQM8540 board.
         select DEFAULT_UIMAGE
-        select PPC_CPM_NEW_BINDING
         select TQM85xx
 
 config TQM8541
@@ -68,7 +71,6 @@ config TQM8541
         help
           This option enables support for the TQ Components TQM8541 board.
         select DEFAULT_UIMAGE
-        select PPC_CPM_NEW_BINDING
         select TQM85xx
         select CPM2
 
@@ -77,7 +79,6 @@ config TQM8555
         help
           This option enables support for the TQ Components TQM8555 board.
         select DEFAULT_UIMAGE
-        select PPC_CPM_NEW_BINDING
         select TQM85xx
         select CPM2
 
@@ -86,7 +87,6 @@ config TQM8560
         help
           This option enables support for the TQ Components TQM8560 board.
         select DEFAULT_UIMAGE
-        select PPC_CPM_NEW_BINDING
         select TQM85xx
         select CPM2
 
@@ -99,7 +99,6 @@ config SBC8548
 config SBC8560
         bool "Wind River SBC8560"
         select DEFAULT_UIMAGE
-        select PPC_CPM_NEW_BINDING if CPM2
         help
           This option enables support for the Wind River SBC8560 board
 
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index cb7af4ebd75f..6cea185f62b2 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_STX_GP3)	  += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
 obj-$(CONFIG_SBC8560)     += sbc8560.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
+obj-$(CONFIG_KSI8560)     += ksi8560.o
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
new file mode 100644
index 000000000000..2145adeb220c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -0,0 +1,257 @@
+/*
+ * Board setup routines for the Emerson KSI8560
+ *
+ * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
+ *
+ * Based on mpc85xx_ads.c maintained by Kumar Gala
+ *
+ * 2008 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpic.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+#include <asm/prom.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include <asm/cpm2.h>
+#include <sysdev/cpm2_pic.h>
+
+
+#define KSI8560_CPLD_HVR                0x04 /* Hardware Version Register */
+#define KSI8560_CPLD_PVR                0x08 /* PLD Version Register */
+#define KSI8560_CPLD_RCR1               0x30 /* Reset Command Register 1 */
+
+#define KSI8560_CPLD_RCR1_CPUHR         0x80 /* CPU Hard Reset */
+
+static void __iomem *cpld_base = NULL;
+
+static void machine_restart(char *cmd)
+{
+        if (cpld_base)
+                out_8(cpld_base + KSI8560_CPLD_RCR1, KSI8560_CPLD_RCR1_CPUHR);
+        else
+                printk(KERN_ERR "Can't find CPLD base, hang forever\n");
+
+        for (;;);
+}
+
+static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        int cascade_irq;
+
+        while ((cascade_irq = cpm2_get_irq()) >= 0)
+                generic_handle_irq(cascade_irq);
+
+        desc->chip->eoi(irq);
+}
+
+static void __init ksi8560_pic_init(void)
+{
+        struct mpic *mpic;
+        struct resource r;
+        struct device_node *np;
+#ifdef CONFIG_CPM2
+        int irq;
+#endif
+
+        np = of_find_node_by_type(NULL, "open-pic");
+
+        if (np == NULL) {
+                printk(KERN_ERR "Could not find open-pic node\n");
+                return;
+        }
+
+        if (of_address_to_resource(np, 0, &r)) {
+                printk(KERN_ERR "Could not map mpic register space\n");
+                of_node_put(np);
+                return;
+        }
+
+        mpic = mpic_alloc(np, r.start,
+                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+                        0, 256, " OpenPIC  ");
+        BUG_ON(mpic == NULL);
+        of_node_put(np);
+
+        mpic_init(mpic);
+
+#ifdef CONFIG_CPM2
+        /* Setup CPM2 PIC */
+        np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
+        if (np == NULL) {
+                printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
+                return;
+        }
+        irq = irq_of_parse_and_map(np, 0);
+
+        cpm2_pic_init(np);
+        of_node_put(np);
+        set_irq_chained_handler(irq, cpm2_cascade);
+
+        setup_irq(0, NULL);
+#endif
+}
+
+#ifdef CONFIG_CPM2
+/*
+ * Setup I/O ports
+ */
+struct cpm_pin {
+        int port, pin, flags;
+};
+
+static struct cpm_pin __initdata ksi8560_pins[] = {
+        /* SCC1 */
+        {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+        /* SCC2 */
+        {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+        /* FCC1 */
+        {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK9 */
+        {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK10 */
+
+};
+
+static void __init init_ioports(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(ksi8560_pins); i++) {
+                struct cpm_pin *pin = &ksi8560_pins[i];
+                cpm2_set_pin(pin->port, pin->pin, pin->flags);
+        }
+
+        cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
+        cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
+        cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
+}
+#endif
+
+/*
+ * Setup the architecture
+ */
+static void __init ksi8560_setup_arch(void)
+{
+        struct device_node *cpld;
+
+        cpld = of_find_compatible_node(NULL, NULL, "emerson,KSI8560-cpld");
+        if (cpld)
+                cpld_base = of_iomap(cpld, 0);
+        else
+                printk(KERN_ERR "Can't find CPLD in device tree\n");
+
+        if (ppc_md.progress)
+                ppc_md.progress("ksi8560_setup_arch()", 0);
+
+#ifdef CONFIG_CPM2
+        cpm2_reset();
+        init_ioports();
+#endif
+}
+
+static void ksi8560_show_cpuinfo(struct seq_file *m)
+{
+        uint pvid, svid, phid1;
+        uint memsize = total_memory;
+
+        pvid = mfspr(SPRN_PVR);
+        svid = mfspr(SPRN_SVR);
+
+        seq_printf(m, "Vendor\t\t: Emerson Network Power\n");
+        seq_printf(m, "Board\t\t: KSI8560\n");
+
+        if (cpld_base) {
+                seq_printf(m, "Hardware rev\t: %d\n",
+                                        in_8(cpld_base + KSI8560_CPLD_HVR));
+                seq_printf(m, "CPLD rev\t: %d\n",
+                                        in_8(cpld_base + KSI8560_CPLD_PVR));
+        } else
+                seq_printf(m, "Unknown Hardware and CPLD revs\n");
+
+        seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+        /* Display cpu Pll setting */
+        phid1 = mfspr(SPRN_HID1);
+        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+
+        /* Display the amount of memory */
+        seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .type = "soc", },
+        { .name = "cpm", },
+        { .name = "localbus", },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+        return 0;
+}
+machine_device_initcall(ksi8560, declare_of_platform_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ksi8560_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "emerson,KSI8560");
+}
+
+define_machine(ksi8560) {
+        .name                   = "KSI8560",
+        .probe                  = ksi8560_probe,
+        .setup_arch             = ksi8560_setup_arch,
+        .init_IRQ               = ksi8560_pic_init,
+        .show_cpuinfo           = ksi8560_show_cpuinfo,
+        .get_irq                = mpic_get_irq,
+        .restart                = machine_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 4e0305096114..3582c841844b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -165,7 +165,7 @@ static void __init init_ioports(void)
         int i;
 
         for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
-                struct cpm_pin *pin = &mpc8560_ads_pins[i];
+                const struct cpm_pin *pin = &mpc8560_ads_pins[i];
                 cpm2_set_pin(pin->port, pin->pin, pin->flags);
         }
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index bdb3d0b38cd2..dfd8b4ad9b28 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -19,6 +19,7 @@
 #include <linux/delay.h>
 #include <linux/seq_file.h>
 #include <linux/interrupt.h>
+#include <linux/of_platform.h>
 
 #include <asm/system.h>
 #include <asm/time.h>
@@ -36,7 +37,7 @@
 #undef DEBUG
 
 #ifdef DEBUG
-#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
 #else
 #define DBG(fmt, args...)
 #endif
@@ -183,6 +184,18 @@ static int __init mpc8544_ds_probe(void)
         }
 }
 
+static struct of_device_id mpc85xxds_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        {},
+};
+
+static int __init mpc85xxds_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
+}
+machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
+
 /*
  * Called very early, device-tree isn't unflattened
  */
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 21d113536b86..7442c58d44f5 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -11,6 +11,12 @@ config MPC8641_HPCN
         help
           This option enables support for the MPC8641 HPCN board.
 
+config SBC8641D
+        bool "Wind River SBC8641D"
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the WRS SBC8641D board.
+
 config MPC8610_HPCD
         bool "Freescale MPC8610 HPCD"
         select DEFAULT_UIMAGE
@@ -24,7 +30,7 @@ config MPC8641
         select FSL_PCI if PCI
         select PPC_UDBG_16550
         select MPIC
-        default y if MPC8641_HPCN
+        default y if MPC8641_HPCN || SBC8641D
 
 config MPC8610
         bool
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index c96706327eaa..1b9b4a9b2525 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -4,4 +4,5 @@
 
 obj-$(CONFIG_SMP)               += mpc86xx_smp.o
 obj-$(CONFIG_MPC8641_HPCN)      += mpc86xx_hpcn.o
+obj-$(CONFIG_SBC8641D)          += sbc8641d.o
 obj-$(CONFIG_MPC8610_HPCD)      += mpc8610_hpcd.o
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 0b07485641fe..18b8ebe930d5 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -52,7 +52,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
 }
 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
 
-void __init
+static void __init
 mpc86xx_hpcd_init_irq(void)
 {
         struct mpic *mpic1;
@@ -200,7 +200,7 @@ static int __init mpc86xx_hpcd_probe(void)
         return 0;
 }
 
-long __init
+static long __init
 mpc86xx_time_init(void)
 {
         unsigned int temp;
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index cfbe8c52e263..f947f555fd46 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -55,7 +55,7 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
 }
 #endif  /* CONFIG_PCI */
 
-void __init
+static void __init
 mpc86xx_hpcn_init_irq(void)
 {
         struct mpic *mpic1;
@@ -162,7 +162,7 @@ mpc86xx_hpcn_setup_arch(void)
 }
 
 
-void
+static void
 mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
 {
         struct device_node *root;
@@ -190,13 +190,19 @@ static int __init mpc86xx_hpcn_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "mpc86xx"))
+        if (of_flat_dt_is_compatible(root, "fsl,mpc8641hpcn"))
                 return 1;       /* Looks good */
 
+        /* Be nice and don't give silent boot death.  Delete this in 2.6.27 */
+        if (of_flat_dt_is_compatible(root, "mpc86xx")) {
+                pr_warning("WARNING: your dts/dtb is old. You must update before the next kernel release\n");
+                return 1;
+        }
+
         return 0;
 }
 
-long __init
+static long __init
 mpc86xx_time_init(void)
 {
         unsigned int temp;
diff --git a/arch/powerpc/platforms/86xx/sbc8641d.c b/arch/powerpc/platforms/86xx/sbc8641d.c
new file mode 100644
index 000000000000..510a06ef0b55
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/sbc8641d.c
@@ -0,0 +1,164 @@
+/*
+ * SBC8641D board specific routines
+ *
+ * Copyright 2008 Wind River Systems Inc.
+ *
+ * By Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * Based largely on the 8641 HPCN support by Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc86xx.h>
+#include <asm/prom.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_pci.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+static void __init
+sbc8641_init_irq(void)
+{
+        struct mpic *mpic1;
+        struct device_node *np;
+        struct resource res;
+
+        /* Determine PIC address. */
+        np = of_find_node_by_type(NULL, "open-pic");
+        if (np == NULL)
+                return;
+        of_address_to_resource(np, 0, &res);
+
+        /* Alloc mpic structure and per isu has 16 INT entries. */
+        mpic1 = mpic_alloc(np, res.start,
+                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+                        0, 256, " MPIC     ");
+        of_node_put(np);
+        BUG_ON(mpic1 == NULL);
+
+        mpic_init(mpic1);
+}
+
+static void __init
+sbc8641_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+
+        if (ppc_md.progress)
+                ppc_md.progress("sbc8641_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie")
+                fsl_add_bridge(np, 0);
+#endif
+
+        printk("SBC8641 board from Wind River\n");
+
+#ifdef CONFIG_SMP
+        mpc86xx_smp_init();
+#endif
+}
+
+
+static void
+sbc8641_show_cpuinfo(struct seq_file *m)
+{
+        struct device_node *root;
+        uint memsize = total_memory;
+        const char *model = "";
+        uint svid = mfspr(SPRN_SVR);
+
+        seq_printf(m, "Vendor\t\t: Wind River Systems\n");
+
+        root = of_find_node_by_path("/");
+        if (root)
+                model = of_get_property(root, "model", NULL);
+        seq_printf(m, "Machine\t\t: %s\n", model);
+        of_node_put(root);
+
+        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+        seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init sbc8641_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "wind,sbc8641"))
+                return 1;       /* Looks good */
+
+        return 0;
+}
+
+static long __init
+mpc86xx_time_init(void)
+{
+        unsigned int temp;
+
+        /* Set the time base to zero */
+        mtspr(SPRN_TBWL, 0);
+        mtspr(SPRN_TBWU, 0);
+
+        temp = mfspr(SPRN_HID0);
+        temp |= HID0_TBEN;
+        mtspr(SPRN_HID0, temp);
+        asm volatile("isync");
+
+        return 0;
+}
+
+static __initdata struct of_device_id of_bus_ids[] = {
+        { .compatible = "simple-bus", },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+        return 0;
+}
+machine_device_initcall(sbc8641, declare_of_platform_devices);
+
+define_machine(sbc8641) {
+        .name                   = "SBC8641D",
+        .probe                  = sbc8641_probe,
+        .setup_arch             = sbc8641_setup_arch,
+        .init_IRQ               = sbc8641_init_irq,
+        .show_cpuinfo           = sbc8641_show_cpuinfo,
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .time_init              = mpc86xx_time_init,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+};
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 7fd224ca233d..6fc849e51e48 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -18,7 +18,6 @@ config MPC8XXFADS
 config MPC86XADS
         bool "MPC86XADS"
         select CPM1
-        select PPC_CPM_NEW_BINDING
         help
           MPC86x Application Development System by Freescale Semiconductor.
           The MPC86xADS is meant to serve as a platform for s/w and h/w
@@ -27,7 +26,6 @@ config MPC86XADS
 config MPC885ADS
         bool "MPC885ADS"
         select CPM1
-        select PPC_CPM_NEW_BINDING
         help
           Freescale Semiconductor MPC885 Application Development System (ADS).
           Also known as DUET.
@@ -37,7 +35,6 @@ config MPC885ADS
 config PPC_EP88XC
         bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
         select CPM1
-        select PPC_CPM_NEW_BINDING
         help
           This enables support for the Embedded Planet EP88xC board.
 
@@ -47,7 +44,6 @@ config PPC_EP88XC
 config PPC_ADDER875
         bool "Analogue & Micro Adder 875"
         select CPM1
-        select PPC_CPM_NEW_BINDING
         select REDBOOT
         help
           This enables support for the Analogue & Micro Adder 875
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index 184f998d1be2..0d9f75c74f8c 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -111,17 +111,12 @@ void __init mpc8xx_calibrate_decr(void)
 
         /* Processor frequency is MHz.
          */
-        ppc_tb_freq = 50000000;
-        if (!get_freq("bus-frequency", &ppc_tb_freq)) {
-                printk(KERN_ERR "WARNING: Estimating decrementer frequency "
-                                "(not found)\n");
-        }
-        ppc_tb_freq /= 16;
         ppc_proc_freq = 50000000;
         if (!get_freq("clock-frequency", &ppc_proc_freq))
                 printk(KERN_ERR "WARNING: Estimating processor frequency "
                                 "(not found)\n");
 
+        ppc_tb_freq = ppc_proc_freq / 16;
         printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
 
         /* Perform some more timer/timebase initialization.  This used
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index a578b966ecbc..f38c50b4ce56 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -290,13 +290,7 @@ config CPM2
 config PPC_CPM_NEW_BINDING
         bool
         depends on CPM1 || CPM2
-        help
-          Select this if your board has been converted to use the new
-          device tree bindings for CPM, and no longer needs the
-          ioport callbacks or the platform device glue code.
-
-          The fs_enet and cpm_uart drivers will be built as
-          of_platform devices.
+        default y
 
 config AXON_RAM
         tristate "Axon DDR2 memory device driver"
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 0c3face0ddbb..5fc7fac10e93 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -41,11 +41,13 @@ config 40x
         bool "AMCC 40x"
         select PPC_DCR_NATIVE
         select PPC_UDBG_16550
+        select 4xx_SOC
 
 config 44x
         bool "AMCC 44x"
         select PPC_DCR_NATIVE
         select PPC_UDBG_16550
+        select 4xx_SOC
 
 config E200
         bool "Freescale e200"
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index d75ccded7f10..45646b2b4af4 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -28,13 +28,13 @@
 #include <linux/notifier.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/lmb.h>
 
 #include <asm/prom.h>
 #include <asm/iommu.h>
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
 #include <asm/udbg.h>
-#include <asm/lmb.h>
 #include <asm/firmware.h>
 #include <asm/cell-regs.h>
 
@@ -316,7 +316,7 @@ static void cell_iommu_setup_stab(struct cbe_iommu *iommu,
         segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT;
 
         pr_debug("%s: iommu[%d]: segments: %lu\n",
-                        __FUNCTION__, iommu->nid, segments);
+                        __func__, iommu->nid, segments);
 
         /* set up the segment table */
         stab_size = segments * sizeof(unsigned long);
@@ -343,7 +343,7 @@ static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
                                 (1 << 12) / sizeof(unsigned long));
 
         ptab_size = segments * pages_per_segment * sizeof(unsigned long);
-        pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__,
+        pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__,
                         iommu->nid, ptab_size, get_order(ptab_size));
         page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
         BUG_ON(!page);
@@ -355,7 +355,7 @@ static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
         n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12;
 
         pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
-                        __FUNCTION__, iommu->nid, iommu->stab, ptab,
+                        __func__, iommu->nid, iommu->stab, ptab,
                         n_pte_pages);
 
         /* initialise the STEs */
@@ -394,7 +394,7 @@ static void cell_iommu_enable_hardware(struct cbe_iommu *iommu)
 
         if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
                 panic("%s: missing IOC register mappings for node %d\n",
-                      __FUNCTION__, iommu->nid);
+                      __func__, iommu->nid);
 
         iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
         iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c
index 0304589c0a80..8a3631ce912b 100644
--- a/arch/powerpc/platforms/cell/pervasive.c
+++ b/arch/powerpc/platforms/cell/pervasive.c
@@ -65,7 +65,7 @@ static void cbe_power_save(void)
                 break;
         default:
                 printk(KERN_WARNING "%s: unknown configuration\n",
-                        __FUNCTION__);
+                        __func__);
                 break;
         }
         mtspr(SPRN_TSC_CELL, thread_switch_control);
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index e43024c0392e..655704ad03cf 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -132,7 +132,7 @@ static int __init cbe_ptcal_enable_on_node(int nid, int order)
                                 (unsigned int)(addr >> 32),
                                 (unsigned int)(addr & 0xffffffff))) {
                 printk(KERN_ERR "%s: error enabling PTCAL on node %d!\n",
-                                __FUNCTION__, nid);
+                                __func__, nid);
                 goto out_free_pages;
         }
 
@@ -162,7 +162,7 @@ static int __init cbe_ptcal_enable(void)
         if (!size)
                 return -ENODEV;
 
-        pr_debug("%s: enabling PTCAL, size = 0x%x\n", __FUNCTION__, *size);
+        pr_debug("%s: enabling PTCAL, size = 0x%x\n", __func__, *size);
         order = get_order(*size);
         of_node_put(np);
 
@@ -180,7 +180,7 @@ static int __init cbe_ptcal_enable(void)
                 const u32 *nid = of_get_property(np, "node-id", NULL);
                 if (!nid) {
                         printk(KERN_ERR "%s: node %s is missing node-id?\n",
-                                        __FUNCTION__, np->full_name);
+                                        __func__, np->full_name);
                         continue;
                 }
                 cbe_ptcal_enable_on_node(*nid, order);
@@ -195,13 +195,13 @@ static int cbe_ptcal_disable(void)
         struct ptcal_area *area, *tmp;
         int ret = 0;
 
-        pr_debug("%s: disabling PTCAL\n", __FUNCTION__);
+        pr_debug("%s: disabling PTCAL\n", __func__);
 
         list_for_each_entry_safe(area, tmp, &ptcal_list, list) {
                 /* disable ptcal on this node */
                 if (rtas_call(ptcal_stop_tok, 1, 1, NULL, area->nid)) {
                         printk(KERN_ERR "%s: error disabling PTCAL "
-                                        "on node %d!\n", __FUNCTION__,
+                                        "on node %d!\n", __func__,
                                         area->nid);
                         ret = -EIO;
                         continue;
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index 712001f6b7da..6bab44b7716b 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -165,7 +165,7 @@ static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
         struct spu_slb slb;
         int psize;
 
-        pr_debug("%s\n", __FUNCTION__);
+        pr_debug("%s\n", __func__);
 
         slb.esid = (ea & ESID_MASK) | SLB_ESID_V;
 
@@ -215,7 +215,7 @@ static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
 static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
 {
-        pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);
+        pr_debug("%s, %lx, %lx\n", __func__, dsisr, ea);
 
         /* Handle kernel space hash faults immediately.
            User hash faults need to be deferred to process context. */
@@ -351,7 +351,7 @@ spu_irq_class_1(int irq, void *data)
                 __spu_trap_data_seg(spu, dar);
 
         spin_unlock(&spu->register_lock);
-        pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
+        pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,
                         dar, dsisr);
 
         if (stat & CLASS1_STORAGE_FAULT_INTR)
@@ -726,7 +726,7 @@ static int __init init_spu_base(void)
 
         if (ret < 0) {
                 printk(KERN_WARNING "%s: Error initializing spus\n",
-                        __FUNCTION__);
+                        __func__);
                 goto out_unregister_sysdev_class;
         }
 
diff --git a/arch/powerpc/platforms/cell/spu_callbacks.c b/arch/powerpc/platforms/cell/spu_callbacks.c
index dceb8b6a9382..19f6bfdbb933 100644
--- a/arch/powerpc/platforms/cell/spu_callbacks.c
+++ b/arch/powerpc/platforms/cell/spu_callbacks.c
@@ -54,7 +54,7 @@ long spu_sys_callback(struct spu_syscall_block *s)
         long (*syscall)(u64 a1, u64 a2, u64 a3, u64 a4, u64 a5, u64 a6);
 
         if (s->nr_ret >= ARRAY_SIZE(spu_syscall_table)) {
-                pr_debug("%s: invalid syscall #%ld", __FUNCTION__, s->nr_ret);
+                pr_debug("%s: invalid syscall #%ld", __func__, s->nr_ret);
                 return -ENOSYS;
         }
 
diff --git a/arch/powerpc/platforms/cell/spu_manage.c b/arch/powerpc/platforms/cell/spu_manage.c
index d351bdebf5f1..4c506c1463cd 100644
--- a/arch/powerpc/platforms/cell/spu_manage.c
+++ b/arch/powerpc/platforms/cell/spu_manage.c
@@ -92,7 +92,7 @@ static int __init spu_map_interrupts_old(struct spu *spu,
 
         tmp = of_get_property(np->parent->parent, "node-id", NULL);
         if (!tmp) {
-                printk(KERN_WARNING "%s: can't find node-id\n", __FUNCTION__);
+                printk(KERN_WARNING "%s: can't find node-id\n", __func__);
                 nid = spu->node;
         } else
                 nid = tmp[0];
@@ -296,7 +296,7 @@ static int __init of_enumerate_spus(int (*fn)(void *data))
                 ret = fn(node);
                 if (ret) {
                         printk(KERN_WARNING "%s: Error initializing %s\n",
-                                __FUNCTION__, node->name);
+                                __func__, node->name);
                         break;
                 }
                 n++;
@@ -327,7 +327,7 @@ static int __init of_create_spu(struct spu *spu, void *data)
                 if (!legacy_map) {
                         legacy_map = 1;
                         printk(KERN_WARNING "%s: Legacy device tree found, "
-                                "trying to map old style\n", __FUNCTION__);
+                                "trying to map old style\n", __func__);
                 }
                 ret = spu_map_device_old(spu);
                 if (ret) {
@@ -342,7 +342,7 @@ static int __init of_create_spu(struct spu *spu, void *data)
                 if (!legacy_irq) {
                         legacy_irq = 1;
                         printk(KERN_WARNING "%s: Legacy device tree found, "
-                                "trying old style irq\n", __FUNCTION__);
+                                "trying old style irq\n", __func__);
                 }
                 ret = spu_map_interrupts_old(spu, spe);
                 if (ret) {
diff --git a/arch/powerpc/platforms/cell/spufs/coredump.c b/arch/powerpc/platforms/cell/spufs/coredump.c
index 0c6a96b82b2d..b962c3ab470c 100644
--- a/arch/powerpc/platforms/cell/spufs/coredump.c
+++ b/arch/powerpc/platforms/cell/spufs/coredump.c
@@ -133,8 +133,6 @@ static struct spu_context *coredump_next_context(int *fd)
                 if (ctx->flags & SPU_CREATE_NOSCHED)
                         continue;
 
-                /* start searching the next fd next time we're called */
-                (*fd)++;
                 break;
         }
 
@@ -157,6 +155,9 @@ int spufs_coredump_extra_notes_size(void)
                         break;
 
                 size += rc;
+
+                /* start searching the next fd next time */
+                fd++;
         }
 
         return size;
@@ -239,6 +240,9 @@ int spufs_coredump_extra_notes_write(struct file *file, loff_t *foffset)
                 }
 
                 spu_release_saved(ctx);
+
+                /* start searching the next fd next time */
+                fd++;
         }
 
         return 0;
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index f7a7e8635fb6..08f44d1971ac 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -32,7 +32,6 @@
 #include <linux/marker.h>
 
 #include <asm/io.h>
-#include <asm/semaphore.h>
 #include <asm/spu.h>
 #include <asm/spu_info.h>
 #include <asm/uaccess.h>
@@ -1337,7 +1336,7 @@ static u64 spufs_signal1_type_get(struct spu_context *ctx)
         return ctx->ops->signal1_type_get(ctx);
 }
 DEFINE_SPUFS_ATTRIBUTE(spufs_signal1_type, spufs_signal1_type_get,
-                       spufs_signal1_type_set, "%llu", SPU_ATTR_ACQUIRE);
+                       spufs_signal1_type_set, "%llu\n", SPU_ATTR_ACQUIRE);
 
 
 static int spufs_signal2_type_set(void *data, u64 val)
@@ -1359,7 +1358,7 @@ static u64 spufs_signal2_type_get(struct spu_context *ctx)
         return ctx->ops->signal2_type_get(ctx);
 }
 DEFINE_SPUFS_ATTRIBUTE(spufs_signal2_type, spufs_signal2_type_get,
-                       spufs_signal2_type_set, "%llu", SPU_ATTR_ACQUIRE);
+                       spufs_signal2_type_set, "%llu\n", SPU_ATTR_ACQUIRE);
 
 #if SPUFS_MMAP_4K
 static unsigned long spufs_mss_mmap_nopfn(struct vm_area_struct *vma,
@@ -1556,7 +1555,7 @@ void spufs_mfc_callback(struct spu *spu)
 
         wake_up_all(&ctx->mfc_wq);
 
-        pr_debug("%s %s\n", __FUNCTION__, spu->name);
+        pr_debug("%s %s\n", __func__, spu->name);
         if (ctx->mfc_fasync) {
                 u32 free_elements, tagstatus;
                 unsigned int mask;
@@ -1790,7 +1789,7 @@ static unsigned int spufs_mfc_poll(struct file *file,poll_table *wait)
         if (tagstatus & ctx->tagwait)
                 mask |= POLLIN | POLLRDNORM;
 
-        pr_debug("%s: free %d tagstatus %d tagwait %d\n", __FUNCTION__,
+        pr_debug("%s: free %d tagstatus %d tagwait %d\n", __func__,
                 free_elements, tagstatus, ctx->tagwait);
 
         return mask;
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 6d1228c66c5e..0c32a05ab068 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -35,7 +35,6 @@
 #include <linux/parser.h>
 
 #include <asm/prom.h>
-#include <asm/semaphore.h>
 #include <asm/spu.h>
 #include <asm/spu_priv1.h>
 #include <asm/uaccess.h>
diff --git a/arch/powerpc/platforms/cell/spufs/run.c b/arch/powerpc/platforms/cell/spufs/run.c
index cac69e116776..96bf7c2b86fc 100644
--- a/arch/powerpc/platforms/cell/spufs/run.c
+++ b/arch/powerpc/platforms/cell/spufs/run.c
@@ -98,7 +98,7 @@ static int spu_setup_isolated(struct spu_context *ctx)
                         != MFC_CNTL_PURGE_DMA_COMPLETE) {
                 if (time_after(jiffies, timeout)) {
                         printk(KERN_ERR "%s: timeout flushing MFC DMA queue\n",
-                                        __FUNCTION__);
+                                        __func__);
                         ret = -EIO;
                         goto out;
                 }
@@ -124,7 +124,7 @@ static int spu_setup_isolated(struct spu_context *ctx)
                                 status_loading) {
                 if (time_after(jiffies, timeout)) {
                         printk(KERN_ERR "%s: timeout waiting for loader\n",
-                                        __FUNCTION__);
+                                        __func__);
                         ret = -EIO;
                         goto out_drop_priv;
                 }
@@ -134,7 +134,7 @@ static int spu_setup_isolated(struct spu_context *ctx)
         if (!(status & SPU_STATUS_RUNNING)) {
                 /* If isolated LOAD has failed: run SPU, we will get a stop-and
                  * signal later. */
-                pr_debug("%s: isolated LOAD failed\n", __FUNCTION__);
+                pr_debug("%s: isolated LOAD failed\n", __func__);
                 ctx->ops->runcntl_write(ctx, SPU_RUNCNTL_RUNNABLE);
                 ret = -EACCES;
                 goto out_drop_priv;
@@ -142,7 +142,7 @@ static int spu_setup_isolated(struct spu_context *ctx)
 
         if (!(status & SPU_STATUS_ISOLATED_STATE)) {
                 /* This isn't allowed by the CBEA, but check anyway */
-                pr_debug("%s: SPU fell out of isolated mode?\n", __FUNCTION__);
+                pr_debug("%s: SPU fell out of isolated mode?\n", __func__);
                 ctx->ops->runcntl_write(ctx, SPU_RUNCNTL_STOP);
                 ret = -EINVAL;
                 goto out_drop_priv;
@@ -282,7 +282,7 @@ static int spu_handle_restartsys(struct spu_context *ctx, long *spu_ret,
                 break;
         default:
                 printk(KERN_WARNING "%s: unexpected return code %ld\n",
-                        __FUNCTION__, *spu_ret);
+                        __func__, *spu_ret);
                 ret = 0;
         }
         return ret;
@@ -323,6 +323,10 @@ static int spu_process_callback(struct spu_context *ctx)
                         return -EINTR;
         }
 
+        /* need to re-get the ls, as it may have changed when we released the
+         * spu */
+        ls = (void __iomem *)ctx->ops->get_ls(ctx);
+
         /* write result, jump over indirect pointer */
         memcpy_toio(ls + ls_pointer, &spu_ret, sizeof(spu_ret));
         ctx->ops->npc_write(ctx, npc);
diff --git a/arch/powerpc/platforms/cell/spufs/switch.c b/arch/powerpc/platforms/cell/spufs/switch.c
index e9dc7a55d1b9..d2a1249d36dd 100644
--- a/arch/powerpc/platforms/cell/spufs/switch.c
+++ b/arch/powerpc/platforms/cell/spufs/switch.c
@@ -1815,6 +1815,7 @@ static void save_csa(struct spu_state *prev, struct spu *spu)
         save_mfc_csr_ato(prev, spu);    /* Step 24. */
         save_mfc_tclass_id(prev, spu);  /* Step 25. */
         set_mfc_tclass_id(prev, spu);   /* Step 26. */
+        save_mfc_cmd(prev, spu);        /* Step 26a - moved from 44. */
         purge_mfc_queue(prev, spu);     /* Step 27. */
         wait_purge_complete(prev, spu); /* Step 28. */
         setup_mfc_sr1(prev, spu);       /* Step 30. */
@@ -1831,7 +1832,6 @@ static void save_csa(struct spu_state *prev, struct spu *spu)
         save_ppuint_mb(prev, spu);      /* Step 41. */
         save_ch_part1(prev, spu);       /* Step 42. */
         save_spu_mb(prev, spu);         /* Step 43. */
-        save_mfc_cmd(prev, spu);        /* Step 44. */
         reset_ch(prev, spu);            /* Step 45. */
 }
 
diff --git a/arch/powerpc/platforms/celleb/beat.c b/arch/powerpc/platforms/celleb/beat.c
index 93ebb7d85120..b64b171f245b 100644
--- a/arch/powerpc/platforms/celleb/beat.c
+++ b/arch/powerpc/platforms/celleb/beat.c
@@ -48,6 +48,7 @@ void beat_power_off(void)
 }
 
 u64 beat_halt_code = 0x1000000000000000UL;
+EXPORT_SYMBOL(beat_halt_code);
 
 void beat_halt(void)
 {
@@ -94,9 +95,8 @@ ssize_t beat_nvram_read(char *buf, size_t count, loff_t *index)
                 len = count;
                 if (len > BEAT_NVRW_CNT)
                         len = BEAT_NVRW_CNT;
-                if (beat_eeprom_read(i, len, p)) {
+                if (beat_eeprom_read(i, len, p))
                         return -EIO;
-                }
 
                 p += len;
                 i += len;
@@ -121,9 +121,8 @@ ssize_t beat_nvram_write(char *buf, size_t count, loff_t *index)
                 len = count;
                 if (len > BEAT_NVRW_CNT)
                         len = BEAT_NVRW_CNT;
-                if (beat_eeprom_write(i, len, p)) {
+                if (beat_eeprom_write(i, len, p))
                         return -EIO;
-                }
 
                 p += len;
                 i += len;
@@ -149,13 +148,14 @@ int64_t beat_get_term_char(u64 vterm, u64 *len, u64 *t1, u64 *t2)
         u64 db[2];
         s64 ret;
 
-        ret = beat_get_characters_from_console(vterm, len, (u8*)db);
+        ret = beat_get_characters_from_console(vterm, len, (u8 *)db);
         if (ret == 0) {
                 *t1 = db[0];
                 *t2 = db[1];
         }
         return ret;
 }
+EXPORT_SYMBOL(beat_get_term_char);
 
 int64_t beat_put_term_char(u64 vterm, u64 len, u64 t1, u64 t2)
 {
@@ -163,8 +163,9 @@ int64_t beat_put_term_char(u64 vterm, u64 len, u64 t1, u64 t2)
 
         db[0] = t1;
         db[1] = t2;
-        return beat_put_characters_to_console(vterm, len, (u8*)db);
+        return beat_put_characters_to_console(vterm, len, (u8 *)db);
 }
+EXPORT_SYMBOL(beat_put_term_char);
 
 void beat_power_save(void)
 {
@@ -261,7 +262,3 @@ static int __init beat_event_init(void)
 }
 
 device_initcall(beat_event_init);
-
-EXPORT_SYMBOL(beat_get_term_char);
-EXPORT_SYMBOL(beat_put_term_char);
-EXPORT_SYMBOL(beat_halt_code);
diff --git a/arch/powerpc/platforms/celleb/beat.h b/arch/powerpc/platforms/celleb/beat.h
index ac82ac35b991..32c8efcedc80 100644
--- a/arch/powerpc/platforms/celleb/beat.h
+++ b/arch/powerpc/platforms/celleb/beat.h
@@ -21,8 +21,8 @@
 #ifndef _CELLEB_BEAT_H
 #define _CELLEB_BEAT_H
 
-int64_t beat_get_term_char(uint64_t,uint64_t*,uint64_t*,uint64_t*);
-int64_t beat_put_term_char(uint64_t,uint64_t,uint64_t,uint64_t);
+int64_t beat_get_term_char(uint64_t, uint64_t *, uint64_t *, uint64_t *);
+int64_t beat_put_term_char(uint64_t, uint64_t, uint64_t, uint64_t);
 int64_t beat_repository_encode(int, const char *, uint64_t[4]);
 void beat_restart(char *);
 void beat_power_off(void);
diff --git a/arch/powerpc/platforms/celleb/beat_wrapper.h b/arch/powerpc/platforms/celleb/beat_wrapper.h
index cbc1487df7de..b47dfda48d06 100644
--- a/arch/powerpc/platforms/celleb/beat_wrapper.h
+++ b/arch/powerpc/platforms/celleb/beat_wrapper.h
@@ -197,7 +197,8 @@ static inline s64 beat_put_characters_to_console(u64 termno, u64 len,
         u64 b[2];
 
         memcpy(b, buffer, len);
-        return beat_hcall_norets(HV_put_characters_to_console, termno, len,                                      b[0], b[1]);
+        return beat_hcall_norets(HV_put_characters_to_console, termno, len,
+                b[0], b[1]);
 }
 
 static inline s64 beat_get_spe_privileged_state_1_registers(
diff --git a/arch/powerpc/platforms/celleb/htab.c b/arch/powerpc/platforms/celleb/htab.c
index fbf27c74ebda..81467ff055c8 100644
--- a/arch/powerpc/platforms/celleb/htab.c
+++ b/arch/powerpc/platforms/celleb/htab.c
@@ -35,9 +35,9 @@
 #include "beat_wrapper.h"
 
 #ifdef DEBUG_LOW
-#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while(0)
+#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while (0)
 #else
-#define DBG_LOW(fmt...) do { } while(0)
+#define DBG_LOW(fmt...) do { } while (0)
 #endif
 
 static DEFINE_SPINLOCK(beat_htab_lock);
@@ -116,7 +116,8 @@ static long beat_lpar_hpte_insert(unsigned long hpte_group,
                 hpte_r &= ~_PAGE_COHERENT;
 
         spin_lock(&beat_htab_lock);
-        if ((lpar_rc = beat_read_mask(hpte_group)) == 0) {
+        lpar_rc = beat_read_mask(hpte_group);
+        if (lpar_rc == 0) {
                 if (!(vflags & HPTE_V_BOLTED))
                         DBG_LOW(" full\n");
                 spin_unlock(&beat_htab_lock);
diff --git a/arch/powerpc/platforms/celleb/interrupt.c b/arch/powerpc/platforms/celleb/interrupt.c
index c7c68ca70c82..69562a867876 100644
--- a/arch/powerpc/platforms/celleb/interrupt.c
+++ b/arch/powerpc/platforms/celleb/interrupt.c
@@ -34,7 +34,7 @@ static DEFINE_SPINLOCK(beatic_irq_mask_lock);
 static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64];
 static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64];
 
-static struct irq_host *beatic_host = NULL;
+static struct irq_host *beatic_host;
 
 /*
  * In this implementation, "virq" == "IRQ plug number",
@@ -49,13 +49,13 @@ static inline void beatic_update_irq_mask(unsigned int irq_plug)
 
         off = (irq_plug / 256) * 4;
         masks[0] = beatic_irq_mask_enable[off + 0]
-                   & beatic_irq_mask_ack[off + 0];
+                & beatic_irq_mask_ack[off + 0];
         masks[1] = beatic_irq_mask_enable[off + 1]
-                   & beatic_irq_mask_ack[off + 1];
+                & beatic_irq_mask_ack[off + 1];
         masks[2] = beatic_irq_mask_enable[off + 2]
-                   & beatic_irq_mask_ack[off + 2];
+                & beatic_irq_mask_ack[off + 2];
         masks[3] = beatic_irq_mask_enable[off + 3]
-                   & beatic_irq_mask_ack[off + 3];
+                & beatic_irq_mask_ack[off + 3];
         if (beat_set_interrupt_mask(irq_plug&~255UL,
                 masks[0], masks[1], masks[2], masks[3]) != 0)
                 panic("Failed to set mask IRQ!");
@@ -96,7 +96,8 @@ static void beatic_end_irq(unsigned int irq_plug)
         s64 err;
         unsigned long flags;
 
-        if ((err = beat_downcount_of_interrupt(irq_plug)) != 0) {
+        err = beat_downcount_of_interrupt(irq_plug);
+        if (err != 0) {
                 if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */
                         panic("Failed to downcount IRQ! Error = %16lx", err);
 
@@ -138,7 +139,8 @@ static int beatic_pic_host_map(struct irq_host *h, unsigned int virq,
         struct irq_desc *desc = get_irq_desc(virq);
         int64_t err;
 
-        if ((err = beat_construct_and_connect_irq_plug(virq, hw)) < 0)
+        err = beat_construct_and_connect_irq_plug(virq, hw);
+        if (err < 0)
                 return -EIO;
 
         desc->status |= IRQ_LEVEL;
@@ -202,22 +204,22 @@ static inline unsigned int beatic_get_irq_plug(void)
                 beat_detect_pending_interrupts(i, pending);
                 __asm__ ("cntlzd %0,%1":"=r"(ub):
                         "r"(pending[0] & beatic_irq_mask_enable[i/64+0]
-                                       & beatic_irq_mask_ack[i/64+0]));
+                                       & beatic_irq_mask_ack[i/64+0]));
                 if (ub != 64)
                         return i + ub + 0;
                 __asm__ ("cntlzd %0,%1":"=r"(ub):
                         "r"(pending[1] & beatic_irq_mask_enable[i/64+1]
-                                       & beatic_irq_mask_ack[i/64+1]));
+                                       & beatic_irq_mask_ack[i/64+1]));
                 if (ub != 64)
                         return i + ub + 64;
                 __asm__ ("cntlzd %0,%1":"=r"(ub):
                         "r"(pending[2] & beatic_irq_mask_enable[i/64+2]
-                                       & beatic_irq_mask_ack[i/64+2]));
+                                       & beatic_irq_mask_ack[i/64+2]));
                 if (ub != 64)
                         return i + ub + 128;
                 __asm__ ("cntlzd %0,%1":"=r"(ub):
                         "r"(pending[3] & beatic_irq_mask_enable[i/64+3]
-                                       & beatic_irq_mask_ack[i/64+3]));
+                                       & beatic_irq_mask_ack[i/64+3]));
                 if (ub != 64)
                         return i + ub + 192;
         }
@@ -250,7 +252,7 @@ void __init beatic_init_IRQ(void)
 
         /* Allocate an irq host */
         beatic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_NOMAP, 0,
-                                         &beatic_pic_host_ops,
+                                     &beatic_pic_host_ops,
                                          0);
         BUG_ON(beatic_host == NULL);
         irq_set_default_host(beatic_host);
diff --git a/arch/powerpc/platforms/celleb/scc_epci.c b/arch/powerpc/platforms/celleb/scc_epci.c
index a3c7cfbcb323..a999b393f6f6 100644
--- a/arch/powerpc/platforms/celleb/scc_epci.c
+++ b/arch/powerpc/platforms/celleb/scc_epci.c
@@ -161,9 +161,9 @@ static PCI_IO_ADDR celleb_epci_make_config_addr(
         if (bus != hose->bus)
                 addr = celleb_epci_get_epci_cfg(hose) +
                        (((bus->number & 0xff) << 16)
-                        | ((devfn & 0xff) << 8)
-                        | (where & 0xff)
-                        | 0x01000000);
+                        | ((devfn & 0xff) << 8)
+                        | (where & 0xff)
+                        | 0x01000000);
         else
                 addr = celleb_epci_get_epci_cfg(hose) +
                        (((devfn & 0xff) << 8) | (where & 0xff));
@@ -174,7 +174,7 @@ static PCI_IO_ADDR celleb_epci_make_config_addr(
 }
 
 static int celleb_epci_read_config(struct pci_bus *bus,
-                        unsigned int devfn, int where, int size, u32 * val)
+                        unsigned int devfn, int where, int size, u32 *val)
 {
         PCI_IO_ADDR epci_base;
         PCI_IO_ADDR addr;
diff --git a/arch/powerpc/platforms/celleb/scc_sio.c b/arch/powerpc/platforms/celleb/scc_sio.c
index 610008211ca1..3a16c5b3c464 100644
--- a/arch/powerpc/platforms/celleb/scc_sio.c
+++ b/arch/powerpc/platforms/celleb/scc_sio.c
@@ -28,7 +28,7 @@
 
 /* sio irq0=0xb00010022 irq0=0xb00010023 irq2=0xb00010024
     mmio=0xfff000-0x1000,0xff2000-0x1000 */
-static int txx9_serial_bitmap __initdata = 0;
+static int txx9_serial_bitmap __initdata;
 
 static struct {
         uint32_t offset;
@@ -84,7 +84,7 @@ static int __init txx9_serial_config(char *ptr)
         int     i;
 
         for (;;) {
-                switch(get_option(&ptr, &i)) {
+                switch (get_option(&ptr, &i)) {
                 default:
                         return 0;
                 case 2:
diff --git a/arch/powerpc/platforms/celleb/spu_priv1.c b/arch/powerpc/platforms/celleb/spu_priv1.c
index 2bf6700f747a..bcc17f7fe8ad 100644
--- a/arch/powerpc/platforms/celleb/spu_priv1.c
+++ b/arch/powerpc/platforms/celleb/spu_priv1.c
@@ -183,8 +183,7 @@ static u64 resource_allocation_enable_get(struct spu *spu)
         return enable;
 }
 
-const struct spu_priv1_ops spu_priv1_beat_ops =
-{
+const struct spu_priv1_ops spu_priv1_beat_ops = {
         .int_mask_and = int_mask_and,
         .int_mask_or = int_mask_or,
         .int_mask_set = int_mask_set,
diff --git a/arch/powerpc/platforms/celleb/udbg_beat.c b/arch/powerpc/platforms/celleb/udbg_beat.c
index d888c4674c62..6b418f6b6175 100644
--- a/arch/powerpc/platforms/celleb/udbg_beat.c
+++ b/arch/powerpc/platforms/celleb/udbg_beat.c
@@ -54,7 +54,8 @@ static int udbg_getc_poll_beat(void)
         if (inbuflen == 0) {
                 /* get some more chars. */
                 inbuflen = 0;
-                rc = beat_get_term_char(celleb_vtermno, &inbuflen, inbuf+0, inbuf+1);
+                rc = beat_get_term_char(celleb_vtermno, &inbuflen,
+                                        inbuf+0, inbuf+1);
                 if (rc != 0)
                         inbuflen = 0;   /* otherwise inbuflen is garbage */
         }
@@ -78,7 +79,7 @@ static int udbg_getc_beat(void)
                 if (ch == -1) {
                         /* This shouldn't be needed...but... */
                         volatile unsigned long delay;
-                        for (delay=0; delay < 2000000; delay++)
+                        for (delay = 0; delay < 2000000; delay++)
                                 ;
                 } else {
                         return ch;
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index d4f8bf581e3a..84e2d78b9a62 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -117,11 +117,11 @@ static void __init mpc7448_hpc2_init_IRQ(void)
         }
 
         if (mpic_paddr == 0) {
-                printk("%s: No tsi108 PIC found !\n", __FUNCTION__);
+                printk("%s: No tsi108 PIC found !\n", __func__);
                 return;
         }
 
-        DBG("%s: tsi108 pic phys_addr = 0x%x\n", __FUNCTION__,
+        DBG("%s: tsi108 pic phys_addr = 0x%x\n", __func__,
             (u32) mpic_paddr);
 
         mpic = mpic_alloc(tsi_pic, mpic_paddr,
@@ -140,17 +140,17 @@ static void __init mpc7448_hpc2_init_IRQ(void)
 #ifdef CONFIG_PCI
         tsi_pci = of_find_node_by_type(NULL, "pci");
         if (tsi_pci == NULL) {
-                printk("%s: No tsi108 pci node found !\n", __FUNCTION__);
+                printk("%s: No tsi108 pci node found !\n", __func__);
                 return;
         }
         cascade_node = of_find_node_by_type(NULL, "pic-router");
         if (cascade_node == NULL) {
-                printk("%s: No tsi108 pci cascade node found !\n", __FUNCTION__);
+                printk("%s: No tsi108 pci cascade node found !\n", __func__);
                 return;
         }
 
         cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
-        DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __FUNCTION__,
+        DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__,
             (u32) cascade_pci_irq);
         tsi108_pci_int_init(cascade_node);
         set_irq_data(cascade_pci_irq, mpic);
diff --git a/arch/powerpc/platforms/embedded6xx/prpmc2800.c b/arch/powerpc/platforms/embedded6xx/prpmc2800.c
index 653a5eb91c90..5a19b9a1457c 100644
--- a/arch/powerpc/platforms/embedded6xx/prpmc2800.c
+++ b/arch/powerpc/platforms/embedded6xx/prpmc2800.c
@@ -49,13 +49,13 @@ static void __init prpmc2800_setup_arch(void)
          * ioremap mpp and gpp registers in case they are later
          * needed by prpmc2800_reset_board().
          */
-        np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-mpp");
+        np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp");
         reg = of_get_property(np, "reg", NULL);
         paddr = of_translate_address(np, reg);
         of_node_put(np);
         mv64x60_mpp_reg_base = ioremap(paddr, reg[1]);
 
-        np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp");
+        np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
         reg = of_get_property(np, "reg", NULL);
         paddr = of_translate_address(np, reg);
         of_node_put(np);
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 5381038f0881..c775cd4b3d6e 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -38,11 +38,19 @@
 
         .globl system_reset_iSeries
 system_reset_iSeries:
-        mfspr   r13,SPRN_SPRG3          /* Get paca address */
+        mfspr   r13,SPRN_SPRG3          /* Get alpaca address */
+        LOAD_REG_IMMEDIATE(r23, alpaca)
+        li      r0,ALPACA_SIZE
+        sub     r23,r13,r23
+        divdu   r23,r23,r0              /* r23 has cpu number */
+        LOAD_REG_IMMEDIATE(r13, paca)
+        mulli   r0,r23,PACA_SIZE
+        add     r13,r13,r0
+        mtspr   SPRN_SPRG3,r13          /* Save it away for the future */
         mfmsr   r24
         ori     r24,r24,MSR_RI
         mtmsrd  r24                     /* RI on */
-        lhz     r24,PACAPACAINDEX(r13)  /* Get processor # */
+        mr      r24,r23
         cmpwi   0,r24,0                 /* Are we processor 0? */
         bne     1f
         b       .__start_initialization_iSeries /* Start up the first processor */
diff --git a/arch/powerpc/platforms/iseries/ipl_parms.h b/arch/powerpc/platforms/iseries/ipl_parms.h
index 77c135ddbf1b..83e4ca42fc57 100644
--- a/arch/powerpc/platforms/iseries/ipl_parms.h
+++ b/arch/powerpc/platforms/iseries/ipl_parms.h
@@ -65,6 +65,4 @@ struct ItIplParmsReal {
         u64     xRsvd13;                // Reserved                     x38-x3F
 };
 
-extern struct ItIplParmsReal    xItIplParmsReal;
-
 #endif /* _ISERIES_IPL_PARMS_H */
diff --git a/arch/powerpc/platforms/iseries/lpardata.c b/arch/powerpc/platforms/iseries/lpardata.c
index 8162049bb04d..98bd2d37038a 100644
--- a/arch/powerpc/platforms/iseries/lpardata.c
+++ b/arch/powerpc/platforms/iseries/lpardata.c
@@ -14,10 +14,10 @@
 #include <asm/ptrace.h>
 #include <asm/abs_addr.h>
 #include <asm/lppaca.h>
-#include <asm/iseries/it_lp_reg_save.h>
 #include <asm/paca.h>
 #include <asm/iseries/lpar_map.h>
 #include <asm/iseries/it_lp_queue.h>
+#include <asm/iseries/alpaca.h>
 
 #include "naca.h"
 #include "vpd_areas.h"
@@ -31,7 +31,7 @@
 /* The HvReleaseData is the root of the information shared between
  * the hypervisor and Linux.
  */
-struct HvReleaseData hvReleaseData = {
+const struct HvReleaseData hvReleaseData = {
         .xDesc = 0xc8a5d9c4,    /* "HvRD" ebcdic */
         .xSize = sizeof(struct HvReleaseData),
         .xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
@@ -61,6 +61,63 @@ struct naca_struct naca = {
         .xRamDiskSize = 0,
 };
 
+struct ItLpRegSave {
+        u32     xDesc;          // Eye catcher  "LpRS" ebcdic   000-003
+        u16     xSize;          // Size of this class           004-005
+        u8      xInUse;         // Area is live                 006-007
+        u8      xRsvd1[9];      // Reserved                     007-00F
+
+        u8      xFixedRegSave[352]; // Fixed Register Save Area 010-16F
+        u32     xCTRL;          // Control Register             170-173
+        u32     xDEC;           // Decrementer                  174-177
+        u32     xFPSCR;         // FP Status and Control Reg    178-17B
+        u32     xPVR;           // Processor Version Number     17C-17F
+
+        u64     xMMCR0;         // Monitor Mode Control Reg 0   180-187
+        u32     xPMC1;          // Perf Monitor Counter 1       188-18B
+        u32     xPMC2;          // Perf Monitor Counter 2       18C-18F
+        u32     xPMC3;          // Perf Monitor Counter 3       190-193
+        u32     xPMC4;          // Perf Monitor Counter 4       194-197
+        u32     xPIR;           // Processor ID Reg             198-19B
+
+        u32     xMMCR1;         // Monitor Mode Control Reg 1   19C-19F
+        u32     xMMCRA;         // Monitor Mode Control Reg A   1A0-1A3
+        u32     xPMC5;          // Perf Monitor Counter 5       1A4-1A7
+        u32     xPMC6;          // Perf Monitor Counter 6       1A8-1AB
+        u32     xPMC7;          // Perf Monitor Counter 7       1AC-1AF
+        u32     xPMC8;          // Perf Monitor Counter 8       1B0-1B3
+        u32     xTSC;           // Thread Switch Control        1B4-1B7
+        u32     xTST;           // Thread Switch Timeout        1B8-1BB
+        u32     xRsvd;          // Reserved                     1BC-1BF
+
+        u64     xACCR;          // Address Compare Control Reg  1C0-1C7
+        u64     xIMR;           // Instruction Match Register   1C8-1CF
+        u64     xSDR1;          // Storage Description Reg 1    1D0-1D7
+        u64     xSPRG0;         // Special Purpose Reg General0 1D8-1DF
+        u64     xSPRG1;         // Special Purpose Reg General1 1E0-1E7
+        u64     xSPRG2;         // Special Purpose Reg General2 1E8-1EF
+        u64     xSPRG3;         // Special Purpose Reg General3 1F0-1F7
+        u64     xTB;            // Time Base Register           1F8-1FF
+
+        u64     xFPR[32];       // Floating Point Registers     200-2FF
+
+        u64     xMSR;           // Machine State Register       300-307
+        u64     xNIA;           // Next Instruction Address     308-30F
+
+        u64     xDABR;          // Data Address Breakpoint Reg  310-317
+        u64     xIABR;          // Inst Address Breakpoint Reg  318-31F
+
+        u64     xHID0;          // HW Implementation Dependent0 320-327
+
+        u64     xHID4;          // HW Implementation Dependent4 328-32F
+        u64     xSCOMd;         // SCON Data Reg (SPRG4)        330-337
+        u64     xSCOMc;         // SCON Command Reg (SPRG5)     338-33F
+        u64     xSDAR;          // Sample Data Address Register 340-347
+        u64     xSIAR;          // Sample Inst Address Register 348-34F
+
+        u8      xRsvd3[176];    // Reserved                     350-3FF
+};
+
 extern void system_reset_iSeries(void);
 extern void machine_check_iSeries(void);
 extern void data_access_iSeries(void);
@@ -129,7 +186,7 @@ struct ItLpNaca itLpNaca = {
 };
 
 /* May be filled in by the hypervisor so cannot end up in the BSS */
-struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
+static struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
 
 /* May be filled in by the hypervisor so cannot end up in the BSS */
 struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
@@ -152,13 +209,54 @@ u64    xMsVpd[3400] __attribute__((__section__(".data")));
 
 /* Space for Recovery Log Buffer */
 /* May be filled in by the hypervisor so cannot end up in the BSS */
-u64    xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
+static u64    xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
 
-struct SpCommArea xSpCommArea = {
+static const struct SpCommArea xSpCommArea = {
         .xDesc = 0xE2D7C3C2,
         .xFormat = 1,
 };
 
+static const struct ItLpRegSave iseries_reg_save[] = {
+        [0 ... (NR_CPUS-1)] = {
+                .xDesc = 0xd397d9e2,    /* "LpRS" */
+                .xSize = sizeof(struct ItLpRegSave),
+        },
+};
+
+#define ALPACA_INIT(number)                                             \
+{                                                                       \
+        .lppaca_ptr = &lppaca[number],                                  \
+        .reg_save_ptr = &iseries_reg_save[number],                      \
+}
+
+const struct alpaca alpaca[] = {
+        ALPACA_INIT( 0),
+#if NR_CPUS > 1
+        ALPACA_INIT( 1), ALPACA_INIT( 2), ALPACA_INIT( 3),
+#if NR_CPUS > 4
+        ALPACA_INIT( 4), ALPACA_INIT( 5), ALPACA_INIT( 6), ALPACA_INIT( 7),
+#if NR_CPUS > 8
+        ALPACA_INIT( 8), ALPACA_INIT( 9), ALPACA_INIT(10), ALPACA_INIT(11),
+        ALPACA_INIT(12), ALPACA_INIT(13), ALPACA_INIT(14), ALPACA_INIT(15),
+        ALPACA_INIT(16), ALPACA_INIT(17), ALPACA_INIT(18), ALPACA_INIT(19),
+        ALPACA_INIT(20), ALPACA_INIT(21), ALPACA_INIT(22), ALPACA_INIT(23),
+        ALPACA_INIT(24), ALPACA_INIT(25), ALPACA_INIT(26), ALPACA_INIT(27),
+        ALPACA_INIT(28), ALPACA_INIT(29), ALPACA_INIT(30), ALPACA_INIT(31),
+#if NR_CPUS > 32
+        ALPACA_INIT(32), ALPACA_INIT(33), ALPACA_INIT(34), ALPACA_INIT(35),
+        ALPACA_INIT(36), ALPACA_INIT(37), ALPACA_INIT(38), ALPACA_INIT(39),
+        ALPACA_INIT(40), ALPACA_INIT(41), ALPACA_INIT(42), ALPACA_INIT(43),
+        ALPACA_INIT(44), ALPACA_INIT(45), ALPACA_INIT(46), ALPACA_INIT(47),
+        ALPACA_INIT(48), ALPACA_INIT(49), ALPACA_INIT(50), ALPACA_INIT(51),
+        ALPACA_INIT(52), ALPACA_INIT(53), ALPACA_INIT(54), ALPACA_INIT(55),
+        ALPACA_INIT(56), ALPACA_INIT(57), ALPACA_INIT(58), ALPACA_INIT(59),
+        ALPACA_INIT(60), ALPACA_INIT(61), ALPACA_INIT(62), ALPACA_INIT(63),
+#endif
+#endif
+#endif
+#endif
+};
+
 /* The LparMap data is now located at offset 0x6000 in head.S
  * It was put there so that the HvReleaseData could address it
  * with a 32-bit offset as required by the iSeries hypervisor
@@ -167,7 +265,7 @@ struct SpCommArea xSpCommArea = {
  * the Naca via the HvReleaseData area.  The HvReleaseData has the
  * offset into the Naca of the pointer to the ItVpdAreas.
  */
-struct ItVpdAreas itVpdAreas = {
+const struct ItVpdAreas itVpdAreas = {
         .xSlicDesc = 0xc9a3e5c1,                /* "ItVA" */
         .xSlicSize = sizeof(struct ItVpdAreas),
         .xSlicVpdEntries = ItVpdMaxEntries,     /* # VPD array entries */
@@ -185,7 +283,7 @@ struct ItVpdAreas itVpdAreas = {
         .xSlicVpdLens = {                       /* VPD lengths */
                 0,0,0,                  /*  0 - 2 */
                 sizeof(xItExtVpdPanel), /*       3 Extended VPD   */
-                sizeof(struct paca_struct),     /*       4 length of Paca  */
+                sizeof(struct alpaca),  /*       4 length of (fake) Paca  */
                 0,                      /*       5 */
                 sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
                 26992,                  /*       7 length of MS VPD */
@@ -203,7 +301,7 @@ struct ItVpdAreas itVpdAreas = {
         .xSlicVpdAdrs = {                       /* VPD addresses */
                 0,0,0,                  /*       0 -  2 */
                 &xItExtVpdPanel,        /*       3 Extended VPD */
-                &paca[0],               /*       4 first Paca */
+                &alpaca[0],             /*       4 first (fake) Paca */
                 0,                      /*       5 */
                 &xItIplParmsReal,       /*       6 IPL parms */
                 &xMsVpd,                /*       7 MS Vpd */
@@ -219,10 +317,3 @@ struct ItVpdAreas itVpdAreas = {
                 0,0
         }
 };
-
-struct ItLpRegSave iseries_reg_save[] = {
-        [0 ... (NR_CPUS-1)] = {
-                .xDesc = 0xd397d9e2,    /* "LpRS" */
-                .xSize = sizeof(struct ItLpRegSave),
-        },
-};
diff --git a/arch/powerpc/platforms/iseries/naca.h b/arch/powerpc/platforms/iseries/naca.h
index ab2372eb8d2e..f01708e12862 100644
--- a/arch/powerpc/platforms/iseries/naca.h
+++ b/arch/powerpc/platforms/iseries/naca.h
@@ -14,7 +14,7 @@
 
 struct naca_struct {
         /* Kernel only data - undefined for user space */
-        void *xItVpdAreas;              /* VPD Data                  0x00 */
+        const void *xItVpdAreas;        /* VPD Data                  0x00 */
         void *xRamDisk;                 /* iSeries ramdisk           0x08 */
         u64   xRamDiskSize;             /* In pages                  0x10 */
 };
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c
index cc562e4c2f32..02a634faedbe 100644
--- a/arch/powerpc/platforms/iseries/pci.c
+++ b/arch/powerpc/platforms/iseries/pci.c
@@ -23,6 +23,7 @@
 
 #undef DEBUG
 
+#include <linux/jiffies.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/string.h>
@@ -586,7 +587,7 @@ static inline struct device_node *xlate_iomm_address(
                 static unsigned long last_jiffies;
                 static int num_printed;
 
-                if ((jiffies - last_jiffies) > 60 * HZ) {
+                if (time_after(jiffies, last_jiffies + 60 * HZ)) {
                         last_jiffies = jiffies;
                         num_printed = 0;
                 }
diff --git a/arch/powerpc/platforms/iseries/release_data.h b/arch/powerpc/platforms/iseries/release_data.h
index 66189fd2e32d..6ad7d843e8fc 100644
--- a/arch/powerpc/platforms/iseries/release_data.h
+++ b/arch/powerpc/platforms/iseries/release_data.h
@@ -58,6 +58,6 @@ struct HvReleaseData {
         char    xRsvd3[20];     /* Reserved                     x2C-x3F */
 };
 
-extern struct HvReleaseData     hvReleaseData;
+extern const struct HvReleaseData       hvReleaseData;
 
 #endif /* _ISERIES_RELEASE_DATA_H */
diff --git a/arch/powerpc/platforms/iseries/spcomm_area.h b/arch/powerpc/platforms/iseries/spcomm_area.h
index 6e3b685115c9..598b7c14573a 100644
--- a/arch/powerpc/platforms/iseries/spcomm_area.h
+++ b/arch/powerpc/platforms/iseries/spcomm_area.h
@@ -31,6 +31,4 @@ struct SpCommArea {
         u8      xRsvd2[80];             // Reserved                             030-07F
 };
 
-extern struct SpCommArea xSpCommArea;
-
 #endif /* _ISERIES_SPCOMM_AREA_H */
diff --git a/arch/powerpc/platforms/iseries/vpd_areas.h b/arch/powerpc/platforms/iseries/vpd_areas.h
index 601e6dd860ed..feb001f3a5fe 100644
--- a/arch/powerpc/platforms/iseries/vpd_areas.h
+++ b/arch/powerpc/platforms/iseries/vpd_areas.h
@@ -80,9 +80,9 @@ struct ItVpdAreas {
         u32     xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths   080-0A7
         u32     xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens    0A8-0CF
         u32     xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths   0D0-12F
-        void    *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers  130-1EF
+        const void *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers 130-1EF
 };
 
-extern struct ItVpdAreas        itVpdAreas;
+extern const struct ItVpdAreas  itVpdAreas;
 
 #endif /* _ISERIES_VPD_AREAS_H */
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index 3ffa0ac170ee..301855263b81 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -592,50 +592,3 @@ int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
         }
         return irq;
 }
-
-/* XXX: To remove once all firmwares are ok */
-static void fixup_maple_ide(struct pci_dev* dev)
-{
-        if (!machine_is(maple))
-                return;
-
-#if 0 /* Enable this to enable IDE port 0 */
-        {
-                u8 v;
-
-                pci_read_config_byte(dev, 0x40, &v);
-                v |= 2;
-                pci_write_config_byte(dev, 0x40, v);
-        }
-#endif
-#if 0 /* fix bus master base */
-        pci_write_config_dword(dev, 0x20, 0xcc01);
-        printk("old ide resource: %lx -> %lx \n",
-               dev->resource[4].start, dev->resource[4].end);
-        dev->resource[4].start = 0xcc00;
-        dev->resource[4].end = 0xcc10;
-#endif
-#if 0 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
-        {
-                struct pci_dev *apicdev;
-                u32 v;
-
-                apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
-                if (apicdev == NULL)
-                        printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
-                else {
-                        pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
-                        pci_read_config_dword(apicdev, 0xf4, &v);
-                        v &= ~0x00000022;
-                        pci_write_config_dword(apicdev, 0xf4, v);
-                        pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
-                        pci_read_config_dword(apicdev, 0xf4, &v);
-                        v &= ~0x00000022;
-                        pci_write_config_dword(apicdev, 0xf4, v);
-                        pci_dev_put(apicdev);
-                }
-        }
-#endif
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,
-                         fixup_maple_ide);
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c
index 3ce2d73b4177..364714757cf1 100644
--- a/arch/powerpc/platforms/maple/setup.c
+++ b/arch/powerpc/platforms/maple/setup.c
@@ -43,6 +43,7 @@
 #include <linux/smp.h>
 #include <linux/bitops.h>
 #include <linux/of_device.h>
+#include <linux/lmb.h>
 
 #include <asm/processor.h>
 #include <asm/sections.h>
@@ -57,7 +58,6 @@
 #include <asm/dma.h>
 #include <asm/cputable.h>
 #include <asm/time.h>
-#include <asm/lmb.h>
 #include <asm/mpic.h>
 #include <asm/rtas.h>
 #include <asm/udbg.h>
@@ -319,7 +319,7 @@ static int __init maple_probe(void)
         return 1;
 }
 
-define_machine(maple_md) {
+define_machine(maple) {
         .name                   = "Maple",
         .probe                  = maple_probe,
         .setup_arch             = maple_setup_arch,
diff --git a/arch/powerpc/platforms/pasemi/dma_lib.c b/arch/powerpc/platforms/pasemi/dma_lib.c
index c529d8dff395..217af321b0ca 100644
--- a/arch/powerpc/platforms/pasemi/dma_lib.c
+++ b/arch/powerpc/platforms/pasemi/dma_lib.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/pci.h>
@@ -26,6 +27,8 @@
 
 #define MAX_TXCH 64
 #define MAX_RXCH 64
+#define MAX_FLAGS 64
+#define MAX_FUN 8
 
 static struct pasdma_status *dma_status;
 
@@ -43,6 +46,8 @@ static struct pci_dev *dma_pdev;
 
 static DECLARE_BITMAP(txch_free, MAX_TXCH);
 static DECLARE_BITMAP(rxch_free, MAX_RXCH);
+static DECLARE_BITMAP(flags_free, MAX_FLAGS);
+static DECLARE_BITMAP(fun_free, MAX_FUN);
 
 /* pasemi_read_iob_reg - read IOB register
  * @reg: Register to read (offset into PCI CFG space)
@@ -373,6 +378,106 @@ void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
 }
 EXPORT_SYMBOL(pasemi_dma_free_buf);
 
+/* pasemi_dma_alloc_flag - Allocate a flag (event) for channel syncronization
+ *
+ * Allocates a flag for use with channel syncronization (event descriptors).
+ * Returns allocated flag (0-63), < 0 on error.
+ */
+int pasemi_dma_alloc_flag(void)
+{
+        int bit;
+
+retry:
+        bit = find_next_bit(flags_free, MAX_FLAGS, 0);
+        if (bit >= MAX_FLAGS)
+                return -ENOSPC;
+        if (!test_and_clear_bit(bit, flags_free))
+                goto retry;
+
+        return bit;
+}
+EXPORT_SYMBOL(pasemi_dma_alloc_flag);
+
+
+/* pasemi_dma_free_flag - Deallocates a flag (event)
+ * @flag: Flag number to deallocate
+ *
+ * Frees up a flag so it can be reused for other purposes.
+ */
+void pasemi_dma_free_flag(int flag)
+{
+        BUG_ON(test_bit(flag, flags_free));
+        BUG_ON(flag >= MAX_FLAGS);
+        set_bit(flag, flags_free);
+}
+EXPORT_SYMBOL(pasemi_dma_free_flag);
+
+
+/* pasemi_dma_set_flag - Sets a flag (event) to 1
+ * @flag: Flag number to set active
+ *
+ * Sets the flag provided to 1.
+ */
+void pasemi_dma_set_flag(int flag)
+{
+        BUG_ON(flag >= MAX_FLAGS);
+        if (flag < 32)
+                pasemi_write_dma_reg(PAS_DMA_TXF_SFLG0, 1 << flag);
+        else
+                pasemi_write_dma_reg(PAS_DMA_TXF_SFLG1, 1 << flag);
+}
+EXPORT_SYMBOL(pasemi_dma_set_flag);
+
+/* pasemi_dma_clear_flag - Sets a flag (event) to 0
+ * @flag: Flag number to set inactive
+ *
+ * Sets the flag provided to 0.
+ */
+void pasemi_dma_clear_flag(int flag)
+{
+        BUG_ON(flag >= MAX_FLAGS);
+        if (flag < 32)
+                pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 1 << flag);
+        else
+                pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 1 << flag);
+}
+EXPORT_SYMBOL(pasemi_dma_clear_flag);
+
+/* pasemi_dma_alloc_fun - Allocate a function engine
+ *
+ * Allocates a function engine to use for crypto/checksum offload
+ * Returns allocated engine (0-8), < 0 on error.
+ */
+int pasemi_dma_alloc_fun(void)
+{
+        int bit;
+
+retry:
+        bit = find_next_bit(fun_free, MAX_FLAGS, 0);
+        if (bit >= MAX_FLAGS)
+                return -ENOSPC;
+        if (!test_and_clear_bit(bit, fun_free))
+                goto retry;
+
+        return bit;
+}
+EXPORT_SYMBOL(pasemi_dma_alloc_fun);
+
+
+/* pasemi_dma_free_fun - Deallocates a function engine
+ * @flag: Engine number to deallocate
+ *
+ * Frees up a function engine so it can be used for other purposes.
+ */
+void pasemi_dma_free_fun(int fun)
+{
+        BUG_ON(test_bit(fun, fun_free));
+        BUG_ON(fun >= MAX_FLAGS);
+        set_bit(fun, fun_free);
+}
+EXPORT_SYMBOL(pasemi_dma_free_fun);
+
+
 static void *map_onedev(struct pci_dev *p, int index)
 {
         struct device_node *dn;
@@ -410,6 +515,7 @@ int pasemi_dma_init(void)
         struct resource res;
         struct device_node *dn;
         int i, intf, err = 0;
+        unsigned long timeout;
         u32 tmp;
 
         if (!machine_is(pasemi))
@@ -478,6 +584,44 @@ int pasemi_dma_init(void)
         for (i = 0; i < MAX_RXCH; i++)
                 __set_bit(i, rxch_free);
 
+        timeout = jiffies + HZ;
+        pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, 0);
+        while (pasemi_read_dma_reg(PAS_DMA_COM_RXSTA) & 1) {
+                if (time_after(jiffies, timeout)) {
+                        pr_warning("Warning: Could not disable RX section\n");
+                        break;
+                }
+        }
+
+        timeout = jiffies + HZ;
+        pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, 0);
+        while (pasemi_read_dma_reg(PAS_DMA_COM_TXSTA) & 1) {
+                if (time_after(jiffies, timeout)) {
+                        pr_warning("Warning: Could not disable TX section\n");
+                        break;
+                }
+        }
+
+        /* setup resource allocations for the different DMA sections */
+        tmp = pasemi_read_dma_reg(PAS_DMA_COM_CFG);
+        pasemi_write_dma_reg(PAS_DMA_COM_CFG, tmp | 0x18000000);
+
+        /* enable tx section */
+        pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
+
+        /* enable rx section */
+        pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
+
+        for (i = 0; i < MAX_FLAGS; i++)
+                __set_bit(i, flags_free);
+
+        for (i = 0; i < MAX_FUN; i++)
+                __set_bit(i, fun_free);
+
+        /* clear all status flags */
+        pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 0xffffffff);
+        pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 0xffffffff);
+
         printk(KERN_INFO "PA Semi PWRficient DMA library initialized "
                 "(%d tx, %d rx channels)\n", num_txch, num_rxch);
 
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 5803f11c77fc..86967bdd8774 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005-2007, PA Semi, Inc
+ * Copyright (C) 2005-2008, PA Semi, Inc
  *
  * Maintained by: Olof Johansson <olof@lixom.net>
  *
@@ -27,7 +27,6 @@
 #include <asm/abs_addr.h>
 #include <asm/firmware.h>
 
-
 #define IOBMAP_PAGE_SHIFT       12
 #define IOBMAP_PAGE_SIZE        (1 << IOBMAP_PAGE_SHIFT)
 #define IOBMAP_PAGE_MASK        (IOBMAP_PAGE_SIZE - 1)
@@ -35,13 +34,13 @@
 #define IOB_BASE                0xe0000000
 #define IOB_SIZE                0x3000
 /* Configuration registers */
-#define IOBCAP_REG              0x10
-#define IOBCOM_REG              0x40
+#define IOBCAP_REG              0x40
+#define IOBCOM_REG              0x100
 /* Enable IOB address translation */
 #define IOBCOM_ATEN             0x00000100
 
 /* Address decode configuration register */
-#define IOB_AD_REG              0x53
+#define IOB_AD_REG              0x14c
 /* IOBCOM_AD_REG fields */
 #define IOB_AD_VGPRT            0x00000e00
 #define IOB_AD_VGAEN            0x00000100
@@ -56,13 +55,13 @@
 #define IOB_AD_TRNG_2G          0x00000001
 #define IOB_AD_TRNG_128G        0x00000003
 
-#define IOB_TABLEBASE_REG       0x55
+#define IOB_TABLEBASE_REG       0x154
 
 /* Base of the 64 4-byte L1 registers */
-#define IOB_XLT_L1_REGBASE      0xac0
+#define IOB_XLT_L1_REGBASE      0x2b00
 
 /* Register to invalidate TLB entries */
-#define IOB_AT_INVAL_TLB_REG    0xb40
+#define IOB_AT_INVAL_TLB_REG    0x2d00
 
 /* The top two bits of the level 1 entry contains valid and type flags */
 #define IOBMAP_L1E_V            0x40000000
@@ -76,7 +75,7 @@
 #define IOBMAP_L2E_V            0x80000000
 #define IOBMAP_L2E_V_CACHED     0xc0000000
 
-static u32 __iomem *iob;
+static void __iomem *iob;
 static u32 iob_l1_emptyval;
 static u32 iob_l2_emptyval;
 static u32 *iob_l2_base;
@@ -219,7 +218,7 @@ int __init iob_init(struct device_node *dn)
         for (i = 0; i < 64; i++) {
                 /* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */
                 regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12);
-                out_le32(iob+IOB_XLT_L1_REGBASE+i, regword);
+                out_le32(iob+IOB_XLT_L1_REGBASE+i*4, regword);
         }
 
         /* set 2GB translation window, based at 0 */
diff --git a/arch/powerpc/platforms/powermac/pfunc_core.c b/arch/powerpc/platforms/powermac/pfunc_core.c
index 85434231ae14..96d5ce50364e 100644
--- a/arch/powerpc/platforms/powermac/pfunc_core.c
+++ b/arch/powerpc/platforms/powermac/pfunc_core.c
@@ -12,7 +12,6 @@
 #include <linux/module.h>
 #include <linux/mutex.h>
 
-#include <asm/semaphore.h>
 #include <asm/prom.h>
 #include <asm/pmac_pfunc.h>
 
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 2693fc371eab..bf44c5441a36 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -53,6 +53,7 @@
 #include <linux/suspend.h>
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
+#include <linux/lmb.h>
 
 #include <asm/reg.h>
 #include <asm/sections.h>
@@ -74,7 +75,6 @@
 #include <asm/iommu.h>
 #include <asm/smu.h>
 #include <asm/pmc.h>
-#include <asm/lmb.h>
 #include <asm/udbg.h>
 
 #include "pmac.h"
diff --git a/arch/powerpc/platforms/ps3/device-init.c b/arch/powerpc/platforms/ps3/device-init.c
index 9d251d0ca8c6..3866debfa3c4 100644
--- a/arch/powerpc/platforms/ps3/device-init.c
+++ b/arch/powerpc/platforms/ps3/device-init.c
@@ -499,41 +499,14 @@ static int __init ps3_register_graphics_devices(void)
 }
 
 /**
- * ps3_register_repository_device - Register a device from the repositiory info.
- *
+ * ps3_setup_dynamic_device - Setup a dynamic device from the repository
  */
 
-static int ps3_register_repository_device(
-        const struct ps3_repository_device *repo)
+static int ps3_setup_dynamic_device(const struct ps3_repository_device *repo)
 {
         int result;
 
         switch (repo->dev_type) {
-        case PS3_DEV_TYPE_SB_GELIC:
-                result = ps3_setup_gelic_device(repo);
-                if (result) {
-                        pr_debug("%s:%d ps3_setup_gelic_device failed\n",
-                                __func__, __LINE__);
-                }
-                break;
-        case PS3_DEV_TYPE_SB_USB:
-
-                /* Each USB device has both an EHCI and an OHCI HC */
-
-                result = ps3_setup_ehci_device(repo);
-
-                if (result) {
-                        pr_debug("%s:%d ps3_setup_ehci_device failed\n",
-                                __func__, __LINE__);
-                }
-
-                result = ps3_setup_ohci_device(repo);
-
-                if (result) {
-                        pr_debug("%s:%d ps3_setup_ohci_device failed\n",
-                                __func__, __LINE__);
-                }
-                break;
         case PS3_DEV_TYPE_STOR_DISK:
                 result = ps3_setup_storage_dev(repo, PS3_MATCH_ID_STOR_DISK);
 
@@ -572,6 +545,48 @@ static int ps3_register_repository_device(
         return result;
 }
 
+/**
+ * ps3_setup_static_device - Setup a static device from the repository
+ */
+
+static int __init ps3_setup_static_device(const struct ps3_repository_device *repo)
+{
+        int result;
+
+        switch (repo->dev_type) {
+        case PS3_DEV_TYPE_SB_GELIC:
+                result = ps3_setup_gelic_device(repo);
+                if (result) {
+                        pr_debug("%s:%d ps3_setup_gelic_device failed\n",
+                                __func__, __LINE__);
+                }
+                break;
+        case PS3_DEV_TYPE_SB_USB:
+
+                /* Each USB device has both an EHCI and an OHCI HC */
+
+                result = ps3_setup_ehci_device(repo);
+
+                if (result) {
+                        pr_debug("%s:%d ps3_setup_ehci_device failed\n",
+                                __func__, __LINE__);
+                }
+
+                result = ps3_setup_ohci_device(repo);
+
+                if (result) {
+                        pr_debug("%s:%d ps3_setup_ohci_device failed\n",
+                                __func__, __LINE__);
+                }
+                break;
+
+        default:
+                return ps3_setup_dynamic_device(repo);
+        }
+
+        return result;
+}
+
 static void ps3_find_and_add_device(u64 bus_id, u64 dev_id)
 {
         struct ps3_repository_device repo;
@@ -601,7 +616,7 @@ found:
                 pr_debug("%s:%u: device %lu:%lu found after %u retries\n",
                          __func__, __LINE__, bus_id, dev_id, retries);
 
-        ps3_register_repository_device(&repo);
+        ps3_setup_dynamic_device(&repo);
         return;
 }
 
@@ -905,8 +920,7 @@ static int __init ps3_register_devices(void)
 
         ps3_register_graphics_devices();
 
-        ps3_repository_find_devices(PS3_BUS_TYPE_SB,
-                ps3_register_repository_device);
+        ps3_repository_find_devices(PS3_BUS_TYPE_SB, ps3_setup_static_device);
 
         ps3_register_sound_devices();
 
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 7382f195c4f8..1cf901fa9031 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -19,9 +19,10 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/lmb.h>
 
 #include <asm/machdep.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
 #include <asm/ps3fb.h>
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c
index 3a6db04aa940..a14e5cdc2fed 100644
--- a/arch/powerpc/platforms/ps3/interrupt.c
+++ b/arch/powerpc/platforms/ps3/interrupt.c
@@ -709,7 +709,7 @@ static unsigned int ps3_get_irq(void)
         asm volatile("cntlzd %0,%1" : "=r" (plug) : "r" (x));
         plug &= 0x3f;
 
-        if (unlikely(plug) == NO_IRQ) {
+        if (unlikely(plug == NO_IRQ)) {
                 pr_debug("%s:%d: no plug found: thread_id %lu\n", __func__,
                         __LINE__, pd->thread_id);
                 dump_bmp(&per_cpu(ps3_private, 0));
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 68900476c842..5b3fb2b321ab 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -21,9 +21,10 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/memory_hotplug.h>
+#include <linux/lmb.h>
 
 #include <asm/firmware.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
 
diff --git a/arch/powerpc/platforms/ps3/os-area.c b/arch/powerpc/platforms/ps3/os-area.c
index b9ea09d9d2fb..c73379ec9141 100644
--- a/arch/powerpc/platforms/ps3/os-area.c
+++ b/arch/powerpc/platforms/ps3/os-area.c
@@ -24,8 +24,9 @@
 #include <linux/fs.h>
 #include <linux/syscalls.h>
 #include <linux/ctype.h>
+#include <linux/lmb.h>
 
-#include <asm/lmb.h>
+#include <asm/prom.h>
 
 #include "platform.h"
 
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index 5c2cbb08eb52..a413abbd4123 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -95,6 +95,14 @@ static void ps3_power_off(void)
         ps3_sys_manager_power_off(); /* never returns */
 }
 
+static void ps3_halt(void)
+{
+        DBG("%s:%d\n", __func__, __LINE__);
+
+        smp_send_stop();
+        ps3_sys_manager_halt(); /* never returns */
+}
+
 static void ps3_panic(char *str)
 {
         DBG("%s:%d %s\n", __func__, __LINE__, str);
@@ -105,7 +113,8 @@ static void ps3_panic(char *str)
         printk("   Please press POWER button.\n");
         printk("\n");
 
-        while(1);
+        while(1)
+                lv1_pause(1);
 }
 
 #if defined(CONFIG_FB_PS3) || defined(CONFIG_FB_PS3_MODULE) || \
@@ -117,7 +126,7 @@ static void __init prealloc(struct ps3_prealloc *p)
 
         p->address = __alloc_bootmem(p->size, p->align, __pa(MAX_DMA_ADDRESS));
         if (!p->address) {
-                printk(KERN_ERR "%s: Cannot allocate %s\n", __FUNCTION__,
+                printk(KERN_ERR "%s: Cannot allocate %s\n", __func__,
                        p->name);
                 return;
         }
@@ -266,6 +275,7 @@ define_machine(ps3) {
         .progress                       = ps3_progress,
         .restart                        = ps3_restart,
         .power_off                      = ps3_power_off,
+        .halt                           = ps3_halt,
 #if defined(CONFIG_KEXEC)
         .kexec_cpu_down                 = ps3_kexec_cpu_down,
         .machine_kexec                  = default_machine_kexec,
diff --git a/arch/powerpc/platforms/ps3/spu.c b/arch/powerpc/platforms/ps3/spu.c
index 5ad41189b494..d135cef9ed6a 100644
--- a/arch/powerpc/platforms/ps3/spu.c
+++ b/arch/powerpc/platforms/ps3/spu.c
@@ -27,6 +27,7 @@
 #include <asm/spu.h>
 #include <asm/spu_priv1.h>
 #include <asm/lv1call.h>
+#include <asm/ps3.h>
 
 #include "../cell/spufs/spufs.h"
 #include "platform.h"
@@ -140,6 +141,12 @@ static void _dump_areas(unsigned int spe_id, unsigned long priv2,
         pr_debug("%s:%d: shadow:  %lxh\n", func, line, shadow);
 }
 
+inline u64 ps3_get_spe_id(void *arg)
+{
+        return spu_pdata(arg)->spe_id;
+}
+EXPORT_SYMBOL_GPL(ps3_get_spe_id);
+
 static unsigned long get_vas_id(void)
 {
         unsigned long id;
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 992ba6753cf2..bdae04bb7a01 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug-cpu.o
 obj-$(CONFIG_HVC_CONSOLE)       += hvconsole.o
 obj-$(CONFIG_HVCS)              += hvcserver.o
 obj-$(CONFIG_HCALL_STATS)       += hvCall_inst.o
+obj-$(CONFIG_PHYP_DUMP) += phyp_dump.o
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 9eb539ee5f9a..550b2f7d2cc1 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -945,7 +945,6 @@ static void *early_enable_eeh(struct device_node *dn, void *data)
         unsigned int rets[3];
         struct eeh_early_enable_info *info = data;
         int ret;
-        const char *status = of_get_property(dn, "status", NULL);
         const u32 *class_code = of_get_property(dn, "class-code", NULL);
         const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL);
         const u32 *device_id = of_get_property(dn, "device-id", NULL);
@@ -959,8 +958,8 @@ static void *early_enable_eeh(struct device_node *dn, void *data)
         pdn->eeh_freeze_count = 0;
         pdn->eeh_false_positives = 0;
 
-        if (status && strncmp(status, "ok", 2) != 0)
-                return NULL;    /* ignore devices with bad status */
+        if (!of_device_is_available(dn))
+                return NULL;
 
         /* Ignore bad nodes. */
         if (!class_code || !vendor_id || !device_id)
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 9a455d46379d..9235c469449e 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -40,6 +40,7 @@
 #include <asm/smp.h>
 
 #include "plpar_wrappers.h"
+#include "pseries.h"
 
 #ifdef DEBUG_LOW
 #define DBG_LOW(fmt...) do { udbg_printf(fmt); } while(0)
@@ -203,7 +204,6 @@ void __init find_udbg_vterm(void)
         struct device_node *stdout_node;
         const u32 *termno;
         const char *name;
-        int add_console;
 
         /* find the boot console from /chosen/stdout */
         if (!of_chosen)
@@ -219,8 +219,6 @@ void __init find_udbg_vterm(void)
                 printk(KERN_WARNING "stdout node missing 'name' property!\n");
                 goto out;
         }
-        /* The user has requested a console so this is already set up. */
-        add_console = !strstr(cmd_line, "console=");
 
         /* Check if it's a virtual terminal */
         if (strncmp(name, "vty", 3) != 0)
@@ -234,15 +232,13 @@ void __init find_udbg_vterm(void)
                 udbg_putc = udbg_putcLP;
                 udbg_getc = udbg_getcLP;
                 udbg_getc_poll = udbg_getc_pollLP;
-                if (add_console)
-                        add_preferred_console("hvc", termno[0] & 0xff, NULL);
+                add_preferred_console("hvc", termno[0] & 0xff, NULL);
         } else if (of_device_is_compatible(stdout_node, "hvterm-protocol")) {
                 vtermno = termno[0];
                 udbg_putc = udbg_hvsi_putc;
                 udbg_getc = udbg_hvsi_getc;
                 udbg_getc_poll = udbg_hvsi_getc_poll;
-                if (add_console)
-                        add_preferred_console("hvsi", termno[0] & 0xff, NULL);
+                add_preferred_console("hvsi", termno[0] & 0xff, NULL);
         }
 out:
         of_node_put(stdout_node);
@@ -520,6 +516,20 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
         BUG_ON(lpar_rc != H_SUCCESS);
 }
 
+static void pSeries_lpar_hpte_removebolted(unsigned long ea,
+                                           int psize, int ssize)
+{
+        unsigned long slot, vsid, va;
+
+        vsid = get_kernel_vsid(ea, ssize);
+        va = hpt_va(ea, vsid, ssize);
+
+        slot = pSeries_lpar_hpte_find(va, psize, ssize);
+        BUG_ON(slot == -1);
+
+        pSeries_lpar_hpte_invalidate(slot, va, psize, ssize, 0);
+}
+
 /* Flag bits for H_BULK_REMOVE */
 #define HBR_REQUEST     0x4000000000000000UL
 #define HBR_RESPONSE    0x8000000000000000UL
@@ -597,6 +607,7 @@ void __init hpte_init_lpar(void)
         ppc_md.hpte_updateboltedpp = pSeries_lpar_hpte_updateboltedpp;
         ppc_md.hpte_insert      = pSeries_lpar_hpte_insert;
         ppc_md.hpte_remove      = pSeries_lpar_hpte_remove;
+        ppc_md.hpte_removebolted = pSeries_lpar_hpte_removebolted;
         ppc_md.flush_hash_range = pSeries_lpar_flush_hash_range;
         ppc_md.hpte_clear_all   = pSeries_lpar_hptab_clear;
 }
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 5a5a19e40bb4..0d7229cde0e9 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -123,7 +123,7 @@ pcibios_pci_config_bridge(struct pci_dev *dev)
         /* Add to children of PCI bridge dev->bus */
         child_bus = pci_add_new_bus(dev->bus, dev, sec_busno);
         if (!child_bus) {
-                printk (KERN_ERR "%s: could not add second bus\n", __FUNCTION__);
+                printk (KERN_ERR "%s: could not add second bus\n", __func__);
                 return -EIO;
         }
         sprintf(child_bus->name, "PCI Bus #%02x", child_bus->number);
diff --git a/arch/powerpc/platforms/pseries/phyp_dump.c b/arch/powerpc/platforms/pseries/phyp_dump.c
new file mode 100644
index 000000000000..edbc012c2ebc
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/phyp_dump.c
@@ -0,0 +1,507 @@
+/*
+ * Hypervisor-assisted dump
+ *
+ * Linas Vepstas, Manish Ahuja 2008
+ * Copyright 2008 IBM Corp.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kobject.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <linux/pfn.h>
+#include <linux/swap.h>
+#include <linux/sysfs.h>
+
+#include <asm/page.h>
+#include <asm/phyp_dump.h>
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/rtas.h>
+
+/* Variables, used to communicate data between early boot and late boot */
+static struct phyp_dump phyp_dump_vars;
+struct phyp_dump *phyp_dump_info = &phyp_dump_vars;
+
+static int ibm_configure_kernel_dump;
+/* ------------------------------------------------- */
+/* RTAS interfaces to declare the dump regions */
+
+struct dump_section {
+        u32 dump_flags;
+        u16 source_type;
+        u16 error_flags;
+        u64 source_address;
+        u64 source_length;
+        u64 length_copied;
+        u64 destination_address;
+};
+
+struct phyp_dump_header {
+        u32 version;
+        u16 num_of_sections;
+        u16 status;
+
+        u32 first_offset_section;
+        u32 dump_disk_section;
+        u64 block_num_dd;
+        u64 num_of_blocks_dd;
+        u32 offset_dd;
+        u32 maxtime_to_auto;
+        /* No dump disk path string used */
+
+        struct dump_section cpu_data;
+        struct dump_section hpte_data;
+        struct dump_section kernel_data;
+};
+
+/* The dump header *must be* in low memory, so .bss it */
+static struct phyp_dump_header phdr;
+
+#define NUM_DUMP_SECTIONS       3
+#define DUMP_HEADER_VERSION     0x1
+#define DUMP_REQUEST_FLAG       0x1
+#define DUMP_SOURCE_CPU         0x0001
+#define DUMP_SOURCE_HPTE        0x0002
+#define DUMP_SOURCE_RMO         0x0011
+#define DUMP_ERROR_FLAG         0x2000
+#define DUMP_TRIGGERED          0x4000
+#define DUMP_PERFORMED          0x8000
+
+
+/**
+ * init_dump_header() - initialize the header declaring a dump
+ * Returns: length of dump save area.
+ *
+ * When the hypervisor saves crashed state, it needs to put
+ * it somewhere. The dump header tells the hypervisor where
+ * the data can be saved.
+ */
+static unsigned long init_dump_header(struct phyp_dump_header *ph)
+{
+        unsigned long addr_offset = 0;
+
+        /* Set up the dump header */
+        ph->version = DUMP_HEADER_VERSION;
+        ph->num_of_sections = NUM_DUMP_SECTIONS;
+        ph->status = 0;
+
+        ph->first_offset_section =
+                (u32)offsetof(struct phyp_dump_header, cpu_data);
+        ph->dump_disk_section = 0;
+        ph->block_num_dd = 0;
+        ph->num_of_blocks_dd = 0;
+        ph->offset_dd = 0;
+
+        ph->maxtime_to_auto = 0; /* disabled */
+
+        /* The first two sections are mandatory */
+        ph->cpu_data.dump_flags = DUMP_REQUEST_FLAG;
+        ph->cpu_data.source_type = DUMP_SOURCE_CPU;
+        ph->cpu_data.source_address = 0;
+        ph->cpu_data.source_length = phyp_dump_info->cpu_state_size;
+        ph->cpu_data.destination_address = addr_offset;
+        addr_offset += phyp_dump_info->cpu_state_size;
+
+        ph->hpte_data.dump_flags = DUMP_REQUEST_FLAG;
+        ph->hpte_data.source_type = DUMP_SOURCE_HPTE;
+        ph->hpte_data.source_address = 0;
+        ph->hpte_data.source_length = phyp_dump_info->hpte_region_size;
+        ph->hpte_data.destination_address = addr_offset;
+        addr_offset += phyp_dump_info->hpte_region_size;
+
+        /* This section describes the low kernel region */
+        ph->kernel_data.dump_flags = DUMP_REQUEST_FLAG;
+        ph->kernel_data.source_type = DUMP_SOURCE_RMO;
+        ph->kernel_data.source_address = PHYP_DUMP_RMR_START;
+        ph->kernel_data.source_length = PHYP_DUMP_RMR_END;
+        ph->kernel_data.destination_address = addr_offset;
+        addr_offset += ph->kernel_data.source_length;
+
+        return addr_offset;
+}
+
+static void print_dump_header(const struct phyp_dump_header *ph)
+{
+#ifdef DEBUG
+        printk(KERN_INFO "dump header:\n");
+        /* setup some ph->sections required */
+        printk(KERN_INFO "version = %d\n", ph->version);
+        printk(KERN_INFO "Sections = %d\n", ph->num_of_sections);
+        printk(KERN_INFO "Status = 0x%x\n", ph->status);
+
+        /* No ph->disk, so all should be set to 0 */
+        printk(KERN_INFO "Offset to first section 0x%x\n",
+                ph->first_offset_section);
+        printk(KERN_INFO "dump disk sections should be zero\n");
+        printk(KERN_INFO "dump disk section = %d\n", ph->dump_disk_section);
+        printk(KERN_INFO "block num = %ld\n", ph->block_num_dd);
+        printk(KERN_INFO "number of blocks = %ld\n", ph->num_of_blocks_dd);
+        printk(KERN_INFO "dump disk offset = %d\n", ph->offset_dd);
+        printk(KERN_INFO "Max auto time= %d\n", ph->maxtime_to_auto);
+
+        /*set cpu state and hpte states as well scratch pad area */
+        printk(KERN_INFO " CPU AREA \n");
+        printk(KERN_INFO "cpu dump_flags =%d\n", ph->cpu_data.dump_flags);
+        printk(KERN_INFO "cpu source_type =%d\n", ph->cpu_data.source_type);
+        printk(KERN_INFO "cpu error_flags =%d\n", ph->cpu_data.error_flags);
+        printk(KERN_INFO "cpu source_address =%lx\n",
+                ph->cpu_data.source_address);
+        printk(KERN_INFO "cpu source_length =%lx\n",
+                ph->cpu_data.source_length);
+        printk(KERN_INFO "cpu length_copied =%lx\n",
+                ph->cpu_data.length_copied);
+
+        printk(KERN_INFO " HPTE AREA \n");
+        printk(KERN_INFO "HPTE dump_flags =%d\n", ph->hpte_data.dump_flags);
+        printk(KERN_INFO "HPTE source_type =%d\n", ph->hpte_data.source_type);
+        printk(KERN_INFO "HPTE error_flags =%d\n", ph->hpte_data.error_flags);
+        printk(KERN_INFO "HPTE source_address =%lx\n",
+                ph->hpte_data.source_address);
+        printk(KERN_INFO "HPTE source_length =%lx\n",
+                ph->hpte_data.source_length);
+        printk(KERN_INFO "HPTE length_copied =%lx\n",
+                ph->hpte_data.length_copied);
+
+        printk(KERN_INFO " SRSD AREA \n");
+        printk(KERN_INFO "SRSD dump_flags =%d\n", ph->kernel_data.dump_flags);
+        printk(KERN_INFO "SRSD source_type =%d\n", ph->kernel_data.source_type);
+        printk(KERN_INFO "SRSD error_flags =%d\n", ph->kernel_data.error_flags);
+        printk(KERN_INFO "SRSD source_address =%lx\n",
+                ph->kernel_data.source_address);
+        printk(KERN_INFO "SRSD source_length =%lx\n",
+                ph->kernel_data.source_length);
+        printk(KERN_INFO "SRSD length_copied =%lx\n",
+                ph->kernel_data.length_copied);
+#endif
+}
+
+static ssize_t show_phyp_dump_active(struct kobject *kobj,
+                        struct kobj_attribute *attr, char *buf)
+{
+
+        /* create filesystem entry so kdump is phyp-dump aware */
+        return sprintf(buf, "%lx\n", phyp_dump_info->phyp_dump_at_boot);
+}
+
+static struct kobj_attribute pdl = __ATTR(phyp_dump_active, 0600,
+                                        show_phyp_dump_active,
+                                        NULL);
+
+static void register_dump_area(struct phyp_dump_header *ph, unsigned long addr)
+{
+        int rc;
+
+        /* Add addr value if not initialized before */
+        if (ph->cpu_data.destination_address == 0) {
+                ph->cpu_data.destination_address += addr;
+                ph->hpte_data.destination_address += addr;
+                ph->kernel_data.destination_address += addr;
+        }
+
+        /* ToDo Invalidate kdump and free memory range. */
+
+        do {
+                rc = rtas_call(ibm_configure_kernel_dump, 3, 1, NULL,
+                                1, ph, sizeof(struct phyp_dump_header));
+        } while (rtas_busy_delay(rc));
+
+        if (rc) {
+                printk(KERN_ERR "phyp-dump: unexpected error (%d) on "
+                                                "register\n", rc);
+                print_dump_header(ph);
+                return;
+        }
+
+        rc = sysfs_create_file(kernel_kobj, &pdl.attr);
+        if (rc)
+                printk(KERN_ERR "phyp-dump: unable to create sysfs"
+                                " file (%d)\n", rc);
+}
+
+static
+void invalidate_last_dump(struct phyp_dump_header *ph, unsigned long addr)
+{
+        int rc;
+
+        /* Add addr value if not initialized before */
+        if (ph->cpu_data.destination_address == 0) {
+                ph->cpu_data.destination_address += addr;
+                ph->hpte_data.destination_address += addr;
+                ph->kernel_data.destination_address += addr;
+        }
+
+        do {
+                rc = rtas_call(ibm_configure_kernel_dump, 3, 1, NULL,
+                                2, ph, sizeof(struct phyp_dump_header));
+        } while (rtas_busy_delay(rc));
+
+        if (rc) {
+                printk(KERN_ERR "phyp-dump: unexpected error (%d) "
+                                                "on invalidate\n", rc);
+                print_dump_header(ph);
+        }
+}
+
+/* ------------------------------------------------- */
+/**
+ * release_memory_range -- release memory previously lmb_reserved
+ * @start_pfn: starting physical frame number
+ * @nr_pages: number of pages to free.
+ *
+ * This routine will release memory that had been previously
+ * lmb_reserved in early boot. The released memory becomes
+ * available for genreal use.
+ */
+static void release_memory_range(unsigned long start_pfn,
+                        unsigned long nr_pages)
+{
+        struct page *rpage;
+        unsigned long end_pfn;
+        long i;
+
+        end_pfn = start_pfn + nr_pages;
+
+        for (i = start_pfn; i <= end_pfn; i++) {
+                rpage = pfn_to_page(i);
+                if (PageReserved(rpage)) {
+                        ClearPageReserved(rpage);
+                        init_page_count(rpage);
+                        __free_page(rpage);
+                        totalram_pages++;
+                }
+        }
+}
+
+/**
+ * track_freed_range -- Counts the range being freed.
+ * Once the counter goes to zero, it re-registers dump for
+ * future use.
+ */
+static void
+track_freed_range(unsigned long addr, unsigned long length)
+{
+        static unsigned long scratch_area_size, reserved_area_size;
+
+        if (addr < phyp_dump_info->init_reserve_start)
+                return;
+
+        if ((addr >= phyp_dump_info->init_reserve_start) &&
+            (addr <= phyp_dump_info->init_reserve_start +
+             phyp_dump_info->init_reserve_size))
+                reserved_area_size += length;
+
+        if ((addr >= phyp_dump_info->reserved_scratch_addr) &&
+            (addr <= phyp_dump_info->reserved_scratch_addr +
+             phyp_dump_info->reserved_scratch_size))
+                scratch_area_size += length;
+
+        if ((reserved_area_size == phyp_dump_info->init_reserve_size) &&
+            (scratch_area_size == phyp_dump_info->reserved_scratch_size)) {
+
+                invalidate_last_dump(&phdr,
+                                phyp_dump_info->reserved_scratch_addr);
+                register_dump_area(&phdr,
+                                phyp_dump_info->reserved_scratch_addr);
+        }
+}
+
+/* ------------------------------------------------- */
+/**
+ * sysfs_release_region -- sysfs interface to release memory range.
+ *
+ * Usage:
+ *   "echo <start addr> <length> > /sys/kernel/release_region"
+ *
+ * Example:
+ *   "echo 0x40000000 0x10000000 > /sys/kernel/release_region"
+ *
+ * will release 256MB starting at 1GB.
+ */
+static ssize_t store_release_region(struct kobject *kobj,
+                                struct kobj_attribute *attr,
+                                const char *buf, size_t count)
+{
+        unsigned long start_addr, length, end_addr;
+        unsigned long start_pfn, nr_pages;
+        ssize_t ret;
+
+        ret = sscanf(buf, "%lx %lx", &start_addr, &length);
+        if (ret != 2)
+                return -EINVAL;
+
+        track_freed_range(start_addr, length);
+
+        /* Range-check - don't free any reserved memory that
+         * wasn't reserved for phyp-dump */
+        if (start_addr < phyp_dump_info->init_reserve_start)
+                start_addr = phyp_dump_info->init_reserve_start;
+
+        end_addr = phyp_dump_info->init_reserve_start +
+                        phyp_dump_info->init_reserve_size;
+        if (start_addr+length > end_addr)
+                length = end_addr - start_addr;
+
+        /* Release the region of memory assed in by user */
+        start_pfn = PFN_DOWN(start_addr);
+        nr_pages = PFN_DOWN(length);
+        release_memory_range(start_pfn, nr_pages);
+
+        return count;
+}
+
+static ssize_t show_release_region(struct kobject *kobj,
+                        struct kobj_attribute *attr, char *buf)
+{
+        u64 second_addr_range;
+
+        /* total reserved size - start of scratch area */
+        second_addr_range = phyp_dump_info->init_reserve_size -
+                                phyp_dump_info->reserved_scratch_size;
+        return sprintf(buf, "CPU:0x%lx-0x%lx: HPTE:0x%lx-0x%lx:"
+                            " DUMP:0x%lx-0x%lx, 0x%lx-0x%lx:\n",
+                phdr.cpu_data.destination_address,
+                phdr.cpu_data.length_copied,
+                phdr.hpte_data.destination_address,
+                phdr.hpte_data.length_copied,
+                phdr.kernel_data.destination_address,
+                phdr.kernel_data.length_copied,
+                phyp_dump_info->init_reserve_start,
+                second_addr_range);
+}
+
+static struct kobj_attribute rr = __ATTR(release_region, 0600,
+                                        show_release_region,
+                                        store_release_region);
+
+static int __init phyp_dump_setup(void)
+{
+        struct device_node *rtas;
+        const struct phyp_dump_header *dump_header = NULL;
+        unsigned long dump_area_start;
+        unsigned long dump_area_length;
+        int header_len = 0;
+        int rc;
+
+        /* If no memory was reserved in early boot, there is nothing to do */
+        if (phyp_dump_info->init_reserve_size == 0)
+                return 0;
+
+        /* Return if phyp dump not supported */
+        if (!phyp_dump_info->phyp_dump_configured)
+                return -ENOSYS;
+
+        /* Is there dump data waiting for us? If there isn't,
+         * then register a new dump area, and release all of
+         * the rest of the reserved ram.
+         *
+         * The /rtas/ibm,kernel-dump rtas node is present only
+         * if there is dump data waiting for us.
+         */
+        rtas = of_find_node_by_path("/rtas");
+        if (rtas) {
+                dump_header = of_get_property(rtas, "ibm,kernel-dump",
+                                                &header_len);
+                of_node_put(rtas);
+        }
+
+        print_dump_header(dump_header);
+        dump_area_length = init_dump_header(&phdr);
+        /* align down */
+        dump_area_start = phyp_dump_info->init_reserve_start & PAGE_MASK;
+
+        if (dump_header == NULL) {
+                register_dump_area(&phdr, dump_area_start);
+                return 0;
+        }
+
+        /* re-register the dump area, if old dump was invalid */
+        if ((dump_header) && (dump_header->status & DUMP_ERROR_FLAG)) {
+                invalidate_last_dump(&phdr, dump_area_start);
+                register_dump_area(&phdr, dump_area_start);
+                return 0;
+        }
+
+        if (dump_header) {
+                phyp_dump_info->reserved_scratch_addr =
+                                dump_header->cpu_data.destination_address;
+                phyp_dump_info->reserved_scratch_size =
+                                dump_header->cpu_data.source_length +
+                                dump_header->hpte_data.source_length +
+                                dump_header->kernel_data.source_length;
+        }
+
+        /* Should we create a dump_subsys, analogous to s390/ipl.c ? */
+        rc = sysfs_create_file(kernel_kobj, &rr.attr);
+        if (rc)
+                printk(KERN_ERR "phyp-dump: unable to create sysfs file (%d)\n",
+                                                                        rc);
+
+        /* ToDo: re-register the dump area, for next time. */
+        return 0;
+}
+machine_subsys_initcall(pseries, phyp_dump_setup);
+
+int __init early_init_dt_scan_phyp_dump(unsigned long node,
+                const char *uname, int depth, void *data)
+{
+        const unsigned int *sizes;
+
+        phyp_dump_info->phyp_dump_configured = 0;
+        phyp_dump_info->phyp_dump_is_active = 0;
+
+        if (depth != 1 || strcmp(uname, "rtas") != 0)
+                return 0;
+
+        if (of_get_flat_dt_prop(node, "ibm,configure-kernel-dump", NULL))
+                phyp_dump_info->phyp_dump_configured++;
+
+        if (of_get_flat_dt_prop(node, "ibm,dump-kernel", NULL))
+                phyp_dump_info->phyp_dump_is_active++;
+
+        sizes = of_get_flat_dt_prop(node, "ibm,configure-kernel-dump-sizes",
+                                    NULL);
+        if (!sizes)
+                return 0;
+
+        if (sizes[0] == 1)
+                phyp_dump_info->cpu_state_size = *((unsigned long *)&sizes[1]);
+
+        if (sizes[3] == 2)
+                phyp_dump_info->hpte_region_size =
+                                                *((unsigned long *)&sizes[4]);
+        return 1;
+}
+
+/* Look for phyp_dump= cmdline option */
+static int __init early_phyp_dump_enabled(char *p)
+{
+        phyp_dump_info->phyp_dump_at_boot = 1;
+
+        if (!p)
+                return 0;
+
+        if (strncmp(p, "1", 1) == 0)
+                phyp_dump_info->phyp_dump_at_boot = 1;
+        else if (strncmp(p, "0", 1) == 0)
+                phyp_dump_info->phyp_dump_at_boot = 0;
+
+        return 0;
+}
+early_param("phyp_dump", early_phyp_dump_enabled);
+
+/* Look for phyp_dump_reserve_size= cmdline option */
+static int __init early_phyp_dump_reserve_size(char *p)
+{
+        if (p)
+                phyp_dump_info->reserve_bootvar = memparse(p, &p);
+
+        return 0;
+}
+early_param("phyp_dump_reserve_size", early_phyp_dump_reserve_size);
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 61136d019554..9e17c0d2a0c8 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -38,4 +38,6 @@ extern void pSeries_final_fixup(void);
 /* Poweron flag used for enabling auto ups restart */
 extern unsigned long rtas_poweron_auto;
 
+extern void find_udbg_vterm(void);
+
 #endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index 2800fced8c7c..ac75c10de278 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -222,14 +222,14 @@ static char * parse_next_property(char *buf, char *end, char **name, int *length
         tmp = strchr(buf, ' ');
         if (!tmp) {
                 printk(KERN_ERR "property parse failed in %s at line %d\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 return NULL;
         }
         *tmp = '\0';
 
         if (++tmp >= end) {
                 printk(KERN_ERR "property parse failed in %s at line %d\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 return NULL;
         }
 
@@ -238,12 +238,12 @@ static char * parse_next_property(char *buf, char *end, char **name, int *length
         *length = simple_strtoul(tmp, &tmp, 10);
         if (*length == -1) {
                 printk(KERN_ERR "property parse failed in %s at line %d\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 return NULL;
         }
         if (*tmp != ' ' || ++tmp >= end) {
                 printk(KERN_ERR "property parse failed in %s at line %d\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 return NULL;
         }
 
@@ -252,12 +252,12 @@ static char * parse_next_property(char *buf, char *end, char **name, int *length
         tmp += *length;
         if (tmp > end) {
                 printk(KERN_ERR "property parse failed in %s at line %d\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 return NULL;
         }
         else if (tmp < end && *tmp != ' ' && *tmp != '\0') {
                 printk(KERN_ERR "property parse failed in %s at line %d\n",
-                       __FUNCTION__, __LINE__);
+                       __func__, __LINE__);
                 return NULL;
         }
         tmp++;
diff --git a/arch/powerpc/platforms/pseries/scanlog.c b/arch/powerpc/platforms/pseries/scanlog.c
index 8e1ef168e2dd..e5b0ea870164 100644
--- a/arch/powerpc/platforms/pseries/scanlog.c
+++ b/arch/powerpc/platforms/pseries/scanlog.c
@@ -195,31 +195,30 @@ const struct file_operations scanlog_fops = {
 static int __init scanlog_init(void)
 {
         struct proc_dir_entry *ent;
+        void *data;
+        int err = -ENOMEM;
 
         ibm_scan_log_dump = rtas_token("ibm,scan-log-dump");
-        if (ibm_scan_log_dump == RTAS_UNKNOWN_SERVICE) {
-                printk(KERN_ERR "scan-log-dump not implemented on this system\n");
-                return -EIO;
-        }
+        if (ibm_scan_log_dump == RTAS_UNKNOWN_SERVICE)
+                return -ENODEV;
 
-        ent = create_proc_entry("ppc64/rtas/scan-log-dump",  S_IRUSR, NULL);
-        if (ent) {
-                ent->proc_fops = &scanlog_fops;
-                /* Ideally we could allocate a buffer < 4G */
-                ent->data = kmalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
-                if (!ent->data) {
-                        printk(KERN_ERR "Failed to allocate a buffer\n");
-                        remove_proc_entry("scan-log-dump", ent->parent);
-                        return -ENOMEM;
-                }
-                ((unsigned int *)ent->data)[0] = 0;
-        } else {
-                printk(KERN_ERR "Failed to create ppc64/scan-log-dump proc entry\n");
-                return -EIO;
-        }
+        /* Ideally we could allocate a buffer < 4G */
+        data = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
+        if (!data)
+                goto err;
+
+        ent = proc_create("ppc64/rtas/scan-log-dump", S_IRUSR, NULL,
+                          &scanlog_fops);
+        if (!ent)
+                goto err;
+
+        ent->data = data;
         proc_ppc64_scan_log_dump = ent;
 
         return 0;
+err:
+        kfree(data);
+        return err;
 }
 
 static void __exit scanlog_cleanup(void)
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index fdb9b1c8f977..f66aa9c3b135 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -76,9 +76,6 @@
 #define DBG(fmt...)
 #endif
 
-/* move those away to a .h */
-extern void find_udbg_vterm(void);
-
 int fwnmi_active;  /* TRUE if an FWNMI handler is present */
 
 static void pseries_shared_idle_sleep(void);
@@ -127,14 +124,60 @@ void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc)
         desc->chip->eoi(irq);
 }
 
-static void __init pseries_mpic_init_IRQ(void)
+static void __init pseries_setup_i8259_cascade(void)
 {
-        struct device_node *np, *old, *cascade = NULL;
-        const unsigned int *addrp;
+        struct device_node *np, *old, *found = NULL;
+        unsigned int cascade;
+        const u32 *addrp;
         unsigned long intack = 0;
+        int naddr;
+
+        for_each_node_by_type(np, "interrupt-controller") {
+                if (of_device_is_compatible(np, "chrp,iic")) {
+                        found = np;
+                        break;
+                }
+        }
+
+        if (found == NULL) {
+                printk(KERN_DEBUG "pic: no ISA interrupt controller\n");
+                return;
+        }
+
+        cascade = irq_of_parse_and_map(found, 0);
+        if (cascade == NO_IRQ) {
+                printk(KERN_ERR "pic: failed to map cascade interrupt");
+                return;
+        }
+        pr_debug("pic: cascade mapped to irq %d\n", cascade);
+
+        for (old = of_node_get(found); old != NULL ; old = np) {
+                np = of_get_parent(old);
+                of_node_put(old);
+                if (np == NULL)
+                        break;
+                if (strcmp(np->name, "pci") != 0)
+                        continue;
+                addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
+                if (addrp == NULL)
+                        continue;
+                naddr = of_n_addr_cells(np);
+                intack = addrp[naddr-1];
+                if (naddr > 1)
+                        intack |= ((unsigned long)addrp[naddr-2]) << 32;
+        }
+        if (intack)
+                printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
+        i8259_init(found, intack);
+        of_node_put(found);
+        set_irq_chained_handler(cascade, pseries_8259_cascade);
+}
+
+static void __init pseries_mpic_init_IRQ(void)
+{
+        struct device_node *np;
         const unsigned int *opprop;
         unsigned long openpic_addr = 0;
-        unsigned int cascade_irq;
         int naddr, n, i, opplen;
         struct mpic *mpic;
 
@@ -167,43 +210,13 @@ static void __init pseries_mpic_init_IRQ(void)
         mpic_init(mpic);
 
         /* Look for cascade */
-        for_each_node_by_type(np, "interrupt-controller")
-                if (of_device_is_compatible(np, "chrp,iic")) {
-                        cascade = np;
-                        break;
-                }
-        if (cascade == NULL)
-                return;
-
-        cascade_irq = irq_of_parse_and_map(cascade, 0);
-        if (cascade_irq == NO_IRQ) {
-                printk(KERN_ERR "mpic: failed to map cascade interrupt");
-                return;
-        }
+        pseries_setup_i8259_cascade();
+}
 
-        /* Check ACK type */
-        for (old = of_node_get(cascade); old != NULL ; old = np) {
-                np = of_get_parent(old);
-                of_node_put(old);
-                if (np == NULL)
-                        break;
-                if (strcmp(np->name, "pci") != 0)
-                        continue;
-                addrp = of_get_property(np, "8259-interrupt-acknowledge",
-                                            NULL);
-                if (addrp == NULL)
-                        continue;
-                naddr = of_n_addr_cells(np);
-                intack = addrp[naddr-1];
-                if (naddr > 1)
-                        intack |= ((unsigned long)addrp[naddr-2]) << 32;
-        }
-        if (intack)
-                printk(KERN_DEBUG "mpic: PCI 8259 intack at 0x%016lx\n",
-                       intack);
-        i8259_init(cascade, intack);
-        of_node_put(cascade);
-        set_irq_chained_handler(cascade_irq, pseries_8259_cascade);
+static void __init pseries_xics_init_IRQ(void)
+{
+        xics_init_IRQ();
+        pseries_setup_i8259_cascade();
 }
 
 static void pseries_lpar_enable_pmcs(void)
@@ -235,7 +248,7 @@ static void __init pseries_discover_pic(void)
                         smp_init_pseries_mpic();
                         return;
                 } else if (strstr(typep, "ppc-xicp")) {
-                        ppc_md.init_IRQ       = xics_init_IRQ;
+                        ppc_md.init_IRQ       = pseries_xics_init_IRQ;
                         setup_kexec_cpu_down_xics();
                         smp_init_pseries_xics();
                         return;
@@ -393,6 +406,7 @@ static void pseries_dedicated_idle_sleep(void)
 { 
         unsigned int cpu = smp_processor_id();
         unsigned long start_snooze;
+        unsigned long in_purr, out_purr;
 
         /*
          * Indicate to the HV that we are idle. Now would be
@@ -400,6 +414,7 @@ static void pseries_dedicated_idle_sleep(void)
          */
         get_lppaca()->idle = 1;
         get_lppaca()->donate_dedicated_cpu = 1;
+        in_purr = mfspr(SPRN_PURR);
 
         /*
          * We come in with interrupts disabled, and need_resched()
@@ -432,6 +447,8 @@ static void pseries_dedicated_idle_sleep(void)
 
 out:
         HMT_medium();
+        out_purr = mfspr(SPRN_PURR);
+        get_lppaca()->wait_state_cycles += out_purr - in_purr;
         get_lppaca()->donate_dedicated_cpu = 0;
         get_lppaca()->idle = 0;
 }
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index a977f200db89..43df53c30aa0 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -516,6 +516,8 @@ static struct irq_chip xics_pic_lpar = {
         .set_affinity = xics_set_affinity
 };
 
+/* Points to the irq_chip we're actually using */
+static struct irq_chip *xics_irq_chip;
 
 static int xics_host_match(struct irq_host *h, struct device_node *node)
 {
@@ -526,23 +528,13 @@ static int xics_host_match(struct irq_host *h, struct device_node *node)
         return !of_device_is_compatible(node, "chrp,iic");
 }
 
-static int xics_host_map_direct(struct irq_host *h, unsigned int virq,
-                                irq_hw_number_t hw)
+static int xics_host_map(struct irq_host *h, unsigned int virq,
+                         irq_hw_number_t hw)
 {
-        pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
+        pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
 
         get_irq_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &xics_pic_direct, handle_fasteoi_irq);
-        return 0;
-}
-
-static int xics_host_map_lpar(struct irq_host *h, unsigned int virq,
-                              irq_hw_number_t hw)
-{
-        pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
-
-        get_irq_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &xics_pic_lpar, handle_fasteoi_irq);
+        set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
         return 0;
 }
 
@@ -561,27 +553,20 @@ static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
         return 0;
 }
 
-static struct irq_host_ops xics_host_direct_ops = {
+static struct irq_host_ops xics_host_ops = {
         .match = xics_host_match,
-        .map = xics_host_map_direct,
-        .xlate = xics_host_xlate,
-};
-
-static struct irq_host_ops xics_host_lpar_ops = {
-        .match = xics_host_match,
-        .map = xics_host_map_lpar,
+        .map = xics_host_map,
         .xlate = xics_host_xlate,
 };
 
 static void __init xics_init_host(void)
 {
-        struct irq_host_ops *ops;
-
         if (firmware_has_feature(FW_FEATURE_LPAR))
-                ops = &xics_host_lpar_ops;
+                xics_irq_chip = &xics_pic_lpar;
         else
-                ops = &xics_host_direct_ops;
-        xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, ops,
+                xics_irq_chip = &xics_pic_direct;
+
+        xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
                                    XICS_IRQ_SPURIOUS);
         BUG_ON(xics_host == NULL);
         irq_set_default_host(xics_host);
@@ -655,52 +640,6 @@ static void __init xics_init_one_node(struct device_node *np,
         }
 }
 
-
-static void __init xics_setup_8259_cascade(void)
-{
-        struct device_node *np, *old, *found = NULL;
-        int cascade, naddr;
-        const u32 *addrp;
-        unsigned long intack = 0;
-
-        for_each_node_by_type(np, "interrupt-controller")
-                if (of_device_is_compatible(np, "chrp,iic")) {
-                        found = np;
-                        break;
-                }
-        if (found == NULL) {
-                printk(KERN_DEBUG "xics: no ISA interrupt controller\n");
-                return;
-        }
-        cascade = irq_of_parse_and_map(found, 0);
-        if (cascade == NO_IRQ) {
-                printk(KERN_ERR "xics: failed to map cascade interrupt");
-                return;
-        }
-        pr_debug("xics: cascade mapped to irq %d\n", cascade);
-
-        for (old = of_node_get(found); old != NULL ; old = np) {
-                np = of_get_parent(old);
-                of_node_put(old);
-                if (np == NULL)
-                        break;
-                if (strcmp(np->name, "pci") != 0)
-                        continue;
-                addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
-                if (addrp == NULL)
-                        continue;
-                naddr = of_n_addr_cells(np);
-                intack = addrp[naddr-1];
-                if (naddr > 1)
-                        intack |= ((unsigned long)addrp[naddr-2]) << 32;
-        }
-        if (intack)
-                printk(KERN_DEBUG "xics: PCI 8259 intack at 0x%016lx\n", intack);
-        i8259_init(found, intack);
-        of_node_put(found);
-        set_irq_chained_handler(cascade, pseries_8259_cascade);
-}
-
 void __init xics_init_IRQ(void)
 {
         struct device_node *np;
@@ -733,8 +672,6 @@ void __init xics_init_IRQ(void)
 
         xics_setup_cpu();
 
-        xics_setup_8259_cascade();
-
         ppc64_boot_msg(0x21, "XICS Done");
 }
 
diff --git a/arch/powerpc/platforms/pseries/xics.h b/arch/powerpc/platforms/pseries/xics.h
index c26bcff47b6d..1c5321ae8f2f 100644
--- a/arch/powerpc/platforms/pseries/xics.h
+++ b/arch/powerpc/platforms/pseries/xics.h
@@ -28,7 +28,4 @@ struct xics_ipi_struct {
 
 extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
 
-struct irq_desc;
-extern void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc);
-
 #endif /* _POWERPC_KERNEL_XICS_H */
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 15f3e8527d77..6d386d0071a0 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART)		+= dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)        += mmio_nvram.o
 obj-$(CONFIG_FSL_SOC)           += fsl_soc.o
 obj-$(CONFIG_FSL_PCI)           += fsl_pci.o
+obj-$(CONFIG_FSL_LBC)           += fsl_lbc.o
 obj-$(CONFIG_RAPIDIO)           += fsl_rio.o
 obj-$(CONFIG_TSI108_BRIDGE)     += tsi108_pci.o tsi108_dev.o
 obj-$(CONFIG_QUICC_ENGINE)      += qe_lib/
@@ -27,6 +28,7 @@ obj-$(CONFIG_PPC_INDIRECT_PCI)	+= indirect_pci.o
 obj-$(CONFIG_PPC_I8259)         += i8259.o
 obj-$(CONFIG_IPIC)              += ipic.o
 obj-$(CONFIG_4xx)               += uic.o
+obj-$(CONFIG_4xx_SOC)           += ppc4xx_soc.o
 obj-$(CONFIG_XILINX_VIRTEX)     += xilinx_intc.o
 obj-$(CONFIG_OF_RTC)            += of_rtc.o
 ifeq ($(CONFIG_PCI),y)
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index df8bd2b64796..58292a086c16 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -44,9 +44,6 @@
 
 #define CPM_MAP_SIZE    (0x4000)
 
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-static void m8xx_cpm_dpinit(void);
-#endif
 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
 immap_t __iomem *mpc8xx_immr;
 static cpic8xx_t __iomem *cpic_reg;
@@ -229,12 +226,7 @@ void __init cpm_reset(void)
         out_be32(&siu_conf->sc_sdcr, 1);
         immr_unmap(siu_conf);
 
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
         cpm_muram_init();
-#else
-        /* Reclaim the DP memory for our use. */
-        m8xx_cpm_dpinit();
-#endif
 }
 
 static DEFINE_SPINLOCK(cmd_lock);
@@ -257,7 +249,7 @@ int cpm_command(u32 command, u8 opcode)
                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
                         goto out;
 
-        printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__);
+        printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
         ret = -EIO;
 out:
         spin_unlock_irqrestore(&cmd_lock, flags);
@@ -293,110 +285,6 @@ cpm_setbrg(uint brg, uint rate)
                               CPM_BRG_EN | CPM_BRG_DIV16);
 }
 
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-/*
- * dpalloc / dpfree bits.
- */
-static spinlock_t cpm_dpmem_lock;
-/*
- * 16 blocks should be enough to satisfy all requests
- * until the memory subsystem goes up...
- */
-static rh_block_t cpm_boot_dpmem_rh_block[16];
-static rh_info_t cpm_dpmem_info;
-
-#define CPM_DPMEM_ALIGNMENT     8
-static u8 __iomem *dpram_vbase;
-static phys_addr_t dpram_pbase;
-
-static void m8xx_cpm_dpinit(void)
-{
-        spin_lock_init(&cpm_dpmem_lock);
-
-        dpram_vbase = cpmp->cp_dpmem;
-        dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
-
-        /* Initialize the info header */
-        rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
-                        sizeof(cpm_boot_dpmem_rh_block) /
-                        sizeof(cpm_boot_dpmem_rh_block[0]),
-                        cpm_boot_dpmem_rh_block);
-
-        /*
-         * Attach the usable dpmem area.
-         * XXX: This is actually crap.  CPM_DATAONLY_BASE and
-         * CPM_DATAONLY_SIZE are a subset of the available dparm.  It varies
-         * with the processor and the microcode patches applied / activated.
-         * But the following should be at least safe.
-         */
-        rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
-}
-
-/*
- * Allocate the requested size worth of DP memory.
- * This function returns an offset into the DPRAM area.
- * Use cpm_dpram_addr() to get the virtual address of the area.
- */
-unsigned long cpm_dpalloc(uint size, uint align)
-{
-        unsigned long start;
-        unsigned long flags;
-
-        spin_lock_irqsave(&cpm_dpmem_lock, flags);
-        cpm_dpmem_info.alignment = align;
-        start = rh_alloc(&cpm_dpmem_info, size, "commproc");
-        spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
-        return (uint)start;
-}
-EXPORT_SYMBOL(cpm_dpalloc);
-
-int cpm_dpfree(unsigned long offset)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&cpm_dpmem_lock, flags);
-        ret = rh_free(&cpm_dpmem_info, offset);
-        spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(cpm_dpfree);
-
-unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
-{
-        unsigned long start;
-        unsigned long flags;
-
-        spin_lock_irqsave(&cpm_dpmem_lock, flags);
-        cpm_dpmem_info.alignment = align;
-        start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
-        spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
-        return start;
-}
-EXPORT_SYMBOL(cpm_dpalloc_fixed);
-
-void cpm_dpdump(void)
-{
-        rh_dump(&cpm_dpmem_info);
-}
-EXPORT_SYMBOL(cpm_dpdump);
-
-void *cpm_dpram_addr(unsigned long offset)
-{
-        return (void *)(dpram_vbase + offset);
-}
-EXPORT_SYMBOL(cpm_dpram_addr);
-
-uint cpm_dpram_phys(u8 *addr)
-{
-        return (dpram_pbase + (uint)(addr - dpram_vbase));
-}
-EXPORT_SYMBOL(cpm_dpram_phys);
-#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
-
 struct cpm_ioport16 {
         __be16 dir, par, odr_sor, dat, intr;
         __be16 res[3];
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index dd066bb1d562..5a6c5dfc53ef 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -46,10 +46,6 @@
 
 #include <sysdev/fsl_soc.h>
 
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-static void cpm2_dpinit(void);
-#endif
-
 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
 
 /* We allocate this here because it is used almost exclusively for
@@ -71,15 +67,17 @@ void __init cpm2_reset(void)
 
         /* Reclaim the DP memory for our use.
          */
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
         cpm_muram_init();
-#else
-        cpm2_dpinit();
-#endif
 
         /* Tell everyone where the comm processor resides.
          */
         cpmp = &cpm2_immr->im_cpm;
+
+#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
+        /* Reset the CPM.
+         */
+        cpm_command(CPM_CR_RST, 0);
+#endif
 }
 
 static DEFINE_SPINLOCK(cmd_lock);
@@ -99,7 +97,7 @@ int cpm_command(u32 command, u8 opcode)
                 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
                         goto out;
 
-        printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__);
+        printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
         ret = -EIO;
 out:
         spin_unlock_irqrestore(&cmd_lock, flags);
@@ -347,95 +345,6 @@ int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
         return ret;
 }
 
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-/*
- * dpalloc / dpfree bits.
- */
-static spinlock_t cpm_dpmem_lock;
-/* 16 blocks should be enough to satisfy all requests
- * until the memory subsystem goes up... */
-static rh_block_t cpm_boot_dpmem_rh_block[16];
-static rh_info_t cpm_dpmem_info;
-static u8 __iomem *im_dprambase;
-
-static void cpm2_dpinit(void)
-{
-        spin_lock_init(&cpm_dpmem_lock);
-
-        /* initialize the info header */
-        rh_init(&cpm_dpmem_info, 1,
-                        sizeof(cpm_boot_dpmem_rh_block) /
-                        sizeof(cpm_boot_dpmem_rh_block[0]),
-                        cpm_boot_dpmem_rh_block);
-
-        im_dprambase = cpm2_immr;
-
-        /* Attach the usable dpmem area */
-        /* XXX: This is actually crap. CPM_DATAONLY_BASE and
-         * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
-         * varies with the processor and the microcode patches activated.
-         * But the following should be at least safe.
-         */
-        rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
-}
-
-/* This function returns an index into the DPRAM area.
- */
-unsigned long cpm_dpalloc(uint size, uint align)
-{
-        unsigned long start;
-        unsigned long flags;
-
-        spin_lock_irqsave(&cpm_dpmem_lock, flags);
-        cpm_dpmem_info.alignment = align;
-        start = rh_alloc(&cpm_dpmem_info, size, "commproc");
-        spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
-        return (uint)start;
-}
-EXPORT_SYMBOL(cpm_dpalloc);
-
-int cpm_dpfree(unsigned long offset)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&cpm_dpmem_lock, flags);
-        ret = rh_free(&cpm_dpmem_info, offset);
-        spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(cpm_dpfree);
-
-/* not sure if this is ever needed */
-unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
-{
-        unsigned long start;
-        unsigned long flags;
-
-        spin_lock_irqsave(&cpm_dpmem_lock, flags);
-        cpm_dpmem_info.alignment = align;
-        start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
-        spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
-        return start;
-}
-EXPORT_SYMBOL(cpm_dpalloc_fixed);
-
-void cpm_dpdump(void)
-{
-        rh_dump(&cpm_dpmem_info);
-}
-EXPORT_SYMBOL(cpm_dpdump);
-
-void *cpm_dpram_addr(unsigned long offset)
-{
-        return (void *)(im_dprambase + offset);
-}
-EXPORT_SYMBOL(cpm_dpram_addr);
-#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
-
 struct cpm2_ioports {
         u32 dir, par, sor, odr, dat;
         u32 res[3];
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 165981c87786..cb7df2dce44f 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -58,7 +58,6 @@ void __init udbg_init_cpm(void)
 }
 #endif
 
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
 static spinlock_t cpm_muram_lock;
 static rh_block_t cpm_boot_muram_rh_block[16];
 static rh_info_t cpm_muram_info;
@@ -199,5 +198,3 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
         return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
 }
 EXPORT_SYMBOL(cpm_muram_dma);
-
-#endif /* CONFIG_PPC_CPM_NEW_BINDING */
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index e0e24b01e3a6..005c2ecf976f 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -37,6 +37,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/vmalloc.h>
 #include <linux/suspend.h>
+#include <linux/lmb.h>
 #include <asm/io.h>
 #include <asm/prom.h>
 #include <asm/iommu.h>
@@ -44,7 +45,6 @@
 #include <asm/machdep.h>
 #include <asm/abs_addr.h>
 #include <asm/cacheflush.h>
-#include <asm/lmb.h>
 #include <asm/ppc-pci.h>
 
 #include "dart.h"
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
new file mode 100644
index 000000000000..422c8faef593
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -0,0 +1,129 @@
+/*
+ * Freescale LBC and UPM routines.
+ *
+ * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <asm/fsl_lbc.h>
+
+spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
+
+struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+EXPORT_SYMBOL(fsl_lbc_regs);
+
+static char __initdata *compat_lbc[] = {
+        "fsl,pq2-localbus",
+        "fsl,pq2pro-localbus",
+        "fsl,pq3-localbus",
+        "fsl,elbc",
+};
+
+static int __init fsl_lbc_init(void)
+{
+        struct device_node *lbus;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
+                lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
+                if (lbus)
+                        goto found;
+        }
+        return -ENODEV;
+
+found:
+        fsl_lbc_regs = of_iomap(lbus, 0);
+        of_node_put(lbus);
+        if (!fsl_lbc_regs)
+                return -ENOMEM;
+        return 0;
+}
+arch_initcall(fsl_lbc_init);
+
+/**
+ * fsl_lbc_find - find Localbus bank
+ * @addr_base:  base address of the memory bank
+ *
+ * This function walks LBC banks comparing "Base address" field of the BR
+ * registers with the supplied addr_base argument. When bases match this
+ * function returns bank number (starting with 0), otherwise it returns
+ * appropriate errno value.
+ */
+int fsl_lbc_find(phys_addr_t addr_base)
+{
+        int i;
+
+        if (!fsl_lbc_regs)
+                return -ENODEV;
+
+        for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
+                __be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
+                __be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
+
+                if (br & BR_V && (br & or & BR_BA) == addr_base)
+                        return i;
+        }
+
+        return -ENOENT;
+}
+EXPORT_SYMBOL(fsl_lbc_find);
+
+/**
+ * fsl_upm_find - find pre-programmed UPM via base address
+ * @addr_base:  base address of the memory bank controlled by the UPM
+ * @upm:        pointer to the allocated fsl_upm structure
+ *
+ * This function fills fsl_upm structure so you can use it with the rest of
+ * UPM API. On success this function returns 0, otherwise it returns
+ * appropriate errno value.
+ */
+int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
+{
+        int bank;
+        __be32 br;
+
+        bank = fsl_lbc_find(addr_base);
+        if (bank < 0)
+                return bank;
+
+        br = in_be32(&fsl_lbc_regs->bank[bank].br);
+
+        switch (br & BR_MSEL) {
+        case BR_MS_UPMA:
+                upm->mxmr = &fsl_lbc_regs->mamr;
+                break;
+        case BR_MS_UPMB:
+                upm->mxmr = &fsl_lbc_regs->mbmr;
+                break;
+        case BR_MS_UPMC:
+                upm->mxmr = &fsl_lbc_regs->mcmr;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (br & BR_PS) {
+        case BR_PS_8:
+                upm->width = 8;
+                break;
+        case BR_PS_16:
+                upm->width = 16;
+                break;
+        case BR_PS_32:
+                upm->width = 32;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(fsl_upm_find);
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 3581416905ea..5c1b246aaccc 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -75,6 +75,33 @@ phys_addr_t get_immrbase(void)
 
 EXPORT_SYMBOL(get_immrbase);
 
+static u32 sysfreq = -1;
+
+u32 fsl_get_sys_freq(void)
+{
+        struct device_node *soc;
+        const u32 *prop;
+        int size;
+
+        if (sysfreq != -1)
+                return sysfreq;
+
+        soc = of_find_node_by_type(NULL, "soc");
+        if (!soc)
+                return -1;
+
+        prop = of_get_property(soc, "clock-frequency", &size);
+        if (!prop || size != sizeof(*prop) || *prop == 0)
+                prop = of_get_property(soc, "bus-frequency", &size);
+
+        if (prop && size == sizeof(*prop))
+                sysfreq = *prop;
+
+        of_node_put(soc);
+        return sysfreq;
+}
+EXPORT_SYMBOL(fsl_get_sys_freq);
+
 #if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
 
 static u32 brgfreq = -1;
@@ -517,9 +544,9 @@ arch_initcall(fsl_i2c_of_init);
 static int __init mpc83xx_wdt_init(void)
 {
         struct resource r;
-        struct device_node *soc, *np;
+        struct device_node *np;
         struct platform_device *dev;
-        const unsigned int *freq;
+        u32 freq = fsl_get_sys_freq();
         int ret;
 
         np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
@@ -529,19 +556,6 @@ static int __init mpc83xx_wdt_init(void)
                 goto nodev;
         }
 
-        soc = of_find_node_by_type(NULL, "soc");
-
-        if (!soc) {
-                ret = -ENODEV;
-                goto nosoc;
-        }
-
-        freq = of_get_property(soc, "bus-frequency", NULL);
-        if (!freq) {
-                ret = -ENODEV;
-                goto err;
-        }
-
         memset(&r, 0, sizeof(r));
 
         ret = of_address_to_resource(np, 0, &r);
@@ -554,20 +568,16 @@ static int __init mpc83xx_wdt_init(void)
                 goto err;
         }
 
-        ret = platform_device_add_data(dev, freq, sizeof(int));
+        ret = platform_device_add_data(dev, &freq, sizeof(freq));
         if (ret)
                 goto unreg;
 
-        of_node_put(soc);
         of_node_put(np);
-
         return 0;
 
 unreg:
         platform_device_unregister(dev);
 err:
-        of_node_put(soc);
-nosoc:
         of_node_put(np);
 nodev:
         return ret;
@@ -736,547 +746,6 @@ err:
 
 arch_initcall(fsl_usb_of_init);
 
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-#ifdef CONFIG_CPM2
-
-extern void init_scc_ioports(struct fs_uart_platform_info*);
-
-static const char fcc_regs[] = "fcc_regs";
-static const char fcc_regs_c[] = "fcc_regs_c";
-static const char fcc_pram[] = "fcc_pram";
-static char bus_id[9][BUS_ID_SIZE];
-
-static int __init fs_enet_of_init(void)
-{
-        struct device_node *np;
-        unsigned int i;
-        struct platform_device *fs_enet_dev;
-        struct resource res;
-        int ret;
-
-        for (np = NULL, i = 0;
-             (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
-             i++) {
-                struct resource r[4];
-                struct device_node *phy, *mdio;
-                struct fs_platform_info fs_enet_data;
-                const unsigned int *id, *phy_addr, *phy_irq;
-                const void *mac_addr;
-                const phandle *ph;
-                const char *model;
-
-                memset(r, 0, sizeof(r));
-                memset(&fs_enet_data, 0, sizeof(fs_enet_data));
-
-                ret = of_address_to_resource(np, 0, &r[0]);
-                if (ret)
-                        goto err;
-                r[0].name = fcc_regs;
-
-                ret = of_address_to_resource(np, 1, &r[1]);
-                if (ret)
-                        goto err;
-                r[1].name = fcc_pram;
-
-                ret = of_address_to_resource(np, 2, &r[2]);
-                if (ret)
-                        goto err;
-                r[2].name = fcc_regs_c;
-                fs_enet_data.fcc_regs_c = r[2].start;
-
-                of_irq_to_resource(np, 0, &r[3]);
-
-                fs_enet_dev =
-                    platform_device_register_simple("fsl-cpm-fcc", i, &r[0], 4);
-
-                if (IS_ERR(fs_enet_dev)) {
-                        ret = PTR_ERR(fs_enet_dev);
-                        goto err;
-                }
-
-                model = of_get_property(np, "model", NULL);
-                if (model == NULL) {
-                        ret = -ENODEV;
-                        goto unreg;
-                }
-
-                mac_addr = of_get_mac_address(np);
-                if (mac_addr)
-                        memcpy(fs_enet_data.macaddr, mac_addr, 6);
-
-                ph = of_get_property(np, "phy-handle", NULL);
-                phy = of_find_node_by_phandle(*ph);
-
-                if (phy == NULL) {
-                        ret = -ENODEV;
-                        goto unreg;
-                }
-
-                phy_addr = of_get_property(phy, "reg", NULL);
-                fs_enet_data.phy_addr = *phy_addr;
-
-                phy_irq = of_get_property(phy, "interrupts", NULL);
-
-                id = of_get_property(np, "device-id", NULL);
-                fs_enet_data.fs_no = *id;
-                strcpy(fs_enet_data.fs_type, model);
-
-                mdio = of_get_parent(phy);
-                ret = of_address_to_resource(mdio, 0, &res);
-                if (ret) {
-                        of_node_put(phy);
-                        of_node_put(mdio);
-                        goto unreg;
-                }
-
-                fs_enet_data.clk_rx = *((u32 *)of_get_property(np,
-                                                "rx-clock", NULL));
-                fs_enet_data.clk_tx = *((u32 *)of_get_property(np,
-                                                "tx-clock", NULL));
-
-                if (strstr(model, "FCC")) {
-                        int fcc_index = *id - 1;
-                        const unsigned char *mdio_bb_prop;
-
-                        fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
-                        fs_enet_data.rx_ring = 32;
-                        fs_enet_data.tx_ring = 32;
-                        fs_enet_data.rx_copybreak = 240;
-                        fs_enet_data.use_napi = 0;
-                        fs_enet_data.napi_weight = 17;
-                        fs_enet_data.mem_offset = FCC_MEM_OFFSET(fcc_index);
-                        fs_enet_data.cp_page = CPM_CR_FCC_PAGE(fcc_index);
-                        fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
-
-                        snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
-                                                        (u32)res.start, fs_enet_data.phy_addr);
-                        fs_enet_data.bus_id = (char*)&bus_id[(*id)];
-                        fs_enet_data.init_ioports = init_fcc_ioports;
-
-                        mdio_bb_prop = of_get_property(phy, "bitbang", NULL);
-                        if (mdio_bb_prop) {
-                                struct platform_device *fs_enet_mdio_bb_dev;
-                                struct fs_mii_bb_platform_info fs_enet_mdio_bb_data;
-
-                                fs_enet_mdio_bb_dev =
-                                        platform_device_register_simple("fsl-bb-mdio",
-                                                        i, NULL, 0);
-                                memset(&fs_enet_mdio_bb_data, 0,
-                                                sizeof(struct fs_mii_bb_platform_info));
-                                fs_enet_mdio_bb_data.mdio_dat.bit =
-                                        mdio_bb_prop[0];
-                                fs_enet_mdio_bb_data.mdio_dir.bit =
-                                        mdio_bb_prop[1];
-                                fs_enet_mdio_bb_data.mdc_dat.bit =
-                                        mdio_bb_prop[2];
-                                fs_enet_mdio_bb_data.mdio_port =
-                                        mdio_bb_prop[3];
-                                fs_enet_mdio_bb_data.mdc_port =
-                                        mdio_bb_prop[4];
-                                fs_enet_mdio_bb_data.delay =
-                                        mdio_bb_prop[5];
-
-                                fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
-                                fs_enet_mdio_bb_data.irq[1] = -1;
-                                fs_enet_mdio_bb_data.irq[2] = -1;
-                                fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
-                                fs_enet_mdio_bb_data.irq[31] = -1;
-
-                                fs_enet_mdio_bb_data.mdio_dat.offset =
-                                        (u32)&cpm2_immr->im_ioport.iop_pdatc;
-                                fs_enet_mdio_bb_data.mdio_dir.offset =
-                                        (u32)&cpm2_immr->im_ioport.iop_pdirc;
-                                fs_enet_mdio_bb_data.mdc_dat.offset =
-                                        (u32)&cpm2_immr->im_ioport.iop_pdatc;
-
-                                ret = platform_device_add_data(
-                                                fs_enet_mdio_bb_dev,
-                                                &fs_enet_mdio_bb_data,
-                                                sizeof(struct fs_mii_bb_platform_info));
-                                if (ret)
-                                        goto unreg;
-                        }
-
-                        of_node_put(phy);
-                        of_node_put(mdio);
-
-                        ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
-                                                     sizeof(struct
-                                                            fs_platform_info));
-                        if (ret)
-                                goto unreg;
-                }
-        }
-        return 0;
-
-unreg:
-        platform_device_unregister(fs_enet_dev);
-err:
-        return ret;
-}
-
-arch_initcall(fs_enet_of_init);
-
-static const char scc_regs[] = "regs";
-static const char scc_pram[] = "pram";
-
-static int __init cpm_uart_of_init(void)
-{
-        struct device_node *np;
-        unsigned int i;
-        struct platform_device *cpm_uart_dev;
-        int ret;
-
-        for (np = NULL, i = 0;
-             (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
-             i++) {
-                struct resource r[3];
-                struct fs_uart_platform_info cpm_uart_data;
-                const int *id;
-                const char *model;
-
-                memset(r, 0, sizeof(r));
-                memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
-
-                ret = of_address_to_resource(np, 0, &r[0]);
-                if (ret)
-                        goto err;
-
-                r[0].name = scc_regs;
-
-                ret = of_address_to_resource(np, 1, &r[1]);
-                if (ret)
-                        goto err;
-                r[1].name = scc_pram;
-
-                of_irq_to_resource(np, 0, &r[2]);
-
-                cpm_uart_dev =
-                    platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
-
-                if (IS_ERR(cpm_uart_dev)) {
-                        ret = PTR_ERR(cpm_uart_dev);
-                        goto err;
-                }
-
-                id = of_get_property(np, "device-id", NULL);
-                cpm_uart_data.fs_no = *id;
-
-                model = of_get_property(np, "model", NULL);
-                strcpy(cpm_uart_data.fs_type, model);
-
-                cpm_uart_data.uart_clk = ppc_proc_freq;
-
-                cpm_uart_data.tx_num_fifo = 4;
-                cpm_uart_data.tx_buf_size = 32;
-                cpm_uart_data.rx_num_fifo = 4;
-                cpm_uart_data.rx_buf_size = 32;
-                cpm_uart_data.clk_rx = *((u32 *)of_get_property(np,
-                                                "rx-clock", NULL));
-                cpm_uart_data.clk_tx = *((u32 *)of_get_property(np,
-                                                "tx-clock", NULL));
-
-                ret =
-                    platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
-                                             sizeof(struct
-                                                    fs_uart_platform_info));
-                if (ret)
-                        goto unreg;
-        }
-
-        return 0;
-
-unreg:
-        platform_device_unregister(cpm_uart_dev);
-err:
-        return ret;
-}
-
-arch_initcall(cpm_uart_of_init);
-#endif /* CONFIG_CPM2 */
-
-#ifdef CONFIG_8xx
-
-extern void init_scc_ioports(struct fs_platform_info*);
-extern int platform_device_skip(const char *model, int id);
-
-static int __init fs_enet_mdio_of_init(void)
-{
-        struct device_node *np;
-        unsigned int i;
-        struct platform_device *mdio_dev;
-        struct resource res;
-        int ret;
-
-        for (np = NULL, i = 0;
-             (np = of_find_compatible_node(np, "mdio", "fs_enet")) != NULL;
-             i++) {
-                struct fs_mii_fec_platform_info mdio_data;
-
-                memset(&res, 0, sizeof(res));
-                memset(&mdio_data, 0, sizeof(mdio_data));
-
-                ret = of_address_to_resource(np, 0, &res);
-                if (ret)
-                        goto err;
-
-                mdio_dev =
-                    platform_device_register_simple("fsl-cpm-fec-mdio",
-                                                    res.start, &res, 1);
-                if (IS_ERR(mdio_dev)) {
-                        ret = PTR_ERR(mdio_dev);
-                        goto err;
-                }
-
-                mdio_data.mii_speed = ((((ppc_proc_freq + 4999999) / 2500000) / 2) & 0x3F) << 1;
-
-                ret =
-                    platform_device_add_data(mdio_dev, &mdio_data,
-                                             sizeof(struct fs_mii_fec_platform_info));
-                if (ret)
-                        goto unreg;
-        }
-        return 0;
-
-unreg:
-        platform_device_unregister(mdio_dev);
-err:
-        return ret;
-}
-
-arch_initcall(fs_enet_mdio_of_init);
-
-static const char *enet_regs = "regs";
-static const char *enet_pram = "pram";
-static const char *enet_irq = "interrupt";
-static char bus_id[9][BUS_ID_SIZE];
-
-static int __init fs_enet_of_init(void)
-{
-        struct device_node *np;
-        unsigned int i;
-        struct platform_device *fs_enet_dev = NULL;
-        struct resource res;
-        int ret;
-
-        for (np = NULL, i = 0;
-             (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
-             i++) {
-                struct resource r[4];
-                struct device_node *phy = NULL, *mdio = NULL;
-                struct fs_platform_info fs_enet_data;
-                const unsigned int *id;
-                const unsigned int *phy_addr;
-                const void *mac_addr;
-                const phandle *ph;
-                const char *model;
-
-                memset(r, 0, sizeof(r));
-                memset(&fs_enet_data, 0, sizeof(fs_enet_data));
-
-                model = of_get_property(np, "model", NULL);
-                if (model == NULL) {
-                        ret = -ENODEV;
-                        goto unreg;
-                }
-
-                id = of_get_property(np, "device-id", NULL);
-                fs_enet_data.fs_no = *id;
-
-                if (platform_device_skip(model, *id))
-                        continue;
-
-                ret = of_address_to_resource(np, 0, &r[0]);
-                if (ret)
-                        goto err;
-                r[0].name = enet_regs;
-
-                mac_addr = of_get_mac_address(np);
-                if (mac_addr)
-                        memcpy(fs_enet_data.macaddr, mac_addr, 6);
-
-                ph = of_get_property(np, "phy-handle", NULL);
-                if (ph != NULL)
-                        phy = of_find_node_by_phandle(*ph);
-
-                if (phy != NULL) {
-                        phy_addr = of_get_property(phy, "reg", NULL);
-                        fs_enet_data.phy_addr = *phy_addr;
-                        fs_enet_data.has_phy = 1;
-
-                        mdio = of_get_parent(phy);
-                        ret = of_address_to_resource(mdio, 0, &res);
-                        if (ret) {
-                                of_node_put(phy);
-                                of_node_put(mdio);
-                                goto unreg;
-                        }
-                }
-
-                model = of_get_property(np, "model", NULL);
-                strcpy(fs_enet_data.fs_type, model);
-
-                if (strstr(model, "FEC")) {
-                        r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
-                        r[1].flags = IORESOURCE_IRQ;
-                        r[1].name = enet_irq;
-
-                        fs_enet_dev =
-                                    platform_device_register_simple("fsl-cpm-fec", i, &r[0], 2);
-
-                        if (IS_ERR(fs_enet_dev)) {
-                                ret = PTR_ERR(fs_enet_dev);
-                                goto err;
-                        }
-
-                        fs_enet_data.rx_ring = 128;
-                        fs_enet_data.tx_ring = 16;
-                        fs_enet_data.rx_copybreak = 240;
-                        fs_enet_data.use_napi = 1;
-                        fs_enet_data.napi_weight = 17;
-
-                        snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%x:%02x",
-                                                        (u32)res.start, fs_enet_data.phy_addr);
-                        fs_enet_data.bus_id = (char*)&bus_id[i];
-                        fs_enet_data.init_ioports = init_fec_ioports;
-                }
-                if (strstr(model, "SCC")) {
-                        ret = of_address_to_resource(np, 1, &r[1]);
-                        if (ret)
-                                goto err;
-                        r[1].name = enet_pram;
-
-                        r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
-                        r[2].flags = IORESOURCE_IRQ;
-                        r[2].name = enet_irq;
-
-                        fs_enet_dev =
-                                    platform_device_register_simple("fsl-cpm-scc", i, &r[0], 3);
-
-                        if (IS_ERR(fs_enet_dev)) {
-                                ret = PTR_ERR(fs_enet_dev);
-                                goto err;
-                        }
-
-                        fs_enet_data.rx_ring = 64;
-                        fs_enet_data.tx_ring = 8;
-                        fs_enet_data.rx_copybreak = 240;
-                        fs_enet_data.use_napi = 1;
-                        fs_enet_data.napi_weight = 17;
-
-                        snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%s", "fixed@10:1");
-                        fs_enet_data.bus_id = (char*)&bus_id[i];
-                        fs_enet_data.init_ioports = init_scc_ioports;
-                }
-
-                of_node_put(phy);
-                of_node_put(mdio);
-
-                ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
-                                             sizeof(struct
-                                                    fs_platform_info));
-                if (ret)
-                        goto unreg;
-        }
-        return 0;
-
-unreg:
-        platform_device_unregister(fs_enet_dev);
-err:
-        return ret;
-}
-
-arch_initcall(fs_enet_of_init);
-
-static int __init fsl_pcmcia_of_init(void)
-{
-        struct device_node *np;
-        /*
-         * Register all the devices which type is "pcmcia"
-         */
-        for_each_compatible_node(np, "pcmcia", "fsl,pq-pcmcia")
-                of_platform_device_create(np, "m8xx-pcmcia", NULL);
-        return 0;
-}
-
-arch_initcall(fsl_pcmcia_of_init);
-
-static const char *smc_regs = "regs";
-static const char *smc_pram = "pram";
-
-static int __init cpm_smc_uart_of_init(void)
-{
-        struct device_node *np;
-        unsigned int i;
-        struct platform_device *cpm_uart_dev;
-        int ret;
-
-        for (np = NULL, i = 0;
-             (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
-             i++) {
-                struct resource r[3];
-                struct fs_uart_platform_info cpm_uart_data;
-                const int *id;
-                const char *model;
-
-                memset(r, 0, sizeof(r));
-                memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
-
-                ret = of_address_to_resource(np, 0, &r[0]);
-                if (ret)
-                        goto err;
-
-                r[0].name = smc_regs;
-
-                ret = of_address_to_resource(np, 1, &r[1]);
-                if (ret)
-                        goto err;
-                r[1].name = smc_pram;
-
-                r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
-                r[2].flags = IORESOURCE_IRQ;
-
-                cpm_uart_dev =
-                    platform_device_register_simple("fsl-cpm-smc:uart", i, &r[0], 3);
-
-                if (IS_ERR(cpm_uart_dev)) {
-                        ret = PTR_ERR(cpm_uart_dev);
-                        goto err;
-                }
-
-                model = of_get_property(np, "model", NULL);
-                strcpy(cpm_uart_data.fs_type, model);
-
-                id = of_get_property(np, "device-id", NULL);
-                cpm_uart_data.fs_no = *id;
-                cpm_uart_data.uart_clk = ppc_proc_freq;
-
-                cpm_uart_data.tx_num_fifo = 4;
-                cpm_uart_data.tx_buf_size = 32;
-                cpm_uart_data.rx_num_fifo = 4;
-                cpm_uart_data.rx_buf_size = 32;
-
-                ret =
-                    platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
-                                             sizeof(struct
-                                                    fs_uart_platform_info));
-                if (ret)
-                        goto unreg;
-        }
-
-        return 0;
-
-unreg:
-        platform_device_unregister(cpm_uart_dev);
-err:
-        return ret;
-}
-
-arch_initcall(cpm_smc_uart_of_init);
-
-#endif /* CONFIG_8xx */
-#endif /* CONFIG_PPC_CPM_NEW_BINDING */
-
 static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
                                    struct spi_board_info *board_infos,
                                    unsigned int num_board_infos,
@@ -1372,25 +841,9 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
         sysclk = get_brgfreq();
 #endif
         if (sysclk == -1) {
-                struct device_node *np;
-                const u32 *freq;
-                int size;
-
-                np = of_find_node_by_type(NULL, "soc");
-                if (!np)
+                sysclk = fsl_get_sys_freq();
+                if (sysclk == -1)
                         return -ENODEV;
-
-                freq = of_get_property(np, "clock-frequency", &size);
-                if (!freq || size != sizeof(*freq) || *freq == 0) {
-                        freq = of_get_property(np, "bus-frequency", &size);
-                        if (!freq || size != sizeof(*freq) || *freq == 0) {
-                                of_node_put(np);
-                                return -ENODEV;
-                        }
-                }
-
-                sysclk = *freq;
-                of_node_put(np);
         }
 
         ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 63e7db30a4cd..74c4a9657b33 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -7,6 +7,7 @@
 extern phys_addr_t get_immrbase(void);
 extern u32 get_brgfreq(void);
 extern u32 get_baudrate(void);
+extern u32 fsl_get_sys_freq(void);
 
 struct spi_board_info;
 
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6ffdda244bb1..8619f2a3f1f6 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -175,13 +175,16 @@ static inline void _mpic_write(enum mpic_reg_type type,
         switch(type) {
 #ifdef CONFIG_PPC_DCR
         case mpic_access_dcr:
-                return dcr_write(rb->dhost, reg, value);
+                dcr_write(rb->dhost, reg, value);
+                break;
 #endif
         case mpic_access_mmio_be:
-                return out_be32(rb->base + (reg >> 2), value);
+                out_be32(rb->base + (reg >> 2), value);
+                break;
         case mpic_access_mmio_le:
         default:
-                return out_le32(rb->base + (reg >> 2), value);
+                out_le32(rb->base + (reg >> 2), value);
+                break;
         }
 }
 
@@ -1000,7 +1003,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
                                 const char *name)
 {
         struct mpic     *mpic;
-        u32             reg;
+        u32             greg_feature;
         const char      *vers;
         int             i;
         int             intvec_top;
@@ -1064,7 +1067,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
 
         /* Look for protected sources */
         if (node) {
-                unsigned int psize, bits, mapsize;
+                int psize;
+                unsigned int bits, mapsize;
                 const u32 *psrc =
                         of_get_property(node, "protected-sources", &psize);
                 if (psrc) {
@@ -1107,8 +1111,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
          * in, try to obtain one
          */
         if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
-                const u32 *reg;
-                reg = of_get_property(node, "reg", NULL);
+                const u32 *reg = of_get_property(node, "reg", NULL);
                 BUG_ON(reg == NULL);
                 paddr = of_translate_address(node, reg);
                 BUG_ON(paddr == OF_BAD_ADDR);
@@ -1137,12 +1140,13 @@ struct mpic * __init mpic_alloc(struct device_node *node,
          * MPICs, num sources as well. On ISU MPICs, sources are counted
          * as ISUs are added
          */
-        reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
-        mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
+        greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
+        mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
         if (isu_size == 0)
-                mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
-                                     >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
+                mpic->num_sources =
+                        ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
+                         >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
 
         /* Map the per-CPU registers */
         for (i = 0; i < mpic->num_cpus; i++) {
@@ -1161,7 +1165,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
 
         /* Display version */
-        switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
+        switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
         case 1:
                 vers = "1.0";
                 break;
@@ -1321,7 +1325,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable)
 
 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
 {
-        int is_ipi;
+        unsigned int is_ipi;
         struct mpic *mpic = mpic_find(irq, &is_ipi);
         unsigned int src = mpic_irq_to_hw(irq);
         unsigned long flags;
@@ -1344,7 +1348,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
 
 unsigned int mpic_irq_get_priority(unsigned int irq)
 {
-        int is_ipi;
+        unsigned int is_ipi;
         struct mpic *mpic = mpic_find(irq, &is_ipi);
         unsigned int src = mpic_irq_to_hw(irq);
         unsigned long flags;
@@ -1406,11 +1410,6 @@ void mpic_cpu_set_priority(int prio)
         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
 }
 
-/*
- * XXX: someone who knows mpic should check this.
- * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
- * or can we reset the mpic in the new kernel?
- */
 void mpic_teardown_this_cpu(int secondary)
 {
         struct mpic *mpic = mpic_primary;
@@ -1430,6 +1429,10 @@ void mpic_teardown_this_cpu(int secondary)
 
         /* Set current processor priority to max */
         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
+        /* We need to EOI the IPI since not all platforms reset the MPIC
+         * on boot and new interrupts wouldn't get delivered otherwise.
+         */
+        mpic_eoi(mpic);
 
         spin_unlock_irqrestore(&mpic_lock, flags);
 }
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index efda0028909d..047b31027fa6 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -127,7 +127,7 @@ static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id)
         if (err)
                 return err;
 
-        prop = of_get_property(np, "block-index", NULL);
+        prop = of_get_property(np, "cell-index", NULL);
         if (!prop)
                 return -ENODEV;
         port_number = *(int *)prop;
@@ -136,6 +136,7 @@ static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id)
 
         pdata.cache_mgmt = 1; /* All current revs need this set */
 
+        pdata.max_idle = 40; /* default */
         prop = of_get_property(np, "max_idle", NULL);
         if (prop)
                 pdata.max_idle = *prop;
@@ -205,30 +206,24 @@ error:
 /*
  * Create mv64x60_eth platform devices
  */
-static int __init eth_register_shared_pdev(struct device_node *np)
+static struct platform_device * __init mv64x60_eth_register_shared_pdev(
+                                                struct device_node *np, int id)
 {
         struct platform_device *pdev;
         struct resource r[1];
         int err;
 
-        np = of_get_parent(np);
-        if (!np)
-                return -ENODEV;
-
         err = of_address_to_resource(np, 0, &r[0]);
-        of_node_put(np);
         if (err)
-                return err;
+                return ERR_PTR(err);
 
-        pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, 0,
+        pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, id,
                                                r, 1);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
-
-        return 0;
+        return pdev;
 }
 
-static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
+static int __init mv64x60_eth_device_setup(struct device_node *np, int id,
+                                           struct platform_device *shared_pdev)
 {
         struct resource r[1];
         struct mv643xx_eth_platform_data pdata;
@@ -239,16 +234,12 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
         const phandle *ph;
         int err;
 
-        /* only register the shared platform device the first time through */
-        if (id == 0 && (err = eth_register_shared_pdev(np)))
-                return err;
-
         memset(r, 0, sizeof(r));
         of_irq_to_resource(np, 0, &r[0]);
 
         memset(&pdata, 0, sizeof(pdata));
 
-        prop = of_get_property(np, "block-index", NULL);
+        prop = of_get_property(np, "reg", NULL);
         if (!prop)
                 return -ENODEV;
         pdata.port_number = *prop;
@@ -301,7 +292,7 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
 
         of_node_put(phy);
 
-        pdev = platform_device_alloc(MV643XX_ETH_NAME, pdata.port_number);
+        pdev = platform_device_alloc(MV643XX_ETH_NAME, id);
         if (!pdev)
                 return -ENOMEM;
 
@@ -345,21 +336,19 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
 
         memset(&pdata, 0, sizeof(pdata));
 
+        pdata.freq_m = 8;       /* default */
         prop = of_get_property(np, "freq_m", NULL);
         if (!prop)
                 return -ENODEV;
         pdata.freq_m = *prop;
 
+        pdata.freq_m = 3;       /* default */
         prop = of_get_property(np, "freq_n", NULL);
         if (!prop)
                 return -ENODEV;
         pdata.freq_n = *prop;
 
-        prop = of_get_property(np, "timeout", NULL);
-        if (prop)
-                pdata.timeout = *prop;
-        else
-                pdata.timeout = 1000;   /* 1 second */
+        pdata.timeout = 1000;                           /* default: 1 second */
 
         pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id);
         if (!pdev)
@@ -401,10 +390,7 @@ static int __init mv64x60_wdt_device_setup(struct device_node *np, int id)
 
         memset(&pdata, 0, sizeof(pdata));
 
-        prop = of_get_property(np, "timeout", NULL);
-        if (!prop)
-                return -ENODEV;
-        pdata.timeout = *prop;
+        pdata.timeout = 10;                     /* Default: 10 seconds */
 
         np = of_get_parent(np);
         if (!np)
@@ -441,27 +427,43 @@ error:
 
 static int __init mv64x60_device_setup(void)
 {
-        struct device_node *np = NULL;
-        int id;
+        struct device_node *np, *np2;
+        struct platform_device *pdev;
+        int id, id2;
         int err;
 
         id = 0;
-        for_each_compatible_node(np, "serial", "marvell,mpsc")
+        for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc")
                 if ((err = mv64x60_mpsc_device_setup(np, id++)))
                         goto error;
 
         id = 0;
-        for_each_compatible_node(np, "network", "marvell,mv64x60-eth")
-                if ((err = mv64x60_eth_device_setup(np, id++)))
+        id2 = 0;
+        for_each_compatible_node(np, NULL, "marvell,mv64360-eth-group") {
+                pdev = mv64x60_eth_register_shared_pdev(np, id++);
+                if (IS_ERR(pdev)) {
+                        err = PTR_ERR(pdev);
                         goto error;
+                }
+                for_each_child_of_node(np, np2) {
+                        if (!of_device_is_compatible(np2,
+                                        "marvell,mv64360-eth"))
+                                continue;
+                        err = mv64x60_eth_device_setup(np2, id2++, pdev);
+                        if (err) {
+                                of_node_put(np2);
+                                goto error;
+                        }
+                }
+        }
 
         id = 0;
-        for_each_compatible_node(np, "i2c", "marvell,mv64x60-i2c")
+        for_each_compatible_node(np, "i2c", "marvell,mv64360-i2c")
                 if ((err = mv64x60_i2c_device_setup(np, id++)))
                         goto error;
 
         /* support up to one watchdog timer */
-        np = of_find_compatible_node(np, NULL, "marvell,mv64x60-wdt");
+        np = of_find_compatible_node(np, NULL, "marvell,mv64360-wdt");
         if (np) {
                 if ((err = mv64x60_wdt_device_setup(np, id)))
                         goto error;
@@ -489,10 +491,10 @@ static int __init mv64x60_add_mpsc_console(void)
         if (!np)
                 goto not_mpsc;
 
-        if (!of_device_is_compatible(np, "marvell,mpsc"))
+        if (!of_device_is_compatible(np, "marvell,mv64360-mpsc"))
                 goto not_mpsc;
 
-        prop = of_get_property(np, "block-index", NULL);
+        prop = of_get_property(np, "cell-index", NULL);
         if (!prop)
                 goto not_mpsc;
 
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index d21ab8fa4993..1456015a22d8 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -86,14 +86,14 @@ static int __init mv64x60_sysfs_init(void)
         struct platform_device *pdev;
         const unsigned int *prop;
 
-        np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60");
+        np = of_find_compatible_node(NULL, NULL, "marvell,mv64360");
         if (!np)
                 return 0;
 
         prop = of_get_property(np, "hs_reg_valid", NULL);
         of_node_put(np);
 
-        pdev = platform_device_register_simple("marvell,mv64x60", 0, NULL, 0);
+        pdev = platform_device_register_simple("marvell,mv64360", 0, NULL, 0);
         if (IS_ERR(pdev))
                 return PTR_ERR(pdev);
 
@@ -166,6 +166,6 @@ void __init mv64x60_pci_init(void)
 {
         struct device_node *np;
 
-        for_each_compatible_node(np, "pci", "marvell,mv64x60-pci")
+        for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
                 mv64x60_add_bridge(np);
 }
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c
index 19e6ef263797..2aa4ed066db1 100644
--- a/arch/powerpc/sysdev/mv64x60_pic.c
+++ b/arch/powerpc/sysdev/mv64x60_pic.c
@@ -238,13 +238,13 @@ void __init mv64x60_init_irq(void)
         const unsigned int *reg;
         unsigned long flags;
 
-        np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp");
+        np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
         reg = of_get_property(np, "reg", &size);
         paddr = of_translate_address(np, reg);
         mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
         of_node_put(np);
 
-        np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-pic");
+        np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
         reg = of_get_property(np, "reg", &size);
         paddr = of_translate_address(np, reg);
         mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
diff --git a/arch/powerpc/sysdev/mv64x60_udbg.c b/arch/powerpc/sysdev/mv64x60_udbg.c
index 35c77c7d0616..ccdb3b0418fc 100644
--- a/arch/powerpc/sysdev/mv64x60_udbg.c
+++ b/arch/powerpc/sysdev/mv64x60_udbg.c
@@ -85,7 +85,7 @@ static void mv64x60_udbg_init(void)
         if (!stdout)
                 return;
 
-        for_each_compatible_node(np, "serial", "marvell,mpsc") {
+        for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
                 if (np == stdout)
                         break;
         }
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 5abfcd157483..1814adbd2236 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -527,6 +527,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
  *
  * ibm,plb-pciex-440spe
  * ibm,plb-pciex-405ex
+ * ibm,plb-pciex-460ex
  *
  * Anything else will be rejected for now as they are all subtly
  * different unfortunately.
@@ -645,7 +646,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
         int time_out = 20;
 
         /* Set PLL clock receiver to LVPECL */
-        mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
+        dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
 
         /* Shouldn't we do all the calibration stuff etc... here ? */
         if (ppc440spe_pciex_check_reset(np))
@@ -659,8 +660,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
         }
 
         /* De-assert reset of PCIe PLL, wait for lock */
-        mtdcri(SDR0, PESDR0_PLLLCT1,
-               mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
+        dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
         udelay(3);
 
         while (time_out) {
@@ -712,9 +712,8 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
                 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
                        0x35000000);
         }
-        val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
-        mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
-               (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
+        dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
+                        (1 << 24) | (1 << 16), 1 << 12);
 
         return 0;
 }
@@ -775,6 +774,115 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
         .setup_utl      = ppc440speB_pciex_init_utl,
 };
 
+static int __init ppc460ex_pciex_core_init(struct device_node *np)
+{
+        /* Nothing to do, return 2 ports */
+        return 2;
+}
+
+static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
+{
+        u32 val;
+        u32 utlset1;
+
+        if (port->endpoint)
+                val = PTYPE_LEGACY_ENDPOINT << 20;
+        else
+                val = PTYPE_ROOT_PORT << 20;
+
+        if (port->index == 0) {
+                val |= LNKW_X1 << 12;
+                utlset1 = 0x20000000;
+        } else {
+                val |= LNKW_X4 << 12;
+                utlset1 = 0x20101101;
+        }
+
+        mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
+        mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
+        mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
+
+        switch (port->index) {
+        case 0:
+                mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
+                mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
+                mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
+
+                mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
+                break;
+
+        case 1:
+                mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
+                mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
+                mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
+                mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
+                mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
+                mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
+                mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
+                mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
+                mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
+                mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
+                mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
+                mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
+
+                mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
+                break;
+        }
+
+        mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+               mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
+               (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
+
+        /* Poll for PHY reset */
+        /* XXX FIXME add timeout */
+        switch (port->index) {
+        case 0:
+                while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
+                        udelay(10);
+                break;
+        case 1:
+                while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
+                        udelay(10);
+                break;
+        }
+
+        mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+               (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
+                ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
+               PESDRx_RCSSET_RSTPYN);
+
+        port->has_ibpre = 1;
+
+        return 0;
+}
+
+static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
+{
+        dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
+
+        /*
+         * Set buffer allocations and then assert VRB and TXE.
+         */
+        out_be32(port->utl_base + PEUTL_PBCTL,  0x0800000c);
+        out_be32(port->utl_base + PEUTL_OUTTR,  0x08000000);
+        out_be32(port->utl_base + PEUTL_INTR,   0x02000000);
+        out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
+        out_be32(port->utl_base + PEUTL_PBBSZ,  0x00000000);
+        out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
+        out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
+        out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
+        out_be32(port->utl_base + PEUTL_PCTL,   0x80800066);
+
+        return 0;
+}
+
+static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
+{
+        .core_init      = ppc460ex_pciex_core_init,
+        .port_init_hw   = ppc460ex_pciex_init_port_hw,
+        .setup_utl      = ppc460ex_pciex_init_utl,
+};
+
 #endif /* CONFIG_44x */
 
 #ifdef CONFIG_40x
@@ -830,17 +938,9 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
          * PCIe boards don't show this problem.
          * This has to be re-tested and fixed in a later release!
          */
-#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
-       * configured as done previously by U-Boot. Then Linux will currently
-       * not reassign them. So the PHY reset is now done always. This will
-       * lead to problems with the Atheros PCIe board again.
-       */
         val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
         if (!(val & 0x00001000))
                 ppc405ex_pcie_phy_reset(port);
-#else
-        ppc405ex_pcie_phy_reset(port);
-#endif
 
         dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000);  /* guarded on */
 
@@ -896,6 +996,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
                 else
                         ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
         }
+        if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
+                ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
 #endif /* CONFIG_44x    */
 #ifdef CONFIG_40x
         if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
@@ -1042,8 +1144,7 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
                 port->link = 0;
         }
 
-        mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
-               mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
+        dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
         msleep(100);
 
         return 0;
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 1c07908dc6ef..d04e40b306fb 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -271,6 +271,59 @@
 #define PESDR1_405EX_PHYSTA             0x044C
 
 /*
+ * 460EX additional DCRs
+ */
+#define PESDR0_460EX_L0BIST             0x0308
+#define PESDR0_460EX_L0BISTSTS          0x0309
+#define PESDR0_460EX_L0CDRCTL           0x030A
+#define PESDR0_460EX_L0DRV              0x030B
+#define PESDR0_460EX_L0REC              0x030C
+#define PESDR0_460EX_L0LPB              0x030D
+#define PESDR0_460EX_L0CLK              0x030E
+#define PESDR0_460EX_PHY_CTL_RST        0x030F
+#define PESDR0_460EX_RSTSTA             0x0310
+#define PESDR0_460EX_OBS                0x0311
+#define PESDR0_460EX_L0ERRC             0x0320
+
+#define PESDR1_460EX_L0BIST             0x0348
+#define PESDR1_460EX_L1BIST             0x0349
+#define PESDR1_460EX_L2BIST             0x034A
+#define PESDR1_460EX_L3BIST             0x034B
+#define PESDR1_460EX_L0BISTSTS          0x034C
+#define PESDR1_460EX_L1BISTSTS          0x034D
+#define PESDR1_460EX_L2BISTSTS          0x034E
+#define PESDR1_460EX_L3BISTSTS          0x034F
+#define PESDR1_460EX_L0CDRCTL           0x0350
+#define PESDR1_460EX_L1CDRCTL           0x0351
+#define PESDR1_460EX_L2CDRCTL           0x0352
+#define PESDR1_460EX_L3CDRCTL           0x0353
+#define PESDR1_460EX_L0DRV              0x0354
+#define PESDR1_460EX_L1DRV              0x0355
+#define PESDR1_460EX_L2DRV              0x0356
+#define PESDR1_460EX_L3DRV              0x0357
+#define PESDR1_460EX_L0REC              0x0358
+#define PESDR1_460EX_L1REC              0x0359
+#define PESDR1_460EX_L2REC              0x035A
+#define PESDR1_460EX_L3REC              0x035B
+#define PESDR1_460EX_L0LPB              0x035C
+#define PESDR1_460EX_L1LPB              0x035D
+#define PESDR1_460EX_L2LPB              0x035E
+#define PESDR1_460EX_L3LPB              0x035F
+#define PESDR1_460EX_L0CLK              0x0360
+#define PESDR1_460EX_L1CLK              0x0361
+#define PESDR1_460EX_L2CLK              0x0362
+#define PESDR1_460EX_L3CLK              0x0363
+#define PESDR1_460EX_PHY_CTL_RST        0x0364
+#define PESDR1_460EX_RSTSTA             0x0365
+#define PESDR1_460EX_OBS                0x0366
+#define PESDR1_460EX_L0ERRC             0x0368
+#define PESDR1_460EX_L1ERRC             0x0369
+#define PESDR1_460EX_L2ERRC             0x036A
+#define PESDR1_460EX_L3ERRC             0x036B
+#define PESDR0_460EX_IHS1               0x036C
+#define PESDR0_460EX_IHS2               0x036D
+
+/*
  * Of the above, some are common offsets from the base
  */
 #define PESDRn_UTLSET1                  0x00
@@ -353,6 +406,12 @@
 #define PECFG_POM2LAL           0x390
 #define PECFG_POM2LAH           0x394
 
+/* SDR Bit Mappings */
+#define PESDRx_RCSSET_HLDPLB    0x10000000
+#define PESDRx_RCSSET_RSTGU     0x01000000
+#define PESDRx_RCSSET_RDY       0x00100000
+#define PESDRx_RCSSET_RSTDL     0x00010000
+#define PESDRx_RCSSET_RSTPYN    0x00001000
 
 enum
 {
diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c
new file mode 100644
index 000000000000..5b32adc9a9b2
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_soc.c
@@ -0,0 +1,200 @@
+/*
+ * IBM/AMCC PPC4xx SoC setup code
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
+ *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *   Copyright (c) 2003 - 2006 Zultys Technologies
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/dcr.h>
+#include <asm/dcr-regs.h>
+#include <asm/reg.h>
+
+static u32 dcrbase_l2c;
+
+/*
+ * L2-cache
+ */
+
+/* Issue L2C diagnostic command */
+static inline u32 l2c_diag(u32 addr)
+{
+        mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
+        mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
+        while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
+                ;
+
+        return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
+}
+
+static irqreturn_t l2c_error_handler(int irq, void *dev)
+{
+        u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
+
+        if (sr & L2C_SR_CPE) {
+                /* Read cache trapped address */
+                u32 addr = l2c_diag(0x42000000);
+                printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
+                       addr);
+        }
+        if (sr & L2C_SR_TPE) {
+                /* Read tag trapped address */
+                u32 addr = l2c_diag(0x82000000) >> 16;
+                printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
+                       addr);
+        }
+
+        /* Clear parity errors */
+        if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
+                mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
+                mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
+        } else {
+                printk(KERN_EMERG "L2C: LRU error\n");
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int __init ppc4xx_l2c_probe(void)
+{
+        struct device_node *np;
+        u32 r;
+        unsigned long flags;
+        int irq;
+        const u32 *dcrreg;
+        u32 dcrbase_isram;
+        int len;
+        const u32 *prop;
+        u32 l2_size;
+
+        np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
+        if (!np)
+                return 0;
+
+        /* Get l2 cache size */
+        prop = of_get_property(np, "cache-size", NULL);
+        if (prop == NULL) {
+                printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
+                of_node_put(np);
+                return -ENODEV;
+        }
+        l2_size = prop[0];
+
+        /* Map DCRs */
+        dcrreg = of_get_property(np, "dcr-reg", &len);
+        if (!dcrreg || (len != 4 * sizeof(u32))) {
+                printk(KERN_ERR "%s: Can't get DCR register base !",
+                       np->full_name);
+                of_node_put(np);
+                return -ENODEV;
+        }
+        dcrbase_isram = dcrreg[0];
+        dcrbase_l2c = dcrreg[2];
+
+        /* Get and map irq number from device tree */
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq == NO_IRQ) {
+                printk(KERN_ERR "irq_of_parse_and_map failed\n");
+                of_node_put(np);
+                return -ENODEV;
+        }
+
+        /* Install error handler */
+        if (request_irq(irq, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0) {
+                printk(KERN_ERR "Cannot install L2C error handler"
+                       ", cache is not enabled\n");
+                of_node_put(np);
+                return -ENODEV;
+        }
+
+        local_irq_save(flags);
+        asm volatile ("sync" ::: "memory");
+
+        /* Disable SRAM */
+        mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
+              mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
+        mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
+              mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
+        mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
+              mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
+        mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
+              mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
+        mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
+              mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
+
+        /* Enable L2_MODE without ICU/DCU */
+        r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
+                ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
+        r |= L2C_CFG_L2M | L2C_CFG_SS_256;
+        mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
+
+        mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
+
+        /* Hardware Clear Command */
+        mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
+        while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
+                ;
+
+        /* Clear Cache Parity and Tag Errors */
+        mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
+
+        /* Enable 64G snoop region starting at 0 */
+        r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
+                ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
+        r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
+        mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
+
+        r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
+                ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
+        r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
+        mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
+
+        asm volatile ("sync" ::: "memory");
+
+        /* Enable ICU/DCU ports */
+        r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
+        r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
+               | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
+        r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
+                | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
+
+        /* Check for 460EX/GT special handling */
+        if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
+                r |= L2C_CFG_RDBW;
+
+        mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
+
+        asm volatile ("sync; isync" ::: "memory");
+        local_irq_restore(flags);
+
+        printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
+
+        of_node_put(np);
+        return 0;
+}
+arch_initcall(ppc4xx_l2c_probe);
+
+/*
+ * At present, this routine just applies a system reset.
+ */
+void ppc4xx_reset_system(char *cmd)
+{
+        mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_RST_SYSTEM);
+        while (1)
+                ;       /* Just in case the reset doesn't work */
+}
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index cc81fd1141b0..cff550eec7e8 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -55,7 +55,7 @@ struct qe_snum {
 /* We allocate this here because it is used almost exclusively for
  * the communication processor devices.
  */
-struct qe_immap *qe_immr = NULL;
+struct qe_immap __iomem *qe_immr;
 EXPORT_SYMBOL(qe_immr);
 
 static struct qe_snum snums[QE_NUM_OF_SNUM];    /* Dynamically allocated SNUMs */
@@ -156,7 +156,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
  */
 static unsigned int brg_clk = 0;
 
-unsigned int get_brg_clk(void)
+unsigned int qe_get_brg_clk(void)
 {
         struct device_node *qe;
         unsigned int size;
@@ -180,6 +180,7 @@ unsigned int get_brg_clk(void)
 
         return brg_clk;
 }
+EXPORT_SYMBOL(qe_get_brg_clk);
 
 /* Program the BRG to the given sampling rate and multiplier
  *
@@ -197,7 +198,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
         if ((brg < QE_BRG1) || (brg > QE_BRG16))
                 return -EINVAL;
 
-        divisor = get_brg_clk() / (rate * multiplier);
+        divisor = qe_get_brg_clk() / (rate * multiplier);
 
         if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
                 div16 = QE_BRGC_DIV16;
@@ -415,12 +416,6 @@ void qe_muram_dump(void)
 }
 EXPORT_SYMBOL(qe_muram_dump);
 
-void *qe_muram_addr(unsigned long offset)
-{
-        return (void *)&qe_immr->muram[offset];
-}
-EXPORT_SYMBOL(qe_muram_addr);
-
 /* The maximum number of RISCs we support */
 #define MAX_QE_RISC     2
 
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e53ea4d374a0..93916a48afec 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -22,6 +22,7 @@
 #include <linux/ioport.h>
 
 #include <asm/io.h>
+#include <asm/qe.h>
 #include <asm/prom.h>
 #include <sysdev/fsl_soc.h>
 
@@ -41,7 +42,7 @@ struct port_regs {
 #endif
 };
 
-static struct port_regs *par_io = NULL;
+static struct port_regs __iomem *par_io;
 static int num_par_io_ports = 0;
 
 int par_io_init(struct device_node *np)
@@ -165,7 +166,7 @@ int par_io_of_config(struct device_node *np)
         }
 
         ph = of_get_property(np, "pio-handle", NULL);
-        if (ph == 0) {
+        if (ph == NULL) {
                 printk(KERN_ERR "pio-handle not available \n");
                 return -1;
         }
@@ -200,7 +201,7 @@ static void dump_par_io(void)
 {
         unsigned int i;
 
-        printk(KERN_INFO "%s: par_io=%p\n", __FUNCTION__, par_io);
+        printk(KERN_INFO "%s: par_io=%p\n", __func__, par_io);
         for (i = 0; i < num_par_io_ports; i++) {
                 printk(KERN_INFO "      cpodr[%u]=%08x\n", i,
                         in_be32(&par_io[i].cpodr));
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index 3223acbc39e5..bcf88e6ce962 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -148,57 +148,57 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
 
         /* check if the UCC port number is in range. */
         if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
-                printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
+                printk(KERN_ERR "%s: illegal UCC number\n", __func__);
                 return -EINVAL;
         }
 
         /* Check that 'max_rx_buf_length' is properly aligned (4). */
         if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
                 printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
-                        __FUNCTION__);
+                        __func__);
                 return -EINVAL;
         }
 
         /* Validate Virtual Fifo register values */
         if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
-                printk(KERN_ERR "%s: urfs is too small\n", __FUNCTION__);
+                printk(KERN_ERR "%s: urfs is too small\n", __func__);
                 return -EINVAL;
         }
 
         if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
-                printk(KERN_ERR "%s: urfs is not aligned\n", __FUNCTION__);
+                printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
                 return -EINVAL;
         }
 
         if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
-                printk(KERN_ERR "%s: urfet is not aligned.\n", __FUNCTION__);
+                printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
                 return -EINVAL;
         }
 
         if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
-                printk(KERN_ERR "%s: urfset is not aligned\n", __FUNCTION__);
+                printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
                 return -EINVAL;
         }
 
         if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
-                printk(KERN_ERR "%s: utfs is not aligned\n", __FUNCTION__);
+                printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
                 return -EINVAL;
         }
 
         if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
-                printk(KERN_ERR "%s: utfet is not aligned\n", __FUNCTION__);
+                printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
                 return -EINVAL;
         }
 
         if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
-                printk(KERN_ERR "%s: utftt is not aligned\n", __FUNCTION__);
+                printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
                 return -EINVAL;
         }
 
         uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
         if (!uccf) {
                 printk(KERN_ERR "%s: Cannot allocate private data\n",
-                        __FUNCTION__);
+                        __func__);
                 return -ENOMEM;
         }
 
@@ -207,7 +207,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
         /* Set the PHY base address */
         uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
         if (uccf->uf_regs == NULL) {
-                printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
+                printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
                 return -ENOMEM;
         }
 
@@ -230,7 +230,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
         /* Set UCC to fast type */
         ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
         if (ret) {
-                printk(KERN_ERR "%s: cannot set UCC type\n", __FUNCTION__);
+                printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
                 ucc_fast_free(uccf);
                 return ret;
         }
@@ -270,7 +270,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
             qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
         if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
                 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
-                        __FUNCTION__);
+                        __func__);
                 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
                 ucc_fast_free(uccf);
                 return -ENOMEM;
@@ -283,7 +283,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
                            UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
         if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
                 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
-                        __FUNCTION__);
+                        __func__);
                 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
                 ucc_fast_free(uccf);
                 return -ENOMEM;
@@ -314,7 +314,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
                     ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
                                         COMM_DIR_RX)) {
                         printk(KERN_ERR "%s: illegal value for RX clock\n",
-                               __FUNCTION__);
+                               __func__);
                         ucc_fast_free(uccf);
                         return -EINVAL;
                 }
@@ -323,7 +323,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
                     ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
                                         COMM_DIR_TX)) {
                         printk(KERN_ERR "%s: illegal value for TX clock\n",
-                               __FUNCTION__);
+                               __func__);
                         ucc_fast_free(uccf);
                         return -EINVAL;
                 }
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index b2870b208ddb..a578bc77b9d5 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -142,7 +142,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
 
         /* check if the UCC port number is in range. */
         if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
-                printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
+                printk(KERN_ERR "%s: illegal UCC number\n", __func__);
                 return -EINVAL;
         }
 
@@ -161,7 +161,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
         uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
         if (!uccs) {
                 printk(KERN_ERR "%s: Cannot allocate private data\n",
-                        __FUNCTION__);
+                        __func__);
                 return -ENOMEM;
         }
 
@@ -170,7 +170,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
         /* Set the PHY base address */
         uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
         if (uccs->us_regs == NULL) {
-                printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
+                printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
                 return -ENOMEM;
         }
 
@@ -189,7 +189,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
         uccs->us_pram_offset =
                 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
         if (IS_ERR_VALUE(uccs->us_pram_offset)) {
-                printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __FUNCTION__);
+                printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
                 ucc_slow_free(uccs);
                 return -ENOMEM;
         }
@@ -202,7 +202,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
         /* Set UCC to slow type */
         ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
         if (ret) {
-                printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
+                printk(KERN_ERR "%s: cannot set UCC type", __func__);
                 ucc_slow_free(uccs);
                 return ret;
         }
@@ -216,7 +216,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
                 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
                                 QE_ALIGNMENT_OF_BD);
         if (IS_ERR_VALUE(uccs->rx_base_offset)) {
-                printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __FUNCTION__,
+                printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
                         us_info->rx_bd_ring_len);
                 uccs->rx_base_offset = 0;
                 ucc_slow_free(uccs);
@@ -227,7 +227,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
                 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
                         QE_ALIGNMENT_OF_BD);
         if (IS_ERR_VALUE(uccs->tx_base_offset)) {
-                printk(KERN_ERR "%s: cannot allocate TX BDs", __FUNCTION__);
+                printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
                 uccs->tx_base_offset = 0;
                 ucc_slow_free(uccs);
                 return -ENOMEM;
@@ -317,7 +317,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
                 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
                                         COMM_DIR_RX)) {
                         printk(KERN_ERR "%s: illegal value for RX clock\n",
-                               __FUNCTION__);
+                               __func__);
                         ucc_slow_free(uccs);
                         return -EINVAL;
                 }
@@ -325,7 +325,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
                 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
                                         COMM_DIR_TX)) {
                         printk(KERN_ERR "%s: illegal value for TX clock\n",
-                               __FUNCTION__);
+                               __func__);
                         ucc_slow_free(uccs);
                         return -EINVAL;
                 }
diff --git a/arch/powerpc/sysdev/rtc_cmos_setup.c b/arch/powerpc/sysdev/rtc_cmos_setup.c
index 0c9ac7ee08fb..c09ddc0dbeb3 100644
--- a/arch/powerpc/sysdev/rtc_cmos_setup.c
+++ b/arch/powerpc/sysdev/rtc_cmos_setup.c
@@ -56,3 +56,5 @@ static int  __init add_rtc(void)
         return 0;
 }
 fs_initcall(add_rtc);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c
index be2808a292f7..d4d15aaf18fa 100644
--- a/arch/powerpc/sysdev/tsi108_dev.c
+++ b/arch/powerpc/sysdev/tsi108_dev.c
@@ -84,7 +84,7 @@ static int __init tsi108_eth_of_init(void)
 
                 ret = of_address_to_resource(np, 0, &r[0]);
                 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
-                        __FUNCTION__,r[0].name, r[0].start, r[0].end);
+                        __func__,r[0].name, r[0].start, r[0].end);
                 if (ret)
                         goto err;
 
@@ -93,7 +93,7 @@ static int __init tsi108_eth_of_init(void)
                 r[1].end = irq_of_parse_and_map(np, 0);
                 r[1].flags = IORESOURCE_IRQ;
                 DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
-                        __FUNCTION__,r[1].name, r[1].start, r[1].end);
+                        __func__,r[1].name, r[1].start, r[1].end);
 
                 tsi_eth_dev =
                     platform_device_register_simple("tsi-ethernet", i++, &r[0],
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 31d3d33d91fc..ac1a72dc21e5 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -207,7 +207,7 @@ int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
         /* PCI Config mapping */
         tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
         tsi108_pci_cfg_phys = cfg_phys;
-        DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
+        DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
             tsi108_pci_cfg_base);
 
         /* Fetch host bridge registers address */
@@ -395,7 +395,7 @@ static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
 static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
                           irq_hw_number_t hw)
 {       unsigned int irq;
-        DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw);
+        DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
         if ((virq >= 1) && (virq <= 4)){
                 irq = virq + IRQ_PCI_INTAD_BASE - 1;
                 get_irq_desc(irq)->status |= IRQ_LEVEL;
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index a34172ddc468..52c74780f403 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -45,7 +45,6 @@
 #ifdef CONFIG_PPC64
 #include <asm/hvcall.h>
 #include <asm/paca.h>
-#include <asm/iseries/it_lp_reg_save.h>
 #endif
 
 #include "nonstdio.h"
@@ -1244,15 +1243,12 @@ static void get_function_bounds(unsigned long pc, unsigned long *startp,
 
 static int xmon_depth_to_print = 64;
 
-#ifdef CONFIG_PPC64
-#define LRSAVE_OFFSET           0x10
-#define REG_FRAME_MARKER        0x7265677368657265ul    /* "regshere" */
-#define MARKER_OFFSET           0x60
+#define LRSAVE_OFFSET           (STACK_FRAME_LR_SAVE * sizeof(unsigned long))
+#define MARKER_OFFSET           (STACK_FRAME_MARKER * sizeof(unsigned long))
+
+#ifdef __powerpc64__
 #define REGS_OFFSET             0x70
 #else
-#define LRSAVE_OFFSET           4
-#define REG_FRAME_MARKER        0x72656773
-#define MARKER_OFFSET           8
 #define REGS_OFFSET             16
 #endif
 
@@ -1318,7 +1314,7 @@ static void xmon_show_stack(unsigned long sp, unsigned long lr,
                 /* Look for "regshere" marker to see if this is
                    an exception frame. */
                 if (mread(sp + MARKER_OFFSET, &marker, sizeof(unsigned long))
-                    && marker == REG_FRAME_MARKER) {
+                    && marker == STACK_FRAME_REGS_MARKER) {
                         if (mread(sp + REGS_OFFSET, &regs, sizeof(regs))
                             != sizeof(regs)) {
                                 printf("Couldn't read registers at %lx\n",
@@ -1598,7 +1594,6 @@ void super_regs(void)
                 if (firmware_has_feature(FW_FEATURE_ISERIES)) {
                         struct paca_struct *ptrPaca;
                         struct lppaca *ptrLpPaca;
-                        struct ItLpRegSave *ptrLpRegSave;
 
                         /* Dump out relevant Paca data areas. */
                         printf("Paca: \n");
@@ -1611,15 +1606,6 @@ void super_regs(void)
                         printf("    Saved Gpr3=%.16lx  Saved Gpr4=%.16lx \n",
                                ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
                         printf("    Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
-
-                        printf("  Local Processor Register Save Area (LpRegSave): \n");
-                        ptrLpRegSave = ptrPaca->reg_save_ptr;
-                        printf("    Saved Sprg0=%.16lx  Saved Sprg1=%.16lx \n",
-                               ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0);
-                        printf("    Saved Sprg2=%.16lx  Saved Sprg3=%.16lx \n",
-                               ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3);
-                        printf("    Saved Msr  =%.16lx  Saved Nia  =%.16lx \n",
-                               ptrLpRegSave->xMSR, ptrLpRegSave->xNIA);
                 }
 #endif
 
diff --git a/arch/ppc/8xx_io/commproc.c b/arch/ppc/8xx_io/commproc.c
index 9d656de0f0f1..752443df5ecf 100644
--- a/arch/ppc/8xx_io/commproc.c
+++ b/arch/ppc/8xx_io/commproc.c
@@ -43,7 +43,7 @@
 ({                                                                      \
         u32 offset = offsetof(immap_t, member);                         \
         void *addr = ioremap (IMAP_ADDR + offset,                       \
-                              sizeof( ((immap_t*)0)->member));          \
+                              FIELD_SIZEOF(immap_t, member));           \
         addr;                                                           \
 })
 
diff --git a/arch/ppc/8xx_io/fec.c b/arch/ppc/8xx_io/fec.c
index 11b0aa6ca97e..2c604d4f6e8b 100644
--- a/arch/ppc/8xx_io/fec.c
+++ b/arch/ppc/8xx_io/fec.c
@@ -199,7 +199,6 @@ static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
 #ifdef  CONFIG_USE_MDIO
 static void fec_enet_mii(struct net_device *dev);
 #endif  /* CONFIG_USE_MDIO */
-static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
 #ifdef CONFIG_FEC_PACKETHOOK
 static void  fec_enet_tx(struct net_device *dev, __u32 regval);
 static void  fec_enet_rx(struct net_device *dev, __u32 regval);
@@ -472,7 +471,7 @@ fec_timeout(struct net_device *dev)
  * This is called from the MPC core interrupt.
  */
 static  irqreturn_t
-fec_enet_interrupt(int irq, void * dev_id)
+fec_enet_interrupt(int irq, void *dev_id)
 {
         struct  net_device *dev = dev_id;
         volatile fec_t  *fecp;
@@ -520,7 +519,7 @@ fec_enet_interrupt(int irq, void * dev_id)
 #ifdef  CONFIG_USE_MDIO
                         fec_enet_mii(dev);
 #else
-printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTION__);
+printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__, __LINE__, __func__);
 #endif  /* CONFIG_USE_MDIO */
                 }
 
@@ -1441,7 +1440,7 @@ irqreturn_t mii_link_interrupt(int irq, void * dev_id)
                 fecp->fec_ecntrl = ecntrl;      /* restore old settings */
         }
 #else
-printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
+printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__, __LINE__, __func__);
 #endif  /* CONFIG_USE_MDIO */
 
 #ifndef CONFIG_RPXCLASSIC
diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S
index 1b0ec7202dd5..e7e642b95138 100644
--- a/arch/ppc/kernel/head.S
+++ b/arch/ppc/kernel/head.S
@@ -701,23 +701,6 @@ load_up_altivec:
         b       fast_exception_return
 
 /*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
-        lwz     r3,_MSR(r1)
-        oris    r3,r3,MSR_VEC@h
-        stw     r3,_MSR(r1)     /* enable use of AltiVec after return */
-        lis     r3,87f@h
-        ori     r3,r3,87f@l
-        mr      r4,r2           /* current */
-        lwz     r5,_NIP(r1)
-        bl      printk
-        b       ret_from_except
-87:     .string "AltiVec used in kernel  (task=%p, pc=%x)  \n"
-        .align  4,0
-
-/*
  * giveup_altivec(tsk)
  * Disable AltiVec for the task given as the argument,
  * and save the AltiVec registers in its thread_struct.
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
index 7444df3889c5..1a63711081b5 100644
--- a/arch/ppc/mm/init.c
+++ b/arch/ppc/mm/init.c
@@ -109,7 +109,6 @@ void show_mem(void)
 
         printk("Mem-info:\n");
         show_free_areas();
-        printk("Free swap:       %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
         i = max_mapnr;
         while (i-- > 0) {
                 total++;
diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c
index 179b4a99b5b5..f1dee1e87809 100644
--- a/arch/ppc/platforms/radstone_ppc7d.c
+++ b/arch/ppc/platforms/radstone_ppc7d.c
@@ -511,7 +511,7 @@ static void __init ppc7d_init_irq(void)
 {
         int irq;
 
-        pr_debug("%s\n", __FUNCTION__);
+        pr_debug("%s\n", __func__);
         i8259_init(0, 0);
         mv64360_init_irq();
 
@@ -568,7 +568,7 @@ static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel,
         };
         const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;
 
-        pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__,
+        pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __func__,
                  dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);
 
         return PCI_IRQ_TABLE_LOOKUP;
@@ -1299,7 +1299,7 @@ static void ppc7d_init2(void)
         u32 data;
         u8 data8;
 
-        pr_debug("%s: enter\n", __FUNCTION__);
+        pr_debug("%s: enter\n", __func__);
 
         /* Wait for debugger? */
         if (ppc7d_wait_debugger) {
@@ -1332,7 +1332,7 @@ static void ppc7d_init2(void)
         ppc_md.set_rtc_time = ppc7d_set_rtc_time;
         ppc_md.get_rtc_time = ppc7d_get_rtc_time;
 
-        pr_debug("%s: exit\n", __FUNCTION__);
+        pr_debug("%s: exit\n", __func__);
 }
 
 /* Called from machine_init(), early, before any of the __init functions
diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c
index cc0935ccab7a..0df6aacb8237 100644
--- a/arch/ppc/platforms/sbc82xx.c
+++ b/arch/ppc/platforms/sbc82xx.c
@@ -121,8 +121,10 @@ struct hw_interrupt_type sbc82xx_i8259_ic = {
         .end = sbc82xx_i8259_end_irq,
 };
 
-static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id)
+static irqreturn_t sbc82xx_i8259_demux(int dummy, void *dev_id)
 {
+        int irq;
+
         spin_lock(&sbc82xx_i8259_lock);
 
         sbc82xx_i8259_map[0] = 0x0c;    /* OCW3: Read IR register on RD# pulse */
diff --git a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
index 9f504fc7693e..ab0cf4ced9e5 100644
--- a/arch/ppc/syslib/mpc52xx_setup.c
+++ b/arch/ppc/syslib/mpc52xx_setup.c
@@ -279,7 +279,7 @@ int mpc52xx_match_psc_function(int psc_idx, const char *func)
 
 int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
 {
-        static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+        static DEFINE_SPINLOCK(lock);
         struct mpc52xx_cdm __iomem *cdm;
         unsigned long flags;
         u16 mclken_div;
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index ac80370ed2f7..a6fb7dcfa738 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -49,7 +49,6 @@
 #include <asm/io.h>
 #include <asm/ocp.h>
 #include <asm/errno.h>
-#include <asm/semaphore.h>
 
 //#define DBG(x)        printk x
 #define DBG(x)
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index 50b85d07ddd2..d7f22226fc4e 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -62,7 +62,6 @@
 
 #include <asm/types.h>
 #include <asm/uaccess.h>
-#include <asm/semaphore.h>
 
 #include <net/scm.h>
 #include <net/sock.h>
diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c
index 1e7d4ac7068b..dff0568e67ec 100644
--- a/arch/s390/kernel/debug.c
+++ b/arch/s390/kernel/debug.c
@@ -17,7 +17,6 @@
 #include <linux/ctype.h>
 #include <linux/sysctl.h>
 #include <asm/uaccess.h>
-#include <asm/semaphore.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/fs.h>
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8d2cd1de5726..6a679c3e15e8 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -167,6 +167,12 @@ config CPU_SUBTYPE_SH7263
         select CPU_SH2A
         select CPU_HAS_FPU
 
+config CPU_SUBTYPE_MXG
+        bool "Support MX-G processor"
+        select CPU_SH2A
+        help
+          Select MX-G if running on an R8A03022BG part.
+
 # SH-3 Processor Support
 
 config CPU_SUBTYPE_SH7705
@@ -270,6 +276,15 @@ config CPU_SUBTYPE_SH4_202
 
 # SH-4A Processor Support
 
+config CPU_SUBTYPE_SH7723
+        bool "Support SH7723 processor"
+        select CPU_SH4A
+        select CPU_SHX2
+        select ARCH_SPARSEMEM_ENABLE
+        select SYS_SUPPORTS_NUMA
+        help
+          Select SH7723 if you have an SH-MobileR2 CPU.
+
 config CPU_SUBTYPE_SH7763
         bool "Support SH7763 processor"
         select CPU_SH4A
@@ -366,6 +381,14 @@ config SH_7619_SOLUTION_ENGINE
           Select 7619 SolutionEngine if configuring for a Hitachi SH7619
           evaluation board.
         
+config SH_7721_SOLUTION_ENGINE
+        bool "SolutionEngine7721"
+        select SOLUTION_ENGINE
+        depends on CPU_SUBTYPE_SH7721
+        help
+          Select 7721 SolutionEngine if configuring for a Hitachi SH7721
+          evaluation board.
+
 config SH_7722_SOLUTION_ENGINE
         bool "SolutionEngine7722"
         select SOLUTION_ENGINE
@@ -560,7 +583,7 @@ config SH_TMU
 config SH_CMT
         def_bool y
         prompt "CMT timer support"
-        depends on CPU_SH2
+        depends on CPU_SH2 && !CPU_SUBTYPE_MXG
         help
           This enables the use of the CMT as the system timer.
 
@@ -578,6 +601,7 @@ config SH_TIMER_IRQ
         default "86" if CPU_SUBTYPE_SH7619
         default "140" if CPU_SUBTYPE_SH7206
         default "142" if CPU_SUBTYPE_SH7203
+        default "238" if CPU_SUBTYPE_MXG
         default "16"
 
 config SH_PCLK_FREQ
@@ -585,10 +609,10 @@ config SH_PCLK_FREQ
         default "27000000" if CPU_SUBTYPE_SH7343
         default "31250000" if CPU_SUBTYPE_SH7619
         default "32000000" if CPU_SUBTYPE_SH7722
-        default "33333333" if CPU_SUBTYPE_SH7770 || \
+        default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \
                               CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
                               CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
-                              CPU_SUBTYPE_SH7263
+                              CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
         default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
         default "66000000" if CPU_SUBTYPE_SH4_202
         default "50000000"
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 5dcb74b947a9..d9d28f9dd0db 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -29,16 +29,17 @@ config EARLY_SCIF_CONSOLE
 config EARLY_SCIF_CONSOLE_PORT
         hex
         depends on EARLY_SCIF_CONSOLE
-        default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
-        default "0xffe00000" if CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
-        default "0xffea0000" if CPU_SUBTYPE_SH7785
-        default "0xfffe8000" if CPU_SUBTYPE_SH7203
-        default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
-        default "0xf8420000" if CPU_SUBTYPE_SH7619
         default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
         default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
+        default "0xf8420000" if CPU_SUBTYPE_SH7619
+        default "0xff804000" if CPU_SUBTYPE_MXG
         default "0xffc30000" if CPU_SUBTYPE_SHX3
+        default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
+                                CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
         default "0xffe80000" if CPU_SH4
+        default "0xffea0000" if CPU_SUBTYPE_SH7785
+        default "0xfffe8000" if CPU_SUBTYPE_SH7203
+        default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
         default "0x00000000"
 
 config EARLY_PRINTK
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index cffc92b1bf2e..bb06f83e6239 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -107,6 +107,7 @@ machdir-$(CONFIG_SH_7722_SOLUTION_ENGINE)	+= se/7722
 machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE)       += se/7751
 machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE)       += se/7780
 machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE)       += se/7343
+machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE)       += se/7721
 machdir-$(CONFIG_SH_HP6XX)                      += hp6xx
 machdir-$(CONFIG_SH_DREAMCAST)                  += dreamcast
 machdir-$(CONFIG_SH_MPC1211)                    += mpc1211
diff --git a/arch/sh/boards/renesas/migor/setup.c b/arch/sh/boards/renesas/migor/setup.c
index 21ab8c8fb590..00d52a20d8a5 100644
--- a/arch/sh/boards/renesas/migor/setup.c
+++ b/arch/sh/boards/renesas/migor/setup.c
@@ -10,8 +10,14 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/i2c.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
+#include <asm/sh_keysc.h>
+#include <asm/migor.h>
 
 /* Address     IRQ  Size  Bus  Description
  * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
@@ -23,9 +29,9 @@
 
 static struct resource smc91x_eth_resources[] = {
         [0] = {
-                .name   = "smc91x-regs" ,
-                .start  = P2SEGADDR(0x10000300),
-                .end    = P2SEGADDR(0x1000030f),
+                .name   = "SMC91C111" ,
+                .start  = 0x10000300,
+                .end    = 0x1000030f,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -40,19 +46,202 @@ static struct platform_device smc91x_eth_device = {
         .resource       = smc91x_eth_resources,
 };
 
+static struct sh_keysc_info sh_keysc_info = {
+        .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
+        .scan_timing = 3,
+        .delay = 5,
+        .keycodes = {
+                0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
+                0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
+                0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
+                0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
+                0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
+        },
+};
+
+static struct resource sh_keysc_resources[] = {
+        [0] = {
+                .start  = 0x044b0000,
+                .end    = 0x044b000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 79,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sh_keysc_device = {
+        .name           = "sh_keysc",
+        .num_resources  = ARRAY_SIZE(sh_keysc_resources),
+        .resource       = sh_keysc_resources,
+        .dev    = {
+                .platform_data  = &sh_keysc_info,
+        },
+};
+
+static struct mtd_partition migor_nor_flash_partitions[] =
+{
+        {
+                .name = "uboot",
+                .offset = 0,
+                .size = (1 * 1024 * 1024),
+                .mask_flags = MTD_WRITEABLE,    /* Read-only */
+        },
+        {
+                .name = "rootfs",
+                .offset = MTDPART_OFS_APPEND,
+                .size = (15 * 1024 * 1024),
+        },
+        {
+                .name = "other",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data migor_nor_flash_data = {
+        .width          = 2,
+        .parts          = migor_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(migor_nor_flash_partitions),
+};
+
+static struct resource migor_nor_flash_resources[] = {
+        [0] = {
+                .name           = "NOR Flash",
+                .start          = 0x00000000,
+                .end            = 0x03ffffff,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device migor_nor_flash_device = {
+        .name           = "physmap-flash",
+        .resource       = migor_nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(migor_nor_flash_resources),
+        .dev            = {
+                .platform_data = &migor_nor_flash_data,
+        },
+};
+
+static struct mtd_partition migor_nand_flash_partitions[] = {
+        {
+                .name           = "nanddata1",
+                .offset         = 0x0,
+                .size           = 512 * 1024 * 1024,
+        },
+        {
+                .name           = "nanddata2",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024 * 1024,
+        },
+};
+
+static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
+                                     unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        if (ctrl & NAND_CLE)
+                writeb(cmd, chip->IO_ADDR_W + 0x00400000);
+        else if (ctrl & NAND_ALE)
+                writeb(cmd, chip->IO_ADDR_W + 0x00800000);
+        else
+                writeb(cmd, chip->IO_ADDR_W);
+}
+
+static int migor_nand_flash_ready(struct mtd_info *mtd)
+{
+        return ctrl_inb(PORT_PADR) & 0x02; /* PTA1 */
+}
+
+struct platform_nand_data migor_nand_flash_data = {
+        .chip = {
+                .nr_chips = 1,
+                .partitions = migor_nand_flash_partitions,
+                .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
+                .chip_delay = 20,
+                .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
+        },
+        .ctrl = {
+                .dev_ready = migor_nand_flash_ready,
+                .cmd_ctrl = migor_nand_flash_cmd_ctl,
+        },
+};
+
+static struct resource migor_nand_flash_resources[] = {
+        [0] = {
+                .name           = "NAND Flash",
+                .start          = 0x18000000,
+                .end            = 0x18ffffff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device migor_nand_flash_device = {
+        .name           = "gen_nand",
+        .resource       = migor_nand_flash_resources,
+        .num_resources  = ARRAY_SIZE(migor_nand_flash_resources),
+        .dev            = {
+                .platform_data = &migor_nand_flash_data,
+        }
+};
+
 static struct platform_device *migor_devices[] __initdata = {
         &smc91x_eth_device,
+        &sh_keysc_device,
+        &migor_nor_flash_device,
+        &migor_nand_flash_device,
+};
+
+static struct i2c_board_info __initdata migor_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+                .type   = "rs5c372b",
+        },
+        {
+                I2C_BOARD_INFO("migor_ts", 0x51),
+                .irq = 38, /* IRQ6 */
+        },
 };
 
 static int __init migor_devices_setup(void)
 {
+        i2c_register_board_info(0, migor_i2c_devices,
+                                ARRAY_SIZE(migor_i2c_devices));
+ 
         return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
 }
 __initcall(migor_devices_setup);
 
 static void __init migor_setup(char **cmdline_p)
 {
-        ctrl_outw(0x1000, 0xa4050110); /* Enable IRQ0 in PJCR */
+        /* SMC91C111 - Enable IRQ0 */
+        ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR);
+
+        /* KEYSC */
+        ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR);
+        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR);
+        ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA);
+        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+        ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
+        ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2);
+
+        /* NAND Flash */
+        ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR);
+        ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200,
+                  BSC_CS6ABCR);
+
+        /* I2C */
+        ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1);
+
+        /* Touch Panel - Enable IRQ6 */
+        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR);
+        ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA);
+        ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC);
 }
 
 static struct sh_machine_vector mv_migor __initmv = {
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c b/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c
index 1f8f073f27be..68f0ad1b637d 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c
+++ b/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c
@@ -18,31 +18,44 @@ enum {
         UNUSED = 0,
 
         /* board specific interrupt sources */
-        AX88796,          /* Ethernet controller */
-        CF,               /* Compact Flash */
-        PSW,              /* Push Switch */
-        EXT1,             /* EXT1n IRQ */
-        EXT4,             /* EXT4n IRQ */
+        CF,             /* Compact Flash */
+        TP,             /* Touch panel */
+        SCIF1,          /* FPGA SCIF1 */
+        SCIF0,          /* FPGA SCIF0 */
+        SMBUS,          /* SMBUS */
+        RTC,            /* RTC Alarm */
+        AX88796,        /* Ethernet controller */
+        PSW,            /* Push Switch */
+
+        /* external bus connector */
+        EXT1, EXT2, EXT4, EXT5, EXT6,
 };
 
 static struct intc_vect vectors[] __initdata = {
         INTC_IRQ(CF, IRQ_CF),
-        INTC_IRQ(PSW, IRQ_PSW),
+        INTC_IRQ(TP, IRQ_TP),
+        INTC_IRQ(SCIF1, IRQ_SCIF1),
+        INTC_IRQ(SCIF0, IRQ_SCIF0),
+        INTC_IRQ(SMBUS, IRQ_SMBUS),
+        INTC_IRQ(RTC, IRQ_RTC),
         INTC_IRQ(AX88796, IRQ_AX88796),
-        INTC_IRQ(EXT1, IRQ_EXT1),
-        INTC_IRQ(EXT4, IRQ_EXT4),
+        INTC_IRQ(PSW, IRQ_PSW),
+
+        INTC_IRQ(EXT1, IRQ_EXT1), INTC_IRQ(EXT2, IRQ_EXT2),
+        INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
+        INTC_IRQ(EXT6, IRQ_EXT6),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4000000, 0, 16, /* IRLMSK */
-          { 0, 0, 0, 0, CF, 0, 0, 0,
-            0, 0, 0, EXT4, 0, EXT1, PSW, AX88796 } },
+          { SCIF0, SCIF1, RTC, 0, CF, 0, TP, SMBUS,
+            0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } },
 };
 
 static unsigned char irl2irq[HL_NR_IRL] __initdata = {
-        0, IRQ_CF, 0, 0,
-        0, 0, 0, 0,
-        0, IRQ_EXT4, 0, IRQ_EXT1,
+        0, IRQ_CF, IRQ_TP, IRQ_SCIF1,
+        IRQ_SCIF0, IRQ_SMBUS, IRQ_RTC, IRQ_EXT6,
+        IRQ_EXT5, IRQ_EXT4, IRQ_EXT2, IRQ_EXT1,
         0, IRQ_AX88796, IRQ_PSW,
 };
 
diff --git a/arch/sh/boards/renesas/r7780rp/setup.c b/arch/sh/boards/renesas/r7780rp/setup.c
index 2f68bea7890c..a5c5e9236501 100644
--- a/arch/sh/boards/renesas/r7780rp/setup.c
+++ b/arch/sh/boards/renesas/r7780rp/setup.c
@@ -4,7 +4,7 @@
  * Renesas Solutions Highlander Support.
  *
  * Copyright (C) 2002 Atom Create Engineering Co., Ltd.
- * Copyright (C) 2005 - 2007 Paul Mundt
+ * Copyright (C) 2005 - 2008 Paul Mundt
  *
  * This contains support for the R7780RP-1, R7780MP, and R7785RP
  * Highlander modules.
@@ -17,6 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/types.h>
+#include <linux/i2c.h>
 #include <net/ax88796.h>
 #include <asm/machvec.h>
 #include <asm/r7780rp.h>
@@ -176,11 +177,38 @@ static struct platform_device ax88796_device = {
         .resource       = ax88796_resources,
 };
 
+static struct resource smbus_resources[] = {
+        [0] = {
+                .start  = PA_SMCR,
+                .end    = PA_SMCR + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_SMBUS,
+                .end    = IRQ_SMBUS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device smbus_device = {
+        .name           = "i2c-highlander",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smbus_resources),
+        .resource       = smbus_resources,
+};
+
+static struct i2c_board_info __initdata highlander_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+                .type   = "r2025sd",
+        },
+};
 
 static struct platform_device *r7780rp_devices[] __initdata = {
         &r8a66597_usb_host_device,
         &m66592_usb_peripheral_device,
         &heartbeat_device,
+        &smbus_device,
 #ifndef CONFIG_SH_R7780RP
         &ax88796_device,
 #endif
@@ -199,12 +227,20 @@ static struct trapped_io cf_trapped_io = {
 
 static int __init r7780rp_devices_setup(void)
 {
+        int ret = 0;
+
 #ifndef CONFIG_SH_R7780RP
         if (register_trapped_io(&cf_trapped_io) == 0)
-                platform_device_register(&cf_ide_device);
+                ret |= platform_device_register(&cf_ide_device);
 #endif
-        return platform_add_devices(r7780rp_devices,
+
+        ret |= platform_add_devices(r7780rp_devices,
                                     ARRAY_SIZE(r7780rp_devices));
+
+        ret |= i2c_register_board_info(0, highlander_i2c_devices,
+                                       ARRAY_SIZE(highlander_i2c_devices));
+
+        return ret;
 }
 device_initcall(r7780rp_devices_setup);
 
diff --git a/arch/sh/boards/se/7721/Makefile b/arch/sh/boards/se/7721/Makefile
new file mode 100644
index 000000000000..7f09030980b3
--- /dev/null
+++ b/arch/sh/boards/se/7721/Makefile
@@ -0,0 +1 @@
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/se/7721/irq.c b/arch/sh/boards/se/7721/irq.c
new file mode 100644
index 000000000000..c4fdd622bf8b
--- /dev/null
+++ b/arch/sh/boards/se/7721/irq.c
@@ -0,0 +1,45 @@
+/*
+ * linux/arch/sh/boards/se/7721/irq.c
+ *
+ * Copyright (C) 2008  Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <asm/se7721.h>
+
+enum {
+        UNUSED = 0,
+
+        /* board specific interrupt sources */
+        MRSHPC,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_IRQ(MRSHPC, MRSHPC_IRQ0),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { FPGA_ILSR6, 0, 8, 4, /* IRLMSK */
+          { 0, MRSHPC } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors,
+                         NULL, NULL, prio_registers, NULL);
+
+/*
+ * Initialize IRQ setting
+ */
+void __init init_se7721_IRQ(void)
+{
+        /* PPCR */
+        ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118);
+
+        register_intc_controller(&intc_desc);
+        intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0);
+}
diff --git a/arch/sh/boards/se/7721/setup.c b/arch/sh/boards/se/7721/setup.c
new file mode 100644
index 000000000000..1be3e92752f7
--- /dev/null
+++ b/arch/sh/boards/se/7721/setup.c
@@ -0,0 +1,99 @@
+/*
+ * linux/arch/sh/boards/se/7721/setup.c
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <asm/machvec.h>
+#include <asm/se7721.h>
+#include <asm/io.h>
+#include <asm/heartbeat.h>
+
+static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
+
+static struct heartbeat_data heartbeat_data = {
+        .bit_pos        = heartbeat_bit_pos,
+        .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
+        .regsize        = 16,
+};
+
+static struct resource heartbeat_resources[] = {
+        [0] = {
+                .start  = PA_LED,
+                .end    = PA_LED,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device heartbeat_device = {
+        .name           = "heartbeat",
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &heartbeat_data,
+        },
+        .num_resources  = ARRAY_SIZE(heartbeat_resources),
+        .resource       = heartbeat_resources,
+};
+
+static struct resource cf_ide_resources[] = {
+        [0] = {
+                .start  = PA_MRSHPC_IO + 0x1f0,
+                .end    = PA_MRSHPC_IO + 0x1f0 + 8 ,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                .start  = PA_MRSHPC_IO + 0x1f0 + 0x206,
+                .end    = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
+                .flags  = IORESOURCE_IO,
+        },
+        [2] = {
+                .start  = MRSHPC_IRQ0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cf_ide_device = {
+        .name           = "pata_platform",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(cf_ide_resources),
+        .resource       = cf_ide_resources,
+};
+
+static struct platform_device *se7721_devices[] __initdata = {
+        &cf_ide_device,
+        &heartbeat_device
+};
+
+static int __init se7721_devices_setup(void)
+{
+        return platform_add_devices(se7721_devices,
+                ARRAY_SIZE(se7721_devices));
+}
+device_initcall(se7721_devices_setup);
+
+static void __init se7721_setup(char **cmdline_p)
+{
+        /* for USB */
+        ctrl_outw(0x0000, 0xA405010C);  /* PGCR */
+        ctrl_outw(0x0000, 0xA405010E);  /* PHCR */
+        ctrl_outw(0x00AA, 0xA4050118);  /* PPCR */
+        ctrl_outw(0x0000, 0xA4050124);  /* PSELA */
+}
+
+/*
+ * The Machine Vector
+ */
+struct sh_machine_vector mv_se7721 __initmv = {
+        .mv_name                = "Solution Engine 7721",
+        .mv_setup               = se7721_setup,
+        .mv_nr_irqs             = 109,
+        .mv_init_irq            = init_se7721_IRQ,
+};
diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/se/7722/setup.c
index b1a3d9d0172f..33f6ee71f848 100644
--- a/arch/sh/boards/se/7722/setup.c
+++ b/arch/sh/boards/se/7722/setup.c
@@ -13,10 +13,12 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
+#include <linux/input.h>
 #include <asm/machvec.h>
 #include <asm/se7722.h>
 #include <asm/io.h>
 #include <asm/heartbeat.h>
+#include <asm/sh_keysc.h>
 
 /* Heartbeat */
 static struct heartbeat_data heartbeat_data = {
@@ -92,10 +94,47 @@ static struct platform_device cf_ide_device  = {
         .resource       = cf_ide_resources,
 };
 
+static struct sh_keysc_info sh_keysc_info = {
+        .mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */
+        .scan_timing = 3,
+        .delay = 5,
+        .keycodes = { /* SW1 -> SW30 */
+                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
+                KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
+                KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
+                KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T,
+                KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y,
+                KEY_Z,
+                KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */
+        },
+};
+
+static struct resource sh_keysc_resources[] = {
+        [0] = {
+                .start  = 0x044b0000,
+                .end    = 0x044b000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 79,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sh_keysc_device = {
+        .name           = "sh_keysc",
+        .num_resources  = ARRAY_SIZE(sh_keysc_resources),
+        .resource       = sh_keysc_resources,
+        .dev    = {
+                .platform_data  = &sh_keysc_info,
+        },
+};
+
 static struct platform_device *se7722_devices[] __initdata = {
         &heartbeat_device,
         &smc91x_eth_device,
         &cf_ide_device,
+        &sh_keysc_device,
 };
 
 static int __init se7722_devices_setup(void)
@@ -136,6 +175,8 @@ static void __init se7722_setup(char **cmdline_p)
         ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */
         ctrl_outw(0x0000, PORT_PYCR);
         ctrl_outw(0x0000, PORT_PZCR);
+        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+        ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
 }
 
 /*
diff --git a/arch/sh/configs/se7721_defconfig b/arch/sh/configs/se7721_defconfig
new file mode 100644
index 000000000000..f3d4ca0caa46
--- /dev/null
+++ b/arch/sh/configs/se7721_defconfig
@@ -0,0 +1,1085 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc5
+# Fri Mar 21 12:05:31 2008
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_BUG is not set
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System type
+#
+CONFIG_CPU_SH3=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+CONFIG_CPU_SUBTYPE_SH7721=y
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_MEMORY_SIZE=0x02000000
+CONFIG_29BIT=y
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_SH_FPU_EMU is not set
+# CONFIG_SH_DSP is not set
+# CONFIG_SH_ADC is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_DSP=y
+
+#
+# Board support
+#
+CONFIG_SOLUTION_ENGINE=y
+CONFIG_SH_7721_SOLUTION_ENGINE=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
+CONFIG_SH_PCLK_FREQ=33333333
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/sda2"
+
+#
+# Bus options
+#
+CONFIG_CF_ENABLER=y
+# CONFIG_CF_AREA5 is not set
+CONFIG_CF_AREA6=y
+CONFIG_CF_BASE_ADDR=0xb8000000
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+# CONFIG_NET_SCH_RR is not set
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_MV is not set
+CONFIG_PATA_PLATFORM=y
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=2
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_CODEPAGE_932=y
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DEBUG_BOOTMEM is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_4KSTACKS is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_SH_KGDB is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c
index 1c3b99642e1c..01ff4d05aab0 100644
--- a/arch/sh/kernel/cf-enabler.c
+++ b/arch/sh/kernel/cf-enabler.c
@@ -83,6 +83,8 @@ static int __init cf_init_default(void)
 #include <asm/se.h>
 #elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
 #include <asm/se7722.h>
+#elif defined(CONFIG_SH_7721_SOLUTION_ENGINE)
+#include <asm/se7721.h>
 #endif
 
 /*
@@ -99,7 +101,9 @@ static int __init cf_init_default(void)
  * 0xB0600000 : I/O
  */
 
-#if defined(CONFIG_SH_SOLUTION_ENGINE) || defined(CONFIG_SH_7722_SOLUTION_ENGINE) 
+#if defined(CONFIG_SH_SOLUTION_ENGINE) || \
+    defined(CONFIG_SH_7722_SOLUTION_ENGINE) || \
+    defined(CONFIG_SH_7721_SOLUTION_ENGINE)
 static int __init cf_init_se(void)
 {
         if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
@@ -112,7 +116,7 @@ static int __init cf_init_se(void)
         }
 
         /*
-         *  PC-Card window open 
+         *  PC-Card window open
          *  flag == COMMON/ATTRIBUTE/IO
          */
         /* common window open */
@@ -122,7 +126,7 @@ static int __init cf_init_se(void)
                 ctrl_outw(0x0b00, MRSHPC_MW0CR2);
         else
                 /* common mode & bus width 16bit SWAP = 0*/
-                ctrl_outw(0x0300, MRSHPC_MW0CR2); 
+                ctrl_outw(0x0300, MRSHPC_MW0CR2);
 
         /* attribute window open */
         ctrl_outw(0x8a85, MRSHPC_MW1CR1);
@@ -155,10 +159,9 @@ static int __init cf_init_se(void)
 
 int __init cf_init(void)
 {
-        if( mach_is_se() || mach_is_7722se() ){
+        if (mach_is_se() || mach_is_7722se() || mach_is_7721se())
                 return cf_init_se();
-        }
-        
+
         return cf_init_default();
 }
 
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index b279cdc3a233..7e2b90cfa7bf 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -8,6 +8,7 @@ common-y	+= $(addprefix ../sh2/, ex.o entry.o)
 
 obj-$(CONFIG_SH_FPU)    += fpu.o
 
-obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7206)        += setup-sh7206.o clock-sh7206.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7203)        += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7263)        += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_MXG)           += setup-mxg.o clock-sh7206.o
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 6910e2664468..6e79132f6f30 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -29,6 +29,9 @@ int __init detect_cpu_and_cache_system(void)
         boot_cpu_data.type                      = CPU_SH7206;
         /* While SH7206 has a DSP.. */
         boot_cpu_data.flags                     |= CPU_HAS_DSP;
+#elif defined(CONFIG_CPU_SUBTYPE_MXG)
+        boot_cpu_data.type                      = CPU_MXG;
+        boot_cpu_data.flags                     |= CPU_HAS_DSP;
 #endif
 
         boot_cpu_data.dcache.ways               = 4;
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
new file mode 100644
index 000000000000..e611d79fac4c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -0,0 +1,168 @@
+/*
+ * Renesas MX-G (R8A03022BG) Setup
+ *
+ *  Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+        IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
+
+        PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
+
+        SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
+
+        SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
+        SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
+
+        MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+        MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
+        MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
+        MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+        MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
+        MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
+        MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
+
+        /* interrupt groups */
+        PINT, SCIF0, SCIF1,
+        MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
+        INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
+        INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
+        INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
+        INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
+        INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
+        INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
+        INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
+
+        INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
+        INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
+        INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
+        INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
+
+        INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
+        INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
+        INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
+        INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
+
+        INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221),
+        INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223),
+        INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225),
+        INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227),
+
+        INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229),
+        INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231),
+        INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233),
+
+        INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235),
+        INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237),
+        INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239),
+
+        INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241),
+        INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243),
+
+        INTC_IRQ(MTU2_TGI3B, 244),
+        INTC_IRQ(MTU2_TGI3C, 245),
+
+        INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247),
+        INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249),
+        INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251),
+
+        INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253),
+        INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
+                   PINT4, PINT5, PINT6, PINT7),
+        INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+                   MTU2_TCI0V, MTU2_TGI0E),
+        INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
+                   MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
+        INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+                   MTU2_TGI3A),
+        INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
+                   MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
+        INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
+        INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
+        INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
+        { 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
+        { 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
+        { 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
+        { 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
+        { 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
+        { 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
+        { 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
+        { 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
+        { 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
+        { 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
+        { 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
+        { 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
+        { 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
+        { 0xfffd9812, 0, 16, 4, /* IPR15 */
+                { SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
+        { 0xfffd9814, 0, 16, 4, /* IPR16 */
+                { MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xfffd9408, 0, 16, /* PINTER */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
+                         mask_registers, prio_registers, NULL);
+
+static struct plat_sci_port sci_platform_data[] = {
+        {
+                .mapbase        = 0xff804000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 223, 220, 221, 222 },
+        }, {
+                .flags = 0,
+        }
+};
+
+static struct platform_device sci_device = {
+        .name           = "sh-sci",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = sci_platform_data,
+        },
+};
+
+static struct platform_device *mxg_devices[] __initdata = {
+        &sci_device,
+};
+
+static int __init mxg_devices_setup(void)
+{
+        return platform_add_devices(mxg_devices,
+                                    ARRAY_SIZE(mxg_devices));
+}
+__initcall(mxg_devices_setup);
+
+void __init plat_irq_setup(void)
+{
+        register_intc_controller(&intc_desc);
+}
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 9e89984c4f1d..ebceb0dadff5 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -53,7 +53,7 @@ int __init detect_cpu_and_cache_system(void)
         /*
          * Setup some generic flags we can probe on SH-4A parts
          */
-        if (((pvr >> 16) & 0xff) == 0x10) {
+        if (((pvr >> 24) & 0xff) == 0x10) {
                 if ((cvr & 0x10000000) == 0)
                         boot_cpu_data.flags |= CPU_HAS_DSP;
 
@@ -126,17 +126,22 @@ int __init detect_cpu_and_cache_system(void)
                                           CPU_HAS_LLSC;
                 break;
         case 0x3008:
-                if (prr == 0xa0 || prr == 0xa1) {
-                        boot_cpu_data.type = CPU_SH7722;
-                        boot_cpu_data.icache.ways = 4;
-                        boot_cpu_data.dcache.ways = 4;
-                        boot_cpu_data.flags |= CPU_HAS_LLSC;
-                }
-                else if (prr == 0x70) {
+                boot_cpu_data.icache.ways = 4;
+                boot_cpu_data.dcache.ways = 4;
+                boot_cpu_data.flags |= CPU_HAS_LLSC;
+
+                switch (prr) {
+                case 0x50:
+                        boot_cpu_data.type = CPU_SH7723;
+                        boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
+                        break;
+                case 0x70:
                         boot_cpu_data.type = CPU_SH7366;
-                        boot_cpu_data.icache.ways = 4;
-                        boot_cpu_data.dcache.ways = 4;
-                        boot_cpu_data.flags |= CPU_HAS_LLSC;
+                        break;
+                case 0xa0:
+                case 0xa1:
+                        boot_cpu_data.type = CPU_SH7722;
+                        break;
                 }
                 break;
         case 0x4000:    /* 1st cut */
@@ -215,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
          * SH-4A's have an optional PIPT L2.
          */
         if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+                /* Bug if we can't decode the L2 info */
+                BUG_ON(!(cvr & 0xf));
+
+                /* Silicon and specifications have clearly never met.. */
+                cvr ^= 0xf;
+
                 /*
                  * Size calculation is much more sensible
                  * than it is for the L1.
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 5d890ac8e793..a880e7968750 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780)	+= setup-sh7780.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)        += setup-sh7785.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)        += setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)        += setup-sh7722.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7723)        += setup-sh7723.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7366)        += setup-sh7366.o
 obj-$(CONFIG_CPU_SUBTYPE_SHX3)          += setup-shx3.o
 
@@ -22,6 +23,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780)	:= clock-sh7780.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7785)      := clock-sh7785.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7343)      := clock-sh7343.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7722)      := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7723)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7366)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SHX3)        := clock-shx3.o
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index b98b4bc93ec9..069314037049 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -16,13 +16,12 @@
 
 static struct resource usbf_resources[] = {
         [0] = {
-                .name   = "m66592_udc",
-                .start  = 0xA4480000,
-                .end    = 0xA44800FF,
+                .name   = "USBF",
+                .start  = 0x04480000,
+                .end    = 0x044800FF,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .name   = "m66592_udc",
                 .start  = 65,
                 .end    = 65,
                 .flags  = IORESOURCE_IRQ,
@@ -40,6 +39,26 @@ static struct platform_device usbf_device = {
         .resource       = usbf_resources,
 };
 
+static struct resource iic_resources[] = {
+        [0] = {
+                .name   = "IIC",
+                .start  = 0x04470000,
+                .end    = 0x04470017,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .end    = 99,
+                .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic_device = {
+        .name           = "i2c-sh_mobile",
+        .num_resources  = ARRAY_SIZE(iic_resources),
+        .resource       = iic_resources,
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffe00000,
@@ -74,6 +93,7 @@ static struct platform_device sci_device = {
 
 static struct platform_device *sh7722_devices[] __initdata = {
         &usbf_device,
+        &iic_device,
         &sci_device,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
new file mode 100644
index 000000000000..16925cf28db8
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -0,0 +1,300 @@
+/*
+ * SH7723 Setup
+ *
+ *  Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/mm.h>
+#include <linux/serial_sci.h>
+#include <asm/mmzone.h>
+
+static struct plat_sci_port sci_platform_data[] = {
+        {
+                .mapbase        = 0xa4e30000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCI,
+                .irqs           = { 56, 56, 56, 56 },
+        },{
+                .mapbase        = 0xa4e40000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCI,
+                .irqs           = { 88, 88, 88, 88 },
+        },{
+                .mapbase        = 0xa4e50000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCI,
+                .irqs           = { 109, 109, 109, 109 },
+        }, {
+                .flags = 0,
+        }
+};
+
+static struct platform_device sci_device = {
+        .name           = "sh-sci",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = sci_platform_data,
+        },
+};
+
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = 0xa465fec0,
+                .end    = 0xa465fec0 + 0x58 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                /* Period IRQ */
+                .start  = 69,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* Carry IRQ */
+                .start  = 70,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                /* Alarm IRQ */
+                .start  = 68,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device rtc_device = {
+        .name           = "sh-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
+        .resource       = rtc_resources,
+};
+
+static struct platform_device *sh7723_devices[] __initdata = {
+        &sci_device,
+        &rtc_device,
+};
+
+static int __init sh7723_devices_setup(void)
+{
+        return platform_add_devices(sh7723_devices,
+                                    ARRAY_SIZE(sh7723_devices));
+}
+__initcall(sh7723_devices_setup);
+
+enum {
+        UNUSED=0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+        HUDI,
+        DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
+        _2DG_TRI,_2DG_INI,_2DG_CEI,
+        DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
+        VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
+        SCIFA_SCIFA0,
+        VPU_VPUI,
+        TPU_TPUI,
+        ADC_ADI,
+        USB_USI0,
+        RTC_ATI,RTC_PRI,RTC_CUI,
+        DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
+        DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
+        KEYSC_KEYI,
+        SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
+        MSIOF_MSIOFI0,MSIOF_MSIOFI1,
+        SCIFA_SCIFA1,
+        FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
+        I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
+        SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
+        CMT_CMTI,
+        TSIF_TSIFI,
+        SIU_SIUI,
+        SCIFA_SCIFA2,
+        TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
+        IRDA_IRDAI,
+        ATAPI_ATAPII,
+        SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
+        VEU2H1_VEU2HI,
+        LCDC_LCDCI,
+        TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
+
+        /* interrupt groups */
+        DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
+        SDHI1, RTC, DMAC1B, SDHI0,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
+        INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
+        INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
+        INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
+
+        INTC_VECT(DMAC1A_DEI0,0x700),
+        INTC_VECT(DMAC1A_DEI1,0x720),
+        INTC_VECT(DMAC1A_DEI2,0x740),
+        INTC_VECT(DMAC1A_DEI3,0x760),
+
+        INTC_VECT(_2DG_TRI, 0x780),
+        INTC_VECT(_2DG_INI, 0x7A0),
+        INTC_VECT(_2DG_CEI, 0x7C0),
+
+        INTC_VECT(DMAC0A_DEI0,0x800),
+        INTC_VECT(DMAC0A_DEI1,0x820),
+        INTC_VECT(DMAC0A_DEI2,0x840),
+        INTC_VECT(DMAC0A_DEI3,0x860),
+
+        INTC_VECT(VIO_CEUI,0x880),
+        INTC_VECT(VIO_BEUI,0x8A0),
+        INTC_VECT(VIO_VEU2HI,0x8C0),
+        INTC_VECT(VIO_VOUI,0x8E0),
+
+        INTC_VECT(SCIFA_SCIFA0,0x900),
+        INTC_VECT(VPU_VPUI,0x920),
+        INTC_VECT(TPU_TPUI,0x9A0),
+        INTC_VECT(ADC_ADI,0x9E0),
+        INTC_VECT(USB_USI0,0xA20),
+
+        INTC_VECT(RTC_ATI,0xA80),
+        INTC_VECT(RTC_PRI,0xAA0),
+        INTC_VECT(RTC_CUI,0xAC0),
+
+        INTC_VECT(DMAC1B_DEI4,0xB00),
+        INTC_VECT(DMAC1B_DEI5,0xB20),
+        INTC_VECT(DMAC1B_DADERR,0xB40),
+
+        INTC_VECT(DMAC0B_DEI4,0xB80),
+        INTC_VECT(DMAC0B_DEI5,0xBA0),
+        INTC_VECT(DMAC0B_DADERR,0xBC0),
+
+        INTC_VECT(KEYSC_KEYI,0xBE0),
+        INTC_VECT(SCIF_SCIF0,0xC00),
+        INTC_VECT(SCIF_SCIF1,0xC20),
+        INTC_VECT(SCIF_SCIF2,0xC40),
+        INTC_VECT(MSIOF_MSIOFI0,0xC80),
+        INTC_VECT(MSIOF_MSIOFI1,0xCA0),
+        INTC_VECT(SCIFA_SCIFA1,0xD00),
+
+        INTC_VECT(FLCTL_FLSTEI,0xD80),
+        INTC_VECT(FLCTL_FLTENDI,0xDA0),
+        INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
+        INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
+
+        INTC_VECT(I2C_ALI,0xE00),
+        INTC_VECT(I2C_TACKI,0xE20),
+        INTC_VECT(I2C_WAITI,0xE40),
+        INTC_VECT(I2C_DTEI,0xE60),
+
+        INTC_VECT(SDHI0_SDHII0,0xE80),
+        INTC_VECT(SDHI0_SDHII1,0xEA0),
+        INTC_VECT(SDHI0_SDHII2,0xEC0),
+
+        INTC_VECT(CMT_CMTI,0xF00),
+        INTC_VECT(TSIF_TSIFI,0xF20),
+        INTC_VECT(SIU_SIUI,0xF80),
+        INTC_VECT(SCIFA_SCIFA2,0xFA0),
+
+        INTC_VECT(TMU0_TUNI0,0x400),
+        INTC_VECT(TMU0_TUNI1,0x420),
+        INTC_VECT(TMU0_TUNI2,0x440),
+
+        INTC_VECT(IRDA_IRDAI,0x480),
+        INTC_VECT(ATAPI_ATAPII,0x4A0),
+
+        INTC_VECT(SDHI1_SDHII0,0x4E0),
+        INTC_VECT(SDHI1_SDHII1,0x500),
+        INTC_VECT(SDHI1_SDHII2,0x520),
+
+        INTC_VECT(VEU2H1_VEU2HI,0x560),
+        INTC_VECT(LCDC_LCDCI,0x580),
+
+        INTC_VECT(TMU1_TUNI0,0x920),
+        INTC_VECT(TMU1_TUNI1,0x940),
+        INTC_VECT(TMU1_TUNI2,0x960),
+
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
+        INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
+        INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
+        INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
+        INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
+        INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
+        INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
+        INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
+        INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
+        INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
+        INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
+          { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
+        { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
+          { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
+        { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
+          { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
+        { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
+          { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
+        { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
+          { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
+        { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
+          { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
+        { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
+          { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
+        { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
+          { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
+            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+        { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
+          { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
+        { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
+          { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
+        { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
+          { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
+        { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
+          { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
+        { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
+          { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
+        { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
+        { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
+        { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
+        { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
+        { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
+        { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
+        { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
+        { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
+        { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
+        { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
+        { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
+        { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
+        { 0xa4140010, 0, 32, 4, /* INTPRI00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+        { 0xa414001c, 16, 2, /* ICR1 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
+                         mask_registers, prio_registers, sense_registers);
+
+void __init plat_irq_setup(void)
+{
+        register_intc_controller(&intc_desc);
+}
+
+void __init plat_mem_setup(void)
+{
+        /* Register the URAM space as Node 1 */
+        setup_bootmem_node(1, 0x055f0000, 0x05610000);
+}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 07c988dc9de6..ae2b22219f02 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -231,12 +231,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
 };
 
-static struct intc_prio priorities[] __initdata = {
-        INTC_PRIO(SCIF0, 3),
-        INTC_PRIO(SCIF1, 3),
-        INTC_PRIO(SCIF2, 3),
-};
-
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
           { 0, 0, 0, 0, 0, 0, GPIO, 0,
@@ -270,11 +264,10 @@ static struct intc_prio_reg prio_registers[] __initdata = {
         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 };
 
-static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, priorities,
+static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
 /* Support for external interrupt pins in IRQ mode */
-
 static struct intc_vect irq_vectors[] __initdata = {
         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
@@ -302,7 +295,6 @@ static DECLARE_INTC_DESC(intc_irq_desc, "sh7763-irq", irq_vectors,
                          irq_sense_registers);
 
 /* External interrupt pins in IRL mode */
-
 static struct intc_vect irl_vectors[] __initdata = {
         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index b9cec48b1808..b73578ee295d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -1,7 +1,7 @@
 /*
  * SH7770 Setup
  *
- *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2006 - 2008  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -29,6 +29,41 @@ static struct plat_sci_port sci_platform_data[] = {
                 .type           = PORT_SCIF,
                 .irqs           = { 63, 63, 63, 63 },
         }, {
+                .mapbase        = 0xff926000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 64, 64, 64, 64 },
+        }, {
+                .mapbase        = 0xff927000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 65, 65, 65, 65 },
+        }, {
+                .mapbase        = 0xff928000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 66, 66, 66, 66 },
+        }, {
+                .mapbase        = 0xff929000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 67, 67, 67, 67 },
+        }, {
+                .mapbase        = 0xff92a000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 68, 68, 68, 68 },
+        }, {
+                .mapbase        = 0xff92b000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 69, 69, 69, 69 },
+        }, {
+                .mapbase        = 0xff92c000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 70, 70, 70, 70 },
+        }, {
                 .flags = 0,
         }
 };
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index ff4f54a47c07..284f66f1ebbe 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -23,6 +23,8 @@
 #include <linux/kexec.h>
 #include <linux/module.h>
 #include <linux/smp.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/page.h>
@@ -333,6 +335,7 @@ static const char *cpu_name[] = {
         [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
         [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
         [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
+        [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
         [CPU_SH7366]    = "SH7366",     [CPU_SH_NONE]   = "Unknown"
 };
 
@@ -443,3 +446,15 @@ const struct seq_operations cpuinfo_op = {
         .show   = show_cpuinfo,
 };
 #endif /* CONFIG_PROC_FS */
+
+struct dentry *sh_debugfs_root;
+
+static int __init sh_debugfs_init(void)
+{
+        sh_debugfs_root = debugfs_create_dir("sh", NULL);
+        if (IS_ERR(sh_debugfs_root))
+                return PTR_ERR(sh_debugfs_root);
+
+        return 0;
+}
+arch_initcall(sh_debugfs_init);
diff --git a/arch/sh/lib/clear_page.S b/arch/sh/lib/clear_page.S
index 3539123fe517..8342bfbde64c 100644
--- a/arch/sh/lib/clear_page.S
+++ b/arch/sh/lib/clear_page.S
@@ -27,11 +27,11 @@ ENTRY(clear_page)
         mov     #0,r0
         !
 1:
-#if defined(CONFIG_CPU_SH3)
-        mov.l   r0,@r4
-#elif defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4)
         movca.l r0,@r4
         mov     r4,r1
+#else
+        mov.l   r0,@r4
 #endif
         add     #32,r4
         mov.l   r0,@-r4
diff --git a/arch/sh/lib/copy_page.S b/arch/sh/lib/copy_page.S
index e002b91c8752..5d12e657be34 100644
--- a/arch/sh/lib/copy_page.S
+++ b/arch/sh/lib/copy_page.S
@@ -41,11 +41,11 @@ ENTRY(copy_page)
         mov.l   @r11+,r5
         mov.l   @r11+,r6
         mov.l   @r11+,r7
-#if defined(CONFIG_CPU_SH3)
-        mov.l   r0,@r10
-#elif defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4)
         movca.l r0,@r10
         mov     r10,r0
+#else
+        mov.l   r0,@r10
 #endif
         add     #32,r10
         mov.l   r7,@-r10
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index db6d950b6f5e..c5b56d52b7d2 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -127,13 +127,13 @@ static int __init cache_debugfs_init(void)
 {
         struct dentry *dcache_dentry, *icache_dentry;
 
-        dcache_dentry = debugfs_create_file("dcache", S_IRUSR, NULL,
+        dcache_dentry = debugfs_create_file("dcache", S_IRUSR, sh_debugfs_root,
                                             (unsigned int *)CACHE_TYPE_DCACHE,
                                             &cache_debugfs_fops);
         if (IS_ERR(dcache_dentry))
                 return PTR_ERR(dcache_dentry);
 
-        icache_dentry = debugfs_create_file("icache", S_IRUSR, NULL,
+        icache_dentry = debugfs_create_file("icache", S_IRUSR, sh_debugfs_root,
                                             (unsigned int *)CACHE_TYPE_ICACHE,
                                             &cache_debugfs_fops);
         if (IS_ERR(icache_dentry)) {
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index ab81c602295f..0b0ec6e04753 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -393,7 +393,7 @@ static int __init pmb_debugfs_init(void)
         struct dentry *dentry;
 
         dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
-                                     NULL, NULL, &pmb_debugfs_fops);
+                                     sh_debugfs_root, NULL, &pmb_debugfs_fops);
         if (IS_ERR(dentry))
                 return PTR_ERR(dentry);
 
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index d63b93da952d..987c6682bf99 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -21,8 +21,9 @@ HD64465			HD64465
 7206SE                  SH_7206_SOLUTION_ENGINE
 7343SE                  SH_7343_SOLUTION_ENGINE
 7619SE                  SH_7619_SOLUTION_ENGINE
-7722SE                  SH_7722_SOLUTION_ENGINE         
-7751SE                  SH_7751_SOLUTION_ENGINE         
+7721SE                  SH_7721_SOLUTION_ENGINE
+7722SE                  SH_7722_SOLUTION_ENGINE
+7751SE                  SH_7751_SOLUTION_ENGINE
 7780SE                  SH_7780_SOLUTION_ENGINE
 7751SYSTEMH             SH_7751_SYSTEMH
 HP6XX                   SH_HP6XX
diff --git a/arch/sparc/kernel/time.c b/arch/sparc/kernel/time.c
index cfaf22c05bc4..53caacbb3982 100644
--- a/arch/sparc/kernel/time.c
+++ b/arch/sparc/kernel/time.c
@@ -105,7 +105,7 @@ __volatile__ unsigned int *master_l10_limit;
 
 #define TICK_SIZE (tick_nsec / 1000)
 
-irqreturn_t timer_interrupt(int irq, void *dev_id)
+static irqreturn_t timer_interrupt(int dummy, void *dev_id)
 {
         /* last time the cmos clock got updated */
         static long last_rtc_update;
diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig
index 463d1be32c98..2667a9dee11d 100644
--- a/arch/sparc64/Kconfig
+++ b/arch/sparc64/Kconfig
@@ -16,6 +16,7 @@ config SPARC64
         bool
         default y
         select HAVE_IDE
+        select HAVE_LMB
         help
           SPARC is a family of RISC microprocessors designed and marketed by
           Sun Microsystems, incorporated.  This port covers the newer 64-bit
diff --git a/arch/sparc64/kernel/sys_sparc32.c b/arch/sparc64/kernel/sys_sparc32.c
index 2455fa498876..c1a61e98899a 100644
--- a/arch/sparc64/kernel/sys_sparc32.c
+++ b/arch/sparc64/kernel/sys_sparc32.c
@@ -55,7 +55,6 @@
 #include <asm/types.h>
 #include <asm/uaccess.h>
 #include <asm/fpumacro.h>
-#include <asm/semaphore.h>
 #include <asm/mmu_context.h>
 #include <asm/compat_signal.h>
 
diff --git a/arch/v850/kernel/syscalls.c b/arch/v850/kernel/syscalls.c
index 0a4df4d6e05f..003db9c8c44a 100644
--- a/arch/v850/kernel/syscalls.c
+++ b/arch/v850/kernel/syscalls.c
@@ -30,7 +30,6 @@
 #include <linux/file.h>
 
 #include <asm/uaccess.h>
-#include <asm/semaphore.h>
 #include <asm/unistd.h>
 
 /*
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 2a59dbb28248..87a693cf2bb7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -117,6 +117,9 @@ config ARCH_HAS_CPU_RELAX
 config HAVE_SETUP_PER_CPU_AREA
         def_bool X86_64 || (X86_SMP && !X86_VOYAGER)
 
+config HAVE_CPUMASK_OF_CPU_MAP
+        def_bool X86_64_SMP
+
 config ARCH_HIBERNATION_POSSIBLE
         def_bool y
         depends on !SMP || !X86_VOYAGER
@@ -903,6 +906,15 @@ config X86_64_ACPI_NUMA
         help
           Enable ACPI SRAT based node topology detection.
 
+# Some NUMA nodes have memory ranges that span
+# other nodes.  Even though a pfn is valid and
+# between a node's start and end pfns, it may not
+# reside on that node.  See memmap_init_zone()
+# for details.
+config NODES_SPAN_OTHER_NODES
+        def_bool y
+        depends on X86_64_ACPI_NUMA
+
 config NUMA_EMU
         bool "NUMA emulation"
         depends on X86_64 && NUMA
diff --git a/arch/x86/boot/a20.c b/arch/x86/boot/a20.c
index 31348d054fca..90943f83e84d 100644
--- a/arch/x86/boot/a20.c
+++ b/arch/x86/boot/a20.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/a20.c
- *
  * Enable A20 gate (return -1 on failure)
  */
 
diff --git a/arch/x86/boot/apm.c b/arch/x86/boot/apm.c
index c117c7fb859c..7aa6033001f9 100644
--- a/arch/x86/boot/apm.c
+++ b/arch/x86/boot/apm.c
@@ -12,8 +12,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/apm.c
- *
  * Get APM BIOS information
  */
 
diff --git a/arch/x86/boot/bitops.h b/arch/x86/boot/bitops.h
index 8dcc8dc7db88..878e4b9940d9 100644
--- a/arch/x86/boot/bitops.h
+++ b/arch/x86/boot/bitops.h
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/bitops.h
- *
  * Very simple bitops for the boot code.
  */
 
diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h
index 09578070bfba..a34b9982c7cb 100644
--- a/arch/x86/boot/boot.h
+++ b/arch/x86/boot/boot.h
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/boot.h
- *
  * Header file for the real-mode kernel code
  */
 
diff --git a/arch/x86/boot/cmdline.c b/arch/x86/boot/cmdline.c
index 680408a0f463..a1d35634bce0 100644
--- a/arch/x86/boot/cmdline.c
+++ b/arch/x86/boot/cmdline.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/cmdline.c
- *
  * Simple command-line parser for early boot.
  */
 
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index 036e635f18a3..ba7736cf2ec7 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -130,7 +130,7 @@ relocated:
 /*
  * Setup the stack for the decompressor
  */
-        leal stack_end(%ebx), %esp
+        leal boot_stack_end(%ebx), %esp
 
 /*
  * Do the decompression, and jump to the new kernel..
@@ -142,8 +142,8 @@ relocated:
         pushl %eax      # input_len
         leal input_data(%ebx), %eax
         pushl %eax      # input_data
-        leal _end(%ebx), %eax
-        pushl %eax      # end of the image as third argument
+        leal boot_heap(%ebx), %eax
+        pushl %eax      # heap area as third argument
         pushl %esi      # real mode pointer as second arg
         call decompress_kernel
         addl $20, %esp
@@ -181,7 +181,10 @@ relocated:
         jmp *%ebp
 
 .bss
+/* Stack and heap for uncompression */
 .balign 4
-stack:
-        .fill 4096, 1, 0
-stack_end:
+boot_heap:
+        .fill BOOT_HEAP_SIZE, 1, 0
+boot_stack:
+        .fill BOOT_STACK_SIZE, 1, 0
+boot_stack_end:
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index e8657b98c902..d8819efac81d 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -28,6 +28,7 @@
 #include <asm/segment.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
+#include <asm/boot.h>
 #include <asm/msr.h>
 #include <asm/asm-offsets.h>
 
@@ -62,7 +63,7 @@ startup_32:
         subl    $1b, %ebp
 
 /* setup a stack and make sure cpu supports long mode. */
-        movl    $user_stack_end, %eax
+        movl    $boot_stack_end, %eax
         addl    %ebp, %eax
         movl    %eax, %esp
 
@@ -243,9 +244,9 @@ ENTRY(startup_64)
 /* Copy the compressed kernel to the end of our buffer
  * where decompression in place becomes safe.
  */
-        leaq    _end(%rip), %r8
-        leaq    _end(%rbx), %r9
-        movq    $_end /* - $startup_32 */, %rcx
+        leaq    _end_before_pgt(%rip), %r8
+        leaq    _end_before_pgt(%rbx), %r9
+        movq    $_end_before_pgt /* - $startup_32 */, %rcx
 1:      subq    $8, %r8
         subq    $8, %r9
         movq    0(%r8), %rax
@@ -267,14 +268,14 @@ relocated:
  */
         xorq    %rax, %rax
         leaq    _edata(%rbx), %rdi
-        leaq    _end(%rbx), %rcx
+        leaq    _end_before_pgt(%rbx), %rcx
         subq    %rdi, %rcx
         cld
         rep
         stosb
 
         /* Setup the stack */
-        leaq    user_stack_end(%rip), %rsp
+        leaq    boot_stack_end(%rip), %rsp
 
         /* zero EFLAGS after setting rsp */
         pushq   $0
@@ -285,7 +286,7 @@ relocated:
  */
         pushq   %rsi                    # Save the real mode argument
         movq    %rsi, %rdi              # real mode address
-        leaq    _heap(%rip), %rsi       # _heap
+        leaq    boot_heap(%rip), %rsi   # malloc area for uncompression
         leaq    input_data(%rip), %rdx  # input_data
         movl    input_len(%rip), %eax
         movq    %rax, %rcx              # input_len
@@ -310,9 +311,12 @@ gdt:
         .quad   0x0080890000000000      /* TS descriptor */
         .quad   0x0000000000000000      /* TS continued */
 gdt_end:
-        .bss
-/* Stack for uncompression */
-        .balign 4
-user_stack:
-        .fill 4096,4,0
-user_stack_end:
+
+.bss
+/* Stack and heap for uncompression */
+.balign 4
+boot_heap:
+        .fill BOOT_HEAP_SIZE, 1, 0
+boot_stack:
+        .fill BOOT_STACK_SIZE, 1, 0
+boot_stack_end:
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index dad4e699f5a3..90456cee47c3 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -217,12 +217,6 @@ static void putstr(const char *);
 static memptr free_mem_ptr;
 static memptr free_mem_end_ptr;
 
-#ifdef CONFIG_X86_64
-#define HEAP_SIZE             0x7000
-#else
-#define HEAP_SIZE             0x4000
-#endif
-
 static char *vidmem;
 static int vidport;
 static int lines, cols;
@@ -449,7 +443,7 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
 
         window = output;                /* Output buffer (Normally at 1M) */
         free_mem_ptr     = heap;        /* Heap */
-        free_mem_end_ptr = heap + HEAP_SIZE;
+        free_mem_end_ptr = heap + BOOT_HEAP_SIZE;
         inbuf  = input_data;            /* Input buffer */
         insize = input_len;
         inptr  = 0;
diff --git a/arch/x86/boot/compressed/vmlinux_64.lds b/arch/x86/boot/compressed/vmlinux_64.lds
index 7e5c7209f6cc..bef1ac891bce 100644
--- a/arch/x86/boot/compressed/vmlinux_64.lds
+++ b/arch/x86/boot/compressed/vmlinux_64.lds
@@ -39,10 +39,10 @@ SECTIONS
                 *(.bss.*)
                 *(COMMON)
                 . = ALIGN(8);
-                _end = . ;
+                _end_before_pgt = . ;
                 . = ALIGN(4096);
                 pgtable = . ;
                 . = . + 4096 * 6;
-                _heap = .;
+                _ebss = .;
         }
 }
diff --git a/arch/x86/boot/copy.S b/arch/x86/boot/copy.S
index ef127e56a3cf..ef50c84e8b4b 100644
--- a/arch/x86/boot/copy.S
+++ b/arch/x86/boot/copy.S
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/copy.S
- *
  * Memory copy routines
  */
 
diff --git a/arch/x86/boot/cpucheck.c b/arch/x86/boot/cpucheck.c
index 2462c88689ed..7804389ee005 100644
--- a/arch/x86/boot/cpucheck.c
+++ b/arch/x86/boot/cpucheck.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/cpucheck.c
- *
  * Check for obligatory CPU features and abort if the features are not
  * present.  This code should be compilable as 16-, 32- or 64-bit
  * code, so be very careful with types and inline assembly.
diff --git a/arch/x86/boot/edd.c b/arch/x86/boot/edd.c
index 8721dc46a0b6..d84a48ece785 100644
--- a/arch/x86/boot/edd.c
+++ b/arch/x86/boot/edd.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/edd.c
- *
  * Get EDD BIOS disk information
  */
 
diff --git a/arch/x86/boot/install.sh b/arch/x86/boot/install.sh
index 88d77761d01b..8d60ee15dfd9 100644
--- a/arch/x86/boot/install.sh
+++ b/arch/x86/boot/install.sh
@@ -1,7 +1,5 @@
 #!/bin/sh
 #
-# arch/i386/boot/install.sh
-#
 # This file is subject to the terms and conditions of the GNU General Public
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
diff --git a/arch/x86/boot/main.c b/arch/x86/boot/main.c
index 7828da5cfd07..77569a4a3be1 100644
--- a/arch/x86/boot/main.c
+++ b/arch/x86/boot/main.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/main.c
- *
  * Main module for the real-mode kernel code
  */
 
diff --git a/arch/x86/boot/mca.c b/arch/x86/boot/mca.c
index 68222f2d4b67..911eaae5d696 100644
--- a/arch/x86/boot/mca.c
+++ b/arch/x86/boot/mca.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/mca.c
- *
  * Get the MCA system description table
  */
 
diff --git a/arch/x86/boot/memory.c b/arch/x86/boot/memory.c
index e77d89f9e8aa..acad32eb4290 100644
--- a/arch/x86/boot/memory.c
+++ b/arch/x86/boot/memory.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/memory.c
- *
  * Memory detection code
  */
 
diff --git a/arch/x86/boot/pm.c b/arch/x86/boot/pm.c
index a93cb8bded4d..328956fdb59e 100644
--- a/arch/x86/boot/pm.c
+++ b/arch/x86/boot/pm.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/pm.c
- *
  * Prepare the machine for transition to protected mode.
  */
 
diff --git a/arch/x86/boot/pmjump.S b/arch/x86/boot/pmjump.S
index f5402d51f7c3..ab049d40a884 100644
--- a/arch/x86/boot/pmjump.S
+++ b/arch/x86/boot/pmjump.S
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/pmjump.S
- *
  * The actual transition into protected mode
  */
 
diff --git a/arch/x86/boot/printf.c b/arch/x86/boot/printf.c
index 7e7e890699be..c1d00c0274c4 100644
--- a/arch/x86/boot/printf.c
+++ b/arch/x86/boot/printf.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/printf.c
- *
  * Oh, it's a waste of space, but oh-so-yummy for debugging.  This
  * version of printf() does not include 64-bit support.  "Live with
  * it."
diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c
index 481a22097781..f94b7a0c2abf 100644
--- a/arch/x86/boot/string.c
+++ b/arch/x86/boot/string.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/string.c
- *
  * Very basic string functions
  */
 
diff --git a/arch/x86/boot/tty.c b/arch/x86/boot/tty.c
index f3f14bd26371..0be77b39328a 100644
--- a/arch/x86/boot/tty.c
+++ b/arch/x86/boot/tty.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/tty.c
- *
  * Very simple screen I/O
  * XXX: Probably should add very simple serial I/O?
  */
diff --git a/arch/x86/boot/version.c b/arch/x86/boot/version.c
index c61462f7d9a7..2723d9b5ce43 100644
--- a/arch/x86/boot/version.c
+++ b/arch/x86/boot/version.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/version.c
- *
  * Kernel version string
  */
 
diff --git a/arch/x86/boot/video-bios.c b/arch/x86/boot/video-bios.c
index 39e247e96172..49f26aaaebc8 100644
--- a/arch/x86/boot/video-bios.c
+++ b/arch/x86/boot/video-bios.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/video-bios.c
- *
  * Standard video BIOS modes
  *
  * We have two options for this; silent and scanned.
diff --git a/arch/x86/boot/video-vesa.c b/arch/x86/boot/video-vesa.c
index 5d5a3f6e8b5c..401ad998ad08 100644
--- a/arch/x86/boot/video-vesa.c
+++ b/arch/x86/boot/video-vesa.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/video-vesa.c
- *
  * VESA text modes
  */
 
diff --git a/arch/x86/boot/video-vga.c b/arch/x86/boot/video-vga.c
index 330d6589a2ad..40ecb8d7688c 100644
--- a/arch/x86/boot/video-vga.c
+++ b/arch/x86/boot/video-vga.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/video-vga.c
- *
  * Common all-VGA modes
  */
 
diff --git a/arch/x86/boot/video.c b/arch/x86/boot/video.c
index c1c47ba069ef..83598b23093a 100644
--- a/arch/x86/boot/video.c
+++ b/arch/x86/boot/video.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/video.c
- *
  * Select video mode
  */
 
diff --git a/arch/x86/boot/video.h b/arch/x86/boot/video.h
index d69347f79e8e..ee63f5d14461 100644
--- a/arch/x86/boot/video.h
+++ b/arch/x86/boot/video.h
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/video.h
- *
  * Header file for the real-mode video probing code
  */
 
diff --git a/arch/x86/boot/voyager.c b/arch/x86/boot/voyager.c
index 6499e3239b41..433909d61e5c 100644
--- a/arch/x86/boot/voyager.c
+++ b/arch/x86/boot/voyager.c
@@ -9,8 +9,6 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * arch/i386/boot/voyager.c
- *
  * Get the Voyager config information
  */
 
diff --git a/arch/x86/ia32/sys_ia32.c b/arch/x86/ia32/sys_ia32.c
index 7cede7a9e0dc..f00afdf61e67 100644
--- a/arch/x86/ia32/sys_ia32.c
+++ b/arch/x86/ia32/sys_ia32.c
@@ -43,7 +43,6 @@
 #include <asm/mman.h>
 #include <asm/types.h>
 #include <asm/uaccess.h>
-#include <asm/semaphore.h>
 #include <asm/atomic.h>
 #include <asm/ia32.h>
 #include <asm/vgtod.h>
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index c3920ea8ac56..90e092d0af0c 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -22,13 +22,14 @@ obj-y			+= setup_$(BITS).o i8259_$(BITS).o setup.o
 obj-$(CONFIG_X86_32)    += sys_i386_32.o i386_ksyms_32.o
 obj-$(CONFIG_X86_64)    += sys_x86_64.o x8664_ksyms_64.o
 obj-$(CONFIG_X86_64)    += syscall_64.o vsyscall_64.o setup64.o
-obj-y                   += pci-dma_$(BITS).o  bootflag.o e820_$(BITS).o
-obj-y                   += quirks.o i8237.o topology.o kdebugfs.o
-obj-y                   += alternative.o i8253.o
-obj-$(CONFIG_X86_64)    += pci-nommu_64.o bugs_64.o
+obj-y                   += bootflag.o e820_$(BITS).o
+obj-y                   += pci-dma.o quirks.o i8237.o topology.o kdebugfs.o
+obj-y                   += alternative.o i8253.o pci-nommu.o
+obj-$(CONFIG_X86_64)    += bugs_64.o
 obj-y                   += tsc_$(BITS).o io_delay.o rtc.o
 
 obj-$(CONFIG_X86_TRAMPOLINE)    += trampoline.o
+obj-y                           += process.o
 obj-y                           += i387.o
 obj-y                           += ptrace.o
 obj-y                           += ds.o
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 8ca3557a6d59..c2502eb9aa83 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -1,6 +1,4 @@
 /*
- * arch/i386/kernel/acpi/cstate.c
- *
  * Copyright (C) 2005 Intel Corporation
  *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
  *      - Added _PDC for SMP C-states on Intel CPUs
@@ -93,7 +91,7 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
 
         /* Make sure we are running on right CPU */
         saved_mask = current->cpus_allowed;
-        retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        retval = set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (retval)
                 return -1;
 
@@ -130,7 +128,7 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
                  cx->address);
 
 out:
-        set_cpus_allowed(current, saved_mask);
+        set_cpus_allowed_ptr(current, &saved_mask);
         return retval;
 }
 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
diff --git a/arch/x86/kernel/acpi/processor.c b/arch/x86/kernel/acpi/processor.c
index 324eb0cab19c..de2d2e4ebad9 100644
--- a/arch/x86/kernel/acpi/processor.c
+++ b/arch/x86/kernel/acpi/processor.c
@@ -1,6 +1,4 @@
 /*
- * arch/i386/kernel/acpi/processor.c
- *
  * Copyright (C) 2005 Intel Corporation
  *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
  *      - Added _PDC for platforms with Intel CPUs
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d999d7833bc2..35b4f6a9c8ef 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -5,7 +5,6 @@
 #include <linux/module.h>
 #include <linux/percpu.h>
 #include <linux/bootmem.h>
-#include <asm/semaphore.h>
 #include <asm/processor.h>
 #include <asm/i387.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index a962dcb9c408..e2d870de837c 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -192,9 +192,9 @@ static void drv_read(struct drv_cmd *cmd)
         cpumask_t saved_mask = current->cpus_allowed;
         cmd->val = 0;
 
-        set_cpus_allowed(current, cmd->mask);
+        set_cpus_allowed_ptr(current, &cmd->mask);
         do_drv_read(cmd);
-        set_cpus_allowed(current, saved_mask);
+        set_cpus_allowed_ptr(current, &saved_mask);
 }
 
 static void drv_write(struct drv_cmd *cmd)
@@ -203,30 +203,30 @@ static void drv_write(struct drv_cmd *cmd)
         unsigned int i;
 
         for_each_cpu_mask(i, cmd->mask) {
-                set_cpus_allowed(current, cpumask_of_cpu(i));
+                set_cpus_allowed_ptr(current, &cpumask_of_cpu(i));
                 do_drv_write(cmd);
         }
 
-        set_cpus_allowed(current, saved_mask);
+        set_cpus_allowed_ptr(current, &saved_mask);
         return;
 }
 
-static u32 get_cur_val(cpumask_t mask)
+static u32 get_cur_val(const cpumask_t *mask)
 {
         struct acpi_processor_performance *perf;
         struct drv_cmd cmd;
 
-        if (unlikely(cpus_empty(mask)))
+        if (unlikely(cpus_empty(*mask)))
                 return 0;
 
-        switch (per_cpu(drv_data, first_cpu(mask))->cpu_feature) {
+        switch (per_cpu(drv_data, first_cpu(*mask))->cpu_feature) {
         case SYSTEM_INTEL_MSR_CAPABLE:
                 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
                 cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
                 break;
         case SYSTEM_IO_CAPABLE:
                 cmd.type = SYSTEM_IO_CAPABLE;
-                perf = per_cpu(drv_data, first_cpu(mask))->acpi_data;
+                perf = per_cpu(drv_data, first_cpu(*mask))->acpi_data;
                 cmd.addr.io.port = perf->control_register.address;
                 cmd.addr.io.bit_width = perf->control_register.bit_width;
                 break;
@@ -234,7 +234,7 @@ static u32 get_cur_val(cpumask_t mask)
                 return 0;
         }
 
-        cmd.mask = mask;
+        cmd.mask = *mask;
 
         drv_read(&cmd);
 
@@ -271,7 +271,7 @@ static unsigned int get_measured_perf(unsigned int cpu)
         unsigned int retval;
 
         saved_mask = current->cpus_allowed;
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (get_cpu() != cpu) {
                 /* We were not able to run on requested processor */
                 put_cpu();
@@ -329,7 +329,7 @@ static unsigned int get_measured_perf(unsigned int cpu)
         retval = per_cpu(drv_data, cpu)->max_freq * perf_percent / 100;
 
         put_cpu();
-        set_cpus_allowed(current, saved_mask);
+        set_cpus_allowed_ptr(current, &saved_mask);
 
         dprintk("cpu %d: performance percent %d\n", cpu, perf_percent);
         return retval;
@@ -347,13 +347,13 @@ static unsigned int get_cur_freq_on_cpu(unsigned int cpu)
                 return 0;
         }
 
-        freq = extract_freq(get_cur_val(cpumask_of_cpu(cpu)), data);
+        freq = extract_freq(get_cur_val(&cpumask_of_cpu(cpu)), data);
         dprintk("cur freq = %u\n", freq);
 
         return freq;
 }
 
-static unsigned int check_freqs(cpumask_t mask, unsigned int freq,
+static unsigned int check_freqs(const cpumask_t *mask, unsigned int freq,
                                 struct acpi_cpufreq_data *data)
 {
         unsigned int cur_freq;
@@ -449,7 +449,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
         drv_write(&cmd);
 
         if (acpi_pstate_strict) {
-                if (!check_freqs(cmd.mask, freqs.new, data)) {
+                if (!check_freqs(&cmd.mask, freqs.new, data)) {
                         dprintk("acpi_cpufreq_target failed (%d)\n",
                                 policy->cpu);
                         return -EAGAIN;
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index 14791ec55cfd..199e4e05e5dc 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -289,8 +289,8 @@ static int __init cpufreq_p4_init(void)
         if (c->x86_vendor != X86_VENDOR_INTEL)
                 return -ENODEV;
 
-        if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
-                !test_bit(X86_FEATURE_ACC, c->x86_capability))
+        if (!test_cpu_cap(c, X86_FEATURE_ACPI) ||
+                                !test_cpu_cap(c, X86_FEATURE_ACC))
                 return -ENODEV;
 
         ret = cpufreq_register_driver(&p4clockmod_driver);
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index c99d59d8ef2e..46d4034d9f37 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -478,12 +478,12 @@ static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvi
 
 static int check_supported_cpu(unsigned int cpu)
 {
-        cpumask_t oldmask = CPU_MASK_ALL;
+        cpumask_t oldmask;
         u32 eax, ebx, ecx, edx;
         unsigned int rc = 0;
 
         oldmask = current->cpus_allowed;
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
 
         if (smp_processor_id() != cpu) {
                 printk(KERN_ERR PFX "limiting to cpu %u failed\n", cpu);
@@ -528,7 +528,7 @@ static int check_supported_cpu(unsigned int cpu)
         rc = 1;
 
 out:
-        set_cpus_allowed(current, oldmask);
+        set_cpus_allowed_ptr(current, &oldmask);
         return rc;
 }
 
@@ -1015,7 +1015,7 @@ static int transition_frequency_pstate(struct powernow_k8_data *data, unsigned i
 /* Driver entry point to switch to the target frequency */
 static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsigned relation)
 {
-        cpumask_t oldmask = CPU_MASK_ALL;
+        cpumask_t oldmask;
         struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu);
         u32 checkfid;
         u32 checkvid;
@@ -1030,7 +1030,7 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
 
         /* only run on specific CPU from here on */
         oldmask = current->cpus_allowed;
-        set_cpus_allowed(current, cpumask_of_cpu(pol->cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu));
 
         if (smp_processor_id() != pol->cpu) {
                 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
@@ -1085,7 +1085,7 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
         ret = 0;
 
 err_out:
-        set_cpus_allowed(current, oldmask);
+        set_cpus_allowed_ptr(current, &oldmask);
         return ret;
 }
 
@@ -1104,7 +1104,7 @@ static int powernowk8_verify(struct cpufreq_policy *pol)
 static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
 {
         struct powernow_k8_data *data;
-        cpumask_t oldmask = CPU_MASK_ALL;
+        cpumask_t oldmask;
         int rc;
 
         if (!cpu_online(pol->cpu))
@@ -1145,7 +1145,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
 
         /* only run on specific CPU from here on */
         oldmask = current->cpus_allowed;
-        set_cpus_allowed(current, cpumask_of_cpu(pol->cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu));
 
         if (smp_processor_id() != pol->cpu) {
                 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
@@ -1164,7 +1164,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
                 fidvid_msr_init();
 
         /* run on any CPU again */
-        set_cpus_allowed(current, oldmask);
+        set_cpus_allowed_ptr(current, &oldmask);
 
         if (cpu_family == CPU_HW_PSTATE)
                 pol->cpus = cpumask_of_cpu(pol->cpu);
@@ -1205,7 +1205,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
         return 0;
 
 err_out:
-        set_cpus_allowed(current, oldmask);
+        set_cpus_allowed_ptr(current, &oldmask);
         powernow_k8_cpu_exit_acpi(data);
 
         kfree(data);
@@ -1242,10 +1242,11 @@ static unsigned int powernowk8_get (unsigned int cpu)
         if (!data)
                 return -EINVAL;
 
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (smp_processor_id() != cpu) {
-                printk(KERN_ERR PFX "limiting to CPU %d failed in powernowk8_get\n", cpu);
-                set_cpus_allowed(current, oldmask);
+                printk(KERN_ERR PFX
+                        "limiting to CPU %d failed in powernowk8_get\n", cpu);
+                set_cpus_allowed_ptr(current, &oldmask);
                 return 0;
         }
 
@@ -1253,13 +1254,14 @@ static unsigned int powernowk8_get (unsigned int cpu)
                 goto out;
 
         if (cpu_family == CPU_HW_PSTATE)
-                khz = find_khz_freq_from_pstate(data->powernow_table, data->currpstate);
+                khz = find_khz_freq_from_pstate(data->powernow_table,
+                                                data->currpstate);
         else
                 khz = find_khz_freq_from_fid(data->currfid);
 
 
 out:
-        set_cpus_allowed(current, oldmask);
+        set_cpus_allowed_ptr(current, &oldmask);
         return khz;
 }
 
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
index 3031f1196192..908dd347c67e 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -315,7 +315,7 @@ static unsigned int get_cur_freq(unsigned int cpu)
         cpumask_t saved_mask;
 
         saved_mask = current->cpus_allowed;
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (smp_processor_id() != cpu)
                 return 0;
 
@@ -333,7 +333,7 @@ static unsigned int get_cur_freq(unsigned int cpu)
                 clock_freq = extract_clock(l, cpu, 1);
         }
 
-        set_cpus_allowed(current, saved_mask);
+        set_cpus_allowed_ptr(current, &saved_mask);
         return clock_freq;
 }
 
@@ -487,7 +487,7 @@ static int centrino_target (struct cpufreq_policy *policy,
                 else
                         cpu_set(j, set_mask);
 
-                set_cpus_allowed(current, set_mask);
+                set_cpus_allowed_ptr(current, &set_mask);
                 preempt_disable();
                 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
                         dprintk("couldn't limit to CPUs in this domain\n");
@@ -555,7 +555,8 @@ static int centrino_target (struct cpufreq_policy *policy,
 
                 if (!cpus_empty(covered_cpus)) {
                         for_each_cpu_mask(j, covered_cpus) {
-                                set_cpus_allowed(current, cpumask_of_cpu(j));
+                                set_cpus_allowed_ptr(current,
+                                                     &cpumask_of_cpu(j));
                                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
                         }
                 }
@@ -569,12 +570,12 @@ static int centrino_target (struct cpufreq_policy *policy,
                         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
                 }
         }
-        set_cpus_allowed(current, saved_mask);
+        set_cpus_allowed_ptr(current, &saved_mask);
         return 0;
 
 migrate_end:
         preempt_enable();
-        set_cpus_allowed(current, saved_mask);
+        set_cpus_allowed_ptr(current, &saved_mask);
         return 0;
 }
 
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
index 14d68aa301ee..1b50244b1fdf 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
@@ -229,22 +229,22 @@ static unsigned int speedstep_detect_chipset (void)
         return 0;
 }
 
-static unsigned int _speedstep_get(cpumask_t cpus)
+static unsigned int _speedstep_get(const cpumask_t *cpus)
 {
         unsigned int speed;
         cpumask_t cpus_allowed;
 
         cpus_allowed = current->cpus_allowed;
-        set_cpus_allowed(current, cpus);
+        set_cpus_allowed_ptr(current, cpus);
         speed = speedstep_get_processor_frequency(speedstep_processor);
-        set_cpus_allowed(current, cpus_allowed);
+        set_cpus_allowed_ptr(current, &cpus_allowed);
         dprintk("detected %u kHz as current frequency\n", speed);
         return speed;
 }
 
 static unsigned int speedstep_get(unsigned int cpu)
 {
-        return _speedstep_get(cpumask_of_cpu(cpu));
+        return _speedstep_get(&cpumask_of_cpu(cpu));
 }
 
 /**
@@ -267,7 +267,7 @@ static int speedstep_target (struct cpufreq_policy *policy,
         if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], target_freq, relation, &newstate))
                 return -EINVAL;
 
-        freqs.old = _speedstep_get(policy->cpus);
+        freqs.old = _speedstep_get(&policy->cpus);
         freqs.new = speedstep_freqs[newstate].frequency;
         freqs.cpu = policy->cpu;
 
@@ -285,12 +285,12 @@ static int speedstep_target (struct cpufreq_policy *policy,
         }
 
         /* switch to physical CPU where state is to be changed */
-        set_cpus_allowed(current, policy->cpus);
+        set_cpus_allowed_ptr(current, &policy->cpus);
 
         speedstep_set_state(newstate);
 
         /* allow to be run on all CPUs */
-        set_cpus_allowed(current, cpus_allowed);
+        set_cpus_allowed_ptr(current, &cpus_allowed);
 
         for_each_cpu_mask(i, policy->cpus) {
                 freqs.cpu = i;
@@ -326,7 +326,7 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
 #endif
 
         cpus_allowed = current->cpus_allowed;
-        set_cpus_allowed(current, policy->cpus);
+        set_cpus_allowed_ptr(current, &policy->cpus);
 
         /* detect low and high frequency and transition latency */
         result = speedstep_get_freqs(speedstep_processor,
@@ -334,12 +334,12 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
                                      &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
                                      &policy->cpuinfo.transition_latency,
                                      &speedstep_set_state);
-        set_cpus_allowed(current, cpus_allowed);
+        set_cpus_allowed_ptr(current, &cpus_allowed);
         if (result)
                 return result;
 
         /* get current speed setting */
-        speed = _speedstep_get(policy->cpus);
+        speed = _speedstep_get(&policy->cpus);
         if (!speed)
                 return -EIO;
 
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 1b889860eb73..26d615dcb149 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -129,7 +129,7 @@ struct _cpuid4_info {
         union _cpuid4_leaf_ebx ebx;
         union _cpuid4_leaf_ecx ecx;
         unsigned long size;
-        cpumask_t shared_cpu_map;
+        cpumask_t shared_cpu_map;       /* future?: only cpus/node is needed */
 };
 
 unsigned short                  num_cache_leaves;
@@ -451,8 +451,8 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 }
 
 /* pointer to _cpuid4_info array (for each cache leaf) */
-static struct _cpuid4_info *cpuid4_info[NR_CPUS];
-#define CPUID4_INFO_IDX(x,y)    (&((cpuid4_info[x])[y]))
+static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
+#define CPUID4_INFO_IDX(x, y)    (&((per_cpu(cpuid4_info, x))[y]))
 
 #ifdef CONFIG_SMP
 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
@@ -474,7 +474,7 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
                         if (cpu_data(i).apicid >> index_msb ==
                             c->apicid >> index_msb) {
                                 cpu_set(i, this_leaf->shared_cpu_map);
-                                if (i != cpu && cpuid4_info[i])  {
+                                if (i != cpu && per_cpu(cpuid4_info, i))  {
                                         sibling_leaf = CPUID4_INFO_IDX(i, index);
                                         cpu_set(cpu, sibling_leaf->shared_cpu_map);
                                 }
@@ -505,8 +505,8 @@ static void __cpuinit free_cache_attributes(unsigned int cpu)
         for (i = 0; i < num_cache_leaves; i++)
                 cache_remove_shared_cpu_map(cpu, i);
 
-        kfree(cpuid4_info[cpu]);
-        cpuid4_info[cpu] = NULL;
+        kfree(per_cpu(cpuid4_info, cpu));
+        per_cpu(cpuid4_info, cpu) = NULL;
 }
 
 static int __cpuinit detect_cache_attributes(unsigned int cpu)
@@ -519,13 +519,13 @@ static int __cpuinit detect_cache_attributes(unsigned int cpu)
         if (num_cache_leaves == 0)
                 return -ENOENT;
 
-        cpuid4_info[cpu] = kzalloc(
+        per_cpu(cpuid4_info, cpu) = kzalloc(
             sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
-        if (cpuid4_info[cpu] == NULL)
+        if (per_cpu(cpuid4_info, cpu) == NULL)
                 return -ENOMEM;
 
         oldmask = current->cpus_allowed;
-        retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        retval = set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (retval)
                 goto out;
 
@@ -542,12 +542,12 @@ static int __cpuinit detect_cache_attributes(unsigned int cpu)
                 }
                 cache_shared_cpu_map_setup(cpu, j);
         }
-        set_cpus_allowed(current, oldmask);
+        set_cpus_allowed_ptr(current, &oldmask);
 
 out:
         if (retval) {
-                kfree(cpuid4_info[cpu]);
-                cpuid4_info[cpu] = NULL;
+                kfree(per_cpu(cpuid4_info, cpu));
+                per_cpu(cpuid4_info, cpu) = NULL;
         }
 
         return retval;
@@ -561,7 +561,7 @@ out:
 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
 
 /* pointer to kobject for cpuX/cache */
-static struct kobject * cache_kobject[NR_CPUS];
+static DEFINE_PER_CPU(struct kobject *, cache_kobject);
 
 struct _index_kobject {
         struct kobject kobj;
@@ -570,8 +570,8 @@ struct _index_kobject {
 };
 
 /* pointer to array of kobjects for cpuX/cache/indexY */
-static struct _index_kobject *index_kobject[NR_CPUS];
-#define INDEX_KOBJECT_PTR(x,y)    (&((index_kobject[x])[y]))
+static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
+#define INDEX_KOBJECT_PTR(x, y)    (&((per_cpu(index_kobject, x))[y]))
 
 #define show_one_plus(file_name, object, val)                           \
 static ssize_t show_##file_name                                         \
@@ -591,11 +591,32 @@ static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
         return sprintf (buf, "%luK\n", this_leaf->size / 1024);
 }
 
-static ssize_t show_shared_cpu_map(struct _cpuid4_info *this_leaf, char *buf)
+static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
+                                        int type, char *buf)
 {
-        char mask_str[NR_CPUS];
-        cpumask_scnprintf(mask_str, NR_CPUS, this_leaf->shared_cpu_map);
-        return sprintf(buf, "%s\n", mask_str);
+        ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
+        int n = 0;
+
+        if (len > 1) {
+                cpumask_t *mask = &this_leaf->shared_cpu_map;
+
+                n = type?
+                        cpulist_scnprintf(buf, len-2, *mask):
+                        cpumask_scnprintf(buf, len-2, *mask);
+                buf[n++] = '\n';
+                buf[n] = '\0';
+        }
+        return n;
+}
+
+static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
+{
+        return show_shared_cpu_map_func(leaf, 0, buf);
+}
+
+static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
+{
+        return show_shared_cpu_map_func(leaf, 1, buf);
 }
 
 static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
@@ -633,6 +654,7 @@ define_one_ro(ways_of_associativity);
 define_one_ro(number_of_sets);
 define_one_ro(size);
 define_one_ro(shared_cpu_map);
+define_one_ro(shared_cpu_list);
 
 static struct attribute * default_attrs[] = {
         &type.attr,
@@ -643,6 +665,7 @@ static struct attribute * default_attrs[] = {
         &number_of_sets.attr,
         &size.attr,
         &shared_cpu_map.attr,
+        &shared_cpu_list.attr,
         NULL
 };
 
@@ -684,10 +707,10 @@ static struct kobj_type ktype_percpu_entry = {
 
 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
 {
-        kfree(cache_kobject[cpu]);
-        kfree(index_kobject[cpu]);
-        cache_kobject[cpu] = NULL;
-        index_kobject[cpu] = NULL;
+        kfree(per_cpu(cache_kobject, cpu));
+        kfree(per_cpu(index_kobject, cpu));
+        per_cpu(cache_kobject, cpu) = NULL;
+        per_cpu(index_kobject, cpu) = NULL;
         free_cache_attributes(cpu);
 }
 
@@ -703,13 +726,14 @@ static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
                 return err;
 
         /* Allocate all required memory */
-        cache_kobject[cpu] = kzalloc(sizeof(struct kobject), GFP_KERNEL);
-        if (unlikely(cache_kobject[cpu] == NULL))
+        per_cpu(cache_kobject, cpu) =
+                kzalloc(sizeof(struct kobject), GFP_KERNEL);
+        if (unlikely(per_cpu(cache_kobject, cpu) == NULL))
                 goto err_out;
 
-        index_kobject[cpu] = kzalloc(
+        per_cpu(index_kobject, cpu) = kzalloc(
             sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL);
-        if (unlikely(index_kobject[cpu] == NULL))
+        if (unlikely(per_cpu(index_kobject, cpu) == NULL))
                 goto err_out;
 
         return 0;
@@ -733,7 +757,8 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
         if (unlikely(retval < 0))
                 return retval;
 
-        retval = kobject_init_and_add(cache_kobject[cpu], &ktype_percpu_entry,
+        retval = kobject_init_and_add(per_cpu(cache_kobject, cpu),
+                                      &ktype_percpu_entry,
                                       &sys_dev->kobj, "%s", "cache");
         if (retval < 0) {
                 cpuid4_cache_sysfs_exit(cpu);
@@ -745,13 +770,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
                 this_object->cpu = cpu;
                 this_object->index = i;
                 retval = kobject_init_and_add(&(this_object->kobj),
-                                              &ktype_cache, cache_kobject[cpu],
+                                              &ktype_cache,
+                                              per_cpu(cache_kobject, cpu),
                                               "index%1lu", i);
                 if (unlikely(retval)) {
                         for (j = 0; j < i; j++) {
                                 kobject_put(&(INDEX_KOBJECT_PTR(cpu,j)->kobj));
                         }
-                        kobject_put(cache_kobject[cpu]);
+                        kobject_put(per_cpu(cache_kobject, cpu));
                         cpuid4_cache_sysfs_exit(cpu);
                         break;
                 }
@@ -760,7 +786,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
         if (!retval)
                 cpu_set(cpu, cache_dev_map);
 
-        kobject_uevent(cache_kobject[cpu], KOBJ_ADD);
+        kobject_uevent(per_cpu(cache_kobject, cpu), KOBJ_ADD);
         return retval;
 }
 
@@ -769,7 +795,7 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
         unsigned int cpu = sys_dev->id;
         unsigned long i;
 
-        if (cpuid4_info[cpu] == NULL)
+        if (per_cpu(cpuid4_info, cpu) == NULL)
                 return;
         if (!cpu_isset(cpu, cache_dev_map))
                 return;
@@ -777,7 +803,7 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
 
         for (i = 0; i < num_cache_leaves; i++)
                 kobject_put(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
-        kobject_put(cache_kobject[cpu]);
+        kobject_put(per_cpu(cache_kobject, cpu));
         cpuid4_cache_sysfs_exit(cpu);
 }
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index 32671da8184e..7c9a813e1193 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -251,18 +251,18 @@ struct threshold_attr {
         ssize_t(*store) (struct threshold_block *, const char *, size_t count);
 };
 
-static cpumask_t affinity_set(unsigned int cpu)
+static void affinity_set(unsigned int cpu, cpumask_t *oldmask,
+                                           cpumask_t *newmask)
 {
-        cpumask_t oldmask = current->cpus_allowed;
-        cpumask_t newmask = CPU_MASK_NONE;
-        cpu_set(cpu, newmask);
-        set_cpus_allowed(current, newmask);
-        return oldmask;
+        *oldmask = current->cpus_allowed;
+        cpus_clear(*newmask);
+        cpu_set(cpu, *newmask);
+        set_cpus_allowed_ptr(current, newmask);
 }
 
-static void affinity_restore(cpumask_t oldmask)
+static void affinity_restore(const cpumask_t *oldmask)
 {
-        set_cpus_allowed(current, oldmask);
+        set_cpus_allowed_ptr(current, oldmask);
 }
 
 #define SHOW_FIELDS(name)                                           \
@@ -277,15 +277,15 @@ static ssize_t store_interrupt_enable(struct threshold_block *b,
                                       const char *buf, size_t count)
 {
         char *end;
-        cpumask_t oldmask;
+        cpumask_t oldmask, newmask;
         unsigned long new = simple_strtoul(buf, &end, 0);
         if (end == buf)
                 return -EINVAL;
         b->interrupt_enable = !!new;
 
-        oldmask = affinity_set(b->cpu);
+        affinity_set(b->cpu, &oldmask, &newmask);
         threshold_restart_bank(b, 0, 0);
-        affinity_restore(oldmask);
+        affinity_restore(&oldmask);
 
         return end - buf;
 }
@@ -294,7 +294,7 @@ static ssize_t store_threshold_limit(struct threshold_block *b,
                                      const char *buf, size_t count)
 {
         char *end;
-        cpumask_t oldmask;
+        cpumask_t oldmask, newmask;
         u16 old;
         unsigned long new = simple_strtoul(buf, &end, 0);
         if (end == buf)
@@ -306,9 +306,9 @@ static ssize_t store_threshold_limit(struct threshold_block *b,
         old = b->threshold_limit;
         b->threshold_limit = new;
 
-        oldmask = affinity_set(b->cpu);
+        affinity_set(b->cpu, &oldmask, &newmask);
         threshold_restart_bank(b, 0, old);
-        affinity_restore(oldmask);
+        affinity_restore(&oldmask);
 
         return end - buf;
 }
@@ -316,10 +316,10 @@ static ssize_t store_threshold_limit(struct threshold_block *b,
 static ssize_t show_error_count(struct threshold_block *b, char *buf)
 {
         u32 high, low;
-        cpumask_t oldmask;
-        oldmask = affinity_set(b->cpu);
+        cpumask_t oldmask, newmask;
+        affinity_set(b->cpu, &oldmask, &newmask);
         rdmsr(b->address, low, high);
-        affinity_restore(oldmask);
+        affinity_restore(&oldmask);
         return sprintf(buf, "%x\n",
                        (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
 }
@@ -327,10 +327,10 @@ static ssize_t show_error_count(struct threshold_block *b, char *buf)
 static ssize_t store_error_count(struct threshold_block *b,
                                  const char *buf, size_t count)
 {
-        cpumask_t oldmask;
-        oldmask = affinity_set(b->cpu);
+        cpumask_t oldmask, newmask;
+        affinity_set(b->cpu, &oldmask, &newmask);
         threshold_restart_bank(b, 1, 0);
-        affinity_restore(oldmask);
+        affinity_restore(&oldmask);
         return 1;
 }
 
@@ -468,7 +468,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 {
         int i, err = 0;
         struct threshold_bank *b = NULL;
-        cpumask_t oldmask = CPU_MASK_NONE;
+        cpumask_t oldmask, newmask;
         char name[32];
 
         sprintf(name, "threshold_bank%i", bank);
@@ -519,10 +519,10 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 
         per_cpu(threshold_banks, cpu)[bank] = b;
 
-        oldmask = affinity_set(cpu);
+        affinity_set(cpu, &oldmask, &newmask);
         err = allocate_threshold_blocks(cpu, bank, 0,
                                         MSR_IA32_MC0_MISC + bank * 4);
-        affinity_restore(oldmask);
+        affinity_restore(&oldmask);
 
         if (err)
                 goto out_free;
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 9b7e01daa1ca..1f4cc48c14c6 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -1,5 +1,4 @@
 /*
- * linux/arch/i386/kernel/cpu/mcheck/therm_throt.c
  *
  * Thermal throttle event support code (such as syslog messaging and rate
  * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 0978a4a39418..0d0d9057e7c0 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -1,7 +1,6 @@
 #include <linux/smp.h>
 #include <linux/timex.h>
 #include <linux/string.h>
-#include <asm/semaphore.h>
 #include <linux/seq_file.h>
 #include <linux/cpufreq.h>
 
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 288e7a6598ac..daff52a62248 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -154,12 +154,10 @@ static int __cpuinit cpuid_class_cpu_callback(struct notifier_block *nfb,
                 err = cpuid_device_create(cpu);
                 break;
         case CPU_UP_CANCELED:
+        case CPU_UP_CANCELED_FROZEN:
         case CPU_DEAD:
                 cpuid_device_destroy(cpu);
                 break;
-        case CPU_UP_CANCELED_FROZEN:
-                destroy_suspended_device(cpuid_class, MKDEV(CPUID_MAJOR, cpu));
-                break;
         }
         return err ? NOTIFY_BAD : NOTIFY_OK;
 }
diff --git a/arch/x86/kernel/e820_32.c b/arch/x86/kernel/e820_32.c
index 0240cd778365..ed733e7cf4e6 100644
--- a/arch/x86/kernel/e820_32.c
+++ b/arch/x86/kernel/e820_32.c
@@ -475,7 +475,7 @@ int __init copy_e820_map(struct e820entry *biosmap, int nr_map)
 /*
  * Find the highest page frame number we have available
  */
-void __init find_max_pfn(void)
+void __init propagate_e820_map(void)
 {
         int i;
 
@@ -704,7 +704,7 @@ static int __init parse_memmap(char *arg)
                  * size before original memory map is
                  * reset.
                  */
-                find_max_pfn();
+                propagate_e820_map();
                 saved_max_pfn = max_pfn;
 #endif
                 e820.nr_map = 0;
diff --git a/arch/x86/kernel/e820_64.c b/arch/x86/kernel/e820_64.c
index 7f6c0c85c8f6..cbd42e51cb08 100644
--- a/arch/x86/kernel/e820_64.c
+++ b/arch/x86/kernel/e820_64.c
@@ -96,7 +96,7 @@ void __init early_res_to_bootmem(void)
 }
 
 /* Check for already reserved areas */
-static inline int
+static inline int __init
 bad_addr(unsigned long *addrp, unsigned long size, unsigned long align)
 {
         int i;
@@ -116,7 +116,7 @@ again:
 }
 
 /* Check for already reserved areas */
-static inline int
+static inline int __init
 bad_addr_size(unsigned long *addrp, unsigned long *sizep, unsigned long align)
 {
         int i;
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c
index 759e02bec070..77d424cf68b3 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/kernel/efi.c
@@ -383,6 +383,7 @@ static void __init runtime_code_page_mkexec(void)
 {
         efi_memory_desc_t *md;
         void *p;
+        u64 addr, npages;
 
         /* Make EFI runtime service code area executable */
         for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
@@ -391,7 +392,10 @@ static void __init runtime_code_page_mkexec(void)
                 if (md->type != EFI_RUNTIME_SERVICES_CODE)
                         continue;
 
-                set_memory_x(md->virt_addr, md->num_pages);
+                addr = md->virt_addr;
+                npages = md->num_pages;
+                memrange_efi_to_native(&addr, &npages);
+                set_memory_x(addr, npages);
         }
 }
 
@@ -408,7 +412,7 @@ void __init efi_enter_virtual_mode(void)
         efi_memory_desc_t *md;
         efi_status_t status;
         unsigned long size;
-        u64 end, systab;
+        u64 end, systab, addr, npages;
         void *p, *va;
 
         efi.systab = NULL;
@@ -420,7 +424,7 @@ void __init efi_enter_virtual_mode(void)
                 size = md->num_pages << EFI_PAGE_SHIFT;
                 end = md->phys_addr + size;
 
-                if ((end >> PAGE_SHIFT) <= max_pfn_mapped)
+                if (PFN_UP(end) <= max_pfn_mapped)
                         va = __va(md->phys_addr);
                 else
                         va = efi_ioremap(md->phys_addr, size);
@@ -433,8 +437,12 @@ void __init efi_enter_virtual_mode(void)
                         continue;
                 }
 
-                if (!(md->attribute & EFI_MEMORY_WB))
-                        set_memory_uc(md->virt_addr, md->num_pages);
+                if (!(md->attribute & EFI_MEMORY_WB)) {
+                        addr = md->virt_addr;
+                        npages = md->num_pages;
+                        memrange_efi_to_native(&addr, &npages);
+                        set_memory_uc(addr, npages);
+                }
 
                 systab = (u64) (unsigned long) efi_phys.systab;
                 if (md->phys_addr <= systab && systab < end) {
diff --git a/arch/x86/kernel/efi_64.c b/arch/x86/kernel/efi_64.c
index d143a1e76b30..d0060fdcccac 100644
--- a/arch/x86/kernel/efi_64.c
+++ b/arch/x86/kernel/efi_64.c
@@ -105,14 +105,14 @@ void __init efi_reserve_bootmem(void)
 
 void __iomem * __init efi_ioremap(unsigned long phys_addr, unsigned long size)
 {
-        static unsigned pages_mapped;
+        static unsigned pages_mapped __initdata;
         unsigned i, pages;
+        unsigned long offset;
 
-        /* phys_addr and size must be page aligned */
-        if ((phys_addr & ~PAGE_MASK) || (size & ~PAGE_MASK))
-                return NULL;
+        pages = PFN_UP(phys_addr + size) - PFN_DOWN(phys_addr);
+        offset = phys_addr & ~PAGE_MASK;
+        phys_addr &= PAGE_MASK;
 
-        pages = size >> PAGE_SHIFT;
         if (pages_mapped + pages > MAX_EFI_IO_PAGES)
                 return NULL;
 
@@ -124,5 +124,5 @@ void __iomem * __init efi_ioremap(unsigned long phys_addr, unsigned long size)
         }
 
         return (void __iomem *)__fix_to_virt(FIX_EFI_IO_MAP_FIRST_PAGE - \
-                                             (pages_mapped - pages));
+                                             (pages_mapped - pages)) + offset;
 }
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index 9ba49a26dff8..f0f8934fc303 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -1,5 +1,4 @@
 /*
- *  linux/arch/i386/entry.S
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
  */
diff --git a/arch/x86/kernel/genx2apic_uv_x.c b/arch/x86/kernel/genx2apic_uv_x.c
index 5d77c9cd8e15..ebf13908a743 100644
--- a/arch/x86/kernel/genx2apic_uv_x.c
+++ b/arch/x86/kernel/genx2apic_uv_x.c
@@ -61,26 +61,31 @@ int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
-            (6 << UVH_IPI_INT_DELIVERY_MODE_SHFT);
+            APIC_DM_INIT;
+        uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+        mdelay(10);
+
+        val = (1UL << UVH_IPI_INT_SEND_SHFT) |
+            (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
+            (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
+            APIC_DM_STARTUP;
         uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
         return 0;
 }
 
 static void uv_send_IPI_one(int cpu, int vector)
 {
-        unsigned long val, apicid;
+        unsigned long val, apicid, lapicid;
         int nasid;
 
         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
+        lapicid = apicid & 0x3f;                /* ZZZ macro needed */
         nasid = uv_apicid_to_nasid(apicid);
         val =
-            (1UL << UVH_IPI_INT_SEND_SHFT) | (apicid <<
+            (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
                                               UVH_IPI_INT_APIC_ID_SHFT) |
             (vector << UVH_IPI_INT_VECTOR_SHFT);
         uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
-        printk(KERN_DEBUG
-             "UV: IPI to cpu %d, apicid 0x%lx, vec %d, nasid%d, val 0x%lx\n",
-             cpu, apicid, vector, nasid, val);
 }
 
 static void uv_send_IPI_mask(cpumask_t mask, int vector)
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index d6d54faa84df..993c76773256 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -146,6 +146,7 @@ void __init x86_64_start_kernel(char * real_mode_data)
 
         reserve_early(__pa_symbol(&_text), __pa_symbol(&_end), "TEXT DATA BSS");
 
+#ifdef CONFIG_BLK_DEV_INITRD
         /* Reserve INITRD */
         if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
                 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
@@ -153,6 +154,7 @@ void __init x86_64_start_kernel(char * real_mode_data)
                 unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
                 reserve_early(ramdisk_image, ramdisk_end, "RAMDISK");
         }
+#endif
 
         reserve_ebda_region();
 
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index 826988a6e964..90f038af3adc 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -1,5 +1,4 @@
 /*
- *  linux/arch/i386/kernel/head.S -- the 32-bit startup code.
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
  *
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 8f8102d967b3..db6839b53195 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -35,17 +35,18 @@
 #endif
 
 static unsigned int             mxcsr_feature_mask __read_mostly = 0xffffffffu;
+unsigned int xstate_size;
+static struct i387_fxsave_struct fx_scratch __cpuinitdata;
 
-void mxcsr_feature_mask_init(void)
+void __cpuinit mxcsr_feature_mask_init(void)
 {
         unsigned long mask = 0;
 
         clts();
         if (cpu_has_fxsr) {
-                memset(&current->thread.i387.fxsave, 0,
-                       sizeof(struct i387_fxsave_struct));
-                asm volatile("fxsave %0" : : "m" (current->thread.i387.fxsave));
-                mask = current->thread.i387.fxsave.mxcsr_mask;
+                memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct));
+                asm volatile("fxsave %0" : : "m" (fx_scratch));
+                mask = fx_scratch.mxcsr_mask;
                 if (mask == 0)
                         mask = 0x0000ffbf;
         }
@@ -53,6 +54,16 @@ void mxcsr_feature_mask_init(void)
         stts();
 }
 
+void __init init_thread_xstate(void)
+{
+        if (cpu_has_fxsr)
+                xstate_size = sizeof(struct i387_fxsave_struct);
+#ifdef CONFIG_X86_32
+        else
+                xstate_size = sizeof(struct i387_fsave_struct);
+#endif
+}
+
 #ifdef CONFIG_X86_64
 /*
  * Called at bootup to set up the initial FPU state that is later cloned
@@ -61,10 +72,6 @@ void mxcsr_feature_mask_init(void)
 void __cpuinit fpu_init(void)
 {
         unsigned long oldcr0 = read_cr0();
-        extern void __bad_fxsave_alignment(void);
-
-        if (offsetof(struct task_struct, thread.i387.fxsave) & 15)
-                __bad_fxsave_alignment();
 
         set_in_cr4(X86_CR4_OSFXSR);
         set_in_cr4(X86_CR4_OSXMMEXCPT);
@@ -84,32 +91,44 @@ void __cpuinit fpu_init(void)
  * value at reset if we support XMM instructions and then
  * remeber the current task has used the FPU.
  */
-void init_fpu(struct task_struct *tsk)
+int init_fpu(struct task_struct *tsk)
 {
         if (tsk_used_math(tsk)) {
                 if (tsk == current)
                         unlazy_fpu(tsk);
-                return;
+                return 0;
+        }
+
+        /*
+         * Memory allocation at the first usage of the FPU and other state.
+         */
+        if (!tsk->thread.xstate) {
+                tsk->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
+                                                      GFP_KERNEL);
+                if (!tsk->thread.xstate)
+                        return -ENOMEM;
         }
 
         if (cpu_has_fxsr) {
-                memset(&tsk->thread.i387.fxsave, 0,
-                       sizeof(struct i387_fxsave_struct));
-                tsk->thread.i387.fxsave.cwd = 0x37f;
+                struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
+
+                memset(fx, 0, xstate_size);
+                fx->cwd = 0x37f;
                 if (cpu_has_xmm)
-                        tsk->thread.i387.fxsave.mxcsr = MXCSR_DEFAULT;
+                        fx->mxcsr = MXCSR_DEFAULT;
         } else {
-                memset(&tsk->thread.i387.fsave, 0,
-                       sizeof(struct i387_fsave_struct));
-                tsk->thread.i387.fsave.cwd = 0xffff037fu;
-                tsk->thread.i387.fsave.swd = 0xffff0000u;
-                tsk->thread.i387.fsave.twd = 0xffffffffu;
-                tsk->thread.i387.fsave.fos = 0xffff0000u;
+                struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave;
+                memset(fp, 0, xstate_size);
+                fp->cwd = 0xffff037fu;
+                fp->swd = 0xffff0000u;
+                fp->twd = 0xffffffffu;
+                fp->fos = 0xffff0000u;
         }
         /*
          * Only the device not available exception or ptrace can call init_fpu.
          */
         set_stopped_child_used_math(tsk);
+        return 0;
 }
 
 int fpregs_active(struct task_struct *target, const struct user_regset *regset)
@@ -126,13 +145,17 @@ int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
                 unsigned int pos, unsigned int count,
                 void *kbuf, void __user *ubuf)
 {
+        int ret;
+
         if (!cpu_has_fxsr)
                 return -ENODEV;
 
-        init_fpu(target);
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
 
         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
-                                   &target->thread.i387.fxsave, 0, -1);
+                                   &target->thread.xstate->fxsave, 0, -1);
 }
 
 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
@@ -144,16 +167,19 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
         if (!cpu_has_fxsr)
                 return -ENODEV;
 
-        init_fpu(target);
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
+
         set_stopped_child_used_math(target);
 
         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-                                 &target->thread.i387.fxsave, 0, -1);
+                                 &target->thread.xstate->fxsave, 0, -1);
 
         /*
          * mxcsr reserved bits must be masked to zero for security reasons.
          */
-        target->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;
+        target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask;
 
         return ret;
 }
@@ -233,7 +259,7 @@ static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
 static void
 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
 {
-        struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
+        struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave;
         struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
         struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
         int i;
@@ -273,7 +299,7 @@ static void convert_to_fxsr(struct task_struct *tsk,
                             const struct user_i387_ia32_struct *env)
 
 {
-        struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
+        struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave;
         struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
         struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
         int i;
@@ -302,15 +328,19 @@ int fpregs_get(struct task_struct *target, const struct user_regset *regset,
                void *kbuf, void __user *ubuf)
 {
         struct user_i387_ia32_struct env;
+        int ret;
 
         if (!HAVE_HWFP)
                 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
 
-        init_fpu(target);
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
 
         if (!cpu_has_fxsr) {
                 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
-                                           &target->thread.i387.fsave, 0, -1);
+                                           &target->thread.xstate->fsave, 0,
+                                           -1);
         }
 
         if (kbuf && pos == 0 && count == sizeof(env)) {
@@ -333,12 +363,15 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
         if (!HAVE_HWFP)
                 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
 
-        init_fpu(target);
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
+
         set_stopped_child_used_math(target);
 
         if (!cpu_has_fxsr) {
                 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-                                          &target->thread.i387.fsave, 0, -1);
+                                          &target->thread.xstate->fsave, 0, -1);
         }
 
         if (pos > 0 || count < sizeof(env))
@@ -358,11 +391,11 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
 static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf)
 {
         struct task_struct *tsk = current;
+        struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave;
 
         unlazy_fpu(tsk);
-        tsk->thread.i387.fsave.status = tsk->thread.i387.fsave.swd;
-        if (__copy_to_user(buf, &tsk->thread.i387.fsave,
-                           sizeof(struct i387_fsave_struct)))
+        fp->status = fp->swd;
+        if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct)))
                 return -1;
         return 1;
 }
@@ -370,6 +403,7 @@ static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf)
 static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
 {
         struct task_struct *tsk = current;
+        struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
         struct user_i387_ia32_struct env;
         int err = 0;
 
@@ -379,12 +413,12 @@ static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
         if (__copy_to_user(buf, &env, sizeof(env)))
                 return -1;
 
-        err |= __put_user(tsk->thread.i387.fxsave.swd, &buf->status);
+        err |= __put_user(fx->swd, &buf->status);
         err |= __put_user(X86_FXSR_MAGIC, &buf->magic);
         if (err)
                 return -1;
 
-        if (__copy_to_user(&buf->_fxsr_env[0], &tsk->thread.i387.fxsave,
+        if (__copy_to_user(&buf->_fxsr_env[0], fx,
                            sizeof(struct i387_fxsave_struct)))
                 return -1;
         return 1;
@@ -417,7 +451,7 @@ static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf)
         struct task_struct *tsk = current;
 
         clear_fpu(tsk);
-        return __copy_from_user(&tsk->thread.i387.fsave, buf,
+        return __copy_from_user(&tsk->thread.xstate->fsave, buf,
                                 sizeof(struct i387_fsave_struct));
 }
 
@@ -428,10 +462,10 @@ static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf)
         int err;
 
         clear_fpu(tsk);
-        err = __copy_from_user(&tsk->thread.i387.fxsave, &buf->_fxsr_env[0],
+        err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0],
                                sizeof(struct i387_fxsave_struct));
         /* mxcsr reserved bits must be masked to zero for security reasons */
-        tsk->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;
+        tsk->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask;
         if (err || __copy_from_user(&env, buf, sizeof(env)))
                 return 1;
         convert_to_fxsr(tsk, &env);
diff --git a/arch/x86/kernel/io_apic_64.c b/arch/x86/kernel/io_apic_64.c
index b54464b26658..9ba11d07920f 100644
--- a/arch/x86/kernel/io_apic_64.c
+++ b/arch/x86/kernel/io_apic_64.c
@@ -785,7 +785,7 @@ static void __clear_irq_vector(int irq)
                 per_cpu(vector_irq, cpu)[vector] = -1;
 
         cfg->vector = 0;
-        cfg->domain = CPU_MASK_NONE;
+        cpus_clear(cfg->domain);
 }
 
 void __setup_vector_irq(int cpu)
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 24362ecf5f9a..f47f0eb886b8 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -46,11 +46,7 @@
 #include <asm/apicdef.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_X86_32
-# include <mach_ipi.h>
-#else
-# include <asm/mach_apic.h>
-#endif
+#include <mach_ipi.h>
 
 /*
  * Put the error code here just in case the user cares:
diff --git a/arch/x86/kernel/microcode.c b/arch/x86/kernel/microcode.c
index 25cf6dee4e56..69729e38b78a 100644
--- a/arch/x86/kernel/microcode.c
+++ b/arch/x86/kernel/microcode.c
@@ -402,7 +402,7 @@ static int do_microcode_update (void)
 
                         if (!uci->valid)
                                 continue;
-                        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+                        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
                         error = get_maching_microcode(new_mc, cpu);
                         if (error < 0)
                                 goto out;
@@ -416,7 +416,7 @@ out:
                 vfree(new_mc);
         if (cursor < 0)
                 error = cursor;
-        set_cpus_allowed(current, old);
+        set_cpus_allowed_ptr(current, &old);
         return error;
 }
 
@@ -579,7 +579,7 @@ static int apply_microcode_check_cpu(int cpu)
                 return 0;
 
         old = current->cpus_allowed;
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
 
         /* Check if the microcode we have in memory matches the CPU */
         if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
@@ -610,7 +610,7 @@ static int apply_microcode_check_cpu(int cpu)
                         " sig=0x%x, pf=0x%x, rev=0x%x\n",
                         cpu, uci->sig, uci->pf, uci->rev);
 
-        set_cpus_allowed(current, old);
+        set_cpus_allowed_ptr(current, &old);
         return err;
 }
 
@@ -621,13 +621,13 @@ static void microcode_init_cpu(int cpu, int resume)
 
         old = current->cpus_allowed;
 
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         mutex_lock(&microcode_mutex);
         collect_cpu_info(cpu);
         if (uci->valid && system_state == SYSTEM_RUNNING && !resume)
                 cpu_request_microcode(cpu);
         mutex_unlock(&microcode_mutex);
-        set_cpus_allowed(current, old);
+        set_cpus_allowed_ptr(current, &old);
 }
 
 static void microcode_fini_cpu(int cpu)
@@ -657,14 +657,14 @@ static ssize_t reload_store(struct sys_device *dev, const char *buf, size_t sz)
                 old = current->cpus_allowed;
 
                 get_online_cpus();
-                set_cpus_allowed(current, cpumask_of_cpu(cpu));
+                set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
 
                 mutex_lock(&microcode_mutex);
                 if (uci->valid)
                         err = cpu_request_microcode(cpu);
                 mutex_unlock(&microcode_mutex);
                 put_online_cpus();
-                set_cpus_allowed(current, old);
+                set_cpus_allowed_ptr(current, &old);
         }
         if (err)
                 return err;
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index 4dfb40530057..1f3abe048e93 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -162,12 +162,10 @@ static int __cpuinit msr_class_cpu_callback(struct notifier_block *nfb,
                 err = msr_device_create(cpu);
                 break;
         case CPU_UP_CANCELED:
+        case CPU_UP_CANCELED_FROZEN:
         case CPU_DEAD:
                 msr_device_destroy(cpu);
                 break;
-        case CPU_UP_CANCELED_FROZEN:
-                destroy_suspended_device(msr_class, MKDEV(MSR_MAJOR, cpu));
-                break;
         }
         return err ? NOTIFY_BAD : NOTIFY_OK;
 }
diff --git a/arch/x86/kernel/nmi_32.c b/arch/x86/kernel/nmi_32.c
index 8421d0ac6f22..11b14bbaa61e 100644
--- a/arch/x86/kernel/nmi_32.c
+++ b/arch/x86/kernel/nmi_32.c
@@ -321,7 +321,8 @@ EXPORT_SYMBOL(touch_nmi_watchdog);
 
 extern void die_nmi(struct pt_regs *, const char *msg);
 
-__kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
+notrace __kprobes int
+nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
 {
 
         /*
diff --git a/arch/x86/kernel/nmi_64.c b/arch/x86/kernel/nmi_64.c
index 11f9130ac513..5a29ded994fa 100644
--- a/arch/x86/kernel/nmi_64.c
+++ b/arch/x86/kernel/nmi_64.c
@@ -313,7 +313,8 @@ void touch_nmi_watchdog(void)
 }
 EXPORT_SYMBOL(touch_nmi_watchdog);
 
-int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
+notrace __kprobes int
+nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
 {
         int sum;
         int touched = 0;
@@ -384,7 +385,8 @@ int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 
 static unsigned ignore_nmis;
 
-asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
+asmlinkage notrace __kprobes void
+do_nmi(struct pt_regs *regs, long error_code)
 {
         nmi_enter();
         add_pda(__nmi_count,1);
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index 1b5464c2434f..adb91e4b62da 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -470,10 +470,11 @@ error:
         return 0;
 }
 
-static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
+static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
         size_t size, int direction)
 {
         dma_addr_t dma_handle = bad_dma_address;
+        void *vaddr = phys_to_virt(paddr);
         unsigned long uaddr;
         unsigned int npages;
         struct iommu_table *tbl = find_iommu_table(dev);
diff --git a/arch/x86/kernel/pci-dma_64.c b/arch/x86/kernel/pci-dma.c
index ada5a0604992..388b113a7d88 100644
--- a/arch/x86/kernel/pci-dma_64.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -1,61 +1,370 @@
-/*
- * Dynamic DMA mapping support.
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/module.h>
+#include <linux/dma-mapping.h>
 #include <linux/dmar.h>
-#include <asm/io.h>
+#include <linux/bootmem.h>
+#include <linux/pci.h>
+
+#include <asm/proto.h>
+#include <asm/dma.h>
 #include <asm/gart.h>
 #include <asm/calgary.h>
 
-int iommu_merge __read_mostly = 0;
-
-dma_addr_t bad_dma_address __read_mostly;
-EXPORT_SYMBOL(bad_dma_address);
+int forbid_dac __read_mostly;
+EXPORT_SYMBOL(forbid_dac);
 
-/* This tells the BIO block layer to assume merging. Default to off
-   because we cannot guarantee merging later. */
-int iommu_bio_merge __read_mostly = 0;
-EXPORT_SYMBOL(iommu_bio_merge);
+const struct dma_mapping_ops *dma_ops;
+EXPORT_SYMBOL(dma_ops);
 
-static int iommu_sac_force __read_mostly = 0;
+int iommu_sac_force __read_mostly = 0;
 
-int no_iommu __read_mostly;
 #ifdef CONFIG_IOMMU_DEBUG
 int panic_on_overflow __read_mostly = 1;
 int force_iommu __read_mostly = 1;
 #else
 int panic_on_overflow __read_mostly = 0;
-int force_iommu __read_mostly= 0;
+int force_iommu __read_mostly = 0;
 #endif
 
+int iommu_merge __read_mostly = 0;
+
+int no_iommu __read_mostly;
 /* Set this to 1 if there is a HW IOMMU in the system */
 int iommu_detected __read_mostly = 0;
 
+/* This tells the BIO block layer to assume merging. Default to off
+   because we cannot guarantee merging later. */
+int iommu_bio_merge __read_mostly = 0;
+EXPORT_SYMBOL(iommu_bio_merge);
+
+dma_addr_t bad_dma_address __read_mostly = 0;
+EXPORT_SYMBOL(bad_dma_address);
+
 /* Dummy device used for NULL arguments (normally ISA). Better would
    be probably a smaller DMA mask, but this is bug-to-bug compatible
-   to i386. */
+   to older i386. */
 struct device fallback_dev = {
         .bus_id = "fallback device",
         .coherent_dma_mask = DMA_32BIT_MASK,
         .dma_mask = &fallback_dev.coherent_dma_mask,
 };
 
+int dma_set_mask(struct device *dev, u64 mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = mask;
+
+        return 0;
+}
+EXPORT_SYMBOL(dma_set_mask);
+
+#ifdef CONFIG_X86_64
+static __initdata void *dma32_bootmem_ptr;
+static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
+
+static int __init parse_dma32_size_opt(char *p)
+{
+        if (!p)
+                return -EINVAL;
+        dma32_bootmem_size = memparse(p, &p);
+        return 0;
+}
+early_param("dma32_size", parse_dma32_size_opt);
+
+void __init dma32_reserve_bootmem(void)
+{
+        unsigned long size, align;
+        if (end_pfn <= MAX_DMA32_PFN)
+                return;
+
+        align = 64ULL<<20;
+        size = round_up(dma32_bootmem_size, align);
+        dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
+                                 __pa(MAX_DMA_ADDRESS));
+        if (dma32_bootmem_ptr)
+                dma32_bootmem_size = size;
+        else
+                dma32_bootmem_size = 0;
+}
+static void __init dma32_free_bootmem(void)
+{
+        int node;
+
+        if (end_pfn <= MAX_DMA32_PFN)
+                return;
+
+        if (!dma32_bootmem_ptr)
+                return;
+
+        for_each_online_node(node)
+                free_bootmem_node(NODE_DATA(node), __pa(dma32_bootmem_ptr),
+                                  dma32_bootmem_size);
+
+        dma32_bootmem_ptr = NULL;
+        dma32_bootmem_size = 0;
+}
+
+void __init pci_iommu_alloc(void)
+{
+        /* free the range so iommu could get some range less than 4G */
+        dma32_free_bootmem();
+        /*
+         * The order of these functions is important for
+         * fall-back/fail-over reasons
+         */
+#ifdef CONFIG_GART_IOMMU
+        gart_iommu_hole_init();
+#endif
+
+#ifdef CONFIG_CALGARY_IOMMU
+        detect_calgary();
+#endif
+
+        detect_intel_iommu();
+
+#ifdef CONFIG_SWIOTLB
+        pci_swiotlb_init();
+#endif
+}
+#endif
+
+/*
+ * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
+ * documentation.
+ */
+static __init int iommu_setup(char *p)
+{
+        iommu_merge = 1;
+
+        if (!p)
+                return -EINVAL;
+
+        while (*p) {
+                if (!strncmp(p, "off", 3))
+                        no_iommu = 1;
+                /* gart_parse_options has more force support */
+                if (!strncmp(p, "force", 5))
+                        force_iommu = 1;
+                if (!strncmp(p, "noforce", 7)) {
+                        iommu_merge = 0;
+                        force_iommu = 0;
+                }
+
+                if (!strncmp(p, "biomerge", 8)) {
+                        iommu_bio_merge = 4096;
+                        iommu_merge = 1;
+                        force_iommu = 1;
+                }
+                if (!strncmp(p, "panic", 5))
+                        panic_on_overflow = 1;
+                if (!strncmp(p, "nopanic", 7))
+                        panic_on_overflow = 0;
+                if (!strncmp(p, "merge", 5)) {
+                        iommu_merge = 1;
+                        force_iommu = 1;
+                }
+                if (!strncmp(p, "nomerge", 7))
+                        iommu_merge = 0;
+                if (!strncmp(p, "forcesac", 8))
+                        iommu_sac_force = 1;
+                if (!strncmp(p, "allowdac", 8))
+                        forbid_dac = 0;
+                if (!strncmp(p, "nodac", 5))
+                        forbid_dac = -1;
+                if (!strncmp(p, "usedac", 6)) {
+                        forbid_dac = -1;
+                        return 1;
+                }
+#ifdef CONFIG_SWIOTLB
+                if (!strncmp(p, "soft", 4))
+                        swiotlb = 1;
+#endif
+
+#ifdef CONFIG_GART_IOMMU
+                gart_parse_options(p);
+#endif
+
+#ifdef CONFIG_CALGARY_IOMMU
+                if (!strncmp(p, "calgary", 7))
+                        use_calgary = 1;
+#endif /* CONFIG_CALGARY_IOMMU */
+
+                p += strcspn(p, ",");
+                if (*p == ',')
+                        ++p;
+        }
+        return 0;
+}
+early_param("iommu", iommu_setup);
+
+#ifdef CONFIG_X86_32
+int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+                                dma_addr_t device_addr, size_t size, int flags)
+{
+        void __iomem *mem_base = NULL;
+        int pages = size >> PAGE_SHIFT;
+        int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
+
+        if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
+                goto out;
+        if (!size)
+                goto out;
+        if (dev->dma_mem)
+                goto out;
+
+        /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
+
+        mem_base = ioremap(bus_addr, size);
+        if (!mem_base)
+                goto out;
+
+        dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
+        if (!dev->dma_mem)
+                goto out;
+        dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+        if (!dev->dma_mem->bitmap)
+                goto free1_out;
+
+        dev->dma_mem->virt_base = mem_base;
+        dev->dma_mem->device_base = device_addr;
+        dev->dma_mem->size = pages;
+        dev->dma_mem->flags = flags;
+
+        if (flags & DMA_MEMORY_MAP)
+                return DMA_MEMORY_MAP;
+
+        return DMA_MEMORY_IO;
+
+ free1_out:
+        kfree(dev->dma_mem);
+ out:
+        if (mem_base)
+                iounmap(mem_base);
+        return 0;
+}
+EXPORT_SYMBOL(dma_declare_coherent_memory);
+
+void dma_release_declared_memory(struct device *dev)
+{
+        struct dma_coherent_mem *mem = dev->dma_mem;
+
+        if (!mem)
+                return;
+        dev->dma_mem = NULL;
+        iounmap(mem->virt_base);
+        kfree(mem->bitmap);
+        kfree(mem);
+}
+EXPORT_SYMBOL(dma_release_declared_memory);
+
+void *dma_mark_declared_memory_occupied(struct device *dev,
+                                        dma_addr_t device_addr, size_t size)
+{
+        struct dma_coherent_mem *mem = dev->dma_mem;
+        int pos, err;
+        int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1);
+
+        pages >>= PAGE_SHIFT;
+
+        if (!mem)
+                return ERR_PTR(-EINVAL);
+
+        pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
+        err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
+        if (err != 0)
+                return ERR_PTR(err);
+        return mem->virt_base + (pos << PAGE_SHIFT);
+}
+EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
+
+static int dma_alloc_from_coherent_mem(struct device *dev, ssize_t size,
+                                       dma_addr_t *dma_handle, void **ret)
+{
+        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+        int order = get_order(size);
+
+        if (mem) {
+                int page = bitmap_find_free_region(mem->bitmap, mem->size,
+                                                     order);
+                if (page >= 0) {
+                        *dma_handle = mem->device_base + (page << PAGE_SHIFT);
+                        *ret = mem->virt_base + (page << PAGE_SHIFT);
+                        memset(*ret, 0, size);
+                }
+                if (mem->flags & DMA_MEMORY_EXCLUSIVE)
+                        *ret = NULL;
+        }
+        return (mem != NULL);
+}
+
+static int dma_release_coherent(struct device *dev, int order, void *vaddr)
+{
+        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+
+        if (mem && vaddr >= mem->virt_base && vaddr <
+                   (mem->virt_base + (mem->size << PAGE_SHIFT))) {
+                int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
+
+                bitmap_release_region(mem->bitmap, page, order);
+                return 1;
+        }
+        return 0;
+}
+#else
+#define dma_alloc_from_coherent_mem(dev, size, handle, ret) (0)
+#define dma_release_coherent(dev, order, vaddr) (0)
+#endif /* CONFIG_X86_32 */
+
+int dma_supported(struct device *dev, u64 mask)
+{
+#ifdef CONFIG_PCI
+        if (mask > 0xffffffff && forbid_dac > 0) {
+                printk(KERN_INFO "PCI: Disallowing DAC for device %s\n",
+                                 dev->bus_id);
+                return 0;
+        }
+#endif
+
+        if (dma_ops->dma_supported)
+                return dma_ops->dma_supported(dev, mask);
+
+        /* Copied from i386. Doesn't make much sense, because it will
+           only work for pci_alloc_coherent.
+           The caller just has to use GFP_DMA in this case. */
+        if (mask < DMA_24BIT_MASK)
+                return 0;
+
+        /* Tell the device to use SAC when IOMMU force is on.  This
+           allows the driver to use cheaper accesses in some cases.
+
+           Problem with this is that if we overflow the IOMMU area and
+           return DAC as fallback address the device may not handle it
+           correctly.
+
+           As a special case some controllers have a 39bit address
+           mode that is as efficient as 32bit (aic79xx). Don't force
+           SAC for these.  Assume all masks <= 40 bits are of this
+           type. Normally this doesn't make any difference, but gives
+           more gentle handling of IOMMU overflow. */
+        if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
+                printk(KERN_INFO "%s: Force SAC with mask %Lx\n",
+                                 dev->bus_id, mask);
+                return 0;
+        }
+
+        return 1;
+}
+EXPORT_SYMBOL(dma_supported);
+
 /* Allocate DMA memory on node near device */
-noinline static void *
+noinline struct page *
 dma_alloc_pages(struct device *dev, gfp_t gfp, unsigned order)
 {
-        struct page *page;
         int node;
 
         node = dev_to_node(dev);
 
-        page = alloc_pages_node(node, gfp, order);
-        return page ? page_address(page) : NULL;
+        return alloc_pages_node(node, gfp, order);
 }
 
 /*
@@ -65,9 +374,16 @@ void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
                    gfp_t gfp)
 {
-        void *memory;
+        void *memory = NULL;
+        struct page *page;
         unsigned long dma_mask = 0;
-        u64 bus;
+        dma_addr_t bus;
+
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
+
+        if (dma_alloc_from_coherent_mem(dev, size, dma_handle, &memory))
+                return memory;
 
         if (!dev)
                 dev = &fallback_dev;
@@ -82,26 +398,25 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
         /* Don't invoke OOM killer */
         gfp |= __GFP_NORETRY;
 
-        /* Kludge to make it bug-to-bug compatible with i386. i386
-           uses the normal dma_mask for alloc_coherent. */
-        dma_mask &= *dev->dma_mask;
-
+#ifdef CONFIG_X86_64
         /* Why <=? Even when the mask is smaller than 4GB it is often
            larger than 16MB and in this case we have a chance of
            finding fitting memory in the next higher zone first. If
            not retry with true GFP_DMA. -AK */
         if (dma_mask <= DMA_32BIT_MASK)
                 gfp |= GFP_DMA32;
+#endif
 
  again:
-        memory = dma_alloc_pages(dev, gfp, get_order(size));
-        if (memory == NULL)
+        page = dma_alloc_pages(dev, gfp, get_order(size));
+        if (page == NULL)
                 return NULL;
 
         {
                 int high, mmu;
-                bus = virt_to_bus(memory);
-                high = (bus + size) >= dma_mask;
+                bus = page_to_phys(page);
+                memory = page_address(page);
+                high = (bus + size) >= dma_mask;
                 mmu = high;
                 if (force_iommu && !(gfp & GFP_DMA))
                         mmu = 1;
@@ -127,7 +442,7 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
 
                 memset(memory, 0, size);
                 if (!mmu) {
-                        *dma_handle = virt_to_bus(memory);
+                        *dma_handle = bus;
                         return memory;
                 }
         }
@@ -139,7 +454,7 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
         }
 
         if (dma_ops->map_simple) {
-                *dma_handle = dma_ops->map_simple(dev, memory,
+                *dma_handle = dma_ops->map_simple(dev, virt_to_phys(memory),
                                               size,
                                               PCI_DMA_BIDIRECTIONAL);
                 if (*dma_handle != bad_dma_address)
@@ -147,7 +462,8 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
         }
 
         if (panic_on_overflow)
-                panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",size);
+                panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",
+                      (unsigned long)size);
         free_pages((unsigned long)memory, get_order(size));
         return NULL;
 }
@@ -160,153 +476,16 @@ EXPORT_SYMBOL(dma_alloc_coherent);
 void dma_free_coherent(struct device *dev, size_t size,
                          void *vaddr, dma_addr_t bus)
 {
+        int order = get_order(size);
         WARN_ON(irqs_disabled());       /* for portability */
+        if (dma_release_coherent(dev, order, vaddr))
+                return;
         if (dma_ops->unmap_single)
                 dma_ops->unmap_single(dev, bus, size, 0);
-        free_pages((unsigned long)vaddr, get_order(size));
+        free_pages((unsigned long)vaddr, order);
 }
 EXPORT_SYMBOL(dma_free_coherent);
 
-static int forbid_dac __read_mostly;
-
-int dma_supported(struct device *dev, u64 mask)
-{
-#ifdef CONFIG_PCI
-        if (mask > 0xffffffff && forbid_dac > 0) {
-
-
-
-                printk(KERN_INFO "PCI: Disallowing DAC for device %s\n", dev->bus_id);
-                return 0;
-        }
-#endif
-
-        if (dma_ops->dma_supported)
-                return dma_ops->dma_supported(dev, mask);
-
-        /* Copied from i386. Doesn't make much sense, because it will
-           only work for pci_alloc_coherent.
-           The caller just has to use GFP_DMA in this case. */
-        if (mask < DMA_24BIT_MASK)
-                return 0;
-
-        /* Tell the device to use SAC when IOMMU force is on.  This
-           allows the driver to use cheaper accesses in some cases.
-
-           Problem with this is that if we overflow the IOMMU area and
-           return DAC as fallback address the device may not handle it
-           correctly.
-
-           As a special case some controllers have a 39bit address
-           mode that is as efficient as 32bit (aic79xx). Don't force
-           SAC for these.  Assume all masks <= 40 bits are of this
-           type. Normally this doesn't make any difference, but gives
-           more gentle handling of IOMMU overflow. */
-        if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
-                printk(KERN_INFO "%s: Force SAC with mask %Lx\n", dev->bus_id,mask);
-                return 0;
-        }
-
-        return 1;
-}
-EXPORT_SYMBOL(dma_supported);
-
-int dma_set_mask(struct device *dev, u64 mask)
-{
-        if (!dev->dma_mask || !dma_supported(dev, mask))
-                return -EIO;
-        *dev->dma_mask = mask;
-        return 0;
-}
-EXPORT_SYMBOL(dma_set_mask);
-
-/*
- * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
- * documentation.
- */
-static __init int iommu_setup(char *p)
-{
-        iommu_merge = 1;
-
-        if (!p)
-                return -EINVAL;
-
-        while (*p) {
-                if (!strncmp(p, "off", 3))
-                        no_iommu = 1;
-                /* gart_parse_options has more force support */
-                if (!strncmp(p, "force", 5))
-                        force_iommu = 1;
-                if (!strncmp(p, "noforce", 7)) {
-                        iommu_merge = 0;
-                        force_iommu = 0;
-                }
-
-                if (!strncmp(p, "biomerge", 8)) {
-                        iommu_bio_merge = 4096;
-                        iommu_merge = 1;
-                        force_iommu = 1;
-                }
-                if (!strncmp(p, "panic", 5))
-                        panic_on_overflow = 1;
-                if (!strncmp(p, "nopanic", 7))
-                        panic_on_overflow = 0;
-                if (!strncmp(p, "merge", 5)) {
-                        iommu_merge = 1;
-                        force_iommu = 1;
-                }
-                if (!strncmp(p, "nomerge", 7))
-                        iommu_merge = 0;
-                if (!strncmp(p, "forcesac", 8))
-                        iommu_sac_force = 1;
-                if (!strncmp(p, "allowdac", 8))
-                        forbid_dac = 0;
-                if (!strncmp(p, "nodac", 5))
-                        forbid_dac = -1;
-
-#ifdef CONFIG_SWIOTLB
-                if (!strncmp(p, "soft", 4))
-                        swiotlb = 1;
-#endif
-
-#ifdef CONFIG_GART_IOMMU
-                gart_parse_options(p);
-#endif
-
-#ifdef CONFIG_CALGARY_IOMMU
-                if (!strncmp(p, "calgary", 7))
-                        use_calgary = 1;
-#endif /* CONFIG_CALGARY_IOMMU */
-
-                p += strcspn(p, ",");
-                if (*p == ',')
-                        ++p;
-        }
-        return 0;
-}
-early_param("iommu", iommu_setup);
-
-void __init pci_iommu_alloc(void)
-{
-        /*
-         * The order of these functions is important for
-         * fall-back/fail-over reasons
-         */
-#ifdef CONFIG_GART_IOMMU
-        gart_iommu_hole_init();
-#endif
-
-#ifdef CONFIG_CALGARY_IOMMU
-        detect_calgary();
-#endif
-
-        detect_intel_iommu();
-
-#ifdef CONFIG_SWIOTLB
-        pci_swiotlb_init();
-#endif
-}
-
 static int __init pci_iommu_init(void)
 {
 #ifdef CONFIG_CALGARY_IOMMU
@@ -327,6 +506,8 @@ void pci_iommu_shutdown(void)
 {
         gart_iommu_shutdown();
 }
+/* Must execute after PCI subsystem */
+fs_initcall(pci_iommu_init);
 
 #ifdef CONFIG_PCI
 /* Many VIA bridges seem to corrupt data for DAC. Disable it here */
@@ -334,11 +515,10 @@ void pci_iommu_shutdown(void)
 static __devinit void via_no_dac(struct pci_dev *dev)
 {
         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
-                printk(KERN_INFO "PCI: VIA PCI bridge detected. Disabling DAC.\n");
+                printk(KERN_INFO "PCI: VIA PCI bridge detected."
+                                 "Disabling DAC.\n");
                 forbid_dac = 1;
         }
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
 #endif
-/* Must execute after PCI subsystem */
-fs_initcall(pci_iommu_init);
diff --git a/arch/x86/kernel/pci-dma_32.c b/arch/x86/kernel/pci-dma_32.c
deleted file mode 100644
index 51330321a5d3..000000000000
--- a/arch/x86/kernel/pci-dma_32.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Dynamic DMA mapping support.
- *
- * On i386 there is no hardware dynamic DMA address translation,
- * so consistent alloc/free are merely page allocation/freeing.
- * The rest of the dynamic DMA mapping interface is implemented
- * in asm/pci.h.
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/module.h>
-#include <asm/io.h>
-
-struct dma_coherent_mem {
-        void            *virt_base;
-        u32             device_base;
-        int             size;
-        int             flags;
-        unsigned long   *bitmap;
-};
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t gfp)
-{
-        void *ret;
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
-        int order = get_order(size);
-        /* ignore region specifiers */
-        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
-
-        if (mem) {
-                int page = bitmap_find_free_region(mem->bitmap, mem->size,
-                                                     order);
-                if (page >= 0) {
-                        *dma_handle = mem->device_base + (page << PAGE_SHIFT);
-                        ret = mem->virt_base + (page << PAGE_SHIFT);
-                        memset(ret, 0, size);
-                        return ret;
-                }
-                if (mem->flags & DMA_MEMORY_EXCLUSIVE)
-                        return NULL;
-        }
-
-        if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
-                gfp |= GFP_DMA;
-
-        ret = (void *)__get_free_pages(gfp, order);
-
-        if (ret != NULL) {
-                memset(ret, 0, size);
-                *dma_handle = virt_to_phys(ret);
-        }
-        return ret;
-}
-EXPORT_SYMBOL(dma_alloc_coherent);
-
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle)
-{
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
-        int order = get_order(size);
-
-        WARN_ON(irqs_disabled());       /* for portability */
-        if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) {
-                int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
-
-                bitmap_release_region(mem->bitmap, page, order);
-        } else
-                free_pages((unsigned long)vaddr, order);
-}
-EXPORT_SYMBOL(dma_free_coherent);
-
-int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
-                                dma_addr_t device_addr, size_t size, int flags)
-{
-        void __iomem *mem_base = NULL;
-        int pages = size >> PAGE_SHIFT;
-        int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
-
-        if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
-                goto out;
-        if (!size)
-                goto out;
-        if (dev->dma_mem)
-                goto out;
-
-        /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
-
-        mem_base = ioremap(bus_addr, size);
-        if (!mem_base)
-                goto out;
-
-        dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
-        if (!dev->dma_mem)
-                goto out;
-        dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-        if (!dev->dma_mem->bitmap)
-                goto free1_out;
-
-        dev->dma_mem->virt_base = mem_base;
-        dev->dma_mem->device_base = device_addr;
-        dev->dma_mem->size = pages;
-        dev->dma_mem->flags = flags;
-
-        if (flags & DMA_MEMORY_MAP)
-                return DMA_MEMORY_MAP;
-
-        return DMA_MEMORY_IO;
-
- free1_out:
-        kfree(dev->dma_mem);
- out:
-        if (mem_base)
-                iounmap(mem_base);
-        return 0;
-}
-EXPORT_SYMBOL(dma_declare_coherent_memory);
-
-void dma_release_declared_memory(struct device *dev)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-        
-        if(!mem)
-                return;
-        dev->dma_mem = NULL;
-        iounmap(mem->virt_base);
-        kfree(mem->bitmap);
-        kfree(mem);
-}
-EXPORT_SYMBOL(dma_release_declared_memory);
-
-void *dma_mark_declared_memory_occupied(struct device *dev,
-                                        dma_addr_t device_addr, size_t size)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-        int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT;
-        int pos, err;
-
-        if (!mem)
-                return ERR_PTR(-EINVAL);
-
-        pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
-        err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
-        if (err != 0)
-                return ERR_PTR(err);
-        return mem->virt_base + (pos << PAGE_SHIFT);
-}
-EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
-
-#ifdef CONFIG_PCI
-/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
-
-int forbid_dac;
-EXPORT_SYMBOL(forbid_dac);
-
-static __devinit void via_no_dac(struct pci_dev *dev)
-{
-        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
-                printk(KERN_INFO "PCI: VIA PCI bridge detected. Disabling DAC.\n");
-                forbid_dac = 1;
-        }
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
-
-static int check_iommu(char *s)
-{
-        if (!strcmp(s, "usedac")) {
-                forbid_dac = -1;
-                return 1;
-        }
-        return 0;
-}
-__setup("iommu=", check_iommu);
-#endif
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 700e4647dd30..c07455d1695f 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -264,9 +264,9 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
 }
 
 static dma_addr_t
-gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
+gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir)
 {
-        dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
+        dma_addr_t map = dma_map_area(dev, paddr, size, dir);
 
         flush_gart();
 
@@ -275,18 +275,17 @@ gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
 
 /* Map a single area into the IOMMU */
 static dma_addr_t
-gart_map_single(struct device *dev, void *addr, size_t size, int dir)
+gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
 {
-        unsigned long phys_mem, bus;
+        unsigned long bus;
 
         if (!dev)
                 dev = &fallback_dev;
 
-        phys_mem = virt_to_phys(addr);
-        if (!need_iommu(dev, phys_mem, size))
-                return phys_mem;
+        if (!need_iommu(dev, paddr, size))
+                return paddr;
 
-        bus = gart_map_simple(dev, addr, size, dir);
+        bus = gart_map_simple(dev, paddr, size, dir);
 
         return bus;
 }
diff --git a/arch/x86/kernel/pci-nommu_64.c b/arch/x86/kernel/pci-nommu.c
index ab08e1832228..aec43d56f49c 100644
--- a/arch/x86/kernel/pci-nommu_64.c
+++ b/arch/x86/kernel/pci-nommu.c
@@ -14,7 +14,7 @@
 static int
 check_addr(char *name, struct device *hwdev, dma_addr_t bus, size_t size)
 {
-        if (hwdev && bus + size > *hwdev->dma_mask) {
+        if (hwdev && bus + size > *hwdev->dma_mask) {
                 if (*hwdev->dma_mask >= DMA_32BIT_MASK)
                         printk(KERN_ERR
                             "nommu_%s: overflow %Lx+%zu of device mask %Lx\n",
@@ -26,19 +26,17 @@ check_addr(char *name, struct device *hwdev, dma_addr_t bus, size_t size)
 }
 
 static dma_addr_t
-nommu_map_single(struct device *hwdev, void *ptr, size_t size,
+nommu_map_single(struct device *hwdev, phys_addr_t paddr, size_t size,
                int direction)
 {
-        dma_addr_t bus = virt_to_bus(ptr);
+        dma_addr_t bus = paddr;
+        WARN_ON(size == 0);
         if (!check_addr("map_single", hwdev, bus, size))
                                 return bad_dma_address;
+        flush_write_buffers();
         return bus;
 }
 
-static void nommu_unmap_single(struct device *dev, dma_addr_t addr,size_t size,
-                        int direction)
-{
-}
 
 /* Map a set of buffers described by scatterlist in streaming
  * mode for DMA.  This is the scatter-gather version of the
@@ -61,30 +59,34 @@ static int nommu_map_sg(struct device *hwdev, struct scatterlist *sg,
         struct scatterlist *s;
         int i;
 
+        WARN_ON(nents == 0 || sg[0].length == 0);
+
         for_each_sg(sg, s, nents, i) {
                 BUG_ON(!sg_page(s));
-                s->dma_address = virt_to_bus(sg_virt(s));
+                s->dma_address = sg_phys(s);
                 if (!check_addr("map_sg", hwdev, s->dma_address, s->length))
                         return 0;
                 s->dma_length = s->length;
         }
+        flush_write_buffers();
         return nents;
 }
 
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-static void nommu_unmap_sg(struct device *dev, struct scatterlist *sg,
-                  int nents, int dir)
+/* Make sure we keep the same behaviour */
+static int nommu_mapping_error(dma_addr_t dma_addr)
 {
+#ifdef CONFIG_X86_32
+        return 0;
+#else
+        return (dma_addr == bad_dma_address);
+#endif
 }
 
+
 const struct dma_mapping_ops nommu_dma_ops = {
         .map_single = nommu_map_single,
-        .unmap_single = nommu_unmap_single,
         .map_sg = nommu_map_sg,
-        .unmap_sg = nommu_unmap_sg,
+        .mapping_error = nommu_mapping_error,
         .is_phys = 1,
 };
 
diff --git a/arch/x86/kernel/pci-swiotlb_64.c b/arch/x86/kernel/pci-swiotlb_64.c
index 82a0a674a003..490da7f4b8d0 100644
--- a/arch/x86/kernel/pci-swiotlb_64.c
+++ b/arch/x86/kernel/pci-swiotlb_64.c
@@ -11,11 +11,18 @@
 
 int swiotlb __read_mostly;
 
+static dma_addr_t
+swiotlb_map_single_phys(struct device *hwdev, phys_addr_t paddr, size_t size,
+                        int direction)
+{
+        return swiotlb_map_single(hwdev, phys_to_virt(paddr), size, direction);
+}
+
 const struct dma_mapping_ops swiotlb_dma_ops = {
         .mapping_error = swiotlb_dma_mapping_error,
         .alloc_coherent = swiotlb_alloc_coherent,
         .free_coherent = swiotlb_free_coherent,
-        .map_single = swiotlb_map_single,
+        .map_single = swiotlb_map_single_phys,
         .unmap_single = swiotlb_unmap_single,
         .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
         .sync_single_for_device = swiotlb_sync_single_for_device,
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
new file mode 100644
index 000000000000..3004d716539d
--- /dev/null
+++ b/arch/x86/kernel/process.c
@@ -0,0 +1,44 @@
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+
+struct kmem_cache *task_xstate_cachep;
+
+int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
+{
+        *dst = *src;
+        if (src->thread.xstate) {
+                dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
+                                                      GFP_KERNEL);
+                if (!dst->thread.xstate)
+                        return -ENOMEM;
+                WARN_ON((unsigned long)dst->thread.xstate & 15);
+                memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
+        }
+        return 0;
+}
+
+void free_thread_xstate(struct task_struct *tsk)
+{
+        if (tsk->thread.xstate) {
+                kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
+                tsk->thread.xstate = NULL;
+        }
+}
+
+void free_thread_info(struct thread_info *ti)
+{
+        free_thread_xstate(ti->task);
+        free_pages((unsigned long)ti, get_order(THREAD_SIZE));
+}
+
+void arch_task_cache_init(void)
+{
+        task_xstate_cachep =
+                kmem_cache_create("task_xstate", xstate_size,
+                                  __alignof__(union thread_xstate),
+                                  SLAB_PANIC, NULL);
+}
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 3903a8f2eb97..7adad088e373 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -36,6 +36,7 @@
 #include <linux/personality.h>
 #include <linux/tick.h>
 #include <linux/percpu.h>
+#include <linux/prctl.h>
 
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -45,7 +46,6 @@
 #include <asm/processor.h>
 #include <asm/i387.h>
 #include <asm/desc.h>
-#include <asm/vm86.h>
 #ifdef CONFIG_MATH_EMULATION
 #include <asm/math_emu.h>
 #endif
@@ -521,14 +521,18 @@ start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
         regs->cs                = __USER_CS;
         regs->ip                = new_ip;
         regs->sp                = new_sp;
+        /*
+         * Free the old FP and other extended state
+         */
+        free_thread_xstate(current);
 }
 EXPORT_SYMBOL_GPL(start_thread);
 
-#ifdef CONFIG_SECCOMP
 static void hard_disable_TSC(void)
 {
         write_cr4(read_cr4() | X86_CR4_TSD);
 }
+
 void disable_TSC(void)
 {
         preempt_disable();
@@ -540,11 +544,47 @@ void disable_TSC(void)
                 hard_disable_TSC();
         preempt_enable();
 }
+
 static void hard_enable_TSC(void)
 {
         write_cr4(read_cr4() & ~X86_CR4_TSD);
 }
-#endif /* CONFIG_SECCOMP */
+
+void enable_TSC(void)
+{
+        preempt_disable();
+        if (test_and_clear_thread_flag(TIF_NOTSC))
+                /*
+                 * Must flip the CPU state synchronously with
+                 * TIF_NOTSC in the current running context.
+                 */
+                hard_enable_TSC();
+        preempt_enable();
+}
+
+int get_tsc_mode(unsigned long adr)
+{
+        unsigned int val;
+
+        if (test_thread_flag(TIF_NOTSC))
+                val = PR_TSC_SIGSEGV;
+        else
+                val = PR_TSC_ENABLE;
+
+        return put_user(val, (unsigned int __user *)adr);
+}
+
+int set_tsc_mode(unsigned int val)
+{
+        if (val == PR_TSC_SIGSEGV)
+                disable_TSC();
+        else if (val == PR_TSC_ENABLE)
+                enable_TSC();
+        else
+                return -EINVAL;
+
+        return 0;
+}
 
 static noinline void
 __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
@@ -578,7 +618,6 @@ __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
                 set_debugreg(next->debugreg7, 7);
         }
 
-#ifdef CONFIG_SECCOMP
         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
                 /* prev and next are different */
@@ -587,7 +626,6 @@ __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
                 else
                         hard_enable_TSC();
         }
-#endif
 
 #ifdef X86_BTS
         if (test_tsk_thread_flag(prev_p, TIF_BTS_TRACE_TS))
@@ -669,7 +707,7 @@ struct task_struct * __switch_to(struct task_struct *prev_p, struct task_struct
 
         /* we're going to use this soon, after a few expensive things */
         if (next_p->fpu_counter > 5)
-                prefetch(&next->i387.fxsave);
+                prefetch(next->xstate);
 
         /*
          * Reload esp0.
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index e75ccc8a2b87..891af1a1b48a 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -36,6 +36,7 @@
 #include <linux/kprobes.h>
 #include <linux/kdebug.h>
 #include <linux/tick.h>
+#include <linux/prctl.h>
 
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -532,9 +533,71 @@ start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
         regs->ss                = __USER_DS;
         regs->flags             = 0x200;
         set_fs(USER_DS);
+        /*
+         * Free the old FP and other extended state
+         */
+        free_thread_xstate(current);
 }
 EXPORT_SYMBOL_GPL(start_thread);
 
+static void hard_disable_TSC(void)
+{
+        write_cr4(read_cr4() | X86_CR4_TSD);
+}
+
+void disable_TSC(void)
+{
+        preempt_disable();
+        if (!test_and_set_thread_flag(TIF_NOTSC))
+                /*
+                 * Must flip the CPU state synchronously with
+                 * TIF_NOTSC in the current running context.
+                 */
+                hard_disable_TSC();
+        preempt_enable();
+}
+
+static void hard_enable_TSC(void)
+{
+        write_cr4(read_cr4() & ~X86_CR4_TSD);
+}
+
+void enable_TSC(void)
+{
+        preempt_disable();
+        if (test_and_clear_thread_flag(TIF_NOTSC))
+                /*
+                 * Must flip the CPU state synchronously with
+                 * TIF_NOTSC in the current running context.
+                 */
+                hard_enable_TSC();
+        preempt_enable();
+}
+
+int get_tsc_mode(unsigned long adr)
+{
+        unsigned int val;
+
+        if (test_thread_flag(TIF_NOTSC))
+                val = PR_TSC_SIGSEGV;
+        else
+                val = PR_TSC_ENABLE;
+
+        return put_user(val, (unsigned int __user *)adr);
+}
+
+int set_tsc_mode(unsigned int val)
+{
+        if (val == PR_TSC_SIGSEGV)
+                disable_TSC();
+        else if (val == PR_TSC_ENABLE)
+                enable_TSC();
+        else
+                return -EINVAL;
+
+        return 0;
+}
+
 /*
  * This special macro can be used to load a debugging register
  */
@@ -572,6 +635,15 @@ static inline void __switch_to_xtra(struct task_struct *prev_p,
                 loaddebug(next, 7);
         }
 
+        if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
+            test_tsk_thread_flag(next_p, TIF_NOTSC)) {
+                /* prev and next are different */
+                if (test_tsk_thread_flag(next_p, TIF_NOTSC))
+                        hard_disable_TSC();
+                else
+                        hard_enable_TSC();
+        }
+
         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
                 /*
                  * Copy the relevant range of the IO bitmap.
@@ -614,7 +686,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
 
         /* we're going to use this soon, after a few expensive things */
         if (next_p->fpu_counter>5)
-                prefetch(&next->i387.fxsave);
+                prefetch(next->xstate);
 
         /*
          * Reload esp0, LDT and the page table pointer:
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 9692202d3bfb..19c9386ac118 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -420,7 +420,7 @@ static void native_machine_shutdown(void)
                 reboot_cpu_id = smp_processor_id();
 
         /* Make certain I only run on the appropriate processor */
-        set_cpus_allowed(current, cpumask_of_cpu(reboot_cpu_id));
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(reboot_cpu_id));
 
         /* O.K Now that I'm on the appropriate processor,
          * stop all of the others.
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index ed157c90412e..0d1f44ae6eea 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -54,6 +54,24 @@ static void __init setup_per_cpu_maps(void)
 #endif
 }
 
+#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
+cpumask_t *cpumask_of_cpu_map __read_mostly;
+EXPORT_SYMBOL(cpumask_of_cpu_map);
+
+/* requires nr_cpu_ids to be initialized */
+static void __init setup_cpumask_of_cpu(void)
+{
+        int i;
+
+        /* alloc_bootmem zeroes memory */
+        cpumask_of_cpu_map = alloc_bootmem_low(sizeof(cpumask_t) * nr_cpu_ids);
+        for (i = 0; i < nr_cpu_ids; i++)
+                cpu_set(i, cpumask_of_cpu_map[i]);
+}
+#else
+static inline void setup_cpumask_of_cpu(void) { }
+#endif
+
 #ifdef CONFIG_X86_32
 /*
  * Great future not-so-futuristic plan: make i386 and x86_64 do it
@@ -70,7 +88,7 @@ EXPORT_SYMBOL(__per_cpu_offset);
  */
 void __init setup_per_cpu_areas(void)
 {
-        int i;
+        int i, highest_cpu = 0;
         unsigned long size;
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -104,10 +122,18 @@ void __init setup_per_cpu_areas(void)
                 __per_cpu_offset[i] = ptr - __per_cpu_start;
 #endif
                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
+
+                highest_cpu = i;
         }
 
+        nr_cpu_ids = highest_cpu + 1;
+        printk(KERN_DEBUG "NR_CPUS: %d, nr_cpu_ids: %d\n", NR_CPUS, nr_cpu_ids);
+
         /* Setup percpu data maps */
         setup_per_cpu_maps();
+
+        /* Setup cpumask_of_cpu map */
+        setup_cpumask_of_cpu();
 }
 
 #endif
diff --git a/arch/x86/kernel/setup64.c b/arch/x86/kernel/setup64.c
index 9042fb0e36f5..aee0e8200777 100644
--- a/arch/x86/kernel/setup64.c
+++ b/arch/x86/kernel/setup64.c
@@ -74,8 +74,8 @@ int force_personality32 = 0;
 Control non executable heap for 32bit processes.
 To control the stack too use noexec=off
 
-on      PROT_READ does not imply PROT_EXEC for 32bit processes
-off     PROT_READ implies PROT_EXEC (default)
+on      PROT_READ does not imply PROT_EXEC for 32bit processes (default)
+off     PROT_READ implies PROT_EXEC
 */
 static int __init nonx32_setup(char *str)
 {
diff --git a/arch/x86/kernel/setup_32.c b/arch/x86/kernel/setup_32.c
index 5b0bffb7fcc9..78828b0f604f 100644
--- a/arch/x86/kernel/setup_32.c
+++ b/arch/x86/kernel/setup_32.c
@@ -39,6 +39,7 @@
 #include <linux/efi.h>
 #include <linux/init.h>
 #include <linux/edd.h>
+#include <linux/iscsi_ibft.h>
 #include <linux/nodemask.h>
 #include <linux/kexec.h>
 #include <linux/crash_dump.h>
@@ -689,6 +690,8 @@ void __init setup_bootmem_allocator(void)
 #endif
         numa_kva_reserve();
         reserve_crashkernel();
+
+        reserve_ibft_region();
 }
 
 /*
@@ -812,10 +815,10 @@ void __init setup_arch(char **cmdline_p)
                 efi_init();
 
         /* update e820 for memory not covered by WB MTRRs */
-        find_max_pfn();
+        propagate_e820_map();
         mtrr_bp_init();
         if (mtrr_trim_uncached_memory(max_pfn))
-                find_max_pfn();
+                propagate_e820_map();
 
         max_low_pfn = setup_memory();
 
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 674ef3510cdf..c2ec3dcb6b99 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -33,6 +33,7 @@
 #include <linux/acpi.h>
 #include <linux/kallsyms.h>
 #include <linux/edd.h>
+#include <linux/iscsi_ibft.h>
 #include <linux/mmzone.h>
 #include <linux/kexec.h>
 #include <linux/cpufreq.h>
@@ -398,6 +399,8 @@ void __init setup_arch(char **cmdline_p)
 
         early_res_to_bootmem();
 
+        dma32_reserve_bootmem();
+
 #ifdef CONFIG_ACPI_SLEEP
         /*
          * Reserve low memory region for sleep support.
@@ -420,11 +423,14 @@ void __init setup_arch(char **cmdline_p)
                 unsigned long end_of_mem    = end_pfn << PAGE_SHIFT;
 
                 if (ramdisk_end <= end_of_mem) {
-                        reserve_bootmem_generic(ramdisk_image, ramdisk_size);
+                        /*
+                         * don't need to reserve again, already reserved early
+                         * in x86_64_start_kernel, and early_res_to_bootmem
+                         * convert that to reserved in bootmem
+                         */
                         initrd_start = ramdisk_image + PAGE_OFFSET;
                         initrd_end = initrd_start+ramdisk_size;
                 } else {
-                        /* Assumes everything on node 0 */
                         free_bootmem(ramdisk_image, ramdisk_size);
                         printk(KERN_ERR "initrd extends beyond end of memory "
                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
@@ -434,6 +440,9 @@ void __init setup_arch(char **cmdline_p)
         }
 #endif
         reserve_crashkernel();
+
+        reserve_ibft_region();
+
         paging_init();
         map_vsyscall();
 
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index e6abe8a49b1f..6a925394bc7e 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -61,6 +61,7 @@
 #include <asm/mtrr.h>
 #include <asm/nmi.h>
 #include <asm/vmi.h>
+#include <asm/genapic.h>
 #include <linux/mc146818rtc.h>
 
 #include <mach_apic.h>
@@ -677,6 +678,12 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
         unsigned long send_status, accept_status = 0;
         int maxlvt, num_starts, j;
 
+        if (get_uv_system_type() == UV_NON_UNIQUE_APIC) {
+                send_status = uv_wakeup_secondary(phys_apicid, start_eip);
+                atomic_set(&init_deasserted, 1);
+                return send_status;
+        }
+
         /*
          * Be paranoid about clearing APIC errors.
          */
@@ -918,16 +925,19 @@ do_rest:
 
         atomic_set(&init_deasserted, 0);
 
-        Dprintk("Setting warm reset code and vector.\n");
+        if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
 
-        store_NMI_vector(&nmi_high, &nmi_low);
+                Dprintk("Setting warm reset code and vector.\n");
 
-        smpboot_setup_warm_reset_vector(start_ip);
-        /*
-         * Be paranoid about clearing APIC errors.
-         */
-        apic_write(APIC_ESR, 0);
-        apic_read(APIC_ESR);
+                store_NMI_vector(&nmi_high, &nmi_low);
+
+                smpboot_setup_warm_reset_vector(start_ip);
+                /*
+                 * Be paranoid about clearing APIC errors.
+                */
+                apic_write(APIC_ESR, 0);
+                apic_read(APIC_ESR);
+        }
 
         /*
          * Starting actual IPI sequence...
@@ -966,7 +976,8 @@ do_rest:
                         else
                                 /* trampoline code not run */
                                 printk(KERN_ERR "Not responding.\n");
-                        inquire_remote_apic(apicid);
+                        if (get_uv_system_type() != UV_NON_UNIQUE_APIC)
+                                inquire_remote_apic(apicid);
                 }
         }
 
diff --git a/arch/x86/kernel/traps_32.c b/arch/x86/kernel/traps_32.c
index 65791ca2824a..471e694d6713 100644
--- a/arch/x86/kernel/traps_32.c
+++ b/arch/x86/kernel/traps_32.c
@@ -681,7 +681,7 @@ gp_in_kernel:
         }
 }
 
-static __kprobes void
+static notrace __kprobes void
 mem_parity_error(unsigned char reason, struct pt_regs *regs)
 {
         printk(KERN_EMERG
@@ -707,7 +707,7 @@ mem_parity_error(unsigned char reason, struct pt_regs *regs)
         clear_mem_error(reason);
 }
 
-static __kprobes void
+static notrace __kprobes void
 io_check_error(unsigned char reason, struct pt_regs *regs)
 {
         unsigned long i;
@@ -727,7 +727,7 @@ io_check_error(unsigned char reason, struct pt_regs *regs)
         outb(reason, 0x61);
 }
 
-static __kprobes void
+static notrace __kprobes void
 unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
 {
         if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
@@ -755,7 +755,7 @@ unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
 
 static DEFINE_SPINLOCK(nmi_print_lock);
 
-void __kprobes die_nmi(struct pt_regs *regs, const char *msg)
+void notrace __kprobes die_nmi(struct pt_regs *regs, const char *msg)
 {
         if (notify_die(DIE_NMIWATCHDOG, msg, regs, 0, 2, SIGINT) == NOTIFY_STOP)
                 return;
@@ -786,7 +786,7 @@ void __kprobes die_nmi(struct pt_regs *regs, const char *msg)
         do_exit(SIGSEGV);
 }
 
-static __kprobes void default_do_nmi(struct pt_regs *regs)
+static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
 {
         unsigned char reason = 0;
 
@@ -828,7 +828,7 @@ static __kprobes void default_do_nmi(struct pt_regs *regs)
 
 static int ignore_nmis;
 
-__kprobes void do_nmi(struct pt_regs *regs, long error_code)
+notrace __kprobes void do_nmi(struct pt_regs *regs, long error_code)
 {
         int cpu;
 
@@ -1148,9 +1148,22 @@ asmlinkage void math_state_restore(void)
         struct thread_info *thread = current_thread_info();
         struct task_struct *tsk = thread->task;
 
+        if (!tsk_used_math(tsk)) {
+                local_irq_enable();
+                /*
+                 * does a slab alloc which can sleep
+                 */
+                if (init_fpu(tsk)) {
+                        /*
+                         * ran out of memory!
+                         */
+                        do_group_exit(SIGKILL);
+                        return;
+                }
+                local_irq_disable();
+        }
+
         clts();                         /* Allow maths ops (or we recurse) */
-        if (!tsk_used_math(tsk))
-                init_fpu(tsk);
         restore_fpu(tsk);
         thread->status |= TS_USEDFPU;   /* So we fnsave on switch_to() */
         tsk->fpu_counter++;
@@ -1208,11 +1221,6 @@ void __init trap_init(void)
 #endif
         set_trap_gate(19, &simd_coprocessor_error);
 
-        /*
-         * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned.
-         * Generate a build-time error if the alignment is wrong.
-         */
-        BUILD_BUG_ON(offsetof(struct task_struct, thread.i387.fxsave) & 15);
         if (cpu_has_fxsr) {
                 printk(KERN_INFO "Enabling fast FPU save and restore... ");
                 set_in_cr4(X86_CR4_OSFXSR);
@@ -1233,6 +1241,7 @@ void __init trap_init(void)
 
         set_bit(SYSCALL_VECTOR, used_vectors);
 
+        init_thread_xstate();
         /*
          * Should be a barrier for any external CPU state:
          */
diff --git a/arch/x86/kernel/traps_64.c b/arch/x86/kernel/traps_64.c
index 79aa6fc0815c..adff76ea97c4 100644
--- a/arch/x86/kernel/traps_64.c
+++ b/arch/x86/kernel/traps_64.c
@@ -600,7 +600,8 @@ void die(const char * str, struct pt_regs * regs, long err)
         oops_end(flags, regs, SIGSEGV);
 }
 
-void __kprobes die_nmi(char *str, struct pt_regs *regs, int do_panic)
+notrace __kprobes void
+die_nmi(char *str, struct pt_regs *regs, int do_panic)
 {
         unsigned long flags;
 
@@ -772,7 +773,7 @@ asmlinkage void __kprobes do_general_protection(struct pt_regs * regs,
         die("general protection fault", regs, error_code);
 }
 
-static __kprobes void
+static notrace __kprobes void
 mem_parity_error(unsigned char reason, struct pt_regs * regs)
 {
         printk(KERN_EMERG "Uhhuh. NMI received for unknown reason %02x.\n",
@@ -796,7 +797,7 @@ mem_parity_error(unsigned char reason, struct pt_regs * regs)
         outb(reason, 0x61);
 }
 
-static __kprobes void
+static notrace __kprobes void
 io_check_error(unsigned char reason, struct pt_regs * regs)
 {
         printk("NMI: IOCK error (debug interrupt?)\n");
@@ -810,7 +811,7 @@ io_check_error(unsigned char reason, struct pt_regs * regs)
         outb(reason, 0x61);
 }
 
-static __kprobes void
+static notrace __kprobes void
 unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
 {
         if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
@@ -827,7 +828,7 @@ unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
 
 /* Runs on IST stack. This code must keep interrupts off all the time.
    Nested NMIs are prevented by the CPU. */
-asmlinkage __kprobes void default_do_nmi(struct pt_regs *regs)
+asmlinkage notrace  __kprobes void default_do_nmi(struct pt_regs *regs)
 {
         unsigned char reason = 0;
         int cpu;
@@ -1123,11 +1124,24 @@ asmlinkage void __attribute__((weak)) mce_threshold_interrupt(void)
 asmlinkage void math_state_restore(void)
 {
         struct task_struct *me = current;
-        clts();                 /* Allow maths ops (or we recurse) */
 
-        if (!used_math())
-                init_fpu(me);
-        restore_fpu_checking(&me->thread.i387.fxsave);
+        if (!used_math()) {
+                local_irq_enable();
+                /*
+                 * does a slab alloc which can sleep
+                 */
+                if (init_fpu(me)) {
+                        /*
+                         * ran out of memory!
+                         */
+                        do_group_exit(SIGKILL);
+                        return;
+                }
+                local_irq_disable();
+        }
+
+        clts();                 /* Allow maths ops (or we recurse) */
+        restore_fpu_checking(&me->thread.xstate->fxsave);
         task_thread_info(me)->status |= TS_USEDFPU;
         me->fpu_counter++;
 }
@@ -1163,6 +1177,10 @@ void __init trap_init(void)
 #endif
        
         /*
+         * initialize the per thread extended state:
+         */
+        init_thread_xstate();
+        /*
          * Should be a barrier for any external CPU state.
          */
         cpu_init();
diff --git a/arch/x86/kernel/tsc_32.c b/arch/x86/kernel/tsc_32.c
index 3d7e6e9fa6c2..e4790728b224 100644
--- a/arch/x86/kernel/tsc_32.c
+++ b/arch/x86/kernel/tsc_32.c
@@ -221,9 +221,9 @@ EXPORT_SYMBOL(recalibrate_cpu_khz);
  * if the CPU frequency is scaled, TSC-based delays will need a different
  * loops_per_jiffy value to function properly.
  */
-static unsigned int ref_freq = 0;
-static unsigned long loops_per_jiffy_ref = 0;
-static unsigned long cpu_khz_ref = 0;
+static unsigned int ref_freq;
+static unsigned long loops_per_jiffy_ref;
+static unsigned long cpu_khz_ref;
 
 static int
 time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
@@ -283,15 +283,28 @@ core_initcall(cpufreq_tsc);
 
 /* clock source code */
 
-static unsigned long current_tsc_khz = 0;
+static unsigned long current_tsc_khz;
+static struct clocksource clocksource_tsc;
 
+/*
+ * We compare the TSC to the cycle_last value in the clocksource
+ * structure to avoid a nasty time-warp issue. This can be observed in
+ * a very small window right after one CPU updated cycle_last under
+ * xtime lock and the other CPU reads a TSC value which is smaller
+ * than the cycle_last reference value due to a TSC which is slighty
+ * behind. This delta is nowhere else observable, but in that case it
+ * results in a forward time jump in the range of hours due to the
+ * unsigned delta calculation of the time keeping core code, which is
+ * necessary to support wrapping clocksources like pm timer.
+ */
 static cycle_t read_tsc(void)
 {
         cycle_t ret;
 
         rdtscll(ret);
 
-        return ret;
+        return ret >= clocksource_tsc.cycle_last ?
+                ret : clocksource_tsc.cycle_last;
 }
 
 static struct clocksource clocksource_tsc = {
diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c
index ceeba01e7f47..fcc16e58609e 100644
--- a/arch/x86/kernel/tsc_64.c
+++ b/arch/x86/kernel/tsc_64.c
@@ -11,6 +11,7 @@
 #include <asm/hpet.h>
 #include <asm/timex.h>
 #include <asm/timer.h>
+#include <asm/vgtod.h>
 
 static int notsc __initdata = 0;
 
@@ -287,18 +288,34 @@ int __init notsc_setup(char *s)
 
 __setup("notsc", notsc_setup);
 
+static struct clocksource clocksource_tsc;
 
-/* clock source code: */
+/*
+ * We compare the TSC to the cycle_last value in the clocksource
+ * structure to avoid a nasty time-warp. This can be observed in a
+ * very small window right after one CPU updated cycle_last under
+ * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
+ * is smaller than the cycle_last reference value due to a TSC which
+ * is slighty behind. This delta is nowhere else observable, but in
+ * that case it results in a forward time jump in the range of hours
+ * due to the unsigned delta calculation of the time keeping core
+ * code, which is necessary to support wrapping clocksources like pm
+ * timer.
+ */
 static cycle_t read_tsc(void)
 {
         cycle_t ret = (cycle_t)get_cycles();
-        return ret;
+
+        return ret >= clocksource_tsc.cycle_last ?
+                ret : clocksource_tsc.cycle_last;
 }
 
 static cycle_t __vsyscall_fn vread_tsc(void)
 {
         cycle_t ret = (cycle_t)vget_cycles();
-        return ret;
+
+        return ret >= __vsyscall_gtod_data.clock.cycle_last ?
+                ret : __vsyscall_gtod_data.clock.cycle_last;
 }
 
 static struct clocksource clocksource_tsc = {
diff --git a/arch/x86/mach-visws/visws_apic.c b/arch/x86/mach-visws/visws_apic.c
index 710faf71a650..cef9cb1d15ac 100644
--- a/arch/x86/mach-visws/visws_apic.c
+++ b/arch/x86/mach-visws/visws_apic.c
@@ -1,6 +1,4 @@
 /*
- *      linux/arch/i386/mach-visws/visws_apic.c
- *
  *      Copyright (C) 1999 Bent Hagemark, Ingo Molnar
  *
  *  SGI Visual Workstation interrupt controller
diff --git a/arch/x86/mach-voyager/voyager_basic.c b/arch/x86/mach-voyager/voyager_basic.c
index 6a949e4edde8..46d6f8067690 100644
--- a/arch/x86/mach-voyager/voyager_basic.c
+++ b/arch/x86/mach-voyager/voyager_basic.c
@@ -2,8 +2,6 @@
  *
  * Author: J.E.J.Bottomley@HansenPartnership.com
  *
- * linux/arch/i386/kernel/voyager.c
- *
  * This file contains all the voyager specific routines for getting
  * initialisation of the architecture to function.  For additional
  * features see:
diff --git a/arch/x86/mach-voyager/voyager_cat.c b/arch/x86/mach-voyager/voyager_cat.c
index 17a7904f75b1..ecab9fff0fd1 100644
--- a/arch/x86/mach-voyager/voyager_cat.c
+++ b/arch/x86/mach-voyager/voyager_cat.c
@@ -4,8 +4,6 @@
  *
  * Author: J.E.J.Bottomley@HansenPartnership.com
  *
- * linux/arch/i386/kernel/voyager_cat.c
- *
  * This file contains all the logic for manipulating the CAT bus
  * in a level 5 machine.
  *
diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c
index be7235bf105d..96f60c7cd124 100644
--- a/arch/x86/mach-voyager/voyager_smp.c
+++ b/arch/x86/mach-voyager/voyager_smp.c
@@ -4,8 +4,6 @@
  *
  * Author: J.E.J.Bottomley@HansenPartnership.com
  *
- * linux/arch/i386/kernel/voyager_smp.c
- *
  * This file provides all the same external entries as smp.c but uses
  * the voyager hal to provide the functionality
  */
diff --git a/arch/x86/mach-voyager/voyager_thread.c b/arch/x86/mach-voyager/voyager_thread.c
index c69c931818ed..15464a20fb38 100644
--- a/arch/x86/mach-voyager/voyager_thread.c
+++ b/arch/x86/mach-voyager/voyager_thread.c
@@ -4,8 +4,6 @@
  *
  * Author: J.E.J.Bottomley@HansenPartnership.com
  *
- * linux/arch/i386/kernel/voyager_thread.c
- *
  * This module provides the machine status monitor thread for the
  * voyager architecture.  This allows us to monitor the machine
  * environment (temp, voltage, fan function) and the front panel and
diff --git a/arch/x86/math-emu/fpu_entry.c b/arch/x86/math-emu/fpu_entry.c
index 4bab3b145392..6e38d877ea77 100644
--- a/arch/x86/math-emu/fpu_entry.c
+++ b/arch/x86/math-emu/fpu_entry.c
@@ -678,7 +678,7 @@ int fpregs_soft_set(struct task_struct *target,
                     unsigned int pos, unsigned int count,
                     const void *kbuf, const void __user *ubuf)
 {
-        struct i387_soft_struct *s387 = &target->thread.i387.soft;
+        struct i387_soft_struct *s387 = &target->thread.xstate->soft;
         void *space = s387->st_space;
         int ret;
         int offset, other, i, tags, regnr, tag, newtop;
@@ -730,7 +730,7 @@ int fpregs_soft_get(struct task_struct *target,
                     unsigned int pos, unsigned int count,
                     void *kbuf, void __user *ubuf)
 {
-        struct i387_soft_struct *s387 = &target->thread.i387.soft;
+        struct i387_soft_struct *s387 = &target->thread.xstate->soft;
         const void *space = s387->st_space;
         int ret;
         int offset = (S387->ftop & 7) * 10, other = 80 - offset;
diff --git a/arch/x86/math-emu/fpu_system.h b/arch/x86/math-emu/fpu_system.h
index a3ae28c49ddd..13488fa153e0 100644
--- a/arch/x86/math-emu/fpu_system.h
+++ b/arch/x86/math-emu/fpu_system.h
@@ -35,8 +35,8 @@
 #define SEG_EXPAND_DOWN(s)      (((s).b & ((1 << 11) | (1 << 10))) \
                                  == (1 << 10))
 
-#define I387                    (current->thread.i387)
-#define FPU_info                (I387.soft.info)
+#define I387                    (current->thread.xstate)
+#define FPU_info                (I387->soft.info)
 
 #define FPU_CS                  (*(unsigned short *) &(FPU_info->___cs))
 #define FPU_SS                  (*(unsigned short *) &(FPU_info->___ss))
@@ -46,25 +46,25 @@
 #define FPU_EIP                 (FPU_info->___eip)
 #define FPU_ORIG_EIP            (FPU_info->___orig_eip)
 
-#define FPU_lookahead           (I387.soft.lookahead)
+#define FPU_lookahead           (I387->soft.lookahead)
 
 /* nz if ip_offset and cs_selector are not to be set for the current
    instruction. */
-#define no_ip_update            (*(u_char *)&(I387.soft.no_update))
-#define FPU_rm                  (*(u_char *)&(I387.soft.rm))
+#define no_ip_update            (*(u_char *)&(I387->soft.no_update))
+#define FPU_rm                  (*(u_char *)&(I387->soft.rm))
 
 /* Number of bytes of data which can be legally accessed by the current
    instruction. This only needs to hold a number <= 108, so a byte will do. */
-#define access_limit            (*(u_char *)&(I387.soft.alimit))
+#define access_limit            (*(u_char *)&(I387->soft.alimit))
 
-#define partial_status          (I387.soft.swd)
-#define control_word            (I387.soft.cwd)
-#define fpu_tag_word            (I387.soft.twd)
-#define registers               (I387.soft.st_space)
-#define top                     (I387.soft.ftop)
+#define partial_status          (I387->soft.swd)
+#define control_word            (I387->soft.cwd)
+#define fpu_tag_word            (I387->soft.twd)
+#define registers               (I387->soft.st_space)
+#define top                     (I387->soft.ftop)
 
-#define instruction_address     (*(struct address *)&I387.soft.fip)
-#define operand_address         (*(struct address *)&I387.soft.foo)
+#define instruction_address     (*(struct address *)&I387->soft.fip)
+#define operand_address         (*(struct address *)&I387->soft.foo)
 
 #define FPU_access_ok(x,y,z)    if ( !access_ok(x,y,z) ) \
                                 math_abort(FPU_info,SIGSEGV)
diff --git a/arch/x86/math-emu/reg_ld_str.c b/arch/x86/math-emu/reg_ld_str.c
index 02af772a24db..d597fe7423c9 100644
--- a/arch/x86/math-emu/reg_ld_str.c
+++ b/arch/x86/math-emu/reg_ld_str.c
@@ -1180,8 +1180,8 @@ u_char __user *fstenv(fpu_addr_modes addr_modes, u_char __user *d)
                 control_word |= 0xffff0040;
                 partial_status = status_word() | 0xffff0000;
                 fpu_tag_word |= 0xffff0000;
-                I387.soft.fcs &= ~0xf8000000;
-                I387.soft.fos |= 0xffff0000;
+                I387->soft.fcs &= ~0xf8000000;
+                I387->soft.fos |= 0xffff0000;
 #endif /* PECULIAR_486 */
                 if (__copy_to_user(d, &control_word, 7 * 4))
                         FPU_abort;
diff --git a/arch/x86/mm/discontig_32.c b/arch/x86/mm/discontig_32.c
index eba0bbede7a6..18378850e25a 100644
--- a/arch/x86/mm/discontig_32.c
+++ b/arch/x86/mm/discontig_32.c
@@ -120,7 +120,7 @@ int __init get_memcfg_numa_flat(void)
         printk("NUMA - single node, flat memory mode\n");
 
         /* Run the memory configuration and find the top of memory. */
-        find_max_pfn();
+        propagate_e820_map();
         node_start_pfn[0] = 0;
         node_end_pfn[0] = max_pfn;
         memory_present(0, 0, max_pfn);
@@ -134,7 +134,7 @@ int __init get_memcfg_numa_flat(void)
 /*
  * Find the highest page frame number we have available for the node
  */
-static void __init find_max_pfn_node(int nid)
+static void __init propagate_e820_map_node(int nid)
 {
         if (node_end_pfn[nid] > max_pfn)
                 node_end_pfn[nid] = max_pfn;
@@ -379,7 +379,7 @@ unsigned long __init setup_memory(void)
         printk("High memory starts at vaddr %08lx\n",
                         (ulong) pfn_to_kaddr(highstart_pfn));
         for_each_online_node(nid)
-                find_max_pfn_node(nid);
+                propagate_e820_map_node(nid);
 
         memset(NODE_DATA(0), 0, sizeof(struct pglist_data));
         NODE_DATA(0)->bdata = &node0_bdata;
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 1500dc8d63e4..9ec62da85fd7 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -1,5 +1,4 @@
 /*
- *  linux/arch/i386/mm/init.c
  *
  *  Copyright (C) 1995  Linus Torvalds
  *
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 1076097dcab2..1ff7906a9a4d 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -47,9 +47,6 @@
 #include <asm/numa.h>
 #include <asm/cacheflush.h>
 
-const struct dma_mapping_ops *dma_ops;
-EXPORT_SYMBOL(dma_ops);
-
 static unsigned long dma_reserve __initdata;
 
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index c590fd200e29..3a4baf95e24d 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -134,7 +134,7 @@ static void __iomem *__ioremap(resource_size_t phys_addr, unsigned long size,
 
         if (!phys_addr_valid(phys_addr)) {
                 printk(KERN_WARNING "ioremap: invalid physical address %llx\n",
-                       phys_addr);
+                       (unsigned long long)phys_addr);
                 WARN_ON_ONCE(1);
                 return NULL;
         }
@@ -187,7 +187,8 @@ static void __iomem *__ioremap(resource_size_t phys_addr, unsigned long size,
                      new_prot_val == _PAGE_CACHE_WB)) {
                         pr_debug(
                 "ioremap error for 0x%llx-0x%llx, requested 0x%lx, got 0x%lx\n",
-                                phys_addr, phys_addr + size,
+                                (unsigned long long)phys_addr,
+                                (unsigned long long)(phys_addr + size),
                                 prot_val, new_prot_val);
                         free_memtype(phys_addr, phys_addr + size);
                         return NULL;
diff --git a/arch/x86/mm/k8topology_64.c b/arch/x86/mm/k8topology_64.c
index 7a2ebce87df5..86808e666f9c 100644
--- a/arch/x86/mm/k8topology_64.c
+++ b/arch/x86/mm/k8topology_64.c
@@ -164,7 +164,7 @@ int __init k8_scan_nodes(unsigned long start, unsigned long end)
         if (!found)
                 return -1;
 
-        memnode_shift = compute_hash_shift(nodes, 8);
+        memnode_shift = compute_hash_shift(nodes, 8, NULL);
         if (memnode_shift < 0) {
                 printk(KERN_ERR "No NUMA node hash function found. Contact maintainer\n");
                 return -1;
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index 2ea56f48f29b..9a6892200b27 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -60,7 +60,7 @@ unsigned long __initdata nodemap_size;
  * -1 if node overlap or lost ram (shift too big)
  */
 static int __init populate_memnodemap(const struct bootnode *nodes,
-                                      int numnodes, int shift)
+                                      int numnodes, int shift, int *nodeids)
 {
         unsigned long addr, end;
         int i, res = -1;
@@ -76,7 +76,12 @@ static int __init populate_memnodemap(const struct bootnode *nodes,
                 do {
                         if (memnodemap[addr >> shift] != NUMA_NO_NODE)
                                 return -1;
-                        memnodemap[addr >> shift] = i;
+
+                        if (!nodeids)
+                                memnodemap[addr >> shift] = i;
+                        else
+                                memnodemap[addr >> shift] = nodeids[i];
+
                         addr += (1UL << shift);
                 } while (addr < end);
                 res = 1;
@@ -139,7 +144,8 @@ static int __init extract_lsb_from_nodes(const struct bootnode *nodes,
         return i;
 }
 
-int __init compute_hash_shift(struct bootnode *nodes, int numnodes)
+int __init compute_hash_shift(struct bootnode *nodes, int numnodes,
+                              int *nodeids)
 {
         int shift;
 
@@ -149,7 +155,7 @@ int __init compute_hash_shift(struct bootnode *nodes, int numnodes)
         printk(KERN_DEBUG "NUMA: Using %d for the hash shift.\n",
                 shift);
 
-        if (populate_memnodemap(nodes, numnodes, shift) != 1) {
+        if (populate_memnodemap(nodes, numnodes, shift, nodeids) != 1) {
                 printk(KERN_INFO "Your memory is not aligned you need to "
                        "rebuild your kernel with a bigger NODEMAPSIZE "
                        "shift=%d\n", shift);
@@ -380,9 +386,10 @@ static int __init split_nodes_by_size(struct bootnode *nodes, u64 *addr,
  * Sets up the system RAM area from start_pfn to end_pfn according to the
  * numa=fake command-line option.
  */
+static struct bootnode nodes[MAX_NUMNODES] __initdata;
+
 static int __init numa_emulation(unsigned long start_pfn, unsigned long end_pfn)
 {
-        struct bootnode nodes[MAX_NUMNODES];
         u64 size, addr = start_pfn << PAGE_SHIFT;
         u64 max_addr = end_pfn << PAGE_SHIFT;
         int num_nodes = 0, num = 0, coeff_flag, coeff = -1, i;
@@ -462,7 +469,7 @@ done:
                 }
         }
 out:
-        memnode_shift = compute_hash_shift(nodes, num_nodes);
+        memnode_shift = compute_hash_shift(nodes, num_nodes, NULL);
         if (memnode_shift < 0) {
                 memnode_shift = 0;
                 printk(KERN_ERR "No NUMA hash function found.  NUMA emulation "
diff --git a/arch/x86/mm/pgtable_32.c b/arch/x86/mm/pgtable_32.c
index 3165ec0672bd..6fb9e7c6893f 100644
--- a/arch/x86/mm/pgtable_32.c
+++ b/arch/x86/mm/pgtable_32.c
@@ -1,7 +1,3 @@
-/*
- *  linux/arch/i386/mm/pgtable.c
- */
-
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index 1bae9c855ceb..fb43d89f46f3 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -32,6 +32,10 @@ static struct bootnode nodes_add[MAX_NUMNODES];
 static int found_add_area __initdata;
 int hotadd_percent __initdata = 0;
 
+static int num_node_memblks __initdata;
+static struct bootnode node_memblk_range[NR_NODE_MEMBLKS] __initdata;
+static int memblk_nodeid[NR_NODE_MEMBLKS] __initdata;
+
 /* Too small nodes confuse the VM badly. Usually they result
    from BIOS bugs. */
 #define NODE_MIN_SIZE (4*1024*1024)
@@ -41,17 +45,17 @@ static __init int setup_node(int pxm)
         return acpi_map_pxm_to_node(pxm);
 }
 
-static __init int conflicting_nodes(unsigned long start, unsigned long end)
+static __init int conflicting_memblks(unsigned long start, unsigned long end)
 {
         int i;
-        for_each_node_mask(i, nodes_parsed) {
-                struct bootnode *nd = &nodes[i];
+        for (i = 0; i < num_node_memblks; i++) {
+                struct bootnode *nd = &node_memblk_range[i];
                 if (nd->start == nd->end)
                         continue;
                 if (nd->end > start && nd->start < end)
-                        return i;
+                        return memblk_nodeid[i];
                 if (nd->end == end && nd->start == start)
-                        return i;
+                        return memblk_nodeid[i];
         }
         return -1;
 }
@@ -258,7 +262,7 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
                 bad_srat();
                 return;
         }
-        i = conflicting_nodes(start, end);
+        i = conflicting_memblks(start, end);
         if (i == node) {
                 printk(KERN_WARNING
                 "SRAT: Warning: PXM %d (%lx-%lx) overlaps with itself (%Lx-%Lx)\n",
@@ -283,10 +287,10 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
                         nd->end = end;
         }
 
-        printk(KERN_INFO "SRAT: Node %u PXM %u %Lx-%Lx\n", node, pxm,
-               nd->start, nd->end);
-        e820_register_active_regions(node, nd->start >> PAGE_SHIFT,
-                                                nd->end >> PAGE_SHIFT);
+        printk(KERN_INFO "SRAT: Node %u PXM %u %lx-%lx\n", node, pxm,
+               start, end);
+        e820_register_active_regions(node, start >> PAGE_SHIFT,
+                                     end >> PAGE_SHIFT);
         push_node_boundaries(node, nd->start >> PAGE_SHIFT,
                                                 nd->end >> PAGE_SHIFT);
 
@@ -298,6 +302,11 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
                 if ((nd->start | nd->end) == 0)
                         node_clear(node, nodes_parsed);
         }
+
+        node_memblk_range[num_node_memblks].start = start;
+        node_memblk_range[num_node_memblks].end = end;
+        memblk_nodeid[num_node_memblks] = node;
+        num_node_memblks++;
 }
 
 /* Sanity check to catch more bad SRATs (they are amazingly common).
@@ -368,7 +377,8 @@ int __init acpi_scan_nodes(unsigned long start, unsigned long end)
                 return -1;
         }
 
-        memnode_shift = compute_hash_shift(nodes, MAX_NUMNODES);
+        memnode_shift = compute_hash_shift(node_memblk_range, num_node_memblks,
+                                           memblk_nodeid);
         if (memnode_shift < 0) {
                 printk(KERN_ERR
                      "SRAT: No NUMA node hash function found. Contact maintainer\n");
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 1f11cf0a307f..cc48d3fde545 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -23,8 +23,8 @@
 #include "op_x86_model.h"
 
 static struct op_x86_model_spec const *model;
-static struct op_msrs cpu_msrs[NR_CPUS];
-static unsigned long saved_lvtpc[NR_CPUS];
+static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
+static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
 
 static int nmi_start(void);
 static void nmi_stop(void);
@@ -89,7 +89,7 @@ static int profile_exceptions_notify(struct notifier_block *self,
 
         switch (val) {
         case DIE_NMI:
-                if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
+                if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
                         ret = NOTIFY_STOP;
                 break;
         default:
@@ -126,7 +126,7 @@ static void nmi_cpu_save_registers(struct op_msrs *msrs)
 static void nmi_save_registers(void *dummy)
 {
         int cpu = smp_processor_id();
-        struct op_msrs *msrs = &cpu_msrs[cpu];
+        struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
         nmi_cpu_save_registers(msrs);
 }
 
@@ -134,10 +134,10 @@ static void free_msrs(void)
 {
         int i;
         for_each_possible_cpu(i) {
-                kfree(cpu_msrs[i].counters);
-                cpu_msrs[i].counters = NULL;
-                kfree(cpu_msrs[i].controls);
-                cpu_msrs[i].controls = NULL;
+                kfree(per_cpu(cpu_msrs, i).counters);
+                per_cpu(cpu_msrs, i).counters = NULL;
+                kfree(per_cpu(cpu_msrs, i).controls);
+                per_cpu(cpu_msrs, i).controls = NULL;
         }
 }
 
@@ -149,13 +149,15 @@ static int allocate_msrs(void)
 
         int i;
         for_each_possible_cpu(i) {
-                cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
-                if (!cpu_msrs[i].counters) {
+                per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
+                                                                GFP_KERNEL);
+                if (!per_cpu(cpu_msrs, i).counters) {
                         success = 0;
                         break;
                 }
-                cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
-                if (!cpu_msrs[i].controls) {
+                per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
+                                                                GFP_KERNEL);
+                if (!per_cpu(cpu_msrs, i).controls) {
                         success = 0;
                         break;
                 }
@@ -170,11 +172,11 @@ static int allocate_msrs(void)
 static void nmi_cpu_setup(void *dummy)
 {
         int cpu = smp_processor_id();
-        struct op_msrs *msrs = &cpu_msrs[cpu];
+        struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
         spin_lock(&oprofilefs_lock);
         model->setup_ctrs(msrs);
         spin_unlock(&oprofilefs_lock);
-        saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
+        per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
         apic_write(APIC_LVTPC, APIC_DM_NMI);
 }
 
@@ -203,13 +205,15 @@ static int nmi_setup(void)
          */
 
         /* Assume saved/restored counters are the same on all CPUs */
-        model->fill_in_addresses(&cpu_msrs[0]);
+        model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
         for_each_possible_cpu(cpu) {
                 if (cpu != 0) {
-                        memcpy(cpu_msrs[cpu].counters, cpu_msrs[0].counters,
+                        memcpy(per_cpu(cpu_msrs, cpu).counters,
+                                per_cpu(cpu_msrs, 0).counters,
                                 sizeof(struct op_msr) * model->num_counters);
 
-                        memcpy(cpu_msrs[cpu].controls, cpu_msrs[0].controls,
+                        memcpy(per_cpu(cpu_msrs, cpu).controls,
+                                per_cpu(cpu_msrs, 0).controls,
                                 sizeof(struct op_msr) * model->num_controls);
                 }
 
@@ -249,7 +253,7 @@ static void nmi_cpu_shutdown(void *dummy)
 {
         unsigned int v;
         int cpu = smp_processor_id();
-        struct op_msrs *msrs = &cpu_msrs[cpu];
+        struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
 
         /* restoring APIC_LVTPC can trigger an apic error because the delivery
          * mode and vector nr combination can be illegal. That's by design: on
@@ -258,23 +262,24 @@ static void nmi_cpu_shutdown(void *dummy)
          */
         v = apic_read(APIC_LVTERR);
         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
-        apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
+        apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
         apic_write(APIC_LVTERR, v);
         nmi_restore_registers(msrs);
 }
 
 static void nmi_shutdown(void)
 {
+        struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
         nmi_enabled = 0;
         on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
         unregister_die_notifier(&profile_exceptions_nb);
-        model->shutdown(cpu_msrs);
+        model->shutdown(msrs);
         free_msrs();
 }
 
 static void nmi_cpu_start(void *dummy)
 {
-        struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
+        struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
         model->start(msrs);
 }
 
@@ -286,7 +291,7 @@ static int nmi_start(void)
 
 static void nmi_cpu_stop(void *dummy)
 {
-        struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
+        struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
         model->stop(msrs);
 }
 
diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile
index 17a6b057856b..b7ad9f89d21f 100644
--- a/arch/x86/vdso/Makefile
+++ b/arch/x86/vdso/Makefile
@@ -37,7 +37,8 @@ $(obj)/%.so: OBJCOPYFLAGS := -S
 $(obj)/%.so: $(obj)/%.so.dbg FORCE
         $(call if_changed,objcopy)
 
-CFL := $(PROFILING) -mcmodel=small -fPIC -g0 -O2 -fasynchronous-unwind-tables -m64
+CFL := $(PROFILING) -mcmodel=small -fPIC -O2 -fasynchronous-unwind-tables -m64 \
+       $(filter -g%,$(KBUILD_CFLAGS))
 
 $(vobjs): KBUILD_CFLAGS += $(CFL)
 
diff --git a/arch/x86/video/fbdev.c b/arch/x86/video/fbdev.c
index 48fb38d7d2c0..4db42bff8c60 100644
--- a/arch/x86/video/fbdev.c
+++ b/arch/x86/video/fbdev.c
@@ -1,5 +1,4 @@
 /*
- * arch/i386/video/fbdev.c - i386 Framebuffer
  *
  * Copyright (C) 2007 Antonino Daplas <adaplas@gmail.com>
  *