diff options
Diffstat (limited to 'arch')
37 files changed, 1656 insertions, 586 deletions
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 5b7c26395b44..028bdc9228fb 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c | |||
@@ -179,17 +179,19 @@ alloc_safe_buffer(struct dmabounce_device_info *device_info, void *ptr, | |||
179 | static inline struct safe_buffer * | 179 | static inline struct safe_buffer * |
180 | find_safe_buffer(struct dmabounce_device_info *device_info, dma_addr_t safe_dma_addr) | 180 | find_safe_buffer(struct dmabounce_device_info *device_info, dma_addr_t safe_dma_addr) |
181 | { | 181 | { |
182 | struct safe_buffer *b = NULL; | 182 | struct safe_buffer *b, *rb = NULL; |
183 | unsigned long flags; | 183 | unsigned long flags; |
184 | 184 | ||
185 | read_lock_irqsave(&device_info->lock, flags); | 185 | read_lock_irqsave(&device_info->lock, flags); |
186 | 186 | ||
187 | list_for_each_entry(b, &device_info->safe_buffers, node) | 187 | list_for_each_entry(b, &device_info->safe_buffers, node) |
188 | if (b->safe_dma_addr == safe_dma_addr) | 188 | if (b->safe_dma_addr == safe_dma_addr) { |
189 | rb = b; | ||
189 | break; | 190 | break; |
191 | } | ||
190 | 192 | ||
191 | read_unlock_irqrestore(&device_info->lock, flags); | 193 | read_unlock_irqrestore(&device_info->lock, flags); |
192 | return b; | 194 | return rb; |
193 | } | 195 | } |
194 | 196 | ||
195 | static inline void | 197 | static inline void |
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 7ea5f01dfc7b..de4e33137901 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
@@ -634,6 +634,14 @@ ENTRY(__switch_to) | |||
634 | * purpose. | 634 | * purpose. |
635 | */ | 635 | */ |
636 | 636 | ||
637 | .macro usr_ret, reg | ||
638 | #ifdef CONFIG_ARM_THUMB | ||
639 | bx \reg | ||
640 | #else | ||
641 | mov pc, \reg | ||
642 | #endif | ||
643 | .endm | ||
644 | |||
637 | .align 5 | 645 | .align 5 |
638 | .globl __kuser_helper_start | 646 | .globl __kuser_helper_start |
639 | __kuser_helper_start: | 647 | __kuser_helper_start: |
@@ -675,7 +683,7 @@ __kuser_memory_barrier: @ 0xffff0fa0 | |||
675 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) | 683 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) |
676 | mcr p15, 0, r0, c7, c10, 5 @ dmb | 684 | mcr p15, 0, r0, c7, c10, 5 @ dmb |
677 | #endif | 685 | #endif |
678 | mov pc, lr | 686 | usr_ret lr |
679 | 687 | ||
680 | .align 5 | 688 | .align 5 |
681 | 689 | ||
@@ -778,7 +786,7 @@ __kuser_cmpxchg: @ 0xffff0fc0 | |||
778 | mov r0, #-1 | 786 | mov r0, #-1 |
779 | adds r0, r0, #0 | 787 | adds r0, r0, #0 |
780 | #endif | 788 | #endif |
781 | mov pc, lr | 789 | usr_ret lr |
782 | 790 | ||
783 | #else | 791 | #else |
784 | 792 | ||
@@ -792,7 +800,7 @@ __kuser_cmpxchg: @ 0xffff0fc0 | |||
792 | #ifdef CONFIG_SMP | 800 | #ifdef CONFIG_SMP |
793 | mcr p15, 0, r0, c7, c10, 5 @ dmb | 801 | mcr p15, 0, r0, c7, c10, 5 @ dmb |
794 | #endif | 802 | #endif |
795 | mov pc, lr | 803 | usr_ret lr |
796 | 804 | ||
797 | #endif | 805 | #endif |
798 | 806 | ||
@@ -834,16 +842,11 @@ __kuser_cmpxchg: @ 0xffff0fc0 | |||
834 | __kuser_get_tls: @ 0xffff0fe0 | 842 | __kuser_get_tls: @ 0xffff0fe0 |
835 | 843 | ||
836 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) | 844 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
837 | |||
838 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 | 845 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 |
839 | mov pc, lr | ||
840 | |||
841 | #else | 846 | #else |
842 | |||
843 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register | 847 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register |
844 | mov pc, lr | ||
845 | |||
846 | #endif | 848 | #endif |
849 | usr_ret lr | ||
847 | 850 | ||
848 | .rep 5 | 851 | .rep 5 |
849 | .word 0 @ pad up to __kuser_helper_version | 852 | .word 0 @ pad up to __kuser_helper_version |
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 4fe386eea4b4..5365d4e5949e 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
@@ -118,7 +118,7 @@ ENTRY(secondary_startup) | |||
118 | sub r4, r4, r5 @ mmu has been enabled | 118 | sub r4, r4, r5 @ mmu has been enabled |
119 | ldr r4, [r7, r4] @ get secondary_data.pgdir | 119 | ldr r4, [r7, r4] @ get secondary_data.pgdir |
120 | adr lr, __enable_mmu @ return address | 120 | adr lr, __enable_mmu @ return address |
121 | add pc, r10, #12 @ initialise processor | 121 | add pc, r10, #PROCINFO_INITFUNC @ initialise processor |
122 | @ (return control reg) | 122 | @ (return control reg) |
123 | 123 | ||
124 | /* | 124 | /* |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 0c7938645df6..273e05f2b8de 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
@@ -10,45 +10,47 @@ obj-m := | |||
10 | obj-n := | 10 | obj-n := |
11 | obj- := | 11 | obj- := |
12 | 12 | ||
13 | # DMA | ||
14 | obj-$(CONFIG_S3C2410_DMA) += dma.o | ||
15 | |||
13 | # S3C2400 support files | 16 | # S3C2400 support files |
14 | obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o | 17 | obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o |
15 | 18 | ||
16 | # S3C2410 support files | 19 | # S3C2410 support files |
17 | 20 | ||
18 | obj-$(CONFIG_CPU_S3C2410) += s3c2410.o | 21 | obj-$(CONFIG_CPU_S3C2410) += s3c2410.o |
19 | obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o | 22 | obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o |
20 | obj-$(CONFIG_S3C2410_DMA) += dma.o | ||
21 | 23 | ||
22 | # Power Management support | 24 | # Power Management support |
23 | 25 | ||
24 | obj-$(CONFIG_PM) += pm.o sleep.o | 26 | obj-$(CONFIG_PM) += pm.o sleep.o |
25 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o | 27 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o |
26 | 28 | ||
27 | # S3C2412 support | 29 | # S3C2412 support |
28 | obj-$(CONFIG_CPU_S3C2412) += s3c2412.o | 30 | obj-$(CONFIG_CPU_S3C2412) += s3c2412.o |
29 | obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o | 31 | obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o |
30 | 32 | ||
31 | # | 33 | # |
32 | # S3C244X support | 34 | # S3C244X support |
33 | 35 | ||
34 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o | 36 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o |
35 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o | 37 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o |
36 | 38 | ||
37 | # Clock control | 39 | # Clock control |
38 | 40 | ||
39 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | 41 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o |
40 | 42 | ||
41 | # S3C2440 support | 43 | # S3C2440 support |
42 | 44 | ||
43 | obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o | 45 | obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o |
44 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o | 46 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o |
45 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o | 47 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o |
46 | obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o | 48 | obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o |
47 | 49 | ||
48 | # S3C2442 support | 50 | # S3C2442 support |
49 | 51 | ||
50 | obj-$(CONFIG_CPU_S3C2442) += s3c2442.o | 52 | obj-$(CONFIG_CPU_S3C2442) += s3c2442.o |
51 | obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o | 53 | obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o |
52 | 54 | ||
53 | # bast extras | 55 | # bast extras |
54 | 56 | ||
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 094cc52745c5..25855452fe8c 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c | |||
@@ -112,7 +112,7 @@ dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs) | |||
112 | } | 112 | } |
113 | 113 | ||
114 | static void | 114 | static void |
115 | dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan, | 115 | dmadbg_dumpregs(const char *fname, int line, s3c2410_dma_chan_t *chan, |
116 | struct s3c2410_dma_regstate *regs) | 116 | struct s3c2410_dma_regstate *regs) |
117 | { | 117 | { |
118 | printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", | 118 | printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", |
@@ -132,7 +132,16 @@ dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan) | |||
132 | chan->number, fname, line, chan->load_state, | 132 | chan->number, fname, line, chan->load_state, |
133 | chan->curr, chan->next, chan->end); | 133 | chan->curr, chan->next, chan->end); |
134 | 134 | ||
135 | dmadbg_showregs(fname, line, chan, &state); | 135 | dmadbg_dumpregs(fname, line, chan, &state); |
136 | } | ||
137 | |||
138 | static void | ||
139 | dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan) | ||
140 | { | ||
141 | struct s3c2410_dma_regstate state; | ||
142 | |||
143 | dmadbg_capture(chan, &state); | ||
144 | dmadbg_dumpregs(fname, line, chan, &state); | ||
136 | } | 145 | } |
137 | 146 | ||
138 | #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) | 147 | #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) |
@@ -253,10 +262,14 @@ s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan, | |||
253 | buf->next); | 262 | buf->next); |
254 | reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; | 263 | reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; |
255 | } else { | 264 | } else { |
256 | pr_debug("load_state is %d => autoreload\n", chan->load_state); | 265 | //pr_debug("load_state is %d => autoreload\n", chan->load_state); |
257 | reload = S3C2410_DCON_AUTORELOAD; | 266 | reload = S3C2410_DCON_AUTORELOAD; |
258 | } | 267 | } |
259 | 268 | ||
269 | if ((buf->data & 0xf0000000) != 0x30000000) { | ||
270 | dmawarn("dmaload: buffer is %p\n", (void *)buf->data); | ||
271 | } | ||
272 | |||
260 | writel(buf->data, chan->addr_reg); | 273 | writel(buf->data, chan->addr_reg); |
261 | 274 | ||
262 | dma_wrreg(chan, S3C2410_DMA_DCON, | 275 | dma_wrreg(chan, S3C2410_DMA_DCON, |
@@ -370,7 +383,7 @@ static int s3c2410_dma_start(s3c2410_dma_chan_t *chan) | |||
370 | tmp |= S3C2410_DMASKTRIG_ON; | 383 | tmp |= S3C2410_DMASKTRIG_ON; |
371 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | 384 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); |
372 | 385 | ||
373 | pr_debug("wrote %08lx to DMASKTRIG\n", tmp); | 386 | pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); |
374 | 387 | ||
375 | #if 0 | 388 | #if 0 |
376 | /* the dma buffer loads should take care of clearing the AUTO | 389 | /* the dma buffer loads should take care of clearing the AUTO |
@@ -384,7 +397,30 @@ static int s3c2410_dma_start(s3c2410_dma_chan_t *chan) | |||
384 | 397 | ||
385 | dbg_showchan(chan); | 398 | dbg_showchan(chan); |
386 | 399 | ||
400 | /* if we've only loaded one buffer onto the channel, then chec | ||
401 | * to see if we have another, and if so, try and load it so when | ||
402 | * the first buffer is finished, the new one will be loaded onto | ||
403 | * the channel */ | ||
404 | |||
405 | if (chan->next != NULL) { | ||
406 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | ||
407 | |||
408 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | ||
409 | pr_debug("%s: buff not yet loaded, no more todo\n", | ||
410 | __FUNCTION__); | ||
411 | } else { | ||
412 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | ||
413 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
414 | } | ||
415 | |||
416 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | ||
417 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
418 | } | ||
419 | } | ||
420 | |||
421 | |||
387 | local_irq_restore(flags); | 422 | local_irq_restore(flags); |
423 | |||
388 | return 0; | 424 | return 0; |
389 | } | 425 | } |
390 | 426 | ||
@@ -436,12 +472,11 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id, | |||
436 | buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); | 472 | buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); |
437 | if (buf == NULL) { | 473 | if (buf == NULL) { |
438 | pr_debug("%s: out of memory (%ld alloc)\n", | 474 | pr_debug("%s: out of memory (%ld alloc)\n", |
439 | __FUNCTION__, sizeof(*buf)); | 475 | __FUNCTION__, (long)sizeof(*buf)); |
440 | return -ENOMEM; | 476 | return -ENOMEM; |
441 | } | 477 | } |
442 | 478 | ||
443 | pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); | 479 | //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); |
444 | |||
445 | //dbg_showchan(chan); | 480 | //dbg_showchan(chan); |
446 | 481 | ||
447 | buf->next = NULL; | 482 | buf->next = NULL; |
@@ -537,14 +572,20 @@ s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan) | |||
537 | case S3C2410_DMALOAD_1LOADED: | 572 | case S3C2410_DMALOAD_1LOADED: |
538 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | 573 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { |
539 | /* flag error? */ | 574 | /* flag error? */ |
540 | printk(KERN_ERR "dma%d: timeout waiting for load\n", | 575 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", |
541 | chan->number); | 576 | chan->number, __FUNCTION__); |
542 | return; | 577 | return; |
543 | } | 578 | } |
544 | break; | 579 | break; |
545 | 580 | ||
581 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | ||
582 | /* I belive in this case we do not have anything to do | ||
583 | * until the next buffer comes along, and we turn off the | ||
584 | * reload */ | ||
585 | return; | ||
586 | |||
546 | default: | 587 | default: |
547 | pr_debug("dma%d: lastxfer: unhandled load_state %d with no next", | 588 | pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n", |
548 | chan->number, chan->load_state); | 589 | chan->number, chan->load_state); |
549 | return; | 590 | return; |
550 | 591 | ||
@@ -629,7 +670,14 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) | |||
629 | } else { | 670 | } else { |
630 | } | 671 | } |
631 | 672 | ||
632 | if (chan->next != NULL) { | 673 | /* only reload if the channel is still running... our buffer done |
674 | * routine may have altered the state by requesting the dma channel | ||
675 | * to stop or shutdown... */ | ||
676 | |||
677 | /* todo: check that when the channel is shut-down from inside this | ||
678 | * function, we cope with unsetting reload, etc */ | ||
679 | |||
680 | if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { | ||
633 | unsigned long flags; | 681 | unsigned long flags; |
634 | 682 | ||
635 | switch (chan->load_state) { | 683 | switch (chan->load_state) { |
@@ -644,8 +692,8 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) | |||
644 | case S3C2410_DMALOAD_1LOADED: | 692 | case S3C2410_DMALOAD_1LOADED: |
645 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | 693 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { |
646 | /* flag error? */ | 694 | /* flag error? */ |
647 | printk(KERN_ERR "dma%d: timeout waiting for load\n", | 695 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", |
648 | chan->number); | 696 | chan->number, __FUNCTION__); |
649 | return IRQ_HANDLED; | 697 | return IRQ_HANDLED; |
650 | } | 698 | } |
651 | 699 | ||
@@ -678,8 +726,6 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) | |||
678 | return IRQ_HANDLED; | 726 | return IRQ_HANDLED; |
679 | } | 727 | } |
680 | 728 | ||
681 | |||
682 | |||
683 | /* s3c2410_request_dma | 729 | /* s3c2410_request_dma |
684 | * | 730 | * |
685 | * get control of an dma channel | 731 | * get control of an dma channel |
@@ -718,11 +764,17 @@ int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client, | |||
718 | pr_debug("dma%d: %s : requesting irq %d\n", | 764 | pr_debug("dma%d: %s : requesting irq %d\n", |
719 | channel, __FUNCTION__, chan->irq); | 765 | channel, __FUNCTION__, chan->irq); |
720 | 766 | ||
767 | chan->irq_claimed = 1; | ||
768 | local_irq_restore(flags); | ||
769 | |||
721 | err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, | 770 | err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, |
722 | client->name, (void *)chan); | 771 | client->name, (void *)chan); |
723 | 772 | ||
773 | local_irq_save(flags); | ||
774 | |||
724 | if (err) { | 775 | if (err) { |
725 | chan->in_use = 0; | 776 | chan->in_use = 0; |
777 | chan->irq_claimed = 0; | ||
726 | local_irq_restore(flags); | 778 | local_irq_restore(flags); |
727 | 779 | ||
728 | printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", | 780 | printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", |
@@ -730,7 +782,6 @@ int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client, | |||
730 | return err; | 782 | return err; |
731 | } | 783 | } |
732 | 784 | ||
733 | chan->irq_claimed = 1; | ||
734 | chan->irq_enabled = 1; | 785 | chan->irq_enabled = 1; |
735 | } | 786 | } |
736 | 787 | ||
@@ -810,6 +861,7 @@ static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) | |||
810 | 861 | ||
811 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | 862 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); |
812 | tmp |= S3C2410_DMASKTRIG_STOP; | 863 | tmp |= S3C2410_DMASKTRIG_STOP; |
864 | //tmp &= ~S3C2410_DMASKTRIG_ON; | ||
813 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | 865 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); |
814 | 866 | ||
815 | #if 0 | 867 | #if 0 |
@@ -819,6 +871,7 @@ static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) | |||
819 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | 871 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); |
820 | #endif | 872 | #endif |
821 | 873 | ||
874 | /* should stop do this, or should we wait for flush? */ | ||
822 | chan->state = S3C2410_DMA_IDLE; | 875 | chan->state = S3C2410_DMA_IDLE; |
823 | chan->load_state = S3C2410_DMALOAD_NONE; | 876 | chan->load_state = S3C2410_DMALOAD_NONE; |
824 | 877 | ||
@@ -827,6 +880,22 @@ static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) | |||
827 | return 0; | 880 | return 0; |
828 | } | 881 | } |
829 | 882 | ||
883 | void s3c2410_dma_waitforstop(s3c2410_dma_chan_t *chan) | ||
884 | { | ||
885 | unsigned long tmp; | ||
886 | unsigned int timeout = 0x10000; | ||
887 | |||
888 | while (timeout-- > 0) { | ||
889 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | ||
890 | |||
891 | if (!(tmp & S3C2410_DMASKTRIG_ON)) | ||
892 | return; | ||
893 | } | ||
894 | |||
895 | pr_debug("dma%d: failed to stop?\n", chan->number); | ||
896 | } | ||
897 | |||
898 | |||
830 | /* s3c2410_dma_flush | 899 | /* s3c2410_dma_flush |
831 | * | 900 | * |
832 | * stop the channel, and remove all current and pending transfers | 901 | * stop the channel, and remove all current and pending transfers |
@@ -837,7 +906,9 @@ static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan) | |||
837 | s3c2410_dma_buf_t *buf, *next; | 906 | s3c2410_dma_buf_t *buf, *next; |
838 | unsigned long flags; | 907 | unsigned long flags; |
839 | 908 | ||
840 | pr_debug("%s:\n", __FUNCTION__); | 909 | pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); |
910 | |||
911 | dbg_showchan(chan); | ||
841 | 912 | ||
842 | local_irq_save(flags); | 913 | local_irq_save(flags); |
843 | 914 | ||
@@ -864,11 +935,64 @@ static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan) | |||
864 | } | 935 | } |
865 | } | 936 | } |
866 | 937 | ||
938 | dbg_showregs(chan); | ||
939 | |||
940 | s3c2410_dma_waitforstop(chan); | ||
941 | |||
942 | #if 0 | ||
943 | /* should also clear interrupts, according to WinCE BSP */ | ||
944 | { | ||
945 | unsigned long tmp; | ||
946 | |||
947 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | ||
948 | tmp |= S3C2410_DCON_NORELOAD; | ||
949 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | ||
950 | } | ||
951 | #endif | ||
952 | |||
953 | dbg_showregs(chan); | ||
954 | |||
867 | local_irq_restore(flags); | 955 | local_irq_restore(flags); |
868 | 956 | ||
869 | return 0; | 957 | return 0; |
870 | } | 958 | } |
871 | 959 | ||
960 | int | ||
961 | s3c2410_dma_started(s3c2410_dma_chan_t *chan) | ||
962 | { | ||
963 | unsigned long flags; | ||
964 | |||
965 | local_irq_save(flags); | ||
966 | |||
967 | dbg_showchan(chan); | ||
968 | |||
969 | /* if we've only loaded one buffer onto the channel, then chec | ||
970 | * to see if we have another, and if so, try and load it so when | ||
971 | * the first buffer is finished, the new one will be loaded onto | ||
972 | * the channel */ | ||
973 | |||
974 | if (chan->next != NULL) { | ||
975 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | ||
976 | |||
977 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | ||
978 | pr_debug("%s: buff not yet loaded, no more todo\n", | ||
979 | __FUNCTION__); | ||
980 | } else { | ||
981 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | ||
982 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
983 | } | ||
984 | |||
985 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | ||
986 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
987 | } | ||
988 | } | ||
989 | |||
990 | |||
991 | local_irq_restore(flags); | ||
992 | |||
993 | return 0; | ||
994 | |||
995 | } | ||
872 | 996 | ||
873 | int | 997 | int |
874 | s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) | 998 | s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) |
@@ -885,14 +1009,15 @@ s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) | |||
885 | return s3c2410_dma_dostop(chan); | 1009 | return s3c2410_dma_dostop(chan); |
886 | 1010 | ||
887 | case S3C2410_DMAOP_PAUSE: | 1011 | case S3C2410_DMAOP_PAUSE: |
888 | return -ENOENT; | ||
889 | |||
890 | case S3C2410_DMAOP_RESUME: | 1012 | case S3C2410_DMAOP_RESUME: |
891 | return -ENOENT; | 1013 | return -ENOENT; |
892 | 1014 | ||
893 | case S3C2410_DMAOP_FLUSH: | 1015 | case S3C2410_DMAOP_FLUSH: |
894 | return s3c2410_dma_flush(chan); | 1016 | return s3c2410_dma_flush(chan); |
895 | 1017 | ||
1018 | case S3C2410_DMAOP_STARTED: | ||
1019 | return s3c2410_dma_started(chan); | ||
1020 | |||
896 | case S3C2410_DMAOP_TIMEOUT: | 1021 | case S3C2410_DMAOP_TIMEOUT: |
897 | return 0; | 1022 | return 0; |
898 | 1023 | ||
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index c4e3f8c68479..f2bbef07b1e4 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
@@ -285,7 +285,7 @@ static struct flash_platform_data versatile_flash_data = { | |||
285 | 285 | ||
286 | static struct resource versatile_flash_resource = { | 286 | static struct resource versatile_flash_resource = { |
287 | .start = VERSATILE_FLASH_BASE, | 287 | .start = VERSATILE_FLASH_BASE, |
288 | .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE, | 288 | .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1, |
289 | .flags = IORESOURCE_MEM, | 289 | .flags = IORESOURCE_MEM, |
290 | }; | 290 | }; |
291 | 291 | ||
diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig index f71fb4a029cb..b2751eadbc56 100644 --- a/arch/i386/Kconfig +++ b/arch/i386/Kconfig | |||
@@ -142,6 +142,7 @@ config X86_SUMMIT | |||
142 | In particular, it is needed for the x440. | 142 | In particular, it is needed for the x440. |
143 | 143 | ||
144 | If you don't have one of these computers, you should say N here. | 144 | If you don't have one of these computers, you should say N here. |
145 | If you want to build a NUMA kernel, you must select ACPI. | ||
145 | 146 | ||
146 | config X86_BIGSMP | 147 | config X86_BIGSMP |
147 | bool "Support for other sub-arch SMP systems with more than 8 CPUs" | 148 | bool "Support for other sub-arch SMP systems with more than 8 CPUs" |
@@ -169,6 +170,7 @@ config X86_GENERICARCH | |||
169 | help | 170 | help |
170 | This option compiles in the Summit, bigsmp, ES7000, default subarchitectures. | 171 | This option compiles in the Summit, bigsmp, ES7000, default subarchitectures. |
171 | It is intended for a generic binary kernel. | 172 | It is intended for a generic binary kernel. |
173 | If you want a NUMA kernel, select ACPI. We need SRAT for NUMA. | ||
172 | 174 | ||
173 | config X86_ES7000 | 175 | config X86_ES7000 |
174 | bool "Support for Unisys ES7000 IA32 series" | 176 | bool "Support for Unisys ES7000 IA32 series" |
@@ -542,7 +544,7 @@ config X86_PAE | |||
542 | # Common NUMA Features | 544 | # Common NUMA Features |
543 | config NUMA | 545 | config NUMA |
544 | bool "Numa Memory Allocation and Scheduler Support" | 546 | bool "Numa Memory Allocation and Scheduler Support" |
545 | depends on SMP && HIGHMEM64G && (X86_NUMAQ || X86_GENERICARCH || (X86_SUMMIT && ACPI)) | 547 | depends on SMP && HIGHMEM64G && (X86_NUMAQ || (X86_SUMMIT || X86_GENERICARCH) && ACPI) |
546 | default n if X86_PC | 548 | default n if X86_PC |
547 | default y if (X86_NUMAQ || X86_SUMMIT) | 549 | default y if (X86_NUMAQ || X86_SUMMIT) |
548 | 550 | ||
diff --git a/arch/i386/kernel/acpi/boot.c b/arch/i386/kernel/acpi/boot.c index 0db6387025ca..ee003bc0e8b1 100644 --- a/arch/i386/kernel/acpi/boot.c +++ b/arch/i386/kernel/acpi/boot.c | |||
@@ -59,7 +59,7 @@ static inline int gsi_irq_sharing(int gsi) { return gsi; } | |||
59 | 59 | ||
60 | #define BAD_MADT_ENTRY(entry, end) ( \ | 60 | #define BAD_MADT_ENTRY(entry, end) ( \ |
61 | (!entry) || (unsigned long)entry + sizeof(*entry) > end || \ | 61 | (!entry) || (unsigned long)entry + sizeof(*entry) > end || \ |
62 | ((acpi_table_entry_header *)entry)->length != sizeof(*entry)) | 62 | ((acpi_table_entry_header *)entry)->length < sizeof(*entry)) |
63 | 63 | ||
64 | #define PREFIX "ACPI: " | 64 | #define PREFIX "ACPI: " |
65 | 65 | ||
diff --git a/arch/i386/kernel/acpi/wakeup.S b/arch/i386/kernel/acpi/wakeup.S index 9f408eee4e6f..b781b38131c0 100644 --- a/arch/i386/kernel/acpi/wakeup.S +++ b/arch/i386/kernel/acpi/wakeup.S | |||
@@ -292,7 +292,10 @@ ENTRY(do_suspend_lowlevel) | |||
292 | pushl $3 | 292 | pushl $3 |
293 | call acpi_enter_sleep_state | 293 | call acpi_enter_sleep_state |
294 | addl $4, %esp | 294 | addl $4, %esp |
295 | ret | 295 | |
296 | # In case of S3 failure, we'll emerge here. Jump | ||
297 | # to ret_point to recover | ||
298 | jmp ret_point | ||
296 | .p2align 4,,7 | 299 | .p2align 4,,7 |
297 | ret_point: | 300 | ret_point: |
298 | call restore_registers | 301 | call restore_registers |
diff --git a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c index efb41e81351c..e6ea00edcb54 100644 --- a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c +++ b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c | |||
@@ -567,16 +567,11 @@ static struct cpufreq_driver acpi_cpufreq_driver = { | |||
567 | static int __init | 567 | static int __init |
568 | acpi_cpufreq_init (void) | 568 | acpi_cpufreq_init (void) |
569 | { | 569 | { |
570 | int result = 0; | ||
571 | |||
572 | dprintk("acpi_cpufreq_init\n"); | 570 | dprintk("acpi_cpufreq_init\n"); |
573 | 571 | ||
574 | result = acpi_cpufreq_early_init_acpi(); | 572 | acpi_cpufreq_early_init_acpi(); |
575 | 573 | ||
576 | if (!result) | 574 | return cpufreq_register_driver(&acpi_cpufreq_driver); |
577 | result = cpufreq_register_driver(&acpi_cpufreq_driver); | ||
578 | |||
579 | return (result); | ||
580 | } | 575 | } |
581 | 576 | ||
582 | 577 | ||
diff --git a/arch/i386/pci/init.c b/arch/i386/pci/init.c index c7650a7e0b07..51087a9d9172 100644 --- a/arch/i386/pci/init.c +++ b/arch/i386/pci/init.c | |||
@@ -14,8 +14,12 @@ static __init int pci_access_init(void) | |||
14 | #ifdef CONFIG_PCI_BIOS | 14 | #ifdef CONFIG_PCI_BIOS |
15 | pci_pcbios_init(); | 15 | pci_pcbios_init(); |
16 | #endif | 16 | #endif |
17 | if (raw_pci_ops) | 17 | /* |
18 | return 0; | 18 | * don't check for raw_pci_ops here because we want pcbios as last |
19 | * fallback, yet it's needed to run first to set pcibios_last_bus | ||
20 | * in case legacy PCI probing is used. otherwise detecting peer busses | ||
21 | * fails. | ||
22 | */ | ||
19 | #ifdef CONFIG_PCI_DIRECT | 23 | #ifdef CONFIG_PCI_DIRECT |
20 | pci_direct_init(); | 24 | pci_direct_init(); |
21 | #endif | 25 | #endif |
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c index e545b0992c48..972180f738d9 100644 --- a/arch/i386/pci/mmconfig.c +++ b/arch/i386/pci/mmconfig.c | |||
@@ -178,7 +178,7 @@ static __init void unreachable_devices(void) | |||
178 | pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0)); | 178 | pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0)); |
179 | if (addr == 0 || | 179 | if (addr == 0 || |
180 | readl((u32 __iomem *)mmcfg_virt_addr) != val1) { | 180 | readl((u32 __iomem *)mmcfg_virt_addr) != val1) { |
181 | set_bit(i, fallback_slots); | 181 | set_bit(i + 32*k, fallback_slots); |
182 | printk(KERN_NOTICE | 182 | printk(KERN_NOTICE |
183 | "PCI: No mmconfig possible on %x:%x\n", k, i); | 183 | "PCI: No mmconfig possible on %x:%x\n", k, i); |
184 | } | 184 | } |
diff --git a/arch/ia64/hp/sim/simscsi.c b/arch/ia64/hp/sim/simscsi.c index 8a4f0d0d17a3..8f0a16a79a67 100644 --- a/arch/ia64/hp/sim/simscsi.c +++ b/arch/ia64/hp/sim/simscsi.c | |||
@@ -244,7 +244,8 @@ static void simscsi_fillresult(struct scsi_cmnd *sc, char *buf, unsigned len) | |||
244 | 244 | ||
245 | if (scatterlen == 0) | 245 | if (scatterlen == 0) |
246 | memcpy(sc->request_buffer, buf, len); | 246 | memcpy(sc->request_buffer, buf, len); |
247 | else for (slp = (struct scatterlist *)sc->request_buffer; scatterlen-- > 0 && len > 0; slp++) { | 247 | else for (slp = (struct scatterlist *)sc->request_buffer; |
248 | scatterlen-- > 0 && len > 0; slp++) { | ||
248 | unsigned thislen = min(len, slp->length); | 249 | unsigned thislen = min(len, slp->length); |
249 | 250 | ||
250 | memcpy(page_address(slp->page) + slp->offset, buf, thislen); | 251 | memcpy(page_address(slp->page) + slp->offset, buf, thislen); |
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c index 99761b81db44..0176556aeecc 100644 --- a/arch/ia64/kernel/acpi.c +++ b/arch/ia64/kernel/acpi.c | |||
@@ -55,7 +55,7 @@ | |||
55 | 55 | ||
56 | #define BAD_MADT_ENTRY(entry, end) ( \ | 56 | #define BAD_MADT_ENTRY(entry, end) ( \ |
57 | (!entry) || (unsigned long)entry + sizeof(*entry) > end || \ | 57 | (!entry) || (unsigned long)entry + sizeof(*entry) > end || \ |
58 | ((acpi_table_entry_header *)entry)->length != sizeof(*entry)) | 58 | ((acpi_table_entry_header *)entry)->length < sizeof(*entry)) |
59 | 59 | ||
60 | #define PREFIX "ACPI: " | 60 | #define PREFIX "ACPI: " |
61 | 61 | ||
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts new file mode 100644 index 000000000000..5f41c1f7a5f3 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8540ads.dts | |||
@@ -0,0 +1,257 @@ | |||
1 | /* | ||
2 | * MPC8540 ADS Device Tree Source | ||
3 | * | ||
4 | * Copyright 2006 Freescale Semiconductor Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | |||
13 | / { | ||
14 | model = "MPC8540ADS"; | ||
15 | compatible = "MPC85xxADS"; | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <1>; | ||
18 | linux,phandle = <100>; | ||
19 | |||
20 | cpus { | ||
21 | #cpus = <1>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | linux,phandle = <200>; | ||
25 | |||
26 | PowerPC,8540@0 { | ||
27 | device_type = "cpu"; | ||
28 | reg = <0>; | ||
29 | d-cache-line-size = <20>; // 32 bytes | ||
30 | i-cache-line-size = <20>; // 32 bytes | ||
31 | d-cache-size = <8000>; // L1, 32K | ||
32 | i-cache-size = <8000>; // L1, 32K | ||
33 | timebase-frequency = <0>; // 33 MHz, from uboot | ||
34 | bus-frequency = <0>; // 166 MHz | ||
35 | clock-frequency = <0>; // 825 MHz, from uboot | ||
36 | 32-bit; | ||
37 | linux,phandle = <201>; | ||
38 | }; | ||
39 | }; | ||
40 | |||
41 | memory { | ||
42 | device_type = "memory"; | ||
43 | linux,phandle = <300>; | ||
44 | reg = <00000000 08000000>; // 128M at 0x0 | ||
45 | }; | ||
46 | |||
47 | soc8540@e0000000 { | ||
48 | #address-cells = <1>; | ||
49 | #size-cells = <1>; | ||
50 | #interrupt-cells = <2>; | ||
51 | device_type = "soc"; | ||
52 | ranges = <0 e0000000 00100000>; | ||
53 | reg = <e0000000 00100000>; // CCSRBAR 1M | ||
54 | bus-frequency = <0>; | ||
55 | |||
56 | i2c@3000 { | ||
57 | device_type = "i2c"; | ||
58 | compatible = "fsl-i2c"; | ||
59 | reg = <3000 100>; | ||
60 | interrupts = <1b 2>; | ||
61 | interrupt-parent = <40000>; | ||
62 | dfsrr; | ||
63 | }; | ||
64 | |||
65 | mdio@24520 { | ||
66 | #address-cells = <1>; | ||
67 | #size-cells = <0>; | ||
68 | device_type = "mdio"; | ||
69 | compatible = "gianfar"; | ||
70 | reg = <24520 20>; | ||
71 | linux,phandle = <24520>; | ||
72 | ethernet-phy@0 { | ||
73 | linux,phandle = <2452000>; | ||
74 | interrupt-parent = <40000>; | ||
75 | interrupts = <35 1>; | ||
76 | reg = <0>; | ||
77 | device_type = "ethernet-phy"; | ||
78 | }; | ||
79 | ethernet-phy@1 { | ||
80 | linux,phandle = <2452001>; | ||
81 | interrupt-parent = <40000>; | ||
82 | interrupts = <35 1>; | ||
83 | reg = <1>; | ||
84 | device_type = "ethernet-phy"; | ||
85 | }; | ||
86 | ethernet-phy@3 { | ||
87 | linux,phandle = <2452003>; | ||
88 | interrupt-parent = <40000>; | ||
89 | interrupts = <37 1>; | ||
90 | reg = <3>; | ||
91 | device_type = "ethernet-phy"; | ||
92 | }; | ||
93 | }; | ||
94 | |||
95 | ethernet@24000 { | ||
96 | #address-cells = <1>; | ||
97 | #size-cells = <0>; | ||
98 | device_type = "network"; | ||
99 | model = "TSEC"; | ||
100 | compatible = "gianfar"; | ||
101 | reg = <24000 1000>; | ||
102 | address = [ 00 E0 0C 00 73 00 ]; | ||
103 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | ||
104 | interrupts = <d 2 e 2 12 2>; | ||
105 | interrupt-parent = <40000>; | ||
106 | phy-handle = <2452000>; | ||
107 | }; | ||
108 | |||
109 | ethernet@25000 { | ||
110 | #address-cells = <1>; | ||
111 | #size-cells = <0>; | ||
112 | device_type = "network"; | ||
113 | model = "TSEC"; | ||
114 | compatible = "gianfar"; | ||
115 | reg = <25000 1000>; | ||
116 | address = [ 00 E0 0C 00 73 01 ]; | ||
117 | local-mac-address = [ 00 E0 0C 00 73 01 ]; | ||
118 | interrupts = <13 2 14 2 18 2>; | ||
119 | interrupt-parent = <40000>; | ||
120 | phy-handle = <2452001>; | ||
121 | }; | ||
122 | |||
123 | ethernet@26000 { | ||
124 | #address-cells = <1>; | ||
125 | #size-cells = <0>; | ||
126 | device_type = "network"; | ||
127 | model = "FEC"; | ||
128 | compatible = "gianfar"; | ||
129 | reg = <26000 1000>; | ||
130 | address = [ 00 E0 0C 00 73 02 ]; | ||
131 | local-mac-address = [ 00 E0 0C 00 73 02 ]; | ||
132 | interrupts = <19 2>; | ||
133 | interrupt-parent = <40000>; | ||
134 | phy-handle = <2452003>; | ||
135 | }; | ||
136 | |||
137 | serial@4500 { | ||
138 | device_type = "serial"; | ||
139 | compatible = "ns16550"; | ||
140 | reg = <4500 100>; // reg base, size | ||
141 | clock-frequency = <0>; // should we fill in in uboot? | ||
142 | interrupts = <1a 2>; | ||
143 | interrupt-parent = <40000>; | ||
144 | }; | ||
145 | |||
146 | serial@4600 { | ||
147 | device_type = "serial"; | ||
148 | compatible = "ns16550"; | ||
149 | reg = <4600 100>; // reg base, size | ||
150 | clock-frequency = <0>; // should we fill in in uboot? | ||
151 | interrupts = <1a 2>; | ||
152 | interrupt-parent = <40000>; | ||
153 | }; | ||
154 | pci@8000 { | ||
155 | linux,phandle = <8000>; | ||
156 | interrupt-map-mask = <f800 0 0 7>; | ||
157 | interrupt-map = < | ||
158 | |||
159 | /* IDSEL 0x02 */ | ||
160 | 1000 0 0 1 40000 31 1 | ||
161 | 1000 0 0 2 40000 32 1 | ||
162 | 1000 0 0 3 40000 33 1 | ||
163 | 1000 0 0 4 40000 34 1 | ||
164 | |||
165 | /* IDSEL 0x03 */ | ||
166 | 1800 0 0 1 40000 34 1 | ||
167 | 1800 0 0 2 40000 31 1 | ||
168 | 1800 0 0 3 40000 32 1 | ||
169 | 1800 0 0 4 40000 33 1 | ||
170 | |||
171 | /* IDSEL 0x04 */ | ||
172 | 2000 0 0 1 40000 33 1 | ||
173 | 2000 0 0 2 40000 34 1 | ||
174 | 2000 0 0 3 40000 31 1 | ||
175 | 2000 0 0 4 40000 32 1 | ||
176 | |||
177 | /* IDSEL 0x05 */ | ||
178 | 2800 0 0 1 40000 32 1 | ||
179 | 2800 0 0 2 40000 33 1 | ||
180 | 2800 0 0 3 40000 34 1 | ||
181 | 2800 0 0 4 40000 31 1 | ||
182 | |||
183 | /* IDSEL 0x0c */ | ||
184 | 6000 0 0 1 40000 31 1 | ||
185 | 6000 0 0 2 40000 32 1 | ||
186 | 6000 0 0 3 40000 33 1 | ||
187 | 6000 0 0 4 40000 34 1 | ||
188 | |||
189 | /* IDSEL 0x0d */ | ||
190 | 6800 0 0 1 40000 34 1 | ||
191 | 6800 0 0 2 40000 31 1 | ||
192 | 6800 0 0 3 40000 32 1 | ||
193 | 6800 0 0 4 40000 33 1 | ||
194 | |||
195 | /* IDSEL 0x0e */ | ||
196 | 7000 0 0 1 40000 33 1 | ||
197 | 7000 0 0 2 40000 34 1 | ||
198 | 7000 0 0 3 40000 31 1 | ||
199 | 7000 0 0 4 40000 32 1 | ||
200 | |||
201 | /* IDSEL 0x0f */ | ||
202 | 7800 0 0 1 40000 32 1 | ||
203 | 7800 0 0 2 40000 33 1 | ||
204 | 7800 0 0 3 40000 34 1 | ||
205 | 7800 0 0 4 40000 31 1 | ||
206 | |||
207 | /* IDSEL 0x12 */ | ||
208 | 9000 0 0 1 40000 31 1 | ||
209 | 9000 0 0 2 40000 32 1 | ||
210 | 9000 0 0 3 40000 33 1 | ||
211 | 9000 0 0 4 40000 34 1 | ||
212 | |||
213 | /* IDSEL 0x13 */ | ||
214 | 9800 0 0 1 40000 34 1 | ||
215 | 9800 0 0 2 40000 31 1 | ||
216 | 9800 0 0 3 40000 32 1 | ||
217 | 9800 0 0 4 40000 33 1 | ||
218 | |||
219 | /* IDSEL 0x14 */ | ||
220 | a000 0 0 1 40000 33 1 | ||
221 | a000 0 0 2 40000 34 1 | ||
222 | a000 0 0 3 40000 31 1 | ||
223 | a000 0 0 4 40000 32 1 | ||
224 | |||
225 | /* IDSEL 0x15 */ | ||
226 | a800 0 0 1 40000 32 1 | ||
227 | a800 0 0 2 40000 33 1 | ||
228 | a800 0 0 3 40000 34 1 | ||
229 | a800 0 0 4 40000 31 1>; | ||
230 | interrupt-parent = <40000>; | ||
231 | interrupts = <08 2>; | ||
232 | bus-range = <0 0>; | ||
233 | ranges = <02000000 0 80000000 80000000 0 20000000 | ||
234 | 01000000 0 00000000 e2000000 0 00100000>; | ||
235 | clock-frequency = <3f940aa>; | ||
236 | #interrupt-cells = <1>; | ||
237 | #size-cells = <2>; | ||
238 | #address-cells = <3>; | ||
239 | reg = <8000 1000>; | ||
240 | compatible = "85xx"; | ||
241 | device_type = "pci"; | ||
242 | }; | ||
243 | |||
244 | pic@40000 { | ||
245 | linux,phandle = <40000>; | ||
246 | clock-frequency = <0>; | ||
247 | interrupt-controller; | ||
248 | #address-cells = <0>; | ||
249 | #interrupt-cells = <2>; | ||
250 | reg = <40000 40000>; | ||
251 | built-in; | ||
252 | compatible = "chrp,open-pic"; | ||
253 | device_type = "open-pic"; | ||
254 | big-endian; | ||
255 | }; | ||
256 | }; | ||
257 | }; | ||
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts new file mode 100644 index 000000000000..7be0bc659e1c --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8541cds.dts | |||
@@ -0,0 +1,244 @@ | |||
1 | /* | ||
2 | * MPC8541 CDS Device Tree Source | ||
3 | * | ||
4 | * Copyright 2006 Freescale Semiconductor Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | |||
13 | / { | ||
14 | model = "MPC8541CDS"; | ||
15 | compatible = "MPC85xxCDS"; | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <1>; | ||
18 | linux,phandle = <100>; | ||
19 | |||
20 | cpus { | ||
21 | #cpus = <1>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | linux,phandle = <200>; | ||
25 | |||
26 | PowerPC,8541@0 { | ||
27 | device_type = "cpu"; | ||
28 | reg = <0>; | ||
29 | d-cache-line-size = <20>; // 32 bytes | ||
30 | i-cache-line-size = <20>; // 32 bytes | ||
31 | d-cache-size = <8000>; // L1, 32K | ||
32 | i-cache-size = <8000>; // L1, 32K | ||
33 | timebase-frequency = <0>; // 33 MHz, from uboot | ||
34 | bus-frequency = <0>; // 166 MHz | ||
35 | clock-frequency = <0>; // 825 MHz, from uboot | ||
36 | 32-bit; | ||
37 | linux,phandle = <201>; | ||
38 | }; | ||
39 | }; | ||
40 | |||
41 | memory { | ||
42 | device_type = "memory"; | ||
43 | linux,phandle = <300>; | ||
44 | reg = <00000000 08000000>; // 128M at 0x0 | ||
45 | }; | ||
46 | |||
47 | soc8541@e0000000 { | ||
48 | #address-cells = <1>; | ||
49 | #size-cells = <1>; | ||
50 | #interrupt-cells = <2>; | ||
51 | device_type = "soc"; | ||
52 | ranges = <0 e0000000 00100000>; | ||
53 | reg = <e0000000 00100000>; // CCSRBAR 1M | ||
54 | bus-frequency = <0>; | ||
55 | |||
56 | i2c@3000 { | ||
57 | device_type = "i2c"; | ||
58 | compatible = "fsl-i2c"; | ||
59 | reg = <3000 100>; | ||
60 | interrupts = <1b 2>; | ||
61 | interrupt-parent = <40000>; | ||
62 | dfsrr; | ||
63 | }; | ||
64 | |||
65 | mdio@24520 { | ||
66 | #address-cells = <1>; | ||
67 | #size-cells = <0>; | ||
68 | device_type = "mdio"; | ||
69 | compatible = "gianfar"; | ||
70 | reg = <24520 20>; | ||
71 | linux,phandle = <24520>; | ||
72 | ethernet-phy@0 { | ||
73 | linux,phandle = <2452000>; | ||
74 | interrupt-parent = <40000>; | ||
75 | interrupts = <35 0>; | ||
76 | reg = <0>; | ||
77 | device_type = "ethernet-phy"; | ||
78 | }; | ||
79 | ethernet-phy@1 { | ||
80 | linux,phandle = <2452001>; | ||
81 | interrupt-parent = <40000>; | ||
82 | interrupts = <35 0>; | ||
83 | reg = <1>; | ||
84 | device_type = "ethernet-phy"; | ||
85 | }; | ||
86 | }; | ||
87 | |||
88 | ethernet@24000 { | ||
89 | #address-cells = <1>; | ||
90 | #size-cells = <0>; | ||
91 | device_type = "network"; | ||
92 | model = "TSEC"; | ||
93 | compatible = "gianfar"; | ||
94 | reg = <24000 1000>; | ||
95 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | ||
96 | interrupts = <d 2 e 2 12 2>; | ||
97 | interrupt-parent = <40000>; | ||
98 | phy-handle = <2452000>; | ||
99 | }; | ||
100 | |||
101 | ethernet@25000 { | ||
102 | #address-cells = <1>; | ||
103 | #size-cells = <0>; | ||
104 | device_type = "network"; | ||
105 | model = "TSEC"; | ||
106 | compatible = "gianfar"; | ||
107 | reg = <25000 1000>; | ||
108 | local-mac-address = [ 00 E0 0C 00 73 01 ]; | ||
109 | interrupts = <13 2 14 2 18 2>; | ||
110 | interrupt-parent = <40000>; | ||
111 | phy-handle = <2452001>; | ||
112 | }; | ||
113 | |||
114 | serial@4500 { | ||
115 | device_type = "serial"; | ||
116 | compatible = "ns16550"; | ||
117 | reg = <4500 100>; // reg base, size | ||
118 | clock-frequency = <0>; // should we fill in in uboot? | ||
119 | interrupts = <1a 2>; | ||
120 | interrupt-parent = <40000>; | ||
121 | }; | ||
122 | |||
123 | serial@4600 { | ||
124 | device_type = "serial"; | ||
125 | compatible = "ns16550"; | ||
126 | reg = <4600 100>; // reg base, size | ||
127 | clock-frequency = <0>; // should we fill in in uboot? | ||
128 | interrupts = <1a 2>; | ||
129 | interrupt-parent = <40000>; | ||
130 | }; | ||
131 | |||
132 | pci@8000 { | ||
133 | linux,phandle = <8000>; | ||
134 | interrupt-map-mask = <1f800 0 0 7>; | ||
135 | interrupt-map = < | ||
136 | |||
137 | /* IDSEL 0x10 */ | ||
138 | 08000 0 0 1 40000 30 1 | ||
139 | 08000 0 0 2 40000 31 1 | ||
140 | 08000 0 0 3 40000 32 1 | ||
141 | 08000 0 0 4 40000 33 1 | ||
142 | |||
143 | /* IDSEL 0x11 */ | ||
144 | 08800 0 0 1 40000 30 1 | ||
145 | 08800 0 0 2 40000 31 1 | ||
146 | 08800 0 0 3 40000 32 1 | ||
147 | 08800 0 0 4 40000 33 1 | ||
148 | |||
149 | /* IDSEL 0x12 (Slot 1) */ | ||
150 | 09000 0 0 1 40000 30 1 | ||
151 | 09000 0 0 2 40000 31 1 | ||
152 | 09000 0 0 3 40000 32 1 | ||
153 | 09000 0 0 4 40000 33 1 | ||
154 | |||
155 | /* IDSEL 0x13 (Slot 2) */ | ||
156 | 09800 0 0 1 40000 31 1 | ||
157 | 09800 0 0 2 40000 32 1 | ||
158 | 09800 0 0 3 40000 33 1 | ||
159 | 09800 0 0 4 40000 30 1 | ||
160 | |||
161 | /* IDSEL 0x14 (Slot 3) */ | ||
162 | 0a000 0 0 1 40000 32 1 | ||
163 | 0a000 0 0 2 40000 33 1 | ||
164 | 0a000 0 0 3 40000 30 1 | ||
165 | 0a000 0 0 4 40000 31 1 | ||
166 | |||
167 | /* IDSEL 0x15 (Slot 4) */ | ||
168 | 0a800 0 0 1 40000 33 1 | ||
169 | 0a800 0 0 2 40000 30 1 | ||
170 | 0a800 0 0 3 40000 31 1 | ||
171 | 0a800 0 0 4 40000 32 1 | ||
172 | |||
173 | /* Bus 1 (Tundra Bridge) */ | ||
174 | /* IDSEL 0x12 (ISA bridge) */ | ||
175 | 19000 0 0 1 40000 30 1 | ||
176 | 19000 0 0 2 40000 31 1 | ||
177 | 19000 0 0 3 40000 32 1 | ||
178 | 19000 0 0 4 40000 33 1>; | ||
179 | interrupt-parent = <40000>; | ||
180 | interrupts = <08 2>; | ||
181 | bus-range = <0 0>; | ||
182 | ranges = <02000000 0 80000000 80000000 0 20000000 | ||
183 | 01000000 0 00000000 e2000000 0 00100000>; | ||
184 | clock-frequency = <3f940aa>; | ||
185 | #interrupt-cells = <1>; | ||
186 | #size-cells = <2>; | ||
187 | #address-cells = <3>; | ||
188 | reg = <8000 1000>; | ||
189 | compatible = "85xx"; | ||
190 | device_type = "pci"; | ||
191 | |||
192 | i8259@19000 { | ||
193 | clock-frequency = <0>; | ||
194 | interrupt-controller; | ||
195 | device_type = "interrupt-controller"; | ||
196 | reg = <19000 0 0 0 1>; | ||
197 | #address-cells = <0>; | ||
198 | #interrupt-cells = <2>; | ||
199 | built-in; | ||
200 | compatible = "chrp,iic"; | ||
201 | big-endian; | ||
202 | interrupts = <1>; | ||
203 | interrupt-parent = <8000>; | ||
204 | }; | ||
205 | }; | ||
206 | |||
207 | pci@9000 { | ||
208 | linux,phandle = <9000>; | ||
209 | interrupt-map-mask = <f800 0 0 7>; | ||
210 | interrupt-map = < | ||
211 | |||
212 | /* IDSEL 0x15 */ | ||
213 | a800 0 0 1 40000 3b 1 | ||
214 | a800 0 0 2 40000 3b 1 | ||
215 | a800 0 0 3 40000 3b 1 | ||
216 | a800 0 0 4 40000 3b 1>; | ||
217 | interrupt-parent = <40000>; | ||
218 | interrupts = <09 2>; | ||
219 | bus-range = <0 0>; | ||
220 | ranges = <02000000 0 a0000000 a0000000 0 20000000 | ||
221 | 01000000 0 00000000 e3000000 0 00100000>; | ||
222 | clock-frequency = <3f940aa>; | ||
223 | #interrupt-cells = <1>; | ||
224 | #size-cells = <2>; | ||
225 | #address-cells = <3>; | ||
226 | reg = <9000 1000>; | ||
227 | compatible = "85xx"; | ||
228 | device_type = "pci"; | ||
229 | }; | ||
230 | |||
231 | pic@40000 { | ||
232 | linux,phandle = <40000>; | ||
233 | clock-frequency = <0>; | ||
234 | interrupt-controller; | ||
235 | #address-cells = <0>; | ||
236 | #interrupt-cells = <2>; | ||
237 | reg = <40000 40000>; | ||
238 | built-in; | ||
239 | compatible = "chrp,open-pic"; | ||
240 | device_type = "open-pic"; | ||
241 | big-endian; | ||
242 | }; | ||
243 | }; | ||
244 | }; | ||
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts new file mode 100644 index 000000000000..893d7957c174 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8548cds.dts | |||
@@ -0,0 +1,287 @@ | |||
1 | /* | ||
2 | * MPC8555 CDS Device Tree Source | ||
3 | * | ||
4 | * Copyright 2006 Freescale Semiconductor Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | |||
13 | / { | ||
14 | model = "MPC8548CDS"; | ||
15 | compatible = "MPC85xxCDS"; | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <1>; | ||
18 | linux,phandle = <100>; | ||
19 | |||
20 | cpus { | ||
21 | #cpus = <1>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | linux,phandle = <200>; | ||
25 | |||
26 | PowerPC,8548@0 { | ||
27 | device_type = "cpu"; | ||
28 | reg = <0>; | ||
29 | d-cache-line-size = <20>; // 32 bytes | ||
30 | i-cache-line-size = <20>; // 32 bytes | ||
31 | d-cache-size = <8000>; // L1, 32K | ||
32 | i-cache-size = <8000>; // L1, 32K | ||
33 | timebase-frequency = <0>; // 33 MHz, from uboot | ||
34 | bus-frequency = <0>; // 166 MHz | ||
35 | clock-frequency = <0>; // 825 MHz, from uboot | ||
36 | 32-bit; | ||
37 | linux,phandle = <201>; | ||
38 | }; | ||
39 | }; | ||
40 | |||
41 | memory { | ||
42 | device_type = "memory"; | ||
43 | linux,phandle = <300>; | ||
44 | reg = <00000000 08000000>; // 128M at 0x0 | ||
45 | }; | ||
46 | |||
47 | soc8548@e0000000 { | ||
48 | #address-cells = <1>; | ||
49 | #size-cells = <1>; | ||
50 | #interrupt-cells = <2>; | ||
51 | device_type = "soc"; | ||
52 | ranges = <0 e0000000 00100000>; | ||
53 | reg = <e0000000 00100000>; // CCSRBAR 1M | ||
54 | bus-frequency = <0>; | ||
55 | |||
56 | i2c@3000 { | ||
57 | device_type = "i2c"; | ||
58 | compatible = "fsl-i2c"; | ||
59 | reg = <3000 100>; | ||
60 | interrupts = <1b 2>; | ||
61 | interrupt-parent = <40000>; | ||
62 | dfsrr; | ||
63 | }; | ||
64 | |||
65 | mdio@24520 { | ||
66 | #address-cells = <1>; | ||
67 | #size-cells = <0>; | ||
68 | device_type = "mdio"; | ||
69 | compatible = "gianfar"; | ||
70 | reg = <24520 20>; | ||
71 | linux,phandle = <24520>; | ||
72 | ethernet-phy@0 { | ||
73 | linux,phandle = <2452000>; | ||
74 | interrupt-parent = <40000>; | ||
75 | interrupts = <35 0>; | ||
76 | reg = <0>; | ||
77 | device_type = "ethernet-phy"; | ||
78 | }; | ||
79 | ethernet-phy@1 { | ||
80 | linux,phandle = <2452001>; | ||
81 | interrupt-parent = <40000>; | ||
82 | interrupts = <35 0>; | ||
83 | reg = <1>; | ||
84 | device_type = "ethernet-phy"; | ||
85 | }; | ||
86 | |||
87 | ethernet-phy@2 { | ||
88 | linux,phandle = <2452002>; | ||
89 | interrupt-parent = <40000>; | ||
90 | interrupts = <35 0>; | ||
91 | reg = <2>; | ||
92 | device_type = "ethernet-phy"; | ||
93 | }; | ||
94 | ethernet-phy@3 { | ||
95 | linux,phandle = <2452003>; | ||
96 | interrupt-parent = <40000>; | ||
97 | interrupts = <35 0>; | ||
98 | reg = <3>; | ||
99 | device_type = "ethernet-phy"; | ||
100 | }; | ||
101 | }; | ||
102 | |||
103 | ethernet@24000 { | ||
104 | #address-cells = <1>; | ||
105 | #size-cells = <0>; | ||
106 | device_type = "network"; | ||
107 | model = "eTSEC"; | ||
108 | compatible = "gianfar"; | ||
109 | reg = <24000 1000>; | ||
110 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | ||
111 | interrupts = <d 2 e 2 12 2>; | ||
112 | interrupt-parent = <40000>; | ||
113 | phy-handle = <2452000>; | ||
114 | }; | ||
115 | |||
116 | ethernet@25000 { | ||
117 | #address-cells = <1>; | ||
118 | #size-cells = <0>; | ||
119 | device_type = "network"; | ||
120 | model = "eTSEC"; | ||
121 | compatible = "gianfar"; | ||
122 | reg = <25000 1000>; | ||
123 | local-mac-address = [ 00 E0 0C 00 73 01 ]; | ||
124 | interrupts = <13 2 14 2 18 2>; | ||
125 | interrupt-parent = <40000>; | ||
126 | phy-handle = <2452001>; | ||
127 | }; | ||
128 | |||
129 | ethernet@26000 { | ||
130 | #address-cells = <1>; | ||
131 | #size-cells = <0>; | ||
132 | device_type = "network"; | ||
133 | model = "eTSEC"; | ||
134 | compatible = "gianfar"; | ||
135 | reg = <26000 1000>; | ||
136 | local-mac-address = [ 00 E0 0C 00 73 02 ]; | ||
137 | interrupts = <f 2 10 2 11 2>; | ||
138 | interrupt-parent = <40000>; | ||
139 | phy-handle = <2452001>; | ||
140 | }; | ||
141 | |||
142 | /* eTSEC 4 is currently broken | ||
143 | ethernet@27000 { | ||
144 | #address-cells = <1>; | ||
145 | #size-cells = <0>; | ||
146 | device_type = "network"; | ||
147 | model = "eTSEC"; | ||
148 | compatible = "gianfar"; | ||
149 | reg = <27000 1000>; | ||
150 | local-mac-address = [ 00 E0 0C 00 73 03 ]; | ||
151 | interrupts = <15 2 16 2 17 2>; | ||
152 | interrupt-parent = <40000>; | ||
153 | phy-handle = <2452001>; | ||
154 | }; | ||
155 | */ | ||
156 | |||
157 | serial@4500 { | ||
158 | device_type = "serial"; | ||
159 | compatible = "ns16550"; | ||
160 | reg = <4500 100>; // reg base, size | ||
161 | clock-frequency = <0>; // should we fill in in uboot? | ||
162 | interrupts = <1a 2>; | ||
163 | interrupt-parent = <40000>; | ||
164 | }; | ||
165 | |||
166 | serial@4600 { | ||
167 | device_type = "serial"; | ||
168 | compatible = "ns16550"; | ||
169 | reg = <4600 100>; // reg base, size | ||
170 | clock-frequency = <0>; // should we fill in in uboot? | ||
171 | interrupts = <1a 2>; | ||
172 | interrupt-parent = <40000>; | ||
173 | }; | ||
174 | |||
175 | pci@8000 { | ||
176 | linux,phandle = <8000>; | ||
177 | interrupt-map-mask = <1f800 0 0 7>; | ||
178 | interrupt-map = < | ||
179 | |||
180 | /* IDSEL 0x10 */ | ||
181 | 08000 0 0 1 40000 30 1 | ||
182 | 08000 0 0 2 40000 31 1 | ||
183 | 08000 0 0 3 40000 32 1 | ||
184 | 08000 0 0 4 40000 33 1 | ||
185 | |||
186 | /* IDSEL 0x11 */ | ||
187 | 08800 0 0 1 40000 30 1 | ||
188 | 08800 0 0 2 40000 31 1 | ||
189 | 08800 0 0 3 40000 32 1 | ||
190 | 08800 0 0 4 40000 33 1 | ||
191 | |||
192 | /* IDSEL 0x12 (Slot 1) */ | ||
193 | 09000 0 0 1 40000 30 1 | ||
194 | 09000 0 0 2 40000 31 1 | ||
195 | 09000 0 0 3 40000 32 1 | ||
196 | 09000 0 0 4 40000 33 1 | ||
197 | |||
198 | /* IDSEL 0x13 (Slot 2) */ | ||
199 | 09800 0 0 1 40000 31 1 | ||
200 | 09800 0 0 2 40000 32 1 | ||
201 | 09800 0 0 3 40000 33 1 | ||
202 | 09800 0 0 4 40000 30 1 | ||
203 | |||
204 | /* IDSEL 0x14 (Slot 3) */ | ||
205 | 0a000 0 0 1 40000 32 1 | ||
206 | 0a000 0 0 2 40000 33 1 | ||
207 | 0a000 0 0 3 40000 30 1 | ||
208 | 0a000 0 0 4 40000 31 1 | ||
209 | |||
210 | /* IDSEL 0x15 (Slot 4) */ | ||
211 | 0a800 0 0 1 40000 33 1 | ||
212 | 0a800 0 0 2 40000 30 1 | ||
213 | 0a800 0 0 3 40000 31 1 | ||
214 | 0a800 0 0 4 40000 32 1 | ||
215 | |||
216 | /* Bus 1 (Tundra Bridge) */ | ||
217 | /* IDSEL 0x12 (ISA bridge) */ | ||
218 | 19000 0 0 1 40000 30 1 | ||
219 | 19000 0 0 2 40000 31 1 | ||
220 | 19000 0 0 3 40000 32 1 | ||
221 | 19000 0 0 4 40000 33 1>; | ||
222 | interrupt-parent = <40000>; | ||
223 | interrupts = <08 2>; | ||
224 | bus-range = <0 0>; | ||
225 | ranges = <02000000 0 80000000 80000000 0 20000000 | ||
226 | 01000000 0 00000000 e2000000 0 00100000>; | ||
227 | clock-frequency = <3f940aa>; | ||
228 | #interrupt-cells = <1>; | ||
229 | #size-cells = <2>; | ||
230 | #address-cells = <3>; | ||
231 | reg = <8000 1000>; | ||
232 | compatible = "85xx"; | ||
233 | device_type = "pci"; | ||
234 | |||
235 | i8259@19000 { | ||
236 | clock-frequency = <0>; | ||
237 | interrupt-controller; | ||
238 | device_type = "interrupt-controller"; | ||
239 | reg = <19000 0 0 0 1>; | ||
240 | #address-cells = <0>; | ||
241 | #interrupt-cells = <2>; | ||
242 | built-in; | ||
243 | compatible = "chrp,iic"; | ||
244 | big-endian; | ||
245 | interrupts = <1>; | ||
246 | interrupt-parent = <8000>; | ||
247 | }; | ||
248 | }; | ||
249 | |||
250 | pci@9000 { | ||
251 | linux,phandle = <9000>; | ||
252 | interrupt-map-mask = <f800 0 0 7>; | ||
253 | interrupt-map = < | ||
254 | |||
255 | /* IDSEL 0x15 */ | ||
256 | a800 0 0 1 40000 3b 1 | ||
257 | a800 0 0 2 40000 3b 1 | ||
258 | a800 0 0 3 40000 3b 1 | ||
259 | a800 0 0 4 40000 3b 1>; | ||
260 | interrupt-parent = <40000>; | ||
261 | interrupts = <09 2>; | ||
262 | bus-range = <0 0>; | ||
263 | ranges = <02000000 0 a0000000 a0000000 0 20000000 | ||
264 | 01000000 0 00000000 e3000000 0 00100000>; | ||
265 | clock-frequency = <3f940aa>; | ||
266 | #interrupt-cells = <1>; | ||
267 | #size-cells = <2>; | ||
268 | #address-cells = <3>; | ||
269 | reg = <9000 1000>; | ||
270 | compatible = "85xx"; | ||
271 | device_type = "pci"; | ||
272 | }; | ||
273 | |||
274 | pic@40000 { | ||
275 | linux,phandle = <40000>; | ||
276 | clock-frequency = <0>; | ||
277 | interrupt-controller; | ||
278 | #address-cells = <0>; | ||
279 | #interrupt-cells = <2>; | ||
280 | reg = <40000 40000>; | ||
281 | built-in; | ||
282 | compatible = "chrp,open-pic"; | ||
283 | device_type = "open-pic"; | ||
284 | big-endian; | ||
285 | }; | ||
286 | }; | ||
287 | }; | ||
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts new file mode 100644 index 000000000000..118f5a887651 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8555cds.dts | |||
@@ -0,0 +1,244 @@ | |||
1 | /* | ||
2 | * MPC8555 CDS Device Tree Source | ||
3 | * | ||
4 | * Copyright 2006 Freescale Semiconductor Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | |||
13 | / { | ||
14 | model = "MPC8555CDS"; | ||
15 | compatible = "MPC85xxCDS"; | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <1>; | ||
18 | linux,phandle = <100>; | ||
19 | |||
20 | cpus { | ||
21 | #cpus = <1>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | linux,phandle = <200>; | ||
25 | |||
26 | PowerPC,8555@0 { | ||
27 | device_type = "cpu"; | ||
28 | reg = <0>; | ||
29 | d-cache-line-size = <20>; // 32 bytes | ||
30 | i-cache-line-size = <20>; // 32 bytes | ||
31 | d-cache-size = <8000>; // L1, 32K | ||
32 | i-cache-size = <8000>; // L1, 32K | ||
33 | timebase-frequency = <0>; // 33 MHz, from uboot | ||
34 | bus-frequency = <0>; // 166 MHz | ||
35 | clock-frequency = <0>; // 825 MHz, from uboot | ||
36 | 32-bit; | ||
37 | linux,phandle = <201>; | ||
38 | }; | ||
39 | }; | ||
40 | |||
41 | memory { | ||
42 | device_type = "memory"; | ||
43 | linux,phandle = <300>; | ||
44 | reg = <00000000 08000000>; // 128M at 0x0 | ||
45 | }; | ||
46 | |||
47 | soc8555@e0000000 { | ||
48 | #address-cells = <1>; | ||
49 | #size-cells = <1>; | ||
50 | #interrupt-cells = <2>; | ||
51 | device_type = "soc"; | ||
52 | ranges = <0 e0000000 00100000>; | ||
53 | reg = <e0000000 00100000>; // CCSRBAR 1M | ||
54 | bus-frequency = <0>; | ||
55 | |||
56 | i2c@3000 { | ||
57 | device_type = "i2c"; | ||
58 | compatible = "fsl-i2c"; | ||
59 | reg = <3000 100>; | ||
60 | interrupts = <1b 2>; | ||
61 | interrupt-parent = <40000>; | ||
62 | dfsrr; | ||
63 | }; | ||
64 | |||
65 | mdio@24520 { | ||
66 | #address-cells = <1>; | ||
67 | #size-cells = <0>; | ||
68 | device_type = "mdio"; | ||
69 | compatible = "gianfar"; | ||
70 | reg = <24520 20>; | ||
71 | linux,phandle = <24520>; | ||
72 | ethernet-phy@0 { | ||
73 | linux,phandle = <2452000>; | ||
74 | interrupt-parent = <40000>; | ||
75 | interrupts = <35 0>; | ||
76 | reg = <0>; | ||
77 | device_type = "ethernet-phy"; | ||
78 | }; | ||
79 | ethernet-phy@1 { | ||
80 | linux,phandle = <2452001>; | ||
81 | interrupt-parent = <40000>; | ||
82 | interrupts = <35 0>; | ||
83 | reg = <1>; | ||
84 | device_type = "ethernet-phy"; | ||
85 | }; | ||
86 | }; | ||
87 | |||
88 | ethernet@24000 { | ||
89 | #address-cells = <1>; | ||
90 | #size-cells = <0>; | ||
91 | device_type = "network"; | ||
92 | model = "TSEC"; | ||
93 | compatible = "gianfar"; | ||
94 | reg = <24000 1000>; | ||
95 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | ||
96 | interrupts = <0d 2 0e 2 12 2>; | ||
97 | interrupt-parent = <40000>; | ||
98 | phy-handle = <2452000>; | ||
99 | }; | ||
100 | |||
101 | ethernet@25000 { | ||
102 | #address-cells = <1>; | ||
103 | #size-cells = <0>; | ||
104 | device_type = "network"; | ||
105 | model = "TSEC"; | ||
106 | compatible = "gianfar"; | ||
107 | reg = <25000 1000>; | ||
108 | local-mac-address = [ 00 E0 0C 00 73 01 ]; | ||
109 | interrupts = <13 2 14 2 18 2>; | ||
110 | interrupt-parent = <40000>; | ||
111 | phy-handle = <2452001>; | ||
112 | }; | ||
113 | |||
114 | serial@4500 { | ||
115 | device_type = "serial"; | ||
116 | compatible = "ns16550"; | ||
117 | reg = <4500 100>; // reg base, size | ||
118 | clock-frequency = <0>; // should we fill in in uboot? | ||
119 | interrupts = <1a 2>; | ||
120 | interrupt-parent = <40000>; | ||
121 | }; | ||
122 | |||
123 | serial@4600 { | ||
124 | device_type = "serial"; | ||
125 | compatible = "ns16550"; | ||
126 | reg = <4600 100>; // reg base, size | ||
127 | clock-frequency = <0>; // should we fill in in uboot? | ||
128 | interrupts = <1a 2>; | ||
129 | interrupt-parent = <40000>; | ||
130 | }; | ||
131 | |||
132 | pci@8000 { | ||
133 | linux,phandle = <8000>; | ||
134 | interrupt-map-mask = <1f800 0 0 7>; | ||
135 | interrupt-map = < | ||
136 | |||
137 | /* IDSEL 0x10 */ | ||
138 | 08000 0 0 1 40000 30 1 | ||
139 | 08000 0 0 2 40000 31 1 | ||
140 | 08000 0 0 3 40000 32 1 | ||
141 | 08000 0 0 4 40000 33 1 | ||
142 | |||
143 | /* IDSEL 0x11 */ | ||
144 | 08800 0 0 1 40000 30 1 | ||
145 | 08800 0 0 2 40000 31 1 | ||
146 | 08800 0 0 3 40000 32 1 | ||
147 | 08800 0 0 4 40000 33 1 | ||
148 | |||
149 | /* IDSEL 0x12 (Slot 1) */ | ||
150 | 09000 0 0 1 40000 30 1 | ||
151 | 09000 0 0 2 40000 31 1 | ||
152 | 09000 0 0 3 40000 32 1 | ||
153 | 09000 0 0 4 40000 33 1 | ||
154 | |||
155 | /* IDSEL 0x13 (Slot 2) */ | ||
156 | 09800 0 0 1 40000 31 1 | ||
157 | 09800 0 0 2 40000 32 1 | ||
158 | 09800 0 0 3 40000 33 1 | ||
159 | 09800 0 0 4 40000 30 1 | ||
160 | |||
161 | /* IDSEL 0x14 (Slot 3) */ | ||
162 | 0a000 0 0 1 40000 32 1 | ||
163 | 0a000 0 0 2 40000 33 1 | ||
164 | 0a000 0 0 3 40000 30 1 | ||
165 | 0a000 0 0 4 40000 31 1 | ||
166 | |||
167 | /* IDSEL 0x15 (Slot 4) */ | ||
168 | 0a800 0 0 1 40000 33 1 | ||
169 | 0a800 0 0 2 40000 30 1 | ||
170 | 0a800 0 0 3 40000 31 1 | ||
171 | 0a800 0 0 4 40000 32 1 | ||
172 | |||
173 | /* Bus 1 (Tundra Bridge) */ | ||
174 | /* IDSEL 0x12 (ISA bridge) */ | ||
175 | 19000 0 0 1 40000 30 1 | ||
176 | 19000 0 0 2 40000 31 1 | ||
177 | 19000 0 0 3 40000 32 1 | ||
178 | 19000 0 0 4 40000 33 1>; | ||
179 | interrupt-parent = <40000>; | ||
180 | interrupts = <08 2>; | ||
181 | bus-range = <0 0>; | ||
182 | ranges = <02000000 0 80000000 80000000 0 20000000 | ||
183 | 01000000 0 00000000 e2000000 0 00100000>; | ||
184 | clock-frequency = <3f940aa>; | ||
185 | #interrupt-cells = <1>; | ||
186 | #size-cells = <2>; | ||
187 | #address-cells = <3>; | ||
188 | reg = <8000 1000>; | ||
189 | compatible = "85xx"; | ||
190 | device_type = "pci"; | ||
191 | |||
192 | i8259@19000 { | ||
193 | clock-frequency = <0>; | ||
194 | interrupt-controller; | ||
195 | device_type = "interrupt-controller"; | ||
196 | reg = <19000 0 0 0 1>; | ||
197 | #address-cells = <0>; | ||
198 | #interrupt-cells = <2>; | ||
199 | built-in; | ||
200 | compatible = "chrp,iic"; | ||
201 | big-endian; | ||
202 | interrupts = <1>; | ||
203 | interrupt-parent = <8000>; | ||
204 | }; | ||
205 | }; | ||
206 | |||
207 | pci@9000 { | ||
208 | linux,phandle = <9000>; | ||
209 | interrupt-map-mask = <f800 0 0 7>; | ||
210 | interrupt-map = < | ||
211 | |||
212 | /* IDSEL 0x15 */ | ||
213 | a800 0 0 1 40000 3b 1 | ||
214 | a800 0 0 2 40000 3b 1 | ||
215 | a800 0 0 3 40000 3b 1 | ||
216 | a800 0 0 4 40000 3b 1>; | ||
217 | interrupt-parent = <40000>; | ||
218 | interrupts = <09 2>; | ||
219 | bus-range = <0 0>; | ||
220 | ranges = <02000000 0 a0000000 a0000000 0 20000000 | ||
221 | 01000000 0 00000000 e3000000 0 00100000>; | ||
222 | clock-frequency = <3f940aa>; | ||
223 | #interrupt-cells = <1>; | ||
224 | #size-cells = <2>; | ||
225 | #address-cells = <3>; | ||
226 | reg = <9000 1000>; | ||
227 | compatible = "85xx"; | ||
228 | device_type = "pci"; | ||
229 | }; | ||
230 | |||
231 | pic@40000 { | ||
232 | linux,phandle = <40000>; | ||
233 | clock-frequency = <0>; | ||
234 | interrupt-controller; | ||
235 | #address-cells = <0>; | ||
236 | #interrupt-cells = <2>; | ||
237 | reg = <40000 40000>; | ||
238 | built-in; | ||
239 | compatible = "chrp,open-pic"; | ||
240 | device_type = "open-pic"; | ||
241 | big-endian; | ||
242 | }; | ||
243 | }; | ||
244 | }; | ||
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c index 359ab89748e0..40a39291861f 100644 --- a/arch/powerpc/kernel/legacy_serial.c +++ b/arch/powerpc/kernel/legacy_serial.c | |||
@@ -115,6 +115,7 @@ static int __init add_legacy_soc_port(struct device_node *np, | |||
115 | u64 addr; | 115 | u64 addr; |
116 | u32 *addrp; | 116 | u32 *addrp; |
117 | upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; | 117 | upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; |
118 | struct device_node *tsi = of_get_parent(np); | ||
118 | 119 | ||
119 | /* We only support ports that have a clock frequency properly | 120 | /* We only support ports that have a clock frequency properly |
120 | * encoded in the device-tree. | 121 | * encoded in the device-tree. |
@@ -134,7 +135,10 @@ static int __init add_legacy_soc_port(struct device_node *np, | |||
134 | /* Add port, irq will be dealt with later. We passed a translated | 135 | /* Add port, irq will be dealt with later. We passed a translated |
135 | * IO port value. It will be fixed up later along with the irq | 136 | * IO port value. It will be fixed up later along with the irq |
136 | */ | 137 | */ |
137 | return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags, 0); | 138 | if (tsi && !strcmp(tsi->type, "tsi-bridge")) |
139 | return add_legacy_port(np, -1, UPIO_TSI, addr, addr, NO_IRQ, flags, 0); | ||
140 | else | ||
141 | return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags, 0); | ||
138 | } | 142 | } |
139 | 143 | ||
140 | static int __init add_legacy_isa_port(struct device_node *np, | 144 | static int __init add_legacy_isa_port(struct device_node *np, |
@@ -464,7 +468,7 @@ static int __init serial_dev_init(void) | |||
464 | fixup_port_irq(i, np, port); | 468 | fixup_port_irq(i, np, port); |
465 | if (port->iotype == UPIO_PORT) | 469 | if (port->iotype == UPIO_PORT) |
466 | fixup_port_pio(i, np, port); | 470 | fixup_port_pio(i, np, port); |
467 | if (port->iotype == UPIO_MEM) | 471 | if ((port->iotype == UPIO_MEM) || (port->iotype == UPIO_TSI)) |
468 | fixup_port_mmio(i, np, port); | 472 | fixup_port_mmio(i, np, port); |
469 | } | 473 | } |
470 | 474 | ||
diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c index 6a7e997c401d..11052c212ad5 100644 --- a/arch/powerpc/kernel/prom_parse.c +++ b/arch/powerpc/kernel/prom_parse.c | |||
@@ -598,11 +598,6 @@ static struct device_node *of_irq_find_parent(struct device_node *child) | |||
598 | return p; | 598 | return p; |
599 | } | 599 | } |
600 | 600 | ||
601 | static u8 of_irq_pci_swizzle(u8 slot, u8 pin) | ||
602 | { | ||
603 | return (((pin - 1) + slot) % 4) + 1; | ||
604 | } | ||
605 | |||
606 | /* This doesn't need to be called if you don't have any special workaround | 601 | /* This doesn't need to be called if you don't have any special workaround |
607 | * flags to pass | 602 | * flags to pass |
608 | */ | 603 | */ |
@@ -891,6 +886,12 @@ int of_irq_map_one(struct device_node *device, int index, struct of_irq *out_irq | |||
891 | } | 886 | } |
892 | EXPORT_SYMBOL_GPL(of_irq_map_one); | 887 | EXPORT_SYMBOL_GPL(of_irq_map_one); |
893 | 888 | ||
889 | #ifdef CONFIG_PCI | ||
890 | static u8 of_irq_pci_swizzle(u8 slot, u8 pin) | ||
891 | { | ||
892 | return (((pin - 1) + slot) % 4) + 1; | ||
893 | } | ||
894 | |||
894 | int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq) | 895 | int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq) |
895 | { | 896 | { |
896 | struct device_node *dn, *ppnode; | 897 | struct device_node *dn, *ppnode; |
@@ -967,4 +968,4 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq) | |||
967 | return of_irq_map_raw(ppnode, &lspec, laddr, out_irq); | 968 | return of_irq_map_raw(ppnode, &lspec, laddr, out_irq); |
968 | } | 969 | } |
969 | EXPORT_SYMBOL_GPL(of_irq_map_pci); | 970 | EXPORT_SYMBOL_GPL(of_irq_map_pci); |
970 | 971 | #endif /* CONFIG_PCI */ | |
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 774c0a3c5019..18e59e43d2b3 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c | |||
@@ -417,7 +417,7 @@ static __inline__ void timer_check_rtc(void) | |||
417 | /* | 417 | /* |
418 | * This version of gettimeofday has microsecond resolution. | 418 | * This version of gettimeofday has microsecond resolution. |
419 | */ | 419 | */ |
420 | static inline void __do_gettimeofday(struct timeval *tv, u64 tb_val) | 420 | static inline void __do_gettimeofday(struct timeval *tv) |
421 | { | 421 | { |
422 | unsigned long sec, usec; | 422 | unsigned long sec, usec; |
423 | u64 tb_ticks, xsec; | 423 | u64 tb_ticks, xsec; |
@@ -431,7 +431,12 @@ static inline void __do_gettimeofday(struct timeval *tv, u64 tb_val) | |||
431 | * without a divide (and in fact, without a multiply) | 431 | * without a divide (and in fact, without a multiply) |
432 | */ | 432 | */ |
433 | temp_varp = do_gtod.varp; | 433 | temp_varp = do_gtod.varp; |
434 | tb_ticks = tb_val - temp_varp->tb_orig_stamp; | 434 | |
435 | /* Sampling the time base must be done after loading | ||
436 | * do_gtod.varp in order to avoid racing with update_gtod. | ||
437 | */ | ||
438 | data_barrier(temp_varp); | ||
439 | tb_ticks = get_tb() - temp_varp->tb_orig_stamp; | ||
435 | temp_tb_to_xs = temp_varp->tb_to_xs; | 440 | temp_tb_to_xs = temp_varp->tb_to_xs; |
436 | temp_stamp_xsec = temp_varp->stamp_xsec; | 441 | temp_stamp_xsec = temp_varp->stamp_xsec; |
437 | xsec = temp_stamp_xsec + mulhdu(tb_ticks, temp_tb_to_xs); | 442 | xsec = temp_stamp_xsec + mulhdu(tb_ticks, temp_tb_to_xs); |
@@ -464,7 +469,7 @@ void do_gettimeofday(struct timeval *tv) | |||
464 | tv->tv_usec = usec; | 469 | tv->tv_usec = usec; |
465 | return; | 470 | return; |
466 | } | 471 | } |
467 | __do_gettimeofday(tv, get_tb()); | 472 | __do_gettimeofday(tv); |
468 | } | 473 | } |
469 | 474 | ||
470 | EXPORT_SYMBOL(do_gettimeofday); | 475 | EXPORT_SYMBOL(do_gettimeofday); |
@@ -650,6 +655,7 @@ void timer_interrupt(struct pt_regs * regs) | |||
650 | int next_dec; | 655 | int next_dec; |
651 | int cpu = smp_processor_id(); | 656 | int cpu = smp_processor_id(); |
652 | unsigned long ticks; | 657 | unsigned long ticks; |
658 | u64 tb_next_jiffy; | ||
653 | 659 | ||
654 | #ifdef CONFIG_PPC32 | 660 | #ifdef CONFIG_PPC32 |
655 | if (atomic_read(&ppc_n_lost_interrupts) != 0) | 661 | if (atomic_read(&ppc_n_lost_interrupts) != 0) |
@@ -691,11 +697,14 @@ void timer_interrupt(struct pt_regs * regs) | |||
691 | continue; | 697 | continue; |
692 | 698 | ||
693 | write_seqlock(&xtime_lock); | 699 | write_seqlock(&xtime_lock); |
694 | tb_last_jiffy += tb_ticks_per_jiffy; | 700 | tb_next_jiffy = tb_last_jiffy + tb_ticks_per_jiffy; |
695 | tb_last_stamp = per_cpu(last_jiffy, cpu); | 701 | if (per_cpu(last_jiffy, cpu) >= tb_next_jiffy) { |
696 | do_timer(regs); | 702 | tb_last_jiffy = tb_next_jiffy; |
697 | timer_recalc_offset(tb_last_jiffy); | 703 | tb_last_stamp = per_cpu(last_jiffy, cpu); |
698 | timer_check_rtc(); | 704 | do_timer(regs); |
705 | timer_recalc_offset(tb_last_jiffy); | ||
706 | timer_check_rtc(); | ||
707 | } | ||
699 | write_sequnlock(&xtime_lock); | 708 | write_sequnlock(&xtime_lock); |
700 | } | 709 | } |
701 | 710 | ||
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index e4d1713e8aea..9b352bd0a460 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c | |||
@@ -585,14 +585,14 @@ static void parse_fpe(struct pt_regs *regs) | |||
585 | #define INST_MFSPR_PVR_MASK 0xfc1fffff | 585 | #define INST_MFSPR_PVR_MASK 0xfc1fffff |
586 | 586 | ||
587 | #define INST_DCBA 0x7c0005ec | 587 | #define INST_DCBA 0x7c0005ec |
588 | #define INST_DCBA_MASK 0x7c0007fe | 588 | #define INST_DCBA_MASK 0xfc0007fe |
589 | 589 | ||
590 | #define INST_MCRXR 0x7c000400 | 590 | #define INST_MCRXR 0x7c000400 |
591 | #define INST_MCRXR_MASK 0x7c0007fe | 591 | #define INST_MCRXR_MASK 0xfc0007fe |
592 | 592 | ||
593 | #define INST_STRING 0x7c00042a | 593 | #define INST_STRING 0x7c00042a |
594 | #define INST_STRING_MASK 0x7c0007fe | 594 | #define INST_STRING_MASK 0xfc0007fe |
595 | #define INST_STRING_GEN_MASK 0x7c00067e | 595 | #define INST_STRING_GEN_MASK 0xfc00067e |
596 | #define INST_LSWI 0x7c0004aa | 596 | #define INST_LSWI 0x7c0004aa |
597 | #define INST_LSWX 0x7c00042a | 597 | #define INST_LSWX 0x7c00042a |
598 | #define INST_STSWI 0x7c0005aa | 598 | #define INST_STSWI 0x7c0005aa |
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c index 266b8b2ceac9..5615acc29527 100644 --- a/arch/powerpc/mm/hugetlbpage.c +++ b/arch/powerpc/mm/hugetlbpage.c | |||
@@ -153,7 +153,7 @@ static void free_hugepte_range(struct mmu_gather *tlb, hugepd_t *hpdp) | |||
153 | hpdp->pd = 0; | 153 | hpdp->pd = 0; |
154 | tlb->need_flush = 1; | 154 | tlb->need_flush = 1; |
155 | pgtable_free_tlb(tlb, pgtable_free_cache(hugepte, HUGEPTE_CACHE_NUM, | 155 | pgtable_free_tlb(tlb, pgtable_free_cache(hugepte, HUGEPTE_CACHE_NUM, |
156 | HUGEPTE_TABLE_SIZE-1)); | 156 | PGF_CACHENUM_MASK)); |
157 | } | 157 | } |
158 | 158 | ||
159 | #ifdef CONFIG_PPC_64K_PAGES | 159 | #ifdef CONFIG_PPC_64K_PAGES |
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 454fc53289ab..c3268d9877e4 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig | |||
@@ -14,7 +14,6 @@ config MPC8540_ADS | |||
14 | config MPC85xx_CDS | 14 | config MPC85xx_CDS |
15 | bool "Freescale MPC85xx CDS" | 15 | bool "Freescale MPC85xx CDS" |
16 | select DEFAULT_UIMAGE | 16 | select DEFAULT_UIMAGE |
17 | select PPC_I8259 if PCI | ||
18 | help | 17 | help |
19 | This option enables support for the MPC85xx CDS board | 18 | This option enables support for the MPC85xx CDS board |
20 | 19 | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c index 06a497676c99..9d2acfbbeccd 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c | |||
@@ -37,79 +37,7 @@ unsigned long isa_io_base = 0; | |||
37 | unsigned long isa_mem_base = 0; | 37 | unsigned long isa_mem_base = 0; |
38 | #endif | 38 | #endif |
39 | 39 | ||
40 | /* | ||
41 | * Internal interrupts are all Level Sensitive, and Positive Polarity | ||
42 | * | ||
43 | * Note: Likely, this table and the following function should be | ||
44 | * obtained and derived from the OF Device Tree. | ||
45 | */ | ||
46 | static u_char mpc85xx_ads_openpic_initsenses[] __initdata = { | ||
47 | MPC85XX_INTERNAL_IRQ_SENSES, | ||
48 | 0x0, /* External 0: */ | ||
49 | #if defined(CONFIG_PCI) | ||
50 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */ | ||
51 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */ | ||
52 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */ | ||
53 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */ | ||
54 | #else | ||
55 | 0x0, /* External 1: */ | ||
56 | 0x0, /* External 2: */ | ||
57 | 0x0, /* External 3: */ | ||
58 | 0x0, /* External 4: */ | ||
59 | #endif | ||
60 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */ | ||
61 | 0x0, /* External 6: */ | ||
62 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */ | ||
63 | 0x0, /* External 8: */ | ||
64 | 0x0, /* External 9: */ | ||
65 | 0x0, /* External 10: */ | ||
66 | 0x0, /* External 11: */ | ||
67 | }; | ||
68 | |||
69 | #ifdef CONFIG_PCI | 40 | #ifdef CONFIG_PCI |
70 | /* | ||
71 | * interrupt routing | ||
72 | */ | ||
73 | |||
74 | int | ||
75 | mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | ||
76 | { | ||
77 | static char pci_irq_table[][4] = | ||
78 | /* | ||
79 | * This is little evil, but works around the fact | ||
80 | * that revA boards have IDSEL starting at 18 | ||
81 | * and others boards (older) start at 12 | ||
82 | * | ||
83 | * PCI IDSEL/INTPIN->INTLINE | ||
84 | * A B C D | ||
85 | */ | ||
86 | { | ||
87 | {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */ | ||
88 | {PIRQD, PIRQA, PIRQB, PIRQC}, | ||
89 | {PIRQC, PIRQD, PIRQA, PIRQB}, | ||
90 | {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */ | ||
91 | {0, 0, 0, 0}, /* -- */ | ||
92 | {0, 0, 0, 0}, /* -- */ | ||
93 | {0, 0, 0, 0}, /* -- */ | ||
94 | {0, 0, 0, 0}, /* -- */ | ||
95 | {0, 0, 0, 0}, /* -- */ | ||
96 | {0, 0, 0, 0}, /* -- */ | ||
97 | {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */ | ||
98 | {PIRQD, PIRQA, PIRQB, PIRQC}, | ||
99 | {PIRQC, PIRQD, PIRQA, PIRQB}, | ||
100 | {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */ | ||
101 | {0, 0, 0, 0}, /* -- */ | ||
102 | {0, 0, 0, 0}, /* -- */ | ||
103 | {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */ | ||
104 | {PIRQD, PIRQA, PIRQB, PIRQC}, | ||
105 | {PIRQC, PIRQD, PIRQA, PIRQB}, | ||
106 | {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */ | ||
107 | }; | ||
108 | |||
109 | const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4; | ||
110 | return PCI_IRQ_TABLE_LOOKUP; | ||
111 | } | ||
112 | |||
113 | int | 41 | int |
114 | mpc85xx_exclude_device(u_char bus, u_char devfn) | 42 | mpc85xx_exclude_device(u_char bus, u_char devfn) |
115 | { | 43 | { |
@@ -119,44 +47,63 @@ mpc85xx_exclude_device(u_char bus, u_char devfn) | |||
119 | return PCIBIOS_SUCCESSFUL; | 47 | return PCIBIOS_SUCCESSFUL; |
120 | } | 48 | } |
121 | 49 | ||
50 | void __init | ||
51 | mpc85xx_pcibios_fixup(void) | ||
52 | { | ||
53 | struct pci_dev *dev = NULL; | ||
54 | |||
55 | for_each_pci_dev(dev) | ||
56 | pci_read_irq_line(dev); | ||
57 | } | ||
122 | #endif /* CONFIG_PCI */ | 58 | #endif /* CONFIG_PCI */ |
123 | 59 | ||
124 | 60 | ||
125 | void __init mpc85xx_ads_pic_init(void) | 61 | void __init mpc85xx_ads_pic_init(void) |
126 | { | 62 | { |
127 | struct mpic *mpic1; | 63 | struct mpic *mpic; |
128 | phys_addr_t OpenPIC_PAddr; | 64 | struct resource r; |
129 | 65 | struct device_node *np = NULL; | |
130 | /* Determine the Physical Address of the OpenPIC regs */ | 66 | |
131 | OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET; | 67 | np = of_find_node_by_type(np, "open-pic"); |
132 | 68 | ||
133 | mpic1 = mpic_alloc(OpenPIC_PAddr, | 69 | if (np == NULL) { |
134 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, | 70 | printk(KERN_ERR "Could not find open-pic node\n"); |
135 | 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250, | 71 | return; |
136 | mpc85xx_ads_openpic_initsenses, | 72 | } |
137 | sizeof(mpc85xx_ads_openpic_initsenses), | 73 | |
138 | " OpenPIC "); | 74 | if(of_address_to_resource(np, 0, &r)) { |
139 | BUG_ON(mpic1 == NULL); | 75 | printk(KERN_ERR "Could not map mpic register space\n"); |
140 | mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200); | 76 | of_node_put(np); |
141 | mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280); | 77 | return; |
142 | mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300); | 78 | } |
143 | mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380); | 79 | |
144 | mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400); | 80 | mpic = mpic_alloc(np, r.start, |
145 | mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480); | 81 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, |
146 | mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500); | 82 | 4, 0, " OpenPIC "); |
147 | mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580); | 83 | BUG_ON(mpic == NULL); |
148 | 84 | of_node_put(np); | |
149 | /* dummy mappings to get to 48 */ | 85 | |
150 | mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600); | 86 | mpic_assign_isu(mpic, 0, r.start + 0x10200); |
151 | mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680); | 87 | mpic_assign_isu(mpic, 1, r.start + 0x10280); |
152 | mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700); | 88 | mpic_assign_isu(mpic, 2, r.start + 0x10300); |
153 | mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780); | 89 | mpic_assign_isu(mpic, 3, r.start + 0x10380); |
154 | 90 | mpic_assign_isu(mpic, 4, r.start + 0x10400); | |
155 | /* External ints */ | 91 | mpic_assign_isu(mpic, 5, r.start + 0x10480); |
156 | mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000); | 92 | mpic_assign_isu(mpic, 6, r.start + 0x10500); |
157 | mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080); | 93 | mpic_assign_isu(mpic, 7, r.start + 0x10580); |
158 | mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100); | 94 | |
159 | mpic_init(mpic1); | 95 | /* Unused on this platform (leave room for 8548) */ |
96 | mpic_assign_isu(mpic, 8, r.start + 0x10600); | ||
97 | mpic_assign_isu(mpic, 9, r.start + 0x10680); | ||
98 | mpic_assign_isu(mpic, 10, r.start + 0x10700); | ||
99 | mpic_assign_isu(mpic, 11, r.start + 0x10780); | ||
100 | |||
101 | /* External Interrupts */ | ||
102 | mpic_assign_isu(mpic, 12, r.start + 0x10000); | ||
103 | mpic_assign_isu(mpic, 13, r.start + 0x10080); | ||
104 | mpic_assign_isu(mpic, 14, r.start + 0x10100); | ||
105 | |||
106 | mpic_init(mpic); | ||
160 | } | 107 | } |
161 | 108 | ||
162 | /* | 109 | /* |
@@ -165,7 +112,9 @@ void __init mpc85xx_ads_pic_init(void) | |||
165 | static void __init mpc85xx_ads_setup_arch(void) | 112 | static void __init mpc85xx_ads_setup_arch(void) |
166 | { | 113 | { |
167 | struct device_node *cpu; | 114 | struct device_node *cpu; |
115 | #ifdef CONFIG_PCI | ||
168 | struct device_node *np; | 116 | struct device_node *np; |
117 | #endif | ||
169 | 118 | ||
170 | if (ppc_md.progress) | 119 | if (ppc_md.progress) |
171 | ppc_md.progress("mpc85xx_ads_setup_arch()", 0); | 120 | ppc_md.progress("mpc85xx_ads_setup_arch()", 0); |
@@ -186,8 +135,7 @@ static void __init mpc85xx_ads_setup_arch(void) | |||
186 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) | 135 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) |
187 | add_bridge(np); | 136 | add_bridge(np); |
188 | 137 | ||
189 | ppc_md.pci_swizzle = common_swizzle; | 138 | ppc_md.pcibios_fixup = mpc85xx_pcibios_fixup; |
190 | ppc_md.pci_map_irq = mpc85xx_map_irq; | ||
191 | ppc_md.pci_exclude_device = mpc85xx_exclude_device; | 139 | ppc_md.pci_exclude_device = mpc85xx_exclude_device; |
192 | #endif | 140 | #endif |
193 | 141 | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 18e6e11f7020..1d357d32a29f 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c | |||
@@ -57,94 +57,8 @@ unsigned long isa_mem_base = 0; | |||
57 | static int cds_pci_slot = 2; | 57 | static int cds_pci_slot = 2; |
58 | static volatile u8 *cadmus; | 58 | static volatile u8 *cadmus; |
59 | 59 | ||
60 | /* | ||
61 | * Internal interrupts are all Level Sensitive, and Positive Polarity | ||
62 | * | ||
63 | * Note: Likely, this table and the following function should be | ||
64 | * obtained and derived from the OF Device Tree. | ||
65 | */ | ||
66 | static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { | ||
67 | MPC85XX_INTERNAL_IRQ_SENSES, | ||
68 | #if defined(CONFIG_PCI) | ||
69 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Ext 0: PCI slot 0 */ | ||
70 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 1 */ | ||
71 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 2 */ | ||
72 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 3 */ | ||
73 | #else | ||
74 | 0x0, /* External 0: */ | ||
75 | 0x0, /* External 1: */ | ||
76 | 0x0, /* External 2: */ | ||
77 | 0x0, /* External 3: */ | ||
78 | #endif | ||
79 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */ | ||
80 | 0x0, /* External 6: */ | ||
81 | 0x0, /* External 7: */ | ||
82 | 0x0, /* External 8: */ | ||
83 | 0x0, /* External 9: */ | ||
84 | 0x0, /* External 10: */ | ||
85 | #ifdef CONFIG_PCI | ||
86 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 11: PCI2 slot 0 */ | ||
87 | #else | ||
88 | 0x0, /* External 11: */ | ||
89 | #endif | ||
90 | }; | ||
91 | |||
92 | 60 | ||
93 | #ifdef CONFIG_PCI | 61 | #ifdef CONFIG_PCI |
94 | /* | ||
95 | * interrupt routing | ||
96 | */ | ||
97 | int | ||
98 | mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | ||
99 | { | ||
100 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); | ||
101 | |||
102 | if (!hose->index) | ||
103 | { | ||
104 | /* Handle PCI1 interrupts */ | ||
105 | char pci_irq_table[][4] = | ||
106 | /* | ||
107 | * PCI IDSEL/INTPIN->INTLINE | ||
108 | * A B C D | ||
109 | */ | ||
110 | |||
111 | /* Note IRQ assignment for slots is based on which slot the elysium is | ||
112 | * in -- in this setup elysium is in slot #2 (this PIRQA as first | ||
113 | * interrupt on slot */ | ||
114 | { | ||
115 | { 0, 1, 2, 3 }, /* 16 - PMC */ | ||
116 | { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */ | ||
117 | { 0, 1, 2, 3 }, /* 18 - Slot 1 */ | ||
118 | { 1, 2, 3, 0 }, /* 19 - Slot 2 */ | ||
119 | { 2, 3, 0, 1 }, /* 20 - Slot 3 */ | ||
120 | { 3, 0, 1, 2 }, /* 21 - Slot 4 */ | ||
121 | }; | ||
122 | |||
123 | const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4; | ||
124 | int i, j; | ||
125 | |||
126 | for (i = 0; i < 6; i++) | ||
127 | for (j = 0; j < 4; j++) | ||
128 | pci_irq_table[i][j] = | ||
129 | ((pci_irq_table[i][j] + 5 - | ||
130 | cds_pci_slot) & 0x3) + PIRQ0A; | ||
131 | |||
132 | return PCI_IRQ_TABLE_LOOKUP; | ||
133 | } else { | ||
134 | /* Handle PCI2 interrupts (if we have one) */ | ||
135 | char pci_irq_table[][4] = | ||
136 | { | ||
137 | /* | ||
138 | * We only have one slot and one interrupt | ||
139 | * going to PIRQA - PIRQD */ | ||
140 | { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */ | ||
141 | }; | ||
142 | |||
143 | const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4; | ||
144 | |||
145 | return PCI_IRQ_TABLE_LOOKUP; | ||
146 | } | ||
147 | } | ||
148 | 62 | ||
149 | #define ARCADIA_HOST_BRIDGE_IDSEL 17 | 63 | #define ARCADIA_HOST_BRIDGE_IDSEL 17 |
150 | #define ARCADIA_2ND_BRIDGE_IDSEL 3 | 64 | #define ARCADIA_2ND_BRIDGE_IDSEL 3 |
@@ -210,50 +124,104 @@ mpc85xx_cds_pcibios_fixup(void) | |||
210 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); | 124 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); |
211 | pci_dev_put(dev); | 125 | pci_dev_put(dev); |
212 | } | 126 | } |
127 | |||
128 | /* Now map all the PCI irqs */ | ||
129 | dev = NULL; | ||
130 | for_each_pci_dev(dev) | ||
131 | pci_read_irq_line(dev); | ||
132 | } | ||
133 | |||
134 | #ifdef CONFIG_PPC_I8259 | ||
135 | #warning The i8259 PIC support is currently broken | ||
136 | static void mpc85xx_8259_cascade(unsigned int irq, struct | ||
137 | irq_desc *desc, struct pt_regs *regs) | ||
138 | { | ||
139 | unsigned int cascade_irq = i8259_irq(regs); | ||
140 | |||
141 | if (cascade_irq != NO_IRQ) | ||
142 | generic_handle_irq(cascade_irq, regs); | ||
143 | |||
144 | desc->chip->eoi(irq); | ||
213 | } | 145 | } |
146 | #endif /* PPC_I8259 */ | ||
214 | #endif /* CONFIG_PCI */ | 147 | #endif /* CONFIG_PCI */ |
215 | 148 | ||
216 | void __init mpc85xx_cds_pic_init(void) | 149 | void __init mpc85xx_cds_pic_init(void) |
217 | { | 150 | { |
218 | struct mpic *mpic1; | 151 | struct mpic *mpic; |
219 | phys_addr_t OpenPIC_PAddr; | 152 | struct resource r; |
153 | struct device_node *np = NULL; | ||
154 | struct device_node *cascade_node = NULL; | ||
155 | int cascade_irq; | ||
220 | 156 | ||
221 | /* Determine the Physical Address of the OpenPIC regs */ | 157 | np = of_find_node_by_type(np, "open-pic"); |
222 | OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET; | 158 | |
159 | if (np == NULL) { | ||
160 | printk(KERN_ERR "Could not find open-pic node\n"); | ||
161 | return; | ||
162 | } | ||
223 | 163 | ||
224 | mpic1 = mpic_alloc(OpenPIC_PAddr, | 164 | if (of_address_to_resource(np, 0, &r)) { |
165 | printk(KERN_ERR "Failed to map mpic register space\n"); | ||
166 | of_node_put(np); | ||
167 | return; | ||
168 | } | ||
169 | |||
170 | mpic = mpic_alloc(np, r.start, | ||
225 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, | 171 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, |
226 | 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250, | 172 | 4, 0, " OpenPIC "); |
227 | mpc85xx_cds_openpic_initsenses, | 173 | BUG_ON(mpic == NULL); |
228 | sizeof(mpc85xx_cds_openpic_initsenses), " OpenPIC "); | 174 | |
229 | BUG_ON(mpic1 == NULL); | 175 | /* Return the mpic node */ |
230 | mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200); | 176 | of_node_put(np); |
231 | mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280); | 177 | |
232 | mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300); | 178 | mpic_assign_isu(mpic, 0, r.start + 0x10200); |
233 | mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380); | 179 | mpic_assign_isu(mpic, 1, r.start + 0x10280); |
234 | mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400); | 180 | mpic_assign_isu(mpic, 2, r.start + 0x10300); |
235 | mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480); | 181 | mpic_assign_isu(mpic, 3, r.start + 0x10380); |
236 | mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500); | 182 | mpic_assign_isu(mpic, 4, r.start + 0x10400); |
237 | mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580); | 183 | mpic_assign_isu(mpic, 5, r.start + 0x10480); |
238 | 184 | mpic_assign_isu(mpic, 6, r.start + 0x10500); | |
239 | /* dummy mappings to get to 48 */ | 185 | mpic_assign_isu(mpic, 7, r.start + 0x10580); |
240 | mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600); | 186 | |
241 | mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680); | 187 | /* Used only for 8548 so far, but no harm in |
242 | mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700); | 188 | * allocating them for everyone */ |
243 | mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780); | 189 | mpic_assign_isu(mpic, 8, r.start + 0x10600); |
244 | 190 | mpic_assign_isu(mpic, 9, r.start + 0x10680); | |
245 | /* External ints */ | 191 | mpic_assign_isu(mpic, 10, r.start + 0x10700); |
246 | mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000); | 192 | mpic_assign_isu(mpic, 11, r.start + 0x10780); |
247 | mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080); | 193 | |
248 | mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100); | 194 | /* External Interrupts */ |
249 | 195 | mpic_assign_isu(mpic, 12, r.start + 0x10000); | |
250 | mpic_init(mpic1); | 196 | mpic_assign_isu(mpic, 13, r.start + 0x10080); |
197 | mpic_assign_isu(mpic, 14, r.start + 0x10100); | ||
198 | |||
199 | mpic_init(mpic); | ||
200 | |||
201 | #ifdef CONFIG_PPC_I8259 | ||
202 | /* Initialize the i8259 controller */ | ||
203 | for_each_node_by_type(np, "interrupt-controller") | ||
204 | if (device_is_compatible(np, "chrp,iic")) { | ||
205 | cascade_node = np; | ||
206 | break; | ||
207 | } | ||
208 | |||
209 | if (cascade_node == NULL) { | ||
210 | printk(KERN_DEBUG "Could not find i8259 PIC\n"); | ||
211 | return; | ||
212 | } | ||
251 | 213 | ||
252 | #ifdef CONFIG_PCI | 214 | cascade_irq = irq_of_parse_and_map(cascade_node, 0); |
253 | mpic_setup_cascade(PIRQ0A, i8259_irq_cascade, NULL); | 215 | if (cascade_irq == NO_IRQ) { |
216 | printk(KERN_ERR "Failed to map cascade interrupt\n"); | ||
217 | return; | ||
218 | } | ||
254 | 219 | ||
255 | i8259_init(0,0); | 220 | i8259_init(cascade_node, 0); |
256 | #endif | 221 | of_node_put(cascade_node); |
222 | |||
223 | set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); | ||
224 | #endif /* CONFIG_PPC_I8259 */ | ||
257 | } | 225 | } |
258 | 226 | ||
259 | 227 | ||
@@ -298,8 +266,6 @@ mpc85xx_cds_setup_arch(void) | |||
298 | add_bridge(np); | 266 | add_bridge(np); |
299 | 267 | ||
300 | ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup; | 268 | ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup; |
301 | ppc_md.pci_swizzle = common_swizzle; | ||
302 | ppc_md.pci_map_irq = mpc85xx_map_irq; | ||
303 | ppc_md.pci_exclude_device = mpc85xx_exclude_device; | 269 | ppc_md.pci_exclude_device = mpc85xx_exclude_device; |
304 | #endif | 270 | #endif |
305 | 271 | ||
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h index 5d2bcf78cef7..41e554c4af94 100644 --- a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h +++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h | |||
@@ -16,38 +16,6 @@ | |||
16 | 16 | ||
17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | 18 | ||
19 | /* PCI interrupt controller */ | ||
20 | #define PIRQA 3 | ||
21 | #define PIRQB 4 | ||
22 | #define PIRQC 5 | ||
23 | #define PIRQD 6 | ||
24 | #define PIRQ7 7 | ||
25 | #define PIRQE 9 | ||
26 | #define PIRQF 10 | ||
27 | #define PIRQG 11 | ||
28 | #define PIRQH 12 | ||
29 | |||
30 | /* PCI-Express memory map */ | ||
31 | #define MPC86XX_PCIE_LOWER_IO 0x00000000 | ||
32 | #define MPC86XX_PCIE_UPPER_IO 0x00ffffff | ||
33 | |||
34 | #define MPC86XX_PCIE_LOWER_MEM 0x80000000 | ||
35 | #define MPC86XX_PCIE_UPPER_MEM 0x9fffffff | ||
36 | |||
37 | #define MPC86XX_PCIE_IO_BASE 0xe2000000 | ||
38 | #define MPC86XX_PCIE_MEM_OFFSET 0x00000000 | ||
39 | |||
40 | #define MPC86XX_PCIE_IO_SIZE 0x01000000 | ||
41 | |||
42 | #define PCIE1_CFG_ADDR_OFFSET (0x8000) | ||
43 | #define PCIE1_CFG_DATA_OFFSET (0x8004) | ||
44 | |||
45 | #define PCIE2_CFG_ADDR_OFFSET (0x9000) | ||
46 | #define PCIE2_CFG_DATA_OFFSET (0x9004) | ||
47 | |||
48 | #define MPC86xx_PCIE_OFFSET PCIE1_CFG_ADDR_OFFSET | ||
49 | #define MPC86xx_PCIE_SIZE (0x1000) | ||
50 | |||
51 | #define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */ | 19 | #define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */ |
52 | 20 | ||
53 | #endif /* __MPC8641_HPCN_H__ */ | 21 | #endif /* __MPC8641_HPCN_H__ */ |
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c index ebae73eb0063..146da3001c67 100644 --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | |||
@@ -37,6 +37,14 @@ | |||
37 | #include "mpc86xx.h" | 37 | #include "mpc86xx.h" |
38 | #include "mpc8641_hpcn.h" | 38 | #include "mpc8641_hpcn.h" |
39 | 39 | ||
40 | #undef DEBUG | ||
41 | |||
42 | #ifdef DEBUG | ||
43 | #define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0) | ||
44 | #else | ||
45 | #define DBG(fmt...) do { } while(0) | ||
46 | #endif | ||
47 | |||
40 | #ifndef CONFIG_PCI | 48 | #ifndef CONFIG_PCI |
41 | unsigned long isa_io_base = 0; | 49 | unsigned long isa_io_base = 0; |
42 | unsigned long isa_mem_base = 0; | 50 | unsigned long isa_mem_base = 0; |
@@ -44,205 +52,215 @@ unsigned long pci_dram_offset = 0; | |||
44 | #endif | 52 | #endif |
45 | 53 | ||
46 | 54 | ||
47 | /* | 55 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc, |
48 | * Internal interrupts are all Level Sensitive, and Positive Polarity | 56 | struct pt_regs *regs) |
49 | */ | 57 | { |
50 | 58 | unsigned int cascade_irq = i8259_irq(regs); | |
51 | static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = { | 59 | if (cascade_irq != NO_IRQ) |
52 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */ | 60 | generic_handle_irq(cascade_irq, regs); |
53 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */ | 61 | desc->chip->eoi(irq); |
54 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */ | 62 | } |
55 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */ | ||
56 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */ | ||
57 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */ | ||
58 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */ | ||
59 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */ | ||
60 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCIE1 */ | ||
61 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PCIE2 */ | ||
62 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */ | ||
63 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */ | ||
64 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */ | ||
65 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */ | ||
66 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */ | ||
67 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */ | ||
68 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */ | ||
69 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */ | ||
70 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */ | ||
71 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */ | ||
72 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */ | ||
73 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */ | ||
74 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */ | ||
75 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */ | ||
76 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */ | ||
77 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */ | ||
78 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */ | ||
79 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */ | ||
80 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */ | ||
81 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */ | ||
82 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */ | ||
83 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */ | ||
84 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */ | ||
85 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */ | ||
86 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */ | ||
87 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */ | ||
88 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */ | ||
89 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */ | ||
90 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */ | ||
91 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */ | ||
92 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */ | ||
93 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */ | ||
94 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */ | ||
95 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */ | ||
96 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */ | ||
97 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */ | ||
98 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */ | ||
99 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */ | ||
100 | 0x0, /* External 0: */ | ||
101 | 0x0, /* External 1: */ | ||
102 | 0x0, /* External 2: */ | ||
103 | 0x0, /* External 3: */ | ||
104 | 0x0, /* External 4: */ | ||
105 | 0x0, /* External 5: */ | ||
106 | 0x0, /* External 6: */ | ||
107 | 0x0, /* External 7: */ | ||
108 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */ | ||
109 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */ | ||
110 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */ | ||
111 | 0x0, /* External 11: */ | ||
112 | 0x0, | ||
113 | 0x0, | ||
114 | 0x0, | ||
115 | 0x0, | ||
116 | }; | ||
117 | |||
118 | 63 | ||
119 | void __init | 64 | void __init |
120 | mpc86xx_hpcn_init_irq(void) | 65 | mpc86xx_hpcn_init_irq(void) |
121 | { | 66 | { |
122 | struct mpic *mpic1; | 67 | struct mpic *mpic1; |
68 | struct device_node *np, *cascade_node = NULL; | ||
69 | int cascade_irq; | ||
123 | phys_addr_t openpic_paddr; | 70 | phys_addr_t openpic_paddr; |
124 | 71 | ||
72 | np = of_find_node_by_type(NULL, "open-pic"); | ||
73 | if (np == NULL) | ||
74 | return; | ||
75 | |||
125 | /* Determine the Physical Address of the OpenPIC regs */ | 76 | /* Determine the Physical Address of the OpenPIC regs */ |
126 | openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET; | 77 | openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET; |
127 | 78 | ||
128 | /* Alloc mpic structure and per isu has 16 INT entries. */ | 79 | /* Alloc mpic structure and per isu has 16 INT entries. */ |
129 | mpic1 = mpic_alloc(openpic_paddr, | 80 | mpic1 = mpic_alloc(np, openpic_paddr, |
130 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, | 81 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, |
131 | 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250, | 82 | 16, NR_IRQS - 4, |
132 | mpc86xx_hpcn_openpic_initsenses, | ||
133 | sizeof(mpc86xx_hpcn_openpic_initsenses), | ||
134 | " MPIC "); | 83 | " MPIC "); |
135 | BUG_ON(mpic1 == NULL); | 84 | BUG_ON(mpic1 == NULL); |
136 | 85 | ||
86 | mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10000); | ||
87 | |||
137 | /* 48 Internal Interrupts */ | 88 | /* 48 Internal Interrupts */ |
138 | mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200); | 89 | mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10200); |
139 | mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400); | 90 | mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10400); |
140 | mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600); | 91 | mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10600); |
141 | 92 | ||
142 | /* 16 External interrupts */ | 93 | /* 16 External interrupts |
143 | mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000); | 94 | * Moving them from [0 - 15] to [64 - 79] |
95 | */ | ||
96 | mpic_assign_isu(mpic1, 4, openpic_paddr + 0x10000); | ||
144 | 97 | ||
145 | mpic_init(mpic1); | 98 | mpic_init(mpic1); |
146 | 99 | ||
147 | #ifdef CONFIG_PCI | 100 | #ifdef CONFIG_PCI |
148 | mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL); | 101 | /* Initialize i8259 controller */ |
149 | i8259_init(0, I8259_OFFSET); | 102 | for_each_node_by_type(np, "interrupt-controller") |
150 | #endif | 103 | if (device_is_compatible(np, "chrp,iic")) { |
151 | } | 104 | cascade_node = np; |
105 | break; | ||
106 | } | ||
107 | if (cascade_node == NULL) { | ||
108 | printk(KERN_DEBUG "mpc86xxhpcn: no ISA interrupt controller\n"); | ||
109 | return; | ||
110 | } | ||
152 | 111 | ||
112 | cascade_irq = irq_of_parse_and_map(cascade_node, 0); | ||
113 | if (cascade_irq == NO_IRQ) { | ||
114 | printk(KERN_ERR "mpc86xxhpcn: failed to map cascade interrupt"); | ||
115 | return; | ||
116 | } | ||
117 | DBG("mpc86xxhpcn: cascade mapped to irq %d\n", cascade_irq); | ||
153 | 118 | ||
119 | i8259_init(cascade_node, 0); | ||
120 | set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade); | ||
121 | #endif | ||
122 | } | ||
154 | 123 | ||
155 | #ifdef CONFIG_PCI | 124 | #ifdef CONFIG_PCI |
156 | /* | ||
157 | * interrupt routing | ||
158 | */ | ||
159 | 125 | ||
160 | int | 126 | enum pirq{PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH}; |
161 | mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | 127 | const unsigned char uli1575_irq_route_table[16] = { |
128 | 0, /* 0: Reserved */ | ||
129 | 0x8, /* 1: 0b1000 */ | ||
130 | 0, /* 2: Reserved */ | ||
131 | 0x2, /* 3: 0b0010 */ | ||
132 | 0x4, /* 4: 0b0100 */ | ||
133 | 0x5, /* 5: 0b0101 */ | ||
134 | 0x7, /* 6: 0b0111 */ | ||
135 | 0x6, /* 7: 0b0110 */ | ||
136 | 0, /* 8: Reserved */ | ||
137 | 0x1, /* 9: 0b0001 */ | ||
138 | 0x3, /* 10: 0b0011 */ | ||
139 | 0x9, /* 11: 0b1001 */ | ||
140 | 0xb, /* 12: 0b1011 */ | ||
141 | 0, /* 13: Reserved */ | ||
142 | 0xd, /* 14, 0b1101 */ | ||
143 | 0xf, /* 15, 0b1111 */ | ||
144 | }; | ||
145 | |||
146 | static int __devinit | ||
147 | get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin) | ||
162 | { | 148 | { |
163 | static char pci_irq_table[][4] = { | 149 | struct of_irq oirq; |
164 | /* | 150 | u32 laddr[3]; |
165 | * PCI IDSEL/INTPIN->INTLINE | 151 | struct device_node *hosenode = hose ? hose->arch_data : NULL; |
166 | * A B C D | 152 | |
167 | */ | 153 | if (!hosenode) return -EINVAL; |
168 | {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */ | 154 | |
169 | {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */ | 155 | laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8); |
170 | {0, 0, 0, 0}, /* IDSEL 19 */ | 156 | laddr[1] = laddr[2] = 0; |
171 | {0, 0, 0, 0}, /* IDSEL 20 */ | 157 | of_irq_map_raw(hosenode, &pin, laddr, &oirq); |
172 | {0, 0, 0, 0}, /* IDSEL 21 */ | 158 | DBG("mpc86xx_hpcn: pci irq addr %x, slot %d, pin %d, irq %d\n", |
173 | {0, 0, 0, 0}, /* IDSEL 22 */ | 159 | laddr[0], slot, pin, oirq.specifier[0]); |
174 | {0, 0, 0, 0}, /* IDSEL 23 */ | 160 | return oirq.specifier[0]; |
175 | {0, 0, 0, 0}, /* IDSEL 24 */ | ||
176 | {0, 0, 0, 0}, /* IDSEL 25 */ | ||
177 | {PIRQD, PIRQA, PIRQB, PIRQC}, /* IDSEL 26 -- PCI Bridge*/ | ||
178 | {PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */ | ||
179 | {PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */ | ||
180 | {PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */ | ||
181 | {PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/ | ||
182 | {PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */ | ||
183 | }; | ||
184 | |||
185 | const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4; | ||
186 | return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET; | ||
187 | } | 161 | } |
188 | 162 | ||
189 | static void __devinit quirk_ali1575(struct pci_dev *dev) | 163 | static void __devinit quirk_uli1575(struct pci_dev *dev) |
190 | { | 164 | { |
191 | unsigned short temp; | 165 | unsigned short temp; |
166 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | ||
167 | unsigned char irq2pin[16]; | ||
168 | unsigned long pirq_map_word = 0; | ||
169 | u32 irq; | ||
170 | int i; | ||
192 | 171 | ||
193 | /* | 172 | /* |
194 | * ALI1575 interrupts route table setup: | 173 | * ULI1575 interrupts route setup |
174 | */ | ||
175 | memset(irq2pin, 0, 16); /* Initialize default value 0 */ | ||
176 | |||
177 | /* | ||
178 | * PIRQA -> PIRQD mapping read from OF-tree | ||
179 | * | ||
180 | * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD | ||
181 | * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA | ||
182 | */ | ||
183 | for (i = 0; i < 4; i++){ | ||
184 | irq = get_pci_irq_from_of(hose, 17, i + 1); | ||
185 | if (irq > 0 && irq < 16) | ||
186 | irq2pin[irq] = PIRQA + i; | ||
187 | else | ||
188 | printk(KERN_WARNING "ULI1575 device" | ||
189 | "(slot %d, pin %d) irq %d is invalid.\n", | ||
190 | 17, i, irq); | ||
191 | } | ||
192 | |||
193 | /* | ||
194 | * PIRQE -> PIRQF mapping set manually | ||
195 | * | 195 | * |
196 | * IRQ pin IRQ# | 196 | * IRQ pin IRQ# |
197 | * PIRQA ---- 3 | ||
198 | * PIRQB ---- 4 | ||
199 | * PIRQC ---- 5 | ||
200 | * PIRQD ---- 6 | ||
201 | * PIRQE ---- 9 | 197 | * PIRQE ---- 9 |
202 | * PIRQF ---- 10 | 198 | * PIRQF ---- 10 |
203 | * PIRQG ---- 11 | 199 | * PIRQG ---- 11 |
204 | * PIRQH ---- 12 | 200 | * PIRQH ---- 12 |
205 | * | ||
206 | * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD | ||
207 | * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA | ||
208 | */ | 201 | */ |
209 | pci_write_config_dword(dev, 0x48, 0xb9317542); | 202 | for (i = 0; i < 4; i++) irq2pin[i + 9] = PIRQE + i; |
203 | |||
204 | /* Set IRQ-PIRQ Mapping to ULI1575 */ | ||
205 | for (i = 0; i < 16; i++) | ||
206 | if (irq2pin[i]) | ||
207 | pirq_map_word |= (uli1575_irq_route_table[i] & 0xf) | ||
208 | << ((irq2pin[i] - PIRQA) * 4); | ||
210 | 209 | ||
211 | /* USB 1.1 OHCI controller 1, interrupt: PIRQE */ | 210 | /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */ |
212 | pci_write_config_byte(dev, 0x86, 0x0c); | 211 | DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n", |
212 | pirq_map_word); | ||
213 | pci_write_config_dword(dev, 0x48, pirq_map_word); | ||
213 | 214 | ||
214 | /* USB 1.1 OHCI controller 2, interrupt: PIRQF */ | 215 | #define ULI1575_SET_DEV_IRQ(slot, pin, reg) \ |
215 | pci_write_config_byte(dev, 0x87, 0x0d); | 216 | do { \ |
217 | int irq; \ | ||
218 | irq = get_pci_irq_from_of(hose, slot, pin); \ | ||
219 | if (irq > 0 && irq < 16) \ | ||
220 | pci_write_config_byte(dev, reg, irq2pin[irq]); \ | ||
221 | else \ | ||
222 | printk(KERN_WARNING "ULI1575 device" \ | ||
223 | "(slot %d, pin %d) irq %d is invalid.\n", \ | ||
224 | slot, pin, irq); \ | ||
225 | } while(0) | ||
216 | 226 | ||
217 | /* USB 1.1 OHCI controller 3, interrupt: PIRQH */ | 227 | /* USB 1.1 OHCI controller 1, slot 28, pin 1 */ |
218 | pci_write_config_byte(dev, 0x88, 0x0f); | 228 | ULI1575_SET_DEV_IRQ(28, 1, 0x86); |
219 | 229 | ||
220 | /* USB 2.0 controller, interrupt: PIRQ7 */ | 230 | /* USB 1.1 OHCI controller 2, slot 28, pin 2 */ |
221 | pci_write_config_byte(dev, 0x74, 0x06); | 231 | ULI1575_SET_DEV_IRQ(28, 2, 0x87); |
222 | 232 | ||
223 | /* Audio controller, interrupt: PIRQE */ | 233 | /* USB 1.1 OHCI controller 3, slot 28, pin 3 */ |
224 | pci_write_config_byte(dev, 0x8a, 0x0c); | 234 | ULI1575_SET_DEV_IRQ(28, 3, 0x88); |
225 | 235 | ||
226 | /* Modem controller, interrupt: PIRQF */ | 236 | /* USB 2.0 controller, slot 28, pin 4 */ |
227 | pci_write_config_byte(dev, 0x8b, 0x0d); | 237 | irq = get_pci_irq_from_of(hose, 28, 4); |
238 | if (irq >= 0 && irq <=15) | ||
239 | pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]); | ||
228 | 240 | ||
229 | /* HD audio controller, interrupt: PIRQG */ | 241 | /* Audio controller, slot 29, pin 1 */ |
230 | pci_write_config_byte(dev, 0x8c, 0x0e); | 242 | ULI1575_SET_DEV_IRQ(29, 1, 0x8a); |
231 | 243 | ||
232 | /* Serial ATA interrupt: PIRQD */ | 244 | /* Modem controller, slot 29, pin 2 */ |
233 | pci_write_config_byte(dev, 0x8d, 0x0b); | 245 | ULI1575_SET_DEV_IRQ(29, 2, 0x8b); |
234 | 246 | ||
235 | /* SMB interrupt: PIRQH */ | 247 | /* HD audio controller, slot 29, pin 3 */ |
236 | pci_write_config_byte(dev, 0x8e, 0x0f); | 248 | ULI1575_SET_DEV_IRQ(29, 3, 0x8c); |
237 | 249 | ||
238 | /* PMU ACPI SCI interrupt: PIRQH */ | 250 | /* SMB interrupt: slot 30, pin 1 */ |
239 | pci_write_config_byte(dev, 0x8f, 0x0f); | 251 | ULI1575_SET_DEV_IRQ(30, 1, 0x8e); |
252 | |||
253 | /* PMU ACPI SCI interrupt: slot 30, pin 2 */ | ||
254 | ULI1575_SET_DEV_IRQ(30, 2, 0x8f); | ||
255 | |||
256 | /* Serial ATA interrupt: slot 31, pin 1 */ | ||
257 | ULI1575_SET_DEV_IRQ(31, 1, 0x8d); | ||
240 | 258 | ||
241 | /* Primary PATA IDE IRQ: 14 | 259 | /* Primary PATA IDE IRQ: 14 |
242 | * Secondary PATA IDE IRQ: 15 | 260 | * Secondary PATA IDE IRQ: 15 |
243 | */ | 261 | */ |
244 | pci_write_config_byte(dev, 0x44, 0x3d); | 262 | pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]); |
245 | pci_write_config_byte(dev, 0x75, 0x0f); | 263 | pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]); |
246 | 264 | ||
247 | /* Set IRQ14 and IRQ15 to legacy IRQs */ | 265 | /* Set IRQ14 and IRQ15 to legacy IRQs */ |
248 | pci_read_config_word(dev, 0x46, &temp); | 266 | pci_read_config_word(dev, 0x46, &temp); |
@@ -264,6 +282,8 @@ static void __devinit quirk_ali1575(struct pci_dev *dev) | |||
264 | */ | 282 | */ |
265 | outb(0xfa, 0x4d0); | 283 | outb(0xfa, 0x4d0); |
266 | outb(0x1e, 0x4d1); | 284 | outb(0x1e, 0x4d1); |
285 | |||
286 | #undef ULI1575_SET_DEV_IRQ | ||
267 | } | 287 | } |
268 | 288 | ||
269 | static void __devinit quirk_uli5288(struct pci_dev *dev) | 289 | static void __devinit quirk_uli5288(struct pci_dev *dev) |
@@ -306,7 +326,7 @@ static void __devinit early_uli5249(struct pci_dev *dev) | |||
306 | dev->class |= 0x1; | 326 | dev->class |= 0x1; |
307 | } | 327 | } |
308 | 328 | ||
309 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575); | 329 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575); |
310 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); | 330 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); |
311 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); | 331 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); |
312 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); | 332 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); |
@@ -337,8 +357,6 @@ mpc86xx_hpcn_setup_arch(void) | |||
337 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) | 357 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) |
338 | add_bridge(np); | 358 | add_bridge(np); |
339 | 359 | ||
340 | ppc_md.pci_swizzle = common_swizzle; | ||
341 | ppc_md.pci_map_irq = mpc86xx_map_irq; | ||
342 | ppc_md.pci_exclude_device = mpc86xx_exclude_device; | 360 | ppc_md.pci_exclude_device = mpc86xx_exclude_device; |
343 | #endif | 361 | #endif |
344 | 362 | ||
@@ -377,6 +395,15 @@ mpc86xx_hpcn_show_cpuinfo(struct seq_file *m) | |||
377 | } | 395 | } |
378 | 396 | ||
379 | 397 | ||
398 | void __init mpc86xx_hpcn_pcibios_fixup(void) | ||
399 | { | ||
400 | struct pci_dev *dev = NULL; | ||
401 | |||
402 | for_each_pci_dev(dev) | ||
403 | pci_read_irq_line(dev); | ||
404 | } | ||
405 | |||
406 | |||
380 | /* | 407 | /* |
381 | * Called very early, device-tree isn't unflattened | 408 | * Called very early, device-tree isn't unflattened |
382 | */ | 409 | */ |
@@ -431,6 +458,7 @@ define_machine(mpc86xx_hpcn) { | |||
431 | .setup_arch = mpc86xx_hpcn_setup_arch, | 458 | .setup_arch = mpc86xx_hpcn_setup_arch, |
432 | .init_IRQ = mpc86xx_hpcn_init_irq, | 459 | .init_IRQ = mpc86xx_hpcn_init_irq, |
433 | .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo, | 460 | .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo, |
461 | .pcibios_fixup = mpc86xx_hpcn_pcibios_fixup, | ||
434 | .get_irq = mpic_get_irq, | 462 | .get_irq = mpic_get_irq, |
435 | .restart = mpc86xx_restart, | 463 | .restart = mpc86xx_restart, |
436 | .time_init = mpc86xx_time_init, | 464 | .time_init = mpc86xx_time_init, |
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c index d7a4fc7ca238..ed00ed2455dd 100644 --- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c +++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * mpc7448_hpc2.c | 2 | * mpc7448_hpc2.c |
3 | * | 3 | * |
4 | * Board setup routines for the Freescale Taiga platform | 4 | * Board setup routines for the Freescale mpc7448hpc2(taiga) platform |
5 | * | 5 | * |
6 | * Author: Jacob Pan | 6 | * Author: Jacob Pan |
7 | * jacob.pan@freescale.com | 7 | * jacob.pan@freescale.com |
@@ -12,10 +12,10 @@ | |||
12 | * | 12 | * |
13 | * Copyright 2004-2006 Freescale Semiconductor, Inc. | 13 | * Copyright 2004-2006 Freescale Semiconductor, Inc. |
14 | * | 14 | * |
15 | * This file is licensed under | 15 | * This program is free software; you can redistribute it and/or |
16 | * the terms of the GNU General Public License version 2. This program | 16 | * modify it under the terms of the GNU General Public License |
17 | * is licensed "as is" without any warranty of any kind, whether express | 17 | * as published by the Free Software Foundation; either version |
18 | * or implied. | 18 | * 2 of the License, or (at your option) any later version. |
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/config.h> | 21 | #include <linux/config.h> |
@@ -62,43 +62,8 @@ pci_dram_offset = MPC7448_HPC2_PCI_MEM_OFFSET; | |||
62 | extern int tsi108_setup_pci(struct device_node *dev); | 62 | extern int tsi108_setup_pci(struct device_node *dev); |
63 | extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); | 63 | extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); |
64 | extern void tsi108_pci_int_init(void); | 64 | extern void tsi108_pci_int_init(void); |
65 | extern int tsi108_irq_cascade(struct pt_regs *regs, void *unused); | 65 | extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc, |
66 | 66 | struct pt_regs *regs); | |
67 | /* | ||
68 | * Define all of the IRQ senses and polarities. Taken from the | ||
69 | * mpc7448hpc manual. | ||
70 | * Note: Likely, this table and the following function should be | ||
71 | * obtained and derived from the OF Device Tree. | ||
72 | */ | ||
73 | |||
74 | static u_char mpc7448_hpc2_pic_initsenses[] __initdata = { | ||
75 | /* External on-board sources */ | ||
76 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[0] XINT0 from FPGA */ | ||
77 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[1] XINT1 from FPGA */ | ||
78 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[2] PHY_INT from both GIGE */ | ||
79 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[3] RESERVED */ | ||
80 | /* Internal Tsi108/109 interrupt sources */ | ||
81 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */ | ||
82 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */ | ||
83 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */ | ||
84 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */ | ||
85 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA0 */ | ||
86 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA1 */ | ||
87 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA2 */ | ||
88 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA3 */ | ||
89 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* UART0 */ | ||
90 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* UART1 */ | ||
91 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* I2C */ | ||
92 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* GPIO */ | ||
93 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* GIGE0 */ | ||
94 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* GIGE1 */ | ||
95 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */ | ||
96 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* HLP */ | ||
97 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* SDC */ | ||
98 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Processor IF */ | ||
99 | (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */ | ||
100 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* PCI/X block */ | ||
101 | }; | ||
102 | 67 | ||
103 | int mpc7448_hpc2_exclude_device(u_char bus, u_char devfn) | 68 | int mpc7448_hpc2_exclude_device(u_char bus, u_char devfn) |
104 | { | 69 | { |
@@ -229,6 +194,8 @@ static void __init mpc7448_hpc2_init_IRQ(void) | |||
229 | { | 194 | { |
230 | struct mpic *mpic; | 195 | struct mpic *mpic; |
231 | phys_addr_t mpic_paddr = 0; | 196 | phys_addr_t mpic_paddr = 0; |
197 | unsigned int cascade_pci_irq; | ||
198 | struct device_node *tsi_pci; | ||
232 | struct device_node *tsi_pic; | 199 | struct device_node *tsi_pic; |
233 | 200 | ||
234 | tsi_pic = of_find_node_by_type(NULL, "open-pic"); | 201 | tsi_pic = of_find_node_by_type(NULL, "open-pic"); |
@@ -246,24 +213,31 @@ static void __init mpc7448_hpc2_init_IRQ(void) | |||
246 | DBG("%s: tsi108pic phys_addr = 0x%x\n", __FUNCTION__, | 213 | DBG("%s: tsi108pic phys_addr = 0x%x\n", __FUNCTION__, |
247 | (u32) mpic_paddr); | 214 | (u32) mpic_paddr); |
248 | 215 | ||
249 | mpic = mpic_alloc(mpic_paddr, | 216 | mpic = mpic_alloc(tsi_pic, mpic_paddr, |
250 | MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | | 217 | MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | |
251 | MPIC_SPV_EOI | MPIC_MOD_ID(MPIC_ID_TSI108), | 218 | MPIC_SPV_EOI | MPIC_MOD_ID(MPIC_ID_TSI108), |
252 | 0, /* num_sources used */ | 219 | 0, /* num_sources used */ |
253 | TSI108_IRQ_BASE, | ||
254 | 0, /* num_sources used */ | 220 | 0, /* num_sources used */ |
255 | NR_IRQS - 4 /* XXXX */, | 221 | "Tsi108_PIC"); |
256 | mpc7448_hpc2_pic_initsenses, | ||
257 | sizeof(mpc7448_hpc2_pic_initsenses), "Tsi108_PIC"); | ||
258 | 222 | ||
259 | BUG_ON(mpic == NULL); /* XXXX */ | 223 | BUG_ON(mpic == NULL); /* XXXX */ |
260 | |||
261 | mpic_init(mpic); | 224 | mpic_init(mpic); |
262 | mpic_setup_cascade(IRQ_TSI108_PCI, tsi108_irq_cascade, mpic); | 225 | |
226 | tsi_pci = of_find_node_by_type(NULL, "pci"); | ||
227 | if (tsi_pci == 0) { | ||
228 | printk("%s: No tsi108 pci node found !\n", __FUNCTION__); | ||
229 | return; | ||
230 | } | ||
231 | |||
232 | cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); | ||
233 | set_irq_data(cascade_pci_irq, mpic); | ||
234 | set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade); | ||
235 | |||
263 | tsi108_pci_int_init(); | 236 | tsi108_pci_int_init(); |
264 | 237 | ||
265 | /* Configure MPIC outputs to CPU0 */ | 238 | /* Configure MPIC outputs to CPU0 */ |
266 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); | 239 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); |
240 | of_node_put(tsi_pic); | ||
267 | } | 241 | } |
268 | 242 | ||
269 | void mpc7448_hpc2_show_cpuinfo(struct seq_file *m) | 243 | void mpc7448_hpc2_show_cpuinfo(struct seq_file *m) |
@@ -320,6 +294,7 @@ static int mpc7448_machine_check_exception(struct pt_regs *regs) | |||
320 | return 0; | 294 | return 0; |
321 | 295 | ||
322 | } | 296 | } |
297 | |||
323 | define_machine(mpc7448_hpc2){ | 298 | define_machine(mpc7448_hpc2){ |
324 | .name = "MPC7448 HPC2", | 299 | .name = "MPC7448 HPC2", |
325 | .probe = mpc7448_hpc2_probe, | 300 | .probe = mpc7448_hpc2_probe, |
diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c index 6a026c733f6a..9d73d0234c5d 100644 --- a/arch/powerpc/platforms/powermac/bootx_init.c +++ b/arch/powerpc/platforms/powermac/bootx_init.c | |||
@@ -411,8 +411,15 @@ static unsigned long __init bootx_flatten_dt(unsigned long start) | |||
411 | DBG("End of boot params: %x\n", mem_end); | 411 | DBG("End of boot params: %x\n", mem_end); |
412 | rsvmap[0] = mem_start; | 412 | rsvmap[0] = mem_start; |
413 | rsvmap[1] = mem_end; | 413 | rsvmap[1] = mem_end; |
414 | rsvmap[2] = 0; | 414 | if (bootx_info->ramDisk) { |
415 | rsvmap[3] = 0; | 415 | rsvmap[2] = ((unsigned long)bootx_info) + bootx_info->ramDisk; |
416 | rsvmap[3] = rsvmap[2] + bootx_info->ramDiskSize; | ||
417 | rsvmap[4] = 0; | ||
418 | rsvmap[5] = 0; | ||
419 | } else { | ||
420 | rsvmap[2] = 0; | ||
421 | rsvmap[3] = 0; | ||
422 | } | ||
416 | 423 | ||
417 | return (unsigned long)hdr; | 424 | return (unsigned long)hdr; |
418 | } | 425 | } |
@@ -543,12 +550,12 @@ void __init bootx_init(unsigned long r3, unsigned long r4) | |||
543 | */ | 550 | */ |
544 | if (bi->version < 5) { | 551 | if (bi->version < 5) { |
545 | space = bi->deviceTreeOffset + bi->deviceTreeSize; | 552 | space = bi->deviceTreeOffset + bi->deviceTreeSize; |
546 | if (bi->ramDisk) | 553 | if (bi->ramDisk >= space) |
547 | space = bi->ramDisk + bi->ramDiskSize; | 554 | space = bi->ramDisk + bi->ramDiskSize; |
548 | } else | 555 | } else |
549 | space = bi->totalParamsSize; | 556 | space = bi->totalParamsSize; |
550 | 557 | ||
551 | bootx_printf("Total space used by parameters & ramdisk: %x \n", space); | 558 | bootx_printf("Total space used by parameters & ramdisk: 0x%x \n", space); |
552 | 559 | ||
553 | /* New BootX will have flushed all TLBs and enters kernel with | 560 | /* New BootX will have flushed all TLBs and enters kernel with |
554 | * MMU switched OFF, so this should not be useful anymore. | 561 | * MMU switched OFF, so this should not be useful anymore. |
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 12b65609c072..ef10bcf2d943 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c | |||
@@ -85,11 +85,8 @@ static int __init gfar_mdio_of_init(void) | |||
85 | mdio_data.irq[k] = -1; | 85 | mdio_data.irq[k] = -1; |
86 | 86 | ||
87 | while ((child = of_get_next_child(np, child)) != NULL) { | 87 | while ((child = of_get_next_child(np, child)) != NULL) { |
88 | if (child->n_intrs) { | 88 | u32 *id = get_property(child, "reg", NULL); |
89 | u32 *id = | 89 | mdio_data.irq[*id] = irq_of_parse_and_map(child, 0); |
90 | (u32 *) get_property(child, "reg", NULL); | ||
91 | mdio_data.irq[*id] = child->intrs[0].line; | ||
92 | } | ||
93 | } | 90 | } |
94 | 91 | ||
95 | ret = | 92 | ret = |
@@ -131,6 +128,7 @@ static int __init gfar_of_init(void) | |||
131 | char *model; | 128 | char *model; |
132 | void *mac_addr; | 129 | void *mac_addr; |
133 | phandle *ph; | 130 | phandle *ph; |
131 | int n_res = 1; | ||
134 | 132 | ||
135 | memset(r, 0, sizeof(r)); | 133 | memset(r, 0, sizeof(r)); |
136 | memset(&gfar_data, 0, sizeof(gfar_data)); | 134 | memset(&gfar_data, 0, sizeof(gfar_data)); |
@@ -139,8 +137,7 @@ static int __init gfar_of_init(void) | |||
139 | if (ret) | 137 | if (ret) |
140 | goto err; | 138 | goto err; |
141 | 139 | ||
142 | r[1].start = np->intrs[0].line; | 140 | r[1].start = r[1].end = irq_of_parse_and_map(np, 0); |
143 | r[1].end = np->intrs[0].line; | ||
144 | r[1].flags = IORESOURCE_IRQ; | 141 | r[1].flags = IORESOURCE_IRQ; |
145 | 142 | ||
146 | model = get_property(np, "model", NULL); | 143 | model = get_property(np, "model", NULL); |
@@ -150,19 +147,19 @@ static int __init gfar_of_init(void) | |||
150 | r[1].name = gfar_tx_intr; | 147 | r[1].name = gfar_tx_intr; |
151 | 148 | ||
152 | r[2].name = gfar_rx_intr; | 149 | r[2].name = gfar_rx_intr; |
153 | r[2].start = np->intrs[1].line; | 150 | r[2].start = r[2].end = irq_of_parse_and_map(np, 1); |
154 | r[2].end = np->intrs[1].line; | ||
155 | r[2].flags = IORESOURCE_IRQ; | 151 | r[2].flags = IORESOURCE_IRQ; |
156 | 152 | ||
157 | r[3].name = gfar_err_intr; | 153 | r[3].name = gfar_err_intr; |
158 | r[3].start = np->intrs[2].line; | 154 | r[3].start = r[3].end = irq_of_parse_and_map(np, 2); |
159 | r[3].end = np->intrs[2].line; | ||
160 | r[3].flags = IORESOURCE_IRQ; | 155 | r[3].flags = IORESOURCE_IRQ; |
156 | |||
157 | n_res += 2; | ||
161 | } | 158 | } |
162 | 159 | ||
163 | gfar_dev = | 160 | gfar_dev = |
164 | platform_device_register_simple("fsl-gianfar", i, &r[0], | 161 | platform_device_register_simple("fsl-gianfar", i, &r[0], |
165 | np->n_intrs + 1); | 162 | n_res + 1); |
166 | 163 | ||
167 | if (IS_ERR(gfar_dev)) { | 164 | if (IS_ERR(gfar_dev)) { |
168 | ret = PTR_ERR(gfar_dev); | 165 | ret = PTR_ERR(gfar_dev); |
@@ -259,8 +256,7 @@ static int __init fsl_i2c_of_init(void) | |||
259 | if (ret) | 256 | if (ret) |
260 | goto err; | 257 | goto err; |
261 | 258 | ||
262 | r[1].start = np->intrs[0].line; | 259 | r[1].start = r[1].end = irq_of_parse_and_map(np, 0); |
263 | r[1].end = np->intrs[0].line; | ||
264 | r[1].flags = IORESOURCE_IRQ; | 260 | r[1].flags = IORESOURCE_IRQ; |
265 | 261 | ||
266 | i2c_dev = platform_device_register_simple("fsl-i2c", i, r, 2); | 262 | i2c_dev = platform_device_register_simple("fsl-i2c", i, r, 2); |
@@ -396,8 +392,7 @@ static int __init fsl_usb_of_init(void) | |||
396 | if (ret) | 392 | if (ret) |
397 | goto err; | 393 | goto err; |
398 | 394 | ||
399 | r[1].start = np->intrs[0].line; | 395 | r[1].start = r[1].end = irq_of_parse_and_map(np, 0); |
400 | r[1].end = np->intrs[0].line; | ||
401 | r[1].flags = IORESOURCE_IRQ; | 396 | r[1].flags = IORESOURCE_IRQ; |
402 | 397 | ||
403 | usb_dev_mph = | 398 | usb_dev_mph = |
@@ -445,8 +440,7 @@ static int __init fsl_usb_of_init(void) | |||
445 | if (ret) | 440 | if (ret) |
446 | goto unreg_mph; | 441 | goto unreg_mph; |
447 | 442 | ||
448 | r[1].start = np->intrs[0].line; | 443 | r[1].start = r[1].end = irq_of_parse_and_map(np, 0); |
449 | r[1].end = np->intrs[0].line; | ||
450 | r[1].flags = IORESOURCE_IRQ; | 444 | r[1].flags = IORESOURCE_IRQ; |
451 | 445 | ||
452 | usb_dev_dr = | 446 | usb_dev_dr = |
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c index 26a0cc820cde..f3038461d4c0 100644 --- a/arch/powerpc/sysdev/tsi108_dev.c +++ b/arch/powerpc/sysdev/tsi108_dev.c | |||
@@ -93,13 +93,15 @@ static int __init tsi108_eth_of_init(void) | |||
93 | goto err; | 93 | goto err; |
94 | 94 | ||
95 | r[1].name = "tx"; | 95 | r[1].name = "tx"; |
96 | r[1].start = np->intrs[0].line; | 96 | r[1].start = irq_of_parse_and_map(np, 0); |
97 | r[1].end = np->intrs[0].line; | 97 | r[1].end = irq_of_parse_and_map(np, 0); |
98 | r[1].flags = IORESOURCE_IRQ; | 98 | r[1].flags = IORESOURCE_IRQ; |
99 | DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n", | ||
100 | __FUNCTION__,r[1].name, r[1].start, r[1].end); | ||
99 | 101 | ||
100 | tsi_eth_dev = | 102 | tsi_eth_dev = |
101 | platform_device_register_simple("tsi-ethernet", i, &r[0], | 103 | platform_device_register_simple("tsi-ethernet", i, &r[0], |
102 | np->n_intrs + 1); | 104 | 1); |
103 | 105 | ||
104 | if (IS_ERR(tsi_eth_dev)) { | 106 | if (IS_ERR(tsi_eth_dev)) { |
105 | ret = PTR_ERR(tsi_eth_dev); | 107 | ret = PTR_ERR(tsi_eth_dev); |
@@ -127,7 +129,7 @@ static int __init tsi108_eth_of_init(void) | |||
127 | tsi_eth_data.regs = r[0].start; | 129 | tsi_eth_data.regs = r[0].start; |
128 | tsi_eth_data.phyregs = res.start; | 130 | tsi_eth_data.phyregs = res.start; |
129 | tsi_eth_data.phy = *phy_id; | 131 | tsi_eth_data.phy = *phy_id; |
130 | tsi_eth_data.irq_num = np->intrs[0].line; | 132 | tsi_eth_data.irq_num = irq_of_parse_and_map(np, 0); |
131 | of_node_put(phy); | 133 | of_node_put(phy); |
132 | ret = | 134 | ret = |
133 | platform_device_add_data(tsi_eth_dev, &tsi_eth_data, | 135 | platform_device_add_data(tsi_eth_dev, &tsi_eth_data, |
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 3265d54c82ed..2ab06ed3ae73 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <linux/irq.h> | 26 | #include <linux/irq.h> |
27 | #include <linux/interrupt.h> | 27 | #include <linux/interrupt.h> |
28 | 28 | ||
29 | |||
30 | #include <asm/byteorder.h> | 29 | #include <asm/byteorder.h> |
31 | #include <asm/io.h> | 30 | #include <asm/io.h> |
32 | #include <asm/irq.h> | 31 | #include <asm/irq.h> |
@@ -228,7 +227,7 @@ int __init tsi108_setup_pci(struct device_node *dev) | |||
228 | 227 | ||
229 | (hose)->ops = &tsi108_direct_pci_ops; | 228 | (hose)->ops = &tsi108_direct_pci_ops; |
230 | 229 | ||
231 | printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08lx. " | 230 | printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. " |
232 | "Firmware bus number: %d->%d\n", | 231 | "Firmware bus number: %d->%d\n", |
233 | rsrc.start, hose->first_busno, hose->last_busno); | 232 | rsrc.start, hose->first_busno, hose->last_busno); |
234 | 233 | ||
@@ -278,7 +277,7 @@ static void init_pci_source(void) | |||
278 | mb(); | 277 | mb(); |
279 | } | 278 | } |
280 | 279 | ||
281 | static inline int get_pci_source(void) | 280 | static inline unsigned int get_pci_source(void) |
282 | { | 281 | { |
283 | u_int temp = 0; | 282 | u_int temp = 0; |
284 | int irq = -1; | 283 | int irq = -1; |
@@ -371,12 +370,12 @@ static void tsi108_pci_irq_end(u_int irq) | |||
371 | * Interrupt controller descriptor for cascaded PCI interrupt controller. | 370 | * Interrupt controller descriptor for cascaded PCI interrupt controller. |
372 | */ | 371 | */ |
373 | 372 | ||
374 | struct hw_interrupt_type tsi108_pci_irq = { | 373 | static struct irq_chip tsi108_pci_irq = { |
375 | .typename = "tsi108_PCI_int", | 374 | .typename = "tsi108_PCI_int", |
376 | .enable = tsi108_pci_irq_enable, | 375 | .mask = tsi108_pci_irq_disable, |
377 | .disable = tsi108_pci_irq_disable, | ||
378 | .ack = tsi108_pci_irq_ack, | 376 | .ack = tsi108_pci_irq_ack, |
379 | .end = tsi108_pci_irq_end, | 377 | .end = tsi108_pci_irq_end, |
378 | .unmask = tsi108_pci_irq_enable, | ||
380 | }; | 379 | }; |
381 | 380 | ||
382 | /* | 381 | /* |
@@ -399,14 +398,18 @@ void __init tsi108_pci_int_init(void) | |||
399 | DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); | 398 | DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); |
400 | 399 | ||
401 | for (i = 0; i < NUM_PCI_IRQS; i++) { | 400 | for (i = 0; i < NUM_PCI_IRQS; i++) { |
402 | irq_desc[i + IRQ_PCI_INTAD_BASE].handler = &tsi108_pci_irq; | 401 | irq_desc[i + IRQ_PCI_INTAD_BASE].chip = &tsi108_pci_irq; |
403 | irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL; | 402 | irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL; |
404 | } | 403 | } |
405 | 404 | ||
406 | init_pci_source(); | 405 | init_pci_source(); |
407 | } | 406 | } |
408 | 407 | ||
409 | int tsi108_irq_cascade(struct pt_regs *regs, void *unused) | 408 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc, |
409 | struct pt_regs *regs) | ||
410 | { | 410 | { |
411 | return get_pci_source(); | 411 | unsigned int cascade_irq = get_pci_source(); |
412 | if (cascade_irq != NO_IRQ) | ||
413 | generic_handle_irq(cascade_irq, regs); | ||
414 | desc->chip->eoi(irq); | ||
412 | } | 415 | } |
diff --git a/arch/sparc/kernel/setup.c b/arch/sparc/kernel/setup.c index 35488d6c7457..0251cab4708b 100644 --- a/arch/sparc/kernel/setup.c +++ b/arch/sparc/kernel/setup.c | |||
@@ -348,9 +348,9 @@ void __init setup_arch(char **cmdline_p) | |||
348 | init_mm.context = (unsigned long) NO_CONTEXT; | 348 | init_mm.context = (unsigned long) NO_CONTEXT; |
349 | init_task.thread.kregs = &fake_swapper_regs; | 349 | init_task.thread.kregs = &fake_swapper_regs; |
350 | 350 | ||
351 | smp_setup_cpu_possible_map(); | ||
352 | |||
353 | paging_init(); | 351 | paging_init(); |
352 | |||
353 | smp_setup_cpu_possible_map(); | ||
354 | } | 354 | } |
355 | 355 | ||
356 | static int __init set_preferred_console(void) | 356 | static int __init set_preferred_console(void) |
diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c index e311ade1b490..276f22881d0f 100644 --- a/arch/sparc/kernel/smp.c +++ b/arch/sparc/kernel/smp.c | |||
@@ -34,7 +34,6 @@ | |||
34 | #include <asm/tlbflush.h> | 34 | #include <asm/tlbflush.h> |
35 | #include <asm/cpudata.h> | 35 | #include <asm/cpudata.h> |
36 | 36 | ||
37 | volatile int smp_processors_ready = 0; | ||
38 | int smp_num_cpus = 1; | 37 | int smp_num_cpus = 1; |
39 | volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,}; | 38 | volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,}; |
40 | unsigned char boot_cpu_id = 0; | 39 | unsigned char boot_cpu_id = 0; |
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c index ba843f6a2832..3ff4edd32815 100644 --- a/arch/sparc/kernel/sun4d_smp.c +++ b/arch/sparc/kernel/sun4d_smp.c | |||
@@ -42,7 +42,7 @@ extern ctxd_t *srmmu_ctx_table_phys; | |||
42 | 42 | ||
43 | extern void calibrate_delay(void); | 43 | extern void calibrate_delay(void); |
44 | 44 | ||
45 | extern volatile int smp_processors_ready; | 45 | static volatile int smp_processors_ready = 0; |
46 | static int smp_highest_cpu; | 46 | static int smp_highest_cpu; |
47 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; | 47 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; |
48 | extern cpuinfo_sparc cpu_data[NR_CPUS]; | 48 | extern cpuinfo_sparc cpu_data[NR_CPUS]; |
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c index 3b32096134aa..7d4a649138f6 100644 --- a/arch/sparc/kernel/sun4m_smp.c +++ b/arch/sparc/kernel/sun4m_smp.c | |||
@@ -39,7 +39,6 @@ extern ctxd_t *srmmu_ctx_table_phys; | |||
39 | 39 | ||
40 | extern void calibrate_delay(void); | 40 | extern void calibrate_delay(void); |
41 | 41 | ||
42 | extern volatile int smp_processors_ready; | ||
43 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; | 42 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; |
44 | extern unsigned char boot_cpu_id; | 43 | extern unsigned char boot_cpu_id; |
45 | 44 | ||
@@ -217,7 +216,6 @@ void __init smp4m_smp_done(void) | |||
217 | } | 216 | } |
218 | 217 | ||
219 | /* Ok, they are spinning and ready to go. */ | 218 | /* Ok, they are spinning and ready to go. */ |
220 | smp_processors_ready = 1; | ||
221 | } | 219 | } |
222 | 220 | ||
223 | /* At each hardware IRQ, we get this called to forward IRQ reception | 221 | /* At each hardware IRQ, we get this called to forward IRQ reception |