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-rw-r--r--arch/alpha/mm/init.c20
-rw-r--r--arch/arm/kernel/setup.c13
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c105
-rw-r--r--arch/arm/mach-at91/include/mach/board.h3
-rw-r--r--arch/arm/mach-at91/pm.c1
-rw-r--r--arch/arm/mach-omap2/board-ldp.c2
-rw-r--r--arch/arm/mm/abort-ev6.S3
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c2
-rw-r--r--arch/avr32/Kconfig2
-rw-r--r--arch/blackfin/Kconfig7
-rw-r--r--arch/blackfin/Kconfig.debug6
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig63
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig4
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig14
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig6
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BlackStamp_defconfig4
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig4
-rw-r--r--arch/blackfin/configs/CM-BF548_defconfig6
-rw-r--r--arch/blackfin/configs/IP0X_defconfig2
-rw-r--r--arch/blackfin/configs/SRV1_defconfig4
-rw-r--r--arch/blackfin/include/asm/Kbuild1
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h45
-rw-r--r--arch/blackfin/include/asm/ipipe.h100
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h12
-rw-r--r--arch/blackfin/include/asm/irq.h36
-rw-r--r--arch/blackfin/include/asm/percpu.h10
-rw-r--r--arch/blackfin/include/asm/thread_info.h2
-rw-r--r--arch/blackfin/kernel/Makefile8
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c4
-rw-r--r--arch/blackfin/kernel/ipipe.c176
-rw-r--r--arch/blackfin/kernel/irqchip.c14
-rw-r--r--arch/blackfin/kernel/kgdb_test.c9
-rw-r--r--arch/blackfin/kernel/ptrace.c5
-rw-r--r--arch/blackfin/kernel/setup.c10
-rw-r--r--arch/blackfin/kernel/time.c5
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c33
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h17
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c26
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c24
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h6
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf533/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf533/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/generic_board.c126
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c13
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537.c26
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c745
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c24
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c24
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c24
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h6
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h8
-rw-r--r--arch/blackfin/mach-bf561/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf561/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c15
-rw-r--r--arch/blackfin/mach-bf561/boards/generic_board.c113
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-common/arch_checks.c9
-rw-r--r--arch/blackfin/mach-common/cache.S22
-rw-r--r--arch/blackfin/mach-common/clocks-init.c2
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S24
-rw-r--r--arch/blackfin/mach-common/entry.S61
-rw-r--r--arch/blackfin/mach-common/interrupt.S12
-rw-r--r--arch/blackfin/mach-common/ints-priority.c126
-rw-r--r--arch/blackfin/mach-common/smp.c6
-rw-r--r--arch/blackfin/mm/init.c2
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_dma.c7
-rw-r--r--arch/m68knommu/platform/5206e/config.c1
-rw-r--r--arch/m68knommu/platform/528x/config.c228
-rw-r--r--arch/mips/include/asm/compat.h7
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc610.c4
-rw-r--r--arch/s390/crypto/aes_s390.c2
-rw-r--r--arch/sh/boards/board-ap325rxa.c1
-rw-r--r--arch/x86/Kconfig12
-rw-r--r--arch/x86/include/asm/apic.h2
-rw-r--r--arch/x86/include/asm/apicdef.h1
-rw-r--r--arch/x86/include/asm/cacheflush.h53
-rw-r--r--arch/x86/include/asm/efi.h2
-rw-r--r--arch/x86/include/asm/entry_arch.h2
-rw-r--r--arch/x86/include/asm/fixmap.h10
-rw-r--r--arch/x86/include/asm/hardirq.h1
-rw-r--r--arch/x86/include/asm/hw_irq.h1
-rw-r--r--arch/x86/include/asm/i387.h8
-rw-r--r--arch/x86/include/asm/init.h18
-rw-r--r--arch/x86/include/asm/io.h3
-rw-r--r--arch/x86/include/asm/irq.h1
-rw-r--r--arch/x86/include/asm/irq_vectors.h5
-rw-r--r--arch/x86/include/asm/kexec.h13
-rw-r--r--arch/x86/include/asm/linkage.h16
-rw-r--r--arch/x86/include/asm/mce.h35
-rw-r--r--arch/x86/include/asm/mmzone_32.h43
-rw-r--r--arch/x86/include/asm/msr-index.h5
-rw-r--r--arch/x86/include/asm/page_types.h6
-rw-r--r--arch/x86/include/asm/pat.h5
-rw-r--r--arch/x86/include/asm/percpu.h8
-rw-r--r--arch/x86/include/asm/pgtable.h2
-rw-r--r--arch/x86/include/asm/pgtable_32_types.h5
-rw-r--r--arch/x86/include/asm/pgtable_types.h1
-rw-r--r--arch/x86/include/asm/uv/uv_hub.h4
-rw-r--r--arch/x86/include/asm/xen/page.h1
-rw-r--r--arch/x86/kernel/Makefile2
-rw-r--r--arch/x86/kernel/alternative.c17
-rw-r--r--arch/x86/kernel/apic/apic.c15
-rw-r--r--arch/x86/kernel/cpu/amd.c52
-rw-r--r--arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c2
-rw-r--r--arch/x86/kernel/cpu/cpufreq/p4-clockmod.c1
-rw-r--r--arch/x86/kernel/cpu/intel.c25
-rw-r--r--arch/x86/kernel/cpu/mcheck/Makefile1
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_32.c14
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_64.c530
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd_64.c22
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_intel_64.c207
-rw-r--r--arch/x86/kernel/cpu/mcheck/threshold.c29
-rw-r--r--arch/x86/kernel/ds.c3
-rw-r--r--arch/x86/kernel/efi.c7
-rw-r--r--arch/x86/kernel/efi_64.c21
-rw-r--r--arch/x86/kernel/entry_64.S2
-rw-r--r--arch/x86/kernel/i387.c2
-rw-r--r--arch/x86/kernel/irq.c34
-rw-r--r--arch/x86/kernel/irq_32.c29
-rw-r--r--arch/x86/kernel/irqinit_32.c3
-rw-r--r--arch/x86/kernel/irqinit_64.c3
-rw-r--r--arch/x86/kernel/machine_kexec_32.c17
-rw-r--r--arch/x86/kernel/machine_kexec_64.c99
-rw-r--r--arch/x86/kernel/mpparse.c25
-rw-r--r--arch/x86/kernel/reboot.c8
-rw-r--r--arch/x86/kernel/relocate_kernel_32.S24
-rw-r--r--arch/x86/kernel/relocate_kernel_64.S189
-rw-r--r--arch/x86/kernel/setup.c9
-rw-r--r--arch/x86/kernel/setup_percpu.c398
-rw-r--r--arch/x86/kernel/smpboot.c78
-rw-r--r--arch/x86/kernel/tlb_uv.c2
-rw-r--r--arch/x86/kernel/uv_time.c393
-rw-r--r--arch/x86/kernel/vmlinux_64.lds.S7
-rw-r--r--arch/x86/lguest/boot.c21
-rw-r--r--arch/x86/math-emu/fpu_aux.c31
-rw-r--r--arch/x86/mm/highmem_32.c9
-rw-r--r--arch/x86/mm/init.c344
-rw-r--r--arch/x86/mm/init_32.c273
-rw-r--r--arch/x86/mm/init_64.c352
-rw-r--r--arch/x86/mm/ioremap.c35
-rw-r--r--arch/x86/mm/kmmio.c164
-rw-r--r--arch/x86/mm/memtest.c3
-rw-r--r--arch/x86/mm/numa_32.c5
-rw-r--r--arch/x86/mm/testmmiotrace.c70
-rw-r--r--arch/x86/xen/enlighten.c10
-rw-r--r--arch/x86/xen/mmu.c7
-rw-r--r--arch/x86/xen/smp.c6
-rw-r--r--arch/xtensa/Kconfig3
-rw-r--r--arch/xtensa/kernel/setup.c2
-rw-r--r--arch/xtensa/kernel/traps.c1
-rw-r--r--arch/xtensa/mm/fault.c1
-rw-r--r--arch/xtensa/platforms/iss/console.c6
170 files changed, 3541 insertions, 2954 deletions
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 5d7a16eab312..af71d38c8e41 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -189,9 +189,21 @@ callback_init(void * kernel_end)
189 189
190 if (alpha_using_srm) { 190 if (alpha_using_srm) {
191 static struct vm_struct console_remap_vm; 191 static struct vm_struct console_remap_vm;
192 unsigned long vaddr = VMALLOC_START; 192 unsigned long nr_pages = 0;
193 unsigned long vaddr;
193 unsigned long i, j; 194 unsigned long i, j;
194 195
196 /* calculate needed size */
197 for (i = 0; i < crb->map_entries; ++i)
198 nr_pages += crb->map[i].count;
199
200 /* register the vm area */
201 console_remap_vm.flags = VM_ALLOC;
202 console_remap_vm.size = nr_pages << PAGE_SHIFT;
203 vm_area_register_early(&console_remap_vm, PAGE_SIZE);
204
205 vaddr = (unsigned long)console_remap_vm.addr;
206
195 /* Set up the third level PTEs and update the virtual 207 /* Set up the third level PTEs and update the virtual
196 addresses of the CRB entries. */ 208 addresses of the CRB entries. */
197 for (i = 0; i < crb->map_entries; ++i) { 209 for (i = 0; i < crb->map_entries; ++i) {
@@ -213,12 +225,6 @@ callback_init(void * kernel_end)
213 vaddr += PAGE_SIZE; 225 vaddr += PAGE_SIZE;
214 } 226 }
215 } 227 }
216
217 /* Let vmalloc know that we've allocated some space. */
218 console_remap_vm.flags = VM_ALLOC;
219 console_remap_vm.addr = (void *) VMALLOC_START;
220 console_remap_vm.size = vaddr - VMALLOC_START;
221 vmlist = &console_remap_vm;
222 } 228 }
223 229
224 callback_init_done = 1; 230 callback_init_done = 1;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 7049815d66d5..68d6494c0389 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -233,12 +233,13 @@ static void __init cacheid_init(void)
233 unsigned int cachetype = read_cpuid_cachetype(); 233 unsigned int cachetype = read_cpuid_cachetype();
234 unsigned int arch = cpu_architecture(); 234 unsigned int arch = cpu_architecture();
235 235
236 if (arch >= CPU_ARCH_ARMv7) { 236 if (arch >= CPU_ARCH_ARMv6) {
237 cacheid = CACHEID_VIPT_NONALIASING; 237 if ((cachetype & (7 << 29)) == 4 << 29) {
238 if ((cachetype & (3 << 14)) == 1 << 14) 238 /* ARMv7 register format */
239 cacheid |= CACHEID_ASID_TAGGED; 239 cacheid = CACHEID_VIPT_NONALIASING;
240 } else if (arch >= CPU_ARCH_ARMv6) { 240 if ((cachetype & (3 << 14)) == 1 << 14)
241 if (cachetype & (1 << 23)) 241 cacheid |= CACHEID_ASID_TAGGED;
242 } else if (cachetype & (1 << 23))
242 cacheid = CACHEID_VIPT_ALIASING; 243 cacheid = CACHEID_VIPT_ALIASING;
243 else 244 else
244 cacheid = CACHEID_VIPT_NONALIASING; 245 cacheid = CACHEID_VIPT_NONALIASING;
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 134af97ff340..b7f233242315 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -347,6 +347,111 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
347void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 347void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
348#endif 348#endif
349 349
350/* --------------------------------------------------------------------
351 * Compact Flash (PCMCIA or IDE)
352 * -------------------------------------------------------------------- */
353
354#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
355 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
356
357static struct at91_cf_data cf0_data;
358
359static struct resource cf0_resources[] = {
360 [0] = {
361 .start = AT91_CHIPSELECT_4,
362 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
363 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
364 }
365};
366
367static struct platform_device cf0_device = {
368 .id = 0,
369 .dev = {
370 .platform_data = &cf0_data,
371 },
372 .resource = cf0_resources,
373 .num_resources = ARRAY_SIZE(cf0_resources),
374};
375
376static struct at91_cf_data cf1_data;
377
378static struct resource cf1_resources[] = {
379 [0] = {
380 .start = AT91_CHIPSELECT_5,
381 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
382 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
383 }
384};
385
386static struct platform_device cf1_device = {
387 .id = 1,
388 .dev = {
389 .platform_data = &cf1_data,
390 },
391 .resource = cf1_resources,
392 .num_resources = ARRAY_SIZE(cf1_resources),
393};
394
395void __init at91_add_device_cf(struct at91_cf_data *data)
396{
397 unsigned long ebi0_csa;
398 struct platform_device *pdev;
399
400 if (!data)
401 return;
402
403 /*
404 * assign CS4 or CS5 to SMC with Compact Flash logic support,
405 * we assume SMC timings are configured by board code,
406 * except True IDE where timings are controlled by driver
407 */
408 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
409 switch (data->chipselect) {
410 case 4:
411 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
412 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
413 cf0_data = *data;
414 pdev = &cf0_device;
415 break;
416 case 5:
417 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
418 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
419 cf1_data = *data;
420 pdev = &cf1_device;
421 break;
422 default:
423 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
424 data->chipselect);
425 return;
426 }
427 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
428
429 if (data->det_pin) {
430 at91_set_gpio_input(data->det_pin, 1);
431 at91_set_deglitch(data->det_pin, 1);
432 }
433
434 if (data->irq_pin) {
435 at91_set_gpio_input(data->irq_pin, 1);
436 at91_set_deglitch(data->irq_pin, 1);
437 }
438
439 if (data->vcc_pin)
440 /* initially off */
441 at91_set_gpio_output(data->vcc_pin, 0);
442
443 /* enable EBI controlled pins */
444 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
445 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
446 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
447 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
448
449 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
450 platform_device_register(pdev);
451}
452#else
453void __init at91_add_device_cf(struct at91_cf_data *data) {}
454#endif
350 455
351/* -------------------------------------------------------------------- 456/* --------------------------------------------------------------------
352 * NAND / SmartMedia 457 * NAND / SmartMedia
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 0b3ae21b4565..793fe7b25f36 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -56,6 +56,9 @@ struct at91_cf_data {
56 u8 vcc_pin; /* power switching */ 56 u8 vcc_pin; /* power switching */
57 u8 rst_pin; /* card reset */ 57 u8 rst_pin; /* card reset */
58 u8 chipselect; /* EBI Chip Select number */ 58 u8 chipselect; /* EBI Chip Select number */
59 u8 flags;
60#define AT91_CF_TRUE_IDE 0x01
61#define AT91_IDE_SWAP_A0_A2 0x02
59}; 62};
60extern void __init at91_add_device_cf(struct at91_cf_data *data); 63extern void __init at91_add_device_cf(struct at91_cf_data *data);
61 64
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 9bb4f043aa22..7ac812dc055a 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -332,7 +332,6 @@ static int at91_pm_enter(suspend_state_t state)
332 at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); 332 at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
333 333
334error: 334error:
335 sdram_selfrefresh_disable();
336 target_state = PM_SUSPEND_ON; 335 target_state = PM_SUSPEND_ON;
337 at91_irq_resume(); 336 at91_irq_resume();
338 at91_gpio_resume(); 337 at91_gpio_resume();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f6a13451d1fd..6031e179926b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -81,7 +81,7 @@ static inline void __init ldp_init_smc911x(void)
81 } 81 }
82 82
83 ldp_smc911x_resources[0].start = cs_mem_base + 0x0; 83 ldp_smc911x_resources[0].start = cs_mem_base + 0x0;
84 ldp_smc911x_resources[0].end = cs_mem_base + 0xf; 84 ldp_smc911x_resources[0].end = cs_mem_base + 0xff;
85 udelay(100); 85 udelay(100);
86 86
87 eth_gpio = LDP_SMC911X_GPIO; 87 eth_gpio = LDP_SMC911X_GPIO;
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 8a7f65ba14b7..94077fbd96b7 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -23,7 +23,8 @@ ENTRY(v6_early_abort)
23#ifdef CONFIG_CPU_32v6K 23#ifdef CONFIG_CPU_32v6K
24 clrex 24 clrex
25#else 25#else
26 strex r0, r1, [sp] @ Clear the exclusive monitor 26 sub r1, sp, #4 @ Get unused stack location
27 strex r0, r1, [r1] @ Clear the exclusive monitor
27#endif 28#endif
28 mrc p15, 0, r1, c5, c0, 0 @ get FSR 29 mrc p15, 0, r1, c5, c0, 0 @ get FSR
29 mrc p15, 0, r0, c6, c0, 0 @ get FAR 30 mrc p15, 0, r0, c6, c0, 0 @ get FAR
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index 1f7cc0067f5c..ebb305ce7689 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -55,7 +55,7 @@ static void s3c_irq_eint_unmask(unsigned int irq)
55 u32 mask; 55 u32 mask;
56 56
57 mask = __raw_readl(S3C64XX_EINT0MASK); 57 mask = __raw_readl(S3C64XX_EINT0MASK);
58 mask |= eint_irq_to_bit(irq); 58 mask &= ~eint_irq_to_bit(irq);
59 __raw_writel(mask, S3C64XX_EINT0MASK); 59 __raw_writel(mask, S3C64XX_EINT0MASK);
60} 60}
61 61
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index b189680d18b0..05fe3053dcae 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -181,7 +181,7 @@ source "kernel/Kconfig.preempt"
181config QUICKLIST 181config QUICKLIST
182 def_bool y 182 def_bool y
183 183
184config HAVE_ARCH_BOOTMEM_NODE 184config HAVE_ARCH_BOOTMEM
185 def_bool n 185 def_bool n
186 186
187config ARCH_HAVE_MEMORY_PRESENT 187config ARCH_HAVE_MEMORY_PRESENT
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8f1f97d56e1e..0c1f86e3e44a 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -1129,6 +1129,7 @@ endchoice
1129 1129
1130config PM_WAKEUP_BY_GPIO 1130config PM_WAKEUP_BY_GPIO
1131 bool "Allow Wakeup from Standby by GPIO" 1131 bool "Allow Wakeup from Standby by GPIO"
1132 depends on PM && !BF54x
1132 1133
1133config PM_WAKEUP_GPIO_NUMBER 1134config PM_WAKEUP_GPIO_NUMBER
1134 int "GPIO number" 1135 int "GPIO number"
@@ -1168,6 +1169,12 @@ config PM_BFIN_WAKE_GP
1168 default n 1169 default n
1169 help 1170 help
1170 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1171 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1172 (all processors, except ADSP-BF549). This option sets
1173 the general-purpose wake-up enable (GPWE) control bit to enable
1174 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1175 On ADSP-BF549 this option enables the the same functionality on the
1176 /MRXON pin also PH7.
1177
1171endmenu 1178endmenu
1172 1179
1173menu "CPU Frequency scaling" 1180menu "CPU Frequency scaling"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 5f981d9ca625..79e7e63ab709 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -21,12 +21,6 @@ config DEBUG_STACK_USAGE
21config HAVE_ARCH_KGDB 21config HAVE_ARCH_KGDB
22 def_bool y 22 def_bool y
23 23
24config KGDB_TESTCASE
25 tristate "KGDB: for test case in expect"
26 default n
27 help
28 This is a kgdb test case for automated testing.
29
30config DEBUG_VERBOSE 24config DEBUG_VERBOSE
31 bool "Verbose fault messages" 25 bool "Verbose fault messages"
32 default y 26 default y
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 4fdb9e04759f..281f4b60e603 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc2 3# Linux kernel version: 2.6.28
4# Fri Jan 9 17:58:41 2009 4# Fri Feb 20 10:01:44 2009
5# 5#
6# CONFIG_MMU is not set 6# CONFIG_MMU is not set
7# CONFIG_FPU is not set 7# CONFIG_FPU is not set
@@ -133,10 +133,15 @@ CONFIG_BF518=y
133# CONFIG_BF538 is not set 133# CONFIG_BF538 is not set
134# CONFIG_BF539 is not set 134# CONFIG_BF539 is not set
135# CONFIG_BF542 is not set 135# CONFIG_BF542 is not set
136# CONFIG_BF542M is not set
136# CONFIG_BF544 is not set 137# CONFIG_BF544 is not set
138# CONFIG_BF544M is not set
137# CONFIG_BF547 is not set 139# CONFIG_BF547 is not set
140# CONFIG_BF547M is not set
138# CONFIG_BF548 is not set 141# CONFIG_BF548 is not set
142# CONFIG_BF548M is not set
139# CONFIG_BF549 is not set 143# CONFIG_BF549 is not set
144# CONFIG_BF549M is not set
140# CONFIG_BF561 is not set 145# CONFIG_BF561 is not set
141CONFIG_BF_REV_MIN=0 146CONFIG_BF_REV_MIN=0
142CONFIG_BF_REV_MAX=2 147CONFIG_BF_REV_MAX=2
@@ -426,7 +431,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
426# CONFIG_TIPC is not set 431# CONFIG_TIPC is not set
427# CONFIG_ATM is not set 432# CONFIG_ATM is not set
428# CONFIG_BRIDGE is not set 433# CONFIG_BRIDGE is not set
429# CONFIG_NET_DSA is not set 434CONFIG_NET_DSA=y
435# CONFIG_NET_DSA_TAG_DSA is not set
436# CONFIG_NET_DSA_TAG_EDSA is not set
437# CONFIG_NET_DSA_TAG_TRAILER is not set
438CONFIG_NET_DSA_TAG_STPID=y
439# CONFIG_NET_DSA_MV88E6XXX is not set
440# CONFIG_NET_DSA_MV88E6060 is not set
441# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
442# CONFIG_NET_DSA_MV88E6131 is not set
443# CONFIG_NET_DSA_MV88E6123_61_65 is not set
444CONFIG_NET_DSA_KSZ8893M=y
430# CONFIG_VLAN_8021Q is not set 445# CONFIG_VLAN_8021Q is not set
431# CONFIG_DECNET is not set 446# CONFIG_DECNET is not set
432# CONFIG_LLC2 is not set 447# CONFIG_LLC2 is not set
@@ -529,6 +544,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
529# 544#
530# Self-contained MTD device drivers 545# Self-contained MTD device drivers
531# 546#
547# CONFIG_MTD_DATAFLASH is not set
548# CONFIG_MTD_M25P80 is not set
532# CONFIG_MTD_SLRAM is not set 549# CONFIG_MTD_SLRAM is not set
533# CONFIG_MTD_PHRAM is not set 550# CONFIG_MTD_PHRAM is not set
534# CONFIG_MTD_MTDRAM is not set 551# CONFIG_MTD_MTDRAM is not set
@@ -561,7 +578,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
561# CONFIG_BLK_DEV_HD is not set 578# CONFIG_BLK_DEV_HD is not set
562CONFIG_MISC_DEVICES=y 579CONFIG_MISC_DEVICES=y
563# CONFIG_EEPROM_93CX6 is not set 580# CONFIG_EEPROM_93CX6 is not set
581# CONFIG_ICS932S401 is not set
564# CONFIG_ENCLOSURE_SERVICES is not set 582# CONFIG_ENCLOSURE_SERVICES is not set
583# CONFIG_C2PORT is not set
565CONFIG_HAVE_IDE=y 584CONFIG_HAVE_IDE=y
566# CONFIG_IDE is not set 585# CONFIG_IDE is not set
567 586
@@ -607,6 +626,7 @@ CONFIG_BFIN_RX_DESC_NUM=20
607# CONFIG_SMC91X is not set 626# CONFIG_SMC91X is not set
608# CONFIG_SMSC911X is not set 627# CONFIG_SMSC911X is not set
609# CONFIG_DM9000 is not set 628# CONFIG_DM9000 is not set
629# CONFIG_ENC28J60 is not set
610# CONFIG_IBM_NEW_EMAC_ZMII is not set 630# CONFIG_IBM_NEW_EMAC_ZMII is not set
611# CONFIG_IBM_NEW_EMAC_RGMII is not set 631# CONFIG_IBM_NEW_EMAC_RGMII is not set
612# CONFIG_IBM_NEW_EMAC_TAH is not set 632# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -764,7 +784,23 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
764# CONFIG_I2C_DEBUG_ALGO is not set 784# CONFIG_I2C_DEBUG_ALGO is not set
765# CONFIG_I2C_DEBUG_BUS is not set 785# CONFIG_I2C_DEBUG_BUS is not set
766# CONFIG_I2C_DEBUG_CHIP is not set 786# CONFIG_I2C_DEBUG_CHIP is not set
767# CONFIG_SPI is not set 787CONFIG_SPI=y
788# CONFIG_SPI_DEBUG is not set
789CONFIG_SPI_MASTER=y
790
791#
792# SPI Master Controller Drivers
793#
794CONFIG_SPI_BFIN=y
795# CONFIG_SPI_BFIN_LOCK is not set
796# CONFIG_SPI_BITBANG is not set
797
798#
799# SPI Protocol Masters
800#
801# CONFIG_SPI_AT25 is not set
802# CONFIG_SPI_SPIDEV is not set
803# CONFIG_SPI_TLE62X0 is not set
768CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 804CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
769# CONFIG_GPIOLIB is not set 805# CONFIG_GPIOLIB is not set
770# CONFIG_W1 is not set 806# CONFIG_W1 is not set
@@ -788,8 +824,10 @@ CONFIG_BFIN_WDT=y
788# CONFIG_MFD_SM501 is not set 824# CONFIG_MFD_SM501 is not set
789# CONFIG_HTC_PASIC3 is not set 825# CONFIG_HTC_PASIC3 is not set
790# CONFIG_MFD_TMIO is not set 826# CONFIG_MFD_TMIO is not set
827# CONFIG_PMIC_DA903X is not set
791# CONFIG_MFD_WM8400 is not set 828# CONFIG_MFD_WM8400 is not set
792# CONFIG_MFD_WM8350_I2C is not set 829# CONFIG_MFD_WM8350_I2C is not set
830# CONFIG_REGULATOR is not set
793 831
794# 832#
795# Multimedia devices 833# Multimedia devices
@@ -861,10 +899,18 @@ CONFIG_RTC_INTF_DEV=y
861# CONFIG_RTC_DRV_M41T80 is not set 899# CONFIG_RTC_DRV_M41T80 is not set
862# CONFIG_RTC_DRV_S35390A is not set 900# CONFIG_RTC_DRV_S35390A is not set
863# CONFIG_RTC_DRV_FM3130 is not set 901# CONFIG_RTC_DRV_FM3130 is not set
902# CONFIG_RTC_DRV_RX8581 is not set
864 903
865# 904#
866# SPI RTC drivers 905# SPI RTC drivers
867# 906#
907# CONFIG_RTC_DRV_M41T94 is not set
908# CONFIG_RTC_DRV_DS1305 is not set
909# CONFIG_RTC_DRV_DS1390 is not set
910# CONFIG_RTC_DRV_MAX6902 is not set
911# CONFIG_RTC_DRV_R9701 is not set
912# CONFIG_RTC_DRV_RS5C348 is not set
913# CONFIG_RTC_DRV_DS3234 is not set
868 914
869# 915#
870# Platform RTC drivers 916# Platform RTC drivers
@@ -1062,12 +1108,20 @@ CONFIG_DEBUG_INFO=y
1062# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1108# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1063# CONFIG_FAULT_INJECTION is not set 1109# CONFIG_FAULT_INJECTION is not set
1064CONFIG_SYSCTL_SYSCALL_CHECK=y 1110CONFIG_SYSCTL_SYSCALL_CHECK=y
1111
1112#
1113# Tracers
1114#
1115# CONFIG_SCHED_TRACER is not set
1116# CONFIG_CONTEXT_SWITCH_TRACER is not set
1117# CONFIG_BOOT_TRACER is not set
1065# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1118# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1066# CONFIG_SAMPLES is not set 1119# CONFIG_SAMPLES is not set
1067CONFIG_HAVE_ARCH_KGDB=y 1120CONFIG_HAVE_ARCH_KGDB=y
1068# CONFIG_KGDB is not set 1121# CONFIG_KGDB is not set
1069# CONFIG_DEBUG_STACKOVERFLOW is not set 1122# CONFIG_DEBUG_STACKOVERFLOW is not set
1070# CONFIG_DEBUG_STACK_USAGE is not set 1123# CONFIG_DEBUG_STACK_USAGE is not set
1124# CONFIG_KGDB_TESTCASE is not set
1071CONFIG_DEBUG_VERBOSE=y 1125CONFIG_DEBUG_VERBOSE=y
1072CONFIG_DEBUG_MMRS=y 1126CONFIG_DEBUG_MMRS=y
1073# CONFIG_DEBUG_HWERR is not set 1127# CONFIG_DEBUG_HWERR is not set
@@ -1100,6 +1154,7 @@ CONFIG_CRYPTO=y
1100# 1154#
1101# CONFIG_CRYPTO_FIPS is not set 1155# CONFIG_CRYPTO_FIPS is not set
1102# CONFIG_CRYPTO_MANAGER is not set 1156# CONFIG_CRYPTO_MANAGER is not set
1157# CONFIG_CRYPTO_MANAGER2 is not set
1103# CONFIG_CRYPTO_GF128MUL is not set 1158# CONFIG_CRYPTO_GF128MUL is not set
1104# CONFIG_CRYPTO_NULL is not set 1159# CONFIG_CRYPTO_NULL is not set
1105# CONFIG_CRYPTO_CRYPTD is not set 1160# CONFIG_CRYPTO_CRYPTD is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 833128b39724..a50050f17706 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -327,8 +327,8 @@ CONFIG_BFIN_ICACHE=y
327CONFIG_BFIN_DCACHE=y 327CONFIG_BFIN_DCACHE=y
328# CONFIG_BFIN_DCACHE_BANKA is not set 328# CONFIG_BFIN_DCACHE_BANKA is not set
329# CONFIG_BFIN_ICACHE_LOCK is not set 329# CONFIG_BFIN_ICACHE_LOCK is not set
330# CONFIG_BFIN_WB is not set 330CONFIG_BFIN_WB=y
331CONFIG_BFIN_WT=y 331# CONFIG_BFIN_WT is not set
332# CONFIG_MPU is not set 332# CONFIG_MPU is not set
333 333
334# 334#
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 334c94b51c40..0a2a00d63887 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
290CONFIG_BFIN_DCACHE=y 290CONFIG_BFIN_DCACHE=y
291# CONFIG_BFIN_DCACHE_BANKA is not set 291# CONFIG_BFIN_DCACHE_BANKA is not set
292# CONFIG_BFIN_ICACHE_LOCK is not set 292# CONFIG_BFIN_ICACHE_LOCK is not set
293# CONFIG_BFIN_WB is not set 293CONFIG_BFIN_WB=y
294CONFIG_BFIN_WT=y 294# CONFIG_BFIN_WT is not set
295# CONFIG_MPU is not set 295# CONFIG_MPU is not set
296 296
297# 297#
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 9d733436e300..eb027587a355 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
290CONFIG_BFIN_DCACHE=y 290CONFIG_BFIN_DCACHE=y
291# CONFIG_BFIN_DCACHE_BANKA is not set 291# CONFIG_BFIN_DCACHE_BANKA is not set
292# CONFIG_BFIN_ICACHE_LOCK is not set 292# CONFIG_BFIN_ICACHE_LOCK is not set
293# CONFIG_BFIN_WB is not set 293CONFIG_BFIN_WB=y
294CONFIG_BFIN_WT=y 294# CONFIG_BFIN_WT is not set
295# CONFIG_MPU is not set 295# CONFIG_MPU is not set
296 296
297# 297#
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 4fb4108d3103..9e62b9f40eb1 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -298,8 +298,8 @@ CONFIG_BFIN_ICACHE=y
298CONFIG_BFIN_DCACHE=y 298CONFIG_BFIN_DCACHE=y
299# CONFIG_BFIN_DCACHE_BANKA is not set 299# CONFIG_BFIN_DCACHE_BANKA is not set
300# CONFIG_BFIN_ICACHE_LOCK is not set 300# CONFIG_BFIN_ICACHE_LOCK is not set
301# CONFIG_BFIN_WB is not set 301CONFIG_BFIN_WB=y
302CONFIG_BFIN_WT=y 302# CONFIG_BFIN_WT is not set
303# CONFIG_MPU is not set 303# CONFIG_MPU is not set
304 304
305# 305#
@@ -568,15 +568,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
568# CONFIG_MTD_DOC2000 is not set 568# CONFIG_MTD_DOC2000 is not set
569# CONFIG_MTD_DOC2001 is not set 569# CONFIG_MTD_DOC2001 is not set
570# CONFIG_MTD_DOC2001PLUS is not set 570# CONFIG_MTD_DOC2001PLUS is not set
571CONFIG_MTD_NAND=m 571# CONFIG_MTD_NAND is not set
572# CONFIG_MTD_NAND_VERIFY_WRITE is not set
573# CONFIG_MTD_NAND_ECC_SMC is not set
574# CONFIG_MTD_NAND_MUSEUM_IDS is not set
575# CONFIG_MTD_NAND_BFIN is not set
576CONFIG_MTD_NAND_IDS=m
577# CONFIG_MTD_NAND_DISKONCHIP is not set
578# CONFIG_MTD_NAND_NANDSIM is not set
579CONFIG_MTD_NAND_PLATFORM=m
580# CONFIG_MTD_ONENAND is not set 572# CONFIG_MTD_ONENAND is not set
581 573
582# 574#
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index cb32f5624a1b..dd6ad6be1c87 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -306,8 +306,8 @@ CONFIG_BFIN_ICACHE=y
306CONFIG_BFIN_DCACHE=y 306CONFIG_BFIN_DCACHE=y
307# CONFIG_BFIN_DCACHE_BANKA is not set 307# CONFIG_BFIN_DCACHE_BANKA is not set
308# CONFIG_BFIN_ICACHE_LOCK is not set 308# CONFIG_BFIN_ICACHE_LOCK is not set
309# CONFIG_BFIN_WB is not set 309CONFIG_BFIN_WB=y
310CONFIG_BFIN_WT=y 310# CONFIG_BFIN_WT is not set
311# CONFIG_MPU is not set 311# CONFIG_MPU is not set
312 312
313# 313#
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 0f8697618aa5..6bc2fb1b2a70 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -361,8 +361,8 @@ CONFIG_BFIN_ICACHE=y
361CONFIG_BFIN_DCACHE=y 361CONFIG_BFIN_DCACHE=y
362# CONFIG_BFIN_DCACHE_BANKA is not set 362# CONFIG_BFIN_DCACHE_BANKA is not set
363# CONFIG_BFIN_ICACHE_LOCK is not set 363# CONFIG_BFIN_ICACHE_LOCK is not set
364# CONFIG_BFIN_WB is not set 364CONFIG_BFIN_WB=y
365CONFIG_BFIN_WT=y 365# CONFIG_BFIN_WT is not set
366# CONFIG_BFIN_L2_CACHEABLE is not set 366# CONFIG_BFIN_L2_CACHEABLE is not set
367# CONFIG_MPU is not set 367# CONFIG_MPU is not set
368 368
@@ -680,7 +680,7 @@ CONFIG_SCSI=y
680CONFIG_SCSI_DMA=y 680CONFIG_SCSI_DMA=y
681# CONFIG_SCSI_TGT is not set 681# CONFIG_SCSI_TGT is not set
682# CONFIG_SCSI_NETLINK is not set 682# CONFIG_SCSI_NETLINK is not set
683CONFIG_SCSI_PROC_FS=y 683# CONFIG_SCSI_PROC_FS is not set
684 684
685# 685#
686# SCSI support type (disk, tape, CD-ROM) 686# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 042c7adfccfa..69714fb3e608 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -329,8 +329,8 @@ CONFIG_BFIN_ICACHE=y
329CONFIG_BFIN_DCACHE=y 329CONFIG_BFIN_DCACHE=y
330# CONFIG_BFIN_DCACHE_BANKA is not set 330# CONFIG_BFIN_DCACHE_BANKA is not set
331# CONFIG_BFIN_ICACHE_LOCK is not set 331# CONFIG_BFIN_ICACHE_LOCK is not set
332# CONFIG_BFIN_WB is not set 332CONFIG_BFIN_WB=y
333CONFIG_BFIN_WT=y 333# CONFIG_BFIN_WT is not set
334# CONFIG_BFIN_L2_CACHEABLE is not set 334# CONFIG_BFIN_L2_CACHEABLE is not set
335# CONFIG_MPU is not set 335# CONFIG_MPU is not set
336 336
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 3a20e281d23c..017c6ea071b5 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -288,8 +288,8 @@ CONFIG_BFIN_ICACHE=y
288CONFIG_BFIN_DCACHE=y 288CONFIG_BFIN_DCACHE=y
289# CONFIG_BFIN_DCACHE_BANKA is not set 289# CONFIG_BFIN_DCACHE_BANKA is not set
290# CONFIG_BFIN_ICACHE_LOCK is not set 290# CONFIG_BFIN_ICACHE_LOCK is not set
291# CONFIG_BFIN_WB is not set 291CONFIG_BFIN_WB=y
292CONFIG_BFIN_WT=y 292# CONFIG_BFIN_WT is not set
293# CONFIG_MPU is not set 293# CONFIG_MPU is not set
294 294
295# 295#
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index 865ed85a5760..d880ef786770 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -332,8 +332,8 @@ CONFIG_BFIN_ICACHE=y
332CONFIG_BFIN_DCACHE=y 332CONFIG_BFIN_DCACHE=y
333# CONFIG_BFIN_DCACHE_BANKA is not set 333# CONFIG_BFIN_DCACHE_BANKA is not set
334# CONFIG_BFIN_ICACHE_LOCK is not set 334# CONFIG_BFIN_ICACHE_LOCK is not set
335# CONFIG_BFIN_WB is not set 335CONFIG_BFIN_WB=y
336CONFIG_BFIN_WT=y 336# CONFIG_BFIN_WT is not set
337# CONFIG_MPU is not set 337# CONFIG_MPU is not set
338 338
339# 339#
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index efe9741b1f14..f410430b4e3d 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -336,8 +336,8 @@ CONFIG_BFIN_ICACHE=y
336CONFIG_BFIN_DCACHE=y 336CONFIG_BFIN_DCACHE=y
337# CONFIG_BFIN_DCACHE_BANKA is not set 337# CONFIG_BFIN_DCACHE_BANKA is not set
338# CONFIG_BFIN_ICACHE_LOCK is not set 338# CONFIG_BFIN_ICACHE_LOCK is not set
339# CONFIG_BFIN_WB is not set 339CONFIG_BFIN_WB=y
340CONFIG_BFIN_WT=y 340# CONFIG_BFIN_WT is not set
341CONFIG_L1_MAX_PIECE=16 341CONFIG_L1_MAX_PIECE=16
342# CONFIG_MPU is not set 342# CONFIG_MPU is not set
343 343
@@ -595,7 +595,7 @@ CONFIG_SCSI=y
595CONFIG_SCSI_DMA=y 595CONFIG_SCSI_DMA=y
596# CONFIG_SCSI_TGT is not set 596# CONFIG_SCSI_TGT is not set
597# CONFIG_SCSI_NETLINK is not set 597# CONFIG_SCSI_NETLINK is not set
598CONFIG_SCSI_PROC_FS=y 598# CONFIG_SCSI_PROC_FS is not set
599 599
600# 600#
601# SCSI support type (disk, tape, CD-ROM) 601# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index eae83b5de92f..7db93874c987 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -612,7 +612,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
612CONFIG_SCSI=y 612CONFIG_SCSI=y
613# CONFIG_SCSI_TGT is not set 613# CONFIG_SCSI_TGT is not set
614# CONFIG_SCSI_NETLINK is not set 614# CONFIG_SCSI_NETLINK is not set
615CONFIG_SCSI_PROC_FS=y 615# CONFIG_SCSI_PROC_FS is not set
616 616
617# 617#
618# SCSI support type (disk, tape, CD-ROM) 618# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index fa580affc9d6..a46529c6ade3 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -282,8 +282,8 @@ CONFIG_BFIN_ICACHE=y
282CONFIG_BFIN_DCACHE=y 282CONFIG_BFIN_DCACHE=y
283# CONFIG_BFIN_DCACHE_BANKA is not set 283# CONFIG_BFIN_DCACHE_BANKA is not set
284# CONFIG_BFIN_ICACHE_LOCK is not set 284# CONFIG_BFIN_ICACHE_LOCK is not set
285# CONFIG_BFIN_WB is not set 285CONFIG_BFIN_WB=y
286CONFIG_BFIN_WT=y 286# CONFIG_BFIN_WT is not set
287CONFIG_L1_MAX_PIECE=16 287CONFIG_L1_MAX_PIECE=16
288 288
289# 289#
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 606ecfdcc962..09c31418cc08 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,3 +1,4 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3unifdef-y += bfin_sport.h
3unifdef-y += fixed_code.h 4unifdef-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index fe88a2c19213..65a651db5b07 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -1,30 +1,9 @@
1/* 1/*
2 * File: include/asm-blackfin/bfin_sport.h 2 * bfin_sport.h - userspace header for bfin sport driver
3 * Based on:
4 * Author: Roy Huang (roy.huang@analog.com)
5 * 3 *
6 * Created: Thu Aug. 24 2006 4 * Copyright 2004-2008 Analog Devices Inc.
7 * Description:
8 * 5 *
9 * Modified: 6 * Licensed under the GPL-2 or later.
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 7 */
29 8
30#ifndef __BFIN_SPORT_H__ 9#ifndef __BFIN_SPORT_H__
@@ -42,11 +21,10 @@
42#define NORM_FORMAT 0x0 21#define NORM_FORMAT 0x0
43#define ALAW_FORMAT 0x2 22#define ALAW_FORMAT 0x2
44#define ULAW_FORMAT 0x3 23#define ULAW_FORMAT 0x3
45struct sport_register;
46 24
47/* Function driver which use sport must initialize the structure */ 25/* Function driver which use sport must initialize the structure */
48struct sport_config { 26struct sport_config {
49 /*TDM (multichannels), I2S or other mode */ 27 /* TDM (multichannels), I2S or other mode */
50 unsigned int mode:3; 28 unsigned int mode:3;
51 29
52 /* if TDM mode is selected, channels must be set */ 30 /* if TDM mode is selected, channels must be set */
@@ -72,12 +50,18 @@ struct sport_config {
72 int serial_clk; 50 int serial_clk;
73 int fsync_clk; 51 int fsync_clk;
74 52
75 unsigned int data_format:2; /*Normal, u-law or a-law */ 53 unsigned int data_format:2; /* Normal, u-law or a-law */
76 54
77 int word_len; /* How length of the word in bits, 3-32 bits */ 55 int word_len; /* How length of the word in bits, 3-32 bits */
78 int dma_enabled; 56 int dma_enabled;
79}; 57};
80 58
59/* Userspace interface */
60#define SPORT_IOC_MAGIC 'P'
61#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
62
63#ifdef __KERNEL__
64
81struct sport_register { 65struct sport_register {
82 unsigned short tcr1; 66 unsigned short tcr1;
83 unsigned short reserved0; 67 unsigned short reserved0;
@@ -117,9 +101,6 @@ struct sport_register {
117 unsigned long mrcs3; 101 unsigned long mrcs3;
118}; 102};
119 103
120#define SPORT_IOC_MAGIC 'P'
121#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
122
123struct sport_dev { 104struct sport_dev {
124 struct cdev cdev; /* Char device structure */ 105 struct cdev cdev; /* Char device structure */
125 106
@@ -149,6 +130,8 @@ struct sport_dev {
149 struct sport_config config; 130 struct sport_config config;
150}; 131};
151 132
133#endif
134
152#define SPORT_TCR1 0 135#define SPORT_TCR1 0
153#define SPORT_TCR2 1 136#define SPORT_TCR2 1
154#define SPORT_TCLKDIV 2 137#define SPORT_TCLKDIV 2
@@ -169,4 +152,4 @@ struct sport_dev {
169#define SPORT_MRCS2 22 152#define SPORT_MRCS2 22
170#define SPORT_MRCS3 23 153#define SPORT_MRCS3 23
171 154
172#endif /*__BFIN_SPORT_H__*/ 155#endif
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 76f53d8b9a0d..343b56361ec9 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37 37
38#define IPIPE_ARCH_STRING "1.8-00" 38#define IPIPE_ARCH_STRING "1.9-00"
39#define IPIPE_MAJOR_NUMBER 1 39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 8 40#define IPIPE_MINOR_NUMBER 9
41#define IPIPE_PATCH_NUMBER 0 41#define IPIPE_PATCH_NUMBER 0
42 42
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -83,9 +83,9 @@ struct ipipe_sysinfo {
83 "%2 = CYCLES2\n" \ 83 "%2 = CYCLES2\n" \
84 "CC = %2 == %0\n" \ 84 "CC = %2 == %0\n" \
85 "if ! CC jump 1b\n" \ 85 "if ! CC jump 1b\n" \
86 : "=r" (((unsigned long *)&t)[1]), \ 86 : "=d,a" (((unsigned long *)&t)[1]), \
87 "=r" (((unsigned long *)&t)[0]), \ 87 "=d,a" (((unsigned long *)&t)[0]), \
88 "=r" (__cy2) \ 88 "=d,a" (__cy2) \
89 : /*no input*/ : "CC"); \ 89 : /*no input*/ : "CC"); \
90 t; \ 90 t; \
91 }) 91 })
@@ -118,35 +118,40 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
118 118
119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) 119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
120 120
121#define __ipipe_lock_root() \ 121static inline int __ipipe_check_tickdev(const char *devname)
122 set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) 122{
123 return 1;
124}
123 125
124#define __ipipe_unlock_root() \ 126static inline void __ipipe_lock_root(void)
125 clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) 127{
128 set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
129}
130
131static inline void __ipipe_unlock_root(void)
132{
133 clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
134}
126 135
127void __ipipe_enable_pipeline(void); 136void __ipipe_enable_pipeline(void);
128 137
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0) 138#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130 139
131#define __ipipe_sync_pipeline(syncmask) \ 140#define __ipipe_sync_pipeline ___ipipe_sync_pipeline
132 do { \ 141void ___ipipe_sync_pipeline(unsigned long syncmask);
133 struct ipipe_domain *ipd = ipipe_current_domain; \
134 if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
135 __ipipe_sync_stage(syncmask); \
136 } while (0)
137 142
138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); 143void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
139 144
140int __ipipe_get_irq_priority(unsigned irq); 145int __ipipe_get_irq_priority(unsigned irq);
141 146
142int __ipipe_get_irqthread_priority(unsigned irq);
143
144void __ipipe_stall_root_raw(void); 147void __ipipe_stall_root_raw(void);
145 148
146void __ipipe_unstall_root_raw(void); 149void __ipipe_unstall_root_raw(void);
147 150
148void __ipipe_serial_debug(const char *fmt, ...); 151void __ipipe_serial_debug(const char *fmt, ...);
149 152
153asmlinkage void __ipipe_call_irqtail(unsigned long addr);
154
150DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 155DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
151 156
152extern unsigned long __ipipe_core_clock; 157extern unsigned long __ipipe_core_clock;
@@ -162,42 +167,25 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
162 167
163#define __ipipe_run_irqtail() /* Must be a macro */ \ 168#define __ipipe_run_irqtail() /* Must be a macro */ \
164 do { \ 169 do { \
165 asmlinkage void __ipipe_call_irqtail(void); \
166 unsigned long __pending; \ 170 unsigned long __pending; \
167 CSYNC(); \ 171 CSYNC(); \
168 __pending = bfin_read_IPEND(); \ 172 __pending = bfin_read_IPEND(); \
169 if (__pending & 0x8000) { \ 173 if (__pending & 0x8000) { \
170 __pending &= ~0x8010; \ 174 __pending &= ~0x8010; \
171 if (__pending && (__pending & (__pending - 1)) == 0) \ 175 if (__pending && (__pending & (__pending - 1)) == 0) \
172 __ipipe_call_irqtail(); \ 176 __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
173 } \ 177 } \
174 } while (0) 178 } while (0)
175 179
176#define __ipipe_run_isr(ipd, irq) \ 180#define __ipipe_run_isr(ipd, irq) \
177 do { \ 181 do { \
178 if (ipd == ipipe_root_domain) { \ 182 if (ipd == ipipe_root_domain) { \
179 /* \ 183 local_irq_enable_hw(); \
180 * Note: the I-pipe implements a threaded interrupt model on \ 184 if (ipipe_virtual_irq_p(irq)) \
181 * this arch for Linux external IRQs. The interrupt handler we \
182 * call here only wakes up the associated IRQ thread. \
183 */ \
184 if (ipipe_virtual_irq_p(irq)) { \
185 /* No irqtail here; virtual interrupts have no effect \
186 on IPEND so there is no need for processing \
187 deferral. */ \
188 local_irq_enable_nohead(ipd); \
189 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ 185 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
190 local_irq_disable_nohead(ipd); \ 186 else \
191 } else \
192 /* \
193 * No need to run the irqtail here either; \
194 * we can't be preempted by hw IRQs, so \
195 * non-Linux IRQs cannot stack over the short \
196 * thread wakeup code. Which in turn means \
197 * that no irqtail condition could be pending \
198 * for domains above Linux in the pipeline. \
199 */ \
200 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ 187 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
188 local_irq_disable_hw(); \
201 } else { \ 189 } else { \
202 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 190 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
203 local_irq_enable_nohead(ipd); \ 191 local_irq_enable_nohead(ipd); \
@@ -217,42 +205,24 @@ void ipipe_init_irq_threads(void);
217 205
218int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); 206int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219 207
220#define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS) 208#ifdef CONFIG_GENERIC_CLOCKEVENTS
221#define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS) 209#define IRQ_SYSTMR IRQ_CORETMR
222 210#define IRQ_PRIOTMR IRQ_CORETMR
211#else
223#define IRQ_SYSTMR IRQ_TIMER0 212#define IRQ_SYSTMR IRQ_TIMER0
224#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 213#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
214#endif
225 215
226#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) 216#ifdef CONFIG_BF561
227#define PRIO_GPIODEMUX(irq) CONFIG_PFA
228#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
229#define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA
230#elif defined(CONFIG_BF52x)
231#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
232 (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
233 (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
234 -1)
235#elif defined(CONFIG_BF561)
236#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
237 (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
238 (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
239 -1)
240#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) 217#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
241#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) 218#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
242#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) 219#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
243#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() 220#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
244#elif defined(CONFIG_BF54x) 221#elif defined(CONFIG_BF54x)
245#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
246 (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
247 (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
248 (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
249 -1)
250#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) 222#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
251#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) 223#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
252#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) 224#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
253#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) 225#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
254#else
255# error "no PRIO_GPIODEMUX() for this part"
256#endif 226#endif
257 227
258#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) 228#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
@@ -275,4 +245,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
275 245
276#endif /* !CONFIG_IPIPE */ 246#endif /* !CONFIG_IPIPE */
277 247
248#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
249
278#endif /* !__ASM_BLACKFIN_IPIPE_H */ 250#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index cb1025aeabcf..3e8acbd1a3be 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -1,5 +1,5 @@
1/* -*- linux-c -*- 1/* -*- linux-c -*-
2 * include/asm-blackfin/_baseipipe.h 2 * include/asm-blackfin/ipipe_base.h
3 * 3 *
4 * Copyright (C) 2007 Philippe Gerum. 4 * Copyright (C) 2007 Philippe Gerum.
5 * 5 *
@@ -27,8 +27,9 @@
27#define IPIPE_NR_XIRQS NR_IRQS 27#define IPIPE_NR_XIRQS NR_IRQS
28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ 28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
29 29
30/* Blackfin-specific, global domain flags */ 30/* Blackfin-specific, per-cpu pipeline status */
31#define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */ 31#define IPIPE_SYNCDEFER_FLAG 15
32#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
32 33
33 /* Blackfin traps -- i.e. exception vector numbers */ 34 /* Blackfin traps -- i.e. exception vector numbers */
34#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ 35#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
@@ -48,11 +49,6 @@
48 49
49#ifndef __ASSEMBLY__ 50#ifndef __ASSEMBLY__
50 51
51#include <linux/bitops.h>
52
53extern int test_bit(int nr, const void *addr);
54
55
56extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
57 53
58static inline void __ipipe_stall_root(void) 54static inline void __ipipe_stall_root(void)
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 3d977909ce7d..7645e85a5f6f 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -61,20 +61,38 @@ void __ipipe_restore_root(unsigned long flags);
61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) 61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags))
62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) 62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x)
63 63
64#define local_save_flags(x) \ 64#define local_save_flags(x) \
65 do { \ 65 do { \
66 (x) = __ipipe_test_root() ? \ 66 (x) = __ipipe_test_root() ? \
67 __all_masked_irq_flags : bfin_irq_flags; \ 67 __all_masked_irq_flags : bfin_irq_flags; \
68 barrier(); \
68 } while (0) 69 } while (0)
69 70
70#define local_irq_save(x) \ 71#define local_irq_save(x) \
71 do { \ 72 do { \
72 (x) = __ipipe_test_and_stall_root(); \ 73 (x) = __ipipe_test_and_stall_root() ? \
74 __all_masked_irq_flags : bfin_irq_flags; \
75 barrier(); \
76 } while (0)
77
78static inline void local_irq_restore(unsigned long x)
79{
80 barrier();
81 __ipipe_restore_root(x == __all_masked_irq_flags);
82}
83
84#define local_irq_disable() \
85 do { \
86 __ipipe_stall_root(); \
87 barrier(); \
73 } while (0) 88 } while (0)
74 89
75#define local_irq_restore(x) __ipipe_restore_root(x) 90static inline void local_irq_enable(void)
76#define local_irq_disable() __ipipe_stall_root() 91{
77#define local_irq_enable() __ipipe_unstall_root() 92 barrier();
93 __ipipe_unstall_root();
94}
95
78#define irqs_disabled() __ipipe_test_root() 96#define irqs_disabled() __ipipe_test_root()
79 97
80#define local_save_flags_hw(x) \ 98#define local_save_flags_hw(x) \
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h
index 797c0c165069..c94c7bc88c71 100644
--- a/arch/blackfin/include/asm/percpu.h
+++ b/arch/blackfin/include/asm/percpu.h
@@ -3,14 +3,4 @@
3 3
4#include <asm-generic/percpu.h> 4#include <asm-generic/percpu.h>
5 5
6#ifdef CONFIG_MODULES
7#define PERCPU_MODULE_RESERVE 8192
8#else
9#define PERCPU_MODULE_RESERVE 0
10#endif
11
12#define PERCPU_ENOUGH_ROOM \
13 (ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES) + \
14 PERCPU_MODULE_RESERVE)
15
16#endif /* __ARCH_BLACKFIN_PERCPU__ */ 6#endif /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index e721ce55956c..2920087516f2 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -122,6 +122,7 @@ static inline struct thread_info *current_thread_info(void)
122#define TIF_MEMDIE 4 122#define TIF_MEMDIE 4
123#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ 123#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
124#define TIF_FREEZE 6 /* is freezing for suspend */ 124#define TIF_FREEZE 6 /* is freezing for suspend */
125#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
125 126
126/* as above, but as bit values */ 127/* as above, but as bit values */
127#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 128#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void)
130#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 131#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
131#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) 132#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
132#define _TIF_FREEZE (1<<TIF_FREEZE) 133#define _TIF_FREEZE (1<<TIF_FREEZE)
134#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
133 135
134#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ 136#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
135 137
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 4a92a86824b7..fd4d4328a0f2 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -15,13 +15,15 @@ else
15 obj-y += time.o 15 obj-y += time.o
16endif 16endif
17 17
18CFLAGS_kgdb_test.o := -mlong-calls -O0
19
20obj-$(CONFIG_IPIPE) += ipipe.o 18obj-$(CONFIG_IPIPE) += ipipe.o
21obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o 19obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o
22obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o 20obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
23obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 21obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
24obj-$(CONFIG_MODULES) += module.o 22obj-$(CONFIG_MODULES) += module.o
25obj-$(CONFIG_KGDB) += kgdb.o 23obj-$(CONFIG_KGDB) += kgdb.o
26obj-$(CONFIG_KGDB_TESTCASE) += kgdb_test.o 24obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
27obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 25obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
26
27# the kgdb test puts code into L2 and without linker
28# relaxation, we need to force long calls to/from it
29CFLAGS_kgdb_test.o := -mlong-calls -O0
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 0e28f7595733..d6c067782e63 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -53,9 +53,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
53 53
54 i_d = i_i = 0; 54 i_d = i_i = 0;
55 55
56#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
56 /* Set up the zero page. */ 57 /* Set up the zero page. */
57 d_tbl[i_d].addr = 0; 58 d_tbl[i_d].addr = 0;
58 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; 59 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
60 i_tbl[i_i].addr = 0;
61 i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
62#endif
59 63
60 /* Cover kernel memory with 4M pages. */ 64 /* Cover kernel memory with 4M pages. */
61 addr = 0; 65 addr = 0;
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 339be5a3ae6a..a5de8d45424c 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -35,14 +35,8 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/io.h> 36#include <asm/io.h>
37 37
38static int create_irq_threads;
39
40DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 38DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
41 39
42static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask);
43
44static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count);
45
46asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); 40asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
47 41
48static void __ipipe_no_irqtail(void); 42static void __ipipe_no_irqtail(void);
@@ -93,6 +87,7 @@ void __ipipe_enable_pipeline(void)
93 */ 87 */
94void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) 88void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
95{ 89{
90 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
96 struct ipipe_domain *this_domain, *next_domain; 91 struct ipipe_domain *this_domain, *next_domain;
97 struct list_head *head, *pos; 92 struct list_head *head, *pos;
98 int m_ack, s = -1; 93 int m_ack, s = -1;
@@ -104,7 +99,6 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
104 * interrupt. 99 * interrupt.
105 */ 100 */
106 m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); 101 m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
107
108 this_domain = ipipe_current_domain; 102 this_domain = ipipe_current_domain;
109 103
110 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) 104 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control)))
@@ -114,49 +108,28 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
114 next_domain = list_entry(head, struct ipipe_domain, p_link); 108 next_domain = list_entry(head, struct ipipe_domain, p_link);
115 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { 109 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) {
116 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) 110 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL)
117 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); 111 next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
118 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) 112 if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
119 s = __test_and_set_bit(IPIPE_STALL_FLAG, 113 s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
120 &ipipe_root_cpudom_var(status));
121 __ipipe_dispatch_wired(next_domain, irq); 114 __ipipe_dispatch_wired(next_domain, irq);
122 goto finalize; 115 goto out;
123 return;
124 } 116 }
125 } 117 }
126 118
127 /* Ack the interrupt. */ 119 /* Ack the interrupt. */
128 120
129 pos = head; 121 pos = head;
130
131 while (pos != &__ipipe_pipeline) { 122 while (pos != &__ipipe_pipeline) {
132 next_domain = list_entry(pos, struct ipipe_domain, p_link); 123 next_domain = list_entry(pos, struct ipipe_domain, p_link);
133 /*
134 * For each domain handling the incoming IRQ, mark it
135 * as pending in its log.
136 */
137 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { 124 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) {
138 /*
139 * Domains that handle this IRQ are polled for
140 * acknowledging it by decreasing priority
141 * order. The interrupt must be made pending
142 * _first_ in the domain's status flags before
143 * the PIC is unlocked.
144 */
145 __ipipe_set_irq_pending(next_domain, irq); 125 __ipipe_set_irq_pending(next_domain, irq);
146
147 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { 126 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) {
148 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); 127 next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
149 m_ack = 1; 128 m_ack = 1;
150 } 129 }
151 } 130 }
152
153 /*
154 * If the domain does not want the IRQ to be passed
155 * down the interrupt pipe, exit the loop now.
156 */
157 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) 131 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control))
158 break; 132 break;
159
160 pos = next_domain->p_link.next; 133 pos = next_domain->p_link.next;
161 } 134 }
162 135
@@ -166,18 +139,24 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
166 * immediately to the current domain if the interrupt has been 139 * immediately to the current domain if the interrupt has been
167 * marked as 'sticky'. This search does not go beyond the 140 * marked as 'sticky'. This search does not go beyond the
168 * current domain in the pipeline. We also enforce the 141 * current domain in the pipeline. We also enforce the
169 * additional root stage lock (blackfin-specific). */ 142 * additional root stage lock (blackfin-specific).
143 */
144 if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
145 s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
170 146
171 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) 147 /*
172 s = __test_and_set_bit(IPIPE_STALL_FLAG, 148 * If the interrupt preempted the head domain, then do not
173 &ipipe_root_cpudom_var(status)); 149 * even try to walk the pipeline, unless an interrupt is
174finalize: 150 * pending for it.
151 */
152 if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
153 ipipe_head_cpudom_var(irqpend_himask) == 0)
154 goto out;
175 155
176 __ipipe_walk_pipeline(head); 156 __ipipe_walk_pipeline(head);
177 157out:
178 if (!s) 158 if (!s)
179 __clear_bit(IPIPE_STALL_FLAG, 159 __clear_bit(IPIPE_STALL_FLAG, &p->status);
180 &ipipe_root_cpudom_var(status));
181} 160}
182 161
183int __ipipe_check_root(void) 162int __ipipe_check_root(void)
@@ -187,7 +166,7 @@ int __ipipe_check_root(void)
187 166
188void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) 167void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
189{ 168{
190 struct irq_desc *desc = irq_desc + irq; 169 struct irq_desc *desc = irq_to_desc(irq);
191 int prio = desc->ic_prio; 170 int prio = desc->ic_prio;
192 171
193 desc->depth = 0; 172 desc->depth = 0;
@@ -199,7 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc);
199 178
200void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) 179void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
201{ 180{
202 struct irq_desc *desc = irq_desc + irq; 181 struct irq_desc *desc = irq_to_desc(irq);
203 int prio = desc->ic_prio; 182 int prio = desc->ic_prio;
204 183
205 if (ipd != &ipipe_root && 184 if (ipd != &ipipe_root &&
@@ -236,15 +215,18 @@ int __ipipe_syscall_root(struct pt_regs *regs)
236{ 215{
237 unsigned long flags; 216 unsigned long flags;
238 217
239 /* We need to run the IRQ tail hook whenever we don't 218 /*
219 * We need to run the IRQ tail hook whenever we don't
240 * propagate a syscall to higher domains, because we know that 220 * propagate a syscall to higher domains, because we know that
241 * important operations might be pending there (e.g. Xenomai 221 * important operations might be pending there (e.g. Xenomai
242 * deferred rescheduling). */ 222 * deferred rescheduling).
223 */
243 224
244 if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) { 225 if (regs->orig_p0 < NR_syscalls) {
245 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; 226 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
246 hook(); 227 hook();
247 return 0; 228 if ((current->flags & PF_EVNOTIFY) == 0)
229 return 0;
248 } 230 }
249 231
250 /* 232 /*
@@ -312,112 +294,46 @@ int ipipe_trigger_irq(unsigned irq)
312{ 294{
313 unsigned long flags; 295 unsigned long flags;
314 296
297#ifdef CONFIG_IPIPE_DEBUG
315 if (irq >= IPIPE_NR_IRQS || 298 if (irq >= IPIPE_NR_IRQS ||
316 (ipipe_virtual_irq_p(irq) 299 (ipipe_virtual_irq_p(irq)
317 && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) 300 && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
318 return -EINVAL; 301 return -EINVAL;
302#endif
319 303
320 local_irq_save_hw(flags); 304 local_irq_save_hw(flags);
321
322 __ipipe_handle_irq(irq, NULL); 305 __ipipe_handle_irq(irq, NULL);
323
324 local_irq_restore_hw(flags); 306 local_irq_restore_hw(flags);
325 307
326 return 1; 308 return 1;
327} 309}
328 310
329/* Move Linux IRQ to threads. */ 311asmlinkage void __ipipe_sync_root(void)
330
331static int do_irqd(void *__desc)
332{ 312{
333 struct irq_desc *desc = __desc; 313 unsigned long flags;
334 unsigned irq = desc - irq_desc;
335 int thrprio = desc->thr_prio;
336 int thrmask = 1 << thrprio;
337 int cpu = smp_processor_id();
338 cpumask_t cpumask;
339
340 sigfillset(&current->blocked);
341 current->flags |= PF_NOFREEZE;
342 cpumask = cpumask_of_cpu(cpu);
343 set_cpus_allowed(current, cpumask);
344 ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio);
345
346 while (!kthread_should_stop()) {
347 local_irq_disable();
348 if (!(desc->status & IRQ_SCHEDULED)) {
349 set_current_state(TASK_INTERRUPTIBLE);
350resched:
351 local_irq_enable();
352 schedule();
353 local_irq_disable();
354 }
355 __set_current_state(TASK_RUNNING);
356 /*
357 * If higher priority interrupt servers are ready to
358 * run, reschedule immediately. We need this for the
359 * GPIO demux IRQ handler to unmask the interrupt line
360 * _last_, after all GPIO IRQs have run.
361 */
362 if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1)))
363 goto resched;
364 if (--per_cpu(pending_irq_count[thrprio], cpu) == 0)
365 per_cpu(pending_irqthread_mask, cpu) &= ~thrmask;
366 desc->status &= ~IRQ_SCHEDULED;
367 desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs));
368 local_irq_enable();
369 }
370 __set_current_state(TASK_RUNNING);
371 return 0;
372}
373 314
374static void kick_irqd(unsigned irq, void *cookie) 315 BUG_ON(irqs_disabled());
375{
376 struct irq_desc *desc = irq_desc + irq;
377 int thrprio = desc->thr_prio;
378 int thrmask = 1 << thrprio;
379 int cpu = smp_processor_id();
380
381 if (!(desc->status & IRQ_SCHEDULED)) {
382 desc->status |= IRQ_SCHEDULED;
383 per_cpu(pending_irqthread_mask, cpu) |= thrmask;
384 ++per_cpu(pending_irq_count[thrprio], cpu);
385 wake_up_process(desc->thread);
386 }
387}
388 316
389int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc) 317 local_irq_save_hw(flags);
390{
391 if (desc->thread || !create_irq_threads)
392 return 0;
393
394 desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq);
395 if (desc->thread == NULL) {
396 printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq);
397 return -ENOMEM;
398 }
399 318
400 wake_up_process(desc->thread); 319 clear_thread_flag(TIF_IRQ_SYNC);
401 320
402 desc->thr_handler = ipipe_root_domain->irqs[irq].handler; 321 if (ipipe_root_cpudom_var(irqpend_himask) != 0)
403 ipipe_root_domain->irqs[irq].handler = &kick_irqd; 322 __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
404 323
405 return 0; 324 local_irq_restore_hw(flags);
406} 325}
407 326
408void __init ipipe_init_irq_threads(void) 327void ___ipipe_sync_pipeline(unsigned long syncmask)
409{ 328{
410 unsigned irq; 329 struct ipipe_domain *ipd = ipipe_current_domain;
411 struct irq_desc *desc;
412
413 create_irq_threads = 1;
414 330
415 for (irq = 0; irq < NR_IRQS; irq++) { 331 if (ipd == ipipe_root_domain) {
416 desc = irq_desc + irq; 332 if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
417 if (desc->action != NULL || 333 return;
418 (desc->status & IRQ_NOREQUEST) != 0)
419 ipipe_start_irq_thread(irq, desc);
420 } 334 }
335
336 __ipipe_sync_stage(syncmask);
421} 337}
422 338
423EXPORT_SYMBOL(show_stack); 339EXPORT_SYMBOL(show_stack);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 23e9aa080710..1ab5b532ec72 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -149,11 +149,15 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
149#endif 149#endif
150 generic_handle_irq(irq); 150 generic_handle_irq(irq);
151 151
152#ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */ 152#ifndef CONFIG_IPIPE
153 /* If we're the only interrupt running (ignoring IRQ15 which is for 153 /*
154 syscalls), lower our priority to IRQ14 so that softirqs run at 154 * If we're the only interrupt running (ignoring IRQ15 which
155 that level. If there's another, lower-level interrupt, irq_exit 155 * is for syscalls), lower our priority to IRQ14 so that
156 will defer softirqs to that. */ 156 * softirqs run at that level. If there's another,
157 * lower-level interrupt, irq_exit will defer softirqs to
158 * that. If the interrupt pipeline is enabled, we are already
159 * running at IRQ14 priority, so we don't need this code.
160 */
157 CSYNC(); 161 CSYNC();
158 pending = bfin_read_IPEND() & ~0x8000; 162 pending = bfin_read_IPEND() & ~0x8000;
159 other_ints = pending & (pending - 1); 163 other_ints = pending & (pending - 1);
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 3dba9c17304a..dbcf3e45cb0b 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -20,6 +20,7 @@
20static char cmdline[256]; 20static char cmdline[256];
21static unsigned long len; 21static unsigned long len;
22 22
23#ifndef CONFIG_SMP
23static int num1 __attribute__((l1_data)); 24static int num1 __attribute__((l1_data));
24 25
25void kgdb_l1_test(void) __attribute__((l1_text)); 26void kgdb_l1_test(void) __attribute__((l1_text));
@@ -32,6 +33,8 @@ void kgdb_l1_test(void)
32 printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); 33 printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
33 return ; 34 return ;
34} 35}
36#endif
37
35#if L2_LENGTH 38#if L2_LENGTH
36 39
37static int num2 __attribute__((l2)); 40static int num2 __attribute__((l2));
@@ -59,10 +62,12 @@ int kgdb_test(char *name, int len, int count, int z)
59static int test_proc_output(char *buf) 62static int test_proc_output(char *buf)
60{ 63{
61 kgdb_test("hello world!", 12, 0x55, 0x10); 64 kgdb_test("hello world!", 12, 0x55, 0x10);
65#ifndef CONFIG_SMP
62 kgdb_l1_test(); 66 kgdb_l1_test();
63 #if L2_LENGTH 67#endif
68#if L2_LENGTH
64 kgdb_l2_test(); 69 kgdb_l2_test();
65 #endif 70#endif
66 71
67 return 0; 72 return 0;
68} 73}
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 594e325b40e4..d76618db50df 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -45,6 +45,7 @@
45#include <asm/asm-offsets.h> 45#include <asm/asm-offsets.h>
46#include <asm/dma.h> 46#include <asm/dma.h>
47#include <asm/fixed_code.h> 47#include <asm/fixed_code.h>
48#include <asm/cacheflush.h>
48#include <asm/mem_map.h> 49#include <asm/mem_map.h>
49 50
50#define TEXT_OFFSET 0 51#define TEXT_OFFSET 0
@@ -240,7 +241,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
240 241
241 } else if (addr >= FIXED_CODE_START 242 } else if (addr >= FIXED_CODE_START
242 && addr + sizeof(tmp) <= FIXED_CODE_END) { 243 && addr + sizeof(tmp) <= FIXED_CODE_END) {
243 memcpy(&tmp, (const void *)(addr), sizeof(tmp)); 244 copy_from_user_page(0, 0, 0, &tmp, (const void *)(addr), sizeof(tmp));
244 copied = sizeof(tmp); 245 copied = sizeof(tmp);
245 246
246 } else 247 } else
@@ -320,7 +321,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
320 321
321 } else if (addr >= FIXED_CODE_START 322 } else if (addr >= FIXED_CODE_START
322 && addr + sizeof(data) <= FIXED_CODE_END) { 323 && addr + sizeof(data) <= FIXED_CODE_END) {
323 memcpy((void *)(addr), &data, sizeof(data)); 324 copy_to_user_page(0, 0, 0, (void *)(addr), &data, sizeof(data));
324 copied = sizeof(data); 325 copied = sizeof(data);
325 326
326 } else 327 } else
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index e5c116230800..a58687bdee6a 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -889,6 +889,10 @@ void __init setup_arch(char **cmdline_p)
889 CPU, bfin_revid()); 889 CPU, bfin_revid());
890 } 890 }
891 891
892 /* We can't run on BF548-0.1 due to ANOMALY 05000448 */
893 if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
894 panic("You can't run on this processor due to 05000448\n");
895
892 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); 896 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
893 897
894 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", 898 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
@@ -1141,12 +1145,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1141 icache_size = 0; 1145 icache_size = 0;
1142 1146
1143 seq_printf(m, "cache size\t: %d KB(L1 icache) " 1147 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1144 "%d KB(L1 dcache-%s) %d KB(L2 cache)\n", 1148 "%d KB(L1 dcache%s) %d KB(L2 cache)\n",
1145 icache_size, dcache_size, 1149 icache_size, dcache_size,
1146#if defined CONFIG_BFIN_WB 1150#if defined CONFIG_BFIN_WB
1147 "wb" 1151 "-wb"
1148#elif defined CONFIG_BFIN_WT 1152#elif defined CONFIG_BFIN_WT
1149 "wt" 1153 "-wt"
1150#endif 1154#endif
1151 "", 0); 1155 "", 0);
1152 1156
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 172b4c588467..1bbacfbd4c5d 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -134,7 +134,10 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
134 134
135 write_seqlock(&xtime_lock); 135 write_seqlock(&xtime_lock);
136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) 136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
137/* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */ 137 /*
138 * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is
139 * enabled.
140 */
138 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { 141 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) {
139#endif 142#endif
140 do_timer(1); 143 do_timer(1);
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index 0e175342112e..41f2eacfef20 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -113,7 +113,6 @@ static struct platform_device bfin_mac_device = {
113 .name = "bfin_mac", 113 .name = "bfin_mac",
114 .dev.platform_data = &bfin_mii_bus, 114 .dev.platform_data = &bfin_mii_bus,
115}; 115};
116#endif
117 116
118#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 117#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
119static struct dsa_platform_data ksz8893m_switch_data = { 118static struct dsa_platform_data ksz8893m_switch_data = {
@@ -132,6 +131,7 @@ static struct platform_device ksz8893m_switch_device = {
132 .dev.platform_data = &ksz8893m_switch_data, 131 .dev.platform_data = &ksz8893m_switch_data,
133}; 132};
134#endif 133#endif
134#endif
135 135
136#if defined(CONFIG_MTD_M25P80) \ 136#if defined(CONFIG_MTD_M25P80) \
137 || defined(CONFIG_MTD_M25P80_MODULE) 137 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -171,6 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
171}; 171};
172#endif 172#endif
173 173
174#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
174#if defined(CONFIG_NET_DSA_KSZ8893M) \ 175#if defined(CONFIG_NET_DSA_KSZ8893M) \
175 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 176 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
176/* SPI SWITCH CHIP */ 177/* SPI SWITCH CHIP */
@@ -179,10 +180,11 @@ static struct bfin5xx_spi_chip spi_switch_info = {
179 .bits_per_word = 8, 180 .bits_per_word = 8,
180}; 181};
181#endif 182#endif
183#endif
182 184
183#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 185#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
184static struct bfin5xx_spi_chip spi_mmc_chip_info = { 186static struct bfin5xx_spi_chip mmc_spi_chip_info = {
185 .enable_dma = 1, 187 .enable_dma = 0,
186 .bits_per_word = 8, 188 .bits_per_word = 8,
187}; 189};
188#endif 190#endif
@@ -259,6 +261,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
259 }, 261 },
260#endif 262#endif
261 263
264#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
262#if defined(CONFIG_NET_DSA_KSZ8893M) \ 265#if defined(CONFIG_NET_DSA_KSZ8893M) \
263 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 266 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
264 { 267 {
@@ -271,24 +274,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
271 .mode = SPI_MODE_3, 274 .mode = SPI_MODE_3,
272 }, 275 },
273#endif 276#endif
277#endif
274 278
275#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 279#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
276 { 280 {
277 .modalias = "spi_mmc_dummy", 281 .modalias = "mmc_spi",
278 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 282 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
279 .bus_num = 0, 283 .bus_num = 0,
280 .chip_select = 0, 284 .chip_select = 5,
281 .platform_data = NULL, 285 .controller_data = &mmc_spi_chip_info,
282 .controller_data = &spi_mmc_chip_info,
283 .mode = SPI_MODE_3,
284 },
285 {
286 .modalias = "spi_mmc",
287 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
288 .bus_num = 0,
289 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
290 .platform_data = NULL,
291 .controller_data = &spi_mmc_chip_info,
292 .mode = SPI_MODE_3, 286 .mode = SPI_MODE_3,
293 }, 287 },
294#endif 288#endif
@@ -630,11 +624,10 @@ static struct platform_device *stamp_devices[] __initdata = {
630#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 624#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
631 &bfin_mii_bus, 625 &bfin_mii_bus,
632 &bfin_mac_device, 626 &bfin_mac_device,
633#endif
634
635#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 627#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
636 &ksz8893m_switch_device, 628 &ksz8893m_switch_device,
637#endif 629#endif
630#endif
638 631
639#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 632#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
640 &bfin_spi0_device, 633 &bfin_spi0_device,
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index e5b4bef0edae..c847bb101076 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf518/anomaly.h 2 * File: include/asm-blackfin/mach-bf518/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - ???? 10 * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -19,6 +19,8 @@
19#define ANOMALY_05000122 (1) 19#define ANOMALY_05000122 (1)
20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
21#define ANOMALY_05000245 (1) 21#define ANOMALY_05000245 (1)
22/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
23#define ANOMALY_05000254 (1)
22/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
23#define ANOMALY_05000265 (1) 25#define ANOMALY_05000265 (1)
24/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 26/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
@@ -53,6 +55,12 @@
53#define ANOMALY_05000443 (1) 55#define ANOMALY_05000443 (1)
54/* Incorrect L1 Instruction Bank B Memory Map Location */ 56/* Incorrect L1 Instruction Bank B Memory Map Location */
55#define ANOMALY_05000444 (1) 57#define ANOMALY_05000444 (1)
58/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
59#define ANOMALY_05000452 (1)
60/* PWM_TRIPB Signal Not Available on PG10 */
61#define ANOMALY_05000453 (1)
62/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
63#define ANOMALY_05000455 (1)
56 64
57/* Anomalies that don't exist on this proc */ 65/* Anomalies that don't exist on this proc */
58#define ANOMALY_05000125 (0) 66#define ANOMALY_05000125 (0)
@@ -65,15 +73,20 @@
65#define ANOMALY_05000263 (0) 73#define ANOMALY_05000263 (0)
66#define ANOMALY_05000266 (0) 74#define ANOMALY_05000266 (0)
67#define ANOMALY_05000273 (0) 75#define ANOMALY_05000273 (0)
76#define ANOMALY_05000278 (0)
68#define ANOMALY_05000285 (0) 77#define ANOMALY_05000285 (0)
78#define ANOMALY_05000305 (0)
69#define ANOMALY_05000307 (0) 79#define ANOMALY_05000307 (0)
70#define ANOMALY_05000311 (0) 80#define ANOMALY_05000311 (0)
71#define ANOMALY_05000312 (0) 81#define ANOMALY_05000312 (0)
72#define ANOMALY_05000323 (0) 82#define ANOMALY_05000323 (0)
73#define ANOMALY_05000353 (0) 83#define ANOMALY_05000353 (0)
74#define ANOMALY_05000363 (0) 84#define ANOMALY_05000363 (0)
85#define ANOMALY_05000380 (0)
75#define ANOMALY_05000386 (0) 86#define ANOMALY_05000386 (0)
76#define ANOMALY_05000412 (0) 87#define ANOMALY_05000412 (0)
77#define ANOMALY_05000432 (0) 88#define ANOMALY_05000432 (0)
89#define ANOMALY_05000447 (0)
90#define ANOMALY_05000448 (0)
78 91
79#endif 92#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index b50a63b975a2..e21c1c3e4ec7 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 856c097b5317..48e69eecdba4 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -487,9 +487,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
487}; 487};
488#endif 488#endif
489 489
490#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 490#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
491static struct bfin5xx_spi_chip spi_mmc_chip_info = { 491static struct bfin5xx_spi_chip mmc_spi_chip_info = {
492 .enable_dma = 1, 492 .enable_dma = 0,
493 .bits_per_word = 8, 493 .bits_per_word = 8,
494}; 494};
495#endif 495#endif
@@ -585,23 +585,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
585 .controller_data = &ad9960_spi_chip_info, 585 .controller_data = &ad9960_spi_chip_info,
586 }, 586 },
587#endif 587#endif
588#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 588#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
589 { 589 {
590 .modalias = "spi_mmc_dummy", 590 .modalias = "mmc_spi",
591 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 591 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
592 .bus_num = 0,
593 .chip_select = 0,
594 .platform_data = NULL,
595 .controller_data = &spi_mmc_chip_info,
596 .mode = SPI_MODE_3,
597 },
598 {
599 .modalias = "spi_mmc",
600 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
601 .bus_num = 0, 592 .bus_num = 0,
602 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 593 .chip_select = 5,
603 .platform_data = NULL, 594 .controller_data = &mmc_spi_chip_info,
604 .controller_data = &spi_mmc_chip_info,
605 .mode = SPI_MODE_3, 595 .mode = SPI_MODE_3,
606 }, 596 },
607#endif 597#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 83606fcdde27..7fe480e4ebe8 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -256,9 +256,9 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
256}; 256};
257#endif 257#endif
258 258
259#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 259#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
260static struct bfin5xx_spi_chip spi_mmc_chip_info = { 260static struct bfin5xx_spi_chip mmc_spi_chip_info = {
261 .enable_dma = 1, 261 .enable_dma = 0,
262 .bits_per_word = 8, 262 .bits_per_word = 8,
263}; 263};
264#endif 264#endif
@@ -366,23 +366,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
366 }, 366 },
367#endif 367#endif
368 368
369#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 369#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
370 { 370 {
371 .modalias = "spi_mmc_dummy", 371 .modalias = "mmc_spi",
372 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 372 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
373 .bus_num = 0, 373 .bus_num = 0,
374 .chip_select = 0, 374 .chip_select = 5,
375 .platform_data = NULL, 375 .controller_data = &mmc_spi_chip_info,
376 .controller_data = &spi_mmc_chip_info,
377 .mode = SPI_MODE_3,
378 },
379 {
380 .modalias = "spi_mmc",
381 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
382 .bus_num = 0,
383 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
384 .platform_data = NULL,
385 .controller_data = &spi_mmc_chip_info,
386 .mode = SPI_MODE_3, 376 .mode = SPI_MODE_3,
387 }, 377 },
388#endif 378#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 035e8d835058..df6808d8a6ef 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf527/anomaly.h 2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -167,12 +167,16 @@
167#define ANOMALY_05000263 (0) 167#define ANOMALY_05000263 (0)
168#define ANOMALY_05000266 (0) 168#define ANOMALY_05000266 (0)
169#define ANOMALY_05000273 (0) 169#define ANOMALY_05000273 (0)
170#define ANOMALY_05000278 (0)
170#define ANOMALY_05000285 (0) 171#define ANOMALY_05000285 (0)
172#define ANOMALY_05000305 (0)
171#define ANOMALY_05000307 (0) 173#define ANOMALY_05000307 (0)
172#define ANOMALY_05000311 (0) 174#define ANOMALY_05000311 (0)
173#define ANOMALY_05000312 (0) 175#define ANOMALY_05000312 (0)
174#define ANOMALY_05000323 (0) 176#define ANOMALY_05000323 (0)
175#define ANOMALY_05000363 (0) 177#define ANOMALY_05000363 (0)
176#define ANOMALY_05000412 (0) 178#define ANOMALY_05000412 (0)
179#define ANOMALY_05000447 (0)
180#define ANOMALY_05000448 (0)
177 181
178#endif 182#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index 75722d6008b0..e8c41fd842b5 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig
index 308c98dc5aba..8d8b3e7321e6 100644
--- a/arch/blackfin/mach-bf533/boards/Kconfig
+++ b/arch/blackfin/mach-bf533/boards/Kconfig
@@ -38,9 +38,4 @@ config BFIN532_IP0X
38 help 38 help
39 Core support for IP04/IP04 open hardware IP-PBX. 39 Core support for IP04/IP04 open hardware IP-PBX.
40 40
41config GENERIC_BF533_BOARD
42 bool "Generic"
43 help
44 Generic or Custom board support.
45
46endchoice 41endchoice
diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile
index 9afbe72b484f..ff1e832f80d2 100644
--- a/arch/blackfin/mach-bf533/boards/Makefile
+++ b/arch/blackfin/mach-bf533/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf533/boards/Makefile 2# arch/blackfin/mach-bf533/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN533_STAMP) += stamp.o 5obj-$(CONFIG_BFIN533_STAMP) += stamp.o
7obj-$(CONFIG_BFIN532_IP0X) += ip0x.o 6obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
8obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o 7obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 015c18f85e7f..0765872a8ada 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -101,9 +101,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
101}; 101};
102#endif 102#endif
103 103
104#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 104#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
105static struct bfin5xx_spi_chip spi_mmc_chip_info = { 105static struct bfin5xx_spi_chip mmc_spi_chip_info = {
106 .enable_dma = 1, 106 .enable_dma = 0,
107 .bits_per_word = 8, 107 .bits_per_word = 8,
108}; 108};
109#endif 109#endif
@@ -129,23 +129,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
129 }, 129 },
130#endif 130#endif
131 131
132#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 132#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
133 {
134 .modalias = "spi_mmc_dummy",
135 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
136 .bus_num = 0,
137 .chip_select = 0,
138 .platform_data = NULL,
139 .controller_data = &spi_mmc_chip_info,
140 .mode = SPI_MODE_3,
141 },
142 { 133 {
143 .modalias = "spi_mmc", 134 .modalias = "mmc_spi",
144 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 135 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
145 .bus_num = 0, 136 .bus_num = 0,
146 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 137 .chip_select = 5,
147 .platform_data = NULL, 138 .controller_data = &mmc_spi_chip_info,
148 .controller_data = &spi_mmc_chip_info,
149 .mode = SPI_MODE_3, 139 .mode = SPI_MODE_3,
150 }, 140 },
151#endif 141#endif
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index e7061c7e8c42..e8974878d8c2 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -96,9 +96,9 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
96}; 96};
97#endif 97#endif
98 98
99#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 99#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
100static struct bfin5xx_spi_chip spi_mmc_chip_info = { 100static struct bfin5xx_spi_chip mmc_spi_chip_info = {
101 .enable_dma = 1, 101 .enable_dma = 0,
102 .bits_per_word = 8, 102 .bits_per_word = 8,
103}; 103};
104#endif 104#endif
@@ -138,23 +138,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
138 }, 138 },
139#endif 139#endif
140 140
141#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 141#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
142 {
143 .modalias = "spi_mmc_dummy",
144 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
145 .bus_num = 0,
146 .chip_select = 0,
147 .platform_data = NULL,
148 .controller_data = &spi_mmc_chip_info,
149 .mode = SPI_MODE_3,
150 },
151 { 142 {
152 .modalias = "spi_mmc", 143 .modalias = "mmc_spi",
153 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 144 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
154 .bus_num = 0, 145 .bus_num = 0,
155 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 146 .chip_select = 5,
156 .platform_data = NULL, 147 .controller_data = &mmc_spi_chip_info,
157 .controller_data = &spi_mmc_chip_info,
158 .mode = SPI_MODE_3, 148 .mode = SPI_MODE_3,
159 }, 149 },
160#endif 150#endif
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
deleted file mode 100644
index 986eeec53b1f..000000000000
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf533/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created: 2005
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/irq.h>
34
35/*
36 * Name the Board for the /proc/cpuinfo
37 */
38const char bfin_board_name[] = "UNKNOWN BOARD";
39
40#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
41static struct platform_device rtc_device = {
42 .name = "rtc-bfin",
43 .id = -1,
44};
45#endif
46
47/*
48 * Driver needs to know address, irq and flag pin.
49 */
50#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
51static struct resource smc91x_resources[] = {
52 {
53 .start = 0x20300300,
54 .end = 0x20300300 + 16,
55 .flags = IORESOURCE_MEM,
56 }, {
57 .start = IRQ_PROG_INTB,
58 .end = IRQ_PROG_INTB,
59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
60 }, {
61 .start = IRQ_PF7,
62 .end = IRQ_PF7,
63 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
64 },
65};
66
67static struct platform_device smc91x_device = {
68 .name = "smc91x",
69 .id = 0,
70 .num_resources = ARRAY_SIZE(smc91x_resources),
71 .resource = smc91x_resources,
72};
73#endif
74
75#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
76#ifdef CONFIG_BFIN_SIR0
77static struct resource bfin_sir0_resources[] = {
78 {
79 .start = 0xFFC00400,
80 .end = 0xFFC004FF,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .start = IRQ_UART0_RX,
85 .end = IRQ_UART0_RX+1,
86 .flags = IORESOURCE_IRQ,
87 },
88 {
89 .start = CH_UART0_RX,
90 .end = CH_UART0_RX+1,
91 .flags = IORESOURCE_DMA,
92 },
93};
94
95static struct platform_device bfin_sir0_device = {
96 .name = "bfin_sir",
97 .id = 0,
98 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
99 .resource = bfin_sir0_resources,
100};
101#endif
102#endif
103
104static struct platform_device *generic_board_devices[] __initdata = {
105#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
106 &rtc_device,
107#endif
108
109#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
110 &smc91x_device,
111#endif
112
113#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
114#ifdef CONFIG_BFIN_SIR0
115 &bfin_sir0_device,
116#endif
117#endif
118};
119
120static int __init generic_board_init(void)
121{
122 printk(KERN_INFO "%s(): registering device resources\n", __func__);
123 return platform_add_devices(generic_board_devices, ARRAY_SIZE(generic_board_devices));
124}
125
126arch_initcall(generic_board_init);
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index e30b1b7d1442..f19b63378b12 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -127,8 +127,8 @@ static struct platform_device dm9000_device2 = {
127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
128/* all SPI peripherals info goes here */ 128/* all SPI peripherals info goes here */
129 129
130#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 130#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
131static struct bfin5xx_spi_chip spi_mmc_chip_info = { 131static struct bfin5xx_spi_chip mmc_spi_chip_info = {
132/* 132/*
133 * CPOL (Clock Polarity) 133 * CPOL (Clock Polarity)
134 * 0 - Active high SCK 134 * 0 - Active high SCK
@@ -152,14 +152,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
152/* Notice: for blackfin, the speed_hz is the value of register 152/* Notice: for blackfin, the speed_hz is the value of register
153 * SPI_BAUD, not the real baudrate */ 153 * SPI_BAUD, not the real baudrate */
154static struct spi_board_info bfin_spi_board_info[] __initdata = { 154static struct spi_board_info bfin_spi_board_info[] __initdata = {
155#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 155#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
156 { 156 {
157 .modalias = "spi_mmc", 157 .modalias = "mmc_spi",
158 .max_speed_hz = 2, 158 .max_speed_hz = 2,
159 .bus_num = 1, 159 .bus_num = 1,
160 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 160 .chip_select = 5,
161 .platform_data = NULL, 161 .controller_data = &mmc_spi_chip_info,
162 .controller_data = &spi_mmc_chip_info,
163 }, 162 },
164#endif 163#endif
165}; 164};
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 0d3a03429fb9..1cf893e2e55b 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf533/anomaly.h 2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -160,7 +160,7 @@
160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) 160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 163/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
@@ -278,9 +278,12 @@
278#define ANOMALY_05000266 (0) 278#define ANOMALY_05000266 (0)
279#define ANOMALY_05000323 (0) 279#define ANOMALY_05000323 (0)
280#define ANOMALY_05000353 (1) 280#define ANOMALY_05000353 (1)
281#define ANOMALY_05000380 (0)
281#define ANOMALY_05000386 (1) 282#define ANOMALY_05000386 (1)
282#define ANOMALY_05000412 (0) 283#define ANOMALY_05000412 (0)
283#define ANOMALY_05000432 (0) 284#define ANOMALY_05000432 (0)
284#define ANOMALY_05000435 (0) 285#define ANOMALY_05000435 (0)
286#define ANOMALY_05000447 (0)
287#define ANOMALY_05000448 (0)
285 288
286#endif 289#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index f3d9e495230c..5f517f53b0fd 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
134 CH_UART_TX, 134 CH_UART_TX,
135 CH_UART_RX, 135 CH_UART_RX,
136#endif 136#endif
137#ifdef CONFIG_BFIN_UART0_CTSRTS 137#ifdef CONFIG_SERIAL_BFIN_CTSRTS
138 CONFIG_UART0_CTS_PIN, 138 CONFIG_UART0_CTS_PIN,
139 CONFIG_UART0_RTS_PIN, 139 CONFIG_UART0_RTS_PIN,
140#endif 140#endif
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 42a57b0acb29..77c59da87e85 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -33,9 +33,4 @@ config CAMSIG_MINOTAUR
33 help 33 help
34 Board supply package for CSP Minotaur 34 Board supply package for CSP Minotaur
35 35
36config GENERIC_BF537_BOARD
37 bool "Generic"
38 help
39 Generic or Custom board support.
40
41endchoice 36endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7168cc14afd8..68b98a7af6a6 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf537/boards/Makefile 2# arch/blackfin/mach-bf537/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF537_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN537_STAMP) += stamp.o 5obj-$(CONFIG_BFIN537_STAMP) += stamp.o
7obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o 6obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o 7obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index 9cd8fb2a30d3..41c75b9bfac0 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
108}; 108};
109#endif 109#endif
110 110
111#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 111#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
112static struct bfin5xx_spi_chip spi_mmc_chip_info = { 112static struct bfin5xx_spi_chip mmc_spi_chip_info = {
113 .enable_dma = 1, 113 .enable_dma = 0,
114 .bits_per_word = 8, 114 .bits_per_word = 8,
115}; 115};
116#endif 116#endif
@@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
160 }, 160 },
161#endif 161#endif
162 162
163#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 163#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
164 {
165 .modalias = "spi_mmc_dummy",
166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
167 .bus_num = 0,
168 .chip_select = 7,
169 .platform_data = NULL,
170 .controller_data = &spi_mmc_chip_info,
171 .mode = SPI_MODE_3,
172 },
173 { 164 {
174 .modalias = "spi_mmc", 165 .modalias = "mmc_spi",
175 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 166 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
176 .bus_num = 0, 167 .bus_num = 0,
177 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 168 .chip_select = 1,
178 .platform_data = NULL, 169 .controller_data = &mmc_spi_chip_info,
179 .controller_data = &spi_mmc_chip_info,
180 .mode = SPI_MODE_3, 170 .mode = SPI_MODE_3,
181 }, 171 },
182#endif 172#endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
deleted file mode 100644
index da710fdc4569..000000000000
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ /dev/null
@@ -1,745 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/etherdevice.h>
33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
35#include <linux/mtd/partitions.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
39#include <linux/usb/isp1362.h>
40#endif
41#include <linux/irq.h>
42#include <linux/interrupt.h>
43#include <linux/usb/sl811.h>
44#include <asm/dma.h>
45#include <asm/bfin5xx_spi.h>
46#include <asm/reboot.h>
47#include <asm/portmux.h>
48#include <linux/spi/ad7877.h>
49
50/*
51 * Name the Board for the /proc/cpuinfo
52 */
53const char bfin_board_name[] = "UNKNOWN BOARD";
54
55/*
56 * Driver needs to know address, irq and flag pin.
57 */
58
59#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
60#include <linux/usb/isp1760.h>
61static struct resource bfin_isp1760_resources[] = {
62 [0] = {
63 .start = 0x203C0000,
64 .end = 0x203C0000 + 0x000fffff,
65 .flags = IORESOURCE_MEM,
66 },
67 [1] = {
68 .start = IRQ_PF7,
69 .end = IRQ_PF7,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct isp1760_platform_data isp1760_priv = {
75 .is_isp1761 = 0,
76 .port1_disable = 0,
77 .bus_width_16 = 1,
78 .port1_otg = 0,
79 .analog_oc = 0,
80 .dack_polarity_high = 0,
81 .dreq_polarity_high = 0,
82};
83
84static struct platform_device bfin_isp1760_device = {
85 .name = "isp1760-hcd",
86 .id = 0,
87 .dev = {
88 .platform_data = &isp1760_priv,
89 },
90 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
91 .resource = bfin_isp1760_resources,
92};
93#endif
94
95#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
96static struct resource bfin_pcmcia_cf_resources[] = {
97 {
98 .start = 0x20310000, /* IO PORT */
99 .end = 0x20312000,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = 0x20311000, /* Attribute Memory */
103 .end = 0x20311FFF,
104 .flags = IORESOURCE_MEM,
105 }, {
106 .start = IRQ_PF4,
107 .end = IRQ_PF4,
108 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
109 }, {
110 .start = 6, /* Card Detect PF6 */
111 .end = 6,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device bfin_pcmcia_cf_device = {
117 .name = "bfin_cf_pcmcia",
118 .id = -1,
119 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
120 .resource = bfin_pcmcia_cf_resources,
121};
122#endif
123
124#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
125static struct platform_device rtc_device = {
126 .name = "rtc-bfin",
127 .id = -1,
128};
129#endif
130
131#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
132static struct resource smc91x_resources[] = {
133 {
134 .name = "smc91x-regs",
135 .start = 0x20300300,
136 .end = 0x20300300 + 16,
137 .flags = IORESOURCE_MEM,
138 }, {
139
140 .start = IRQ_PF7,
141 .end = IRQ_PF7,
142 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
143 },
144};
145static struct platform_device smc91x_device = {
146 .name = "smc91x",
147 .id = 0,
148 .num_resources = ARRAY_SIZE(smc91x_resources),
149 .resource = smc91x_resources,
150};
151#endif
152
153#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
154static struct resource dm9000_resources[] = {
155 [0] = {
156 .start = 0x203FB800,
157 .end = 0x203FB800 + 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = 0x203FB800 + 4,
162 .end = 0x203FB800 + 5,
163 .flags = IORESOURCE_MEM,
164 },
165 [2] = {
166 .start = IRQ_PF9,
167 .end = IRQ_PF9,
168 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
169 },
170};
171
172static struct platform_device dm9000_device = {
173 .name = "dm9000",
174 .id = -1,
175 .num_resources = ARRAY_SIZE(dm9000_resources),
176 .resource = dm9000_resources,
177};
178#endif
179
180#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
181static struct resource sl811_hcd_resources[] = {
182 {
183 .start = 0x20340000,
184 .end = 0x20340000,
185 .flags = IORESOURCE_MEM,
186 }, {
187 .start = 0x20340004,
188 .end = 0x20340004,
189 .flags = IORESOURCE_MEM,
190 }, {
191 .start = CONFIG_USB_SL811_BFIN_IRQ,
192 .end = CONFIG_USB_SL811_BFIN_IRQ,
193 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
194 },
195};
196
197#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
198void sl811_port_power(struct device *dev, int is_on)
199{
200 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
201 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
202
203}
204#endif
205
206static struct sl811_platform_data sl811_priv = {
207 .potpg = 10,
208 .power = 250, /* == 500mA */
209#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
210 .port_power = &sl811_port_power,
211#endif
212};
213
214static struct platform_device sl811_hcd_device = {
215 .name = "sl811-hcd",
216 .id = 0,
217 .dev = {
218 .platform_data = &sl811_priv,
219 },
220 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
221 .resource = sl811_hcd_resources,
222};
223#endif
224
225#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
226static struct resource isp1362_hcd_resources[] = {
227 {
228 .start = 0x20360000,
229 .end = 0x20360000,
230 .flags = IORESOURCE_MEM,
231 }, {
232 .start = 0x20360004,
233 .end = 0x20360004,
234 .flags = IORESOURCE_MEM,
235 }, {
236 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
237 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
238 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
239 },
240};
241
242static struct isp1362_platform_data isp1362_priv = {
243 .sel15Kres = 1,
244 .clknotstop = 0,
245 .oc_enable = 0,
246 .int_act_high = 0,
247 .int_edge_triggered = 0,
248 .remote_wakeup_connected = 0,
249 .no_power_switching = 1,
250 .power_switching_mode = 0,
251};
252
253static struct platform_device isp1362_hcd_device = {
254 .name = "isp1362-hcd",
255 .id = 0,
256 .dev = {
257 .platform_data = &isp1362_priv,
258 },
259 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
260 .resource = isp1362_hcd_resources,
261};
262#endif
263
264#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
265static struct platform_device bfin_mii_bus = {
266 .name = "bfin_mii_bus",
267};
268
269static struct platform_device bfin_mac_device = {
270 .name = "bfin_mac",
271 .dev.platform_data = &bfin_mii_bus,
272};
273#endif
274
275#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
276static struct resource net2272_bfin_resources[] = {
277 {
278 .start = 0x20300000,
279 .end = 0x20300000 + 0x100,
280 .flags = IORESOURCE_MEM,
281 }, {
282 .start = IRQ_PF7,
283 .end = IRQ_PF7,
284 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
285 },
286};
287
288static struct platform_device net2272_bfin_device = {
289 .name = "net2272",
290 .id = -1,
291 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
292 .resource = net2272_bfin_resources,
293};
294#endif
295
296#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
297/* all SPI peripherals info goes here */
298
299#if defined(CONFIG_MTD_M25P80) \
300 || defined(CONFIG_MTD_M25P80_MODULE)
301static struct mtd_partition bfin_spi_flash_partitions[] = {
302 {
303 .name = "bootloader(spi)",
304 .size = 0x00020000,
305 .offset = 0,
306 .mask_flags = MTD_CAP_ROM
307 }, {
308 .name = "linux kernel(spi)",
309 .size = 0xe0000,
310 .offset = 0x20000
311 }, {
312 .name = "file system(spi)",
313 .size = 0x700000,
314 .offset = 0x00100000,
315 }
316};
317
318static struct flash_platform_data bfin_spi_flash_data = {
319 .name = "m25p80",
320 .parts = bfin_spi_flash_partitions,
321 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
322 .type = "m25p64",
323};
324
325/* SPI flash chip (m25p64) */
326static struct bfin5xx_spi_chip spi_flash_chip_info = {
327 .enable_dma = 0, /* use dma transfer with this chip*/
328 .bits_per_word = 8,
329};
330#endif
331
332#if defined(CONFIG_SPI_ADC_BF533) \
333 || defined(CONFIG_SPI_ADC_BF533_MODULE)
334/* SPI ADC chip */
335static struct bfin5xx_spi_chip spi_adc_chip_info = {
336 .enable_dma = 1, /* use dma transfer with this chip*/
337 .bits_per_word = 16,
338};
339#endif
340
341#if defined(CONFIG_SND_BLACKFIN_AD1836) \
342 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
343static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
344 .enable_dma = 0,
345 .bits_per_word = 16,
346};
347#endif
348
349#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
350static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
351 .enable_dma = 0,
352 .bits_per_word = 16,
353};
354#endif
355
356#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
357static struct bfin5xx_spi_chip spi_mmc_chip_info = {
358 .enable_dma = 1,
359 .bits_per_word = 8,
360};
361#endif
362
363#if defined(CONFIG_PBX)
364static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
365 .ctl_reg = 0x4, /* send zero */
366 .enable_dma = 0,
367 .bits_per_word = 8,
368 .cs_change_per_word = 1,
369};
370#endif
371
372#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
373static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
374 .enable_dma = 0,
375 .bits_per_word = 16,
376};
377
378static const struct ad7877_platform_data bfin_ad7877_ts_info = {
379 .model = 7877,
380 .vref_delay_usecs = 50, /* internal, no capacitor */
381 .x_plate_ohms = 419,
382 .y_plate_ohms = 486,
383 .pressure_max = 1000,
384 .pressure_min = 0,
385 .stopacq_polarity = 1,
386 .first_conversion_delay = 3,
387 .acquisition_time = 1,
388 .averaging = 1,
389 .pen_down_acc_interval = 1,
390};
391#endif
392
393static struct spi_board_info bfin_spi_board_info[] __initdata = {
394#if defined(CONFIG_MTD_M25P80) \
395 || defined(CONFIG_MTD_M25P80_MODULE)
396 {
397 /* the modalias must be the same as spi device driver name */
398 .modalias = "m25p80", /* Name of spi_driver for this device */
399 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
400 .bus_num = 0, /* Framework bus number */
401 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
402 .platform_data = &bfin_spi_flash_data,
403 .controller_data = &spi_flash_chip_info,
404 .mode = SPI_MODE_3,
405 },
406#endif
407
408#if defined(CONFIG_SPI_ADC_BF533) \
409 || defined(CONFIG_SPI_ADC_BF533_MODULE)
410 {
411 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
412 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
413 .bus_num = 0, /* Framework bus number */
414 .chip_select = 1, /* Framework chip select. */
415 .platform_data = NULL, /* No spi_driver specific config */
416 .controller_data = &spi_adc_chip_info,
417 },
418#endif
419
420#if defined(CONFIG_SND_BLACKFIN_AD1836) \
421 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
422 {
423 .modalias = "ad1836-spi",
424 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
425 .bus_num = 0,
426 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
427 .controller_data = &ad1836_spi_chip_info,
428 },
429#endif
430#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
431 {
432 .modalias = "ad9960-spi",
433 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
434 .bus_num = 0,
435 .chip_select = 1,
436 .controller_data = &ad9960_spi_chip_info,
437 },
438#endif
439#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
440 {
441 .modalias = "spi_mmc_dummy",
442 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
443 .bus_num = 0,
444 .chip_select = 0,
445 .platform_data = NULL,
446 .controller_data = &spi_mmc_chip_info,
447 .mode = SPI_MODE_3,
448 },
449 {
450 .modalias = "spi_mmc",
451 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
452 .bus_num = 0,
453 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
454 .platform_data = NULL,
455 .controller_data = &spi_mmc_chip_info,
456 .mode = SPI_MODE_3,
457 },
458#endif
459#if defined(CONFIG_PBX)
460 {
461 .modalias = "fxs-spi",
462 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
463 .bus_num = 0,
464 .chip_select = 8 - CONFIG_J11_JUMPER,
465 .controller_data = &spi_si3xxx_chip_info,
466 .mode = SPI_MODE_3,
467 },
468 {
469 .modalias = "fxo-spi",
470 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0,
472 .chip_select = 8 - CONFIG_J19_JUMPER,
473 .controller_data = &spi_si3xxx_chip_info,
474 .mode = SPI_MODE_3,
475 },
476#endif
477#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
478 {
479 .modalias = "ad7877",
480 .platform_data = &bfin_ad7877_ts_info,
481 .irq = IRQ_PF6,
482 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
483 .bus_num = 0,
484 .chip_select = 1,
485 .controller_data = &spi_ad7877_chip_info,
486 },
487#endif
488};
489
490/* SPI controller data */
491static struct bfin5xx_spi_master bfin_spi0_info = {
492 .num_chipselect = 8,
493 .enable_dma = 1, /* master has the ability to do dma transfer */
494 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
495};
496
497/* SPI (0) */
498static struct resource bfin_spi0_resource[] = {
499 [0] = {
500 .start = SPI0_REGBASE,
501 .end = SPI0_REGBASE + 0xFF,
502 .flags = IORESOURCE_MEM,
503 },
504 [1] = {
505 .start = CH_SPI,
506 .end = CH_SPI,
507 .flags = IORESOURCE_IRQ,
508 },
509};
510
511static struct platform_device bfin_spi0_device = {
512 .name = "bfin-spi",
513 .id = 0, /* Bus number */
514 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
515 .resource = bfin_spi0_resource,
516 .dev = {
517 .platform_data = &bfin_spi0_info, /* Passed to driver */
518 },
519};
520#endif /* spi master and devices */
521
522#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
523static struct platform_device bfin_fb_device = {
524 .name = "bf537-lq035",
525};
526#endif
527
528#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
529static struct platform_device bfin_fb_adv7393_device = {
530 .name = "bfin-adv7393",
531};
532#endif
533
534#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
535static struct resource bfin_uart_resources[] = {
536 {
537 .start = 0xFFC00400,
538 .end = 0xFFC004FF,
539 .flags = IORESOURCE_MEM,
540 }, {
541 .start = 0xFFC02000,
542 .end = 0xFFC020FF,
543 .flags = IORESOURCE_MEM,
544 },
545};
546
547static struct platform_device bfin_uart_device = {
548 .name = "bfin-uart",
549 .id = 1,
550 .num_resources = ARRAY_SIZE(bfin_uart_resources),
551 .resource = bfin_uart_resources,
552};
553#endif
554
555#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
556#ifdef CONFIG_BFIN_SIR0
557static struct resource bfin_sir0_resources[] = {
558 {
559 .start = 0xFFC00400,
560 .end = 0xFFC004FF,
561 .flags = IORESOURCE_MEM,
562 },
563 {
564 .start = IRQ_UART0_RX,
565 .end = IRQ_UART0_RX+1,
566 .flags = IORESOURCE_IRQ,
567 },
568 {
569 .start = CH_UART0_RX,
570 .end = CH_UART0_RX+1,
571 .flags = IORESOURCE_DMA,
572 },
573};
574
575static struct platform_device bfin_sir0_device = {
576 .name = "bfin_sir",
577 .id = 0,
578 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
579 .resource = bfin_sir0_resources,
580};
581#endif
582#ifdef CONFIG_BFIN_SIR1
583static struct resource bfin_sir1_resources[] = {
584 {
585 .start = 0xFFC02000,
586 .end = 0xFFC020FF,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .start = IRQ_UART1_RX,
591 .end = IRQ_UART1_RX+1,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = CH_UART1_RX,
596 .end = CH_UART1_RX+1,
597 .flags = IORESOURCE_DMA,
598 },
599};
600
601static struct platform_device bfin_sir1_device = {
602 .name = "bfin_sir",
603 .id = 1,
604 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
605 .resource = bfin_sir1_resources,
606};
607#endif
608#endif
609
610#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
611static struct resource bfin_twi0_resource[] = {
612 [0] = {
613 .start = TWI0_REGBASE,
614 .end = TWI0_REGBASE + 0xFF,
615 .flags = IORESOURCE_MEM,
616 },
617 [1] = {
618 .start = IRQ_TWI,
619 .end = IRQ_TWI,
620 .flags = IORESOURCE_IRQ,
621 },
622};
623
624static struct platform_device i2c_bfin_twi_device = {
625 .name = "i2c-bfin-twi",
626 .id = 0,
627 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
628 .resource = bfin_twi0_resource,
629};
630#endif
631
632#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
633static struct platform_device bfin_sport0_uart_device = {
634 .name = "bfin-sport-uart",
635 .id = 0,
636};
637
638static struct platform_device bfin_sport1_uart_device = {
639 .name = "bfin-sport-uart",
640 .id = 1,
641};
642#endif
643
644static struct platform_device *stamp_devices[] __initdata = {
645#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
646 &bfin_pcmcia_cf_device,
647#endif
648
649#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
650 &rtc_device,
651#endif
652
653#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
654 &sl811_hcd_device,
655#endif
656
657#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
658 &isp1362_hcd_device,
659#endif
660
661#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
662 &smc91x_device,
663#endif
664
665#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
666 &dm9000_device,
667#endif
668
669#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
670 &bfin_mii_bus,
671 &bfin_mac_device,
672#endif
673
674#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
675 &net2272_bfin_device,
676#endif
677
678#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
679 &bfin_isp1760_device,
680#endif
681
682#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
683 &bfin_spi0_device,
684#endif
685
686#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
687 &bfin_fb_device,
688#endif
689
690#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
691 &bfin_fb_adv7393_device,
692#endif
693
694#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
695 &bfin_uart_device,
696#endif
697
698#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
699#ifdef CONFIG_BFIN_SIR0
700 &bfin_sir0_device,
701#endif
702#ifdef CONFIG_BFIN_SIR1
703 &bfin_sir1_device,
704#endif
705#endif
706
707#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
708 &i2c_bfin_twi_device,
709#endif
710
711#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
712 &bfin_sport0_uart_device,
713 &bfin_sport1_uart_device,
714#endif
715};
716
717static int __init generic_init(void)
718{
719 printk(KERN_INFO "%s(): registering device resources\n", __func__);
720 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
721#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
722 spi_register_board_info(bfin_spi_board_info,
723 ARRAY_SIZE(bfin_spi_board_info));
724#endif
725
726 return 0;
727}
728
729arch_initcall(generic_init);
730
731void native_machine_restart(char *cmd)
732{
733 /* workaround reboot hang when booting from SPI */
734 if ((bfin_read_SYSCR() & 0x7) == 0x3)
735 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
736}
737
738#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
739void bfin_get_ether_addr(char *addr)
740{
741 random_ether_addr(addr);
742 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
743}
744EXPORT_SYMBOL(bfin_get_ether_addr);
745#endif
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index db7d3a385e4b..3c159819e555 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -134,9 +134,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
134}; 134};
135#endif 135#endif
136 136
137#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 137#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
138static struct bfin5xx_spi_chip spi_mmc_chip_info = { 138static struct bfin5xx_spi_chip mmc_spi_chip_info = {
139 .enable_dma = 1, 139 .enable_dma = 0,
140 .bits_per_word = 8, 140 .bits_per_word = 8,
141}; 141};
142#endif 142#endif
@@ -156,23 +156,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
156 }, 156 },
157#endif 157#endif
158 158
159#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 159#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
160 { 160 {
161 .modalias = "spi_mmc_dummy", 161 .modalias = "mmc_spi",
162 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 162 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
163 .bus_num = 0, 163 .bus_num = 0,
164 .chip_select = 0, 164 .chip_select = 5,
165 .platform_data = NULL, 165 .controller_data = &mmc_spi_chip_info,
166 .controller_data = &spi_mmc_chip_info,
167 .mode = SPI_MODE_3,
168 },
169 {
170 .modalias = "spi_mmc",
171 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
172 .bus_num = 0,
173 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
174 .platform_data = NULL,
175 .controller_data = &spi_mmc_chip_info,
176 .mode = SPI_MODE_3, 166 .mode = SPI_MODE_3,
177 }, 167 },
178#endif 168#endif
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 590eb3a139b7..4e1de1e53f89 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -289,9 +289,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
289}; 289};
290#endif 290#endif
291 291
292#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 292#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
293static struct bfin5xx_spi_chip spi_mmc_chip_info = { 293static struct bfin5xx_spi_chip mmc_spi_chip_info = {
294 .enable_dma = 1, 294 .enable_dma = 0,
295 .bits_per_word = 8, 295 .bits_per_word = 8,
296}; 296};
297#endif 297#endif
@@ -364,23 +364,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
364 .controller_data = &ad9960_spi_chip_info, 364 .controller_data = &ad9960_spi_chip_info,
365 }, 365 },
366#endif 366#endif
367#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 367#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
368 {
369 .modalias = "spi_mmc_dummy",
370 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
371 .bus_num = 0,
372 .chip_select = 7,
373 .platform_data = NULL,
374 .controller_data = &spi_mmc_chip_info,
375 .mode = SPI_MODE_3,
376 },
377 { 368 {
378 .modalias = "spi_mmc", 369 .modalias = "mmc_spi",
379 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 370 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
380 .bus_num = 0, 371 .bus_num = 0,
381 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 372 .chip_select = 5,
382 .platform_data = NULL, 373 .controller_data = &mmc_spi_chip_info,
383 .controller_data = &spi_mmc_chip_info,
384 .mode = SPI_MODE_3, 374 .mode = SPI_MODE_3,
385 }, 375 },
386#endif 376#endif
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 3f4f203a06ec..53ad10f3cd76 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
108}; 108};
109#endif 109#endif
110 110
111#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 111#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
112static struct bfin5xx_spi_chip spi_mmc_chip_info = { 112static struct bfin5xx_spi_chip mmc_spi_chip_info = {
113 .enable_dma = 1, 113 .enable_dma = 0,
114 .bits_per_word = 8, 114 .bits_per_word = 8,
115}; 115};
116#endif 116#endif
@@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
160 }, 160 },
161#endif 161#endif
162 162
163#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 163#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
164 {
165 .modalias = "spi_mmc_dummy",
166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
167 .bus_num = 0,
168 .chip_select = 7,
169 .platform_data = NULL,
170 .controller_data = &spi_mmc_chip_info,
171 .mode = SPI_MODE_3,
172 },
173 { 164 {
174 .modalias = "spi_mmc", 165 .modalias = "mmc_spi",
175 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
176 .bus_num = 0, 167 .bus_num = 0,
177 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 168 .chip_select = 5,
178 .platform_data = NULL, 169 .controller_data = &mmc_spi_chip_info,
179 .controller_data = &spi_mmc_chip_info,
180 .mode = SPI_MODE_3, 170 .mode = SPI_MODE_3,
181 }, 171 },
182#endif 172#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 9cb39121d1cb..1bfd80c26c90 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf537/anomaly.h 2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -110,7 +110,7 @@
110#define ANOMALY_05000301 (1) 110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) 112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 113/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) 114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) 116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
@@ -168,9 +168,12 @@
168#define ANOMALY_05000323 (0) 168#define ANOMALY_05000323 (0)
169#define ANOMALY_05000353 (1) 169#define ANOMALY_05000353 (1)
170#define ANOMALY_05000363 (0) 170#define ANOMALY_05000363 (0)
171#define ANOMALY_05000380 (0)
171#define ANOMALY_05000386 (1) 172#define ANOMALY_05000386 (1)
172#define ANOMALY_05000412 (0) 173#define ANOMALY_05000412 (0)
173#define ANOMALY_05000432 (0) 174#define ANOMALY_05000432 (0)
174#define ANOMALY_05000435 (0) 175#define ANOMALY_05000435 (0)
176#define ANOMALY_05000447 (0)
177#define ANOMALY_05000448 (0)
175 178
176#endif 179#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index b3f87e1d16a2..9e34700844a2 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index e130b4f8a05d..3a5699827363 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf538/anomaly.h 2 * File: include/asm-blackfin/mach-bf538/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -120,13 +120,17 @@
120#define ANOMALY_05000198 (0) 120#define ANOMALY_05000198 (0)
121#define ANOMALY_05000230 (0) 121#define ANOMALY_05000230 (0)
122#define ANOMALY_05000263 (0) 122#define ANOMALY_05000263 (0)
123#define ANOMALY_05000305 (0)
123#define ANOMALY_05000311 (0) 124#define ANOMALY_05000311 (0)
124#define ANOMALY_05000323 (0) 125#define ANOMALY_05000323 (0)
125#define ANOMALY_05000353 (1) 126#define ANOMALY_05000353 (1)
126#define ANOMALY_05000363 (0) 127#define ANOMALY_05000363 (0)
128#define ANOMALY_05000380 (0)
127#define ANOMALY_05000386 (1) 129#define ANOMALY_05000386 (1)
128#define ANOMALY_05000412 (0) 130#define ANOMALY_05000412 (0)
129#define ANOMALY_05000432 (0) 131#define ANOMALY_05000432 (0)
130#define ANOMALY_05000435 (0) 132#define ANOMALY_05000435 (0)
133#define ANOMALY_05000447 (0)
134#define ANOMALY_05000448 (0)
131 135
132#endif 136#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 40503b6b89a3..3c2811ebecdd 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 23d03c52f4b4..882e40ccf0d1 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf548/anomaly.h 2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 10 * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -91,8 +91,6 @@
91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) 91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ 92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) 93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
94/* Mobile DDR Operation Not Functional */
95#define ANOMALY_05000377 (1)
96/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ 94/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
97#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) 95#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
98/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ 96/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
@@ -157,8 +155,22 @@
157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) 155#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
158/* Software System Reset Corrupts PLL_LOCKCNT Register */ 156/* Software System Reset Corrupts PLL_LOCKCNT Register */
159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) 157#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
158/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
159#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
160/* OTP Write Accesses Not Supported */
161#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
160/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 162/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
161#define ANOMALY_05000443 (1) 163#define ANOMALY_05000443 (1)
164/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
165#define ANOMALY_05000446 (1)
166/* UART IrDA Receiver Fails on Extended Bit Pulses */
167#define ANOMALY_05000447 (1)
168/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
169#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
170/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
171#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
172/* USB DMA Mode 1 Short Packet Data Corruption */
173#define ANOMALY_05000450 (1
162 174
163/* Anomalies that don't exist on this proc */ 175/* Anomalies that don't exist on this proc */
164#define ANOMALY_05000125 (0) 176#define ANOMALY_05000125 (0)
@@ -171,6 +183,8 @@
171#define ANOMALY_05000263 (0) 183#define ANOMALY_05000263 (0)
172#define ANOMALY_05000266 (0) 184#define ANOMALY_05000266 (0)
173#define ANOMALY_05000273 (0) 185#define ANOMALY_05000273 (0)
186#define ANOMALY_05000278 (0)
187#define ANOMALY_05000305 (0)
174#define ANOMALY_05000307 (0) 188#define ANOMALY_05000307 (0)
175#define ANOMALY_05000311 (0) 189#define ANOMALY_05000311 (0)
176#define ANOMALY_05000323 (0) 190#define ANOMALY_05000323 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index e4cf35e7ab9f..c05e79cba257 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -63,7 +63,7 @@
63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) 63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) 64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
65 65
66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART2_CTSRTS)
67# define CONFIG_SERIAL_BFIN_CTSRTS 67# define CONFIG_SERIAL_BFIN_CTSRTS
68 68
69# ifndef CONFIG_UART0_CTS_PIN 69# ifndef CONFIG_UART0_CTS_PIN
@@ -74,12 +74,12 @@
74# define CONFIG_UART0_RTS_PIN -1 74# define CONFIG_UART0_RTS_PIN -1
75# endif 75# endif
76 76
77# ifndef CONFIG_UART1_CTS_PIN 77# ifndef CONFIG_UART2_CTS_PIN
78# define CONFIG_UART1_CTS_PIN -1 78# define CONFIG_UART2_CTS_PIN -1
79# endif 79# endif
80 80
81# ifndef CONFIG_UART1_RTS_PIN 81# ifndef CONFIG_UART2_RTS_PIN
82# define CONFIG_UART1_RTS_PIN -1 82# define CONFIG_UART2_RTS_PIN -1
83# endif 83# endif
84#endif 84#endif
85 85
@@ -130,7 +130,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
130 CH_UART0_TX, 130 CH_UART0_TX,
131 CH_UART0_RX, 131 CH_UART0_RX,
132#endif 132#endif
133#ifdef CONFIG_BFIN_UART0_CTSRTS 133#ifdef CONFIG_SERIAL_BFIN_CTSRTS
134 CONFIG_UART0_CTS_PIN, 134 CONFIG_UART0_CTS_PIN,
135 CONFIG_UART0_RTS_PIN, 135 CONFIG_UART0_RTS_PIN,
136#endif 136#endif
@@ -144,6 +144,10 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART1_TX, 144 CH_UART1_TX,
145 CH_UART1_RX, 145 CH_UART1_RX,
146#endif 146#endif
147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 0,
149 0,
150#endif
147 }, 151 },
148#endif 152#endif
149#ifdef CONFIG_SERIAL_BFIN_UART2 153#ifdef CONFIG_SERIAL_BFIN_UART2
@@ -154,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 CH_UART2_TX, 158 CH_UART2_TX,
155 CH_UART2_RX, 159 CH_UART2_RX,
156#endif 160#endif
157#ifdef CONFIG_BFIN_UART2_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
158 CONFIG_UART2_CTS_PIN, 162 CONFIG_UART2_CTS_PIN,
159 CONFIG_UART2_RTS_PIN, 163 CONFIG_UART2_RTS_PIN,
160#endif 164#endif
@@ -168,6 +172,10 @@ struct bfin_serial_res bfin_serial_resource[] = {
168 CH_UART3_TX, 172 CH_UART3_TX,
169 CH_UART3_RX, 173 CH_UART3_RX,
170#endif 174#endif
175#ifdef CONFIG_SERIAL_BFIN_CTSRTS
176 0,
177 0,
178#endif
171 }, 179 },
172#endif 180#endif
173}; 181};
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 60299a71e090..f194625f6821 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -123,8 +123,8 @@ Events (highest priority) EMU 0
123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ 123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ 124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ 125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
126#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ 126#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
127#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ 127#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ 128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ 129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ 130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
@@ -361,8 +361,8 @@ Events (highest priority) EMU 0
361#define IRQ_UART2_ERR IRQ_UART2_ERROR 361#define IRQ_UART2_ERR IRQ_UART2_ERROR
362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR 362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR 363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
364#define IRQ_EPP1_ERR IRQ_EPP1_ERROR 364#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
365#define IRQ_EPP2_ERR IRQ_EPP2_ERROR 365#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
366#define IRQ_UART3_ERR IRQ_UART3_ERROR 366#define IRQ_UART3_ERR IRQ_UART3_ERROR
367#define IRQ_HOST_ERR IRQ_HOST_ERROR 367#define IRQ_HOST_ERR IRQ_HOST_ERROR
368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR 368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
index e41a67b1fb53..e4bc6d7c5a6a 100644
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ b/arch/blackfin/mach-bf561/boards/Kconfig
@@ -19,9 +19,4 @@ config BFIN561_BLUETECHNIX_CM
19 help 19 help
20 CM-BF561 support for EVAL- and DEV-Board. 20 CM-BF561 support for EVAL- and DEV-Board.
21 21
22config GENERIC_BF561_BOARD
23 bool "Generic"
24 help
25 Generic or Custom board support.
26
27endchoice 22endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
index 04add010b568..3a152559e957 100644
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ b/arch/blackfin/mach-bf561/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf561/boards/Makefile 2# arch/blackfin/mach-bf561/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF561_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o 5obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
7obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o 6obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
8obj-$(CONFIG_BFIN561_TEPLA) += tepla.o 7obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 6880d1ebfe60..f623c6b0719f 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -105,9 +105,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
105}; 105};
106#endif 106#endif
107 107
108#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
109static struct bfin5xx_spi_chip spi_mmc_chip_info = { 109static struct bfin5xx_spi_chip mmc_spi_chip_info = {
110 .enable_dma = 1, 110 .enable_dma = 0,
111 .bits_per_word = 8, 111 .bits_per_word = 8,
112}; 112};
113#endif 113#endif
@@ -155,14 +155,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
155 .controller_data = &ad9960_spi_chip_info, 155 .controller_data = &ad9960_spi_chip_info,
156 }, 156 },
157#endif 157#endif
158#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 158#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
159 { 159 {
160 .modalias = "spi_mmc", 160 .modalias = "mmc_spi",
161 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 161 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
162 .bus_num = 0, 162 .bus_num = 0,
163 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 163 .chip_select = 5,
164 .platform_data = NULL, 164 .controller_data = &mmc_spi_chip_info,
165 .controller_data = &spi_mmc_chip_info,
166 .mode = SPI_MODE_3, 165 .mode = SPI_MODE_3,
167 }, 166 },
168#endif 167#endif
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
deleted file mode 100644
index 0ba366a0e696..000000000000
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf561/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/irq.h>
34
35const char bfin_board_name[] = "UNKNOWN BOARD";
36
37/*
38 * Driver needs to know address, irq and flag pin.
39 */
40#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
41static struct resource smc91x_resources[] = {
42 {
43 .start = 0x2C010300,
44 .end = 0x2C010300 + 16,
45 .flags = IORESOURCE_MEM,
46 }, {
47 .start = IRQ_PROG_INTB,
48 .end = IRQ_PROG_INTB,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 }, {
51 .start = IRQ_PF9,
52 .end = IRQ_PF9,
53 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
54 },
55};
56
57static struct platform_device smc91x_device = {
58 .name = "smc91x",
59 .id = 0,
60 .num_resources = ARRAY_SIZE(smc91x_resources),
61 .resource = smc91x_resources,
62};
63#endif
64
65#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
66#ifdef CONFIG_BFIN_SIR0
67static struct resource bfin_sir0_resources[] = {
68 {
69 .start = 0xFFC00400,
70 .end = 0xFFC004FF,
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .start = IRQ_UART0_RX,
75 .end = IRQ_UART0_RX+1,
76 .flags = IORESOURCE_IRQ,
77 },
78 {
79 .start = CH_UART0_RX,
80 .end = CH_UART0_RX+1,
81 .flags = IORESOURCE_DMA,
82 },
83};
84
85static struct platform_device bfin_sir0_device = {
86 .name = "bfin_sir",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
89 .resource = bfin_sir0_resources,
90};
91#endif
92#endif
93
94static struct platform_device *generic_board_devices[] __initdata = {
95#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
96 &smc91x_device,
97#endif
98
99#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
100#ifdef CONFIG_BFIN_SIR0
101 &bfin_sir0_device,
102#endif
103#endif
104};
105
106static int __init generic_board_init(void)
107{
108 printk(KERN_INFO "%s(): registering device resources\n", __func__);
109 return platform_add_devices(generic_board_devices,
110 ARRAY_SIZE(generic_board_devices));
111}
112
113arch_initcall(generic_board_init);
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 1a9e17562821..d0b0b3506440 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf561/anomaly.h 2 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -224,7 +224,7 @@
224#define ANOMALY_05000301 (1) 224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1) 226#define ANOMALY_05000302 (1)
227/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 229/* SCKELOW Bit Does Not Maintain State Through Hibernate */
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) 230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
@@ -283,8 +283,11 @@
283#define ANOMALY_05000273 (0) 283#define ANOMALY_05000273 (0)
284#define ANOMALY_05000311 (0) 284#define ANOMALY_05000311 (0)
285#define ANOMALY_05000353 (1) 285#define ANOMALY_05000353 (1)
286#define ANOMALY_05000380 (0)
286#define ANOMALY_05000386 (1) 287#define ANOMALY_05000386 (1)
287#define ANOMALY_05000432 (0) 288#define ANOMALY_05000432 (0)
288#define ANOMALY_05000435 (0) 289#define ANOMALY_05000435 (0)
290#define ANOMALY_05000447 (0)
291#define ANOMALY_05000448 (0)
289 292
290#endif 293#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index 043bfcf26c52..ca8c5f645209 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
134 CH_UART_TX, 134 CH_UART_TX,
135 CH_UART_RX, 135 CH_UART_RX,
136#endif 136#endif
137#ifdef CONFIG_BFIN_UART0_CTSRTS 137#ifdef CONFIG_SERIAL_BFIN_CTSRTS
138 CONFIG_UART0_CTS_PIN, 138 CONFIG_UART0_CTS_PIN,
139 CONFIG_UART0_RTS_PIN, 139 CONFIG_UART0_RTS_PIN,
140#endif 140#endif
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index 98133b968f7b..80d39b2f9db2 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -62,3 +62,12 @@
62#if (CONFIG_BOOT_LOAD & 0x3) 62#if (CONFIG_BOOT_LOAD & 0x3)
63# error "The kernel load address must be 4 byte aligned" 63# error "The kernel load address must be 4 byte aligned"
64#endif 64#endif
65
66/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
67#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
68# error "The kernel load address is too high; keep it below 10meg for safety"
69#endif
70
71#if ANOMALY_05000448
72# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
73#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 3c98dacbf289..aa0648c6a9fe 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -66,11 +66,33 @@
66 66
67/* Invalidate all instruction cache lines assocoiated with this memory area */ 67/* Invalidate all instruction cache lines assocoiated with this memory area */
68ENTRY(_blackfin_icache_flush_range) 68ENTRY(_blackfin_icache_flush_range)
69/*
70 * Walkaround to avoid loading wrong instruction after invalidating icache
71 * and following sequence is met.
72 *
73 * 1) One instruction address is cached in the instruction cache.
74 * 2) This instruction in SDRAM is changed.
75 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
76 * 4) This instruction is executed again, but the old one is loaded.
77 */
78 P0 = R0;
79 IFLUSH[P0];
69 do_flush IFLUSH, , nop 80 do_flush IFLUSH, , nop
70ENDPROC(_blackfin_icache_flush_range) 81ENDPROC(_blackfin_icache_flush_range)
71 82
72/* Flush all cache lines assocoiated with this area of memory. */ 83/* Flush all cache lines assocoiated with this area of memory. */
73ENTRY(_blackfin_icache_dcache_flush_range) 84ENTRY(_blackfin_icache_dcache_flush_range)
85/*
86 * Walkaround to avoid loading wrong instruction after invalidating icache
87 * and following sequence is met.
88 *
89 * 1) One instruction address is cached in the instruction cache.
90 * 2) This instruction in SDRAM is changed.
91 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
92 * 4) This instruction is executed again, but the old one is loaded.
93 */
94 P0 = R0;
95 IFLUSH[P0];
74 do_flush FLUSH, IFLUSH 96 do_flush FLUSH, IFLUSH
75ENDPROC(_blackfin_icache_dcache_flush_range) 97ENDPROC(_blackfin_icache_dcache_flush_range)
76 98
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 9dddb6f8cc85..35393651359b 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -17,7 +17,7 @@
17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
18#define PLL_CTL_VAL \ 18#define PLL_CTL_VAL \
19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ 19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
20 (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) 20 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
21 21
22__attribute__((l1_text)) 22__attribute__((l1_text))
23static void do_sync(void) 23static void do_sync(void)
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 4da50bcd9300..8009a512fb11 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -376,10 +376,22 @@ ENTRY(_do_hibernate)
376#endif 376#endif
377 377
378#ifdef PINT0_ASSIGN 378#ifdef PINT0_ASSIGN
379 PM_SYS_PUSH(PINT0_MASK_SET)
380 PM_SYS_PUSH(PINT1_MASK_SET)
381 PM_SYS_PUSH(PINT2_MASK_SET)
382 PM_SYS_PUSH(PINT3_MASK_SET)
379 PM_SYS_PUSH(PINT0_ASSIGN) 383 PM_SYS_PUSH(PINT0_ASSIGN)
380 PM_SYS_PUSH(PINT1_ASSIGN) 384 PM_SYS_PUSH(PINT1_ASSIGN)
381 PM_SYS_PUSH(PINT2_ASSIGN) 385 PM_SYS_PUSH(PINT2_ASSIGN)
382 PM_SYS_PUSH(PINT3_ASSIGN) 386 PM_SYS_PUSH(PINT3_ASSIGN)
387 PM_SYS_PUSH(PINT0_INVERT_SET)
388 PM_SYS_PUSH(PINT1_INVERT_SET)
389 PM_SYS_PUSH(PINT2_INVERT_SET)
390 PM_SYS_PUSH(PINT3_INVERT_SET)
391 PM_SYS_PUSH(PINT0_EDGE_SET)
392 PM_SYS_PUSH(PINT1_EDGE_SET)
393 PM_SYS_PUSH(PINT2_EDGE_SET)
394 PM_SYS_PUSH(PINT3_EDGE_SET)
383#endif 395#endif
384 396
385 PM_SYS_PUSH(EBIU_AMBCTL0) 397 PM_SYS_PUSH(EBIU_AMBCTL0)
@@ -714,10 +726,22 @@ ENTRY(_do_hibernate)
714 PM_SYS_POP(EBIU_AMBCTL0) 726 PM_SYS_POP(EBIU_AMBCTL0)
715 727
716#ifdef PINT0_ASSIGN 728#ifdef PINT0_ASSIGN
729 PM_SYS_POP(PINT3_EDGE_SET)
730 PM_SYS_POP(PINT2_EDGE_SET)
731 PM_SYS_POP(PINT1_EDGE_SET)
732 PM_SYS_POP(PINT0_EDGE_SET)
733 PM_SYS_POP(PINT3_INVERT_SET)
734 PM_SYS_POP(PINT2_INVERT_SET)
735 PM_SYS_POP(PINT1_INVERT_SET)
736 PM_SYS_POP(PINT0_INVERT_SET)
717 PM_SYS_POP(PINT3_ASSIGN) 737 PM_SYS_POP(PINT3_ASSIGN)
718 PM_SYS_POP(PINT2_ASSIGN) 738 PM_SYS_POP(PINT2_ASSIGN)
719 PM_SYS_POP(PINT1_ASSIGN) 739 PM_SYS_POP(PINT1_ASSIGN)
720 PM_SYS_POP(PINT0_ASSIGN) 740 PM_SYS_POP(PINT0_ASSIGN)
741 PM_SYS_POP(PINT3_MASK_SET)
742 PM_SYS_POP(PINT2_MASK_SET)
743 PM_SYS_POP(PINT1_MASK_SET)
744 PM_SYS_POP(PINT0_MASK_SET)
721#endif 745#endif
722 746
723#ifdef SICA_IWR1 747#ifdef SICA_IWR1
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 88de053bbe8e..21e65a339a22 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -600,6 +600,19 @@ ENTRY(_system_call)
600 p2 = [p2]; 600 p2 = [p2];
601 601
602 [p2+(TASK_THREAD+THREAD_KSP)] = sp; 602 [p2+(TASK_THREAD+THREAD_KSP)] = sp;
603#ifdef CONFIG_IPIPE
604 r0 = sp;
605 SP += -12;
606 call ___ipipe_syscall_root;
607 SP += 12;
608 cc = r0 == 1;
609 if cc jump .Lsyscall_really_exit;
610 cc = r0 == -1;
611 if cc jump .Lresume_userspace;
612 r3 = [sp + PT_R3];
613 r4 = [sp + PT_R4];
614 p0 = [sp + PT_ORIG_P0];
615#endif /* CONFIG_IPIPE */
603 616
604 /* Check the System Call */ 617 /* Check the System Call */
605 r7 = __NR_syscall; 618 r7 = __NR_syscall;
@@ -654,6 +667,17 @@ ENTRY(_system_call)
654 r7 = r7 & r4; 667 r7 = r7 & r4;
655 668
656.Lsyscall_resched: 669.Lsyscall_resched:
670#ifdef CONFIG_IPIPE
671 cc = BITTST(r7, TIF_IRQ_SYNC);
672 if !cc jump .Lsyscall_no_irqsync;
673 [--sp] = reti;
674 r0 = [sp++];
675 SP += -12;
676 call ___ipipe_sync_root;
677 SP += 12;
678 jump .Lresume_userspace_1;
679.Lsyscall_no_irqsync:
680#endif
657 cc = BITTST(r7, TIF_NEED_RESCHED); 681 cc = BITTST(r7, TIF_NEED_RESCHED);
658 if !cc jump .Lsyscall_sigpending; 682 if !cc jump .Lsyscall_sigpending;
659 683
@@ -685,6 +709,10 @@ ENTRY(_system_call)
685.Lsyscall_really_exit: 709.Lsyscall_really_exit:
686 r5 = [sp + PT_RESERVED]; 710 r5 = [sp + PT_RESERVED];
687 rets = r5; 711 rets = r5;
712#ifdef CONFIG_IPIPE
713 [--sp] = reti;
714 r5 = [sp++];
715#endif /* CONFIG_IPIPE */
688 rts; 716 rts;
689ENDPROC(_system_call) 717ENDPROC(_system_call)
690 718
@@ -771,6 +799,15 @@ _new_old_task:
771ENDPROC(_resume) 799ENDPROC(_resume)
772 800
773ENTRY(_ret_from_exception) 801ENTRY(_ret_from_exception)
802#ifdef CONFIG_IPIPE
803 [--sp] = rets;
804 SP += -12;
805 call ___ipipe_check_root
806 SP += 12
807 rets = [sp++];
808 cc = r0 == 0;
809 if cc jump 4f; /* not on behalf of Linux, get out */
810#endif /* CONFIG_IPIPE */
774 p2.l = lo(IPEND); 811 p2.l = lo(IPEND);
775 p2.h = hi(IPEND); 812 p2.h = hi(IPEND);
776 813
@@ -827,6 +864,28 @@ ENTRY(_ret_from_exception)
827 rts; 864 rts;
828ENDPROC(_ret_from_exception) 865ENDPROC(_ret_from_exception)
829 866
867#ifdef CONFIG_IPIPE
868
869_sync_root_irqs:
870 [--sp] = reti; /* Reenable interrupts */
871 r0 = [sp++];
872 jump.l ___ipipe_sync_root
873
874_resume_kernel_from_int:
875 r0.l = _sync_root_irqs
876 r0.h = _sync_root_irqs
877 [--sp] = rets;
878 [--sp] = ( r7:4, p5:3 );
879 SP += -12;
880 call ___ipipe_call_irqtail
881 SP += 12;
882 ( r7:4, p5:3 ) = [sp++];
883 rets = [sp++];
884 rts
885#else
886#define _resume_kernel_from_int 2f
887#endif
888
830ENTRY(_return_from_int) 889ENTRY(_return_from_int)
831 /* If someone else already raised IRQ 15, do nothing. */ 890 /* If someone else already raised IRQ 15, do nothing. */
832 csync; 891 csync;
@@ -848,7 +907,7 @@ ENTRY(_return_from_int)
848 r1 = r0 - r1; 907 r1 = r0 - r1;
849 r2 = r0 & r1; 908 r2 = r0 & r1;
850 cc = r2 == 0; 909 cc = r2 == 0;
851 if !cc jump 2f; 910 if !cc jump _resume_kernel_from_int;
852 911
853 /* Lower the interrupt level to 15. */ 912 /* Lower the interrupt level to 15. */
854 p0.l = lo(EVT15); 913 p0.l = lo(EVT15);
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 43c4eb9acb65..0069c2dd4625 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -235,6 +235,7 @@ ENDPROC(_evt_system_call)
235 235
236#ifdef CONFIG_IPIPE 236#ifdef CONFIG_IPIPE
237ENTRY(___ipipe_call_irqtail) 237ENTRY(___ipipe_call_irqtail)
238 p0 = r0;
238 r0.l = 1f; 239 r0.l = 1f;
239 r0.h = 1f; 240 r0.h = 1f;
240 reti = r0; 241 reti = r0;
@@ -242,9 +243,6 @@ ENTRY(___ipipe_call_irqtail)
2421: 2431:
243 [--sp] = rets; 244 [--sp] = rets;
244 [--sp] = ( r7:4, p5:3 ); 245 [--sp] = ( r7:4, p5:3 );
245 p0.l = ___ipipe_irq_tail_hook;
246 p0.h = ___ipipe_irq_tail_hook;
247 p0 = [p0];
248 sp += -12; 246 sp += -12;
249 call (p0); 247 call (p0);
250 sp += 12; 248 sp += 12;
@@ -259,7 +257,7 @@ ENTRY(___ipipe_call_irqtail)
259 p0.h = hi(EVT14); 257 p0.h = hi(EVT14);
260 [p0] = r0; 258 [p0] = r0;
261 csync; 259 csync;
262 r0 = 0x401f; 260 r0 = 0x401f (z);
263 sti r0; 261 sti r0;
264 raise 14; 262 raise 14;
265 [--sp] = reti; /* IRQs on. */ 263 [--sp] = reti; /* IRQs on. */
@@ -277,11 +275,7 @@ ENTRY(___ipipe_call_irqtail)
277 p0.h = _bfin_irq_flags; 275 p0.h = _bfin_irq_flags;
278 r0 = [p0]; 276 r0 = [p0];
279 sti r0; 277 sti r0;
280#if 0 /* FIXME: this actually raises scheduling latencies */
281 /* Reenable interrupts */
282 [--sp] = reti;
283 r0 = [sp++];
284#endif
285 rts; 278 rts;
286ENDPROC(___ipipe_call_irqtail) 279ENDPROC(___ipipe_call_irqtail)
280
287#endif /* CONFIG_IPIPE */ 281#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 202494568c6c..a7d7b2dd4059 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -161,11 +161,15 @@ static void bfin_core_unmask_irq(unsigned int irq)
161 161
162static void bfin_internal_mask_irq(unsigned int irq) 162static void bfin_internal_mask_irq(unsigned int irq)
163{ 163{
164 unsigned long flags;
165
164#ifdef CONFIG_BF53x 166#ifdef CONFIG_BF53x
167 local_irq_save_hw(flags);
165 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 168 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
166 ~(1 << SIC_SYSIRQ(irq))); 169 ~(1 << SIC_SYSIRQ(irq)));
167#else 170#else
168 unsigned mask_bank, mask_bit; 171 unsigned mask_bank, mask_bit;
172 local_irq_save_hw(flags);
169 mask_bank = SIC_SYSIRQ(irq) / 32; 173 mask_bank = SIC_SYSIRQ(irq) / 32;
170 mask_bit = SIC_SYSIRQ(irq) % 32; 174 mask_bit = SIC_SYSIRQ(irq) % 32;
171 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 175 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
@@ -175,15 +179,20 @@ static void bfin_internal_mask_irq(unsigned int irq)
175 ~(1 << mask_bit)); 179 ~(1 << mask_bit));
176#endif 180#endif
177#endif 181#endif
182 local_irq_restore_hw(flags);
178} 183}
179 184
180static void bfin_internal_unmask_irq(unsigned int irq) 185static void bfin_internal_unmask_irq(unsigned int irq)
181{ 186{
187 unsigned long flags;
188
182#ifdef CONFIG_BF53x 189#ifdef CONFIG_BF53x
190 local_irq_save_hw(flags);
183 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 191 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
184 (1 << SIC_SYSIRQ(irq))); 192 (1 << SIC_SYSIRQ(irq)));
185#else 193#else
186 unsigned mask_bank, mask_bit; 194 unsigned mask_bank, mask_bit;
195 local_irq_save_hw(flags);
187 mask_bank = SIC_SYSIRQ(irq) / 32; 196 mask_bank = SIC_SYSIRQ(irq) / 32;
188 mask_bit = SIC_SYSIRQ(irq) % 32; 197 mask_bit = SIC_SYSIRQ(irq) % 32;
189 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | 198 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
@@ -193,6 +202,7 @@ static void bfin_internal_unmask_irq(unsigned int irq)
193 (1 << mask_bit)); 202 (1 << mask_bit));
194#endif 203#endif
195#endif 204#endif
205 local_irq_restore_hw(flags);
196} 206}
197 207
198#ifdef CONFIG_PM 208#ifdef CONFIG_PM
@@ -390,7 +400,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
390static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) 400static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
391{ 401{
392#ifdef CONFIG_IPIPE 402#ifdef CONFIG_IPIPE
393 _set_irq_handler(irq, handle_edge_irq); 403 _set_irq_handler(irq, handle_level_irq);
394#else 404#else
395 struct irq_desc *desc = irq_desc + irq; 405 struct irq_desc *desc = irq_desc + irq;
396 /* May not call generic set_irq_handler() due to spinlock 406 /* May not call generic set_irq_handler() due to spinlock
@@ -1055,13 +1065,18 @@ int __init init_arch_irq(void)
1055#endif 1065#endif
1056 default: 1066 default:
1057#ifdef CONFIG_IPIPE 1067#ifdef CONFIG_IPIPE
1058 /* 1068 /*
1059 * We want internal interrupt sources to be masked, because 1069 * We want internal interrupt sources to be
1060 * ISRs may trigger interrupts recursively (e.g. DMA), but 1070 * masked, because ISRs may trigger interrupts
1061 * interrupts are _not_ masked at CPU level. So let's handle 1071 * recursively (e.g. DMA), but interrupts are
1062 * them as level interrupts. 1072 * _not_ masked at CPU level. So let's handle
1063 */ 1073 * most of them as level interrupts, except
1064 set_irq_handler(irq, handle_level_irq); 1074 * the timer interrupt which is special.
1075 */
1076 if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR)
1077 set_irq_handler(irq, handle_simple_irq);
1078 else
1079 set_irq_handler(irq, handle_level_irq);
1065#else /* !CONFIG_IPIPE */ 1080#else /* !CONFIG_IPIPE */
1066 set_irq_handler(irq, handle_simple_irq); 1081 set_irq_handler(irq, handle_simple_irq);
1067#endif /* !CONFIG_IPIPE */ 1082#endif /* !CONFIG_IPIPE */
@@ -1123,9 +1138,8 @@ int __init init_arch_irq(void)
1123 1138
1124#ifdef CONFIG_IPIPE 1139#ifdef CONFIG_IPIPE
1125 for (irq = 0; irq < NR_IRQS; irq++) { 1140 for (irq = 0; irq < NR_IRQS; irq++) {
1126 struct irq_desc *desc = irq_desc + irq; 1141 struct irq_desc *desc = irq_to_desc(irq);
1127 desc->ic_prio = __ipipe_get_irq_priority(irq); 1142 desc->ic_prio = __ipipe_get_irq_priority(irq);
1128 desc->thr_prio = __ipipe_get_irqthread_priority(irq);
1129 } 1143 }
1130#endif /* CONFIG_IPIPE */ 1144#endif /* CONFIG_IPIPE */
1131 1145
@@ -1208,76 +1222,21 @@ int __ipipe_get_irq_priority(unsigned irq)
1208 return IVG15; 1222 return IVG15;
1209} 1223}
1210 1224
1211int __ipipe_get_irqthread_priority(unsigned irq)
1212{
1213 int ient, prio;
1214 int demux_irq;
1215
1216 /* The returned priority value is rescaled to [0..IVG13+1]
1217 * with 0 being the lowest effective priority level. */
1218
1219 if (irq <= IRQ_CORETMR)
1220 return IVG13 - irq + 1;
1221
1222 /* GPIO IRQs are given the priority of the demux
1223 * interrupt. */
1224 if (IS_GPIOIRQ(irq)) {
1225#if defined(CONFIG_BF54x)
1226 u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]);
1227 demux_irq = (bank == 0 ? IRQ_PINT0 :
1228 bank == 1 ? IRQ_PINT1 :
1229 bank == 2 ? IRQ_PINT2 :
1230 IRQ_PINT3);
1231#elif defined(CONFIG_BF561)
1232 demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA :
1233 irq >= IRQ_PF16 ? IRQ_PROG1_INTA :
1234 IRQ_PROG0_INTA);
1235#elif defined(CONFIG_BF52x)
1236 demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA :
1237 irq >= IRQ_PG0 ? IRQ_PORTG_INTA :
1238 IRQ_PORTF_INTA);
1239#else
1240 demux_irq = irq;
1241#endif
1242 return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1;
1243 }
1244
1245 /* The GPIO demux interrupt is given a lower priority
1246 * than the GPIO IRQs, so that its threaded handler
1247 * unmasks the interrupt line after the decoded IRQs
1248 * have been processed. */
1249 prio = PRIO_GPIODEMUX(irq);
1250 /* demux irq? */
1251 if (prio != -1)
1252 return IVG13 - prio;
1253
1254 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1255 struct ivgx *ivg = ivg_table + ient;
1256 if (ivg->irqno == irq) {
1257 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1258 if (ivg7_13[prio].ifirst <= ivg &&
1259 ivg7_13[prio].istop > ivg)
1260 return IVG7 - prio;
1261 }
1262 }
1263 }
1264
1265 return 0;
1266}
1267
1268/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ 1225/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1269#ifdef CONFIG_DO_IRQ_L1 1226#ifdef CONFIG_DO_IRQ_L1
1270__attribute__((l1_text)) 1227__attribute__((l1_text))
1271#endif 1228#endif
1272asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) 1229asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1273{ 1230{
1231 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1232 struct ipipe_domain *this_domain = ipipe_current_domain;
1274 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; 1233 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1275 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; 1234 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1276 int irq; 1235 int irq, s;
1277 1236
1278 if (likely(vec == EVT_IVTMR_P)) { 1237 if (likely(vec == EVT_IVTMR_P)) {
1279 irq = IRQ_CORETMR; 1238 irq = IRQ_CORETMR;
1280 goto handle_irq; 1239 goto core_tick;
1281 } 1240 }
1282 1241
1283 SSYNC(); 1242 SSYNC();
@@ -1319,24 +1278,39 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1319 irq = ivg->irqno; 1278 irq = ivg->irqno;
1320 1279
1321 if (irq == IRQ_SYSTMR) { 1280 if (irq == IRQ_SYSTMR) {
1281#ifdef CONFIG_GENERIC_CLOCKEVENTS
1282core_tick:
1283#else
1322 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ 1284 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1285#endif
1323 /* This is basically what we need from the register frame. */ 1286 /* This is basically what we need from the register frame. */
1324 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; 1287 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1325 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; 1288 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1326 if (!ipipe_root_domain_p) 1289 if (this_domain != ipipe_root_domain)
1327 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1328 else
1329 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; 1290 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1291 else
1292 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1330 } 1293 }
1331 1294
1332handle_irq: 1295#ifndef CONFIG_GENERIC_CLOCKEVENTS
1296core_tick:
1297#endif
1298 if (this_domain == ipipe_root_domain) {
1299 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1300 barrier();
1301 }
1333 1302
1334 ipipe_trace_irq_entry(irq); 1303 ipipe_trace_irq_entry(irq);
1335 __ipipe_handle_irq(irq, regs); 1304 __ipipe_handle_irq(irq, regs);
1336 ipipe_trace_irq_exit(irq); 1305 ipipe_trace_irq_exit(irq);
1337 1306
1338 if (ipipe_root_domain_p) 1307 if (this_domain == ipipe_root_domain) {
1339 return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); 1308 set_thread_flag(TIF_IRQ_SYNC);
1309 if (!s) {
1310 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1311 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1312 }
1313 }
1340 1314
1341 return 0; 1315 return 0;
1342} 1316}
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 77c992847094..93eab6146079 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -158,10 +158,14 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance)
158 kfree(msg); 158 kfree(msg);
159 break; 159 break;
160 case BFIN_IPI_CALL_FUNC: 160 case BFIN_IPI_CALL_FUNC:
161 spin_unlock(&msg_queue->lock);
161 ipi_call_function(cpu, msg); 162 ipi_call_function(cpu, msg);
163 spin_lock(&msg_queue->lock);
162 break; 164 break;
163 case BFIN_IPI_CPU_STOP: 165 case BFIN_IPI_CPU_STOP:
166 spin_unlock(&msg_queue->lock);
164 ipi_cpu_stop(cpu); 167 ipi_cpu_stop(cpu);
168 spin_lock(&msg_queue->lock);
165 kfree(msg); 169 kfree(msg);
166 break; 170 break;
167 default: 171 default:
@@ -457,7 +461,7 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end)
457 smp_flush_data.start = start; 461 smp_flush_data.start = start;
458 smp_flush_data.end = end; 462 smp_flush_data.end = end;
459 463
460 if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) 464 if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
461 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); 465 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
462} 466}
463EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); 467EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index d0532b72bba5..9c3629b9a689 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -104,7 +104,7 @@ void __init paging_init(void)
104 } 104 }
105} 105}
106 106
107asmlinkage void init_pda(void) 107asmlinkage void __init init_pda(void)
108{ 108{
109 unsigned int cpu = raw_smp_processor_id(); 109 unsigned int cpu = raw_smp_processor_id();
110 110
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index e626e50a938a..060df4aa9916 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -135,11 +135,10 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
135 if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) 135 if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
136 pci_addr = IS_PIC_SOFT(pcibus_info) ? 136 pci_addr = IS_PIC_SOFT(pcibus_info) ?
137 PHYS_TO_DMA(paddr) : 137 PHYS_TO_DMA(paddr) :
138 PHYS_TO_TIODMA(paddr) | dma_attributes; 138 PHYS_TO_TIODMA(paddr);
139 else 139 else
140 pci_addr = IS_PIC_SOFT(pcibus_info) ? 140 pci_addr = paddr;
141 paddr : 141 pci_addr |= dma_attributes;
142 paddr | dma_attributes;
143 142
144 /* Handle Bus mode */ 143 /* Handle Bus mode */
145 if (IS_PCIX(pcibus_info)) 144 if (IS_PCIX(pcibus_info))
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index d01a5d2b7557..db902540bf2c 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -17,6 +17,7 @@
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfdma.h> 19#include <asm/mcfdma.h>
20#include <asm/mcfuart.h>
20 21
21/***************************************************************************/ 22/***************************************************************************/
22 23
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c
index dfdb5c2ed8e6..44baeb225dc7 100644
--- a/arch/m68knommu/platform/528x/config.c
+++ b/arch/m68knommu/platform/528x/config.c
@@ -24,7 +24,6 @@
24#include <asm/coldfire.h> 24#include <asm/coldfire.h>
25#include <asm/mcfsim.h> 25#include <asm/mcfsim.h>
26#include <asm/mcfuart.h> 26#include <asm/mcfuart.h>
27#include <asm/mcfqspi.h>
28 27
29#ifdef CONFIG_MTD_PARTITIONS 28#ifdef CONFIG_MTD_PARTITIONS
30#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
@@ -33,233 +32,6 @@
33/***************************************************************************/ 32/***************************************************************************/
34 33
35void coldfire_reset(void); 34void coldfire_reset(void);
36static void coldfire_qspi_cs_control(u8 cs, u8 command);
37
38/***************************************************************************/
39
40#if defined(CONFIG_SPI)
41
42#if defined(CONFIG_WILDFIRE)
43#define SPI_NUM_CHIPSELECTS 0x02
44#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
45#define SPI_CS_MASK 0x18
46
47#define FLASH_BLOCKSIZE (1024*64)
48#define FLASH_NUMBLOCKS 16
49#define FLASH_TYPE "m25p80"
50
51#define M25P80_CS 0
52#define MMC_CS 1
53
54#ifdef CONFIG_MTD_PARTITIONS
55static struct mtd_partition stm25p_partitions[] = {
56 /* sflash */
57 [0] = {
58 .name = "stm25p80",
59 .offset = 0x00000000,
60 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
61 .mask_flags = 0
62 }
63};
64
65#endif
66
67#elif defined(CONFIG_WILDFIREMOD)
68
69#define SPI_NUM_CHIPSELECTS 0x08
70#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
71#define SPI_CS_MASK 0x78
72
73#define FLASH_BLOCKSIZE (1024*64)
74#define FLASH_NUMBLOCKS 64
75#define FLASH_TYPE "m25p32"
76/* Reserve 1M for the kernel parition */
77#define FLASH_KERNEL_SIZE (1024 * 1024)
78
79#define M25P80_CS 5
80#define MMC_CS 6
81
82#ifdef CONFIG_MTD_PARTITIONS
83static struct mtd_partition stm25p_partitions[] = {
84 /* sflash */
85 [0] = {
86 .name = "kernel",
87 .offset = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
88 .size = FLASH_KERNEL_SIZE,
89 .mask_flags = 0
90 },
91 [1] = {
92 .name = "image",
93 .offset = 0x00000000,
94 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
95 .mask_flags = 0
96 },
97 [2] = {
98 .name = "all",
99 .offset = 0x00000000,
100 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
101 .mask_flags = 0
102 }
103};
104#endif
105
106#else
107#define SPI_NUM_CHIPSELECTS 0x04
108#define SPI_PAR_VAL 0x7F /* Enable DIN, DOUT, CLK, CS0 - CS4 */
109#endif
110
111#ifdef MMC_CS
112static struct coldfire_spi_chip flash_chip_info = {
113 .mode = SPI_MODE_0,
114 .bits_per_word = 16,
115 .del_cs_to_clk = 17,
116 .del_after_trans = 1,
117 .void_write_data = 0
118};
119
120static struct coldfire_spi_chip mmc_chip_info = {
121 .mode = SPI_MODE_0,
122 .bits_per_word = 16,
123 .del_cs_to_clk = 17,
124 .del_after_trans = 1,
125 .void_write_data = 0xFFFF
126};
127#endif
128
129#ifdef M25P80_CS
130static struct flash_platform_data stm25p80_platform_data = {
131 .name = "ST M25P80 SPI Flash chip",
132#ifdef CONFIG_MTD_PARTITIONS
133 .parts = stm25p_partitions,
134 .nr_parts = sizeof(stm25p_partitions) / sizeof(*stm25p_partitions),
135#endif
136 .type = FLASH_TYPE
137};
138#endif
139
140static struct spi_board_info spi_board_info[] __initdata = {
141#ifdef M25P80_CS
142 {
143 .modalias = "m25p80",
144 .max_speed_hz = 16000000,
145 .bus_num = 1,
146 .chip_select = M25P80_CS,
147 .platform_data = &stm25p80_platform_data,
148 .controller_data = &flash_chip_info
149 },
150#endif
151#ifdef MMC_CS
152 {
153 .modalias = "mmc_spi",
154 .max_speed_hz = 16000000,
155 .bus_num = 1,
156 .chip_select = MMC_CS,
157 .controller_data = &mmc_chip_info
158 }
159#endif
160};
161
162static struct coldfire_spi_master coldfire_master_info = {
163 .bus_num = 1,
164 .num_chipselect = SPI_NUM_CHIPSELECTS,
165 .irq_source = MCF5282_QSPI_IRQ_SOURCE,
166 .irq_vector = MCF5282_QSPI_IRQ_VECTOR,
167 .irq_mask = ((0x01 << MCF5282_QSPI_IRQ_SOURCE) | 0x01),
168 .irq_lp = 0x2B, /* Level 5 and Priority 3 */
169 .par_val = SPI_PAR_VAL,
170 .cs_control = coldfire_qspi_cs_control,
171};
172
173static struct resource coldfire_spi_resources[] = {
174 [0] = {
175 .name = "qspi-par",
176 .start = MCF5282_QSPI_PAR,
177 .end = MCF5282_QSPI_PAR,
178 .flags = IORESOURCE_MEM
179 },
180
181 [1] = {
182 .name = "qspi-module",
183 .start = MCF5282_QSPI_QMR,
184 .end = MCF5282_QSPI_QMR + 0x18,
185 .flags = IORESOURCE_MEM
186 },
187
188 [2] = {
189 .name = "qspi-int-level",
190 .start = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
191 .end = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
192 .flags = IORESOURCE_MEM
193 },
194
195 [3] = {
196 .name = "qspi-int-mask",
197 .start = MCF5282_INTC0 + MCFINTC_IMRL,
198 .end = MCF5282_INTC0 + MCFINTC_IMRL,
199 .flags = IORESOURCE_MEM
200 }
201};
202
203static struct platform_device coldfire_spi = {
204 .name = "spi_coldfire",
205 .id = -1,
206 .resource = coldfire_spi_resources,
207 .num_resources = ARRAY_SIZE(coldfire_spi_resources),
208 .dev = {
209 .platform_data = &coldfire_master_info,
210 }
211};
212
213static void coldfire_qspi_cs_control(u8 cs, u8 command)
214{
215 u8 cs_bit = ((0x01 << cs) << 3) & SPI_CS_MASK;
216
217#if defined(CONFIG_WILDFIRE)
218 u8 cs_mask = ~(((0x01 << cs) << 3) & SPI_CS_MASK);
219#endif
220#if defined(CONFIG_WILDFIREMOD)
221 u8 cs_mask = (cs << 3) & SPI_CS_MASK;
222#endif
223
224 /*
225 * Don't do anything if the chip select is not
226 * one of the port qs pins.
227 */
228 if (command & QSPI_CS_INIT) {
229#if defined(CONFIG_WILDFIRE)
230 MCF5282_GPIO_DDRQS |= cs_bit;
231 MCF5282_GPIO_PQSPAR &= ~cs_bit;
232#endif
233
234#if defined(CONFIG_WILDFIREMOD)
235 MCF5282_GPIO_DDRQS |= SPI_CS_MASK;
236 MCF5282_GPIO_PQSPAR &= ~SPI_CS_MASK;
237#endif
238 }
239
240 if (command & QSPI_CS_ASSERT) {
241 MCF5282_GPIO_PORTQS &= ~SPI_CS_MASK;
242 MCF5282_GPIO_PORTQS |= cs_mask;
243 } else if (command & QSPI_CS_DROP) {
244 MCF5282_GPIO_PORTQS |= SPI_CS_MASK;
245 }
246}
247
248static int __init spi_dev_init(void)
249{
250 int retval;
251
252 retval = platform_device_register(&coldfire_spi);
253 if (retval < 0)
254 return retval;
255
256 if (ARRAY_SIZE(spi_board_info))
257 retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
258
259 return retval;
260}
261
262#endif /* CONFIG_SPI */
263 35
264/***************************************************************************/ 36/***************************************************************************/
265 37
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index ac5d541368e9..6c5b40905dd6 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -3,6 +3,8 @@
3/* 3/*
4 * Architecture specific compatibility types 4 * Architecture specific compatibility types
5 */ 5 */
6#include <linux/seccomp.h>
7#include <linux/thread_info.h>
6#include <linux/types.h> 8#include <linux/types.h>
7#include <asm/page.h> 9#include <asm/page.h>
8#include <asm/ptrace.h> 10#include <asm/ptrace.h>
@@ -218,4 +220,9 @@ struct compat_shmid64_ds {
218 compat_ulong_t __unused2; 220 compat_ulong_t __unused2;
219}; 221};
220 222
223static inline int is_compat_task(void)
224{
225 return test_thread_flag(TIF_32BIT);
226}
227
221#endif /* _ASM_COMPAT_H */ 228#endif /* _ASM_COMPAT_H */
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index fb371f5ce132..d6b772ba3b8f 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -142,6 +142,10 @@ static void __init gef_sbc610_nec_fixup(struct pci_dev *pdev)
142{ 142{
143 unsigned int val; 143 unsigned int val;
144 144
145 /* Do not do the fixup on other platforms! */
146 if (!machine_is(gef_sbc610))
147 return;
148
145 printk(KERN_INFO "Running NEC uPD720101 Fixup\n"); 149 printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
146 150
147 /* Ensure ports 1, 2, 3, 4 & 5 are enabled */ 151 /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c
index c42cd898f68b..6118890c946d 100644
--- a/arch/s390/crypto/aes_s390.c
+++ b/arch/s390/crypto/aes_s390.c
@@ -556,7 +556,7 @@ static void __exit aes_s390_fini(void)
556module_init(aes_s390_init); 556module_init(aes_s390_init);
557module_exit(aes_s390_fini); 557module_exit(aes_s390_fini);
558 558
559MODULE_ALIAS("aes"); 559MODULE_ALIAS("aes-all");
560 560
561MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm"); 561MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm");
562MODULE_LICENSE("GPL"); 562MODULE_LICENSE("GPL");
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index 72da416f6162..15b6d450fbf0 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -22,6 +22,7 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
24#include <linux/spi/spi_gpio.h> 24#include <linux/spi/spi_gpio.h>
25#include <media/soc_camera.h>
25#include <media/soc_camera_platform.h> 26#include <media/soc_camera_platform.h>
26#include <media/sh_mobile_ceu.h> 27#include <media/sh_mobile_ceu.h>
27#include <video/sh_mobile_lcdc.h> 28#include <video/sh_mobile_lcdc.h>
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 469f3450bf81..87717f3687d2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -138,6 +138,9 @@ config ARCH_HAS_CACHE_LINE_SIZE
138config HAVE_SETUP_PER_CPU_AREA 138config HAVE_SETUP_PER_CPU_AREA
139 def_bool y 139 def_bool y
140 140
141config HAVE_DYNAMIC_PER_CPU_AREA
142 def_bool y
143
141config HAVE_CPUMASK_OF_CPU_MAP 144config HAVE_CPUMASK_OF_CPU_MAP
142 def_bool X86_64_SMP 145 def_bool X86_64_SMP
143 146
@@ -780,6 +783,11 @@ config X86_MCE_AMD
780 Additional support for AMD specific MCE features such as 783 Additional support for AMD specific MCE features such as
781 the DRAM Error Threshold. 784 the DRAM Error Threshold.
782 785
786config X86_MCE_THRESHOLD
787 depends on X86_MCE_AMD || X86_MCE_INTEL
788 bool
789 default y
790
783config X86_MCE_NONFATAL 791config X86_MCE_NONFATAL
784 tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4" 792 tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4"
785 depends on X86_32 && X86_MCE 793 depends on X86_32 && X86_MCE
@@ -1125,7 +1133,7 @@ config NODES_SHIFT
1125 Specify the maximum number of NUMA Nodes available on the target 1133 Specify the maximum number of NUMA Nodes available on the target
1126 system. Increases memory reserved to accomodate various tables. 1134 system. Increases memory reserved to accomodate various tables.
1127 1135
1128config HAVE_ARCH_BOOTMEM_NODE 1136config HAVE_ARCH_BOOTMEM
1129 def_bool y 1137 def_bool y
1130 depends on X86_32 && NUMA 1138 depends on X86_32 && NUMA
1131 1139
@@ -1423,7 +1431,7 @@ config CRASH_DUMP
1423config KEXEC_JUMP 1431config KEXEC_JUMP
1424 bool "kexec jump (EXPERIMENTAL)" 1432 bool "kexec jump (EXPERIMENTAL)"
1425 depends on EXPERIMENTAL 1433 depends on EXPERIMENTAL
1426 depends on KEXEC && HIBERNATION && X86_32 1434 depends on KEXEC && HIBERNATION
1427 ---help--- 1435 ---help---
1428 Jump between original kernel and kexeced kernel and invoke 1436 Jump between original kernel and kexeced kernel and invoke
1429 code in physical address mode via KEXEC 1437 code in physical address mode via KEXEC
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 4ef949c1972e..394d177d721b 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -379,6 +379,7 @@ static inline u32 safe_apic_wait_icr_idle(void)
379 379
380static inline void ack_APIC_irq(void) 380static inline void ack_APIC_irq(void)
381{ 381{
382#ifdef CONFIG_X86_LOCAL_APIC
382 /* 383 /*
383 * ack_APIC_irq() actually gets compiled as a single instruction 384 * ack_APIC_irq() actually gets compiled as a single instruction
384 * ... yummie. 385 * ... yummie.
@@ -386,6 +387,7 @@ static inline void ack_APIC_irq(void)
386 387
387 /* Docs say use 0 for future compatibility */ 388 /* Docs say use 0 for future compatibility */
388 apic_write(APIC_EOI, 0); 389 apic_write(APIC_EOI, 0);
390#endif
389} 391}
390 392
391static inline unsigned default_get_apic_id(unsigned long x) 393static inline unsigned default_get_apic_id(unsigned long x)
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index 63134e31e8b9..bc9514fb3b13 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -53,6 +53,7 @@
53#define APIC_ESR_SENDILL 0x00020 53#define APIC_ESR_SENDILL 0x00020
54#define APIC_ESR_RECVILL 0x00040 54#define APIC_ESR_RECVILL 0x00040
55#define APIC_ESR_ILLREGA 0x00080 55#define APIC_ESR_ILLREGA 0x00080
56#define APIC_LVTCMCI 0x2f0
56#define APIC_ICR 0x300 57#define APIC_ICR 0x300
57#define APIC_DEST_SELF 0x40000 58#define APIC_DEST_SELF 0x40000
58#define APIC_DEST_ALLINC 0x80000 59#define APIC_DEST_ALLINC 0x80000
diff --git a/arch/x86/include/asm/cacheflush.h b/arch/x86/include/asm/cacheflush.h
index 2f8466540fb5..5b301b7ff5f4 100644
--- a/arch/x86/include/asm/cacheflush.h
+++ b/arch/x86/include/asm/cacheflush.h
@@ -5,24 +5,43 @@
5#include <linux/mm.h> 5#include <linux/mm.h>
6 6
7/* Caches aren't brain-dead on the intel. */ 7/* Caches aren't brain-dead on the intel. */
8#define flush_cache_all() do { } while (0) 8static inline void flush_cache_all(void) { }
9#define flush_cache_mm(mm) do { } while (0) 9static inline void flush_cache_mm(struct mm_struct *mm) { }
10#define flush_cache_dup_mm(mm) do { } while (0) 10static inline void flush_cache_dup_mm(struct mm_struct *mm) { }
11#define flush_cache_range(vma, start, end) do { } while (0) 11static inline void flush_cache_range(struct vm_area_struct *vma,
12#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) 12 unsigned long start, unsigned long end) { }
13#define flush_dcache_page(page) do { } while (0) 13static inline void flush_cache_page(struct vm_area_struct *vma,
14#define flush_dcache_mmap_lock(mapping) do { } while (0) 14 unsigned long vmaddr, unsigned long pfn) { }
15#define flush_dcache_mmap_unlock(mapping) do { } while (0) 15static inline void flush_dcache_page(struct page *page) { }
16#define flush_icache_range(start, end) do { } while (0) 16static inline void flush_dcache_mmap_lock(struct address_space *mapping) { }
17#define flush_icache_page(vma, pg) do { } while (0) 17static inline void flush_dcache_mmap_unlock(struct address_space *mapping) { }
18#define flush_icache_user_range(vma, pg, adr, len) do { } while (0) 18static inline void flush_icache_range(unsigned long start,
19#define flush_cache_vmap(start, end) do { } while (0) 19 unsigned long end) { }
20#define flush_cache_vunmap(start, end) do { } while (0) 20static inline void flush_icache_page(struct vm_area_struct *vma,
21 struct page *page) { }
22static inline void flush_icache_user_range(struct vm_area_struct *vma,
23 struct page *page,
24 unsigned long addr,
25 unsigned long len) { }
26static inline void flush_cache_vmap(unsigned long start, unsigned long end) { }
27static inline void flush_cache_vunmap(unsigned long start,
28 unsigned long end) { }
21 29
22#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 30static inline void copy_to_user_page(struct vm_area_struct *vma,
23 memcpy((dst), (src), (len)) 31 struct page *page, unsigned long vaddr,
24#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 32 void *dst, const void *src,
25 memcpy((dst), (src), (len)) 33 unsigned long len)
34{
35 memcpy(dst, src, len);
36}
37
38static inline void copy_from_user_page(struct vm_area_struct *vma,
39 struct page *page, unsigned long vaddr,
40 void *dst, const void *src,
41 unsigned long len)
42{
43 memcpy(dst, src, len);
44}
26 45
27#define PG_non_WB PG_arch_1 46#define PG_non_WB PG_arch_1
28PAGEFLAG(NonWB, non_WB) 47PAGEFLAG(NonWB, non_WB)
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index ca5ffb2856b6..edc90f23e708 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -37,8 +37,6 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...);
37 37
38#else /* !CONFIG_X86_32 */ 38#else /* !CONFIG_X86_32 */
39 39
40#define MAX_EFI_IO_PAGES 100
41
42extern u64 efi_call0(void *fp); 40extern u64 efi_call0(void *fp);
43extern u64 efi_call1(void *fp, u64 arg1); 41extern u64 efi_call1(void *fp, u64 arg1);
44extern u64 efi_call2(void *fp, u64 arg1, u64 arg2); 42extern u64 efi_call2(void *fp, u64 arg1, u64 arg2);
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 854d538ae857..c2e6bedaf258 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -33,6 +33,8 @@ BUILD_INTERRUPT3(invalidate_interrupt7,INVALIDATE_TLB_VECTOR_START+7,
33 smp_invalidate_interrupt) 33 smp_invalidate_interrupt)
34#endif 34#endif
35 35
36BUILD_INTERRUPT(generic_interrupt, GENERIC_INTERRUPT_VECTOR)
37
36/* 38/*
37 * every pentium local APIC has two 'local interrupts', with a 39 * every pentium local APIC has two 'local interrupts', with a
38 * soft-definable vector attached to both interrupts, one of 40 * soft-definable vector attached to both interrupts, one of
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index dca8f03da5b2..63a79c77d220 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -24,9 +24,6 @@
24#include <asm/kmap_types.h> 24#include <asm/kmap_types.h>
25#else 25#else
26#include <asm/vsyscall.h> 26#include <asm/vsyscall.h>
27#ifdef CONFIG_EFI
28#include <asm/efi.h>
29#endif
30#endif 27#endif
31 28
32/* 29/*
@@ -92,13 +89,6 @@ enum fixed_addresses {
92 FIX_IO_APIC_BASE_0, 89 FIX_IO_APIC_BASE_0,
93 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, 90 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
94#endif 91#endif
95#ifdef CONFIG_X86_64
96#ifdef CONFIG_EFI
97 FIX_EFI_IO_MAP_LAST_PAGE,
98 FIX_EFI_IO_MAP_FIRST_PAGE = FIX_EFI_IO_MAP_LAST_PAGE
99 + MAX_EFI_IO_PAGES - 1,
100#endif
101#endif
102#ifdef CONFIG_X86_VISWS_APIC 92#ifdef CONFIG_X86_VISWS_APIC
103 FIX_CO_CPU, /* Cobalt timer */ 93 FIX_CO_CPU, /* Cobalt timer */
104 FIX_CO_APIC, /* Cobalt APIC Redirection Table */ 94 FIX_CO_APIC, /* Cobalt APIC Redirection Table */
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h
index 176f058e7159..039db6aa8e02 100644
--- a/arch/x86/include/asm/hardirq.h
+++ b/arch/x86/include/asm/hardirq.h
@@ -12,6 +12,7 @@ typedef struct {
12 unsigned int apic_timer_irqs; /* arch dependent */ 12 unsigned int apic_timer_irqs; /* arch dependent */
13 unsigned int irq_spurious_count; 13 unsigned int irq_spurious_count;
14#endif 14#endif
15 unsigned int generic_irqs; /* arch dependent */
15#ifdef CONFIG_SMP 16#ifdef CONFIG_SMP
16 unsigned int irq_resched_count; 17 unsigned int irq_resched_count;
17 unsigned int irq_call_count; 18 unsigned int irq_call_count;
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 370e1c83bb49..b762ea49bd70 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -27,6 +27,7 @@
27 27
28/* Interrupt handlers registered during init_IRQ */ 28/* Interrupt handlers registered during init_IRQ */
29extern void apic_timer_interrupt(void); 29extern void apic_timer_interrupt(void);
30extern void generic_interrupt(void);
30extern void error_interrupt(void); 31extern void error_interrupt(void);
31extern void spurious_interrupt(void); 32extern void spurious_interrupt(void);
32extern void thermal_interrupt(void); 33extern void thermal_interrupt(void);
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index 48f0004db8c9..71c9e5183982 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -172,7 +172,13 @@ static inline void __save_init_fpu(struct task_struct *tsk)
172 172
173#else /* CONFIG_X86_32 */ 173#else /* CONFIG_X86_32 */
174 174
175extern void finit(void); 175#ifdef CONFIG_MATH_EMULATION
176extern void finit_task(struct task_struct *tsk);
177#else
178static inline void finit_task(struct task_struct *tsk)
179{
180}
181#endif
176 182
177static inline void tolerant_fwait(void) 183static inline void tolerant_fwait(void)
178{ 184{
diff --git a/arch/x86/include/asm/init.h b/arch/x86/include/asm/init.h
new file mode 100644
index 000000000000..36fb1a6a5109
--- /dev/null
+++ b/arch/x86/include/asm/init.h
@@ -0,0 +1,18 @@
1#ifndef _ASM_X86_INIT_32_H
2#define _ASM_X86_INIT_32_H
3
4#ifdef CONFIG_X86_32
5extern void __init early_ioremap_page_table_range_init(void);
6#endif
7
8extern unsigned long __init
9kernel_physical_mapping_init(unsigned long start,
10 unsigned long end,
11 unsigned long page_size_mask);
12
13
14extern unsigned long __initdata e820_table_start;
15extern unsigned long __meminitdata e820_table_end;
16extern unsigned long __meminitdata e820_table_top;
17
18#endif /* _ASM_X86_INIT_32_H */
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 683d0b4c00fc..e5383e3d2f8c 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -172,8 +172,6 @@ static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
172 172
173extern void iounmap(volatile void __iomem *addr); 173extern void iounmap(volatile void __iomem *addr);
174 174
175extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
176
177 175
178#ifdef CONFIG_X86_32 176#ifdef CONFIG_X86_32
179# include "io_32.h" 177# include "io_32.h"
@@ -198,7 +196,6 @@ extern void early_ioremap_reset(void);
198extern void __iomem *early_ioremap(unsigned long offset, unsigned long size); 196extern void __iomem *early_ioremap(unsigned long offset, unsigned long size);
199extern void __iomem *early_memremap(unsigned long offset, unsigned long size); 197extern void __iomem *early_memremap(unsigned long offset, unsigned long size);
200extern void early_iounmap(void __iomem *addr, unsigned long size); 198extern void early_iounmap(void __iomem *addr, unsigned long size);
201extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
202 199
203#define IO_SPACE_LIMIT 0xffff 200#define IO_SPACE_LIMIT 0xffff
204 201
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 107eb2196691..f38481bcd455 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -36,6 +36,7 @@ static inline int irq_canonicalize(int irq)
36extern void fixup_irqs(void); 36extern void fixup_irqs(void);
37#endif 37#endif
38 38
39extern void (*generic_interrupt_extension)(void);
39extern void init_IRQ(void); 40extern void init_IRQ(void);
40extern void native_init_IRQ(void); 41extern void native_init_IRQ(void);
41extern bool handle_irq(unsigned irq, struct pt_regs *regs); 42extern bool handle_irq(unsigned irq, struct pt_regs *regs);
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 8a285f356f8a..3cbd79bbb47c 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -112,6 +112,11 @@
112#define LOCAL_PERF_VECTOR 0xee 112#define LOCAL_PERF_VECTOR 0xee
113 113
114/* 114/*
115 * Generic system vector for platform specific use
116 */
117#define GENERIC_INTERRUPT_VECTOR 0xed
118
119/*
115 * First APIC vector available to drivers: (vectors 0x30-0xee) we 120 * First APIC vector available to drivers: (vectors 0x30-0xee) we
116 * start at 0x31(0x41) to spread out vectors evenly between priority 121 * start at 0x31(0x41) to spread out vectors evenly between priority
117 * levels. (0x80 is the syscall vector) 122 * levels. (0x80 is the syscall vector)
diff --git a/arch/x86/include/asm/kexec.h b/arch/x86/include/asm/kexec.h
index 0ceb6d19ed30..317ff1703d0b 100644
--- a/arch/x86/include/asm/kexec.h
+++ b/arch/x86/include/asm/kexec.h
@@ -9,13 +9,13 @@
9# define PAGES_NR 4 9# define PAGES_NR 4
10#else 10#else
11# define PA_CONTROL_PAGE 0 11# define PA_CONTROL_PAGE 0
12# define PA_TABLE_PAGE 1 12# define VA_CONTROL_PAGE 1
13# define PAGES_NR 2 13# define PA_TABLE_PAGE 2
14# define PA_SWAP_PAGE 3
15# define PAGES_NR 4
14#endif 16#endif
15 17
16#ifdef CONFIG_X86_32
17# define KEXEC_CONTROL_CODE_MAX_SIZE 2048 18# define KEXEC_CONTROL_CODE_MAX_SIZE 2048
18#endif
19 19
20#ifndef __ASSEMBLY__ 20#ifndef __ASSEMBLY__
21 21
@@ -136,10 +136,11 @@ relocate_kernel(unsigned long indirection_page,
136 unsigned int has_pae, 136 unsigned int has_pae,
137 unsigned int preserve_context); 137 unsigned int preserve_context);
138#else 138#else
139NORET_TYPE void 139unsigned long
140relocate_kernel(unsigned long indirection_page, 140relocate_kernel(unsigned long indirection_page,
141 unsigned long page_list, 141 unsigned long page_list,
142 unsigned long start_address) ATTRIB_NORET; 142 unsigned long start_address,
143 unsigned int preserve_context);
143#endif 144#endif
144 145
145#define ARCH_HAS_KIMAGE_ARCH 146#define ARCH_HAS_KIMAGE_ARCH
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h
index 9320e2a8a26a..a0d70b46c27c 100644
--- a/arch/x86/include/asm/linkage.h
+++ b/arch/x86/include/asm/linkage.h
@@ -4,11 +4,6 @@
4#undef notrace 4#undef notrace
5#define notrace __attribute__((no_instrument_function)) 5#define notrace __attribute__((no_instrument_function))
6 6
7#ifdef CONFIG_X86_64
8#define __ALIGN .p2align 4,,15
9#define __ALIGN_STR ".p2align 4,,15"
10#endif
11
12#ifdef CONFIG_X86_32 7#ifdef CONFIG_X86_32
13#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0))) 8#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
14/* 9/*
@@ -50,16 +45,25 @@
50 __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \ 45 __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \
51 "g" (arg4), "g" (arg5), "g" (arg6)) 46 "g" (arg4), "g" (arg5), "g" (arg6))
52 47
53#endif 48#endif /* CONFIG_X86_32 */
49
50#ifdef __ASSEMBLY__
54 51
55#define GLOBAL(name) \ 52#define GLOBAL(name) \
56 .globl name; \ 53 .globl name; \
57 name: 54 name:
58 55
56#ifdef CONFIG_X86_64
57#define __ALIGN .p2align 4,,15
58#define __ALIGN_STR ".p2align 4,,15"
59#endif
60
59#ifdef CONFIG_X86_ALIGNMENT_16 61#ifdef CONFIG_X86_ALIGNMENT_16
60#define __ALIGN .align 16,0x90 62#define __ALIGN .align 16,0x90
61#define __ALIGN_STR ".align 16,0x90" 63#define __ALIGN_STR ".align 16,0x90"
62#endif 64#endif
63 65
66#endif /* __ASSEMBLY__ */
67
64#endif /* _ASM_X86_LINKAGE_H */ 68#endif /* _ASM_X86_LINKAGE_H */
65 69
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 32c6e17b960b..563933e06a35 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -11,6 +11,8 @@
11 */ 11 */
12 12
13#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ 13#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */
14#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
15#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
14 16
15#define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */ 17#define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */
16#define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */ 18#define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */
@@ -90,14 +92,29 @@ extern int mce_disabled;
90 92
91#include <asm/atomic.h> 93#include <asm/atomic.h>
92 94
95void mce_setup(struct mce *m);
93void mce_log(struct mce *m); 96void mce_log(struct mce *m);
94DECLARE_PER_CPU(struct sys_device, device_mce); 97DECLARE_PER_CPU(struct sys_device, device_mce);
95extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 98extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
96 99
100/*
101 * To support more than 128 would need to escape the predefined
102 * Linux defined extended banks first.
103 */
104#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
105
97#ifdef CONFIG_X86_MCE_INTEL 106#ifdef CONFIG_X86_MCE_INTEL
98void mce_intel_feature_init(struct cpuinfo_x86 *c); 107void mce_intel_feature_init(struct cpuinfo_x86 *c);
108void cmci_clear(void);
109void cmci_reenable(void);
110void cmci_rediscover(int dying);
111void cmci_recheck(void);
99#else 112#else
100static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 113static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
114static inline void cmci_clear(void) {}
115static inline void cmci_reenable(void) {}
116static inline void cmci_rediscover(int dying) {}
117static inline void cmci_recheck(void) {}
101#endif 118#endif
102 119
103#ifdef CONFIG_X86_MCE_AMD 120#ifdef CONFIG_X86_MCE_AMD
@@ -106,11 +123,23 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c);
106static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 123static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
107#endif 124#endif
108 125
109void mce_log_therm_throt_event(unsigned int cpu, __u64 status); 126extern int mce_available(struct cpuinfo_x86 *c);
127
128void mce_log_therm_throt_event(__u64 status);
110 129
111extern atomic_t mce_entry; 130extern atomic_t mce_entry;
112 131
113extern void do_machine_check(struct pt_regs *, long); 132extern void do_machine_check(struct pt_regs *, long);
133
134typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
135DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
136
137enum mcp_flags {
138 MCP_TIMESTAMP = (1 << 0), /* log time stamp */
139 MCP_UC = (1 << 1), /* log uncorrected errors */
140};
141extern void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
142
114extern int mce_notify_user(void); 143extern int mce_notify_user(void);
115 144
116#endif /* !CONFIG_X86_32 */ 145#endif /* !CONFIG_X86_32 */
@@ -120,8 +149,8 @@ extern void mcheck_init(struct cpuinfo_x86 *c);
120#else 149#else
121#define mcheck_init(c) do { } while (0) 150#define mcheck_init(c) do { } while (0)
122#endif 151#endif
123extern void stop_mce(void); 152
124extern void restart_mce(void); 153extern void (*mce_threshold_vector)(void);
125 154
126#endif /* __KERNEL__ */ 155#endif /* __KERNEL__ */
127#endif /* _ASM_X86_MCE_H */ 156#endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h
index 105fb90a0635..ede6998bd92c 100644
--- a/arch/x86/include/asm/mmzone_32.h
+++ b/arch/x86/include/asm/mmzone_32.h
@@ -91,46 +91,9 @@ static inline int pfn_valid(int pfn)
91#endif /* CONFIG_DISCONTIGMEM */ 91#endif /* CONFIG_DISCONTIGMEM */
92 92
93#ifdef CONFIG_NEED_MULTIPLE_NODES 93#ifdef CONFIG_NEED_MULTIPLE_NODES
94 94/* always use node 0 for bootmem on this numa platform */
95/* 95#define bootmem_arch_preferred_node(__bdata, size, align, goal, limit) \
96 * Following are macros that are specific to this numa platform. 96 (NODE_DATA(0)->bdata)
97 */
98#define reserve_bootmem(addr, size, flags) \
99 reserve_bootmem_node(NODE_DATA(0), (addr), (size), (flags))
100#define alloc_bootmem(x) \
101 __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
102#define alloc_bootmem_nopanic(x) \
103 __alloc_bootmem_node_nopanic(NODE_DATA(0), (x), SMP_CACHE_BYTES, \
104 __pa(MAX_DMA_ADDRESS))
105#define alloc_bootmem_low(x) \
106 __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
107#define alloc_bootmem_pages(x) \
108 __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
109#define alloc_bootmem_pages_nopanic(x) \
110 __alloc_bootmem_node_nopanic(NODE_DATA(0), (x), PAGE_SIZE, \
111 __pa(MAX_DMA_ADDRESS))
112#define alloc_bootmem_low_pages(x) \
113 __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
114#define alloc_bootmem_node(pgdat, x) \
115({ \
116 struct pglist_data __maybe_unused \
117 *__alloc_bootmem_node__pgdat = (pgdat); \
118 __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, \
119 __pa(MAX_DMA_ADDRESS)); \
120})
121#define alloc_bootmem_pages_node(pgdat, x) \
122({ \
123 struct pglist_data __maybe_unused \
124 *__alloc_bootmem_node__pgdat = (pgdat); \
125 __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, \
126 __pa(MAX_DMA_ADDRESS)); \
127})
128#define alloc_bootmem_low_pages_node(pgdat, x) \
129({ \
130 struct pglist_data __maybe_unused \
131 *__alloc_bootmem_node__pgdat = (pgdat); \
132 __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0); \
133})
134#endif /* CONFIG_NEED_MULTIPLE_NODES */ 97#endif /* CONFIG_NEED_MULTIPLE_NODES */
135 98
136#endif /* _ASM_X86_MMZONE_32_H */ 99#endif /* _ASM_X86_MMZONE_32_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 358acc59ae04..2dbd2314139e 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -77,6 +77,11 @@
77#define MSR_IA32_MC0_ADDR 0x00000402 77#define MSR_IA32_MC0_ADDR 0x00000402
78#define MSR_IA32_MC0_MISC 0x00000403 78#define MSR_IA32_MC0_MISC 0x00000403
79 79
80/* These are consecutive and not in the normal 4er MCE bank block */
81#define MSR_IA32_MC0_CTL2 0x00000280
82#define CMCI_EN (1ULL << 30)
83#define CMCI_THRESHOLD_MASK 0xffffULL
84
80#define MSR_P6_PERFCTR0 0x000000c1 85#define MSR_P6_PERFCTR0 0x000000c1
81#define MSR_P6_PERFCTR1 0x000000c2 86#define MSR_P6_PERFCTR1 0x000000c2
82#define MSR_P6_EVNTSEL0 0x00000186 87#define MSR_P6_EVNTSEL0 0x00000186
diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_types.h
index 2d625da6603c..826ad37006ab 100644
--- a/arch/x86/include/asm/page_types.h
+++ b/arch/x86/include/asm/page_types.h
@@ -40,14 +40,8 @@
40 40
41#ifndef __ASSEMBLY__ 41#ifndef __ASSEMBLY__
42 42
43struct pgprot;
44
45extern int page_is_ram(unsigned long pagenr); 43extern int page_is_ram(unsigned long pagenr);
46extern int devmem_is_allowed(unsigned long pagenr); 44extern int devmem_is_allowed(unsigned long pagenr);
47extern void map_devmem(unsigned long pfn, unsigned long size,
48 struct pgprot vma_prot);
49extern void unmap_devmem(unsigned long pfn, unsigned long size,
50 struct pgprot vma_prot);
51 45
52extern unsigned long max_low_pfn_mapped; 46extern unsigned long max_low_pfn_mapped;
53extern unsigned long max_pfn_mapped; 47extern unsigned long max_pfn_mapped;
diff --git a/arch/x86/include/asm/pat.h b/arch/x86/include/asm/pat.h
index b0e70056838e..2cd07b9422f4 100644
--- a/arch/x86/include/asm/pat.h
+++ b/arch/x86/include/asm/pat.h
@@ -2,6 +2,7 @@
2#define _ASM_X86_PAT_H 2#define _ASM_X86_PAT_H
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5#include <asm/pgtable_types.h>
5 6
6#ifdef CONFIG_X86_PAT 7#ifdef CONFIG_X86_PAT
7extern int pat_enabled; 8extern int pat_enabled;
@@ -17,5 +18,9 @@ extern int free_memtype(u64 start, u64 end);
17 18
18extern int kernel_map_sync_memtype(u64 base, unsigned long size, 19extern int kernel_map_sync_memtype(u64 base, unsigned long size,
19 unsigned long flag); 20 unsigned long flag);
21extern void map_devmem(unsigned long pfn, unsigned long size,
22 struct pgprot vma_prot);
23extern void unmap_devmem(unsigned long pfn, unsigned long size,
24 struct pgprot vma_prot);
20 25
21#endif /* _ASM_X86_PAT_H */ 26#endif /* _ASM_X86_PAT_H */
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index aee103b26d01..8f1d2fbec1d4 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -43,6 +43,14 @@
43#else /* ...!ASSEMBLY */ 43#else /* ...!ASSEMBLY */
44 44
45#include <linux/stringify.h> 45#include <linux/stringify.h>
46#include <asm/sections.h>
47
48#define __addr_to_pcpu_ptr(addr) \
49 (void *)((unsigned long)(addr) - (unsigned long)pcpu_base_addr \
50 + (unsigned long)__per_cpu_start)
51#define __pcpu_ptr_to_addr(ptr) \
52 (void *)((unsigned long)(ptr) + (unsigned long)pcpu_base_addr \
53 - (unsigned long)__per_cpu_start)
46 54
47#ifdef CONFIG_SMP 55#ifdef CONFIG_SMP
48#define __percpu_arg(x) "%%"__stringify(__percpu_seg)":%P" #x 56#define __percpu_arg(x) "%%"__stringify(__percpu_seg)":%P" #x
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 1c097a3a6669..d0812e155f1d 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -288,6 +288,8 @@ static inline int is_new_memtype_allowed(unsigned long flags,
288 return 1; 288 return 1;
289} 289}
290 290
291pmd_t *populate_extra_pmd(unsigned long vaddr);
292pte_t *populate_extra_pte(unsigned long vaddr);
291#endif /* __ASSEMBLY__ */ 293#endif /* __ASSEMBLY__ */
292 294
293#ifdef CONFIG_X86_32 295#ifdef CONFIG_X86_32
diff --git a/arch/x86/include/asm/pgtable_32_types.h b/arch/x86/include/asm/pgtable_32_types.h
index bd8df3b2fe04..2733fad45f98 100644
--- a/arch/x86/include/asm/pgtable_32_types.h
+++ b/arch/x86/include/asm/pgtable_32_types.h
@@ -25,6 +25,11 @@
25 * area for the same reason. ;) 25 * area for the same reason. ;)
26 */ 26 */
27#define VMALLOC_OFFSET (8 * 1024 * 1024) 27#define VMALLOC_OFFSET (8 * 1024 * 1024)
28
29#ifndef __ASSEMBLER__
30extern bool __vmalloc_start_set; /* set once high_memory is set */
31#endif
32
28#define VMALLOC_START ((unsigned long)high_memory + VMALLOC_OFFSET) 33#define VMALLOC_START ((unsigned long)high_memory + VMALLOC_OFFSET)
29#ifdef CONFIG_X86_PAE 34#ifdef CONFIG_X86_PAE
30#define LAST_PKMAP 512 35#define LAST_PKMAP 512
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 4d258ad76a0f..b8238dc8786d 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -273,6 +273,7 @@ typedef struct page *pgtable_t;
273 273
274extern pteval_t __supported_pte_mask; 274extern pteval_t __supported_pte_mask;
275extern int nx_enabled; 275extern int nx_enabled;
276extern void set_nx(void);
276 277
277#define pgprot_writecombine pgprot_writecombine 278#define pgprot_writecombine pgprot_writecombine
278extern pgprot_t pgprot_writecombine(pgprot_t prot); 279extern pgprot_t pgprot_writecombine(pgprot_t prot);
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index 777327ef05c1..9f4dfba33b28 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -199,6 +199,10 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
199#define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 199#define SCIR_CPU_ACTIVITY 0x02 /* not idle */
200#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 200#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
201 201
202/* Loop through all installed blades */
203#define for_each_possible_blade(bid) \
204 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
205
202/* 206/*
203 * Macros for converting between kernel virtual addresses, socket local physical 207 * Macros for converting between kernel virtual addresses, socket local physical
204 * addresses, and UV global physical addresses. 208 * addresses, and UV global physical addresses.
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 4bd990ee43df..1a918dde46b5 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -164,6 +164,7 @@ static inline pte_t __pte_ma(pteval_t x)
164 164
165 165
166xmaddr_t arbitrary_virt_to_machine(void *address); 166xmaddr_t arbitrary_virt_to_machine(void *address);
167unsigned long arbitrary_virt_to_mfn(void *vaddr);
167void make_lowmem_page_readonly(void *vaddr); 168void make_lowmem_page_readonly(void *vaddr);
168void make_lowmem_page_readwrite(void *vaddr); 169void make_lowmem_page_readwrite(void *vaddr);
169 170
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 95f216bbfaf1..339ce35648e6 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -111,7 +111,7 @@ obj-$(CONFIG_SWIOTLB) += pci-swiotlb_64.o # NB rename without _64
111### 111###
112# 64 bit specific files 112# 64 bit specific files
113ifeq ($(CONFIG_X86_64),y) 113ifeq ($(CONFIG_X86_64),y)
114 obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o 114 obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o
115 obj-$(CONFIG_X86_PM_TIMER) += pmtimer_64.o 115 obj-$(CONFIG_X86_PM_TIMER) += pmtimer_64.o
116 obj-$(CONFIG_AUDIT) += audit_64.o 116 obj-$(CONFIG_AUDIT) += audit_64.o
117 117
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 6907b8e85d52..4c80f1557433 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -414,9 +414,17 @@ void __init alternative_instructions(void)
414 that might execute the to be patched code. 414 that might execute the to be patched code.
415 Other CPUs are not running. */ 415 Other CPUs are not running. */
416 stop_nmi(); 416 stop_nmi();
417#ifdef CONFIG_X86_MCE 417
418 stop_mce(); 418 /*
419#endif 419 * Don't stop machine check exceptions while patching.
420 * MCEs only happen when something got corrupted and in this
421 * case we must do something about the corruption.
422 * Ignoring it is worse than a unlikely patching race.
423 * Also machine checks tend to be broadcast and if one CPU
424 * goes into machine check the others follow quickly, so we don't
425 * expect a machine check to cause undue problems during to code
426 * patching.
427 */
420 428
421 apply_alternatives(__alt_instructions, __alt_instructions_end); 429 apply_alternatives(__alt_instructions, __alt_instructions_end);
422 430
@@ -456,9 +464,6 @@ void __init alternative_instructions(void)
456 (unsigned long)__smp_locks_end); 464 (unsigned long)__smp_locks_end);
457 465
458 restart_nmi(); 466 restart_nmi();
459#ifdef CONFIG_X86_MCE
460 restart_mce();
461#endif
462} 467}
463 468
464/** 469/**
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index f9cecdfd05c5..30909a258d0f 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -46,6 +46,7 @@
46#include <asm/idle.h> 46#include <asm/idle.h>
47#include <asm/mtrr.h> 47#include <asm/mtrr.h>
48#include <asm/smp.h> 48#include <asm/smp.h>
49#include <asm/mce.h>
49 50
50unsigned int num_processors; 51unsigned int num_processors;
51 52
@@ -842,6 +843,14 @@ void clear_local_APIC(void)
842 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 843 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
843 } 844 }
844#endif 845#endif
846#ifdef CONFIG_X86_MCE_INTEL
847 if (maxlvt >= 6) {
848 v = apic_read(APIC_LVTCMCI);
849 if (!(v & APIC_LVT_MASKED))
850 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
851 }
852#endif
853
845 /* 854 /*
846 * Clean APIC state for other OSs: 855 * Clean APIC state for other OSs:
847 */ 856 */
@@ -1241,6 +1250,12 @@ void __cpuinit setup_local_APIC(void)
1241 apic_write(APIC_LVT1, value); 1250 apic_write(APIC_LVT1, value);
1242 1251
1243 preempt_enable(); 1252 preempt_enable();
1253
1254#ifdef CONFIG_X86_MCE_INTEL
1255 /* Recheck CMCI information after local APIC is up on CPU #0 */
1256 if (smp_processor_id() == 0)
1257 cmci_recheck();
1258#endif
1244} 1259}
1245 1260
1246void __cpuinit end_local_APIC_setup(void) 1261void __cpuinit end_local_APIC_setup(void)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 25423a5b80ed..f47df59016c5 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -5,6 +5,7 @@
5#include <asm/io.h> 5#include <asm/io.h>
6#include <asm/processor.h> 6#include <asm/processor.h>
7#include <asm/apic.h> 7#include <asm/apic.h>
8#include <asm/cpu.h>
8 9
9#ifdef CONFIG_X86_64 10#ifdef CONFIG_X86_64
10# include <asm/numa_64.h> 11# include <asm/numa_64.h>
@@ -141,6 +142,55 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
141 } 142 }
142} 143}
143 144
145static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
146{
147#ifdef CONFIG_SMP
148 /* calling is from identify_secondary_cpu() ? */
149 if (c->cpu_index == boot_cpu_id)
150 return;
151
152 /*
153 * Certain Athlons might work (for various values of 'work') in SMP
154 * but they are not certified as MP capable.
155 */
156 /* Athlon 660/661 is valid. */
157 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
158 (c->x86_mask == 1)))
159 goto valid_k7;
160
161 /* Duron 670 is valid */
162 if ((c->x86_model == 7) && (c->x86_mask == 0))
163 goto valid_k7;
164
165 /*
166 * Athlon 662, Duron 671, and Athlon >model 7 have capability
167 * bit. It's worth noting that the A5 stepping (662) of some
168 * Athlon XP's have the MP bit set.
169 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
170 * more.
171 */
172 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
173 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
174 (c->x86_model > 7))
175 if (cpu_has_mp)
176 goto valid_k7;
177
178 /* If we get here, not a certified SMP capable AMD system. */
179
180 /*
181 * Don't taint if we are running SMP kernel on a single non-MP
182 * approved Athlon
183 */
184 WARN_ONCE(1, "WARNING: This combination of AMD"
185 "processors is not suitable for SMP.\n");
186 if (!test_taint(TAINT_UNSAFE_SMP))
187 add_taint(TAINT_UNSAFE_SMP);
188
189valid_k7:
190 ;
191#endif
192}
193
144static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) 194static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
145{ 195{
146 u32 l, h; 196 u32 l, h;
@@ -175,6 +225,8 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
175 } 225 }
176 226
177 set_cpu_cap(c, X86_FEATURE_K7); 227 set_cpu_cap(c, X86_FEATURE_K7);
228
229 amd_k7_smp_check(c);
178} 230}
179#endif 231#endif
180 232
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index 4b1c319d30c3..22590cf688ae 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -601,7 +601,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
601 if (!data) 601 if (!data)
602 return -ENOMEM; 602 return -ENOMEM;
603 603
604 data->acpi_data = percpu_ptr(acpi_perf_data, cpu); 604 data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu);
605 per_cpu(drv_data, cpu) = data; 605 per_cpu(drv_data, cpu) = data;
606 606
607 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) 607 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC))
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index b585e04cbc9e..3178c3acd97e 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -277,7 +277,6 @@ static struct cpufreq_driver p4clockmod_driver = {
277 .name = "p4-clockmod", 277 .name = "p4-clockmod",
278 .owner = THIS_MODULE, 278 .owner = THIS_MODULE,
279 .attr = p4clockmod_attr, 279 .attr = p4clockmod_attr,
280 .hide_interface = 1,
281}; 280};
282 281
283 282
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 25c559ba8d54..191117f1ad51 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -13,6 +13,7 @@
13#include <asm/uaccess.h> 13#include <asm/uaccess.h>
14#include <asm/ds.h> 14#include <asm/ds.h>
15#include <asm/bugs.h> 15#include <asm/bugs.h>
16#include <asm/cpu.h>
16 17
17#ifdef CONFIG_X86_64 18#ifdef CONFIG_X86_64
18#include <asm/topology.h> 19#include <asm/topology.h>
@@ -110,6 +111,28 @@ static void __cpuinit trap_init_f00f_bug(void)
110} 111}
111#endif 112#endif
112 113
114static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
115{
116#ifdef CONFIG_SMP
117 /* calling is from identify_secondary_cpu() ? */
118 if (c->cpu_index == boot_cpu_id)
119 return;
120
121 /*
122 * Mask B, Pentium, but not Pentium MMX
123 */
124 if (c->x86 == 5 &&
125 c->x86_mask >= 1 && c->x86_mask <= 4 &&
126 c->x86_model <= 3) {
127 /*
128 * Remember we have B step Pentia with bugs
129 */
130 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
131 "with B stepping processors.\n");
132 }
133#endif
134}
135
113static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 136static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
114{ 137{
115 unsigned long lo, hi; 138 unsigned long lo, hi;
@@ -186,6 +209,8 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
186#ifdef CONFIG_X86_NUMAQ 209#ifdef CONFIG_X86_NUMAQ
187 numaq_tsc_disable(); 210 numaq_tsc_disable();
188#endif 211#endif
212
213 intel_smp_check(c);
189} 214}
190#else 215#else
191static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 216static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/mcheck/Makefile b/arch/x86/kernel/cpu/mcheck/Makefile
index d7d2323bbb69..b2f89829bbe8 100644
--- a/arch/x86/kernel/cpu/mcheck/Makefile
+++ b/arch/x86/kernel/cpu/mcheck/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_X86_32) += k7.o p4.o p5.o p6.o winchip.o
4obj-$(CONFIG_X86_MCE_INTEL) += mce_intel_64.o 4obj-$(CONFIG_X86_MCE_INTEL) += mce_intel_64.o
5obj-$(CONFIG_X86_MCE_AMD) += mce_amd_64.o 5obj-$(CONFIG_X86_MCE_AMD) += mce_amd_64.o
6obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o 6obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o
7obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o
diff --git a/arch/x86/kernel/cpu/mcheck/mce_32.c b/arch/x86/kernel/cpu/mcheck/mce_32.c
index dfaebce3633e..3552119b091d 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_32.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_32.c
@@ -60,20 +60,6 @@ void mcheck_init(struct cpuinfo_x86 *c)
60 } 60 }
61} 61}
62 62
63static unsigned long old_cr4 __initdata;
64
65void __init stop_mce(void)
66{
67 old_cr4 = read_cr4();
68 clear_in_cr4(X86_CR4_MCE);
69}
70
71void __init restart_mce(void)
72{
73 if (old_cr4 & X86_CR4_MCE)
74 set_in_cr4(X86_CR4_MCE);
75}
76
77static int __init mcheck_disable(char *str) 63static int __init mcheck_disable(char *str)
78{ 64{
79 mce_disabled = 1; 65 mce_disabled = 1;
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index fe79985ce0f2..ca14604611ec 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -3,6 +3,8 @@
3 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 3 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
4 * Rest from unknown author(s). 4 * Rest from unknown author(s).
5 * 2004 Andi Kleen. Rewrote most of it. 5 * 2004 Andi Kleen. Rewrote most of it.
6 * Copyright 2008 Intel Corporation
7 * Author: Andi Kleen
6 */ 8 */
7 9
8#include <linux/init.h> 10#include <linux/init.h>
@@ -24,6 +26,9 @@
24#include <linux/ctype.h> 26#include <linux/ctype.h>
25#include <linux/kmod.h> 27#include <linux/kmod.h>
26#include <linux/kdebug.h> 28#include <linux/kdebug.h>
29#include <linux/kobject.h>
30#include <linux/sysfs.h>
31#include <linux/ratelimit.h>
27#include <asm/processor.h> 32#include <asm/processor.h>
28#include <asm/msr.h> 33#include <asm/msr.h>
29#include <asm/mce.h> 34#include <asm/mce.h>
@@ -32,7 +37,6 @@
32#include <asm/idle.h> 37#include <asm/idle.h>
33 38
34#define MISC_MCELOG_MINOR 227 39#define MISC_MCELOG_MINOR 227
35#define NR_SYSFS_BANKS 6
36 40
37atomic_t mce_entry; 41atomic_t mce_entry;
38 42
@@ -47,7 +51,7 @@ static int mce_dont_init;
47 */ 51 */
48static int tolerant = 1; 52static int tolerant = 1;
49static int banks; 53static int banks;
50static unsigned long bank[NR_SYSFS_BANKS] = { [0 ... NR_SYSFS_BANKS-1] = ~0UL }; 54static u64 *bank;
51static unsigned long notify_user; 55static unsigned long notify_user;
52static int rip_msr; 56static int rip_msr;
53static int mce_bootlog = -1; 57static int mce_bootlog = -1;
@@ -58,6 +62,19 @@ static char *trigger_argv[2] = { trigger, NULL };
58 62
59static DECLARE_WAIT_QUEUE_HEAD(mce_wait); 63static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
60 64
65/* MCA banks polled by the period polling timer for corrected events */
66DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
67 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
68};
69
70/* Do initial initialization of a struct mce */
71void mce_setup(struct mce *m)
72{
73 memset(m, 0, sizeof(struct mce));
74 m->cpu = smp_processor_id();
75 rdtscll(m->tsc);
76}
77
61/* 78/*
62 * Lockless MCE logging infrastructure. 79 * Lockless MCE logging infrastructure.
63 * This avoids deadlocks on printk locks without having to break locks. Also 80 * This avoids deadlocks on printk locks without having to break locks. Also
@@ -119,11 +136,11 @@ static void print_mce(struct mce *m)
119 print_symbol("{%s}", m->ip); 136 print_symbol("{%s}", m->ip);
120 printk("\n"); 137 printk("\n");
121 } 138 }
122 printk(KERN_EMERG "TSC %Lx ", m->tsc); 139 printk(KERN_EMERG "TSC %llx ", m->tsc);
123 if (m->addr) 140 if (m->addr)
124 printk("ADDR %Lx ", m->addr); 141 printk("ADDR %llx ", m->addr);
125 if (m->misc) 142 if (m->misc)
126 printk("MISC %Lx ", m->misc); 143 printk("MISC %llx ", m->misc);
127 printk("\n"); 144 printk("\n");
128 printk(KERN_EMERG "This is not a software problem!\n"); 145 printk(KERN_EMERG "This is not a software problem!\n");
129 printk(KERN_EMERG "Run through mcelog --ascii to decode " 146 printk(KERN_EMERG "Run through mcelog --ascii to decode "
@@ -149,8 +166,10 @@ static void mce_panic(char *msg, struct mce *backup, unsigned long start)
149 panic(msg); 166 panic(msg);
150} 167}
151 168
152static int mce_available(struct cpuinfo_x86 *c) 169int mce_available(struct cpuinfo_x86 *c)
153{ 170{
171 if (mce_dont_init)
172 return 0;
154 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 173 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
155} 174}
156 175
@@ -172,7 +191,77 @@ static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
172} 191}
173 192
174/* 193/*
175 * The actual machine check handler 194 * Poll for corrected events or events that happened before reset.
195 * Those are just logged through /dev/mcelog.
196 *
197 * This is executed in standard interrupt context.
198 */
199void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
200{
201 struct mce m;
202 int i;
203
204 mce_setup(&m);
205
206 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
207 for (i = 0; i < banks; i++) {
208 if (!bank[i] || !test_bit(i, *b))
209 continue;
210
211 m.misc = 0;
212 m.addr = 0;
213 m.bank = i;
214 m.tsc = 0;
215
216 barrier();
217 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
218 if (!(m.status & MCI_STATUS_VAL))
219 continue;
220
221 /*
222 * Uncorrected events are handled by the exception handler
223 * when it is enabled. But when the exception is disabled log
224 * everything.
225 *
226 * TBD do the same check for MCI_STATUS_EN here?
227 */
228 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
229 continue;
230
231 if (m.status & MCI_STATUS_MISCV)
232 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
233 if (m.status & MCI_STATUS_ADDRV)
234 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
235
236 if (!(flags & MCP_TIMESTAMP))
237 m.tsc = 0;
238 /*
239 * Don't get the IP here because it's unlikely to
240 * have anything to do with the actual error location.
241 */
242
243 mce_log(&m);
244 add_taint(TAINT_MACHINE_CHECK);
245
246 /*
247 * Clear state for this bank.
248 */
249 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
250 }
251
252 /*
253 * Don't clear MCG_STATUS here because it's only defined for
254 * exceptions.
255 */
256}
257
258/*
259 * The actual machine check handler. This only handles real
260 * exceptions when something got corrupted coming in through int 18.
261 *
262 * This is executed in NMI context not subject to normal locking rules. This
263 * implies that most kernel services cannot be safely used. Don't even
264 * think about putting a printk in there!
176 */ 265 */
177void do_machine_check(struct pt_regs * regs, long error_code) 266void do_machine_check(struct pt_regs * regs, long error_code)
178{ 267{
@@ -190,17 +279,18 @@ void do_machine_check(struct pt_regs * regs, long error_code)
190 * error. 279 * error.
191 */ 280 */
192 int kill_it = 0; 281 int kill_it = 0;
282 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
193 283
194 atomic_inc(&mce_entry); 284 atomic_inc(&mce_entry);
195 285
196 if ((regs 286 if (notify_die(DIE_NMI, "machine check", regs, error_code,
197 && notify_die(DIE_NMI, "machine check", regs, error_code,
198 18, SIGKILL) == NOTIFY_STOP) 287 18, SIGKILL) == NOTIFY_STOP)
199 || !banks) 288 goto out2;
289 if (!banks)
200 goto out2; 290 goto out2;
201 291
202 memset(&m, 0, sizeof(struct mce)); 292 mce_setup(&m);
203 m.cpu = smp_processor_id(); 293
204 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); 294 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
205 /* if the restart IP is not valid, we're done for */ 295 /* if the restart IP is not valid, we're done for */
206 if (!(m.mcgstatus & MCG_STATUS_RIPV)) 296 if (!(m.mcgstatus & MCG_STATUS_RIPV))
@@ -210,18 +300,32 @@ void do_machine_check(struct pt_regs * regs, long error_code)
210 barrier(); 300 barrier();
211 301
212 for (i = 0; i < banks; i++) { 302 for (i = 0; i < banks; i++) {
213 if (i < NR_SYSFS_BANKS && !bank[i]) 303 __clear_bit(i, toclear);
304 if (!bank[i])
214 continue; 305 continue;
215 306
216 m.misc = 0; 307 m.misc = 0;
217 m.addr = 0; 308 m.addr = 0;
218 m.bank = i; 309 m.bank = i;
219 m.tsc = 0;
220 310
221 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); 311 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
222 if ((m.status & MCI_STATUS_VAL) == 0) 312 if ((m.status & MCI_STATUS_VAL) == 0)
223 continue; 313 continue;
224 314
315 /*
316 * Non uncorrected errors are handled by machine_check_poll
317 * Leave them alone.
318 */
319 if ((m.status & MCI_STATUS_UC) == 0)
320 continue;
321
322 /*
323 * Set taint even when machine check was not enabled.
324 */
325 add_taint(TAINT_MACHINE_CHECK);
326
327 __set_bit(i, toclear);
328
225 if (m.status & MCI_STATUS_EN) { 329 if (m.status & MCI_STATUS_EN) {
226 /* if PCC was set, there's no way out */ 330 /* if PCC was set, there's no way out */
227 no_way_out |= !!(m.status & MCI_STATUS_PCC); 331 no_way_out |= !!(m.status & MCI_STATUS_PCC);
@@ -235,6 +339,12 @@ void do_machine_check(struct pt_regs * regs, long error_code)
235 no_way_out = 1; 339 no_way_out = 1;
236 kill_it = 1; 340 kill_it = 1;
237 } 341 }
342 } else {
343 /*
344 * Machine check event was not enabled. Clear, but
345 * ignore.
346 */
347 continue;
238 } 348 }
239 349
240 if (m.status & MCI_STATUS_MISCV) 350 if (m.status & MCI_STATUS_MISCV)
@@ -243,10 +353,7 @@ void do_machine_check(struct pt_regs * regs, long error_code)
243 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); 353 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
244 354
245 mce_get_rip(&m, regs); 355 mce_get_rip(&m, regs);
246 if (error_code >= 0) 356 mce_log(&m);
247 rdtscll(m.tsc);
248 if (error_code != -2)
249 mce_log(&m);
250 357
251 /* Did this bank cause the exception? */ 358 /* Did this bank cause the exception? */
252 /* Assume that the bank with uncorrectable errors did it, 359 /* Assume that the bank with uncorrectable errors did it,
@@ -255,14 +362,8 @@ void do_machine_check(struct pt_regs * regs, long error_code)
255 panicm = m; 362 panicm = m;
256 panicm_found = 1; 363 panicm_found = 1;
257 } 364 }
258
259 add_taint(TAINT_MACHINE_CHECK);
260 } 365 }
261 366
262 /* Never do anything final in the polling timer */
263 if (!regs)
264 goto out;
265
266 /* If we didn't find an uncorrectable error, pick 367 /* If we didn't find an uncorrectable error, pick
267 the last one (shouldn't happen, just being safe). */ 368 the last one (shouldn't happen, just being safe). */
268 if (!panicm_found) 369 if (!panicm_found)
@@ -309,10 +410,11 @@ void do_machine_check(struct pt_regs * regs, long error_code)
309 /* notify userspace ASAP */ 410 /* notify userspace ASAP */
310 set_thread_flag(TIF_MCE_NOTIFY); 411 set_thread_flag(TIF_MCE_NOTIFY);
311 412
312 out:
313 /* the last thing we do is clear state */ 413 /* the last thing we do is clear state */
314 for (i = 0; i < banks; i++) 414 for (i = 0; i < banks; i++) {
315 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); 415 if (test_bit(i, toclear))
416 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
417 }
316 wrmsrl(MSR_IA32_MCG_STATUS, 0); 418 wrmsrl(MSR_IA32_MCG_STATUS, 0);
317 out2: 419 out2:
318 atomic_dec(&mce_entry); 420 atomic_dec(&mce_entry);
@@ -332,15 +434,13 @@ void do_machine_check(struct pt_regs * regs, long error_code)
332 * and historically has been the register value of the 434 * and historically has been the register value of the
333 * MSR_IA32_THERMAL_STATUS (Intel) msr. 435 * MSR_IA32_THERMAL_STATUS (Intel) msr.
334 */ 436 */
335void mce_log_therm_throt_event(unsigned int cpu, __u64 status) 437void mce_log_therm_throt_event(__u64 status)
336{ 438{
337 struct mce m; 439 struct mce m;
338 440
339 memset(&m, 0, sizeof(m)); 441 mce_setup(&m);
340 m.cpu = cpu;
341 m.bank = MCE_THERMAL_BANK; 442 m.bank = MCE_THERMAL_BANK;
342 m.status = status; 443 m.status = status;
343 rdtscll(m.tsc);
344 mce_log(&m); 444 mce_log(&m);
345} 445}
346#endif /* CONFIG_X86_MCE_INTEL */ 446#endif /* CONFIG_X86_MCE_INTEL */
@@ -353,18 +453,18 @@ void mce_log_therm_throt_event(unsigned int cpu, __u64 status)
353 453
354static int check_interval = 5 * 60; /* 5 minutes */ 454static int check_interval = 5 * 60; /* 5 minutes */
355static int next_interval; /* in jiffies */ 455static int next_interval; /* in jiffies */
356static void mcheck_timer(struct work_struct *work); 456static void mcheck_timer(unsigned long);
357static DECLARE_DELAYED_WORK(mcheck_work, mcheck_timer); 457static DEFINE_PER_CPU(struct timer_list, mce_timer);
358 458
359static void mcheck_check_cpu(void *info) 459static void mcheck_timer(unsigned long data)
360{ 460{
361 if (mce_available(&current_cpu_data)) 461 struct timer_list *t = &per_cpu(mce_timer, data);
362 do_machine_check(NULL, 0);
363}
364 462
365static void mcheck_timer(struct work_struct *work) 463 WARN_ON(smp_processor_id() != data);
366{ 464
367 on_each_cpu(mcheck_check_cpu, NULL, 1); 465 if (mce_available(&current_cpu_data))
466 machine_check_poll(MCP_TIMESTAMP,
467 &__get_cpu_var(mce_poll_banks));
368 468
369 /* 469 /*
370 * Alert userspace if needed. If we logged an MCE, reduce the 470 * Alert userspace if needed. If we logged an MCE, reduce the
@@ -377,31 +477,41 @@ static void mcheck_timer(struct work_struct *work)
377 (int)round_jiffies_relative(check_interval*HZ)); 477 (int)round_jiffies_relative(check_interval*HZ));
378 } 478 }
379 479
380 schedule_delayed_work(&mcheck_work, next_interval); 480 t->expires = jiffies + next_interval;
481 add_timer(t);
482}
483
484static void mce_do_trigger(struct work_struct *work)
485{
486 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
381} 487}
382 488
489static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
490
383/* 491/*
384 * This is only called from process context. This is where we do 492 * Notify the user(s) about new machine check events.
385 * anything we need to alert userspace about new MCEs. This is called 493 * Can be called from interrupt context, but not from machine check/NMI
386 * directly from the poller and also from entry.S and idle, thanks to 494 * context.
387 * TIF_MCE_NOTIFY.
388 */ 495 */
389int mce_notify_user(void) 496int mce_notify_user(void)
390{ 497{
498 /* Not more than two messages every minute */
499 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
500
391 clear_thread_flag(TIF_MCE_NOTIFY); 501 clear_thread_flag(TIF_MCE_NOTIFY);
392 if (test_and_clear_bit(0, &notify_user)) { 502 if (test_and_clear_bit(0, &notify_user)) {
393 static unsigned long last_print;
394 unsigned long now = jiffies;
395
396 wake_up_interruptible(&mce_wait); 503 wake_up_interruptible(&mce_wait);
397 if (trigger[0])
398 call_usermodehelper(trigger, trigger_argv, NULL,
399 UMH_NO_WAIT);
400 504
401 if (time_after_eq(now, last_print + (check_interval*HZ))) { 505 /*
402 last_print = now; 506 * There is no risk of missing notifications because
507 * work_pending is always cleared before the function is
508 * executed.
509 */
510 if (trigger[0] && !work_pending(&mce_trigger_work))
511 schedule_work(&mce_trigger_work);
512
513 if (__ratelimit(&ratelimit))
403 printk(KERN_INFO "Machine check events logged\n"); 514 printk(KERN_INFO "Machine check events logged\n");
404 }
405 515
406 return 1; 516 return 1;
407 } 517 }
@@ -425,63 +535,78 @@ static struct notifier_block mce_idle_notifier = {
425 535
426static __init int periodic_mcheck_init(void) 536static __init int periodic_mcheck_init(void)
427{ 537{
428 next_interval = check_interval * HZ; 538 idle_notifier_register(&mce_idle_notifier);
429 if (next_interval) 539 return 0;
430 schedule_delayed_work(&mcheck_work,
431 round_jiffies_relative(next_interval));
432 idle_notifier_register(&mce_idle_notifier);
433 return 0;
434} 540}
435__initcall(periodic_mcheck_init); 541__initcall(periodic_mcheck_init);
436 542
437
438/* 543/*
439 * Initialize Machine Checks for a CPU. 544 * Initialize Machine Checks for a CPU.
440 */ 545 */
441static void mce_init(void *dummy) 546static int mce_cap_init(void)
442{ 547{
443 u64 cap; 548 u64 cap;
444 int i; 549 unsigned b;
445 550
446 rdmsrl(MSR_IA32_MCG_CAP, cap); 551 rdmsrl(MSR_IA32_MCG_CAP, cap);
447 banks = cap & 0xff; 552 b = cap & 0xff;
448 if (banks > MCE_EXTENDED_BANK) { 553 if (b > MAX_NR_BANKS) {
449 banks = MCE_EXTENDED_BANK; 554 printk(KERN_WARNING
450 printk(KERN_INFO "MCE: warning: using only %d banks\n", 555 "MCE: Using only %u machine check banks out of %u\n",
451 MCE_EXTENDED_BANK); 556 MAX_NR_BANKS, b);
557 b = MAX_NR_BANKS;
452 } 558 }
559
560 /* Don't support asymmetric configurations today */
561 WARN_ON(banks != 0 && b != banks);
562 banks = b;
563 if (!bank) {
564 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
565 if (!bank)
566 return -ENOMEM;
567 memset(bank, 0xff, banks * sizeof(u64));
568 }
569
453 /* Use accurate RIP reporting if available. */ 570 /* Use accurate RIP reporting if available. */
454 if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) 571 if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9)
455 rip_msr = MSR_IA32_MCG_EIP; 572 rip_msr = MSR_IA32_MCG_EIP;
456 573
457 /* Log the machine checks left over from the previous reset. 574 return 0;
458 This also clears all registers */ 575}
459 do_machine_check(NULL, mce_bootlog ? -1 : -2); 576
577static void mce_init(void *dummy)
578{
579 u64 cap;
580 int i;
581 mce_banks_t all_banks;
582
583 /*
584 * Log the machine checks left over from the previous reset.
585 */
586 bitmap_fill(all_banks, MAX_NR_BANKS);
587 machine_check_poll(MCP_UC, &all_banks);
460 588
461 set_in_cr4(X86_CR4_MCE); 589 set_in_cr4(X86_CR4_MCE);
462 590
591 rdmsrl(MSR_IA32_MCG_CAP, cap);
463 if (cap & MCG_CTL_P) 592 if (cap & MCG_CTL_P)
464 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 593 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
465 594
466 for (i = 0; i < banks; i++) { 595 for (i = 0; i < banks; i++) {
467 if (i < NR_SYSFS_BANKS) 596 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
468 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
469 else
470 wrmsrl(MSR_IA32_MC0_CTL+4*i, ~0UL);
471
472 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); 597 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
473 } 598 }
474} 599}
475 600
476/* Add per CPU specific workarounds here */ 601/* Add per CPU specific workarounds here */
477static void __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c) 602static void mce_cpu_quirks(struct cpuinfo_x86 *c)
478{ 603{
479 /* This should be disabled by the BIOS, but isn't always */ 604 /* This should be disabled by the BIOS, but isn't always */
480 if (c->x86_vendor == X86_VENDOR_AMD) { 605 if (c->x86_vendor == X86_VENDOR_AMD) {
481 if(c->x86 == 15) 606 if (c->x86 == 15 && banks > 4)
482 /* disable GART TBL walk error reporting, which trips off 607 /* disable GART TBL walk error reporting, which trips off
483 incorrectly with the IOMMU & 3ware & Cerberus. */ 608 incorrectly with the IOMMU & 3ware & Cerberus. */
484 clear_bit(10, &bank[4]); 609 clear_bit(10, (unsigned long *)&bank[4]);
485 if(c->x86 <= 17 && mce_bootlog < 0) 610 if(c->x86 <= 17 && mce_bootlog < 0)
486 /* Lots of broken BIOS around that don't clear them 611 /* Lots of broken BIOS around that don't clear them
487 by default and leave crap in there. Don't log. */ 612 by default and leave crap in there. Don't log. */
@@ -504,20 +629,38 @@ static void mce_cpu_features(struct cpuinfo_x86 *c)
504 } 629 }
505} 630}
506 631
632static void mce_init_timer(void)
633{
634 struct timer_list *t = &__get_cpu_var(mce_timer);
635
636 /* data race harmless because everyone sets to the same value */
637 if (!next_interval)
638 next_interval = check_interval * HZ;
639 if (!next_interval)
640 return;
641 setup_timer(t, mcheck_timer, smp_processor_id());
642 t->expires = round_jiffies(jiffies + next_interval);
643 add_timer(t);
644}
645
507/* 646/*
508 * Called for each booted CPU to set up machine checks. 647 * Called for each booted CPU to set up machine checks.
509 * Must be called with preempt off. 648 * Must be called with preempt off.
510 */ 649 */
511void __cpuinit mcheck_init(struct cpuinfo_x86 *c) 650void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
512{ 651{
513 mce_cpu_quirks(c); 652 if (!mce_available(c))
653 return;
514 654
515 if (mce_dont_init || 655 if (mce_cap_init() < 0) {
516 !mce_available(c)) 656 mce_dont_init = 1;
517 return; 657 return;
658 }
659 mce_cpu_quirks(c);
518 660
519 mce_init(NULL); 661 mce_init(NULL);
520 mce_cpu_features(c); 662 mce_cpu_features(c);
663 mce_init_timer();
521} 664}
522 665
523/* 666/*
@@ -573,7 +716,7 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
573{ 716{
574 unsigned long *cpu_tsc; 717 unsigned long *cpu_tsc;
575 static DEFINE_MUTEX(mce_read_mutex); 718 static DEFINE_MUTEX(mce_read_mutex);
576 unsigned next; 719 unsigned prev, next;
577 char __user *buf = ubuf; 720 char __user *buf = ubuf;
578 int i, err; 721 int i, err;
579 722
@@ -592,25 +735,32 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
592 } 735 }
593 736
594 err = 0; 737 err = 0;
595 for (i = 0; i < next; i++) { 738 prev = 0;
596 unsigned long start = jiffies; 739 do {
597 740 for (i = prev; i < next; i++) {
598 while (!mcelog.entry[i].finished) { 741 unsigned long start = jiffies;
599 if (time_after_eq(jiffies, start + 2)) { 742
600 memset(mcelog.entry + i,0, sizeof(struct mce)); 743 while (!mcelog.entry[i].finished) {
601 goto timeout; 744 if (time_after_eq(jiffies, start + 2)) {
745 memset(mcelog.entry + i, 0,
746 sizeof(struct mce));
747 goto timeout;
748 }
749 cpu_relax();
602 } 750 }
603 cpu_relax(); 751 smp_rmb();
752 err |= copy_to_user(buf, mcelog.entry + i,
753 sizeof(struct mce));
754 buf += sizeof(struct mce);
755timeout:
756 ;
604 } 757 }
605 smp_rmb();
606 err |= copy_to_user(buf, mcelog.entry + i, sizeof(struct mce));
607 buf += sizeof(struct mce);
608 timeout:
609 ;
610 }
611 758
612 memset(mcelog.entry, 0, next * sizeof(struct mce)); 759 memset(mcelog.entry + prev, 0,
613 mcelog.next = 0; 760 (next - prev) * sizeof(struct mce));
761 prev = next;
762 next = cmpxchg(&mcelog.next, prev, 0);
763 } while (next != prev);
614 764
615 synchronize_sched(); 765 synchronize_sched();
616 766
@@ -680,20 +830,6 @@ static struct miscdevice mce_log_device = {
680 &mce_chrdev_ops, 830 &mce_chrdev_ops,
681}; 831};
682 832
683static unsigned long old_cr4 __initdata;
684
685void __init stop_mce(void)
686{
687 old_cr4 = read_cr4();
688 clear_in_cr4(X86_CR4_MCE);
689}
690
691void __init restart_mce(void)
692{
693 if (old_cr4 & X86_CR4_MCE)
694 set_in_cr4(X86_CR4_MCE);
695}
696
697/* 833/*
698 * Old style boot options parsing. Only for compatibility. 834 * Old style boot options parsing. Only for compatibility.
699 */ 835 */
@@ -703,8 +839,7 @@ static int __init mcheck_disable(char *str)
703 return 1; 839 return 1;
704} 840}
705 841
706/* mce=off disables machine check. Note you can re-enable it later 842/* mce=off disables machine check.
707 using sysfs.
708 mce=TOLERANCELEVEL (number, see above) 843 mce=TOLERANCELEVEL (number, see above)
709 mce=bootlog Log MCEs from before booting. Disabled by default on AMD. 844 mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
710 mce=nobootlog Don't log MCEs from before booting. */ 845 mce=nobootlog Don't log MCEs from before booting. */
@@ -728,6 +863,29 @@ __setup("mce=", mcheck_enable);
728 * Sysfs support 863 * Sysfs support
729 */ 864 */
730 865
866/*
867 * Disable machine checks on suspend and shutdown. We can't really handle
868 * them later.
869 */
870static int mce_disable(void)
871{
872 int i;
873
874 for (i = 0; i < banks; i++)
875 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
876 return 0;
877}
878
879static int mce_suspend(struct sys_device *dev, pm_message_t state)
880{
881 return mce_disable();
882}
883
884static int mce_shutdown(struct sys_device *dev)
885{
886 return mce_disable();
887}
888
731/* On resume clear all MCE state. Don't want to see leftovers from the BIOS. 889/* On resume clear all MCE state. Don't want to see leftovers from the BIOS.
732 Only one CPU is active at this time, the others get readded later using 890 Only one CPU is active at this time, the others get readded later using
733 CPU hotplug. */ 891 CPU hotplug. */
@@ -738,20 +896,24 @@ static int mce_resume(struct sys_device *dev)
738 return 0; 896 return 0;
739} 897}
740 898
899static void mce_cpu_restart(void *data)
900{
901 del_timer_sync(&__get_cpu_var(mce_timer));
902 if (mce_available(&current_cpu_data))
903 mce_init(NULL);
904 mce_init_timer();
905}
906
741/* Reinit MCEs after user configuration changes */ 907/* Reinit MCEs after user configuration changes */
742static void mce_restart(void) 908static void mce_restart(void)
743{ 909{
744 if (next_interval)
745 cancel_delayed_work(&mcheck_work);
746 /* Timer race is harmless here */
747 on_each_cpu(mce_init, NULL, 1);
748 next_interval = check_interval * HZ; 910 next_interval = check_interval * HZ;
749 if (next_interval) 911 on_each_cpu(mce_cpu_restart, NULL, 1);
750 schedule_delayed_work(&mcheck_work,
751 round_jiffies_relative(next_interval));
752} 912}
753 913
754static struct sysdev_class mce_sysclass = { 914static struct sysdev_class mce_sysclass = {
915 .suspend = mce_suspend,
916 .shutdown = mce_shutdown,
755 .resume = mce_resume, 917 .resume = mce_resume,
756 .name = "machinecheck", 918 .name = "machinecheck",
757}; 919};
@@ -778,16 +940,26 @@ void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu) __cpuinit
778 } \ 940 } \
779 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); 941 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
780 942
781/* 943static struct sysdev_attribute *bank_attrs;
782 * TBD should generate these dynamically based on number of available banks. 944
783 * Have only 6 contol banks in /sysfs until then. 945static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
784 */ 946 char *buf)
785ACCESSOR(bank0ctl,bank[0],mce_restart()) 947{
786ACCESSOR(bank1ctl,bank[1],mce_restart()) 948 u64 b = bank[attr - bank_attrs];
787ACCESSOR(bank2ctl,bank[2],mce_restart()) 949 return sprintf(buf, "%llx\n", b);
788ACCESSOR(bank3ctl,bank[3],mce_restart()) 950}
789ACCESSOR(bank4ctl,bank[4],mce_restart()) 951
790ACCESSOR(bank5ctl,bank[5],mce_restart()) 952static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
953 const char *buf, size_t siz)
954{
955 char *end;
956 u64 new = simple_strtoull(buf, &end, 0);
957 if (end == buf)
958 return -EINVAL;
959 bank[attr - bank_attrs] = new;
960 mce_restart();
961 return end-buf;
962}
791 963
792static ssize_t show_trigger(struct sys_device *s, struct sysdev_attribute *attr, 964static ssize_t show_trigger(struct sys_device *s, struct sysdev_attribute *attr,
793 char *buf) 965 char *buf)
@@ -814,8 +986,6 @@ static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
814static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); 986static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
815ACCESSOR(check_interval,check_interval,mce_restart()) 987ACCESSOR(check_interval,check_interval,mce_restart())
816static struct sysdev_attribute *mce_attributes[] = { 988static struct sysdev_attribute *mce_attributes[] = {
817 &attr_bank0ctl, &attr_bank1ctl, &attr_bank2ctl,
818 &attr_bank3ctl, &attr_bank4ctl, &attr_bank5ctl,
819 &attr_tolerant.attr, &attr_check_interval, &attr_trigger, 989 &attr_tolerant.attr, &attr_check_interval, &attr_trigger,
820 NULL 990 NULL
821}; 991};
@@ -845,11 +1015,22 @@ static __cpuinit int mce_create_device(unsigned int cpu)
845 if (err) 1015 if (err)
846 goto error; 1016 goto error;
847 } 1017 }
1018 for (i = 0; i < banks; i++) {
1019 err = sysdev_create_file(&per_cpu(device_mce, cpu),
1020 &bank_attrs[i]);
1021 if (err)
1022 goto error2;
1023 }
848 cpu_set(cpu, mce_device_initialized); 1024 cpu_set(cpu, mce_device_initialized);
849 1025
850 return 0; 1026 return 0;
1027error2:
1028 while (--i >= 0) {
1029 sysdev_remove_file(&per_cpu(device_mce, cpu),
1030 &bank_attrs[i]);
1031 }
851error: 1032error:
852 while (i--) { 1033 while (--i >= 0) {
853 sysdev_remove_file(&per_cpu(device_mce,cpu), 1034 sysdev_remove_file(&per_cpu(device_mce,cpu),
854 mce_attributes[i]); 1035 mce_attributes[i]);
855 } 1036 }
@@ -868,15 +1049,46 @@ static __cpuinit void mce_remove_device(unsigned int cpu)
868 for (i = 0; mce_attributes[i]; i++) 1049 for (i = 0; mce_attributes[i]; i++)
869 sysdev_remove_file(&per_cpu(device_mce,cpu), 1050 sysdev_remove_file(&per_cpu(device_mce,cpu),
870 mce_attributes[i]); 1051 mce_attributes[i]);
1052 for (i = 0; i < banks; i++)
1053 sysdev_remove_file(&per_cpu(device_mce, cpu),
1054 &bank_attrs[i]);
871 sysdev_unregister(&per_cpu(device_mce,cpu)); 1055 sysdev_unregister(&per_cpu(device_mce,cpu));
872 cpu_clear(cpu, mce_device_initialized); 1056 cpu_clear(cpu, mce_device_initialized);
873} 1057}
874 1058
1059/* Make sure there are no machine checks on offlined CPUs. */
1060static void mce_disable_cpu(void *h)
1061{
1062 int i;
1063 unsigned long action = *(unsigned long *)h;
1064
1065 if (!mce_available(&current_cpu_data))
1066 return;
1067 if (!(action & CPU_TASKS_FROZEN))
1068 cmci_clear();
1069 for (i = 0; i < banks; i++)
1070 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1071}
1072
1073static void mce_reenable_cpu(void *h)
1074{
1075 int i;
1076 unsigned long action = *(unsigned long *)h;
1077
1078 if (!mce_available(&current_cpu_data))
1079 return;
1080 if (!(action & CPU_TASKS_FROZEN))
1081 cmci_reenable();
1082 for (i = 0; i < banks; i++)
1083 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1084}
1085
875/* Get notified when a cpu comes on/off. Be hotplug friendly. */ 1086/* Get notified when a cpu comes on/off. Be hotplug friendly. */
876static int __cpuinit mce_cpu_callback(struct notifier_block *nfb, 1087static int __cpuinit mce_cpu_callback(struct notifier_block *nfb,
877 unsigned long action, void *hcpu) 1088 unsigned long action, void *hcpu)
878{ 1089{
879 unsigned int cpu = (unsigned long)hcpu; 1090 unsigned int cpu = (unsigned long)hcpu;
1091 struct timer_list *t = &per_cpu(mce_timer, cpu);
880 1092
881 switch (action) { 1093 switch (action) {
882 case CPU_ONLINE: 1094 case CPU_ONLINE:
@@ -891,6 +1103,21 @@ static int __cpuinit mce_cpu_callback(struct notifier_block *nfb,
891 threshold_cpu_callback(action, cpu); 1103 threshold_cpu_callback(action, cpu);
892 mce_remove_device(cpu); 1104 mce_remove_device(cpu);
893 break; 1105 break;
1106 case CPU_DOWN_PREPARE:
1107 case CPU_DOWN_PREPARE_FROZEN:
1108 del_timer_sync(t);
1109 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1110 break;
1111 case CPU_DOWN_FAILED:
1112 case CPU_DOWN_FAILED_FROZEN:
1113 t->expires = round_jiffies(jiffies + next_interval);
1114 add_timer_on(t, cpu);
1115 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1116 break;
1117 case CPU_POST_DEAD:
1118 /* intentionally ignoring frozen here */
1119 cmci_rediscover(cpu);
1120 break;
894 } 1121 }
895 return NOTIFY_OK; 1122 return NOTIFY_OK;
896} 1123}
@@ -899,6 +1126,34 @@ static struct notifier_block mce_cpu_notifier __cpuinitdata = {
899 .notifier_call = mce_cpu_callback, 1126 .notifier_call = mce_cpu_callback,
900}; 1127};
901 1128
1129static __init int mce_init_banks(void)
1130{
1131 int i;
1132
1133 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1134 GFP_KERNEL);
1135 if (!bank_attrs)
1136 return -ENOMEM;
1137
1138 for (i = 0; i < banks; i++) {
1139 struct sysdev_attribute *a = &bank_attrs[i];
1140 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1141 if (!a->attr.name)
1142 goto nomem;
1143 a->attr.mode = 0644;
1144 a->show = show_bank;
1145 a->store = set_bank;
1146 }
1147 return 0;
1148
1149nomem:
1150 while (--i >= 0)
1151 kfree(bank_attrs[i].attr.name);
1152 kfree(bank_attrs);
1153 bank_attrs = NULL;
1154 return -ENOMEM;
1155}
1156
902static __init int mce_init_device(void) 1157static __init int mce_init_device(void)
903{ 1158{
904 int err; 1159 int err;
@@ -906,6 +1161,11 @@ static __init int mce_init_device(void)
906 1161
907 if (!mce_available(&boot_cpu_data)) 1162 if (!mce_available(&boot_cpu_data))
908 return -EIO; 1163 return -EIO;
1164
1165 err = mce_init_banks();
1166 if (err)
1167 return err;
1168
909 err = sysdev_class_register(&mce_sysclass); 1169 err = sysdev_class_register(&mce_sysclass);
910 if (err) 1170 if (err)
911 return err; 1171 return err;
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index 9817506dd469..c5a32f92d07e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -79,6 +79,8 @@ static unsigned char shared_bank[NR_BANKS] = {
79 79
80static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ 80static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
81 81
82static void amd_threshold_interrupt(void);
83
82/* 84/*
83 * CPU Initialization 85 * CPU Initialization
84 */ 86 */
@@ -174,6 +176,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
174 tr.reset = 0; 176 tr.reset = 0;
175 tr.old_limit = 0; 177 tr.old_limit = 0;
176 threshold_restart_bank(&tr); 178 threshold_restart_bank(&tr);
179
180 mce_threshold_vector = amd_threshold_interrupt;
177 } 181 }
178 } 182 }
179} 183}
@@ -187,19 +191,13 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
187 * the interrupt goes off when error_count reaches threshold_limit. 191 * the interrupt goes off when error_count reaches threshold_limit.
188 * the handler will simply log mcelog w/ software defined bank number. 192 * the handler will simply log mcelog w/ software defined bank number.
189 */ 193 */
190asmlinkage void mce_threshold_interrupt(void) 194static void amd_threshold_interrupt(void)
191{ 195{
192 unsigned int bank, block; 196 unsigned int bank, block;
193 struct mce m; 197 struct mce m;
194 u32 low = 0, high = 0, address = 0; 198 u32 low = 0, high = 0, address = 0;
195 199
196 ack_APIC_irq(); 200 mce_setup(&m);
197 exit_idle();
198 irq_enter();
199
200 memset(&m, 0, sizeof(m));
201 rdtscll(m.tsc);
202 m.cpu = smp_processor_id();
203 201
204 /* assume first bank caused it */ 202 /* assume first bank caused it */
205 for (bank = 0; bank < NR_BANKS; ++bank) { 203 for (bank = 0; bank < NR_BANKS; ++bank) {
@@ -233,7 +231,8 @@ asmlinkage void mce_threshold_interrupt(void)
233 231
234 /* Log the machine check that caused the threshold 232 /* Log the machine check that caused the threshold
235 event. */ 233 event. */
236 do_machine_check(NULL, 0); 234 machine_check_poll(MCP_TIMESTAMP,
235 &__get_cpu_var(mce_poll_banks));
237 236
238 if (high & MASK_OVERFLOW_HI) { 237 if (high & MASK_OVERFLOW_HI) {
239 rdmsrl(address, m.misc); 238 rdmsrl(address, m.misc);
@@ -243,13 +242,10 @@ asmlinkage void mce_threshold_interrupt(void)
243 + bank * NR_BLOCKS 242 + bank * NR_BLOCKS
244 + block; 243 + block;
245 mce_log(&m); 244 mce_log(&m);
246 goto out; 245 return;
247 } 246 }
248 } 247 }
249 } 248 }
250out:
251 inc_irq_stat(irq_threshold_count);
252 irq_exit();
253} 249}
254 250
255/* 251/*
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index aa5e287c98e0..aaa7d9730938 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Intel specific MCE features. 2 * Intel specific MCE features.
3 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> 3 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
4 * Copyright (C) 2008, 2009 Intel Corporation
5 * Author: Andi Kleen
4 */ 6 */
5 7
6#include <linux/init.h> 8#include <linux/init.h>
@@ -13,6 +15,7 @@
13#include <asm/hw_irq.h> 15#include <asm/hw_irq.h>
14#include <asm/idle.h> 16#include <asm/idle.h>
15#include <asm/therm_throt.h> 17#include <asm/therm_throt.h>
18#include <asm/apic.h>
16 19
17asmlinkage void smp_thermal_interrupt(void) 20asmlinkage void smp_thermal_interrupt(void)
18{ 21{
@@ -25,7 +28,7 @@ asmlinkage void smp_thermal_interrupt(void)
25 28
26 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); 29 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
27 if (therm_throt_process(msr_val & 1)) 30 if (therm_throt_process(msr_val & 1))
28 mce_log_therm_throt_event(smp_processor_id(), msr_val); 31 mce_log_therm_throt_event(msr_val);
29 32
30 inc_irq_stat(irq_thermal_count); 33 inc_irq_stat(irq_thermal_count);
31 irq_exit(); 34 irq_exit();
@@ -85,7 +88,209 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
85 return; 88 return;
86} 89}
87 90
91/*
92 * Support for Intel Correct Machine Check Interrupts. This allows
93 * the CPU to raise an interrupt when a corrected machine check happened.
94 * Normally we pick those up using a regular polling timer.
95 * Also supports reliable discovery of shared banks.
96 */
97
98static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
99
100/*
101 * cmci_discover_lock protects against parallel discovery attempts
102 * which could race against each other.
103 */
104static DEFINE_SPINLOCK(cmci_discover_lock);
105
106#define CMCI_THRESHOLD 1
107
108static int cmci_supported(int *banks)
109{
110 u64 cap;
111
112 /*
113 * Vendor check is not strictly needed, but the initial
114 * initialization is vendor keyed and this
115 * makes sure none of the backdoors are entered otherwise.
116 */
117 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
118 return 0;
119 if (!cpu_has_apic || lapic_get_maxlvt() < 6)
120 return 0;
121 rdmsrl(MSR_IA32_MCG_CAP, cap);
122 *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
123 return !!(cap & MCG_CMCI_P);
124}
125
126/*
127 * The interrupt handler. This is called on every event.
128 * Just call the poller directly to log any events.
129 * This could in theory increase the threshold under high load,
130 * but doesn't for now.
131 */
132static void intel_threshold_interrupt(void)
133{
134 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
135 mce_notify_user();
136}
137
138static void print_update(char *type, int *hdr, int num)
139{
140 if (*hdr == 0)
141 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
142 *hdr = 1;
143 printk(KERN_CONT " %s:%d", type, num);
144}
145
146/*
147 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
148 * on this CPU. Use the algorithm recommended in the SDM to discover shared
149 * banks.
150 */
151static void cmci_discover(int banks, int boot)
152{
153 unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
154 int hdr = 0;
155 int i;
156
157 spin_lock(&cmci_discover_lock);
158 for (i = 0; i < banks; i++) {
159 u64 val;
160
161 if (test_bit(i, owned))
162 continue;
163
164 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
165
166 /* Already owned by someone else? */
167 if (val & CMCI_EN) {
168 if (test_and_clear_bit(i, owned) || boot)
169 print_update("SHD", &hdr, i);
170 __clear_bit(i, __get_cpu_var(mce_poll_banks));
171 continue;
172 }
173
174 val |= CMCI_EN | CMCI_THRESHOLD;
175 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
176 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
177
178 /* Did the enable bit stick? -- the bank supports CMCI */
179 if (val & CMCI_EN) {
180 if (!test_and_set_bit(i, owned) || boot)
181 print_update("CMCI", &hdr, i);
182 __clear_bit(i, __get_cpu_var(mce_poll_banks));
183 } else {
184 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
185 }
186 }
187 spin_unlock(&cmci_discover_lock);
188 if (hdr)
189 printk(KERN_CONT "\n");
190}
191
192/*
193 * Just in case we missed an event during initialization check
194 * all the CMCI owned banks.
195 */
196void cmci_recheck(void)
197{
198 unsigned long flags;
199 int banks;
200
201 if (!mce_available(&current_cpu_data) || !cmci_supported(&banks))
202 return;
203 local_irq_save(flags);
204 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
205 local_irq_restore(flags);
206}
207
208/*
209 * Disable CMCI on this CPU for all banks it owns when it goes down.
210 * This allows other CPUs to claim the banks on rediscovery.
211 */
212void cmci_clear(void)
213{
214 int i;
215 int banks;
216 u64 val;
217
218 if (!cmci_supported(&banks))
219 return;
220 spin_lock(&cmci_discover_lock);
221 for (i = 0; i < banks; i++) {
222 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
223 continue;
224 /* Disable CMCI */
225 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
226 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
227 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
228 __clear_bit(i, __get_cpu_var(mce_banks_owned));
229 }
230 spin_unlock(&cmci_discover_lock);
231}
232
233/*
234 * After a CPU went down cycle through all the others and rediscover
235 * Must run in process context.
236 */
237void cmci_rediscover(int dying)
238{
239 int banks;
240 int cpu;
241 cpumask_var_t old;
242
243 if (!cmci_supported(&banks))
244 return;
245 if (!alloc_cpumask_var(&old, GFP_KERNEL))
246 return;
247 cpumask_copy(old, &current->cpus_allowed);
248
249 for_each_online_cpu (cpu) {
250 if (cpu == dying)
251 continue;
252 if (set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu)))
253 continue;
254 /* Recheck banks in case CPUs don't all have the same */
255 if (cmci_supported(&banks))
256 cmci_discover(banks, 0);
257 }
258
259 set_cpus_allowed_ptr(current, old);
260 free_cpumask_var(old);
261}
262
263/*
264 * Reenable CMCI on this CPU in case a CPU down failed.
265 */
266void cmci_reenable(void)
267{
268 int banks;
269 if (cmci_supported(&banks))
270 cmci_discover(banks, 0);
271}
272
273static __cpuinit void intel_init_cmci(void)
274{
275 int banks;
276
277 if (!cmci_supported(&banks))
278 return;
279
280 mce_threshold_vector = intel_threshold_interrupt;
281 cmci_discover(banks, 1);
282 /*
283 * For CPU #0 this runs with still disabled APIC, but that's
284 * ok because only the vector is set up. We still do another
285 * check for the banks later for CPU #0 just to make sure
286 * to not miss any events.
287 */
288 apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
289 cmci_recheck();
290}
291
88void mce_intel_feature_init(struct cpuinfo_x86 *c) 292void mce_intel_feature_init(struct cpuinfo_x86 *c)
89{ 293{
90 intel_init_thermal(c); 294 intel_init_thermal(c);
295 intel_init_cmci();
91} 296}
diff --git a/arch/x86/kernel/cpu/mcheck/threshold.c b/arch/x86/kernel/cpu/mcheck/threshold.c
new file mode 100644
index 000000000000..23ee9e730f78
--- /dev/null
+++ b/arch/x86/kernel/cpu/mcheck/threshold.c
@@ -0,0 +1,29 @@
1/*
2 * Common corrected MCE threshold handler code:
3 */
4#include <linux/interrupt.h>
5#include <linux/kernel.h>
6
7#include <asm/irq_vectors.h>
8#include <asm/apic.h>
9#include <asm/idle.h>
10#include <asm/mce.h>
11
12static void default_threshold_interrupt(void)
13{
14 printk(KERN_ERR "Unexpected threshold interrupt at vector %x\n",
15 THRESHOLD_APIC_VECTOR);
16}
17
18void (*mce_threshold_vector)(void) = default_threshold_interrupt;
19
20asmlinkage void mce_threshold_interrupt(void)
21{
22 exit_idle();
23 irq_enter();
24 inc_irq_stat(irq_threshold_count);
25 mce_threshold_vector();
26 irq_exit();
27 /* Ack only at the end to avoid potential reentry */
28 ack_APIC_irq();
29}
diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c
index 169a120587be..87b67e3a765a 100644
--- a/arch/x86/kernel/ds.c
+++ b/arch/x86/kernel/ds.c
@@ -729,7 +729,7 @@ struct pebs_tracer *ds_request_pebs(struct task_struct *task,
729 729
730 spin_unlock_irqrestore(&ds_lock, irq); 730 spin_unlock_irqrestore(&ds_lock, irq);
731 731
732 ds_write_config(tracer->ds.context, &tracer->trace.ds, ds_bts); 732 ds_write_config(tracer->ds.context, &tracer->trace.ds, ds_pebs);
733 ds_resume_pebs(tracer); 733 ds_resume_pebs(tracer);
734 734
735 return tracer; 735 return tracer;
@@ -1029,5 +1029,4 @@ void ds_copy_thread(struct task_struct *tsk, struct task_struct *father)
1029 1029
1030void ds_exit_thread(struct task_struct *tsk) 1030void ds_exit_thread(struct task_struct *tsk)
1031{ 1031{
1032 WARN_ON(tsk->thread.ds_ctx);
1033} 1032}
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c
index b205272ad394..1736acc4d7aa 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/kernel/efi.c
@@ -469,7 +469,7 @@ void __init efi_enter_virtual_mode(void)
469 efi_memory_desc_t *md; 469 efi_memory_desc_t *md;
470 efi_status_t status; 470 efi_status_t status;
471 unsigned long size; 471 unsigned long size;
472 u64 end, systab, addr, npages; 472 u64 end, systab, addr, npages, end_pfn;
473 void *p, *va; 473 void *p, *va;
474 474
475 efi.systab = NULL; 475 efi.systab = NULL;
@@ -481,7 +481,10 @@ void __init efi_enter_virtual_mode(void)
481 size = md->num_pages << EFI_PAGE_SHIFT; 481 size = md->num_pages << EFI_PAGE_SHIFT;
482 end = md->phys_addr + size; 482 end = md->phys_addr + size;
483 483
484 if (PFN_UP(end) <= max_low_pfn_mapped) 484 end_pfn = PFN_UP(end);
485 if (end_pfn <= max_low_pfn_mapped
486 || (end_pfn > (1UL << (32 - PAGE_SHIFT))
487 && end_pfn <= max_pfn_mapped))
485 va = __va(md->phys_addr); 488 va = __va(md->phys_addr);
486 else 489 else
487 va = efi_ioremap(md->phys_addr, size); 490 va = efi_ioremap(md->phys_addr, size);
diff --git a/arch/x86/kernel/efi_64.c b/arch/x86/kernel/efi_64.c
index a4ee29127fdf..22c3b7828c50 100644
--- a/arch/x86/kernel/efi_64.c
+++ b/arch/x86/kernel/efi_64.c
@@ -100,24 +100,11 @@ void __init efi_call_phys_epilog(void)
100 100
101void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size) 101void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size)
102{ 102{
103 static unsigned pages_mapped __initdata; 103 unsigned long last_map_pfn;
104 unsigned i, pages;
105 unsigned long offset;
106 104
107 pages = PFN_UP(phys_addr + size) - PFN_DOWN(phys_addr); 105 last_map_pfn = init_memory_mapping(phys_addr, phys_addr + size);
108 offset = phys_addr & ~PAGE_MASK; 106 if ((last_map_pfn << PAGE_SHIFT) < phys_addr + size)
109 phys_addr &= PAGE_MASK;
110
111 if (pages_mapped + pages > MAX_EFI_IO_PAGES)
112 return NULL; 107 return NULL;
113 108
114 for (i = 0; i < pages; i++) { 109 return (void __iomem *)__va(phys_addr);
115 __set_fixmap(FIX_EFI_IO_MAP_FIRST_PAGE - pages_mapped,
116 phys_addr, PAGE_KERNEL);
117 phys_addr += PAGE_SIZE;
118 pages_mapped++;
119 }
120
121 return (void __iomem *)__fix_to_virt(FIX_EFI_IO_MAP_FIRST_PAGE - \
122 (pages_mapped - pages)) + offset;
123} 110}
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 83d1836b9467..7ba4621c0dfa 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -984,6 +984,8 @@ apicinterrupt UV_BAU_MESSAGE \
984#endif 984#endif
985apicinterrupt LOCAL_TIMER_VECTOR \ 985apicinterrupt LOCAL_TIMER_VECTOR \
986 apic_timer_interrupt smp_apic_timer_interrupt 986 apic_timer_interrupt smp_apic_timer_interrupt
987apicinterrupt GENERIC_INTERRUPT_VECTOR \
988 generic_interrupt smp_generic_interrupt
987 989
988#ifdef CONFIG_SMP 990#ifdef CONFIG_SMP
989apicinterrupt INVALIDATE_TLB_VECTOR_START+0 \ 991apicinterrupt INVALIDATE_TLB_VECTOR_START+0 \
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index b0f61f0dcd0a..f2f8540a7f3d 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -136,7 +136,7 @@ int init_fpu(struct task_struct *tsk)
136#ifdef CONFIG_X86_32 136#ifdef CONFIG_X86_32
137 if (!HAVE_HWFP) { 137 if (!HAVE_HWFP) {
138 memset(tsk->thread.xstate, 0, xstate_size); 138 memset(tsk->thread.xstate, 0, xstate_size);
139 finit(); 139 finit_task(tsk);
140 set_stopped_child_used_math(tsk); 140 set_stopped_child_used_math(tsk);
141 return 0; 141 return 0;
142 } 142 }
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index f13ca1650aaf..b864341dcc45 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -15,6 +15,9 @@
15 15
16atomic_t irq_err_count; 16atomic_t irq_err_count;
17 17
18/* Function pointer for generic interrupt vector handling */
19void (*generic_interrupt_extension)(void) = NULL;
20
18/* 21/*
19 * 'what should we do if we get a hw irq event on an illegal vector'. 22 * 'what should we do if we get a hw irq event on an illegal vector'.
20 * each architecture has to answer this themselves. 23 * each architecture has to answer this themselves.
@@ -56,6 +59,12 @@ static int show_other_interrupts(struct seq_file *p)
56 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); 59 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
57 seq_printf(p, " Local timer interrupts\n"); 60 seq_printf(p, " Local timer interrupts\n");
58#endif 61#endif
62 if (generic_interrupt_extension) {
63 seq_printf(p, "PLT: ");
64 for_each_online_cpu(j)
65 seq_printf(p, "%10u ", irq_stats(j)->generic_irqs);
66 seq_printf(p, " Platform interrupts\n");
67 }
59#ifdef CONFIG_SMP 68#ifdef CONFIG_SMP
60 seq_printf(p, "RES: "); 69 seq_printf(p, "RES: ");
61 for_each_online_cpu(j) 70 for_each_online_cpu(j)
@@ -163,6 +172,8 @@ u64 arch_irq_stat_cpu(unsigned int cpu)
163#ifdef CONFIG_X86_LOCAL_APIC 172#ifdef CONFIG_X86_LOCAL_APIC
164 sum += irq_stats(cpu)->apic_timer_irqs; 173 sum += irq_stats(cpu)->apic_timer_irqs;
165#endif 174#endif
175 if (generic_interrupt_extension)
176 sum += irq_stats(cpu)->generic_irqs;
166#ifdef CONFIG_SMP 177#ifdef CONFIG_SMP
167 sum += irq_stats(cpu)->irq_resched_count; 178 sum += irq_stats(cpu)->irq_resched_count;
168 sum += irq_stats(cpu)->irq_call_count; 179 sum += irq_stats(cpu)->irq_call_count;
@@ -226,4 +237,27 @@ unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
226 return 1; 237 return 1;
227} 238}
228 239
240/*
241 * Handler for GENERIC_INTERRUPT_VECTOR.
242 */
243void smp_generic_interrupt(struct pt_regs *regs)
244{
245 struct pt_regs *old_regs = set_irq_regs(regs);
246
247 ack_APIC_irq();
248
249 exit_idle();
250
251 irq_enter();
252
253 inc_irq_stat(generic_irqs);
254
255 if (generic_interrupt_extension)
256 generic_interrupt_extension();
257
258 irq_exit();
259
260 set_irq_regs(old_regs);
261}
262
229EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); 263EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 9dc6b2b24275..3b09634a5153 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -16,6 +16,7 @@
16#include <linux/cpu.h> 16#include <linux/cpu.h>
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/uaccess.h> 18#include <linux/uaccess.h>
19#include <linux/percpu.h>
19 20
20#include <asm/apic.h> 21#include <asm/apic.h>
21 22
@@ -55,13 +56,13 @@ static inline void print_stack_overflow(void) { }
55union irq_ctx { 56union irq_ctx {
56 struct thread_info tinfo; 57 struct thread_info tinfo;
57 u32 stack[THREAD_SIZE/sizeof(u32)]; 58 u32 stack[THREAD_SIZE/sizeof(u32)];
58}; 59} __attribute__((aligned(PAGE_SIZE)));
59 60
60static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly; 61static DEFINE_PER_CPU(union irq_ctx *, hardirq_ctx);
61static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly; 62static DEFINE_PER_CPU(union irq_ctx *, softirq_ctx);
62 63
63static char softirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss; 64static DEFINE_PER_CPU_PAGE_ALIGNED(union irq_ctx, hardirq_stack);
64static char hardirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss; 65static DEFINE_PER_CPU_PAGE_ALIGNED(union irq_ctx, softirq_stack);
65 66
66static void call_on_stack(void *func, void *stack) 67static void call_on_stack(void *func, void *stack)
67{ 68{
@@ -81,7 +82,7 @@ execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
81 u32 *isp, arg1, arg2; 82 u32 *isp, arg1, arg2;
82 83
83 curctx = (union irq_ctx *) current_thread_info(); 84 curctx = (union irq_ctx *) current_thread_info();
84 irqctx = hardirq_ctx[smp_processor_id()]; 85 irqctx = __get_cpu_var(hardirq_ctx);
85 86
86 /* 87 /*
87 * this is where we switch to the IRQ stack. However, if we are 88 * this is where we switch to the IRQ stack. However, if we are
@@ -125,34 +126,34 @@ void __cpuinit irq_ctx_init(int cpu)
125{ 126{
126 union irq_ctx *irqctx; 127 union irq_ctx *irqctx;
127 128
128 if (hardirq_ctx[cpu]) 129 if (per_cpu(hardirq_ctx, cpu))
129 return; 130 return;
130 131
131 irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE]; 132 irqctx = &per_cpu(hardirq_stack, cpu);
132 irqctx->tinfo.task = NULL; 133 irqctx->tinfo.task = NULL;
133 irqctx->tinfo.exec_domain = NULL; 134 irqctx->tinfo.exec_domain = NULL;
134 irqctx->tinfo.cpu = cpu; 135 irqctx->tinfo.cpu = cpu;
135 irqctx->tinfo.preempt_count = HARDIRQ_OFFSET; 136 irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
136 irqctx->tinfo.addr_limit = MAKE_MM_SEG(0); 137 irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
137 138
138 hardirq_ctx[cpu] = irqctx; 139 per_cpu(hardirq_ctx, cpu) = irqctx;
139 140
140 irqctx = (union irq_ctx *) &softirq_stack[cpu*THREAD_SIZE]; 141 irqctx = &per_cpu(softirq_stack, cpu);
141 irqctx->tinfo.task = NULL; 142 irqctx->tinfo.task = NULL;
142 irqctx->tinfo.exec_domain = NULL; 143 irqctx->tinfo.exec_domain = NULL;
143 irqctx->tinfo.cpu = cpu; 144 irqctx->tinfo.cpu = cpu;
144 irqctx->tinfo.preempt_count = 0; 145 irqctx->tinfo.preempt_count = 0;
145 irqctx->tinfo.addr_limit = MAKE_MM_SEG(0); 146 irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
146 147
147 softirq_ctx[cpu] = irqctx; 148 per_cpu(softirq_ctx, cpu) = irqctx;
148 149
149 printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n", 150 printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n",
150 cpu, hardirq_ctx[cpu], softirq_ctx[cpu]); 151 cpu, per_cpu(hardirq_ctx, cpu), per_cpu(softirq_ctx, cpu));
151} 152}
152 153
153void irq_ctx_exit(int cpu) 154void irq_ctx_exit(int cpu)
154{ 155{
155 hardirq_ctx[cpu] = NULL; 156 per_cpu(hardirq_ctx, cpu) = NULL;
156} 157}
157 158
158asmlinkage void do_softirq(void) 159asmlinkage void do_softirq(void)
@@ -169,7 +170,7 @@ asmlinkage void do_softirq(void)
169 170
170 if (local_softirq_pending()) { 171 if (local_softirq_pending()) {
171 curctx = current_thread_info(); 172 curctx = current_thread_info();
172 irqctx = softirq_ctx[smp_processor_id()]; 173 irqctx = __get_cpu_var(softirq_ctx);
173 irqctx->tinfo.task = curctx->task; 174 irqctx->tinfo.task = curctx->task;
174 irqctx->tinfo.previous_esp = current_stack_pointer; 175 irqctx->tinfo.previous_esp = current_stack_pointer;
175 176
diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c
index 50b8c3a3006c..bc1326105448 100644
--- a/arch/x86/kernel/irqinit_32.c
+++ b/arch/x86/kernel/irqinit_32.c
@@ -175,6 +175,9 @@ void __init native_init_IRQ(void)
175 /* self generated IPI for local APIC timer */ 175 /* self generated IPI for local APIC timer */
176 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); 176 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
177 177
178 /* generic IPI for platform specific use */
179 alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
180
178 /* IPI vectors for APIC spurious and error interrupts */ 181 /* IPI vectors for APIC spurious and error interrupts */
179 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); 182 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
180 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); 183 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
diff --git a/arch/x86/kernel/irqinit_64.c b/arch/x86/kernel/irqinit_64.c
index da481a1e3f30..c7a49e0ffbfb 100644
--- a/arch/x86/kernel/irqinit_64.c
+++ b/arch/x86/kernel/irqinit_64.c
@@ -147,6 +147,9 @@ static void __init apic_intr_init(void)
147 /* self generated IPI for local APIC timer */ 147 /* self generated IPI for local APIC timer */
148 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); 148 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
149 149
150 /* generic IPI for platform specific use */
151 alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
152
150 /* IPI vectors for APIC spurious and error interrupts */ 153 /* IPI vectors for APIC spurious and error interrupts */
151 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); 154 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
152 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); 155 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
diff --git a/arch/x86/kernel/machine_kexec_32.c b/arch/x86/kernel/machine_kexec_32.c
index f5fc8c781a62..e7368c1da01d 100644
--- a/arch/x86/kernel/machine_kexec_32.c
+++ b/arch/x86/kernel/machine_kexec_32.c
@@ -14,12 +14,12 @@
14#include <linux/ftrace.h> 14#include <linux/ftrace.h>
15#include <linux/suspend.h> 15#include <linux/suspend.h>
16#include <linux/gfp.h> 16#include <linux/gfp.h>
17#include <linux/io.h>
17 18
18#include <asm/pgtable.h> 19#include <asm/pgtable.h>
19#include <asm/pgalloc.h> 20#include <asm/pgalloc.h>
20#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
21#include <asm/mmu_context.h> 22#include <asm/mmu_context.h>
22#include <asm/io.h>
23#include <asm/apic.h> 23#include <asm/apic.h>
24#include <asm/cpufeature.h> 24#include <asm/cpufeature.h>
25#include <asm/desc.h> 25#include <asm/desc.h>
@@ -63,7 +63,7 @@ static void load_segments(void)
63 "\tmovl %%eax,%%fs\n" 63 "\tmovl %%eax,%%fs\n"
64 "\tmovl %%eax,%%gs\n" 64 "\tmovl %%eax,%%gs\n"
65 "\tmovl %%eax,%%ss\n" 65 "\tmovl %%eax,%%ss\n"
66 ::: "eax", "memory"); 66 : : : "eax", "memory");
67#undef STR 67#undef STR
68#undef __STR 68#undef __STR
69} 69}
@@ -205,7 +205,8 @@ void machine_kexec(struct kimage *image)
205 205
206 if (image->preserve_context) { 206 if (image->preserve_context) {
207#ifdef CONFIG_X86_IO_APIC 207#ifdef CONFIG_X86_IO_APIC
208 /* We need to put APICs in legacy mode so that we can 208 /*
209 * We need to put APICs in legacy mode so that we can
209 * get timer interrupts in second kernel. kexec/kdump 210 * get timer interrupts in second kernel. kexec/kdump
210 * paths already have calls to disable_IO_APIC() in 211 * paths already have calls to disable_IO_APIC() in
211 * one form or other. kexec jump path also need 212 * one form or other. kexec jump path also need
@@ -227,7 +228,8 @@ void machine_kexec(struct kimage *image)
227 page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) 228 page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page)
228 << PAGE_SHIFT); 229 << PAGE_SHIFT);
229 230
230 /* The segment registers are funny things, they have both a 231 /*
232 * The segment registers are funny things, they have both a
231 * visible and an invisible part. Whenever the visible part is 233 * visible and an invisible part. Whenever the visible part is
232 * set to a specific selector, the invisible part is loaded 234 * set to a specific selector, the invisible part is loaded
233 * with from a table in memory. At no other time is the 235 * with from a table in memory. At no other time is the
@@ -237,11 +239,12 @@ void machine_kexec(struct kimage *image)
237 * segments, before I zap the gdt with an invalid value. 239 * segments, before I zap the gdt with an invalid value.
238 */ 240 */
239 load_segments(); 241 load_segments();
240 /* The gdt & idt are now invalid. 242 /*
243 * The gdt & idt are now invalid.
241 * If you want to load them you must set up your own idt & gdt. 244 * If you want to load them you must set up your own idt & gdt.
242 */ 245 */
243 set_gdt(phys_to_virt(0),0); 246 set_gdt(phys_to_virt(0), 0);
244 set_idt(phys_to_virt(0),0); 247 set_idt(phys_to_virt(0), 0);
245 248
246 /* now call it */ 249 /* now call it */
247 image->start = relocate_kernel_ptr((unsigned long)image->head, 250 image->start = relocate_kernel_ptr((unsigned long)image->head,
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index 6993d51b7fd8..89cea4d44679 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -12,11 +12,47 @@
12#include <linux/reboot.h> 12#include <linux/reboot.h>
13#include <linux/numa.h> 13#include <linux/numa.h>
14#include <linux/ftrace.h> 14#include <linux/ftrace.h>
15#include <linux/io.h>
16#include <linux/suspend.h>
15 17
16#include <asm/pgtable.h> 18#include <asm/pgtable.h>
17#include <asm/tlbflush.h> 19#include <asm/tlbflush.h>
18#include <asm/mmu_context.h> 20#include <asm/mmu_context.h>
19#include <asm/io.h> 21
22static int init_one_level2_page(struct kimage *image, pgd_t *pgd,
23 unsigned long addr)
24{
25 pud_t *pud;
26 pmd_t *pmd;
27 struct page *page;
28 int result = -ENOMEM;
29
30 addr &= PMD_MASK;
31 pgd += pgd_index(addr);
32 if (!pgd_present(*pgd)) {
33 page = kimage_alloc_control_pages(image, 0);
34 if (!page)
35 goto out;
36 pud = (pud_t *)page_address(page);
37 memset(pud, 0, PAGE_SIZE);
38 set_pgd(pgd, __pgd(__pa(pud) | _KERNPG_TABLE));
39 }
40 pud = pud_offset(pgd, addr);
41 if (!pud_present(*pud)) {
42 page = kimage_alloc_control_pages(image, 0);
43 if (!page)
44 goto out;
45 pmd = (pmd_t *)page_address(page);
46 memset(pmd, 0, PAGE_SIZE);
47 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
48 }
49 pmd = pmd_offset(pud, addr);
50 if (!pmd_present(*pmd))
51 set_pmd(pmd, __pmd(addr | __PAGE_KERNEL_LARGE_EXEC));
52 result = 0;
53out:
54 return result;
55}
20 56
21static void init_level2_page(pmd_t *level2p, unsigned long addr) 57static void init_level2_page(pmd_t *level2p, unsigned long addr)
22{ 58{
@@ -83,9 +119,8 @@ static int init_level4_page(struct kimage *image, pgd_t *level4p,
83 } 119 }
84 level3p = (pud_t *)page_address(page); 120 level3p = (pud_t *)page_address(page);
85 result = init_level3_page(image, level3p, addr, last_addr); 121 result = init_level3_page(image, level3p, addr, last_addr);
86 if (result) { 122 if (result)
87 goto out; 123 goto out;
88 }
89 set_pgd(level4p++, __pgd(__pa(level3p) | _KERNPG_TABLE)); 124 set_pgd(level4p++, __pgd(__pa(level3p) | _KERNPG_TABLE));
90 addr += PGDIR_SIZE; 125 addr += PGDIR_SIZE;
91 } 126 }
@@ -156,6 +191,13 @@ static int init_pgtable(struct kimage *image, unsigned long start_pgtable)
156 result = init_level4_page(image, level4p, 0, max_pfn << PAGE_SHIFT); 191 result = init_level4_page(image, level4p, 0, max_pfn << PAGE_SHIFT);
157 if (result) 192 if (result)
158 return result; 193 return result;
194 /*
195 * image->start may be outside 0 ~ max_pfn, for example when
196 * jump back to original kernel from kexeced kernel
197 */
198 result = init_one_level2_page(image, level4p, image->start);
199 if (result)
200 return result;
159 return init_transition_pgtable(image, level4p); 201 return init_transition_pgtable(image, level4p);
160} 202}
161 203
@@ -229,20 +271,45 @@ void machine_kexec(struct kimage *image)
229{ 271{
230 unsigned long page_list[PAGES_NR]; 272 unsigned long page_list[PAGES_NR];
231 void *control_page; 273 void *control_page;
274 int save_ftrace_enabled;
232 275
233 tracer_disable(); 276#ifdef CONFIG_KEXEC_JUMP
277 if (kexec_image->preserve_context)
278 save_processor_state();
279#endif
280
281 save_ftrace_enabled = __ftrace_enabled_save();
234 282
235 /* Interrupts aren't acceptable while we reboot */ 283 /* Interrupts aren't acceptable while we reboot */
236 local_irq_disable(); 284 local_irq_disable();
237 285
286 if (image->preserve_context) {
287#ifdef CONFIG_X86_IO_APIC
288 /*
289 * We need to put APICs in legacy mode so that we can
290 * get timer interrupts in second kernel. kexec/kdump
291 * paths already have calls to disable_IO_APIC() in
292 * one form or other. kexec jump path also need
293 * one.
294 */
295 disable_IO_APIC();
296#endif
297 }
298
238 control_page = page_address(image->control_code_page) + PAGE_SIZE; 299 control_page = page_address(image->control_code_page) + PAGE_SIZE;
239 memcpy(control_page, relocate_kernel, PAGE_SIZE); 300 memcpy(control_page, relocate_kernel, KEXEC_CONTROL_CODE_MAX_SIZE);
240 301
241 page_list[PA_CONTROL_PAGE] = virt_to_phys(control_page); 302 page_list[PA_CONTROL_PAGE] = virt_to_phys(control_page);
303 page_list[VA_CONTROL_PAGE] = (unsigned long)control_page;
242 page_list[PA_TABLE_PAGE] = 304 page_list[PA_TABLE_PAGE] =
243 (unsigned long)__pa(page_address(image->control_code_page)); 305 (unsigned long)__pa(page_address(image->control_code_page));
244 306
245 /* The segment registers are funny things, they have both a 307 if (image->type == KEXEC_TYPE_DEFAULT)
308 page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page)
309 << PAGE_SHIFT);
310
311 /*
312 * The segment registers are funny things, they have both a
246 * visible and an invisible part. Whenever the visible part is 313 * visible and an invisible part. Whenever the visible part is
247 * set to a specific selector, the invisible part is loaded 314 * set to a specific selector, the invisible part is loaded
248 * with from a table in memory. At no other time is the 315 * with from a table in memory. At no other time is the
@@ -252,15 +319,25 @@ void machine_kexec(struct kimage *image)
252 * segments, before I zap the gdt with an invalid value. 319 * segments, before I zap the gdt with an invalid value.
253 */ 320 */
254 load_segments(); 321 load_segments();
255 /* The gdt & idt are now invalid. 322 /*
323 * The gdt & idt are now invalid.
256 * If you want to load them you must set up your own idt & gdt. 324 * If you want to load them you must set up your own idt & gdt.
257 */ 325 */
258 set_gdt(phys_to_virt(0),0); 326 set_gdt(phys_to_virt(0), 0);
259 set_idt(phys_to_virt(0),0); 327 set_idt(phys_to_virt(0), 0);
260 328
261 /* now call it */ 329 /* now call it */
262 relocate_kernel((unsigned long)image->head, (unsigned long)page_list, 330 image->start = relocate_kernel((unsigned long)image->head,
263 image->start); 331 (unsigned long)page_list,
332 image->start,
333 image->preserve_context);
334
335#ifdef CONFIG_KEXEC_JUMP
336 if (kexec_image->preserve_context)
337 restore_processor_state();
338#endif
339
340 __ftrace_enabled_restore(save_ftrace_enabled);
264} 341}
265 342
266void arch_crash_save_vmcoreinfo(void) 343void arch_crash_save_vmcoreinfo(void)
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 37cb1bda1baf..e8192401da47 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -558,6 +558,19 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
558 558
559static struct mpf_intel *mpf_found; 559static struct mpf_intel *mpf_found;
560 560
561static unsigned long __init get_mpc_size(unsigned long physptr)
562{
563 struct mpc_table *mpc;
564 unsigned long size;
565
566 mpc = early_ioremap(physptr, PAGE_SIZE);
567 size = mpc->length;
568 early_iounmap(mpc, PAGE_SIZE);
569 apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size);
570
571 return size;
572}
573
561/* 574/*
562 * Scan the memory blocks for an SMP configuration block. 575 * Scan the memory blocks for an SMP configuration block.
563 */ 576 */
@@ -611,12 +624,16 @@ static void __init __get_smp_config(unsigned int early)
611 construct_default_ISA_mptable(mpf->feature1); 624 construct_default_ISA_mptable(mpf->feature1);
612 625
613 } else if (mpf->physptr) { 626 } else if (mpf->physptr) {
627 struct mpc_table *mpc;
628 unsigned long size;
614 629
630 size = get_mpc_size(mpf->physptr);
631 mpc = early_ioremap(mpf->physptr, size);
615 /* 632 /*
616 * Read the physical hardware table. Anything here will 633 * Read the physical hardware table. Anything here will
617 * override the defaults. 634 * override the defaults.
618 */ 635 */
619 if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { 636 if (!smp_read_mpc(mpc, early)) {
620#ifdef CONFIG_X86_LOCAL_APIC 637#ifdef CONFIG_X86_LOCAL_APIC
621 smp_found_config = 0; 638 smp_found_config = 0;
622#endif 639#endif
@@ -624,8 +641,10 @@ static void __init __get_smp_config(unsigned int early)
624 "BIOS bug, MP table errors detected!...\n"); 641 "BIOS bug, MP table errors detected!...\n");
625 printk(KERN_ERR "... disabling SMP support. " 642 printk(KERN_ERR "... disabling SMP support. "
626 "(tell your hw vendor)\n"); 643 "(tell your hw vendor)\n");
644 early_iounmap(mpc, size);
627 return; 645 return;
628 } 646 }
647 early_iounmap(mpc, size);
629 648
630 if (early) 649 if (early)
631 return; 650 return;
@@ -697,10 +716,10 @@ static int __init smp_scan_config(unsigned long base, unsigned long length,
697 716
698 if (!reserve) 717 if (!reserve)
699 return 1; 718 return 1;
700 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE, 719 reserve_bootmem_generic(virt_to_phys(mpf), sizeof(*mpf),
701 BOOTMEM_DEFAULT); 720 BOOTMEM_DEFAULT);
702 if (mpf->physptr) { 721 if (mpf->physptr) {
703 unsigned long size = PAGE_SIZE; 722 unsigned long size = get_mpc_size(mpf->physptr);
704#ifdef CONFIG_X86_32 723#ifdef CONFIG_X86_32
705 /* 724 /*
706 * We cannot access to MPC table to compute 725 * We cannot access to MPC table to compute
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 1cc18d439bbb..2aef36d8aca2 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -216,6 +216,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
216 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"), 216 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"),
217 }, 217 },
218 }, 218 },
219 { /* Handle problems with rebooting on Dell XPS710 */
220 .callback = set_bios_reboot,
221 .ident = "Dell XPS710",
222 .matches = {
223 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
224 DMI_MATCH(DMI_PRODUCT_NAME, "Dell XPS710"),
225 },
226 },
219 { } 227 { }
220}; 228};
221 229
diff --git a/arch/x86/kernel/relocate_kernel_32.S b/arch/x86/kernel/relocate_kernel_32.S
index 2064d0aa8d28..41235531b11c 100644
--- a/arch/x86/kernel/relocate_kernel_32.S
+++ b/arch/x86/kernel/relocate_kernel_32.S
@@ -17,7 +17,8 @@
17 17
18#define PTR(x) (x << 2) 18#define PTR(x) (x << 2)
19 19
20/* control_page + KEXEC_CONTROL_CODE_MAX_SIZE 20/*
21 * control_page + KEXEC_CONTROL_CODE_MAX_SIZE
21 * ~ control_page + PAGE_SIZE are used as data storage and stack for 22 * ~ control_page + PAGE_SIZE are used as data storage and stack for
22 * jumping back 23 * jumping back
23 */ 24 */
@@ -76,8 +77,10 @@ relocate_kernel:
76 movl %eax, CP_PA_SWAP_PAGE(%edi) 77 movl %eax, CP_PA_SWAP_PAGE(%edi)
77 movl %ebx, CP_PA_BACKUP_PAGES_MAP(%edi) 78 movl %ebx, CP_PA_BACKUP_PAGES_MAP(%edi)
78 79
79 /* get physical address of control page now */ 80 /*
80 /* this is impossible after page table switch */ 81 * get physical address of control page now
82 * this is impossible after page table switch
83 */
81 movl PTR(PA_CONTROL_PAGE)(%ebp), %edi 84 movl PTR(PA_CONTROL_PAGE)(%ebp), %edi
82 85
83 /* switch to new set of page tables */ 86 /* switch to new set of page tables */
@@ -97,7 +100,8 @@ identity_mapped:
97 /* store the start address on the stack */ 100 /* store the start address on the stack */
98 pushl %edx 101 pushl %edx
99 102
100 /* Set cr0 to a known state: 103 /*
104 * Set cr0 to a known state:
101 * - Paging disabled 105 * - Paging disabled
102 * - Alignment check disabled 106 * - Alignment check disabled
103 * - Write protect disabled 107 * - Write protect disabled
@@ -113,7 +117,8 @@ identity_mapped:
113 /* clear cr4 if applicable */ 117 /* clear cr4 if applicable */
114 testl %ecx, %ecx 118 testl %ecx, %ecx
115 jz 1f 119 jz 1f
116 /* Set cr4 to a known state: 120 /*
121 * Set cr4 to a known state:
117 * Setting everything to zero seems safe. 122 * Setting everything to zero seems safe.
118 */ 123 */
119 xorl %eax, %eax 124 xorl %eax, %eax
@@ -132,15 +137,18 @@ identity_mapped:
132 call swap_pages 137 call swap_pages
133 addl $8, %esp 138 addl $8, %esp
134 139
135 /* To be certain of avoiding problems with self-modifying code 140 /*
141 * To be certain of avoiding problems with self-modifying code
136 * I need to execute a serializing instruction here. 142 * I need to execute a serializing instruction here.
137 * So I flush the TLB, it's handy, and not processor dependent. 143 * So I flush the TLB, it's handy, and not processor dependent.
138 */ 144 */
139 xorl %eax, %eax 145 xorl %eax, %eax
140 movl %eax, %cr3 146 movl %eax, %cr3
141 147
142 /* set all of the registers to known values */ 148 /*
143 /* leave %esp alone */ 149 * set all of the registers to known values
150 * leave %esp alone
151 */
144 152
145 testl %esi, %esi 153 testl %esi, %esi
146 jnz 1f 154 jnz 1f
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S
index d32cfb27a479..4de8f5b3d476 100644
--- a/arch/x86/kernel/relocate_kernel_64.S
+++ b/arch/x86/kernel/relocate_kernel_64.S
@@ -19,29 +19,77 @@
19#define PTR(x) (x << 3) 19#define PTR(x) (x << 3)
20#define PAGE_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) 20#define PAGE_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
21 21
22/*
23 * control_page + KEXEC_CONTROL_CODE_MAX_SIZE
24 * ~ control_page + PAGE_SIZE are used as data storage and stack for
25 * jumping back
26 */
27#define DATA(offset) (KEXEC_CONTROL_CODE_MAX_SIZE+(offset))
28
29/* Minimal CPU state */
30#define RSP DATA(0x0)
31#define CR0 DATA(0x8)
32#define CR3 DATA(0x10)
33#define CR4 DATA(0x18)
34
35/* other data */
36#define CP_PA_TABLE_PAGE DATA(0x20)
37#define CP_PA_SWAP_PAGE DATA(0x28)
38#define CP_PA_BACKUP_PAGES_MAP DATA(0x30)
39
22 .text 40 .text
23 .align PAGE_SIZE 41 .align PAGE_SIZE
24 .code64 42 .code64
25 .globl relocate_kernel 43 .globl relocate_kernel
26relocate_kernel: 44relocate_kernel:
27 /* %rdi indirection_page 45 /*
46 * %rdi indirection_page
28 * %rsi page_list 47 * %rsi page_list
29 * %rdx start address 48 * %rdx start address
49 * %rcx preserve_context
30 */ 50 */
31 51
52 /* Save the CPU context, used for jumping back */
53 pushq %rbx
54 pushq %rbp
55 pushq %r12
56 pushq %r13
57 pushq %r14
58 pushq %r15
59 pushf
60
61 movq PTR(VA_CONTROL_PAGE)(%rsi), %r11
62 movq %rsp, RSP(%r11)
63 movq %cr0, %rax
64 movq %rax, CR0(%r11)
65 movq %cr3, %rax
66 movq %rax, CR3(%r11)
67 movq %cr4, %rax
68 movq %rax, CR4(%r11)
69
32 /* zero out flags, and disable interrupts */ 70 /* zero out flags, and disable interrupts */
33 pushq $0 71 pushq $0
34 popfq 72 popfq
35 73
36 /* get physical address of control page now */ 74 /*
37 /* this is impossible after page table switch */ 75 * get physical address of control page now
76 * this is impossible after page table switch
77 */
38 movq PTR(PA_CONTROL_PAGE)(%rsi), %r8 78 movq PTR(PA_CONTROL_PAGE)(%rsi), %r8
39 79
40 /* get physical address of page table now too */ 80 /* get physical address of page table now too */
41 movq PTR(PA_TABLE_PAGE)(%rsi), %rcx 81 movq PTR(PA_TABLE_PAGE)(%rsi), %r9
82
83 /* get physical address of swap page now */
84 movq PTR(PA_SWAP_PAGE)(%rsi), %r10
85
86 /* save some information for jumping back */
87 movq %r9, CP_PA_TABLE_PAGE(%r11)
88 movq %r10, CP_PA_SWAP_PAGE(%r11)
89 movq %rdi, CP_PA_BACKUP_PAGES_MAP(%r11)
42 90
43 /* Switch to the identity mapped page tables */ 91 /* Switch to the identity mapped page tables */
44 movq %rcx, %cr3 92 movq %r9, %cr3
45 93
46 /* setup a new stack at the end of the physical control page */ 94 /* setup a new stack at the end of the physical control page */
47 lea PAGE_SIZE(%r8), %rsp 95 lea PAGE_SIZE(%r8), %rsp
@@ -55,7 +103,8 @@ identity_mapped:
55 /* store the start address on the stack */ 103 /* store the start address on the stack */
56 pushq %rdx 104 pushq %rdx
57 105
58 /* Set cr0 to a known state: 106 /*
107 * Set cr0 to a known state:
59 * - Paging enabled 108 * - Paging enabled
60 * - Alignment check disabled 109 * - Alignment check disabled
61 * - Write protect disabled 110 * - Write protect disabled
@@ -68,7 +117,8 @@ identity_mapped:
68 orl $(X86_CR0_PG | X86_CR0_PE), %eax 117 orl $(X86_CR0_PG | X86_CR0_PE), %eax
69 movq %rax, %cr0 118 movq %rax, %cr0
70 119
71 /* Set cr4 to a known state: 120 /*
121 * Set cr4 to a known state:
72 * - physical address extension enabled 122 * - physical address extension enabled
73 */ 123 */
74 movq $X86_CR4_PAE, %rax 124 movq $X86_CR4_PAE, %rax
@@ -78,9 +128,87 @@ identity_mapped:
781: 1281:
79 129
80 /* Flush the TLB (needed?) */ 130 /* Flush the TLB (needed?) */
81 movq %rcx, %cr3 131 movq %r9, %cr3
132
133 movq %rcx, %r11
134 call swap_pages
135
136 /*
137 * To be certain of avoiding problems with self-modifying code
138 * I need to execute a serializing instruction here.
139 * So I flush the TLB by reloading %cr3 here, it's handy,
140 * and not processor dependent.
141 */
142 movq %cr3, %rax
143 movq %rax, %cr3
144
145 /*
146 * set all of the registers to known values
147 * leave %rsp alone
148 */
149
150 testq %r11, %r11
151 jnz 1f
152 xorq %rax, %rax
153 xorq %rbx, %rbx
154 xorq %rcx, %rcx
155 xorq %rdx, %rdx
156 xorq %rsi, %rsi
157 xorq %rdi, %rdi
158 xorq %rbp, %rbp
159 xorq %r8, %r8
160 xorq %r9, %r9
161 xorq %r10, %r9
162 xorq %r11, %r11
163 xorq %r12, %r12
164 xorq %r13, %r13
165 xorq %r14, %r14
166 xorq %r15, %r15
167
168 ret
169
1701:
171 popq %rdx
172 leaq PAGE_SIZE(%r10), %rsp
173 call *%rdx
174
175 /* get the re-entry point of the peer system */
176 movq 0(%rsp), %rbp
177 call 1f
1781:
179 popq %r8
180 subq $(1b - relocate_kernel), %r8
181 movq CP_PA_SWAP_PAGE(%r8), %r10
182 movq CP_PA_BACKUP_PAGES_MAP(%r8), %rdi
183 movq CP_PA_TABLE_PAGE(%r8), %rax
184 movq %rax, %cr3
185 lea PAGE_SIZE(%r8), %rsp
186 call swap_pages
187 movq $virtual_mapped, %rax
188 pushq %rax
189 ret
190
191virtual_mapped:
192 movq RSP(%r8), %rsp
193 movq CR4(%r8), %rax
194 movq %rax, %cr4
195 movq CR3(%r8), %rax
196 movq CR0(%r8), %r8
197 movq %rax, %cr3
198 movq %r8, %cr0
199 movq %rbp, %rax
200
201 popf
202 popq %r15
203 popq %r14
204 popq %r13
205 popq %r12
206 popq %rbp
207 popq %rbx
208 ret
82 209
83 /* Do the copies */ 210 /* Do the copies */
211swap_pages:
84 movq %rdi, %rcx /* Put the page_list in %rcx */ 212 movq %rdi, %rcx /* Put the page_list in %rcx */
85 xorq %rdi, %rdi 213 xorq %rdi, %rdi
86 xorq %rsi, %rsi 214 xorq %rsi, %rsi
@@ -112,36 +240,27 @@ identity_mapped:
112 movq %rcx, %rsi /* For ever source page do a copy */ 240 movq %rcx, %rsi /* For ever source page do a copy */
113 andq $0xfffffffffffff000, %rsi 241 andq $0xfffffffffffff000, %rsi
114 242
243 movq %rdi, %rdx
244 movq %rsi, %rax
245
246 movq %r10, %rdi
115 movq $512, %rcx 247 movq $512, %rcx
116 rep ; movsq 248 rep ; movsq
117 jmp 0b
1183:
119
120 /* To be certain of avoiding problems with self-modifying code
121 * I need to execute a serializing instruction here.
122 * So I flush the TLB by reloading %cr3 here, it's handy,
123 * and not processor dependent.
124 */
125 movq %cr3, %rax
126 movq %rax, %cr3
127 249
128 /* set all of the registers to known values */ 250 movq %rax, %rdi
129 /* leave %rsp alone */ 251 movq %rdx, %rsi
252 movq $512, %rcx
253 rep ; movsq
130 254
131 xorq %rax, %rax 255 movq %rdx, %rdi
132 xorq %rbx, %rbx 256 movq %r10, %rsi
133 xorq %rcx, %rcx 257 movq $512, %rcx
134 xorq %rdx, %rdx 258 rep ; movsq
135 xorq %rsi, %rsi
136 xorq %rdi, %rdi
137 xorq %rbp, %rbp
138 xorq %r8, %r8
139 xorq %r9, %r9
140 xorq %r10, %r9
141 xorq %r11, %r11
142 xorq %r12, %r12
143 xorq %r13, %r13
144 xorq %r14, %r14
145 xorq %r15, %r15
146 259
260 lea PAGE_SIZE(%rax), %rsi
261 jmp 0b
2623:
147 ret 263 ret
264
265 .globl kexec_control_code_size
266.set kexec_control_code_size, . - relocate_kernel
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 4c54bc0d8ff3..f28c56e6bf94 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -202,7 +202,9 @@ struct ist_info ist_info;
202#endif 202#endif
203 203
204#else 204#else
205struct cpuinfo_x86 boot_cpu_data __read_mostly; 205struct cpuinfo_x86 boot_cpu_data __read_mostly = {
206 .x86_phys_bits = MAX_PHYSMEM_BITS,
207};
206EXPORT_SYMBOL(boot_cpu_data); 208EXPORT_SYMBOL(boot_cpu_data);
207#endif 209#endif
208 210
@@ -770,6 +772,9 @@ void __init setup_arch(char **cmdline_p)
770 772
771 finish_e820_parsing(); 773 finish_e820_parsing();
772 774
775 if (efi_enabled)
776 efi_init();
777
773 dmi_scan_machine(); 778 dmi_scan_machine();
774 779
775 dmi_check_system(bad_bios_dmi_table); 780 dmi_check_system(bad_bios_dmi_table);
@@ -789,8 +794,6 @@ void __init setup_arch(char **cmdline_p)
789 insert_resource(&iomem_resource, &data_resource); 794 insert_resource(&iomem_resource, &data_resource);
790 insert_resource(&iomem_resource, &bss_resource); 795 insert_resource(&iomem_resource, &bss_resource);
791 796
792 if (efi_enabled)
793 efi_init();
794 797
795#ifdef CONFIG_X86_32 798#ifdef CONFIG_X86_32
796 if (ppro_with_ram_bug()) { 799 if (ppro_with_ram_bug()) {
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index d992e6cff730..efa615f2bf43 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -7,6 +7,7 @@
7#include <linux/crash_dump.h> 7#include <linux/crash_dump.h>
8#include <linux/smp.h> 8#include <linux/smp.h>
9#include <linux/topology.h> 9#include <linux/topology.h>
10#include <linux/pfn.h>
10#include <asm/sections.h> 11#include <asm/sections.h>
11#include <asm/processor.h> 12#include <asm/processor.h>
12#include <asm/setup.h> 13#include <asm/setup.h>
@@ -41,6 +42,352 @@ unsigned long __per_cpu_offset[NR_CPUS] __read_mostly = {
41}; 42};
42EXPORT_SYMBOL(__per_cpu_offset); 43EXPORT_SYMBOL(__per_cpu_offset);
43 44
45/*
46 * On x86_64 symbols referenced from code should be reachable using
47 * 32bit relocations. Reserve space for static percpu variables in
48 * modules so that they are always served from the first chunk which
49 * is located at the percpu segment base. On x86_32, anything can
50 * address anywhere. No need to reserve space in the first chunk.
51 */
52#ifdef CONFIG_X86_64
53#define PERCPU_FIRST_CHUNK_RESERVE PERCPU_MODULE_RESERVE
54#else
55#define PERCPU_FIRST_CHUNK_RESERVE 0
56#endif
57
58/**
59 * pcpu_need_numa - determine percpu allocation needs to consider NUMA
60 *
61 * If NUMA is not configured or there is only one NUMA node available,
62 * there is no reason to consider NUMA. This function determines
63 * whether percpu allocation should consider NUMA or not.
64 *
65 * RETURNS:
66 * true if NUMA should be considered; otherwise, false.
67 */
68static bool __init pcpu_need_numa(void)
69{
70#ifdef CONFIG_NEED_MULTIPLE_NODES
71 pg_data_t *last = NULL;
72 unsigned int cpu;
73
74 for_each_possible_cpu(cpu) {
75 int node = early_cpu_to_node(cpu);
76
77 if (node_online(node) && NODE_DATA(node) &&
78 last && last != NODE_DATA(node))
79 return true;
80
81 last = NODE_DATA(node);
82 }
83#endif
84 return false;
85}
86
87/**
88 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
89 * @cpu: cpu to allocate for
90 * @size: size allocation in bytes
91 * @align: alignment
92 *
93 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
94 * does the right thing for NUMA regardless of the current
95 * configuration.
96 *
97 * RETURNS:
98 * Pointer to the allocated area on success, NULL on failure.
99 */
100static void * __init pcpu_alloc_bootmem(unsigned int cpu, unsigned long size,
101 unsigned long align)
102{
103 const unsigned long goal = __pa(MAX_DMA_ADDRESS);
104#ifdef CONFIG_NEED_MULTIPLE_NODES
105 int node = early_cpu_to_node(cpu);
106 void *ptr;
107
108 if (!node_online(node) || !NODE_DATA(node)) {
109 ptr = __alloc_bootmem_nopanic(size, align, goal);
110 pr_info("cpu %d has no node %d or node-local memory\n",
111 cpu, node);
112 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
113 cpu, size, __pa(ptr));
114 } else {
115 ptr = __alloc_bootmem_node_nopanic(NODE_DATA(node),
116 size, align, goal);
117 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
118 "%016lx\n", cpu, size, node, __pa(ptr));
119 }
120 return ptr;
121#else
122 return __alloc_bootmem_nopanic(size, align, goal);
123#endif
124}
125
126/*
127 * Remap allocator
128 *
129 * This allocator uses PMD page as unit. A PMD page is allocated for
130 * each cpu and each is remapped into vmalloc area using PMD mapping.
131 * As PMD page is quite large, only part of it is used for the first
132 * chunk. Unused part is returned to the bootmem allocator.
133 *
134 * So, the PMD pages are mapped twice - once to the physical mapping
135 * and to the vmalloc area for the first percpu chunk. The double
136 * mapping does add one more PMD TLB entry pressure but still is much
137 * better than only using 4k mappings while still being NUMA friendly.
138 */
139#ifdef CONFIG_NEED_MULTIPLE_NODES
140static size_t pcpur_size __initdata;
141static void **pcpur_ptrs __initdata;
142
143static struct page * __init pcpur_get_page(unsigned int cpu, int pageno)
144{
145 size_t off = (size_t)pageno << PAGE_SHIFT;
146
147 if (off >= pcpur_size)
148 return NULL;
149
150 return virt_to_page(pcpur_ptrs[cpu] + off);
151}
152
153static ssize_t __init setup_pcpu_remap(size_t static_size)
154{
155 static struct vm_struct vm;
156 pg_data_t *last;
157 size_t ptrs_size, dyn_size;
158 unsigned int cpu;
159 ssize_t ret;
160
161 /*
162 * If large page isn't supported, there's no benefit in doing
163 * this. Also, on non-NUMA, embedding is better.
164 */
165 if (!cpu_has_pse || pcpu_need_numa())
166 return -EINVAL;
167
168 last = NULL;
169 for_each_possible_cpu(cpu) {
170 int node = early_cpu_to_node(cpu);
171
172 if (node_online(node) && NODE_DATA(node) &&
173 last && last != NODE_DATA(node))
174 goto proceed;
175
176 last = NODE_DATA(node);
177 }
178 return -EINVAL;
179
180proceed:
181 /*
182 * Currently supports only single page. Supporting multiple
183 * pages won't be too difficult if it ever becomes necessary.
184 */
185 pcpur_size = PFN_ALIGN(static_size + PERCPU_MODULE_RESERVE +
186 PERCPU_DYNAMIC_RESERVE);
187 if (pcpur_size > PMD_SIZE) {
188 pr_warning("PERCPU: static data is larger than large page, "
189 "can't use large page\n");
190 return -EINVAL;
191 }
192 dyn_size = pcpur_size - static_size - PERCPU_FIRST_CHUNK_RESERVE;
193
194 /* allocate pointer array and alloc large pages */
195 ptrs_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpur_ptrs[0]));
196 pcpur_ptrs = alloc_bootmem(ptrs_size);
197
198 for_each_possible_cpu(cpu) {
199 pcpur_ptrs[cpu] = pcpu_alloc_bootmem(cpu, PMD_SIZE, PMD_SIZE);
200 if (!pcpur_ptrs[cpu])
201 goto enomem;
202
203 /*
204 * Only use pcpur_size bytes and give back the rest.
205 *
206 * Ingo: The 2MB up-rounding bootmem is needed to make
207 * sure the partial 2MB page is still fully RAM - it's
208 * not well-specified to have a PAT-incompatible area
209 * (unmapped RAM, device memory, etc.) in that hole.
210 */
211 free_bootmem(__pa(pcpur_ptrs[cpu] + pcpur_size),
212 PMD_SIZE - pcpur_size);
213
214 memcpy(pcpur_ptrs[cpu], __per_cpu_load, static_size);
215 }
216
217 /* allocate address and map */
218 vm.flags = VM_ALLOC;
219 vm.size = num_possible_cpus() * PMD_SIZE;
220 vm_area_register_early(&vm, PMD_SIZE);
221
222 for_each_possible_cpu(cpu) {
223 pmd_t *pmd;
224
225 pmd = populate_extra_pmd((unsigned long)vm.addr
226 + cpu * PMD_SIZE);
227 set_pmd(pmd, pfn_pmd(page_to_pfn(virt_to_page(pcpur_ptrs[cpu])),
228 PAGE_KERNEL_LARGE));
229 }
230
231 /* we're ready, commit */
232 pr_info("PERCPU: Remapped at %p with large pages, static data "
233 "%zu bytes\n", vm.addr, static_size);
234
235 ret = pcpu_setup_first_chunk(pcpur_get_page, static_size,
236 PERCPU_FIRST_CHUNK_RESERVE,
237 PMD_SIZE, dyn_size, vm.addr, NULL);
238 goto out_free_ar;
239
240enomem:
241 for_each_possible_cpu(cpu)
242 if (pcpur_ptrs[cpu])
243 free_bootmem(__pa(pcpur_ptrs[cpu]), PMD_SIZE);
244 ret = -ENOMEM;
245out_free_ar:
246 free_bootmem(__pa(pcpur_ptrs), ptrs_size);
247 return ret;
248}
249#else
250static ssize_t __init setup_pcpu_remap(size_t static_size)
251{
252 return -EINVAL;
253}
254#endif
255
256/*
257 * Embedding allocator
258 *
259 * The first chunk is sized to just contain the static area plus
260 * module and dynamic reserves, and allocated as a contiguous area
261 * using bootmem allocator and used as-is without being mapped into
262 * vmalloc area. This enables the first chunk to piggy back on the
263 * linear physical PMD mapping and doesn't add any additional pressure
264 * to TLB. Note that if the needed size is smaller than the minimum
265 * unit size, the leftover is returned to the bootmem allocator.
266 */
267static void *pcpue_ptr __initdata;
268static size_t pcpue_size __initdata;
269static size_t pcpue_unit_size __initdata;
270
271static struct page * __init pcpue_get_page(unsigned int cpu, int pageno)
272{
273 size_t off = (size_t)pageno << PAGE_SHIFT;
274
275 if (off >= pcpue_size)
276 return NULL;
277
278 return virt_to_page(pcpue_ptr + cpu * pcpue_unit_size + off);
279}
280
281static ssize_t __init setup_pcpu_embed(size_t static_size)
282{
283 unsigned int cpu;
284 size_t dyn_size;
285
286 /*
287 * If large page isn't supported, there's no benefit in doing
288 * this. Also, embedding allocation doesn't play well with
289 * NUMA.
290 */
291 if (!cpu_has_pse || pcpu_need_numa())
292 return -EINVAL;
293
294 /* allocate and copy */
295 pcpue_size = PFN_ALIGN(static_size + PERCPU_MODULE_RESERVE +
296 PERCPU_DYNAMIC_RESERVE);
297 pcpue_unit_size = max_t(size_t, pcpue_size, PCPU_MIN_UNIT_SIZE);
298 dyn_size = pcpue_size - static_size - PERCPU_FIRST_CHUNK_RESERVE;
299
300 pcpue_ptr = pcpu_alloc_bootmem(0, num_possible_cpus() * pcpue_unit_size,
301 PAGE_SIZE);
302 if (!pcpue_ptr)
303 return -ENOMEM;
304
305 for_each_possible_cpu(cpu) {
306 void *ptr = pcpue_ptr + cpu * pcpue_unit_size;
307
308 free_bootmem(__pa(ptr + pcpue_size),
309 pcpue_unit_size - pcpue_size);
310 memcpy(ptr, __per_cpu_load, static_size);
311 }
312
313 /* we're ready, commit */
314 pr_info("PERCPU: Embedded %zu pages at %p, static data %zu bytes\n",
315 pcpue_size >> PAGE_SHIFT, pcpue_ptr, static_size);
316
317 return pcpu_setup_first_chunk(pcpue_get_page, static_size,
318 PERCPU_FIRST_CHUNK_RESERVE,
319 pcpue_unit_size, dyn_size,
320 pcpue_ptr, NULL);
321}
322
323/*
324 * 4k page allocator
325 *
326 * This is the basic allocator. Static percpu area is allocated
327 * page-by-page and most of initialization is done by the generic
328 * setup function.
329 */
330static struct page **pcpu4k_pages __initdata;
331static int pcpu4k_nr_static_pages __initdata;
332
333static struct page * __init pcpu4k_get_page(unsigned int cpu, int pageno)
334{
335 if (pageno < pcpu4k_nr_static_pages)
336 return pcpu4k_pages[cpu * pcpu4k_nr_static_pages + pageno];
337 return NULL;
338}
339
340static void __init pcpu4k_populate_pte(unsigned long addr)
341{
342 populate_extra_pte(addr);
343}
344
345static ssize_t __init setup_pcpu_4k(size_t static_size)
346{
347 size_t pages_size;
348 unsigned int cpu;
349 int i, j;
350 ssize_t ret;
351
352 pcpu4k_nr_static_pages = PFN_UP(static_size);
353
354 /* unaligned allocations can't be freed, round up to page size */
355 pages_size = PFN_ALIGN(pcpu4k_nr_static_pages * num_possible_cpus()
356 * sizeof(pcpu4k_pages[0]));
357 pcpu4k_pages = alloc_bootmem(pages_size);
358
359 /* allocate and copy */
360 j = 0;
361 for_each_possible_cpu(cpu)
362 for (i = 0; i < pcpu4k_nr_static_pages; i++) {
363 void *ptr;
364
365 ptr = pcpu_alloc_bootmem(cpu, PAGE_SIZE, PAGE_SIZE);
366 if (!ptr)
367 goto enomem;
368
369 memcpy(ptr, __per_cpu_load + i * PAGE_SIZE, PAGE_SIZE);
370 pcpu4k_pages[j++] = virt_to_page(ptr);
371 }
372
373 /* we're ready, commit */
374 pr_info("PERCPU: Allocated %d 4k pages, static data %zu bytes\n",
375 pcpu4k_nr_static_pages, static_size);
376
377 ret = pcpu_setup_first_chunk(pcpu4k_get_page, static_size,
378 PERCPU_FIRST_CHUNK_RESERVE, -1, -1, NULL,
379 pcpu4k_populate_pte);
380 goto out_free_ar;
381
382enomem:
383 while (--j >= 0)
384 free_bootmem(__pa(page_address(pcpu4k_pages[j])), PAGE_SIZE);
385 ret = -ENOMEM;
386out_free_ar:
387 free_bootmem(__pa(pcpu4k_pages), pages_size);
388 return ret;
389}
390
44static inline void setup_percpu_segment(int cpu) 391static inline void setup_percpu_segment(int cpu)
45{ 392{
46#ifdef CONFIG_X86_32 393#ifdef CONFIG_X86_32
@@ -61,38 +408,35 @@ static inline void setup_percpu_segment(int cpu)
61 */ 408 */
62void __init setup_per_cpu_areas(void) 409void __init setup_per_cpu_areas(void)
63{ 410{
64 ssize_t size; 411 size_t static_size = __per_cpu_end - __per_cpu_start;
65 char *ptr; 412 unsigned int cpu;
66 int cpu; 413 unsigned long delta;
67 414 size_t pcpu_unit_size;
68 /* Copy section for each CPU (we discard the original) */ 415 ssize_t ret;
69 size = roundup(PERCPU_ENOUGH_ROOM, PAGE_SIZE);
70 416
71 pr_info("NR_CPUS:%d nr_cpumask_bits:%d nr_cpu_ids:%d nr_node_ids:%d\n", 417 pr_info("NR_CPUS:%d nr_cpumask_bits:%d nr_cpu_ids:%d nr_node_ids:%d\n",
72 NR_CPUS, nr_cpumask_bits, nr_cpu_ids, nr_node_ids); 418 NR_CPUS, nr_cpumask_bits, nr_cpu_ids, nr_node_ids);
73 419
74 pr_info("PERCPU: Allocating %zd bytes of per cpu data\n", size); 420 /*
421 * Allocate percpu area. If PSE is supported, try to make use
422 * of large page mappings. Please read comments on top of
423 * each allocator for details.
424 */
425 ret = setup_pcpu_remap(static_size);
426 if (ret < 0)
427 ret = setup_pcpu_embed(static_size);
428 if (ret < 0)
429 ret = setup_pcpu_4k(static_size);
430 if (ret < 0)
431 panic("cannot allocate static percpu area (%zu bytes, err=%zd)",
432 static_size, ret);
75 433
76 for_each_possible_cpu(cpu) { 434 pcpu_unit_size = ret;
77#ifndef CONFIG_NEED_MULTIPLE_NODES
78 ptr = alloc_bootmem_pages(size);
79#else
80 int node = early_cpu_to_node(cpu);
81 if (!node_online(node) || !NODE_DATA(node)) {
82 ptr = alloc_bootmem_pages(size);
83 pr_info("cpu %d has no node %d or node-local memory\n",
84 cpu, node);
85 pr_debug("per cpu data for cpu%d at %016lx\n",
86 cpu, __pa(ptr));
87 } else {
88 ptr = alloc_bootmem_pages_node(NODE_DATA(node), size);
89 pr_debug("per cpu data for cpu%d on node%d at %016lx\n",
90 cpu, node, __pa(ptr));
91 }
92#endif
93 435
94 memcpy(ptr, __per_cpu_load, __per_cpu_end - __per_cpu_start); 436 /* alrighty, percpu areas up and running */
95 per_cpu_offset(cpu) = ptr - __per_cpu_start; 437 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
438 for_each_possible_cpu(cpu) {
439 per_cpu_offset(cpu) = delta + cpu * pcpu_unit_size;
96 per_cpu(this_cpu_off, cpu) = per_cpu_offset(cpu); 440 per_cpu(this_cpu_off, cpu) = per_cpu_offset(cpu);
97 per_cpu(cpu_number, cpu) = cpu; 441 per_cpu(cpu_number, cpu) = cpu;
98 setup_percpu_segment(cpu); 442 setup_percpu_segment(cpu);
@@ -125,8 +469,6 @@ void __init setup_per_cpu_areas(void)
125 */ 469 */
126 if (cpu == boot_cpu_id) 470 if (cpu == boot_cpu_id)
127 switch_to_new_gdt(cpu); 471 switch_to_new_gdt(cpu);
128
129 DBG("PERCPU: cpu %4d %p\n", cpu, ptr);
130 } 472 }
131 473
132 /* indicate the early static arrays will soon be gone */ 474 /* indicate the early static arrays will soon be gone */
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 249334f5080a..ef7d10170c30 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -114,10 +114,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_info);
114 114
115atomic_t init_deasserted; 115atomic_t init_deasserted;
116 116
117
118/* Set if we find a B stepping CPU */
119static int __cpuinitdata smp_b_stepping;
120
121#if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 117#if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
122 118
123/* which logical CPUs are on which nodes */ 119/* which logical CPUs are on which nodes */
@@ -271,8 +267,6 @@ static void __cpuinit smp_callin(void)
271 cpumask_set_cpu(cpuid, cpu_callin_mask); 267 cpumask_set_cpu(cpuid, cpu_callin_mask);
272} 268}
273 269
274static int __cpuinitdata unsafe_smp;
275
276/* 270/*
277 * Activate a secondary processor. 271 * Activate a secondary processor.
278 */ 272 */
@@ -340,76 +334,6 @@ notrace static void __cpuinit start_secondary(void *unused)
340 cpu_idle(); 334 cpu_idle();
341} 335}
342 336
343static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
344{
345 /*
346 * Mask B, Pentium, but not Pentium MMX
347 */
348 if (c->x86_vendor == X86_VENDOR_INTEL &&
349 c->x86 == 5 &&
350 c->x86_mask >= 1 && c->x86_mask <= 4 &&
351 c->x86_model <= 3)
352 /*
353 * Remember we have B step Pentia with bugs
354 */
355 smp_b_stepping = 1;
356
357 /*
358 * Certain Athlons might work (for various values of 'work') in SMP
359 * but they are not certified as MP capable.
360 */
361 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
362
363 if (num_possible_cpus() == 1)
364 goto valid_k7;
365
366 /* Athlon 660/661 is valid. */
367 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
368 (c->x86_mask == 1)))
369 goto valid_k7;
370
371 /* Duron 670 is valid */
372 if ((c->x86_model == 7) && (c->x86_mask == 0))
373 goto valid_k7;
374
375 /*
376 * Athlon 662, Duron 671, and Athlon >model 7 have capability
377 * bit. It's worth noting that the A5 stepping (662) of some
378 * Athlon XP's have the MP bit set.
379 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
380 * more.
381 */
382 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
383 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
384 (c->x86_model > 7))
385 if (cpu_has_mp)
386 goto valid_k7;
387
388 /* If we get here, not a certified SMP capable AMD system. */
389 unsafe_smp = 1;
390 }
391
392valid_k7:
393 ;
394}
395
396static void __cpuinit smp_checks(void)
397{
398 if (smp_b_stepping)
399 printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
400 "with B stepping processors.\n");
401
402 /*
403 * Don't taint if we are running SMP kernel on a single non-MP
404 * approved Athlon
405 */
406 if (unsafe_smp && num_online_cpus() > 1) {
407 printk(KERN_INFO "WARNING: This combination of AMD"
408 "processors is not suitable for SMP.\n");
409 add_taint(TAINT_UNSAFE_SMP);
410 }
411}
412
413/* 337/*
414 * The bootstrap kernel entry code has set these up. Save them for 338 * The bootstrap kernel entry code has set these up. Save them for
415 * a given CPU 339 * a given CPU
@@ -423,7 +347,6 @@ void __cpuinit smp_store_cpu_info(int id)
423 c->cpu_index = id; 347 c->cpu_index = id;
424 if (id != 0) 348 if (id != 0)
425 identify_secondary_cpu(c); 349 identify_secondary_cpu(c);
426 smp_apply_quirks(c);
427} 350}
428 351
429 352
@@ -1193,7 +1116,6 @@ void __init native_smp_cpus_done(unsigned int max_cpus)
1193 pr_debug("Boot done.\n"); 1116 pr_debug("Boot done.\n");
1194 1117
1195 impress_friends(); 1118 impress_friends();
1196 smp_checks();
1197#ifdef CONFIG_X86_IO_APIC 1119#ifdef CONFIG_X86_IO_APIC
1198 setup_ioapic_dest(); 1120 setup_ioapic_dest();
1199#endif 1121#endif
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c
index f04549afcfe9..d038b9c45cf8 100644
--- a/arch/x86/kernel/tlb_uv.c
+++ b/arch/x86/kernel/tlb_uv.c
@@ -314,8 +314,6 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
314 int locals = 0; 314 int locals = 0;
315 struct bau_desc *bau_desc; 315 struct bau_desc *bau_desc;
316 316
317 WARN_ON(!in_atomic());
318
319 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); 317 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
320 318
321 uv_cpu = uv_blade_processor_id(); 319 uv_cpu = uv_blade_processor_id();
diff --git a/arch/x86/kernel/uv_time.c b/arch/x86/kernel/uv_time.c
new file mode 100644
index 000000000000..2ffb6c53326e
--- /dev/null
+++ b/arch/x86/kernel/uv_time.c
@@ -0,0 +1,393 @@
1/*
2 * SGI RTC clock/timer routines.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved.
19 * Copyright (c) Dimitri Sivanich
20 */
21#include <linux/clockchips.h>
22
23#include <asm/uv/uv_mmrs.h>
24#include <asm/uv/uv_hub.h>
25#include <asm/uv/bios.h>
26#include <asm/uv/uv.h>
27#include <asm/apic.h>
28#include <asm/cpu.h>
29
30#define RTC_NAME "sgi_rtc"
31
32static cycle_t uv_read_rtc(void);
33static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
34static void uv_rtc_timer_setup(enum clock_event_mode,
35 struct clock_event_device *);
36
37static struct clocksource clocksource_uv = {
38 .name = RTC_NAME,
39 .rating = 400,
40 .read = uv_read_rtc,
41 .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
42 .shift = 10,
43 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
44};
45
46static struct clock_event_device clock_event_device_uv = {
47 .name = RTC_NAME,
48 .features = CLOCK_EVT_FEAT_ONESHOT,
49 .shift = 20,
50 .rating = 400,
51 .irq = -1,
52 .set_next_event = uv_rtc_next_event,
53 .set_mode = uv_rtc_timer_setup,
54 .event_handler = NULL,
55};
56
57static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
58
59/* There is one of these allocated per node */
60struct uv_rtc_timer_head {
61 spinlock_t lock;
62 /* next cpu waiting for timer, local node relative: */
63 int next_cpu;
64 /* number of cpus on this node: */
65 int ncpus;
66 struct {
67 int lcpu; /* systemwide logical cpu number */
68 u64 expires; /* next timer expiration for this cpu */
69 } cpu[1];
70};
71
72/*
73 * Access to uv_rtc_timer_head via blade id.
74 */
75static struct uv_rtc_timer_head **blade_info __read_mostly;
76
77static int uv_rtc_enable;
78
79/*
80 * Hardware interface routines
81 */
82
83/* Send IPIs to another node */
84static void uv_rtc_send_IPI(int cpu)
85{
86 unsigned long apicid, val;
87 int pnode;
88
89 apicid = cpu_physical_id(cpu);
90 pnode = uv_apicid_to_pnode(apicid);
91 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
92 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
93 (GENERIC_INTERRUPT_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
94
95 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
96}
97
98/* Check for an RTC interrupt pending */
99static int uv_intr_pending(int pnode)
100{
101 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
102 UVH_EVENT_OCCURRED0_RTC1_MASK;
103}
104
105/* Setup interrupt and return non-zero if early expiration occurred. */
106static int uv_setup_intr(int cpu, u64 expires)
107{
108 u64 val;
109 int pnode = uv_cpu_to_pnode(cpu);
110
111 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
112 UVH_RTC1_INT_CONFIG_M_MASK);
113 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
114
115 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
116 UVH_EVENT_OCCURRED0_RTC1_MASK);
117
118 val = (GENERIC_INTERRUPT_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
119 ((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
120
121 /* Set configuration */
122 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
123 /* Initialize comparator value */
124 uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
125
126 return (expires < uv_read_rtc() && !uv_intr_pending(pnode));
127}
128
129/*
130 * Per-cpu timer tracking routines
131 */
132
133static __init void uv_rtc_deallocate_timers(void)
134{
135 int bid;
136
137 for_each_possible_blade(bid) {
138 kfree(blade_info[bid]);
139 }
140 kfree(blade_info);
141}
142
143/* Allocate per-node list of cpu timer expiration times. */
144static __init int uv_rtc_allocate_timers(void)
145{
146 int cpu;
147
148 blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
149 if (!blade_info)
150 return -ENOMEM;
151 memset(blade_info, 0, uv_possible_blades * sizeof(void *));
152
153 for_each_present_cpu(cpu) {
154 int nid = cpu_to_node(cpu);
155 int bid = uv_cpu_to_blade_id(cpu);
156 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
157 struct uv_rtc_timer_head *head = blade_info[bid];
158
159 if (!head) {
160 head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
161 (uv_blade_nr_possible_cpus(bid) *
162 2 * sizeof(u64)),
163 GFP_KERNEL, nid);
164 if (!head) {
165 uv_rtc_deallocate_timers();
166 return -ENOMEM;
167 }
168 spin_lock_init(&head->lock);
169 head->ncpus = uv_blade_nr_possible_cpus(bid);
170 head->next_cpu = -1;
171 blade_info[bid] = head;
172 }
173
174 head->cpu[bcpu].lcpu = cpu;
175 head->cpu[bcpu].expires = ULLONG_MAX;
176 }
177
178 return 0;
179}
180
181/* Find and set the next expiring timer. */
182static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
183{
184 u64 lowest = ULLONG_MAX;
185 int c, bcpu = -1;
186
187 head->next_cpu = -1;
188 for (c = 0; c < head->ncpus; c++) {
189 u64 exp = head->cpu[c].expires;
190 if (exp < lowest) {
191 bcpu = c;
192 lowest = exp;
193 }
194 }
195 if (bcpu >= 0) {
196 head->next_cpu = bcpu;
197 c = head->cpu[bcpu].lcpu;
198 if (uv_setup_intr(c, lowest))
199 /* If we didn't set it up in time, trigger */
200 uv_rtc_send_IPI(c);
201 } else {
202 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
203 UVH_RTC1_INT_CONFIG_M_MASK);
204 }
205}
206
207/*
208 * Set expiration time for current cpu.
209 *
210 * Returns 1 if we missed the expiration time.
211 */
212static int uv_rtc_set_timer(int cpu, u64 expires)
213{
214 int pnode = uv_cpu_to_pnode(cpu);
215 int bid = uv_cpu_to_blade_id(cpu);
216 struct uv_rtc_timer_head *head = blade_info[bid];
217 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
218 u64 *t = &head->cpu[bcpu].expires;
219 unsigned long flags;
220 int next_cpu;
221
222 spin_lock_irqsave(&head->lock, flags);
223
224 next_cpu = head->next_cpu;
225 *t = expires;
226 /* Will this one be next to go off? */
227 if (next_cpu < 0 || bcpu == next_cpu ||
228 expires < head->cpu[next_cpu].expires) {
229 head->next_cpu = bcpu;
230 if (uv_setup_intr(cpu, expires)) {
231 *t = ULLONG_MAX;
232 uv_rtc_find_next_timer(head, pnode);
233 spin_unlock_irqrestore(&head->lock, flags);
234 return 1;
235 }
236 }
237
238 spin_unlock_irqrestore(&head->lock, flags);
239 return 0;
240}
241
242/*
243 * Unset expiration time for current cpu.
244 *
245 * Returns 1 if this timer was pending.
246 */
247static int uv_rtc_unset_timer(int cpu)
248{
249 int pnode = uv_cpu_to_pnode(cpu);
250 int bid = uv_cpu_to_blade_id(cpu);
251 struct uv_rtc_timer_head *head = blade_info[bid];
252 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
253 u64 *t = &head->cpu[bcpu].expires;
254 unsigned long flags;
255 int rc = 0;
256
257 spin_lock_irqsave(&head->lock, flags);
258
259 if (head->next_cpu == bcpu && uv_read_rtc() >= *t)
260 rc = 1;
261
262 *t = ULLONG_MAX;
263
264 /* Was the hardware setup for this timer? */
265 if (head->next_cpu == bcpu)
266 uv_rtc_find_next_timer(head, pnode);
267
268 spin_unlock_irqrestore(&head->lock, flags);
269
270 return rc;
271}
272
273
274/*
275 * Kernel interface routines.
276 */
277
278/*
279 * Read the RTC.
280 */
281static cycle_t uv_read_rtc(void)
282{
283 return (cycle_t)uv_read_local_mmr(UVH_RTC);
284}
285
286/*
287 * Program the next event, relative to now
288 */
289static int uv_rtc_next_event(unsigned long delta,
290 struct clock_event_device *ced)
291{
292 int ced_cpu = cpumask_first(ced->cpumask);
293
294 return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc());
295}
296
297/*
298 * Setup the RTC timer in oneshot mode
299 */
300static void uv_rtc_timer_setup(enum clock_event_mode mode,
301 struct clock_event_device *evt)
302{
303 int ced_cpu = cpumask_first(evt->cpumask);
304
305 switch (mode) {
306 case CLOCK_EVT_MODE_PERIODIC:
307 case CLOCK_EVT_MODE_ONESHOT:
308 case CLOCK_EVT_MODE_RESUME:
309 /* Nothing to do here yet */
310 break;
311 case CLOCK_EVT_MODE_UNUSED:
312 case CLOCK_EVT_MODE_SHUTDOWN:
313 uv_rtc_unset_timer(ced_cpu);
314 break;
315 }
316}
317
318static void uv_rtc_interrupt(void)
319{
320 struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
321 int cpu = smp_processor_id();
322
323 if (!ced || !ced->event_handler)
324 return;
325
326 if (uv_rtc_unset_timer(cpu) != 1)
327 return;
328
329 ced->event_handler(ced);
330}
331
332static int __init uv_enable_rtc(char *str)
333{
334 uv_rtc_enable = 1;
335
336 return 1;
337}
338__setup("uvrtc", uv_enable_rtc);
339
340static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
341{
342 struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
343
344 *ced = clock_event_device_uv;
345 ced->cpumask = cpumask_of(smp_processor_id());
346 clockevents_register_device(ced);
347}
348
349static __init int uv_rtc_setup_clock(void)
350{
351 int rc;
352
353 if (!uv_rtc_enable || !is_uv_system() || generic_interrupt_extension)
354 return -ENODEV;
355
356 generic_interrupt_extension = uv_rtc_interrupt;
357
358 clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
359 clocksource_uv.shift);
360
361 rc = clocksource_register(&clocksource_uv);
362 if (rc) {
363 generic_interrupt_extension = NULL;
364 return rc;
365 }
366
367 /* Setup and register clockevents */
368 rc = uv_rtc_allocate_timers();
369 if (rc) {
370 clocksource_unregister(&clocksource_uv);
371 generic_interrupt_extension = NULL;
372 return rc;
373 }
374
375 clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
376 NSEC_PER_SEC, clock_event_device_uv.shift);
377
378 clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
379 sn_rtc_cycles_per_second;
380
381 clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
382 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
383
384 rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
385 if (rc) {
386 clocksource_unregister(&clocksource_uv);
387 generic_interrupt_extension = NULL;
388 uv_rtc_deallocate_timers();
389 }
390
391 return rc;
392}
393arch_initcall(uv_rtc_setup_clock);
diff --git a/arch/x86/kernel/vmlinux_64.lds.S b/arch/x86/kernel/vmlinux_64.lds.S
index fbfced6f6800..5bf54e40c6ef 100644
--- a/arch/x86/kernel/vmlinux_64.lds.S
+++ b/arch/x86/kernel/vmlinux_64.lds.S
@@ -275,3 +275,10 @@ ASSERT((_end - _text <= KERNEL_IMAGE_SIZE),
275ASSERT((per_cpu__irq_stack_union == 0), 275ASSERT((per_cpu__irq_stack_union == 0),
276 "irq_stack_union is not at start of per-cpu area"); 276 "irq_stack_union is not at start of per-cpu area");
277#endif 277#endif
278
279#ifdef CONFIG_KEXEC
280#include <asm/kexec.h>
281
282ASSERT(kexec_control_code_size <= KEXEC_CONTROL_CODE_MAX_SIZE,
283 "kexec control code size is too big")
284#endif
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index f3a5305b8adf..9fe4ddaa8f6f 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -348,6 +348,11 @@ static void lguest_cpuid(unsigned int *ax, unsigned int *bx,
348 * flush_tlb_user() for both user and kernel mappings unless 348 * flush_tlb_user() for both user and kernel mappings unless
349 * the Page Global Enable (PGE) feature bit is set. */ 349 * the Page Global Enable (PGE) feature bit is set. */
350 *dx |= 0x00002000; 350 *dx |= 0x00002000;
351 /* We also lie, and say we're family id 5. 6 or greater
352 * leads to a rdmsr in early_init_intel which we can't handle.
353 * Family ID is returned as bits 8-12 in ax. */
354 *ax &= 0xFFFFF0FF;
355 *ax |= 0x00000500;
351 break; 356 break;
352 case 0x80000000: 357 case 0x80000000:
353 /* Futureproof this a little: if they ask how much extended 358 /* Futureproof this a little: if they ask how much extended
@@ -594,19 +599,21 @@ static void __init lguest_init_IRQ(void)
594 /* Some systems map "vectors" to interrupts weirdly. Lguest has 599 /* Some systems map "vectors" to interrupts weirdly. Lguest has
595 * a straightforward 1 to 1 mapping, so force that here. */ 600 * a straightforward 1 to 1 mapping, so force that here. */
596 __get_cpu_var(vector_irq)[vector] = i; 601 __get_cpu_var(vector_irq)[vector] = i;
597 if (vector != SYSCALL_VECTOR) { 602 if (vector != SYSCALL_VECTOR)
598 set_intr_gate(vector, 603 set_intr_gate(vector, interrupt[i]);
599 interrupt[vector-FIRST_EXTERNAL_VECTOR]);
600 set_irq_chip_and_handler_name(i, &lguest_irq_controller,
601 handle_level_irq,
602 "level");
603 }
604 } 604 }
605 /* This call is required to set up for 4k stacks, where we have 605 /* This call is required to set up for 4k stacks, where we have
606 * separate stacks for hard and soft interrupts. */ 606 * separate stacks for hard and soft interrupts. */
607 irq_ctx_init(smp_processor_id()); 607 irq_ctx_init(smp_processor_id());
608} 608}
609 609
610void lguest_setup_irq(unsigned int irq)
611{
612 irq_to_desc_alloc_cpu(irq, 0);
613 set_irq_chip_and_handler_name(irq, &lguest_irq_controller,
614 handle_level_irq, "level");
615}
616
610/* 617/*
611 * Time. 618 * Time.
612 * 619 *
diff --git a/arch/x86/math-emu/fpu_aux.c b/arch/x86/math-emu/fpu_aux.c
index 491e737ce547..aa0987088774 100644
--- a/arch/x86/math-emu/fpu_aux.c
+++ b/arch/x86/math-emu/fpu_aux.c
@@ -30,20 +30,29 @@ static void fclex(void)
30} 30}
31 31
32/* Needs to be externally visible */ 32/* Needs to be externally visible */
33void finit(void) 33void finit_task(struct task_struct *tsk)
34{ 34{
35 control_word = 0x037f; 35 struct i387_soft_struct *soft = &tsk->thread.xstate->soft;
36 partial_status = 0; 36 struct address *oaddr, *iaddr;
37 top = 0; /* We don't keep top in the status word internally. */ 37 soft->cwd = 0x037f;
38 fpu_tag_word = 0xffff; 38 soft->swd = 0;
39 soft->ftop = 0; /* We don't keep top in the status word internally. */
40 soft->twd = 0xffff;
39 /* The behaviour is different from that detailed in 41 /* The behaviour is different from that detailed in
40 Section 15.1.6 of the Intel manual */ 42 Section 15.1.6 of the Intel manual */
41 operand_address.offset = 0; 43 oaddr = (struct address *)&soft->foo;
42 operand_address.selector = 0; 44 oaddr->offset = 0;
43 instruction_address.offset = 0; 45 oaddr->selector = 0;
44 instruction_address.selector = 0; 46 iaddr = (struct address *)&soft->fip;
45 instruction_address.opcode = 0; 47 iaddr->offset = 0;
46 no_ip_update = 1; 48 iaddr->selector = 0;
49 iaddr->opcode = 0;
50 soft->no_update = 1;
51}
52
53void finit(void)
54{
55 finit_task(current);
47} 56}
48 57
49/* 58/*
diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c
index 00f127c80b0e..d11745334a67 100644
--- a/arch/x86/mm/highmem_32.c
+++ b/arch/x86/mm/highmem_32.c
@@ -158,7 +158,6 @@ EXPORT_SYMBOL(kunmap);
158EXPORT_SYMBOL(kmap_atomic); 158EXPORT_SYMBOL(kmap_atomic);
159EXPORT_SYMBOL(kunmap_atomic); 159EXPORT_SYMBOL(kunmap_atomic);
160 160
161#ifdef CONFIG_NUMA
162void __init set_highmem_pages_init(void) 161void __init set_highmem_pages_init(void)
163{ 162{
164 struct zone *zone; 163 struct zone *zone;
@@ -182,11 +181,3 @@ void __init set_highmem_pages_init(void)
182 } 181 }
183 totalram_pages += totalhigh_pages; 182 totalram_pages += totalhigh_pages;
184} 183}
185#else
186void __init set_highmem_pages_init(void)
187{
188 add_highpages_with_active_regions(0, highstart_pfn, highend_pfn);
189
190 totalram_pages += totalhigh_pages;
191}
192#endif /* CONFIG_NUMA */
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index ce6a722587d8..15219e0d1243 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -1,8 +1,345 @@
1#include <linux/ioport.h>
1#include <linux/swap.h> 2#include <linux/swap.h>
3
2#include <asm/cacheflush.h> 4#include <asm/cacheflush.h>
5#include <asm/e820.h>
6#include <asm/init.h>
3#include <asm/page.h> 7#include <asm/page.h>
8#include <asm/page_types.h>
4#include <asm/sections.h> 9#include <asm/sections.h>
5#include <asm/system.h> 10#include <asm/system.h>
11#include <asm/tlbflush.h>
12
13unsigned long __initdata e820_table_start;
14unsigned long __meminitdata e820_table_end;
15unsigned long __meminitdata e820_table_top;
16
17int after_bootmem;
18
19int direct_gbpages
20#ifdef CONFIG_DIRECT_GBPAGES
21 = 1
22#endif
23;
24
25static void __init find_early_table_space(unsigned long end, int use_pse,
26 int use_gbpages)
27{
28 unsigned long puds, pmds, ptes, tables, start;
29
30 puds = (end + PUD_SIZE - 1) >> PUD_SHIFT;
31 tables = roundup(puds * sizeof(pud_t), PAGE_SIZE);
32
33 if (use_gbpages) {
34 unsigned long extra;
35
36 extra = end - ((end>>PUD_SHIFT) << PUD_SHIFT);
37 pmds = (extra + PMD_SIZE - 1) >> PMD_SHIFT;
38 } else
39 pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
40
41 tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE);
42
43 if (use_pse) {
44 unsigned long extra;
45
46 extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT);
47#ifdef CONFIG_X86_32
48 extra += PMD_SIZE;
49#endif
50 ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT;
51 } else
52 ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
53
54 tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE);
55
56#ifdef CONFIG_X86_32
57 /* for fixmap */
58 tables += roundup(__end_of_fixed_addresses * sizeof(pte_t), PAGE_SIZE);
59#endif
60
61 /*
62 * RED-PEN putting page tables only on node 0 could
63 * cause a hotspot and fill up ZONE_DMA. The page tables
64 * need roughly 0.5KB per GB.
65 */
66#ifdef CONFIG_X86_32
67 start = 0x7000;
68 e820_table_start = find_e820_area(start, max_pfn_mapped<<PAGE_SHIFT,
69 tables, PAGE_SIZE);
70#else /* CONFIG_X86_64 */
71 start = 0x8000;
72 e820_table_start = find_e820_area(start, end, tables, PAGE_SIZE);
73#endif
74 if (e820_table_start == -1UL)
75 panic("Cannot find space for the kernel page tables");
76
77 e820_table_start >>= PAGE_SHIFT;
78 e820_table_end = e820_table_start;
79 e820_table_top = e820_table_start + (tables >> PAGE_SHIFT);
80
81 printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n",
82 end, e820_table_start << PAGE_SHIFT, e820_table_top << PAGE_SHIFT);
83}
84
85struct map_range {
86 unsigned long start;
87 unsigned long end;
88 unsigned page_size_mask;
89};
90
91#ifdef CONFIG_X86_32
92#define NR_RANGE_MR 3
93#else /* CONFIG_X86_64 */
94#define NR_RANGE_MR 5
95#endif
96
97static int save_mr(struct map_range *mr, int nr_range,
98 unsigned long start_pfn, unsigned long end_pfn,
99 unsigned long page_size_mask)
100{
101 if (start_pfn < end_pfn) {
102 if (nr_range >= NR_RANGE_MR)
103 panic("run out of range for init_memory_mapping\n");
104 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
105 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
106 mr[nr_range].page_size_mask = page_size_mask;
107 nr_range++;
108 }
109
110 return nr_range;
111}
112
113#ifdef CONFIG_X86_64
114static void __init init_gbpages(void)
115{
116 if (direct_gbpages && cpu_has_gbpages)
117 printk(KERN_INFO "Using GB pages for direct mapping\n");
118 else
119 direct_gbpages = 0;
120}
121#else
122static inline void init_gbpages(void)
123{
124}
125#endif
126
127/*
128 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
129 * This runs before bootmem is initialized and gets pages directly from
130 * the physical memory. To access them they are temporarily mapped.
131 */
132unsigned long __init_refok init_memory_mapping(unsigned long start,
133 unsigned long end)
134{
135 unsigned long page_size_mask = 0;
136 unsigned long start_pfn, end_pfn;
137 unsigned long ret = 0;
138 unsigned long pos;
139
140 struct map_range mr[NR_RANGE_MR];
141 int nr_range, i;
142 int use_pse, use_gbpages;
143
144 printk(KERN_INFO "init_memory_mapping: %016lx-%016lx\n", start, end);
145
146 if (!after_bootmem)
147 init_gbpages();
148
149#ifdef CONFIG_DEBUG_PAGEALLOC
150 /*
151 * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages.
152 * This will simplify cpa(), which otherwise needs to support splitting
153 * large pages into small in interrupt context, etc.
154 */
155 use_pse = use_gbpages = 0;
156#else
157 use_pse = cpu_has_pse;
158 use_gbpages = direct_gbpages;
159#endif
160
161#ifdef CONFIG_X86_32
162#ifdef CONFIG_X86_PAE
163 set_nx();
164 if (nx_enabled)
165 printk(KERN_INFO "NX (Execute Disable) protection: active\n");
166#endif
167
168 /* Enable PSE if available */
169 if (cpu_has_pse)
170 set_in_cr4(X86_CR4_PSE);
171
172 /* Enable PGE if available */
173 if (cpu_has_pge) {
174 set_in_cr4(X86_CR4_PGE);
175 __supported_pte_mask |= _PAGE_GLOBAL;
176 }
177#endif
178
179 if (use_gbpages)
180 page_size_mask |= 1 << PG_LEVEL_1G;
181 if (use_pse)
182 page_size_mask |= 1 << PG_LEVEL_2M;
183
184 memset(mr, 0, sizeof(mr));
185 nr_range = 0;
186
187 /* head if not big page alignment ? */
188 start_pfn = start >> PAGE_SHIFT;
189 pos = start_pfn << PAGE_SHIFT;
190#ifdef CONFIG_X86_32
191 /*
192 * Don't use a large page for the first 2/4MB of memory
193 * because there are often fixed size MTRRs in there
194 * and overlapping MTRRs into large pages can cause
195 * slowdowns.
196 */
197 if (pos == 0)
198 end_pfn = 1<<(PMD_SHIFT - PAGE_SHIFT);
199 else
200 end_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT)
201 << (PMD_SHIFT - PAGE_SHIFT);
202#else /* CONFIG_X86_64 */
203 end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT)
204 << (PMD_SHIFT - PAGE_SHIFT);
205#endif
206 if (end_pfn > (end >> PAGE_SHIFT))
207 end_pfn = end >> PAGE_SHIFT;
208 if (start_pfn < end_pfn) {
209 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
210 pos = end_pfn << PAGE_SHIFT;
211 }
212
213 /* big page (2M) range */
214 start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT)
215 << (PMD_SHIFT - PAGE_SHIFT);
216#ifdef CONFIG_X86_32
217 end_pfn = (end>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT);
218#else /* CONFIG_X86_64 */
219 end_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT)
220 << (PUD_SHIFT - PAGE_SHIFT);
221 if (end_pfn > ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT)))
222 end_pfn = ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT));
223#endif
224
225 if (start_pfn < end_pfn) {
226 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
227 page_size_mask & (1<<PG_LEVEL_2M));
228 pos = end_pfn << PAGE_SHIFT;
229 }
230
231#ifdef CONFIG_X86_64
232 /* big page (1G) range */
233 start_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT)
234 << (PUD_SHIFT - PAGE_SHIFT);
235 end_pfn = (end >> PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT);
236 if (start_pfn < end_pfn) {
237 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
238 page_size_mask &
239 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
240 pos = end_pfn << PAGE_SHIFT;
241 }
242
243 /* tail is not big page (1G) alignment */
244 start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT)
245 << (PMD_SHIFT - PAGE_SHIFT);
246 end_pfn = (end >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT);
247 if (start_pfn < end_pfn) {
248 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
249 page_size_mask & (1<<PG_LEVEL_2M));
250 pos = end_pfn << PAGE_SHIFT;
251 }
252#endif
253
254 /* tail is not big page (2M) alignment */
255 start_pfn = pos>>PAGE_SHIFT;
256 end_pfn = end>>PAGE_SHIFT;
257 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
258
259 /* try to merge same page size and continuous */
260 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
261 unsigned long old_start;
262 if (mr[i].end != mr[i+1].start ||
263 mr[i].page_size_mask != mr[i+1].page_size_mask)
264 continue;
265 /* move it */
266 old_start = mr[i].start;
267 memmove(&mr[i], &mr[i+1],
268 (nr_range - 1 - i) * sizeof(struct map_range));
269 mr[i--].start = old_start;
270 nr_range--;
271 }
272
273 for (i = 0; i < nr_range; i++)
274 printk(KERN_DEBUG " %010lx - %010lx page %s\n",
275 mr[i].start, mr[i].end,
276 (mr[i].page_size_mask & (1<<PG_LEVEL_1G))?"1G":(
277 (mr[i].page_size_mask & (1<<PG_LEVEL_2M))?"2M":"4k"));
278
279 /*
280 * Find space for the kernel direct mapping tables.
281 *
282 * Later we should allocate these tables in the local node of the
283 * memory mapped. Unfortunately this is done currently before the
284 * nodes are discovered.
285 */
286 if (!after_bootmem)
287 find_early_table_space(end, use_pse, use_gbpages);
288
289#ifdef CONFIG_X86_32
290 for (i = 0; i < nr_range; i++)
291 kernel_physical_mapping_init(mr[i].start, mr[i].end,
292 mr[i].page_size_mask);
293 ret = end;
294#else /* CONFIG_X86_64 */
295 for (i = 0; i < nr_range; i++)
296 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
297 mr[i].page_size_mask);
298#endif
299
300#ifdef CONFIG_X86_32
301 early_ioremap_page_table_range_init();
302
303 load_cr3(swapper_pg_dir);
304#endif
305
306#ifdef CONFIG_X86_64
307 if (!after_bootmem)
308 mmu_cr4_features = read_cr4();
309#endif
310 __flush_tlb_all();
311
312 if (!after_bootmem && e820_table_end > e820_table_start)
313 reserve_early(e820_table_start << PAGE_SHIFT,
314 e820_table_end << PAGE_SHIFT, "PGTABLE");
315
316 if (!after_bootmem)
317 early_memtest(start, end);
318
319 return ret >> PAGE_SHIFT;
320}
321
322
323/*
324 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
325 * is valid. The argument is a physical page number.
326 *
327 *
328 * On x86, access has to be given to the first megabyte of ram because that area
329 * contains bios code and data regions used by X and dosemu and similar apps.
330 * Access has to be given to non-kernel-ram areas as well, these contain the PCI
331 * mmio resources as well as potential bios/acpi data regions.
332 */
333int devmem_is_allowed(unsigned long pagenr)
334{
335 if (pagenr <= 256)
336 return 1;
337 if (iomem_is_exclusive(pagenr << PAGE_SHIFT))
338 return 0;
339 if (!page_is_ram(pagenr))
340 return 1;
341 return 0;
342}
6 343
7void free_init_pages(char *what, unsigned long begin, unsigned long end) 344void free_init_pages(char *what, unsigned long begin, unsigned long end)
8{ 345{
@@ -47,3 +384,10 @@ void free_initmem(void)
47 (unsigned long)(&__init_begin), 384 (unsigned long)(&__init_begin),
48 (unsigned long)(&__init_end)); 385 (unsigned long)(&__init_end));
49} 386}
387
388#ifdef CONFIG_BLK_DEV_INITRD
389void free_initrd_mem(unsigned long start, unsigned long end)
390{
391 free_init_pages("initrd memory", start, end);
392}
393#endif
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 0b087dcd2c18..db81e9a8556b 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -49,6 +49,7 @@
49#include <asm/paravirt.h> 49#include <asm/paravirt.h>
50#include <asm/setup.h> 50#include <asm/setup.h>
51#include <asm/cacheflush.h> 51#include <asm/cacheflush.h>
52#include <asm/init.h>
52 53
53unsigned long max_low_pfn_mapped; 54unsigned long max_low_pfn_mapped;
54unsigned long max_pfn_mapped; 55unsigned long max_pfn_mapped;
@@ -58,19 +59,14 @@ unsigned long highstart_pfn, highend_pfn;
58 59
59static noinline int do_test_wp_bit(void); 60static noinline int do_test_wp_bit(void);
60 61
61 62bool __read_mostly __vmalloc_start_set = false;
62static unsigned long __initdata table_start;
63static unsigned long __meminitdata table_end;
64static unsigned long __meminitdata table_top;
65
66static int __initdata after_init_bootmem;
67 63
68static __init void *alloc_low_page(void) 64static __init void *alloc_low_page(void)
69{ 65{
70 unsigned long pfn = table_end++; 66 unsigned long pfn = e820_table_end++;
71 void *adr; 67 void *adr;
72 68
73 if (pfn >= table_top) 69 if (pfn >= e820_table_top)
74 panic("alloc_low_page: ran out of memory"); 70 panic("alloc_low_page: ran out of memory");
75 71
76 adr = __va(pfn * PAGE_SIZE); 72 adr = __va(pfn * PAGE_SIZE);
@@ -90,7 +86,7 @@ static pmd_t * __init one_md_table_init(pgd_t *pgd)
90 86
91#ifdef CONFIG_X86_PAE 87#ifdef CONFIG_X86_PAE
92 if (!(pgd_val(*pgd) & _PAGE_PRESENT)) { 88 if (!(pgd_val(*pgd) & _PAGE_PRESENT)) {
93 if (after_init_bootmem) 89 if (after_bootmem)
94 pmd_table = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE); 90 pmd_table = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE);
95 else 91 else
96 pmd_table = (pmd_t *)alloc_low_page(); 92 pmd_table = (pmd_t *)alloc_low_page();
@@ -117,7 +113,7 @@ static pte_t * __init one_page_table_init(pmd_t *pmd)
117 if (!(pmd_val(*pmd) & _PAGE_PRESENT)) { 113 if (!(pmd_val(*pmd) & _PAGE_PRESENT)) {
118 pte_t *page_table = NULL; 114 pte_t *page_table = NULL;
119 115
120 if (after_init_bootmem) { 116 if (after_bootmem) {
121#ifdef CONFIG_DEBUG_PAGEALLOC 117#ifdef CONFIG_DEBUG_PAGEALLOC
122 page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE); 118 page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE);
123#endif 119#endif
@@ -135,6 +131,23 @@ static pte_t * __init one_page_table_init(pmd_t *pmd)
135 return pte_offset_kernel(pmd, 0); 131 return pte_offset_kernel(pmd, 0);
136} 132}
137 133
134pmd_t * __init populate_extra_pmd(unsigned long vaddr)
135{
136 int pgd_idx = pgd_index(vaddr);
137 int pmd_idx = pmd_index(vaddr);
138
139 return one_md_table_init(swapper_pg_dir + pgd_idx) + pmd_idx;
140}
141
142pte_t * __init populate_extra_pte(unsigned long vaddr)
143{
144 int pte_idx = pte_index(vaddr);
145 pmd_t *pmd;
146
147 pmd = populate_extra_pmd(vaddr);
148 return one_page_table_init(pmd) + pte_idx;
149}
150
138static pte_t *__init page_table_kmap_check(pte_t *pte, pmd_t *pmd, 151static pte_t *__init page_table_kmap_check(pte_t *pte, pmd_t *pmd,
139 unsigned long vaddr, pte_t *lastpte) 152 unsigned long vaddr, pte_t *lastpte)
140{ 153{
@@ -151,12 +164,12 @@ static pte_t *__init page_table_kmap_check(pte_t *pte, pmd_t *pmd,
151 if (pmd_idx_kmap_begin != pmd_idx_kmap_end 164 if (pmd_idx_kmap_begin != pmd_idx_kmap_end
152 && (vaddr >> PMD_SHIFT) >= pmd_idx_kmap_begin 165 && (vaddr >> PMD_SHIFT) >= pmd_idx_kmap_begin
153 && (vaddr >> PMD_SHIFT) <= pmd_idx_kmap_end 166 && (vaddr >> PMD_SHIFT) <= pmd_idx_kmap_end
154 && ((__pa(pte) >> PAGE_SHIFT) < table_start 167 && ((__pa(pte) >> PAGE_SHIFT) < e820_table_start
155 || (__pa(pte) >> PAGE_SHIFT) >= table_end)) { 168 || (__pa(pte) >> PAGE_SHIFT) >= e820_table_end)) {
156 pte_t *newpte; 169 pte_t *newpte;
157 int i; 170 int i;
158 171
159 BUG_ON(after_init_bootmem); 172 BUG_ON(after_bootmem);
160 newpte = alloc_low_page(); 173 newpte = alloc_low_page();
161 for (i = 0; i < PTRS_PER_PTE; i++) 174 for (i = 0; i < PTRS_PER_PTE; i++)
162 set_pte(newpte + i, pte[i]); 175 set_pte(newpte + i, pte[i]);
@@ -225,11 +238,14 @@ static inline int is_kernel_text(unsigned long addr)
225 * of max_low_pfn pages, by creating page tables starting from address 238 * of max_low_pfn pages, by creating page tables starting from address
226 * PAGE_OFFSET: 239 * PAGE_OFFSET:
227 */ 240 */
228static void __init kernel_physical_mapping_init(pgd_t *pgd_base, 241unsigned long __init
229 unsigned long start_pfn, 242kernel_physical_mapping_init(unsigned long start,
230 unsigned long end_pfn, 243 unsigned long end,
231 int use_pse) 244 unsigned long page_size_mask)
232{ 245{
246 int use_pse = page_size_mask == (1<<PG_LEVEL_2M);
247 unsigned long start_pfn, end_pfn;
248 pgd_t *pgd_base = swapper_pg_dir;
233 int pgd_idx, pmd_idx, pte_ofs; 249 int pgd_idx, pmd_idx, pte_ofs;
234 unsigned long pfn; 250 unsigned long pfn;
235 pgd_t *pgd; 251 pgd_t *pgd;
@@ -238,6 +254,9 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base,
238 unsigned pages_2m, pages_4k; 254 unsigned pages_2m, pages_4k;
239 int mapping_iter; 255 int mapping_iter;
240 256
257 start_pfn = start >> PAGE_SHIFT;
258 end_pfn = end >> PAGE_SHIFT;
259
241 /* 260 /*
242 * First iteration will setup identity mapping using large/small pages 261 * First iteration will setup identity mapping using large/small pages
243 * based on use_pse, with other attributes same as set by 262 * based on use_pse, with other attributes same as set by
@@ -352,26 +371,6 @@ repeat:
352 mapping_iter = 2; 371 mapping_iter = 2;
353 goto repeat; 372 goto repeat;
354 } 373 }
355}
356
357/*
358 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
359 * is valid. The argument is a physical page number.
360 *
361 *
362 * On x86, access has to be given to the first megabyte of ram because that area
363 * contains bios code and data regions used by X and dosemu and similar apps.
364 * Access has to be given to non-kernel-ram areas as well, these contain the PCI
365 * mmio resources as well as potential bios/acpi data regions.
366 */
367int devmem_is_allowed(unsigned long pagenr)
368{
369 if (pagenr <= 256)
370 return 1;
371 if (iomem_is_exclusive(pagenr << PAGE_SHIFT))
372 return 0;
373 if (!page_is_ram(pagenr))
374 return 1;
375 return 0; 374 return 0;
376} 375}
377 376
@@ -528,8 +527,9 @@ void __init native_pagetable_setup_done(pgd_t *base)
528 * be partially populated, and so it avoids stomping on any existing 527 * be partially populated, and so it avoids stomping on any existing
529 * mappings. 528 * mappings.
530 */ 529 */
531static void __init early_ioremap_page_table_range_init(pgd_t *pgd_base) 530void __init early_ioremap_page_table_range_init(void)
532{ 531{
532 pgd_t *pgd_base = swapper_pg_dir;
533 unsigned long vaddr, end; 533 unsigned long vaddr, end;
534 534
535 /* 535 /*
@@ -624,7 +624,7 @@ static int __init noexec_setup(char *str)
624} 624}
625early_param("noexec", noexec_setup); 625early_param("noexec", noexec_setup);
626 626
627static void __init set_nx(void) 627void __init set_nx(void)
628{ 628{
629 unsigned int v[4], l, h; 629 unsigned int v[4], l, h;
630 630
@@ -776,6 +776,8 @@ void __init initmem_init(unsigned long start_pfn,
776#ifdef CONFIG_FLATMEM 776#ifdef CONFIG_FLATMEM
777 max_mapnr = num_physpages; 777 max_mapnr = num_physpages;
778#endif 778#endif
779 __vmalloc_start_set = true;
780
779 printk(KERN_NOTICE "%ldMB LOWMEM available.\n", 781 printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
780 pages_to_mb(max_low_pfn)); 782 pages_to_mb(max_low_pfn));
781 783
@@ -797,176 +799,66 @@ static void __init zone_sizes_init(void)
797 free_area_init_nodes(max_zone_pfns); 799 free_area_init_nodes(max_zone_pfns);
798} 800}
799 801
802static unsigned long __init setup_node_bootmem(int nodeid,
803 unsigned long start_pfn,
804 unsigned long end_pfn,
805 unsigned long bootmap)
806{
807 unsigned long bootmap_size;
808
809 /* don't touch min_low_pfn */
810 bootmap_size = init_bootmem_node(NODE_DATA(nodeid),
811 bootmap >> PAGE_SHIFT,
812 start_pfn, end_pfn);
813 printk(KERN_INFO " node %d low ram: %08lx - %08lx\n",
814 nodeid, start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
815 printk(KERN_INFO " node %d bootmap %08lx - %08lx\n",
816 nodeid, bootmap, bootmap + bootmap_size);
817 free_bootmem_with_active_regions(nodeid, end_pfn);
818 early_res_to_bootmem(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
819
820 return bootmap + bootmap_size;
821}
822
800void __init setup_bootmem_allocator(void) 823void __init setup_bootmem_allocator(void)
801{ 824{
802 int i; 825 int nodeid;
803 unsigned long bootmap_size, bootmap; 826 unsigned long bootmap_size, bootmap;
804 /* 827 /*
805 * Initialize the boot-time allocator (with low memory only): 828 * Initialize the boot-time allocator (with low memory only):
806 */ 829 */
807 bootmap_size = bootmem_bootmap_pages(max_low_pfn)<<PAGE_SHIFT; 830 bootmap_size = bootmem_bootmap_pages(max_low_pfn)<<PAGE_SHIFT;
808 bootmap = find_e820_area(min_low_pfn<<PAGE_SHIFT, 831 bootmap = find_e820_area(0, max_pfn_mapped<<PAGE_SHIFT, bootmap_size,
809 max_pfn_mapped<<PAGE_SHIFT, bootmap_size,
810 PAGE_SIZE); 832 PAGE_SIZE);
811 if (bootmap == -1L) 833 if (bootmap == -1L)
812 panic("Cannot find bootmem map of size %ld\n", bootmap_size); 834 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
813 reserve_early(bootmap, bootmap + bootmap_size, "BOOTMAP"); 835 reserve_early(bootmap, bootmap + bootmap_size, "BOOTMAP");
814 836
815 /* don't touch min_low_pfn */
816 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap >> PAGE_SHIFT,
817 min_low_pfn, max_low_pfn);
818 printk(KERN_INFO " mapped low ram: 0 - %08lx\n", 837 printk(KERN_INFO " mapped low ram: 0 - %08lx\n",
819 max_pfn_mapped<<PAGE_SHIFT); 838 max_pfn_mapped<<PAGE_SHIFT);
820 printk(KERN_INFO " low ram: %08lx - %08lx\n", 839 printk(KERN_INFO " low ram: 0 - %08lx\n", max_low_pfn<<PAGE_SHIFT);
821 min_low_pfn<<PAGE_SHIFT, max_low_pfn<<PAGE_SHIFT);
822 printk(KERN_INFO " bootmap %08lx - %08lx\n",
823 bootmap, bootmap + bootmap_size);
824 for_each_online_node(i)
825 free_bootmem_with_active_regions(i, max_low_pfn);
826 early_res_to_bootmem(0, max_low_pfn<<PAGE_SHIFT);
827
828 after_init_bootmem = 1;
829}
830
831static void __init find_early_table_space(unsigned long end, int use_pse)
832{
833 unsigned long puds, pmds, ptes, tables, start;
834
835 puds = (end + PUD_SIZE - 1) >> PUD_SHIFT;
836 tables = roundup(puds * sizeof(pud_t), PAGE_SIZE);
837
838 pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
839 tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE);
840
841 if (use_pse) {
842 unsigned long extra;
843 840
844 extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT); 841 for_each_online_node(nodeid) {
845 extra += PMD_SIZE; 842 unsigned long start_pfn, end_pfn;
846 ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT;
847 } else
848 ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
849 843
850 tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE); 844#ifdef CONFIG_NEED_MULTIPLE_NODES
851 845 start_pfn = node_start_pfn[nodeid];
852 /* for fixmap */ 846 end_pfn = node_end_pfn[nodeid];
853 tables += roundup(__end_of_fixed_addresses * sizeof(pte_t), PAGE_SIZE); 847 if (start_pfn > max_low_pfn)
854 848 continue;
855 /* 849 if (end_pfn > max_low_pfn)
856 * RED-PEN putting page tables only on node 0 could 850 end_pfn = max_low_pfn;
857 * cause a hotspot and fill up ZONE_DMA. The page tables
858 * need roughly 0.5KB per GB.
859 */
860 start = 0x7000;
861 table_start = find_e820_area(start, max_pfn_mapped<<PAGE_SHIFT,
862 tables, PAGE_SIZE);
863 if (table_start == -1UL)
864 panic("Cannot find space for the kernel page tables");
865
866 table_start >>= PAGE_SHIFT;
867 table_end = table_start;
868 table_top = table_start + (tables>>PAGE_SHIFT);
869
870 printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n",
871 end, table_start << PAGE_SHIFT,
872 (table_start << PAGE_SHIFT) + tables);
873}
874
875unsigned long __init_refok init_memory_mapping(unsigned long start,
876 unsigned long end)
877{
878 pgd_t *pgd_base = swapper_pg_dir;
879 unsigned long start_pfn, end_pfn;
880 unsigned long big_page_start;
881#ifdef CONFIG_DEBUG_PAGEALLOC
882 /*
883 * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages.
884 * This will simplify cpa(), which otherwise needs to support splitting
885 * large pages into small in interrupt context, etc.
886 */
887 int use_pse = 0;
888#else 851#else
889 int use_pse = cpu_has_pse; 852 start_pfn = 0;
890#endif 853 end_pfn = max_low_pfn;
891
892 /*
893 * Find space for the kernel direct mapping tables.
894 */
895 if (!after_init_bootmem)
896 find_early_table_space(end, use_pse);
897
898#ifdef CONFIG_X86_PAE
899 set_nx();
900 if (nx_enabled)
901 printk(KERN_INFO "NX (Execute Disable) protection: active\n");
902#endif 854#endif
903 855 bootmap = setup_node_bootmem(nodeid, start_pfn, end_pfn,
904 /* Enable PSE if available */ 856 bootmap);
905 if (cpu_has_pse)
906 set_in_cr4(X86_CR4_PSE);
907
908 /* Enable PGE if available */
909 if (cpu_has_pge) {
910 set_in_cr4(X86_CR4_PGE);
911 __supported_pte_mask |= _PAGE_GLOBAL;
912 }
913
914 /*
915 * Don't use a large page for the first 2/4MB of memory
916 * because there are often fixed size MTRRs in there
917 * and overlapping MTRRs into large pages can cause
918 * slowdowns.
919 */
920 big_page_start = PMD_SIZE;
921
922 if (start < big_page_start) {
923 start_pfn = start >> PAGE_SHIFT;
924 end_pfn = min(big_page_start>>PAGE_SHIFT, end>>PAGE_SHIFT);
925 } else {
926 /* head is not big page alignment ? */
927 start_pfn = start >> PAGE_SHIFT;
928 end_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT)
929 << (PMD_SHIFT - PAGE_SHIFT);
930 }
931 if (start_pfn < end_pfn)
932 kernel_physical_mapping_init(pgd_base, start_pfn, end_pfn, 0);
933
934 /* big page range */
935 start_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT)
936 << (PMD_SHIFT - PAGE_SHIFT);
937 if (start_pfn < (big_page_start >> PAGE_SHIFT))
938 start_pfn = big_page_start >> PAGE_SHIFT;
939 end_pfn = (end>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT);
940 if (start_pfn < end_pfn)
941 kernel_physical_mapping_init(pgd_base, start_pfn, end_pfn,
942 use_pse);
943
944 /* tail is not big page alignment ? */
945 start_pfn = end_pfn;
946 if (start_pfn > (big_page_start>>PAGE_SHIFT)) {
947 end_pfn = end >> PAGE_SHIFT;
948 if (start_pfn < end_pfn)
949 kernel_physical_mapping_init(pgd_base, start_pfn,
950 end_pfn, 0);
951 } 857 }
952 858
953 early_ioremap_page_table_range_init(pgd_base); 859 after_bootmem = 1;
954
955 load_cr3(swapper_pg_dir);
956
957 __flush_tlb_all();
958
959 if (!after_init_bootmem)
960 reserve_early(table_start << PAGE_SHIFT,
961 table_end << PAGE_SHIFT, "PGTABLE");
962
963 if (!after_init_bootmem)
964 early_memtest(start, end);
965
966 return end >> PAGE_SHIFT;
967} 860}
968 861
969
970/* 862/*
971 * paging_init() sets up the page tables - note that the first 8MB are 863 * paging_init() sets up the page tables - note that the first 8MB are
972 * already mapped by head.S. 864 * already mapped by head.S.
@@ -1200,13 +1092,6 @@ void mark_rodata_ro(void)
1200} 1092}
1201#endif 1093#endif
1202 1094
1203#ifdef CONFIG_BLK_DEV_INITRD
1204void free_initrd_mem(unsigned long start, unsigned long end)
1205{
1206 free_init_pages("initrd memory", start, end);
1207}
1208#endif
1209
1210int __init reserve_bootmem_generic(unsigned long phys, unsigned long len, 1095int __init reserve_bootmem_generic(unsigned long phys, unsigned long len,
1211 int flags) 1096 int flags)
1212{ 1097{
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 724e537432e7..54efa57d1c03 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -48,6 +48,7 @@
48#include <asm/kdebug.h> 48#include <asm/kdebug.h>
49#include <asm/numa.h> 49#include <asm/numa.h>
50#include <asm/cacheflush.h> 50#include <asm/cacheflush.h>
51#include <asm/init.h>
51 52
52/* 53/*
53 * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries. 54 * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries.
@@ -61,12 +62,6 @@ static unsigned long dma_reserve __initdata;
61 62
62DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 63DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
63 64
64int direct_gbpages
65#ifdef CONFIG_DIRECT_GBPAGES
66 = 1
67#endif
68;
69
70static int __init parse_direct_gbpages_off(char *arg) 65static int __init parse_direct_gbpages_off(char *arg)
71{ 66{
72 direct_gbpages = 0; 67 direct_gbpages = 0;
@@ -87,12 +82,10 @@ early_param("gbpages", parse_direct_gbpages_on);
87 * around without checking the pgd every time. 82 * around without checking the pgd every time.
88 */ 83 */
89 84
90int after_bootmem;
91
92pteval_t __supported_pte_mask __read_mostly = ~_PAGE_IOMAP; 85pteval_t __supported_pte_mask __read_mostly = ~_PAGE_IOMAP;
93EXPORT_SYMBOL_GPL(__supported_pte_mask); 86EXPORT_SYMBOL_GPL(__supported_pte_mask);
94 87
95static int do_not_nx __cpuinitdata; 88static int disable_nx __cpuinitdata;
96 89
97/* 90/*
98 * noexec=on|off 91 * noexec=on|off
@@ -107,9 +100,9 @@ static int __init nonx_setup(char *str)
107 return -EINVAL; 100 return -EINVAL;
108 if (!strncmp(str, "on", 2)) { 101 if (!strncmp(str, "on", 2)) {
109 __supported_pte_mask |= _PAGE_NX; 102 __supported_pte_mask |= _PAGE_NX;
110 do_not_nx = 0; 103 disable_nx = 0;
111 } else if (!strncmp(str, "off", 3)) { 104 } else if (!strncmp(str, "off", 3)) {
112 do_not_nx = 1; 105 disable_nx = 1;
113 __supported_pte_mask &= ~_PAGE_NX; 106 __supported_pte_mask &= ~_PAGE_NX;
114 } 107 }
115 return 0; 108 return 0;
@@ -121,7 +114,7 @@ void __cpuinit check_efer(void)
121 unsigned long efer; 114 unsigned long efer;
122 115
123 rdmsrl(MSR_EFER, efer); 116 rdmsrl(MSR_EFER, efer);
124 if (!(efer & EFER_NX) || do_not_nx) 117 if (!(efer & EFER_NX) || disable_nx)
125 __supported_pte_mask &= ~_PAGE_NX; 118 __supported_pte_mask &= ~_PAGE_NX;
126} 119}
127 120
@@ -168,34 +161,51 @@ static __ref void *spp_getpage(void)
168 return ptr; 161 return ptr;
169} 162}
170 163
171void 164static pud_t *fill_pud(pgd_t *pgd, unsigned long vaddr)
172set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte)
173{ 165{
174 pud_t *pud; 166 if (pgd_none(*pgd)) {
175 pmd_t *pmd; 167 pud_t *pud = (pud_t *)spp_getpage();
176 pte_t *pte; 168 pgd_populate(&init_mm, pgd, pud);
169 if (pud != pud_offset(pgd, 0))
170 printk(KERN_ERR "PAGETABLE BUG #00! %p <-> %p\n",
171 pud, pud_offset(pgd, 0));
172 }
173 return pud_offset(pgd, vaddr);
174}
177 175
178 pud = pud_page + pud_index(vaddr); 176static pmd_t *fill_pmd(pud_t *pud, unsigned long vaddr)
177{
179 if (pud_none(*pud)) { 178 if (pud_none(*pud)) {
180 pmd = (pmd_t *) spp_getpage(); 179 pmd_t *pmd = (pmd_t *) spp_getpage();
181 pud_populate(&init_mm, pud, pmd); 180 pud_populate(&init_mm, pud, pmd);
182 if (pmd != pmd_offset(pud, 0)) { 181 if (pmd != pmd_offset(pud, 0))
183 printk(KERN_ERR "PAGETABLE BUG #01! %p <-> %p\n", 182 printk(KERN_ERR "PAGETABLE BUG #01! %p <-> %p\n",
184 pmd, pmd_offset(pud, 0)); 183 pmd, pmd_offset(pud, 0));
185 return;
186 }
187 } 184 }
188 pmd = pmd_offset(pud, vaddr); 185 return pmd_offset(pud, vaddr);
186}
187
188static pte_t *fill_pte(pmd_t *pmd, unsigned long vaddr)
189{
189 if (pmd_none(*pmd)) { 190 if (pmd_none(*pmd)) {
190 pte = (pte_t *) spp_getpage(); 191 pte_t *pte = (pte_t *) spp_getpage();
191 pmd_populate_kernel(&init_mm, pmd, pte); 192 pmd_populate_kernel(&init_mm, pmd, pte);
192 if (pte != pte_offset_kernel(pmd, 0)) { 193 if (pte != pte_offset_kernel(pmd, 0))
193 printk(KERN_ERR "PAGETABLE BUG #02!\n"); 194 printk(KERN_ERR "PAGETABLE BUG #02!\n");
194 return;
195 }
196 } 195 }
196 return pte_offset_kernel(pmd, vaddr);
197}
198
199void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte)
200{
201 pud_t *pud;
202 pmd_t *pmd;
203 pte_t *pte;
204
205 pud = pud_page + pud_index(vaddr);
206 pmd = fill_pmd(pud, vaddr);
207 pte = fill_pte(pmd, vaddr);
197 208
198 pte = pte_offset_kernel(pmd, vaddr);
199 set_pte(pte, new_pte); 209 set_pte(pte, new_pte);
200 210
201 /* 211 /*
@@ -205,8 +215,7 @@ set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte)
205 __flush_tlb_one(vaddr); 215 __flush_tlb_one(vaddr);
206} 216}
207 217
208void 218void set_pte_vaddr(unsigned long vaddr, pte_t pteval)
209set_pte_vaddr(unsigned long vaddr, pte_t pteval)
210{ 219{
211 pgd_t *pgd; 220 pgd_t *pgd;
212 pud_t *pud_page; 221 pud_t *pud_page;
@@ -223,6 +232,24 @@ set_pte_vaddr(unsigned long vaddr, pte_t pteval)
223 set_pte_vaddr_pud(pud_page, vaddr, pteval); 232 set_pte_vaddr_pud(pud_page, vaddr, pteval);
224} 233}
225 234
235pmd_t * __init populate_extra_pmd(unsigned long vaddr)
236{
237 pgd_t *pgd;
238 pud_t *pud;
239
240 pgd = pgd_offset_k(vaddr);
241 pud = fill_pud(pgd, vaddr);
242 return fill_pmd(pud, vaddr);
243}
244
245pte_t * __init populate_extra_pte(unsigned long vaddr)
246{
247 pmd_t *pmd;
248
249 pmd = populate_extra_pmd(vaddr);
250 return fill_pte(pmd, vaddr);
251}
252
226/* 253/*
227 * Create large page table mappings for a range of physical addresses. 254 * Create large page table mappings for a range of physical addresses.
228 */ 255 */
@@ -291,13 +318,9 @@ void __init cleanup_highmap(void)
291 } 318 }
292} 319}
293 320
294static unsigned long __initdata table_start;
295static unsigned long __meminitdata table_end;
296static unsigned long __meminitdata table_top;
297
298static __ref void *alloc_low_page(unsigned long *phys) 321static __ref void *alloc_low_page(unsigned long *phys)
299{ 322{
300 unsigned long pfn = table_end++; 323 unsigned long pfn = e820_table_end++;
301 void *adr; 324 void *adr;
302 325
303 if (after_bootmem) { 326 if (after_bootmem) {
@@ -307,7 +330,7 @@ static __ref void *alloc_low_page(unsigned long *phys)
307 return adr; 330 return adr;
308 } 331 }
309 332
310 if (pfn >= table_top) 333 if (pfn >= e820_table_top)
311 panic("alloc_low_page: ran out of memory"); 334 panic("alloc_low_page: ran out of memory");
312 335
313 adr = early_memremap(pfn * PAGE_SIZE, PAGE_SIZE); 336 adr = early_memremap(pfn * PAGE_SIZE, PAGE_SIZE);
@@ -547,58 +570,10 @@ phys_pud_update(pgd_t *pgd, unsigned long addr, unsigned long end,
547 return phys_pud_init(pud, addr, end, page_size_mask); 570 return phys_pud_init(pud, addr, end, page_size_mask);
548} 571}
549 572
550static void __init find_early_table_space(unsigned long end, int use_pse, 573unsigned long __init
551 int use_gbpages) 574kernel_physical_mapping_init(unsigned long start,
552{ 575 unsigned long end,
553 unsigned long puds, pmds, ptes, tables, start; 576 unsigned long page_size_mask)
554
555 puds = (end + PUD_SIZE - 1) >> PUD_SHIFT;
556 tables = roundup(puds * sizeof(pud_t), PAGE_SIZE);
557 if (use_gbpages) {
558 unsigned long extra;
559 extra = end - ((end>>PUD_SHIFT) << PUD_SHIFT);
560 pmds = (extra + PMD_SIZE - 1) >> PMD_SHIFT;
561 } else
562 pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
563 tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE);
564
565 if (use_pse) {
566 unsigned long extra;
567 extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT);
568 ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT;
569 } else
570 ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
571 tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE);
572
573 /*
574 * RED-PEN putting page tables only on node 0 could
575 * cause a hotspot and fill up ZONE_DMA. The page tables
576 * need roughly 0.5KB per GB.
577 */
578 start = 0x8000;
579 table_start = find_e820_area(start, end, tables, PAGE_SIZE);
580 if (table_start == -1UL)
581 panic("Cannot find space for the kernel page tables");
582
583 table_start >>= PAGE_SHIFT;
584 table_end = table_start;
585 table_top = table_start + (tables >> PAGE_SHIFT);
586
587 printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n",
588 end, table_start << PAGE_SHIFT, table_top << PAGE_SHIFT);
589}
590
591static void __init init_gbpages(void)
592{
593 if (direct_gbpages && cpu_has_gbpages)
594 printk(KERN_INFO "Using GB pages for direct mapping\n");
595 else
596 direct_gbpages = 0;
597}
598
599static unsigned long __meminit kernel_physical_mapping_init(unsigned long start,
600 unsigned long end,
601 unsigned long page_size_mask)
602{ 577{
603 578
604 unsigned long next, last_map_addr = end; 579 unsigned long next, last_map_addr = end;
@@ -635,176 +610,6 @@ static unsigned long __meminit kernel_physical_mapping_init(unsigned long start,
635 return last_map_addr; 610 return last_map_addr;
636} 611}
637 612
638struct map_range {
639 unsigned long start;
640 unsigned long end;
641 unsigned page_size_mask;
642};
643
644#define NR_RANGE_MR 5
645
646static int save_mr(struct map_range *mr, int nr_range,
647 unsigned long start_pfn, unsigned long end_pfn,
648 unsigned long page_size_mask)
649{
650
651 if (start_pfn < end_pfn) {
652 if (nr_range >= NR_RANGE_MR)
653 panic("run out of range for init_memory_mapping\n");
654 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
655 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
656 mr[nr_range].page_size_mask = page_size_mask;
657 nr_range++;
658 }
659
660 return nr_range;
661}
662
663/*
664 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
665 * This runs before bootmem is initialized and gets pages directly from
666 * the physical memory. To access them they are temporarily mapped.
667 */
668unsigned long __init_refok init_memory_mapping(unsigned long start,
669 unsigned long end)
670{
671 unsigned long last_map_addr = 0;
672 unsigned long page_size_mask = 0;
673 unsigned long start_pfn, end_pfn;
674 unsigned long pos;
675
676 struct map_range mr[NR_RANGE_MR];
677 int nr_range, i;
678 int use_pse, use_gbpages;
679
680 printk(KERN_INFO "init_memory_mapping: %016lx-%016lx\n", start, end);
681
682 /*
683 * Find space for the kernel direct mapping tables.
684 *
685 * Later we should allocate these tables in the local node of the
686 * memory mapped. Unfortunately this is done currently before the
687 * nodes are discovered.
688 */
689 if (!after_bootmem)
690 init_gbpages();
691
692#ifdef CONFIG_DEBUG_PAGEALLOC
693 /*
694 * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages.
695 * This will simplify cpa(), which otherwise needs to support splitting
696 * large pages into small in interrupt context, etc.
697 */
698 use_pse = use_gbpages = 0;
699#else
700 use_pse = cpu_has_pse;
701 use_gbpages = direct_gbpages;
702#endif
703
704 if (use_gbpages)
705 page_size_mask |= 1 << PG_LEVEL_1G;
706 if (use_pse)
707 page_size_mask |= 1 << PG_LEVEL_2M;
708
709 memset(mr, 0, sizeof(mr));
710 nr_range = 0;
711
712 /* head if not big page alignment ?*/
713 start_pfn = start >> PAGE_SHIFT;
714 pos = start_pfn << PAGE_SHIFT;
715 end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT)
716 << (PMD_SHIFT - PAGE_SHIFT);
717 if (end_pfn > (end >> PAGE_SHIFT))
718 end_pfn = end >> PAGE_SHIFT;
719 if (start_pfn < end_pfn) {
720 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
721 pos = end_pfn << PAGE_SHIFT;
722 }
723
724 /* big page (2M) range*/
725 start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT)
726 << (PMD_SHIFT - PAGE_SHIFT);
727 end_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT)
728 << (PUD_SHIFT - PAGE_SHIFT);
729 if (end_pfn > ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT)))
730 end_pfn = ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT));
731 if (start_pfn < end_pfn) {
732 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
733 page_size_mask & (1<<PG_LEVEL_2M));
734 pos = end_pfn << PAGE_SHIFT;
735 }
736
737 /* big page (1G) range */
738 start_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT)
739 << (PUD_SHIFT - PAGE_SHIFT);
740 end_pfn = (end >> PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT);
741 if (start_pfn < end_pfn) {
742 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
743 page_size_mask &
744 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
745 pos = end_pfn << PAGE_SHIFT;
746 }
747
748 /* tail is not big page (1G) alignment */
749 start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT)
750 << (PMD_SHIFT - PAGE_SHIFT);
751 end_pfn = (end >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT);
752 if (start_pfn < end_pfn) {
753 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
754 page_size_mask & (1<<PG_LEVEL_2M));
755 pos = end_pfn << PAGE_SHIFT;
756 }
757
758 /* tail is not big page (2M) alignment */
759 start_pfn = pos>>PAGE_SHIFT;
760 end_pfn = end>>PAGE_SHIFT;
761 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
762
763 /* try to merge same page size and continuous */
764 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
765 unsigned long old_start;
766 if (mr[i].end != mr[i+1].start ||
767 mr[i].page_size_mask != mr[i+1].page_size_mask)
768 continue;
769 /* move it */
770 old_start = mr[i].start;
771 memmove(&mr[i], &mr[i+1],
772 (nr_range - 1 - i) * sizeof (struct map_range));
773 mr[i--].start = old_start;
774 nr_range--;
775 }
776
777 for (i = 0; i < nr_range; i++)
778 printk(KERN_DEBUG " %010lx - %010lx page %s\n",
779 mr[i].start, mr[i].end,
780 (mr[i].page_size_mask & (1<<PG_LEVEL_1G))?"1G":(
781 (mr[i].page_size_mask & (1<<PG_LEVEL_2M))?"2M":"4k"));
782
783 if (!after_bootmem)
784 find_early_table_space(end, use_pse, use_gbpages);
785
786 for (i = 0; i < nr_range; i++)
787 last_map_addr = kernel_physical_mapping_init(
788 mr[i].start, mr[i].end,
789 mr[i].page_size_mask);
790
791 if (!after_bootmem)
792 mmu_cr4_features = read_cr4();
793 __flush_tlb_all();
794
795 if (!after_bootmem && table_end > table_start)
796 reserve_early(table_start << PAGE_SHIFT,
797 table_end << PAGE_SHIFT, "PGTABLE");
798
799 printk(KERN_INFO "last_map_addr: %lx end: %lx\n",
800 last_map_addr, end);
801
802 if (!after_bootmem)
803 early_memtest(start, end);
804
805 return last_map_addr >> PAGE_SHIFT;
806}
807
808#ifndef CONFIG_NUMA 613#ifndef CONFIG_NUMA
809void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn) 614void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn)
810{ 615{
@@ -876,28 +681,6 @@ EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
876 681
877#endif /* CONFIG_MEMORY_HOTPLUG */ 682#endif /* CONFIG_MEMORY_HOTPLUG */
878 683
879/*
880 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
881 * is valid. The argument is a physical page number.
882 *
883 *
884 * On x86, access has to be given to the first megabyte of ram because that area
885 * contains bios code and data regions used by X and dosemu and similar apps.
886 * Access has to be given to non-kernel-ram areas as well, these contain the PCI
887 * mmio resources as well as potential bios/acpi data regions.
888 */
889int devmem_is_allowed(unsigned long pagenr)
890{
891 if (pagenr <= 256)
892 return 1;
893 if (iomem_is_exclusive(pagenr << PAGE_SHIFT))
894 return 0;
895 if (!page_is_ram(pagenr))
896 return 1;
897 return 0;
898}
899
900
901static struct kcore_list kcore_mem, kcore_vmalloc, kcore_kernel, 684static struct kcore_list kcore_mem, kcore_vmalloc, kcore_kernel,
902 kcore_modules, kcore_vsyscall; 685 kcore_modules, kcore_vsyscall;
903 686
@@ -985,13 +768,6 @@ void mark_rodata_ro(void)
985 768
986#endif 769#endif
987 770
988#ifdef CONFIG_BLK_DEV_INITRD
989void free_initrd_mem(unsigned long start, unsigned long end)
990{
991 free_init_pages("initrd memory", start, end);
992}
993#endif
994
995int __init reserve_bootmem_generic(unsigned long phys, unsigned long len, 771int __init reserve_bootmem_generic(unsigned long phys, unsigned long len,
996 int flags) 772 int flags)
997{ 773{
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 433f7bd4648a..aca924a30ee6 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -38,8 +38,7 @@ unsigned long __phys_addr(unsigned long x)
38 } else { 38 } else {
39 VIRTUAL_BUG_ON(x < PAGE_OFFSET); 39 VIRTUAL_BUG_ON(x < PAGE_OFFSET);
40 x -= PAGE_OFFSET; 40 x -= PAGE_OFFSET;
41 VIRTUAL_BUG_ON(system_state == SYSTEM_BOOTING ? x > MAXMEM : 41 VIRTUAL_BUG_ON(!phys_addr_valid(x));
42 !phys_addr_valid(x));
43 } 42 }
44 return x; 43 return x;
45} 44}
@@ -56,10 +55,8 @@ bool __virt_addr_valid(unsigned long x)
56 if (x < PAGE_OFFSET) 55 if (x < PAGE_OFFSET)
57 return false; 56 return false;
58 x -= PAGE_OFFSET; 57 x -= PAGE_OFFSET;
59 if (system_state == SYSTEM_BOOTING ? 58 if (!phys_addr_valid(x))
60 x > MAXMEM : !phys_addr_valid(x)) {
61 return false; 59 return false;
62 }
63 } 60 }
64 61
65 return pfn_valid(x >> PAGE_SHIFT); 62 return pfn_valid(x >> PAGE_SHIFT);
@@ -76,10 +73,9 @@ static inline int phys_addr_valid(unsigned long addr)
76#ifdef CONFIG_DEBUG_VIRTUAL 73#ifdef CONFIG_DEBUG_VIRTUAL
77unsigned long __phys_addr(unsigned long x) 74unsigned long __phys_addr(unsigned long x)
78{ 75{
79 /* VMALLOC_* aren't constants; not available at the boot time */ 76 /* VMALLOC_* aren't constants */
80 VIRTUAL_BUG_ON(x < PAGE_OFFSET); 77 VIRTUAL_BUG_ON(x < PAGE_OFFSET);
81 VIRTUAL_BUG_ON(system_state != SYSTEM_BOOTING && 78 VIRTUAL_BUG_ON(__vmalloc_start_set && is_vmalloc_addr((void *) x));
82 is_vmalloc_addr((void *) x));
83 return x - PAGE_OFFSET; 79 return x - PAGE_OFFSET;
84} 80}
85EXPORT_SYMBOL(__phys_addr); 81EXPORT_SYMBOL(__phys_addr);
@@ -89,7 +85,9 @@ bool __virt_addr_valid(unsigned long x)
89{ 85{
90 if (x < PAGE_OFFSET) 86 if (x < PAGE_OFFSET)
91 return false; 87 return false;
92 if (system_state != SYSTEM_BOOTING && is_vmalloc_addr((void *) x)) 88 if (__vmalloc_start_set && is_vmalloc_addr((void *) x))
89 return false;
90 if (x >= FIXADDR_START)
93 return false; 91 return false;
94 return pfn_valid((x - PAGE_OFFSET) >> PAGE_SHIFT); 92 return pfn_valid((x - PAGE_OFFSET) >> PAGE_SHIFT);
95} 93}
@@ -508,13 +506,19 @@ static inline pte_t * __init early_ioremap_pte(unsigned long addr)
508 return &bm_pte[pte_index(addr)]; 506 return &bm_pte[pte_index(addr)];
509} 507}
510 508
509static unsigned long slot_virt[FIX_BTMAPS_SLOTS] __initdata;
510
511void __init early_ioremap_init(void) 511void __init early_ioremap_init(void)
512{ 512{
513 pmd_t *pmd; 513 pmd_t *pmd;
514 int i;
514 515
515 if (early_ioremap_debug) 516 if (early_ioremap_debug)
516 printk(KERN_INFO "early_ioremap_init()\n"); 517 printk(KERN_INFO "early_ioremap_init()\n");
517 518
519 for (i = 0; i < FIX_BTMAPS_SLOTS; i++)
520 slot_virt[i] = fix_to_virt(FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*i);
521
518 pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)); 522 pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN));
519 memset(bm_pte, 0, sizeof(bm_pte)); 523 memset(bm_pte, 0, sizeof(bm_pte));
520 pmd_populate_kernel(&init_mm, pmd, bm_pte); 524 pmd_populate_kernel(&init_mm, pmd, bm_pte);
@@ -581,6 +585,7 @@ static inline void __init early_clear_fixmap(enum fixed_addresses idx)
581 585
582static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata; 586static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata;
583static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata; 587static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata;
588
584static int __init check_early_ioremap_leak(void) 589static int __init check_early_ioremap_leak(void)
585{ 590{
586 int count = 0; 591 int count = 0;
@@ -602,7 +607,8 @@ static int __init check_early_ioremap_leak(void)
602} 607}
603late_initcall(check_early_ioremap_leak); 608late_initcall(check_early_ioremap_leak);
604 609
605static void __init __iomem *__early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot) 610static void __init __iomem *
611__early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot)
606{ 612{
607 unsigned long offset, last_addr; 613 unsigned long offset, last_addr;
608 unsigned int nrpages; 614 unsigned int nrpages;
@@ -668,9 +674,9 @@ static void __init __iomem *__early_ioremap(unsigned long phys_addr, unsigned lo
668 --nrpages; 674 --nrpages;
669 } 675 }
670 if (early_ioremap_debug) 676 if (early_ioremap_debug)
671 printk(KERN_CONT "%08lx + %08lx\n", offset, fix_to_virt(idx0)); 677 printk(KERN_CONT "%08lx + %08lx\n", offset, slot_virt[slot]);
672 678
673 prev_map[slot] = (void __iomem *)(offset + fix_to_virt(idx0)); 679 prev_map[slot] = (void __iomem *)(offset + slot_virt[slot]);
674 return prev_map[slot]; 680 return prev_map[slot];
675} 681}
676 682
@@ -738,8 +744,3 @@ void __init early_iounmap(void __iomem *addr, unsigned long size)
738 } 744 }
739 prev_map[slot] = NULL; 745 prev_map[slot] = NULL;
740} 746}
741
742void __this_fixmap_does_not_exist(void)
743{
744 WARN_ON(1);
745}
diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c
index 93d82038af4b..6a518dd08a36 100644
--- a/arch/x86/mm/kmmio.c
+++ b/arch/x86/mm/kmmio.c
@@ -32,11 +32,14 @@ struct kmmio_fault_page {
32 struct list_head list; 32 struct list_head list;
33 struct kmmio_fault_page *release_next; 33 struct kmmio_fault_page *release_next;
34 unsigned long page; /* location of the fault page */ 34 unsigned long page; /* location of the fault page */
35 bool old_presence; /* page presence prior to arming */
36 bool armed;
35 37
36 /* 38 /*
37 * Number of times this page has been registered as a part 39 * Number of times this page has been registered as a part
38 * of a probe. If zero, page is disarmed and this may be freed. 40 * of a probe. If zero, page is disarmed and this may be freed.
39 * Used only by writers (RCU). 41 * Used only by writers (RCU) and post_kmmio_handler().
42 * Protected by kmmio_lock, when linked into kmmio_page_table.
40 */ 43 */
41 int count; 44 int count;
42}; 45};
@@ -105,57 +108,85 @@ static struct kmmio_fault_page *get_kmmio_fault_page(unsigned long page)
105 return NULL; 108 return NULL;
106} 109}
107 110
108static void set_page_present(unsigned long addr, bool present, 111static void set_pmd_presence(pmd_t *pmd, bool present, bool *old)
109 unsigned int *pglevel) 112{
113 pmdval_t v = pmd_val(*pmd);
114 *old = !!(v & _PAGE_PRESENT);
115 v &= ~_PAGE_PRESENT;
116 if (present)
117 v |= _PAGE_PRESENT;
118 set_pmd(pmd, __pmd(v));
119}
120
121static void set_pte_presence(pte_t *pte, bool present, bool *old)
122{
123 pteval_t v = pte_val(*pte);
124 *old = !!(v & _PAGE_PRESENT);
125 v &= ~_PAGE_PRESENT;
126 if (present)
127 v |= _PAGE_PRESENT;
128 set_pte_atomic(pte, __pte(v));
129}
130
131static int set_page_presence(unsigned long addr, bool present, bool *old)
110{ 132{
111 pteval_t pteval;
112 pmdval_t pmdval;
113 unsigned int level; 133 unsigned int level;
114 pmd_t *pmd;
115 pte_t *pte = lookup_address(addr, &level); 134 pte_t *pte = lookup_address(addr, &level);
116 135
117 if (!pte) { 136 if (!pte) {
118 pr_err("kmmio: no pte for page 0x%08lx\n", addr); 137 pr_err("kmmio: no pte for page 0x%08lx\n", addr);
119 return; 138 return -1;
120 } 139 }
121 140
122 if (pglevel)
123 *pglevel = level;
124
125 switch (level) { 141 switch (level) {
126 case PG_LEVEL_2M: 142 case PG_LEVEL_2M:
127 pmd = (pmd_t *)pte; 143 set_pmd_presence((pmd_t *)pte, present, old);
128 pmdval = pmd_val(*pmd) & ~_PAGE_PRESENT;
129 if (present)
130 pmdval |= _PAGE_PRESENT;
131 set_pmd(pmd, __pmd(pmdval));
132 break; 144 break;
133
134 case PG_LEVEL_4K: 145 case PG_LEVEL_4K:
135 pteval = pte_val(*pte) & ~_PAGE_PRESENT; 146 set_pte_presence(pte, present, old);
136 if (present)
137 pteval |= _PAGE_PRESENT;
138 set_pte_atomic(pte, __pte(pteval));
139 break; 147 break;
140
141 default: 148 default:
142 pr_err("kmmio: unexpected page level 0x%x.\n", level); 149 pr_err("kmmio: unexpected page level 0x%x.\n", level);
143 return; 150 return -1;
144 } 151 }
145 152
146 __flush_tlb_one(addr); 153 __flush_tlb_one(addr);
154 return 0;
147} 155}
148 156
149/** Mark the given page as not present. Access to it will trigger a fault. */ 157/*
150static void arm_kmmio_fault_page(unsigned long page, unsigned int *pglevel) 158 * Mark the given page as not present. Access to it will trigger a fault.
159 *
160 * Struct kmmio_fault_page is protected by RCU and kmmio_lock, but the
161 * protection is ignored here. RCU read lock is assumed held, so the struct
162 * will not disappear unexpectedly. Furthermore, the caller must guarantee,
163 * that double arming the same virtual address (page) cannot occur.
164 *
165 * Double disarming on the other hand is allowed, and may occur when a fault
166 * and mmiotrace shutdown happen simultaneously.
167 */
168static int arm_kmmio_fault_page(struct kmmio_fault_page *f)
151{ 169{
152 set_page_present(page & PAGE_MASK, false, pglevel); 170 int ret;
171 WARN_ONCE(f->armed, KERN_ERR "kmmio page already armed.\n");
172 if (f->armed) {
173 pr_warning("kmmio double-arm: page 0x%08lx, ref %d, old %d\n",
174 f->page, f->count, f->old_presence);
175 }
176 ret = set_page_presence(f->page, false, &f->old_presence);
177 WARN_ONCE(ret < 0, KERN_ERR "kmmio arming 0x%08lx failed.\n", f->page);
178 f->armed = true;
179 return ret;
153} 180}
154 181
155/** Mark the given page as present. */ 182/** Restore the given page to saved presence state. */
156static void disarm_kmmio_fault_page(unsigned long page, unsigned int *pglevel) 183static void disarm_kmmio_fault_page(struct kmmio_fault_page *f)
157{ 184{
158 set_page_present(page & PAGE_MASK, true, pglevel); 185 bool tmp;
186 int ret = set_page_presence(f->page, f->old_presence, &tmp);
187 WARN_ONCE(ret < 0,
188 KERN_ERR "kmmio disarming 0x%08lx failed.\n", f->page);
189 f->armed = false;
159} 190}
160 191
161/* 192/*
@@ -202,28 +233,32 @@ int kmmio_handler(struct pt_regs *regs, unsigned long addr)
202 233
203 ctx = &get_cpu_var(kmmio_ctx); 234 ctx = &get_cpu_var(kmmio_ctx);
204 if (ctx->active) { 235 if (ctx->active) {
205 disarm_kmmio_fault_page(faultpage->page, NULL);
206 if (addr == ctx->addr) { 236 if (addr == ctx->addr) {
207 /* 237 /*
208 * On SMP we sometimes get recursive probe hits on the 238 * A second fault on the same page means some other
209 * same address. Context is already saved, fall out. 239 * condition needs handling by do_page_fault(), the
240 * page really not being present is the most common.
210 */ 241 */
211 pr_debug("kmmio: duplicate probe hit on CPU %d, for " 242 pr_debug("kmmio: secondary hit for 0x%08lx CPU %d.\n",
212 "address 0x%08lx.\n", 243 addr, smp_processor_id());
213 smp_processor_id(), addr); 244
214 ret = 1; 245 if (!faultpage->old_presence)
215 goto no_kmmio_ctx; 246 pr_info("kmmio: unexpected secondary hit for "
216 } 247 "address 0x%08lx on CPU %d.\n", addr,
217 /* 248 smp_processor_id());
218 * Prevent overwriting already in-flight context. 249 } else {
219 * This should not happen, let's hope disarming at least 250 /*
220 * prevents a panic. 251 * Prevent overwriting already in-flight context.
221 */ 252 * This should not happen, let's hope disarming at
222 pr_emerg("kmmio: recursive probe hit on CPU %d, " 253 * least prevents a panic.
254 */
255 pr_emerg("kmmio: recursive probe hit on CPU %d, "
223 "for address 0x%08lx. Ignoring.\n", 256 "for address 0x%08lx. Ignoring.\n",
224 smp_processor_id(), addr); 257 smp_processor_id(), addr);
225 pr_emerg("kmmio: previous hit was at 0x%08lx.\n", 258 pr_emerg("kmmio: previous hit was at 0x%08lx.\n",
226 ctx->addr); 259 ctx->addr);
260 disarm_kmmio_fault_page(faultpage);
261 }
227 goto no_kmmio_ctx; 262 goto no_kmmio_ctx;
228 } 263 }
229 ctx->active++; 264 ctx->active++;
@@ -244,7 +279,7 @@ int kmmio_handler(struct pt_regs *regs, unsigned long addr)
244 regs->flags &= ~X86_EFLAGS_IF; 279 regs->flags &= ~X86_EFLAGS_IF;
245 280
246 /* Now we set present bit in PTE and single step. */ 281 /* Now we set present bit in PTE and single step. */
247 disarm_kmmio_fault_page(ctx->fpage->page, NULL); 282 disarm_kmmio_fault_page(ctx->fpage);
248 283
249 /* 284 /*
250 * If another cpu accesses the same page while we are stepping, 285 * If another cpu accesses the same page while we are stepping,
@@ -275,7 +310,7 @@ static int post_kmmio_handler(unsigned long condition, struct pt_regs *regs)
275 struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx); 310 struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx);
276 311
277 if (!ctx->active) { 312 if (!ctx->active) {
278 pr_debug("kmmio: spurious debug trap on CPU %d.\n", 313 pr_warning("kmmio: spurious debug trap on CPU %d.\n",
279 smp_processor_id()); 314 smp_processor_id());
280 goto out; 315 goto out;
281 } 316 }
@@ -283,7 +318,11 @@ static int post_kmmio_handler(unsigned long condition, struct pt_regs *regs)
283 if (ctx->probe && ctx->probe->post_handler) 318 if (ctx->probe && ctx->probe->post_handler)
284 ctx->probe->post_handler(ctx->probe, condition, regs); 319 ctx->probe->post_handler(ctx->probe, condition, regs);
285 320
286 arm_kmmio_fault_page(ctx->fpage->page, NULL); 321 /* Prevent racing against release_kmmio_fault_page(). */
322 spin_lock(&kmmio_lock);
323 if (ctx->fpage->count)
324 arm_kmmio_fault_page(ctx->fpage);
325 spin_unlock(&kmmio_lock);
287 326
288 regs->flags &= ~X86_EFLAGS_TF; 327 regs->flags &= ~X86_EFLAGS_TF;
289 regs->flags |= ctx->saved_flags; 328 regs->flags |= ctx->saved_flags;
@@ -315,20 +354,24 @@ static int add_kmmio_fault_page(unsigned long page)
315 f = get_kmmio_fault_page(page); 354 f = get_kmmio_fault_page(page);
316 if (f) { 355 if (f) {
317 if (!f->count) 356 if (!f->count)
318 arm_kmmio_fault_page(f->page, NULL); 357 arm_kmmio_fault_page(f);
319 f->count++; 358 f->count++;
320 return 0; 359 return 0;
321 } 360 }
322 361
323 f = kmalloc(sizeof(*f), GFP_ATOMIC); 362 f = kzalloc(sizeof(*f), GFP_ATOMIC);
324 if (!f) 363 if (!f)
325 return -1; 364 return -1;
326 365
327 f->count = 1; 366 f->count = 1;
328 f->page = page; 367 f->page = page;
329 list_add_rcu(&f->list, kmmio_page_list(f->page));
330 368
331 arm_kmmio_fault_page(f->page, NULL); 369 if (arm_kmmio_fault_page(f)) {
370 kfree(f);
371 return -1;
372 }
373
374 list_add_rcu(&f->list, kmmio_page_list(f->page));
332 375
333 return 0; 376 return 0;
334} 377}
@@ -347,7 +390,7 @@ static void release_kmmio_fault_page(unsigned long page,
347 f->count--; 390 f->count--;
348 BUG_ON(f->count < 0); 391 BUG_ON(f->count < 0);
349 if (!f->count) { 392 if (!f->count) {
350 disarm_kmmio_fault_page(f->page, NULL); 393 disarm_kmmio_fault_page(f);
351 f->release_next = *release_list; 394 f->release_next = *release_list;
352 *release_list = f; 395 *release_list = f;
353 } 396 }
@@ -408,23 +451,24 @@ static void rcu_free_kmmio_fault_pages(struct rcu_head *head)
408 451
409static void remove_kmmio_fault_pages(struct rcu_head *head) 452static void remove_kmmio_fault_pages(struct rcu_head *head)
410{ 453{
411 struct kmmio_delayed_release *dr = container_of( 454 struct kmmio_delayed_release *dr =
412 head, 455 container_of(head, struct kmmio_delayed_release, rcu);
413 struct kmmio_delayed_release,
414 rcu);
415 struct kmmio_fault_page *p = dr->release_list; 456 struct kmmio_fault_page *p = dr->release_list;
416 struct kmmio_fault_page **prevp = &dr->release_list; 457 struct kmmio_fault_page **prevp = &dr->release_list;
417 unsigned long flags; 458 unsigned long flags;
459
418 spin_lock_irqsave(&kmmio_lock, flags); 460 spin_lock_irqsave(&kmmio_lock, flags);
419 while (p) { 461 while (p) {
420 if (!p->count) 462 if (!p->count) {
421 list_del_rcu(&p->list); 463 list_del_rcu(&p->list);
422 else 464 prevp = &p->release_next;
465 } else {
423 *prevp = p->release_next; 466 *prevp = p->release_next;
424 prevp = &p->release_next; 467 }
425 p = p->release_next; 468 p = p->release_next;
426 } 469 }
427 spin_unlock_irqrestore(&kmmio_lock, flags); 470 spin_unlock_irqrestore(&kmmio_lock, flags);
471
428 /* This is the real RCU destroy call. */ 472 /* This is the real RCU destroy call. */
429 call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages); 473 call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages);
430} 474}
diff --git a/arch/x86/mm/memtest.c b/arch/x86/mm/memtest.c
index 0bcd7883d036..605c8be06217 100644
--- a/arch/x86/mm/memtest.c
+++ b/arch/x86/mm/memtest.c
@@ -100,6 +100,9 @@ static int __init parse_memtest(char *arg)
100{ 100{
101 if (arg) 101 if (arg)
102 memtest_pattern = simple_strtoul(arg, NULL, 0); 102 memtest_pattern = simple_strtoul(arg, NULL, 0);
103 else
104 memtest_pattern = ARRAY_SIZE(patterns);
105
103 return 0; 106 return 0;
104} 107}
105 108
diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c
index 451fe95a0352..3daefa04ace5 100644
--- a/arch/x86/mm/numa_32.c
+++ b/arch/x86/mm/numa_32.c
@@ -416,10 +416,11 @@ void __init initmem_init(unsigned long start_pfn,
416 for_each_online_node(nid) 416 for_each_online_node(nid)
417 propagate_e820_map_node(nid); 417 propagate_e820_map_node(nid);
418 418
419 for_each_online_node(nid) 419 for_each_online_node(nid) {
420 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); 420 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
421 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
422 }
421 423
422 NODE_DATA(0)->bdata = &bootmem_node_data[0];
423 setup_bootmem_allocator(); 424 setup_bootmem_allocator();
424} 425}
425 426
diff --git a/arch/x86/mm/testmmiotrace.c b/arch/x86/mm/testmmiotrace.c
index ab50a8d7402c..427fd1b56df5 100644
--- a/arch/x86/mm/testmmiotrace.c
+++ b/arch/x86/mm/testmmiotrace.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Written by Pekka Paalanen, 2008 <pq@iki.fi> 2 * Written by Pekka Paalanen, 2008-2009 <pq@iki.fi>
3 */ 3 */
4#include <linux/module.h> 4#include <linux/module.h>
5#include <linux/io.h> 5#include <linux/io.h>
@@ -9,35 +9,74 @@
9 9
10static unsigned long mmio_address; 10static unsigned long mmio_address;
11module_param(mmio_address, ulong, 0); 11module_param(mmio_address, ulong, 0);
12MODULE_PARM_DESC(mmio_address, "Start address of the mapping of 16 kB."); 12MODULE_PARM_DESC(mmio_address, " Start address of the mapping of 16 kB "
13 "(or 8 MB if read_far is non-zero).");
14
15static unsigned long read_far = 0x400100;
16module_param(read_far, ulong, 0);
17MODULE_PARM_DESC(read_far, " Offset of a 32-bit read within 8 MB "
18 "(default: 0x400100).");
19
20static unsigned v16(unsigned i)
21{
22 return i * 12 + 7;
23}
24
25static unsigned v32(unsigned i)
26{
27 return i * 212371 + 13;
28}
13 29
14static void do_write_test(void __iomem *p) 30static void do_write_test(void __iomem *p)
15{ 31{
16 unsigned int i; 32 unsigned int i;
33 pr_info(MODULE_NAME ": write test.\n");
17 mmiotrace_printk("Write test.\n"); 34 mmiotrace_printk("Write test.\n");
35
18 for (i = 0; i < 256; i++) 36 for (i = 0; i < 256; i++)
19 iowrite8(i, p + i); 37 iowrite8(i, p + i);
38
20 for (i = 1024; i < (5 * 1024); i += 2) 39 for (i = 1024; i < (5 * 1024); i += 2)
21 iowrite16(i * 12 + 7, p + i); 40 iowrite16(v16(i), p + i);
41
22 for (i = (5 * 1024); i < (16 * 1024); i += 4) 42 for (i = (5 * 1024); i < (16 * 1024); i += 4)
23 iowrite32(i * 212371 + 13, p + i); 43 iowrite32(v32(i), p + i);
24} 44}
25 45
26static void do_read_test(void __iomem *p) 46static void do_read_test(void __iomem *p)
27{ 47{
28 unsigned int i; 48 unsigned int i;
49 unsigned errs[3] = { 0 };
50 pr_info(MODULE_NAME ": read test.\n");
29 mmiotrace_printk("Read test.\n"); 51 mmiotrace_printk("Read test.\n");
52
30 for (i = 0; i < 256; i++) 53 for (i = 0; i < 256; i++)
31 ioread8(p + i); 54 if (ioread8(p + i) != i)
55 ++errs[0];
56
32 for (i = 1024; i < (5 * 1024); i += 2) 57 for (i = 1024; i < (5 * 1024); i += 2)
33 ioread16(p + i); 58 if (ioread16(p + i) != v16(i))
59 ++errs[1];
60
34 for (i = (5 * 1024); i < (16 * 1024); i += 4) 61 for (i = (5 * 1024); i < (16 * 1024); i += 4)
35 ioread32(p + i); 62 if (ioread32(p + i) != v32(i))
63 ++errs[2];
64
65 mmiotrace_printk("Read errors: 8-bit %d, 16-bit %d, 32-bit %d.\n",
66 errs[0], errs[1], errs[2]);
36} 67}
37 68
38static void do_test(void) 69static void do_read_far_test(void __iomem *p)
39{ 70{
40 void __iomem *p = ioremap_nocache(mmio_address, 0x4000); 71 pr_info(MODULE_NAME ": read far test.\n");
72 mmiotrace_printk("Read far test.\n");
73
74 ioread32(p + read_far);
75}
76
77static void do_test(unsigned long size)
78{
79 void __iomem *p = ioremap_nocache(mmio_address, size);
41 if (!p) { 80 if (!p) {
42 pr_err(MODULE_NAME ": could not ioremap, aborting.\n"); 81 pr_err(MODULE_NAME ": could not ioremap, aborting.\n");
43 return; 82 return;
@@ -45,11 +84,15 @@ static void do_test(void)
45 mmiotrace_printk("ioremap returned %p.\n", p); 84 mmiotrace_printk("ioremap returned %p.\n", p);
46 do_write_test(p); 85 do_write_test(p);
47 do_read_test(p); 86 do_read_test(p);
87 if (read_far && read_far < size - 4)
88 do_read_far_test(p);
48 iounmap(p); 89 iounmap(p);
49} 90}
50 91
51static int __init init(void) 92static int __init init(void)
52{ 93{
94 unsigned long size = (read_far) ? (8 << 20) : (16 << 10);
95
53 if (mmio_address == 0) { 96 if (mmio_address == 0) {
54 pr_err(MODULE_NAME ": you have to use the module argument " 97 pr_err(MODULE_NAME ": you have to use the module argument "
55 "mmio_address.\n"); 98 "mmio_address.\n");
@@ -58,10 +101,11 @@ static int __init init(void)
58 return -ENXIO; 101 return -ENXIO;
59 } 102 }
60 103
61 pr_warning(MODULE_NAME ": WARNING: mapping 16 kB @ 0x%08lx " 104 pr_warning(MODULE_NAME ": WARNING: mapping %lu kB @ 0x%08lx in PCI "
62 "in PCI address space, and writing " 105 "address space, and writing 16 kB of rubbish in there.\n",
63 "rubbish in there.\n", mmio_address); 106 size >> 10, mmio_address);
64 do_test(); 107 do_test(size);
108 pr_info(MODULE_NAME ": All done.\n");
65 return 0; 109 return 0;
66} 110}
67 111
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index c52f4034c7fd..82cd39a6cbd3 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -103,7 +103,7 @@ static void xen_vcpu_setup(int cpu)
103 103
104 vcpup = &per_cpu(xen_vcpu_info, cpu); 104 vcpup = &per_cpu(xen_vcpu_info, cpu);
105 105
106 info.mfn = virt_to_mfn(vcpup); 106 info.mfn = arbitrary_virt_to_mfn(vcpup);
107 info.offset = offset_in_page(vcpup); 107 info.offset = offset_in_page(vcpup);
108 108
109 printk(KERN_DEBUG "trying to map vcpu_info %d at %p, mfn %llx, offset %d\n", 109 printk(KERN_DEBUG "trying to map vcpu_info %d at %p, mfn %llx, offset %d\n",
@@ -301,8 +301,10 @@ static void xen_load_gdt(const struct desc_ptr *dtr)
301 frames = mcs.args; 301 frames = mcs.args;
302 302
303 for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) { 303 for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
304 frames[f] = virt_to_mfn(va); 304 frames[f] = arbitrary_virt_to_mfn((void *)va);
305
305 make_lowmem_page_readonly((void *)va); 306 make_lowmem_page_readonly((void *)va);
307 make_lowmem_page_readonly(mfn_to_virt(frames[f]));
306 } 308 }
307 309
308 MULTI_set_gdt(mcs.mc, frames, size / sizeof(struct desc_struct)); 310 MULTI_set_gdt(mcs.mc, frames, size / sizeof(struct desc_struct));
@@ -314,7 +316,7 @@ static void load_TLS_descriptor(struct thread_struct *t,
314 unsigned int cpu, unsigned int i) 316 unsigned int cpu, unsigned int i)
315{ 317{
316 struct desc_struct *gdt = get_cpu_gdt_table(cpu); 318 struct desc_struct *gdt = get_cpu_gdt_table(cpu);
317 xmaddr_t maddr = virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 319 xmaddr_t maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
318 struct multicall_space mc = __xen_mc_entry(0); 320 struct multicall_space mc = __xen_mc_entry(0);
319 321
320 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 322 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
@@ -488,7 +490,7 @@ static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
488 break; 490 break;
489 491
490 default: { 492 default: {
491 xmaddr_t maddr = virt_to_machine(&dt[entry]); 493 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]);
492 494
493 xen_mc_flush(); 495 xen_mc_flush();
494 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 496 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 319bd40a57c2..cb6afa4ec95c 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -276,6 +276,13 @@ void set_phys_to_machine(unsigned long pfn, unsigned long mfn)
276 p2m_top[topidx][idx] = mfn; 276 p2m_top[topidx][idx] = mfn;
277} 277}
278 278
279unsigned long arbitrary_virt_to_mfn(void *vaddr)
280{
281 xmaddr_t maddr = arbitrary_virt_to_machine(vaddr);
282
283 return PFN_DOWN(maddr.maddr);
284}
285
279xmaddr_t arbitrary_virt_to_machine(void *vaddr) 286xmaddr_t arbitrary_virt_to_machine(void *vaddr)
280{ 287{
281 unsigned long address = (unsigned long)vaddr; 288 unsigned long address = (unsigned long)vaddr;
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 035582ae815d..8d470562ffc9 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -219,6 +219,7 @@ cpu_initialize_context(unsigned int cpu, struct task_struct *idle)
219{ 219{
220 struct vcpu_guest_context *ctxt; 220 struct vcpu_guest_context *ctxt;
221 struct desc_struct *gdt; 221 struct desc_struct *gdt;
222 unsigned long gdt_mfn;
222 223
223 if (cpumask_test_and_set_cpu(cpu, xen_cpu_initialized_map)) 224 if (cpumask_test_and_set_cpu(cpu, xen_cpu_initialized_map))
224 return 0; 225 return 0;
@@ -248,9 +249,12 @@ cpu_initialize_context(unsigned int cpu, struct task_struct *idle)
248 ctxt->ldt_ents = 0; 249 ctxt->ldt_ents = 0;
249 250
250 BUG_ON((unsigned long)gdt & ~PAGE_MASK); 251 BUG_ON((unsigned long)gdt & ~PAGE_MASK);
252
253 gdt_mfn = arbitrary_virt_to_mfn(gdt);
251 make_lowmem_page_readonly(gdt); 254 make_lowmem_page_readonly(gdt);
255 make_lowmem_page_readonly(mfn_to_virt(gdt_mfn));
252 256
253 ctxt->gdt_frames[0] = virt_to_mfn(gdt); 257 ctxt->gdt_frames[0] = gdt_mfn;
254 ctxt->gdt_ents = GDT_ENTRIES; 258 ctxt->gdt_ents = GDT_ENTRIES;
255 259
256 ctxt->user_regs.cs = __KERNEL_CS; 260 ctxt->user_regs.cs = __KERNEL_CS;
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 6c873dceb177..981200830432 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -103,9 +103,6 @@ config MATH_EMULATION
103 help 103 help
104 Can we use information of configuration file? 104 Can we use information of configuration file?
105 105
106config HIGHMEM
107 bool "High memory support"
108
109endmenu 106endmenu
110 107
111menu "Platform options" 108menu "Platform options"
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 9606d2bd1dd9..4ec1633c2941 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -44,6 +44,8 @@
44#include <asm/setup.h> 44#include <asm/setup.h>
45#include <asm/param.h> 45#include <asm/param.h>
46 46
47#include <platform/hardware.h>
48
47#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 49#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
48struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; 50struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
49#endif 51#endif
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index c7a021d9f696..c44f830b6c7a 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -30,6 +30,7 @@
30#include <linux/stringify.h> 30#include <linux/stringify.h>
31#include <linux/kallsyms.h> 31#include <linux/kallsyms.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/hardirq.h>
33 34
34#include <asm/ptrace.h> 35#include <asm/ptrace.h>
35#include <asm/timex.h> 36#include <asm/timex.h>
diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c
index 33f366be323f..bdd860d93f72 100644
--- a/arch/xtensa/mm/fault.c
+++ b/arch/xtensa/mm/fault.c
@@ -14,6 +14,7 @@
14 14
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/hardirq.h>
17#include <asm/mmu_context.h> 18#include <asm/mmu_context.h>
18#include <asm/cacheflush.h> 19#include <asm/cacheflush.h>
19#include <asm/hardirq.h> 20#include <asm/hardirq.h>
diff --git a/arch/xtensa/platforms/iss/console.c b/arch/xtensa/platforms/iss/console.c
index efed8897bef3..25d46c84eb08 100644
--- a/arch/xtensa/platforms/iss/console.c
+++ b/arch/xtensa/platforms/iss/console.c
@@ -140,16 +140,14 @@ static void rs_poll(unsigned long priv)
140} 140}
141 141
142 142
143static void rs_put_char(struct tty_struct *tty, unsigned char ch) 143static int rs_put_char(struct tty_struct *tty, unsigned char ch)
144{ 144{
145 char buf[2]; 145 char buf[2];
146 146
147 if (!tty)
148 return;
149
150 buf[0] = ch; 147 buf[0] = ch;
151 buf[1] = '\0'; /* Is this NULL necessary? */ 148 buf[1] = '\0'; /* Is this NULL necessary? */
152 __simc (SYS_write, 1, (unsigned long) buf, 1, 0, 0); 149 __simc (SYS_write, 1, (unsigned long) buf, 1, 0, 0);
150 return 1;
153} 151}
154 152
155static void rs_flush_chars(struct tty_struct *tty) 153static void rs_flush_chars(struct tty_struct *tty)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-27 00:42:07 -0400