7 files changed, 76 insertions, 45 deletions

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index d3ad5150d660..c25a2a4f2e3d 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -367,17 +367,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
 /* Tegra PCIE requires relaxed ordering */
 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
 {
-        u16 val16;
-        int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-
-        if (pos <= 0) {
-                dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
-                return;
-        }
-
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
-        val16 |= PCI_EXP_DEVCTL_RELAX_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
 
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
index d04ed14bbf0c..71e9bcf58105 100644
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ b/arch/frv/mb93090-mb00/pci-vdk.c
@@ -330,10 +330,8 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)
         pci_read_bridge_bases(bus);
 
         if (bus->number == 0) {
-                struct list_head *ln;
                 struct pci_dev *dev;
-                for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
-                        dev = pci_dev_b(ln);
+                list_for_each_entry(dev, &bus->devices, bus_list) {
                         if (dev->devfn == 0) {
                                 dev->resource[0].start = 0;
                                 dev->resource[0].end = 0;
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 52a1ba70b3b6..c5dfb2c87d44 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -117,16 +117,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         }
 
         /* Enable the PCIe normal error reporting */
-        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-        if (pos) {
-                /* Update Device Control */
-                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
-                config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
-                config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
-                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
-        }
+        config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
+        config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
+        config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
+        config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
 
         /* Find the Advanced Error Reporting capability */
         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 42ce570812c1..f7706d722b39 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -214,6 +214,9 @@ struct machdep_calls {
         /* Called after scan and before resource survey */
         void (*pcibios_fixup_phb)(struct pci_controller *hose);
 
+        /* Called during PCI resource reassignment */
+        resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type);
+
         /* Called to shutdown machine specific hardware not already controlled
          * by other drivers.
          */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 2aa04f29e1de..43fea543d686 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -99,6 +99,26 @@ void pcibios_free_controller(struct pci_controller *phb)
                 kfree(phb);
 }
 
+/*
+ * The function is used to return the minimal alignment
+ * for memory or I/O windows of the associated P2P bridge.
+ * By default, 4KiB alignment for I/O windows and 1MiB for
+ * memory windows.
+ */
+resource_size_t pcibios_window_alignment(struct pci_bus *bus,
+                                         unsigned long type)
+{
+        if (ppc_md.pcibios_window_alignment)
+                return ppc_md.pcibios_window_alignment(bus, type);
+
+        /*
+         * PCI core will figure out the default
+         * alignment: 4KiB for I/O and 1MiB for
+         * memory window.
+         */
+        return 1;
+}
+
 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
 {
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 9cda6a1ad0cf..0e7eccc0f88d 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -855,7 +855,7 @@ static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus)
                 if (pe == NULL)
                         continue;
                 /* Leaving the PCIe domain ... single PE# */
-                if (dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
+                if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
                         pnv_ioda_setup_bus_PE(dev, pe);
                 else if (dev->subordinate)
                         pnv_ioda_setup_PEs(dev->subordinate);
@@ -1139,6 +1139,44 @@ static void __devinit pnv_pci_ioda_fixup_phb(struct pci_controller *hose)
         }
 }
 
+/*
+ * Returns the alignment for I/O or memory windows for P2P
+ * bridges. That actually depends on how PEs are segmented.
+ * For now, we return I/O or M32 segment size for PE sensitive
+ * P2P bridges. Otherwise, the default values (4KiB for I/O,
+ * 1MiB for memory) will be returned.
+ *
+ * The current PCI bus might be put into one PE, which was
+ * create against the parent PCI bridge. For that case, we
+ * needn't enlarge the alignment so that we can save some
+ * resources.
+ */
+static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
+                                                unsigned long type)
+{
+        struct pci_dev *bridge;
+        struct pci_controller *hose = pci_bus_to_host(bus);
+        struct pnv_phb *phb = hose->private_data;
+        int num_pci_bridges = 0;
+
+        bridge = bus->self;
+        while (bridge) {
+                if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
+                        num_pci_bridges++;
+                        if (num_pci_bridges >= 2)
+                                return 1;
+                }
+
+                bridge = bridge->bus->self;
+        }
+
+        /* We need support prefetchable memory window later */
+        if (type & IORESOURCE_MEM)
+                return phb->ioda.m32_segsize;
+
+        return phb->ioda.io_segsize;
+}
+
 /* Prevent enabling devices for which we couldn't properly
  * assign a PE
  */
@@ -1306,6 +1344,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
          */
         ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
+        ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
         pci_add_flags(PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC);
 
         /* Reset IODA tables to a clean state */
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index 33c10864d2f7..d2292be6fb90 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -246,16 +246,13 @@ static void __devinit fixup_read_and_payload_sizes(void)
 
         /* Scan for the smallest maximum payload size. */
         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-                int pcie_caps_offset;
                 u32 devcap;
                 int max_payload;
 
-                pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
-                if (pcie_caps_offset == 0)
+                if (!pci_is_pcie(dev))
                         continue;
 
-                pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
-                                      &devcap);
+                pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
                 max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
                 if (max_payload < smallest_max_payload)
                         smallest_max_payload = max_payload;
@@ -263,21 +260,10 @@ static void __devinit fixup_read_and_payload_sizes(void)
 
         /* Now, set the max_payload_size for all devices to that value. */
         new_values = (max_read_size << 12) | (smallest_max_payload << 5);
-        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-                int pcie_caps_offset;
-                u16 devctl;
-
-                pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
-                if (pcie_caps_offset == 0)
-                        continue;
-
-                pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
-                                     &devctl);
-                devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
-                devctl |= new_values;
-                pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
-                                      devctl);
-        }
+        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
+                pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
+                                PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
+                                new_values);
 }