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-rw-r--r--arch/arm/common/gic.c1
-rw-r--r--arch/arm/kernel/time.c10
-rw-r--r--arch/arm/mach-ixp4xx/common.c155
-rw-r--r--arch/arm/mach-ixp4xx/coyote-pci.c7
-rw-r--r--arch/arm/mach-ixp4xx/coyote-setup.c9
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-pci.c28
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c8
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-pci.c12
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c13
-rw-r--r--arch/arm/mach-ixp4xx/ixdpg425-pci.c4
-rw-r--r--arch/arm/mach-s3c2410/clock.c9
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-clock.c6
-rw-r--r--arch/arm/mm/alignment.c70
-rw-r--r--arch/arm/mm/mm-armv.c4
-rw-r--r--arch/ppc/kernel/cpu_setup_6xx.S5
-rw-r--r--arch/ppc/kernel/l2cr.S31
-rw-r--r--arch/ppc64/mm/slb_low.S22
17 files changed, 211 insertions, 183 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 51dbf5489b6b..d74990717559 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -24,6 +24,7 @@
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/list.h> 25#include <linux/list.h>
26#include <linux/smp.h> 26#include <linux/smp.h>
27#include <linux/cpumask.h>
27 28
28#include <asm/irq.h> 29#include <asm/irq.h>
29#include <asm/io.h> 30#include <asm/io.h>
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 1b7fcd50c3e2..8880482dcbff 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -433,10 +433,12 @@ void timer_dyn_reprogram(void)
433{ 433{
434 struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick; 434 struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
435 435
436 write_seqlock(&xtime_lock); 436 if (dyn_tick) {
437 if (dyn_tick->state & DYN_TICK_ENABLED) 437 write_seqlock(&xtime_lock);
438 dyn_tick->reprogram(next_timer_interrupt() - jiffies); 438 if (dyn_tick->state & DYN_TICK_ENABLED)
439 write_sequnlock(&xtime_lock); 439 dyn_tick->reprogram(next_timer_interrupt() - jiffies);
440 write_sequnlock(&xtime_lock);
441 }
440} 442}
441 443
442static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf) 444static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 04490a9f8f6e..0422e906cc9a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -38,90 +38,6 @@
38#include <asm/mach/irq.h> 38#include <asm/mach/irq.h>
39#include <asm/mach/time.h> 39#include <asm/mach/time.h>
40 40
41enum ixp4xx_irq_type {
42 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
43};
44static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
45
46/*************************************************************************
47 * GPIO acces functions
48 *************************************************************************/
49
50/*
51 * Configure GPIO line for input, interrupt, or output operation
52 *
53 * TODO: Enable/disable the irq_desc based on interrupt or output mode.
54 * TODO: Should these be named ixp4xx_gpio_?
55 */
56void gpio_line_config(u8 line, u32 style)
57{
58 static const int gpio2irq[] = {
59 6, 7, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29
60 };
61 u32 enable;
62 volatile u32 *int_reg;
63 u32 int_style;
64 enum ixp4xx_irq_type irq_type;
65
66 enable = *IXP4XX_GPIO_GPOER;
67
68 if (style & IXP4XX_GPIO_OUT) {
69 enable &= ~((1) << line);
70 } else if (style & IXP4XX_GPIO_IN) {
71 enable |= ((1) << line);
72
73 switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
74 {
75 case (IXP4XX_GPIO_ACTIVE_HIGH):
76 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
77 irq_type = IXP4XX_IRQ_LEVEL;
78 break;
79 case (IXP4XX_GPIO_ACTIVE_LOW):
80 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
81 irq_type = IXP4XX_IRQ_LEVEL;
82 break;
83 case (IXP4XX_GPIO_RISING_EDGE):
84 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
85 irq_type = IXP4XX_IRQ_EDGE;
86 break;
87 case (IXP4XX_GPIO_FALLING_EDGE):
88 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
89 irq_type = IXP4XX_IRQ_EDGE;
90 break;
91 case (IXP4XX_GPIO_TRANSITIONAL):
92 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
93 irq_type = IXP4XX_IRQ_EDGE;
94 break;
95 default:
96 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
97 irq_type = IXP4XX_IRQ_LEVEL;
98 break;
99 }
100
101 if (style & IXP4XX_GPIO_INTSTYLE_MASK)
102 ixp4xx_config_irq(gpio2irq[line], irq_type);
103
104 if (line >= 8) { /* pins 8-15 */
105 line -= 8;
106 int_reg = IXP4XX_GPIO_GPIT2R;
107 }
108 else { /* pins 0-7 */
109 int_reg = IXP4XX_GPIO_GPIT1R;
110 }
111
112 /* Clear the style for the appropriate pin */
113 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
114 (line * IXP4XX_GPIO_STYLE_SIZE));
115
116 /* Set the new style */
117 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
118 }
119
120 *IXP4XX_GPIO_GPOER = enable;
121}
122
123EXPORT_SYMBOL(gpio_line_config);
124
125/************************************************************************* 41/*************************************************************************
126 * IXP4xx chipset I/O mapping 42 * IXP4xx chipset I/O mapping
127 *************************************************************************/ 43 *************************************************************************/
@@ -165,6 +81,69 @@ void __init ixp4xx_map_io(void)
165 * (be it PCI or something else) configures that GPIO line 81 * (be it PCI or something else) configures that GPIO line
166 * as an IRQ. 82 * as an IRQ.
167 **************************************************************************/ 83 **************************************************************************/
84enum ixp4xx_irq_type {
85 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
86};
87
88static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
89
90/*
91 * IRQ -> GPIO mapping table
92 */
93static int irq2gpio[32] = {
94 -1, -1, -1, -1, -1, -1, 0, 1,
95 -1, -1, -1, -1, -1, -1, -1, -1,
96 -1, -1, -1, 2, 3, 4, 5, 6,
97 7, 8, 9, 10, 11, 12, -1, -1,
98};
99
100static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
101{
102 int line = irq2gpio[irq];
103 u32 int_style;
104 enum ixp4xx_irq_type irq_type;
105 volatile u32 *int_reg;
106
107 /*
108 * Only for GPIO IRQs
109 */
110 if (line < 0)
111 return -EINVAL;
112
113 if (type & IRQT_BOTHEDGE) {
114 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
115 irq_type = IXP4XX_IRQ_EDGE;
116 } else if (type & IRQT_RISING) {
117 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
118 irq_type = IXP4XX_IRQ_EDGE;
119 } else if (type & IRQT_FALLING) {
120 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
121 irq_type = IXP4XX_IRQ_EDGE;
122 } else if (type & IRQT_HIGH) {
123 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
124 irq_type = IXP4XX_IRQ_LEVEL;
125 } else if (type & IRQT_LOW) {
126 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
127 irq_type = IXP4XX_IRQ_LEVEL;
128 }
129
130 ixp4xx_config_irq(irq, irq_type);
131
132 if (line >= 8) { /* pins 8-15 */
133 line -= 8;
134 int_reg = IXP4XX_GPIO_GPIT2R;
135 } else { /* pins 0-7 */
136 int_reg = IXP4XX_GPIO_GPIT1R;
137 }
138
139 /* Clear the style for the appropriate pin */
140 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
141 (line * IXP4XX_GPIO_STYLE_SIZE));
142
143 /* Set the new style */
144 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
145}
146
168static void ixp4xx_irq_mask(unsigned int irq) 147static void ixp4xx_irq_mask(unsigned int irq)
169{ 148{
170 if (cpu_is_ixp46x() && irq >= 32) 149 if (cpu_is_ixp46x() && irq >= 32)
@@ -183,12 +162,6 @@ static void ixp4xx_irq_unmask(unsigned int irq)
183 162
184static void ixp4xx_irq_ack(unsigned int irq) 163static void ixp4xx_irq_ack(unsigned int irq)
185{ 164{
186 static int irq2gpio[32] = {
187 -1, -1, -1, -1, -1, -1, 0, 1,
188 -1, -1, -1, -1, -1, -1, -1, -1,
189 -1, -1, -1, 2, 3, 4, 5, 6,
190 7, 8, 9, 10, 11, 12, -1, -1,
191 };
192 int line = (irq < 32) ? irq2gpio[irq] : -1; 165 int line = (irq < 32) ? irq2gpio[irq] : -1;
193 166
194 if (line >= 0) 167 if (line >= 0)
@@ -209,12 +182,14 @@ static struct irqchip ixp4xx_irq_level_chip = {
209 .ack = ixp4xx_irq_mask, 182 .ack = ixp4xx_irq_mask,
210 .mask = ixp4xx_irq_mask, 183 .mask = ixp4xx_irq_mask,
211 .unmask = ixp4xx_irq_level_unmask, 184 .unmask = ixp4xx_irq_level_unmask,
185 .type = ixp4xx_set_irq_type
212}; 186};
213 187
214static struct irqchip ixp4xx_irq_edge_chip = { 188static struct irqchip ixp4xx_irq_edge_chip = {
215 .ack = ixp4xx_irq_ack, 189 .ack = ixp4xx_irq_ack,
216 .mask = ixp4xx_irq_mask, 190 .mask = ixp4xx_irq_mask,
217 .unmask = ixp4xx_irq_unmask, 191 .unmask = ixp4xx_irq_unmask,
192 .type = ixp4xx_set_irq_type
218}; 193};
219 194
220static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type) 195static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index afafb42ae129..60de8a94cff5 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -30,11 +30,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
30 30
31void __init coyote_pci_preinit(void) 31void __init coyote_pci_preinit(void)
32{ 32{
33 gpio_line_config(COYOTE_PCI_SLOT0_PIN, 33 set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW);
34 IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); 34 set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW);
35
36 gpio_line_config(COYOTE_PCI_SLOT1_PIN,
37 IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
38 35
39 gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN); 36 gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN);
40 gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN); 37 gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN);
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 411ea9996190..8b2f25322452 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -24,11 +24,6 @@
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/mach/flash.h> 25#include <asm/mach/flash.h>
26 26
27void __init coyote_map_io(void)
28{
29 ixp4xx_map_io();
30}
31
32static struct flash_platform_data coyote_flash_data = { 27static struct flash_platform_data coyote_flash_data = {
33 .map_name = "cfi_probe", 28 .map_name = "cfi_probe",
34 .width = 2, 29 .width = 2,
@@ -107,7 +102,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
107 .phys_ram = PHYS_OFFSET, 102 .phys_ram = PHYS_OFFSET,
108 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, 103 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
109 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, 104 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
110 .map_io = coyote_map_io, 105 .map_io = ixp4xx_map_io,
111 .init_irq = ixp4xx_init_irq, 106 .init_irq = ixp4xx_init_irq,
112 .timer = &ixp4xx_timer, 107 .timer = &ixp4xx_timer,
113 .boot_params = 0x0100, 108 .boot_params = 0x0100,
@@ -125,7 +120,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425")
125 .phys_ram = PHYS_OFFSET, 120 .phys_ram = PHYS_OFFSET,
126 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, 121 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
127 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, 122 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
128 .map_io = coyote_map_io, 123 .map_io = ixp4xx_map_io,
129 .init_irq = ixp4xx_init_irq, 124 .init_irq = ixp4xx_init_irq,
130 .timer = &ixp4xx_timer, 125 .timer = &ixp4xx_timer,
131 .boot_params = 0x0100, 126 .boot_params = 0x0100,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index b18035824e3e..a66484b63d36 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -35,26 +35,20 @@ extern void ixp4xx_pci_preinit(void);
35extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); 35extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
36extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); 36extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
37 37
38 /*
39 * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
40 * Slot 0 isn't actually populated with a card connector but
41 * we initialize it anyway in case a future version has the
42 * slot populated or someone with good soldering skills has
43 * some free time.
44 */
45
46
47static void gtwx5715_init_gpio(u8 pin, u32 style)
48{
49 gpio_line_config(pin, style | IXP4XX_GPIO_ACTIVE_LOW);
50
51 if (style & IXP4XX_GPIO_IN) gpio_line_isr_clear(pin);
52}
53 38
39/*
40 * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
41 * Slot 0 isn't actually populated with a card connector but
42 * we initialize it anyway in case a future version has the
43 * slot populated or someone with good soldering skills has
44 * some free time.
45 */
54void __init gtwx5715_pci_preinit(void) 46void __init gtwx5715_pci_preinit(void)
55{ 47{
56 gtwx5715_init_gpio(GTWX5715_PCI_SLOT0_INTA_GPIO, IXP4XX_GPIO_IN); 48 set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQT_LOW);
57 gtwx5715_init_gpio(GTWX5715_PCI_SLOT1_INTA_GPIO, IXP4XX_GPIO_IN); 49 set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQT_LOW);
50 set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQT_LOW);
51 set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQT_LOW);
58 52
59 ixp4xx_pci_preinit(); 53 ixp4xx_pci_preinit();
60} 54}
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 333459d6aa46..3fd92c5cbaa8 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -101,12 +101,6 @@ static struct platform_device gtwx5715_uart_device = {
101 .resource = gtwx5715_uart_resources, 101 .resource = gtwx5715_uart_resources,
102}; 102};
103 103
104
105void __init gtwx5715_map_io(void)
106{
107 ixp4xx_map_io();
108}
109
110static struct flash_platform_data gtwx5715_flash_data = { 104static struct flash_platform_data gtwx5715_flash_data = {
111 .map_name = "cfi_probe", 105 .map_name = "cfi_probe",
112 .width = 2, 106 .width = 2,
@@ -144,7 +138,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
144 .phys_ram = PHYS_OFFSET, 138 .phys_ram = PHYS_OFFSET,
145 .phys_io = IXP4XX_UART2_BASE_PHYS, 139 .phys_io = IXP4XX_UART2_BASE_PHYS,
146 .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc, 140 .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc,
147 .map_io = gtwx5715_map_io, 141 .map_io = ixp4xx_map_io,
148 .init_irq = ixp4xx_init_irq, 142 .init_irq = ixp4xx_init_irq,
149 .timer = &ixp4xx_timer, 143 .timer = &ixp4xx_timer,
150 .boot_params = 0x0100, 144 .boot_params = 0x0100,
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index c2ab9ebb5980..f9a1d3e7d692 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -27,14 +27,10 @@
27 27
28void __init ixdp425_pci_preinit(void) 28void __init ixdp425_pci_preinit(void)
29{ 29{
30 gpio_line_config(IXDP425_PCI_INTA_PIN, 30 set_irq_type(IRQ_IXDP425_PCI_INTA, IRQT_LOW);
31 IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); 31 set_irq_type(IRQ_IXDP425_PCI_INTB, IRQT_LOW);
32 gpio_line_config(IXDP425_PCI_INTB_PIN, 32 set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW);
33 IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); 33 set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW);
34 gpio_line_config(IXDP425_PCI_INTC_PIN,
35 IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
36 gpio_line_config(IXDP425_PCI_INTD_PIN,
37 IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
38 34
39 gpio_line_isr_clear(IXDP425_PCI_INTA_PIN); 35 gpio_line_isr_clear(IXDP425_PCI_INTA_PIN);
40 gpio_line_isr_clear(IXDP425_PCI_INTB_PIN); 36 gpio_line_isr_clear(IXDP425_PCI_INTB_PIN);
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index fa0646c8693b..6c14ff3c23a0 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -24,11 +24,6 @@
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/mach/flash.h> 25#include <asm/mach/flash.h>
26 26
27void __init ixdp425_map_io(void)
28{
29 ixp4xx_map_io();
30}
31
32static struct flash_platform_data ixdp425_flash_data = { 27static struct flash_platform_data ixdp425_flash_data = {
33 .map_name = "cfi_probe", 28 .map_name = "cfi_probe",
34 .width = 2, 29 .width = 2,
@@ -133,7 +128,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
133 .phys_ram = PHYS_OFFSET, 128 .phys_ram = PHYS_OFFSET,
134 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, 129 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
135 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, 130 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
136 .map_io = ixdp425_map_io, 131 .map_io = ixp4xx_map_io,
137 .init_irq = ixp4xx_init_irq, 132 .init_irq = ixp4xx_init_irq,
138 .timer = &ixp4xx_timer, 133 .timer = &ixp4xx_timer,
139 .boot_params = 0x0100, 134 .boot_params = 0x0100,
@@ -145,7 +140,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
145 .phys_ram = PHYS_OFFSET, 140 .phys_ram = PHYS_OFFSET,
146 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, 141 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
147 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, 142 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
148 .map_io = ixdp425_map_io, 143 .map_io = ixp4xx_map_io,
149 .init_irq = ixp4xx_init_irq, 144 .init_irq = ixp4xx_init_irq,
150 .timer = &ixp4xx_timer, 145 .timer = &ixp4xx_timer,
151 .boot_params = 0x0100, 146 .boot_params = 0x0100,
@@ -157,7 +152,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
157 .phys_ram = PHYS_OFFSET, 152 .phys_ram = PHYS_OFFSET,
158 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, 153 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
159 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, 154 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
160 .map_io = ixdp425_map_io, 155 .map_io = ixp4xx_map_io,
161 .init_irq = ixp4xx_init_irq, 156 .init_irq = ixp4xx_init_irq,
162 .timer = &ixp4xx_timer, 157 .timer = &ixp4xx_timer,
163 .boot_params = 0x0100, 158 .boot_params = 0x0100,
@@ -176,7 +171,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
176 .phys_ram = PHYS_OFFSET, 171 .phys_ram = PHYS_OFFSET,
177 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, 172 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
178 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, 173 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
179 .map_io = ixdp425_map_io, 174 .map_io = ixp4xx_map_io,
180 .init_irq = ixp4xx_init_irq, 175 .init_irq = ixp4xx_init_irq,
181 .timer = &ixp4xx_timer, 176 .timer = &ixp4xx_timer,
182 .boot_params = 0x0100, 177 .boot_params = 0x0100,
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index ce4563f00676..fe5e7660de1d 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -29,8 +29,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
29 29
30void __init ixdpg425_pci_preinit(void) 30void __init ixdpg425_pci_preinit(void)
31{ 31{
32 gpio_line_config(6, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); 32 set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
33 gpio_line_config(7, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); 33 set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW);
34 34
35 gpio_line_isr_clear(6); 35 gpio_line_isr_clear(6);
36 gpio_line_isr_clear(7); 36 gpio_line_isr_clear(7);
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 9a66050e887d..f59608268751 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -388,6 +388,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
388 unsigned long hclk, 388 unsigned long hclk,
389 unsigned long pclk) 389 unsigned long pclk)
390{ 390{
391 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
391 struct clk *clkp = init_clocks; 392 struct clk *clkp = init_clocks;
392 int ptr; 393 int ptr;
393 int ret; 394 int ret;
@@ -446,5 +447,13 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
446 } 447 }
447 } 448 }
448 449
450 /* show the clock-slow value */
451
452 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
453 print_mhz(xtal / ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
454 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
455 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
456 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
457
449 return 0; 458 return 0;
450} 459}
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c
index b018a1f680ce..c67e0979aec3 100644
--- a/arch/arm/mach-s3c2410/s3c2440-clock.c
+++ b/arch/arm/mach-s3c2410/s3c2440-clock.c
@@ -68,6 +68,7 @@ static struct clk s3c2440_clk_ac97 = {
68static int s3c2440_clk_add(struct sys_device *sysdev) 68static int s3c2440_clk_add(struct sys_device *sysdev)
69{ 69{
70 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); 70 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
71 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
71 struct clk *clk_h; 72 struct clk *clk_h;
72 struct clk *clk_p; 73 struct clk *clk_p;
73 struct clk *clk_xtal; 74 struct clk *clk_xtal;
@@ -80,8 +81,9 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
80 81
81 s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate); 82 s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
82 83
83 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", 84 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",
84 print_mhz(s3c2440_clk_upll.rate)); 85 print_mhz(s3c2440_clk_upll.rate),
86 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
85 87
86 clk_p = clk_get(NULL, "pclk"); 88 clk_p = clk_get(NULL, "pclk");
87 clk_h = clk_get(NULL, "hclk"); 89 clk_h = clk_get(NULL, "hclk");
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 81f4a8a2d34b..4b39d867ac14 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -45,7 +45,7 @@
45 45
46#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0) 46#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
47 47
48#define LDSTH_I_BIT(i) (i & (1 << 22)) /* half-word immed */ 48#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
49#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */ 49#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
50 50
51#define RN_BITS(i) ((i >> 16) & 15) /* Rn */ 51#define RN_BITS(i) ((i >> 16) & 15) /* Rn */
@@ -68,6 +68,7 @@ static unsigned long ai_sys;
68static unsigned long ai_skipped; 68static unsigned long ai_skipped;
69static unsigned long ai_half; 69static unsigned long ai_half;
70static unsigned long ai_word; 70static unsigned long ai_word;
71static unsigned long ai_dword;
71static unsigned long ai_multi; 72static unsigned long ai_multi;
72static int ai_usermode; 73static int ai_usermode;
73 74
@@ -93,6 +94,8 @@ proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
93 p += sprintf(p, "Skipped:\t%lu\n", ai_skipped); 94 p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
94 p += sprintf(p, "Half:\t\t%lu\n", ai_half); 95 p += sprintf(p, "Half:\t\t%lu\n", ai_half);
95 p += sprintf(p, "Word:\t\t%lu\n", ai_word); 96 p += sprintf(p, "Word:\t\t%lu\n", ai_word);
97 if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
98 p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
96 p += sprintf(p, "Multi:\t\t%lu\n", ai_multi); 99 p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
97 p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode, 100 p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
98 usermode_action[ai_usermode]); 101 usermode_action[ai_usermode]);
@@ -283,12 +286,6 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r
283{ 286{
284 unsigned int rd = RD_BITS(instr); 287 unsigned int rd = RD_BITS(instr);
285 288
286 if ((instr & 0x01f00ff0) == 0x01000090)
287 goto swp;
288
289 if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0)
290 goto bad;
291
292 ai_half += 1; 289 ai_half += 1;
293 290
294 if (user_mode(regs)) 291 if (user_mode(regs))
@@ -323,10 +320,47 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r
323 320
324 return TYPE_LDST; 321 return TYPE_LDST;
325 322
326 swp: 323 fault:
327 printk(KERN_ERR "Alignment trap: not handling swp instruction\n"); 324 return TYPE_FAULT;
328 bad: 325}
329 return TYPE_ERROR; 326
327static int
328do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
329 struct pt_regs *regs)
330{
331 unsigned int rd = RD_BITS(instr);
332
333 ai_dword += 1;
334
335 if (user_mode(regs))
336 goto user;
337
338 if ((instr & 0xf0) == 0xd0) {
339 unsigned long val;
340 get32_unaligned_check(val, addr);
341 regs->uregs[rd] = val;
342 get32_unaligned_check(val, addr+4);
343 regs->uregs[rd+1] = val;
344 } else {
345 put32_unaligned_check(regs->uregs[rd], addr);
346 put32_unaligned_check(regs->uregs[rd+1], addr+4);
347 }
348
349 return TYPE_LDST;
350
351 user:
352 if ((instr & 0xf0) == 0xd0) {
353 unsigned long val;
354 get32t_unaligned_check(val, addr);
355 regs->uregs[rd] = val;
356 get32t_unaligned_check(val, addr+4);
357 regs->uregs[rd+1] = val;
358 } else {
359 put32t_unaligned_check(regs->uregs[rd], addr);
360 put32t_unaligned_check(regs->uregs[rd+1], addr+4);
361 }
362
363 return TYPE_LDST;
330 364
331 fault: 365 fault:
332 return TYPE_FAULT; 366 return TYPE_FAULT;
@@ -617,12 +651,20 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
617 regs->ARM_pc += thumb_mode(regs) ? 2 : 4; 651 regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
618 652
619 switch (CODING_BITS(instr)) { 653 switch (CODING_BITS(instr)) {
620 case 0x00000000: /* ldrh or strh */ 654 case 0x00000000: /* 3.13.4 load/store instruction extensions */
621 if (LDSTH_I_BIT(instr)) 655 if (LDSTHD_I_BIT(instr))
622 offset.un = (instr & 0xf00) >> 4 | (instr & 15); 656 offset.un = (instr & 0xf00) >> 4 | (instr & 15);
623 else 657 else
624 offset.un = regs->uregs[RM_BITS(instr)]; 658 offset.un = regs->uregs[RM_BITS(instr)];
625 handler = do_alignment_ldrhstrh; 659
660 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
661 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */
662 handler = do_alignment_ldrhstrh;
663 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
664 (instr & 0x001000f0) == 0x000000f0) /* STRD */
665 handler = do_alignment_ldrdstrd;
666 else
667 goto bad;
626 break; 668 break;
627 669
628 case 0x04000000: /* ldr or str immediate */ 670 case 0x04000000: /* ldr or str immediate */
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index 3c655c54e231..4dae00bf7a56 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -275,11 +275,9 @@ alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
275 int i; 275 int i;
276 276
277 for (i = 0; i < 16; i += 1) { 277 for (i = 0; i < 16; i += 1) {
278 alloc_init_section(virt, phys & SUPERSECTION_MASK, 278 alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
279 prot | PMD_SECT_SUPER);
280 279
281 virt += (PGDIR_SIZE / 2); 280 virt += (PGDIR_SIZE / 2);
282 phys += (PGDIR_SIZE / 2);
283 } 281 }
284} 282}
285 283
diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index 468721d9ebd2..3fb1fb619d2c 100644
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
249 sync 249 sync
250 isync 250 isync
251 251
252 /* Enable L2 HW prefetch 252 /* Enable L2 HW prefetch, if L2 is enabled
253 */ 253 */
254 mfspr r3,SPRN_L2CR
255 andis. r3,r3,L2CR_L2E@h
256 beqlr
254 mfspr r3,SPRN_MSSCR0 257 mfspr r3,SPRN_MSSCR0
255 ori r3,r3,3 258 ori r3,r3,3
256 sync 259 sync
diff --git a/arch/ppc/kernel/l2cr.S b/arch/ppc/kernel/l2cr.S
index c39441048266..861115249b35 100644
--- a/arch/ppc/kernel/l2cr.S
+++ b/arch/ppc/kernel/l2cr.S
@@ -156,6 +156,26 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
156 The bit moved on the 7450..... 156 The bit moved on the 7450.....
157 ****/ 157 ****/
158 158
159BEGIN_FTR_SECTION
160 /* Disable L2 prefetch on some 745x and try to ensure
161 * L2 prefetch engines are idle. As explained by errata
162 * text, we can't be sure they are, we just hope very hard
163 * that well be enough (sic !). At least I noticed Apple
164 * doesn't even bother doing the dcbf's here...
165 */
166 mfspr r4,SPRN_MSSCR0
167 rlwinm r4,r4,0,0,29
168 sync
169 mtspr SPRN_MSSCR0,r4
170 sync
171 isync
172 lis r4,KERNELBASE@h
173 dcbf 0,r4
174 dcbf 0,r4
175 dcbf 0,r4
176 dcbf 0,r4
177END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
178
159 /* TODO: use HW flush assist when available */ 179 /* TODO: use HW flush assist when available */
160 180
161 lis r4,0x0002 181 lis r4,0x0002
@@ -230,7 +250,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
230 oris r3,r3,0x8000 250 oris r3,r3,0x8000
231 mtspr SPRN_L2CR,r3 251 mtspr SPRN_L2CR,r3
232 sync 252 sync
233 253
254 /* Enable L2 HW prefetch on 744x/745x */
255BEGIN_FTR_SECTION
256 mfspr r3,SPRN_MSSCR0
257 ori r3,r3,3
258 sync
259 mtspr SPRN_MSSCR0,r3
260 sync
261 isync
262END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
2344: 2634:
235 264
236 /* Restore HID0[DPM] to whatever it was before */ 265 /* Restore HID0[DPM] to whatever it was before */
diff --git a/arch/ppc64/mm/slb_low.S b/arch/ppc64/mm/slb_low.S
index bab255889c58..698d6b9ed6d1 100644
--- a/arch/ppc64/mm/slb_low.S
+++ b/arch/ppc64/mm/slb_low.S
@@ -97,25 +97,21 @@ BEGIN_FTR_SECTION
97 lhz r9,PACAHIGHHTLBAREAS(r13) 97 lhz r9,PACAHIGHHTLBAREAS(r13)
98 srdi r11,r3,(HTLB_AREA_SHIFT-SID_SHIFT) 98 srdi r11,r3,(HTLB_AREA_SHIFT-SID_SHIFT)
99 srd r9,r9,r11 99 srd r9,r9,r11
100 andi. r9,r9,1 100 lhz r11,PACALOWHTLBAREAS(r13)
101 bne 5f 101 srd r11,r11,r3
102 or r9,r9,r11
103END_FTR_SECTION_IFSET(CPU_FTR_16M_PAGE)
104#endif /* CONFIG_HUGETLB_PAGE */
102 105
103 li r11,SLB_VSID_USER 106 li r11,SLB_VSID_USER
104 107
105 cmpldi r3,16 108#ifdef CONFIG_HUGETLB_PAGE
106 bge 6f 109BEGIN_FTR_SECTION
107 110 rldimi r11,r9,8,55 /* shift masked bit into SLB_VSID_L */
108 lhz r9,PACALOWHTLBAREAS(r13)
109 srd r9,r9,r3
110 andi. r9,r9,1
111
112 beq 6f
113
1145: li r11,SLB_VSID_USER|SLB_VSID_L
115END_FTR_SECTION_IFSET(CPU_FTR_16M_PAGE) 111END_FTR_SECTION_IFSET(CPU_FTR_16M_PAGE)
116#endif /* CONFIG_HUGETLB_PAGE */ 112#endif /* CONFIG_HUGETLB_PAGE */
117 113
1186: ld r9,PACACONTEXTID(r13) 114 ld r9,PACACONTEXTID(r13)
119 rldimi r3,r9,USER_ESID_BITS,0 115 rldimi r3,r9,USER_ESID_BITS,0
120 116
1219: /* r3 = protovsid, r11 = flags, r10 = esid_data, cr7 = <>KERNELBASE */ 1179: /* r3 = protovsid, r11 = flags, r10 = esid_data, cr7 = <>KERNELBASE */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-07 02:23:08 -0400