aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts2
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi6
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi4
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts1
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi9
-rw-r--r--arch/arm/include/asm/delay.h2
-rw-r--r--arch/arm/include/asm/highmem.h7
-rw-r--r--arch/arm/include/asm/mmu_context.h2
-rw-r--r--arch/arm/include/asm/tlbflush.h15
-rw-r--r--arch/arm/kernel/entry-common.S12
-rw-r--r--arch/arm/kernel/head.S2
-rw-r--r--arch/arm/kernel/hw_breakpoint.c6
-rw-r--r--arch/arm/kernel/setup.c24
-rw-r--r--arch/arm/kernel/smp.c3
-rw-r--r--arch/arm/kernel/smp_tlb.c66
-rw-r--r--arch/arm/kvm/vgic.c35
-rw-r--r--arch/arm/lib/delay.c8
-rw-r--r--arch/arm/mach-cns3xxx/core.c16
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/cns3xxx.h16
-rw-r--r--arch/arm/mach-ep93xx/include/mach/uncompress.h10
-rw-r--r--arch/arm/mach-imx/common.h2
-rw-r--r--arch/arm/mach-imx/hotplug.c12
-rw-r--r--arch/arm/mach-imx/src.c12
-rw-r--r--arch/arm/mach-kirkwood/guruplug-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c1
-rw-r--r--arch/arm/mach-msm/timer.c5
-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c8
-rw-r--r--arch/arm/mach-omap1/clock_data.c12
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c20
-rw-r--r--arch/arm/mach-omap2/common.h3
-rw-r--r--arch/arm/mach-omap2/io.c18
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c6
-rw-r--r--arch/arm/mach-omap2/timer.c4
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c1
-rw-r--r--arch/arm/mach-ux500/board-mop500.c12
-rw-r--r--arch/arm/mach-ux500/board-mop500.h1
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c5
-rw-r--r--arch/arm/mm/cache-l2x0.c11
-rw-r--r--arch/arm/mm/context.c3
-rw-r--r--arch/arm/mm/mmu.c73
-rw-r--r--arch/arm/mm/proc-v7.S19
-rw-r--r--arch/mips/Kconfig3
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c5
-rw-r--r--arch/mips/bcm63xx/nvram.c7
-rw-r--r--arch/mips/bcm63xx/setup.c2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h4
-rw-r--r--arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h4
-rw-r--r--arch/mips/include/asm/mipsregs.h209
-rw-r--r--arch/mips/include/asm/signal.h2
-rw-r--r--arch/mips/kernel/Makefile25
-rw-r--r--arch/mips/kernel/cpu-probe.c7
-rw-r--r--arch/mips/kernel/linux32.c2
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/lib/bitops.c16
-rw-r--r--arch/mips/lib/csum_partial.S4
-rw-r--r--arch/s390/include/asm/pgtable.h4
-rw-r--r--arch/s390/lib/uaccess_pt.c83
-rw-r--r--arch/tile/kernel/setup.c25
63 files changed, 674 insertions, 244 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 13b739469c51..1cacda426a0e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1183,9 +1183,9 @@ config ARM_NR_BANKS
1183 default 8 1183 default 8
1184 1184
1185config IWMMXT 1185config IWMMXT
1186 bool "Enable iWMMXt support" 1186 bool "Enable iWMMXt support" if !CPU_PJ4
1187 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1187 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1188 default y if PXA27x || PXA3xx || ARCH_MMP 1188 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1189 help 1189 help
1190 Enable support for iWMMXt context switching at run time if 1190 Enable support for iWMMXt context switching at run time if
1191 running on a CPU that supports it. 1191 running on a CPU that supports it.
@@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420
1439 to deadlock. This workaround puts DSB before executing ISB if 1439 to deadlock. This workaround puts DSB before executing ISB if
1440 an abort may occur on cache maintenance. 1440 an abort may occur on cache maintenance.
1441 1441
1442config ARM_ERRATA_798181
1443 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1444 depends on CPU_V7 && SMP
1445 help
1446 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1447 adequately shooting down all use of the old entries. This
1448 option enables the Linux kernel workaround for this erratum
1449 which sends an IPI to the CPUs that are running the same ASID
1450 as the one being invalidated.
1451
1442endmenu 1452endmenu
1443 1453
1444source "arch/arm/common/Kconfig" 1454source "arch/arm/common/Kconfig"
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index dd0c57dd9f30..3234875824dc 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,7 +54,7 @@
54 }; 54 };
55 55
56 mvsdio@d00d4000 { 56 mvsdio@d00d4000 {
57 pinctrl-0 = <&sdio_pins2>; 57 pinctrl-0 = <&sdio_pins3>;
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 status = "okay"; 59 status = "okay";
60 /* 60 /*
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 8188d138020e..a195debb67d3 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -59,6 +59,12 @@
59 "mpp50", "mpp51", "mpp52"; 59 "mpp50", "mpp51", "mpp52";
60 marvell,function = "sd0"; 60 marvell,function = "sd0";
61 }; 61 };
62
63 sdio_pins3: sdio-pins3 {
64 marvell,pins = "mpp48", "mpp49", "mpp50",
65 "mpp51", "mpp52", "mpp53";
66 marvell,function = "sd0";
67 };
62 }; 68 };
63 69
64 gpio0: gpio@d0018100 { 70 gpio0: gpio@d0018100 {
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 9de93096601a..aaa63d0a8096 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -191,8 +191,8 @@
191 191
192 prcmu: prcmu@80157000 { 192 prcmu: prcmu@80157000 {
193 compatible = "stericsson,db8500-prcmu"; 193 compatible = "stericsson,db8500-prcmu";
194 reg = <0x80157000 0x1000>; 194 reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
195 reg-names = "prcmu"; 195 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
196 interrupts = <0 47 0x4>; 196 interrupts = <0 47 0x4>;
197 #address-cells = <1>; 197 #address-cells = <1>;
198 #size-cells = <1>; 198 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index bd83b8fc7c83..c3573be7b92c 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -77,6 +77,7 @@
77 }; 77 };
78 78
79 nand@3000000 { 79 nand@3000000 {
80 chip-delay = <40>;
80 status = "okay"; 81 status = "okay";
81 82
82 partition@0 { 83 partition@0 {
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 8aad00f81ed9..f7bec3b1ba32 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -13,6 +13,9 @@
13 compatible = "marvell,orion5x"; 13 compatible = "marvell,orion5x";
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 aliases {
17 gpio0 = &gpio0;
18 };
16 intc: interrupt-controller { 19 intc: interrupt-controller {
17 compatible = "marvell,orion-intc", "marvell,intc"; 20 compatible = "marvell,orion-intc", "marvell,intc";
18 interrupt-controller; 21 interrupt-controller;
@@ -32,7 +35,9 @@
32 #gpio-cells = <2>; 35 #gpio-cells = <2>;
33 gpio-controller; 36 gpio-controller;
34 reg = <0x10100 0x40>; 37 reg = <0x10100 0x40>;
35 ngpio = <32>; 38 ngpios = <32>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
36 interrupts = <6>, <7>, <8>, <9>; 41 interrupts = <6>, <7>, <8>, <9>;
37 }; 42 };
38 43
@@ -91,7 +96,7 @@
91 reg = <0x90000 0x10000>, 96 reg = <0x90000 0x10000>,
92 <0xf2200000 0x800>; 97 <0xf2200000 0x800>;
93 reg-names = "regs", "sram"; 98 reg-names = "regs", "sram";
94 interrupts = <22>; 99 interrupts = <28>;
95 status = "okay"; 100 status = "okay";
96 }; 101 };
97 }; 102 };
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index 720799fd3a81..dff714d886d5 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -24,7 +24,7 @@ extern struct arm_delay_ops {
24 void (*delay)(unsigned long); 24 void (*delay)(unsigned long);
25 void (*const_udelay)(unsigned long); 25 void (*const_udelay)(unsigned long);
26 void (*udelay)(unsigned long); 26 void (*udelay)(unsigned long);
27 bool const_clock; 27 unsigned long ticks_per_jiffy;
28} arm_delay_ops; 28} arm_delay_ops;
29 29
30#define __delay(n) arm_delay_ops.delay(n) 30#define __delay(n) arm_delay_ops.delay(n)
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 8c5e828f484d..91b99abe7a95 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page);
41#endif 41#endif
42#endif 42#endif
43 43
44/*
45 * Needed to be able to broadcast the TLB invalidation for kmap.
46 */
47#ifdef CONFIG_ARM_ERRATA_798181
48#undef ARCH_NEEDS_KMAP_HIGH_GET
49#endif
50
44#ifdef ARCH_NEEDS_KMAP_HIGH_GET 51#ifdef ARCH_NEEDS_KMAP_HIGH_GET
45extern void *kmap_high_get(struct page *page); 52extern void *kmap_high_get(struct page *page);
46#else 53#else
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 863a6611323c..a7b85e0d0cc1 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm);
27void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); 27void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
28#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) 28#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
29 29
30DECLARE_PER_CPU(atomic64_t, active_asids);
31
30#else /* !CONFIG_CPU_HAS_ASID */ 32#else /* !CONFIG_CPU_HAS_ASID */
31 33
32#ifdef CONFIG_MMU 34#ifdef CONFIG_MMU
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 4db8c8820f0d..9e9c041358ca 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void)
450 isb(); 450 isb();
451} 451}
452 452
453#ifdef CONFIG_ARM_ERRATA_798181
454static inline void dummy_flush_tlb_a15_erratum(void)
455{
456 /*
457 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
458 */
459 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
460 dsb();
461}
462#else
463static inline void dummy_flush_tlb_a15_erratum(void)
464{
465}
466#endif
467
453/* 468/*
454 * flush_pmd_entry 469 * flush_pmd_entry
455 * 470 *
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 3248cde504ed..fefd7f971437 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old)
276 */ 276 */
277 277
278.macro mcount_enter 278.macro mcount_enter
279/*
280 * This pad compensates for the push {lr} at the call site. Note that we are
281 * unable to unwind through a function which does not otherwise save its lr.
282 */
283 UNWIND(.pad #4)
279 stmdb sp!, {r0-r3, lr} 284 stmdb sp!, {r0-r3, lr}
285 UNWIND(.save {r0-r3, lr})
280.endm 286.endm
281 287
282.macro mcount_get_lr reg 288.macro mcount_get_lr reg
@@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old)
289.endm 295.endm
290 296
291ENTRY(__gnu_mcount_nc) 297ENTRY(__gnu_mcount_nc)
298UNWIND(.fnstart)
292#ifdef CONFIG_DYNAMIC_FTRACE 299#ifdef CONFIG_DYNAMIC_FTRACE
293 mov ip, lr 300 mov ip, lr
294 ldmia sp!, {lr} 301 ldmia sp!, {lr}
@@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc)
296#else 303#else
297 __mcount 304 __mcount
298#endif 305#endif
306UNWIND(.fnend)
299ENDPROC(__gnu_mcount_nc) 307ENDPROC(__gnu_mcount_nc)
300 308
301#ifdef CONFIG_DYNAMIC_FTRACE 309#ifdef CONFIG_DYNAMIC_FTRACE
302ENTRY(ftrace_caller) 310ENTRY(ftrace_caller)
311UNWIND(.fnstart)
303 __ftrace_caller 312 __ftrace_caller
313UNWIND(.fnend)
304ENDPROC(ftrace_caller) 314ENDPROC(ftrace_caller)
305#endif 315#endif
306 316
307#ifdef CONFIG_FUNCTION_GRAPH_TRACER 317#ifdef CONFIG_FUNCTION_GRAPH_TRACER
308ENTRY(ftrace_graph_caller) 318ENTRY(ftrace_graph_caller)
319UNWIND(.fnstart)
309 __ftrace_graph_caller 320 __ftrace_graph_caller
321UNWIND(.fnend)
310ENDPROC(ftrace_graph_caller) 322ENDPROC(ftrace_graph_caller)
311#endif 323#endif
312 324
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index e0eb9a1cae77..8bac553fe213 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -267,7 +267,7 @@ __create_page_tables:
267 addne r6, r6, #1 << SECTION_SHIFT 267 addne r6, r6, #1 << SECTION_SHIFT
268 strne r6, [r3] 268 strne r6, [r3]
269 269
270#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) 270#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
271 sub r4, r4, #4 @ Fixup page table pointer 271 sub r4, r4, #4 @ Fixup page table pointer
272 @ for 64-bit descriptors 272 @ for 64-bit descriptors
273#endif 273#endif
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 96093b75ab90..5dc1aa6f0f7d 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused)
966 } 966 }
967 967
968 if (err) { 968 if (err) {
969 pr_warning("CPU %d debug is powered down!\n", cpu); 969 pr_warn_once("CPU %d debug is powered down!\n", cpu);
970 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); 970 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
971 return; 971 return;
972 } 972 }
@@ -987,7 +987,7 @@ clear_vcr:
987 isb(); 987 isb();
988 988
989 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { 989 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
990 pr_warning("CPU %d failed to disable vector catch\n", cpu); 990 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
991 return; 991 return;
992 } 992 }
993 993
@@ -1007,7 +1007,7 @@ clear_vcr:
1007 } 1007 }
1008 1008
1009 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { 1009 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1010 pr_warning("CPU %d failed to clear debug register pairs\n", cpu); 1010 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1011 return; 1011 return;
1012 } 1012 }
1013 1013
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2e3eda..d343a6c3a6d1 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
353 printk("%s", buf); 353 printk("%s", buf);
354} 354}
355 355
356static void __init cpuid_init_hwcaps(void)
357{
358 unsigned int divide_instrs;
359
360 if (cpu_architecture() < CPU_ARCH_ARMv7)
361 return;
362
363 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
364
365 switch (divide_instrs) {
366 case 2:
367 elf_hwcap |= HWCAP_IDIVA;
368 case 1:
369 elf_hwcap |= HWCAP_IDIVT;
370 }
371}
372
356static void __init feat_v6_fixup(void) 373static void __init feat_v6_fixup(void)
357{ 374{
358 int id = read_cpuid_id(); 375 int id = read_cpuid_id();
@@ -483,8 +500,11 @@ static void __init setup_processor(void)
483 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", 500 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
484 list->elf_name, ENDIANNESS); 501 list->elf_name, ENDIANNESS);
485 elf_hwcap = list->elf_hwcap; 502 elf_hwcap = list->elf_hwcap;
503
504 cpuid_init_hwcaps();
505
486#ifndef CONFIG_ARM_THUMB 506#ifndef CONFIG_ARM_THUMB
487 elf_hwcap &= ~HWCAP_THUMB; 507 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
488#endif 508#endif
489 509
490 feat_v6_fixup(); 510 feat_v6_fixup();
@@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
524 size -= start & ~PAGE_MASK; 544 size -= start & ~PAGE_MASK;
525 bank->start = PAGE_ALIGN(start); 545 bank->start = PAGE_ALIGN(start);
526 546
527#ifndef CONFIG_LPAE 547#ifndef CONFIG_ARM_LPAE
528 if (bank->start + size < bank->start) { 548 if (bank->start + size < bank->start) {
529 printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " 549 printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
530 "32-bit physical address space\n", (long long)start); 550 "32-bit physical address space\n", (long long)start);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 79078edbb9bc..1f2ccccaf009 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb,
673 if (freq->flags & CPUFREQ_CONST_LOOPS) 673 if (freq->flags & CPUFREQ_CONST_LOOPS)
674 return NOTIFY_OK; 674 return NOTIFY_OK;
675 675
676 if (arm_delay_ops.const_clock)
677 return NOTIFY_OK;
678
679 if (!per_cpu(l_p_j_ref, cpu)) { 676 if (!per_cpu(l_p_j_ref, cpu)) {
680 per_cpu(l_p_j_ref, cpu) = 677 per_cpu(l_p_j_ref, cpu) =
681 per_cpu(cpu_data, cpu).loops_per_jiffy; 678 per_cpu(cpu_data, cpu).loops_per_jiffy;
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index bd0300531399..e82e1d248772 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -12,6 +12,7 @@
12 12
13#include <asm/smp_plat.h> 13#include <asm/smp_plat.h>
14#include <asm/tlbflush.h> 14#include <asm/tlbflush.h>
15#include <asm/mmu_context.h>
15 16
16/**********************************************************************/ 17/**********************************************************************/
17 18
@@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored)
69 local_flush_bp_all(); 70 local_flush_bp_all();
70} 71}
71 72
73#ifdef CONFIG_ARM_ERRATA_798181
74static int erratum_a15_798181(void)
75{
76 unsigned int midr = read_cpuid_id();
77
78 /* Cortex-A15 r0p0..r3p2 affected */
79 if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
80 return 0;
81 return 1;
82}
83#else
84static int erratum_a15_798181(void)
85{
86 return 0;
87}
88#endif
89
90static void ipi_flush_tlb_a15_erratum(void *arg)
91{
92 dmb();
93}
94
95static void broadcast_tlb_a15_erratum(void)
96{
97 if (!erratum_a15_798181())
98 return;
99
100 dummy_flush_tlb_a15_erratum();
101 smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
102 NULL, 1);
103}
104
105static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
106{
107 int cpu;
108 cpumask_t mask = { CPU_BITS_NONE };
109
110 if (!erratum_a15_798181())
111 return;
112
113 dummy_flush_tlb_a15_erratum();
114 for_each_online_cpu(cpu) {
115 if (cpu == smp_processor_id())
116 continue;
117 /*
118 * We only need to send an IPI if the other CPUs are running
119 * the same ASID as the one being invalidated. There is no
120 * need for locking around the active_asids check since the
121 * switch_mm() function has at least one dmb() (as required by
122 * this workaround) in case a context switch happens on
123 * another CPU after the condition below.
124 */
125 if (atomic64_read(&mm->context.id) ==
126 atomic64_read(&per_cpu(active_asids, cpu)))
127 cpumask_set_cpu(cpu, &mask);
128 }
129 smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
130}
131
72void flush_tlb_all(void) 132void flush_tlb_all(void)
73{ 133{
74 if (tlb_ops_need_broadcast()) 134 if (tlb_ops_need_broadcast())
75 on_each_cpu(ipi_flush_tlb_all, NULL, 1); 135 on_each_cpu(ipi_flush_tlb_all, NULL, 1);
76 else 136 else
77 local_flush_tlb_all(); 137 local_flush_tlb_all();
138 broadcast_tlb_a15_erratum();
78} 139}
79 140
80void flush_tlb_mm(struct mm_struct *mm) 141void flush_tlb_mm(struct mm_struct *mm)
@@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm)
83 on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1); 144 on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
84 else 145 else
85 local_flush_tlb_mm(mm); 146 local_flush_tlb_mm(mm);
147 broadcast_tlb_mm_a15_erratum(mm);
86} 148}
87 149
88void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 150void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
@@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
95 &ta, 1); 157 &ta, 1);
96 } else 158 } else
97 local_flush_tlb_page(vma, uaddr); 159 local_flush_tlb_page(vma, uaddr);
160 broadcast_tlb_mm_a15_erratum(vma->vm_mm);
98} 161}
99 162
100void flush_tlb_kernel_page(unsigned long kaddr) 163void flush_tlb_kernel_page(unsigned long kaddr)
@@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr)
105 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); 168 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
106 } else 169 } else
107 local_flush_tlb_kernel_page(kaddr); 170 local_flush_tlb_kernel_page(kaddr);
171 broadcast_tlb_a15_erratum();
108} 172}
109 173
110void flush_tlb_range(struct vm_area_struct *vma, 174void flush_tlb_range(struct vm_area_struct *vma,
@@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
119 &ta, 1); 183 &ta, 1);
120 } else 184 } else
121 local_flush_tlb_range(vma, start, end); 185 local_flush_tlb_range(vma, start, end);
186 broadcast_tlb_mm_a15_erratum(vma->vm_mm);
122} 187}
123 188
124void flush_tlb_kernel_range(unsigned long start, unsigned long end) 189void flush_tlb_kernel_range(unsigned long start, unsigned long end)
@@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
130 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); 195 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
131 } else 196 } else
132 local_flush_tlb_kernel_range(start, end); 197 local_flush_tlb_kernel_range(start, end);
198 broadcast_tlb_a15_erratum();
133} 199}
134 200
135void flush_bp_all(void) 201void flush_bp_all(void)
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
index c9a17316e9fe..0e4cfe123b38 100644
--- a/arch/arm/kvm/vgic.c
+++ b/arch/arm/kvm/vgic.c
@@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
883 lr, irq, vgic_cpu->vgic_lr[lr]); 883 lr, irq, vgic_cpu->vgic_lr[lr]);
884 BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); 884 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
885 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT; 885 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
886 886 return true;
887 goto out;
888 } 887 }
889 888
890 /* Try to use another LR for this interrupt */ 889 /* Try to use another LR for this interrupt */
@@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
898 vgic_cpu->vgic_irq_lr_map[irq] = lr; 897 vgic_cpu->vgic_irq_lr_map[irq] = lr;
899 set_bit(lr, vgic_cpu->lr_used); 898 set_bit(lr, vgic_cpu->lr_used);
900 899
901out:
902 if (!vgic_irq_is_edge(vcpu, irq)) 900 if (!vgic_irq_is_edge(vcpu, irq))
903 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; 901 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
904 902
@@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1018 1016
1019 kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr); 1017 kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
1020 1018
1021 /*
1022 * We do not need to take the distributor lock here, since the only
1023 * action we perform is clearing the irq_active_bit for an EOIed
1024 * level interrupt. There is a potential race with
1025 * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
1026 * check if the interrupt is already active. Two possibilities:
1027 *
1028 * - The queuing is occurring on the same vcpu: cannot happen,
1029 * as we're already in the context of this vcpu, and
1030 * executing the handler
1031 * - The interrupt has been migrated to another vcpu, and we
1032 * ignore this interrupt for this run. Big deal. It is still
1033 * pending though, and will get considered when this vcpu
1034 * exits.
1035 */
1036 if (vgic_cpu->vgic_misr & GICH_MISR_EOI) { 1019 if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
1037 /* 1020 /*
1038 * Some level interrupts have been EOIed. Clear their 1021 * Some level interrupts have been EOIed. Clear their
@@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1054 } else { 1037 } else {
1055 vgic_cpu_irq_clear(vcpu, irq); 1038 vgic_cpu_irq_clear(vcpu, irq);
1056 } 1039 }
1040
1041 /*
1042 * Despite being EOIed, the LR may not have
1043 * been marked as empty.
1044 */
1045 set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
1046 vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
1057 } 1047 }
1058 } 1048 }
1059 1049
@@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1064} 1054}
1065 1055
1066/* 1056/*
1067 * Sync back the VGIC state after a guest run. We do not really touch 1057 * Sync back the VGIC state after a guest run. The distributor lock is
1068 * the distributor here (the irq_pending_on_cpu bit is safe to set), 1058 * needed so we don't get preempted in the middle of the state processing.
1069 * so there is no need for taking its lock.
1070 */ 1059 */
1071static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) 1060static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1072{ 1061{
@@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1112 1101
1113void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) 1102void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1114{ 1103{
1104 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1105
1115 if (!irqchip_in_kernel(vcpu->kvm)) 1106 if (!irqchip_in_kernel(vcpu->kvm))
1116 return; 1107 return;
1117 1108
1109 spin_lock(&dist->lock);
1118 __kvm_vgic_sync_hwstate(vcpu); 1110 __kvm_vgic_sync_hwstate(vcpu);
1111 spin_unlock(&dist->lock);
1119} 1112}
1120 1113
1121int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) 1114int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 6b93f6a1a3c7..64dbfa57204a 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles)
58static void __timer_const_udelay(unsigned long xloops) 58static void __timer_const_udelay(unsigned long xloops)
59{ 59{
60 unsigned long long loops = xloops; 60 unsigned long long loops = xloops;
61 loops *= loops_per_jiffy; 61 loops *= arm_delay_ops.ticks_per_jiffy;
62 __timer_delay(loops >> UDELAY_SHIFT); 62 __timer_delay(loops >> UDELAY_SHIFT);
63} 63}
64 64
@@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
73 pr_info("Switching to timer-based delay loop\n"); 73 pr_info("Switching to timer-based delay loop\n");
74 delay_timer = timer; 74 delay_timer = timer;
75 lpj_fine = timer->freq / HZ; 75 lpj_fine = timer->freq / HZ;
76 loops_per_jiffy = lpj_fine; 76
77 /* cpufreq may scale loops_per_jiffy, so keep a private copy */
78 arm_delay_ops.ticks_per_jiffy = lpj_fine;
77 arm_delay_ops.delay = __timer_delay; 79 arm_delay_ops.delay = __timer_delay;
78 arm_delay_ops.const_udelay = __timer_const_udelay; 80 arm_delay_ops.const_udelay = __timer_const_udelay;
79 arm_delay_ops.udelay = __timer_udelay; 81 arm_delay_ops.udelay = __timer_udelay;
80 arm_delay_ops.const_clock = true; 82
81 delay_calibrated = true; 83 delay_calibrated = true;
82 } else { 84 } else {
83 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); 85 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e698f26cc0cb..52e4bb5cf12d 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -22,19 +22,9 @@
22 22
23static struct map_desc cns3xxx_io_desc[] __initdata = { 23static struct map_desc cns3xxx_io_desc[] __initdata = {
24 { 24 {
25 .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, 25 .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
26 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE), 26 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
27 .length = SZ_4K, 27 .length = SZ_8K,
28 .type = MT_DEVICE,
29 }, {
30 .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
31 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
32 .length = SZ_4K,
33 .type = MT_DEVICE,
34 }, {
35 .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
36 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
37 .length = SZ_4K,
38 .type = MT_DEVICE, 28 .type = MT_DEVICE,
39 }, { 29 }, {
40 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, 30 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 191c8e57f289..b1021aafa481 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -94,10 +94,10 @@
94#define RTC_INTR_STS_OFFSET 0x34 94#define RTC_INTR_STS_OFFSET 0x34
95 95
96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ 96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
97#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ 97#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
98 98
99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ 99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
100#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 100#define CNS3XXX_PM_BASE_VIRT 0xFB001000
101 101
102#define PM_CLK_GATE_OFFSET 0x00 102#define PM_CLK_GATE_OFFSET 0x00
103#define PM_SOFT_RST_OFFSET 0x04 103#define PM_SOFT_RST_OFFSET 0x04
@@ -109,7 +109,7 @@
109#define PM_PLL_HM_PD_OFFSET 0x1C 109#define PM_PLL_HM_PD_OFFSET 0x1C
110 110
111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ 111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
112#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 112#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
113 113
114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ 114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
@@ -130,7 +130,7 @@
130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
131 131
132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ 132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
134 134
135#define TIMER1_COUNTER_OFFSET 0x00 135#define TIMER1_COUNTER_OFFSET 0x00
136#define TIMER1_AUTO_RELOAD_OFFSET 0x04 136#define TIMER1_AUTO_RELOAD_OFFSET 0x04
@@ -227,16 +227,16 @@
227 * Testchip peripheral and fpga gic regions 227 * Testchip peripheral and fpga gic regions
228 */ 228 */
229#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ 229#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
230#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 230#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
231 231
232#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ 232#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
233#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 233#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
234 234
235#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 235#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
236#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 236#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
237 237
238#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ 238#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
239#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 239#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
240 240
241#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ 241#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
242#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 242#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index d2afb4dd82ab..b5cc77d2380b 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
47 47
48static inline void putc(int c) 48static inline void putc(int c)
49{ 49{
50 /* Transmit fifo not full? */ 50 int i;
51 while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF) 51
52 ; 52 for (i = 0; i < 10000; i++) {
53 /* Transmit fifo not full? */
54 if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
55 break;
56 }
53 57
54 __raw_writeb(c, PHYS_UART_DATA); 58 __raw_writeb(c, PHYS_UART_DATA);
55} 59}
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5a800bfcec5b..5bf4a97ab241 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -110,6 +110,8 @@ void tzic_handle_irq(struct pt_regs *);
110 110
111extern void imx_enable_cpu(int cpu, bool enable); 111extern void imx_enable_cpu(int cpu, bool enable);
112extern void imx_set_cpu_jump(int cpu, void *jump_addr); 112extern void imx_set_cpu_jump(int cpu, void *jump_addr);
113extern u32 imx_get_cpu_arg(int cpu);
114extern void imx_set_cpu_arg(int cpu, u32 arg);
113extern void v7_cpu_resume(void); 115extern void v7_cpu_resume(void);
114extern u32 *pl310_get_save_ptr(void); 116extern u32 *pl310_get_save_ptr(void);
115#ifdef CONFIG_SMP 117#ifdef CONFIG_SMP
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 7bc5fe15dda2..361a253e2b63 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void)
46void imx_cpu_die(unsigned int cpu) 46void imx_cpu_die(unsigned int cpu)
47{ 47{
48 cpu_enter_lowpower(); 48 cpu_enter_lowpower();
49 /*
50 * We use the cpu jumping argument register to sync with
51 * imx_cpu_kill() which is running on cpu0 and waiting for
52 * the register being cleared to kill the cpu.
53 */
54 imx_set_cpu_arg(cpu, ~0);
49 cpu_do_idle(); 55 cpu_do_idle();
50} 56}
51 57
52int imx_cpu_kill(unsigned int cpu) 58int imx_cpu_kill(unsigned int cpu)
53{ 59{
60 unsigned long timeout = jiffies + msecs_to_jiffies(50);
61
62 while (imx_get_cpu_arg(cpu) == 0)
63 if (time_after(jiffies, timeout))
64 return 0;
54 imx_enable_cpu(cpu, false); 65 imx_enable_cpu(cpu, false);
66 imx_set_cpu_arg(cpu, 0);
55 return 1; 67 return 1;
56} 68}
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index e15f1555c59b..09a742f8c7ab 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -43,6 +43,18 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
43 src_base + SRC_GPR1 + cpu * 8); 43 src_base + SRC_GPR1 + cpu * 8);
44} 44}
45 45
46u32 imx_get_cpu_arg(int cpu)
47{
48 cpu = cpu_logical_map(cpu);
49 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
50}
51
52void imx_set_cpu_arg(int cpu, u32 arg)
53{
54 cpu = cpu_logical_map(cpu);
55 writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
56}
57
46void imx_src_prepare_restart(void) 58void imx_src_prepare_restart(void)
47{ 59{
48 u32 val; 60 u32 val;
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 1c6e736cbbf8..08dd739aa709 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = {
53 53
54static struct mvsdio_platform_data guruplug_mvsdio_data = { 54static struct mvsdio_platform_data guruplug_mvsdio_data = {
55 /* unfortunately the CD signal has not been connected */ 55 /* unfortunately the CD signal has not been connected */
56 .gpio_card_detect = -1,
57 .gpio_write_protect = -1,
56}; 58};
57 59
58static struct gpio_led guruplug_led_pins[] = { 60static struct gpio_led guruplug_led_pins[] = {
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 8ddd69fdc937..6a6eb548307d 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = {
55 55
56static struct mvsdio_platform_data openrd_mvsdio_data = { 56static struct mvsdio_platform_data openrd_mvsdio_data = {
57 .gpio_card_detect = 29, /* MPP29 used as SD card detect */ 57 .gpio_card_detect = 29, /* MPP29 used as SD card detect */
58 .gpio_write_protect = -1,
58}; 59};
59 60
60static unsigned int openrd_mpp_config[] __initdata = { 61static unsigned int openrd_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index c7d93b48926b..d24223166e06 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = {
69 69
70static struct mvsdio_platform_data rd88f6281_mvsdio_data = { 70static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
71 .gpio_card_detect = 28, 71 .gpio_card_detect = 28,
72 .gpio_write_protect = -1,
72}; 73};
73 74
74static unsigned int rd88f6281_mpp_config[] __initdata = { 75static unsigned int rd88f6281_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 2969027f02fa..f9fd77e8f1f5 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles,
62{ 62{
63 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 63 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
64 64
65 writel_relaxed(0, event_base + TIMER_CLEAR); 65 ctrl &= ~TIMER_ENABLE_EN;
66 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
67
68 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
66 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); 69 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
67 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); 70 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
68 return 0; 71 return 0;
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 274ff58271de..6a9195e10579 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -44,6 +44,8 @@
44 44
45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
46 46
47#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
48
47#define ACTIVE_DOORBELLS (8) 49#define ACTIVE_DOORBELLS (8)
48 50
49static DEFINE_RAW_SPINLOCK(irq_controller_lock); 51static DEFINE_RAW_SPINLOCK(irq_controller_lock);
@@ -62,7 +64,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
62#ifdef CONFIG_SMP 64#ifdef CONFIG_SMP
63 irq_hw_number_t hwirq = irqd_to_hwirq(d); 65 irq_hw_number_t hwirq = irqd_to_hwirq(d);
64 66
65 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 67 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
66 writel(hwirq, main_int_base + 68 writel(hwirq, main_int_base +
67 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 69 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
68 else 70 else
@@ -79,7 +81,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
79#ifdef CONFIG_SMP 81#ifdef CONFIG_SMP
80 irq_hw_number_t hwirq = irqd_to_hwirq(d); 82 irq_hw_number_t hwirq = irqd_to_hwirq(d);
81 83
82 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 84 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
83 writel(hwirq, main_int_base + 85 writel(hwirq, main_int_base +
84 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 86 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
85 else 87 else
@@ -147,7 +149,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
147 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 149 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
148 irq_set_status_flags(virq, IRQ_LEVEL); 150 irq_set_status_flags(virq, IRQ_LEVEL);
149 151
150 if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { 152 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
151 irq_set_percpu_devid(virq); 153 irq_set_percpu_devid(virq);
152 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 154 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
153 handle_percpu_devid_irq); 155 handle_percpu_devid_irq);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index cb7c6ae2e3fc..6c4f766365a2 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -543,15 +543,6 @@ static struct clk usb_dc_ck = {
543 /* Direct from ULPD, no parent */ 543 /* Direct from ULPD, no parent */
544 .rate = 48000000, 544 .rate = 48000000,
545 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), 545 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
546 .enable_bit = USB_REQ_EN_SHIFT,
547};
548
549static struct clk usb_dc_ck7xx = {
550 .name = "usb_dc_ck",
551 .ops = &clkops_generic,
552 /* Direct from ULPD, no parent */
553 .rate = 48000000,
554 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
555 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, 546 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
556}; 547};
557 548
@@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
727 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), 718 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
728 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), 719 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
729 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), 720 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
730 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), 721 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
731 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
732 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), 722 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
733 CLK(NULL, "mclk", &mclk_16xx, CK_16XX), 723 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
734 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), 724 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 3d58f335f173..0c6834ae1fc4 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -52,6 +52,13 @@
52 */ 52 */
53#define OMAP4_DPLL_ABE_DEFFREQ 98304000 53#define OMAP4_DPLL_ABE_DEFFREQ 98304000
54 54
55/*
56 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
57 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
58 * locked frequency for the USB DPLL is 960MHz.
59 */
60#define OMAP4_DPLL_USB_DEFFREQ 960000000
61
55/* Root clocks */ 62/* Root clocks */
56 63
57DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); 64DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
@@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1011 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, 1018 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1012 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); 1019 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1013 1020
1021DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1022 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1023 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1024
1014DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, 1025DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1015 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 1026 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1016 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1027 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = {
1538 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), 1549 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
1539 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), 1550 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
1540 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), 1551 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
1552 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
1541 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 1553 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
1542 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 1554 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
1543 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 1555 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
@@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void)
1705 if (rc) 1717 if (rc)
1706 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 1718 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
1707 1719
1720 /*
1721 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1722 * domain can transition to retention state when not in use.
1723 */
1724 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1725 if (rc)
1726 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1727
1708 return 0; 1728 return 0;
1709} 1729}
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 40f4a03d728f..d6ba13e1c540 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -293,5 +293,8 @@ extern void omap_reserve(void);
293struct omap_hwmod; 293struct omap_hwmod;
294extern int omap_dss_reset(struct omap_hwmod *); 294extern int omap_dss_reset(struct omap_hwmod *);
295 295
296/* SoC specific clock initializer */
297extern int (*omap_clk_init)(void);
298
296#endif /* __ASSEMBLER__ */ 299#endif /* __ASSEMBLER__ */
297#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ 300#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2c3fdd65387b..5c445ca1e271 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,6 +55,12 @@
55#include "prm44xx.h" 55#include "prm44xx.h"
56 56
57/* 57/*
58 * omap_clk_init: points to a function that does the SoC-specific
59 * clock initializations
60 */
61int (*omap_clk_init)(void);
62
63/*
58 * The machine specific code may provide the extra mapping besides the 64 * The machine specific code may provide the extra mapping besides the
59 * default mapping provided here. 65 * default mapping provided here.
60 */ 66 */
@@ -397,7 +403,7 @@ void __init omap2420_init_early(void)
397 omap242x_clockdomains_init(); 403 omap242x_clockdomains_init();
398 omap2420_hwmod_init(); 404 omap2420_hwmod_init();
399 omap_hwmod_init_postsetup(); 405 omap_hwmod_init_postsetup();
400 omap2420_clk_init(); 406 omap_clk_init = omap2420_clk_init;
401} 407}
402 408
403void __init omap2420_init_late(void) 409void __init omap2420_init_late(void)
@@ -427,7 +433,7 @@ void __init omap2430_init_early(void)
427 omap243x_clockdomains_init(); 433 omap243x_clockdomains_init();
428 omap2430_hwmod_init(); 434 omap2430_hwmod_init();
429 omap_hwmod_init_postsetup(); 435 omap_hwmod_init_postsetup();
430 omap2430_clk_init(); 436 omap_clk_init = omap2430_clk_init;
431} 437}
432 438
433void __init omap2430_init_late(void) 439void __init omap2430_init_late(void)
@@ -462,7 +468,7 @@ void __init omap3_init_early(void)
462 omap3xxx_clockdomains_init(); 468 omap3xxx_clockdomains_init();
463 omap3xxx_hwmod_init(); 469 omap3xxx_hwmod_init();
464 omap_hwmod_init_postsetup(); 470 omap_hwmod_init_postsetup();
465 omap3xxx_clk_init(); 471 omap_clk_init = omap3xxx_clk_init;
466} 472}
467 473
468void __init omap3430_init_early(void) 474void __init omap3430_init_early(void)
@@ -500,7 +506,7 @@ void __init ti81xx_init_early(void)
500 omap3xxx_clockdomains_init(); 506 omap3xxx_clockdomains_init();
501 omap3xxx_hwmod_init(); 507 omap3xxx_hwmod_init();
502 omap_hwmod_init_postsetup(); 508 omap_hwmod_init_postsetup();
503 omap3xxx_clk_init(); 509 omap_clk_init = omap3xxx_clk_init;
504} 510}
505 511
506void __init omap3_init_late(void) 512void __init omap3_init_late(void)
@@ -568,7 +574,7 @@ void __init am33xx_init_early(void)
568 am33xx_clockdomains_init(); 574 am33xx_clockdomains_init();
569 am33xx_hwmod_init(); 575 am33xx_hwmod_init();
570 omap_hwmod_init_postsetup(); 576 omap_hwmod_init_postsetup();
571 am33xx_clk_init(); 577 omap_clk_init = am33xx_clk_init;
572} 578}
573#endif 579#endif
574 580
@@ -593,7 +599,7 @@ void __init omap4430_init_early(void)
593 omap44xx_clockdomains_init(); 599 omap44xx_clockdomains_init();
594 omap44xx_hwmod_init(); 600 omap44xx_hwmod_init();
595 omap_hwmod_init_postsetup(); 601 omap_hwmod_init_postsetup();
596 omap4xxx_clk_init(); 602 omap_clk_init = omap4xxx_clk_init;
597} 603}
598 604
599void __init omap4430_init_late(void) 605void __init omap4430_init_late(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c2c798c08c2b..a202a4785104 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
1368 } 1368 }
1369 1369
1370 if (sf & SYSC_HAS_MIDLEMODE) { 1370 if (sf & SYSC_HAS_MIDLEMODE) {
1371 if (oh->flags & HWMOD_SWSUP_MSTANDBY) { 1371 if (oh->flags & HWMOD_FORCE_MSTANDBY) {
1372 idlemode = HWMOD_IDLEMODE_FORCE;
1373 } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
1372 idlemode = HWMOD_IDLEMODE_NO; 1374 idlemode = HWMOD_IDLEMODE_NO;
1373 } else { 1375 } else {
1374 if (sf & SYSC_HAS_ENAWAKEUP) 1376 if (sf & SYSC_HAS_ENAWAKEUP)
@@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
1440 } 1442 }
1441 1443
1442 if (sf & SYSC_HAS_MIDLEMODE) { 1444 if (sf & SYSC_HAS_MIDLEMODE) {
1443 if (oh->flags & HWMOD_SWSUP_MSTANDBY) { 1445 if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
1446 (oh->flags & HWMOD_FORCE_MSTANDBY)) {
1444 idlemode = HWMOD_IDLEMODE_FORCE; 1447 idlemode = HWMOD_IDLEMODE_FORCE;
1445 } else { 1448 } else {
1446 if (sf & SYSC_HAS_ENAWAKEUP) 1449 if (sf & SYSC_HAS_ENAWAKEUP)
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d43d9b608eda..d5dc935f6060 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
427 * 427 *
428 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out 428 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
429 * of idle, rather than relying on module smart-idle 429 * of idle, rather than relying on module smart-idle
430 * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out 430 * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
431 * of standby, rather than relying on module smart-standby 431 * out of standby, rather than relying on module smart-standby
432 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for 432 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
433 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file 433 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
434 * XXX Should be HWMOD_SETUP_NO_RESET 434 * XXX Should be HWMOD_SETUP_NO_RESET
@@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
459 * correctly, or this is being abused to deal with some PM latency 459 * correctly, or this is being abused to deal with some PM latency
460 * issues -- but we're currently suffering from a shortage of 460 * issues -- but we're currently suffering from a shortage of
461 * folks who are able to track these issues down properly. 461 * folks who are able to track these issues down properly.
462 * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
463 * is kept in force-standby mode. Failing to do so causes PM problems
464 * with musb on OMAP3630 at least. Note that musb has a dedicated register
465 * to control MSTANDBY signal when MIDLEMODE is set to force-standby.
462 */ 466 */
463#define HWMOD_SWSUP_SIDLE (1 << 0) 467#define HWMOD_SWSUP_SIDLE (1 << 0)
464#define HWMOD_SWSUP_MSTANDBY (1 << 1) 468#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
471#define HWMOD_16BIT_REG (1 << 8) 475#define HWMOD_16BIT_REG (1 << 8)
472#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) 476#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
473#define HWMOD_BLOCK_WFI (1 << 10) 477#define HWMOD_BLOCK_WFI (1 << 10)
478#define HWMOD_FORCE_MSTANDBY (1 << 11)
474 479
475/* 480/*
476 * omap_hwmod._int_flags definitions 481 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ac7e03ec952f..5112d04e7b79 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1707 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1707 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1708 * broken when autoidle is enabled 1708 * broken when autoidle is enabled
1709 * workaround is to disable the autoidle bit at module level. 1709 * workaround is to disable the autoidle bit at module level.
1710 *
1711 * Enabling the device in any other MIDLEMODE setting but force-idle
1712 * causes core_pwrdm not enter idle states at least on OMAP3630.
1713 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1714 * signal when MIDLEMODE is set to force-idle.
1710 */ 1715 */
1711 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 1716 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1712 | HWMOD_SWSUP_MSTANDBY, 1717 | HWMOD_FORCE_MSTANDBY,
1713}; 1718};
1714 1719
1715/* usb_otg_hs */ 1720/* usb_otg_hs */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0e47d2e1687c..9e0576569e07 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2714 { } 2714 { }
2715}; 2715};
2716 2716
2717static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2718 { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
2719};
2720
2717/* ocp2scp_usb_phy */ 2721/* ocp2scp_usb_phy */
2718static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { 2722static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2719 .name = "ocp2scp_usb_phy", 2723 .name = "ocp2scp_usb_phy",
@@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2728 }, 2732 },
2729 }, 2733 },
2730 .dev_attr = ocp2scp_dev_attr, 2734 .dev_attr = ocp2scp_dev_attr,
2735 .opt_clks = ocp2scp_usb_phy_opt_clks,
2736 .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2731}; 2737};
2732 2738
2733/* 2739/*
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2bdd4cf17a8f..f62b509ed08d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -547,6 +547,8 @@ static inline void __init realtime_counter_init(void)
547 clksrc_nr, clksrc_src) \ 547 clksrc_nr, clksrc_src) \
548void __init omap##name##_gptimer_timer_init(void) \ 548void __init omap##name##_gptimer_timer_init(void) \
549{ \ 549{ \
550 if (omap_clk_init) \
551 omap_clk_init(); \
550 omap_dmtimer_init(); \ 552 omap_dmtimer_init(); \
551 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 553 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
552 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ 554 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \
@@ -556,6 +558,8 @@ void __init omap##name##_gptimer_timer_init(void) \
556 clksrc_nr, clksrc_src) \ 558 clksrc_nr, clksrc_src) \
557void __init omap##name##_sync32k_timer_init(void) \ 559void __init omap##name##_sync32k_timer_init(void) \
558{ \ 560{ \
561 if (omap_clk_init) \
562 omap_clk_init(); \
559 omap_dmtimer_init(); \ 563 omap_dmtimer_init(); \
560 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 564 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
561 /* Enable the use of clocksource="gp_timer" kernel parameter */ \ 565 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 051b62c27102..7f2cb6c5e2c1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -81,7 +81,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
81#endif 81#endif
82 82
83struct mmci_platform_data mop500_sdi0_data = { 83struct mmci_platform_data mop500_sdi0_data = {
84 .ios_handler = mop500_sdi0_ios_handler,
85 .ocr_mask = MMC_VDD_29_30, 84 .ocr_mask = MMC_VDD_29_30,
86 .f_max = 50000000, 85 .f_max = 50000000,
87 .capabilities = MMC_CAP_4_BIT_DATA | 86 .capabilities = MMC_CAP_4_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index b03457881c4b..87d2d7b38ce9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/clk.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/i2c.h> 17#include <linux/i2c.h>
17#include <linux/platform_data/i2c-nomadik.h> 18#include <linux/platform_data/i2c-nomadik.h>
@@ -439,6 +440,15 @@ static void mop500_prox_deactivate(struct device *dev)
439 regulator_put(prox_regulator); 440 regulator_put(prox_regulator);
440} 441}
441 442
443void mop500_snowball_ethernet_clock_enable(void)
444{
445 struct clk *clk;
446
447 clk = clk_get_sys("fsmc", NULL);
448 if (!IS_ERR(clk))
449 clk_prepare_enable(clk);
450}
451
442static struct cryp_platform_data u8500_cryp1_platform_data = { 452static struct cryp_platform_data u8500_cryp1_platform_data = {
443 .mem_to_engine = { 453 .mem_to_engine = {
444 .dir = STEDMA40_MEM_TO_PERIPH, 454 .dir = STEDMA40_MEM_TO_PERIPH,
@@ -683,6 +693,8 @@ static void __init snowball_init_machine(void)
683 mop500_audio_init(parent); 693 mop500_audio_init(parent);
684 mop500_uart_init(parent); 694 mop500_uart_init(parent);
685 695
696 mop500_snowball_ethernet_clock_enable();
697
686 /* This board has full regulator constraints */ 698 /* This board has full regulator constraints */
687 regulator_has_full_constraints(); 699 regulator_has_full_constraints();
688} 700}
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index eaa605f5d90d..d38951be70df 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -104,6 +104,7 @@ void __init mop500_pinmaps_init(void);
104void __init snowball_pinmaps_init(void); 104void __init snowball_pinmaps_init(void);
105void __init hrefv60_pinmaps_init(void); 105void __init hrefv60_pinmaps_init(void);
106void mop500_audio_init(struct device *parent); 106void mop500_audio_init(struct device *parent);
107void mop500_snowball_ethernet_clock_enable(void);
107 108
108int __init mop500_uib_init(void); 109int __init mop500_uib_init(void);
109void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 110void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 19235cf7bbe3..f1a581844372 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -312,9 +312,10 @@ static void __init u8500_init_machine(void)
312 /* Pinmaps must be in place before devices register */ 312 /* Pinmaps must be in place before devices register */
313 if (of_machine_is_compatible("st-ericsson,mop500")) 313 if (of_machine_is_compatible("st-ericsson,mop500"))
314 mop500_pinmaps_init(); 314 mop500_pinmaps_init();
315 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) 315 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
316 snowball_pinmaps_init(); 316 snowball_pinmaps_init();
317 else if (of_machine_is_compatible("st-ericsson,hrefv60+")) 317 mop500_snowball_ethernet_clock_enable();
318 } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
318 hrefv60_pinmaps_init(); 319 hrefv60_pinmaps_init();
319 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} 320 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
320 /* TODO: Add pinmaps for ccu9540 board. */ 321 /* TODO: Add pinmaps for ccu9540 board. */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c2f37390308a..c465faca51b0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id)
299 int lockregs; 299 int lockregs;
300 int i; 300 int i;
301 301
302 switch (cache_id) { 302 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
303 case L2X0_CACHE_ID_PART_L310: 303 case L2X0_CACHE_ID_PART_L310:
304 lockregs = 8; 304 lockregs = 8;
305 break; 305 break;
@@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
333 if (cache_id_part_number_from_dt) 333 if (cache_id_part_number_from_dt)
334 cache_id = cache_id_part_number_from_dt; 334 cache_id = cache_id_part_number_from_dt;
335 else 335 else
336 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID) 336 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
337 & L2X0_CACHE_ID_PART_MASK;
338 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 337 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
339 338
340 aux &= aux_mask; 339 aux &= aux_mask;
341 aux |= aux_val; 340 aux |= aux_val;
342 341
343 /* Determine the number of ways */ 342 /* Determine the number of ways */
344 switch (cache_id) { 343 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
345 case L2X0_CACHE_ID_PART_L310: 344 case L2X0_CACHE_ID_PART_L310:
346 if (aux & (1 << 16)) 345 if (aux & (1 << 16))
347 ways = 16; 346 ways = 16;
@@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = {
725 .flush_all = l2x0_flush_all, 724 .flush_all = l2x0_flush_all,
726 .inv_all = l2x0_inv_all, 725 .inv_all = l2x0_inv_all,
727 .disable = l2x0_disable, 726 .disable = l2x0_disable,
728 .set_debug = pl310_set_debug,
729 }, 727 },
730}; 728};
731 729
@@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
814 data->save(); 812 data->save();
815 813
816 of_init = true; 814 of_init = true;
817 l2x0_init(l2x0_base, aux_val, aux_mask);
818
819 memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache)); 815 memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
816 l2x0_init(l2x0_base, aux_val, aux_mask);
820 817
821 return 0; 818 return 0;
822} 819}
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a5a4b2bc42ba..2ac37372ef52 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
48static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION); 48static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
49static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS); 49static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
50 50
51static DEFINE_PER_CPU(atomic64_t, active_asids); 51DEFINE_PER_CPU(atomic64_t, active_asids);
52static DEFINE_PER_CPU(u64, reserved_asids); 52static DEFINE_PER_CPU(u64, reserved_asids);
53static cpumask_t tlb_flush_pending; 53static cpumask_t tlb_flush_pending;
54 54
@@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
215 if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { 215 if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
216 local_flush_bp_all(); 216 local_flush_bp_all();
217 local_flush_tlb_all(); 217 local_flush_tlb_all();
218 dummy_flush_tlb_a15_erratum();
218 } 219 }
219 220
220 atomic64_set(&per_cpu(active_asids, cpu), asid); 221 atomic64_set(&per_cpu(active_asids, cpu), asid);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e95a996ab78f..78978945492a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
598 } while (pte++, addr += PAGE_SIZE, addr != end); 598 } while (pte++, addr += PAGE_SIZE, addr != end);
599} 599}
600 600
601static void __init alloc_init_section(pud_t *pud, unsigned long addr, 601static void __init map_init_section(pmd_t *pmd, unsigned long addr,
602 unsigned long end, phys_addr_t phys, 602 unsigned long end, phys_addr_t phys,
603 const struct mem_type *type) 603 const struct mem_type *type)
604{ 604{
605 pmd_t *pmd = pmd_offset(pud, addr); 605#ifndef CONFIG_ARM_LPAE
606
607 /* 606 /*
608 * Try a section mapping - end, addr and phys must all be aligned 607 * In classic MMU format, puds and pmds are folded in to
609 * to a section boundary. Note that PMDs refer to the individual 608 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
610 * L1 entries, whereas PGDs refer to a group of L1 entries making 609 * group of L1 entries making up one logical pointer to
611 * up one logical pointer to an L2 table. 610 * an L2 table (2MB), where as PMDs refer to the individual
611 * L1 entries (1MB). Hence increment to get the correct
612 * offset for odd 1MB sections.
613 * (See arch/arm/include/asm/pgtable-2level.h)
612 */ 614 */
613 if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { 615 if (addr & SECTION_SIZE)
614 pmd_t *p = pmd; 616 pmd++;
615
616#ifndef CONFIG_ARM_LPAE
617 if (addr & SECTION_SIZE)
618 pmd++;
619#endif 617#endif
618 do {
619 *pmd = __pmd(phys | type->prot_sect);
620 phys += SECTION_SIZE;
621 } while (pmd++, addr += SECTION_SIZE, addr != end);
620 622
621 do { 623 flush_pmd_entry(pmd);
622 *pmd = __pmd(phys | type->prot_sect); 624}
623 phys += SECTION_SIZE;
624 } while (pmd++, addr += SECTION_SIZE, addr != end);
625 625
626 flush_pmd_entry(p); 626static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
627 } else { 627 unsigned long end, phys_addr_t phys,
628 const struct mem_type *type)
629{
630 pmd_t *pmd = pmd_offset(pud, addr);
631 unsigned long next;
632
633 do {
628 /* 634 /*
629 * No need to loop; pte's aren't interested in the 635 * With LPAE, we must loop over to map
630 * individual L1 entries. 636 * all the pmds for the given range.
631 */ 637 */
632 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); 638 next = pmd_addr_end(addr, end);
633 } 639
640 /*
641 * Try a section mapping - addr, next and phys must all be
642 * aligned to a section boundary.
643 */
644 if (type->prot_sect &&
645 ((addr | next | phys) & ~SECTION_MASK) == 0) {
646 map_init_section(pmd, addr, next, phys, type);
647 } else {
648 alloc_init_pte(pmd, addr, next,
649 __phys_to_pfn(phys), type);
650 }
651
652 phys += next - addr;
653
654 } while (pmd++, addr = next, addr != end);
634} 655}
635 656
636static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 657static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
@@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
641 662
642 do { 663 do {
643 next = pud_addr_end(addr, end); 664 next = pud_addr_end(addr, end);
644 alloc_init_section(pud, addr, next, phys, type); 665 alloc_init_pmd(pud, addr, next, phys, type);
645 phys += next - addr; 666 phys += next - addr;
646 } while (pud++, addr = next, addr != end); 667 } while (pud++, addr = next, addr != end);
647} 668}
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015f8d5c..f584d3f5b37c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
420__v7_ca7mp_proc_info: 420__v7_ca7mp_proc_info:
421 .long 0x410fc070 421 .long 0x410fc070
422 .long 0xff0ffff0 422 .long 0xff0ffff0
423 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV 423 __v7_proc __v7_ca7mp_setup
424 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info 424 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
425 425
426 /* 426 /*
@@ -430,10 +430,25 @@ __v7_ca7mp_proc_info:
430__v7_ca15mp_proc_info: 430__v7_ca15mp_proc_info:
431 .long 0x410fc0f0 431 .long 0x410fc0f0
432 .long 0xff0ffff0 432 .long 0xff0ffff0
433 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV 433 __v7_proc __v7_ca15mp_setup
434 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 434 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
435 435
436 /* 436 /*
437 * Qualcomm Inc. Krait processors.
438 */
439 .type __krait_proc_info, #object
440__krait_proc_info:
441 .long 0x510f0400 @ Required ID value
442 .long 0xff0ffc00 @ Mask for ID
443 /*
444 * Some Krait processors don't indicate support for SDIV and UDIV
445 * instructions in the ARM instruction set, even though they actually
446 * do support them.
447 */
448 __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
449 .size __krait_proc_info, . - __krait_proc_info
450
451 /*
437 * Match any ARMv7 processor core. 452 * Match any ARMv7 processor core.
438 */ 453 */
439 .type __v7_proc_info, #object 454 .type __v7_proc_info, #object
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b2df47604759..51244bf97271 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -18,7 +18,7 @@ config MIPS
18 select HAVE_KRETPROBES 18 select HAVE_KRETPROBES
19 select HAVE_DEBUG_KMEMLEAK 19 select HAVE_DEBUG_KMEMLEAK
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 21 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
22 select RTC_LIB if !MACH_LOONGSON 22 select RTC_LIB if !MACH_LOONGSON
23 select GENERIC_ATOMIC64 if !64BIT 23 select GENERIC_ATOMIC64 if !64BIT
24 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 24 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -1493,7 +1493,6 @@ config CPU_XLP
1493 select CPU_SUPPORTS_32BIT_KERNEL 1493 select CPU_SUPPORTS_32BIT_KERNEL
1494 select CPU_SUPPORTS_64BIT_KERNEL 1494 select CPU_SUPPORTS_64BIT_KERNEL
1495 select CPU_SUPPORTS_HIGHMEM 1495 select CPU_SUPPORTS_HIGHMEM
1496 select CPU_HAS_LLSC
1497 select WEAK_ORDERING 1496 select WEAK_ORDERING
1498 select WEAK_REORDERING_BEYOND_LLSC 1497 select WEAK_REORDERING_BEYOND_LLSC
1499 select CPU_HAS_PREFETCH 1498 select CPU_HAS_PREFETCH
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index ed1949c29508..9aa7d44898ed 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -745,10 +745,7 @@ void __init board_prom_init(void)
745 strcpy(cfe_version, "unknown"); 745 strcpy(cfe_version, "unknown");
746 printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); 746 printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
747 747
748 if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) { 748 bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
749 printk(KERN_ERR PFX "invalid nvram checksum\n");
750 return;
751 }
752 749
753 board_name = bcm63xx_nvram_get_name(); 750 board_name = bcm63xx_nvram_get_name();
754 /* find board by name */ 751 /* find board by name */
diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c
index 620611680839..a4b8864f9307 100644
--- a/arch/mips/bcm63xx/nvram.c
+++ b/arch/mips/bcm63xx/nvram.c
@@ -38,7 +38,7 @@ struct bcm963xx_nvram {
38static struct bcm963xx_nvram nvram; 38static struct bcm963xx_nvram nvram;
39static int mac_addr_used; 39static int mac_addr_used;
40 40
41int __init bcm63xx_nvram_init(void *addr) 41void __init bcm63xx_nvram_init(void *addr)
42{ 42{
43 unsigned int check_len; 43 unsigned int check_len;
44 u32 crc, expected_crc; 44 u32 crc, expected_crc;
@@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr)
60 crc = crc32_le(~0, (u8 *)&nvram, check_len); 60 crc = crc32_le(~0, (u8 *)&nvram, check_len);
61 61
62 if (crc != expected_crc) 62 if (crc != expected_crc)
63 return -EINVAL; 63 pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
64 64 expected_crc, crc);
65 return 0;
66} 65}
67 66
68u8 *bcm63xx_nvram_get_name(void) 67u8 *bcm63xx_nvram_get_name(void)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 314231be788c..35e18e98beb9 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void)
157 return board_register_devices(); 157 return board_register_devices();
158} 158}
159 159
160device_initcall(bcm63xx_register_devices); 160arch_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
index 62d6a3b4d3b7..4e0b6bc1165e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -9,10 +9,8 @@
9 * 9 *
10 * Initialized the local nvram copy from the target address and checks 10 * Initialized the local nvram copy from the target address and checks
11 * its checksum. 11 * its checksum.
12 *
13 * Returns 0 on success.
14 */ 12 */
15int __init bcm63xx_nvram_init(void *nvram); 13void bcm63xx_nvram_init(void *nvram);
16 14
17/** 15/**
18 * bcm63xx_nvram_get_name() - returns the board name according to nvram 16 * bcm63xx_nvram_get_name() - returns the board name according to nvram
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index d9c828419037..193c0912d38e 100644
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -28,11 +28,7 @@
28/* #define cpu_has_prefetch ? */ 28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1 29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */ 30/* #define cpu_has_ejtag ? */
31#ifdef CONFIG_CPU_HAS_LLSC
32#define cpu_has_llsc 1 31#define cpu_has_llsc 1
33#else
34#define cpu_has_llsc 0
35#endif
36/* #define cpu_has_vtag_icache ? */ 32/* #define cpu_has_vtag_icache ? */
37/* #define cpu_has_dc_aliases ? */ 33/* #define cpu_has_dc_aliases ? */
38/* #define cpu_has_ic_fills_f_dc ? */ 34/* #define cpu_has_ic_fills_f_dc ? */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 12b70c25906a..0da44d422f5b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1166,7 +1166,10 @@ do { \
1166 unsigned int __dspctl; \ 1166 unsigned int __dspctl; \
1167 \ 1167 \
1168 __asm__ __volatile__( \ 1168 __asm__ __volatile__( \
1169 " .set push \n" \
1170 " .set dsp \n" \
1169 " rddsp %0, %x1 \n" \ 1171 " rddsp %0, %x1 \n" \
1172 " .set pop \n" \
1170 : "=r" (__dspctl) \ 1173 : "=r" (__dspctl) \
1171 : "i" (mask)); \ 1174 : "i" (mask)); \
1172 __dspctl; \ 1175 __dspctl; \
@@ -1175,30 +1178,198 @@ do { \
1175#define wrdsp(val, mask) \ 1178#define wrdsp(val, mask) \
1176do { \ 1179do { \
1177 __asm__ __volatile__( \ 1180 __asm__ __volatile__( \
1181 " .set push \n" \
1182 " .set dsp \n" \
1178 " wrdsp %0, %x1 \n" \ 1183 " wrdsp %0, %x1 \n" \
1184 " .set pop \n" \
1179 : \ 1185 : \
1180 : "r" (val), "i" (mask)); \ 1186 : "r" (val), "i" (mask)); \
1181} while (0) 1187} while (0)
1182 1188
1183#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1189#define mflo0() \
1184#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1190({ \
1185#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1191 long mflo0; \
1186#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) 1192 __asm__( \
1187 1193 " .set push \n" \
1188#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) 1194 " .set dsp \n" \
1189#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) 1195 " mflo %0, $ac0 \n" \
1190#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) 1196 " .set pop \n" \
1191#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) 1197 : "=r" (mflo0)); \
1192 1198 mflo0; \
1193#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) 1199})
1194#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) 1200
1195#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) 1201#define mflo1() \
1196#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) 1202({ \
1197 1203 long mflo1; \
1198#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) 1204 __asm__( \
1199#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) 1205 " .set push \n" \
1200#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) 1206 " .set dsp \n" \
1201#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) 1207 " mflo %0, $ac1 \n" \
1208 " .set pop \n" \
1209 : "=r" (mflo1)); \
1210 mflo1; \
1211})
1212
1213#define mflo2() \
1214({ \
1215 long mflo2; \
1216 __asm__( \
1217 " .set push \n" \
1218 " .set dsp \n" \
1219 " mflo %0, $ac2 \n" \
1220 " .set pop \n" \
1221 : "=r" (mflo2)); \
1222 mflo2; \
1223})
1224
1225#define mflo3() \
1226({ \
1227 long mflo3; \
1228 __asm__( \
1229 " .set push \n" \
1230 " .set dsp \n" \
1231 " mflo %0, $ac3 \n" \
1232 " .set pop \n" \
1233 : "=r" (mflo3)); \
1234 mflo3; \
1235})
1236
1237#define mfhi0() \
1238({ \
1239 long mfhi0; \
1240 __asm__( \
1241 " .set push \n" \
1242 " .set dsp \n" \
1243 " mfhi %0, $ac0 \n" \
1244 " .set pop \n" \
1245 : "=r" (mfhi0)); \
1246 mfhi0; \
1247})
1248
1249#define mfhi1() \
1250({ \
1251 long mfhi1; \
1252 __asm__( \
1253 " .set push \n" \
1254 " .set dsp \n" \
1255 " mfhi %0, $ac1 \n" \
1256 " .set pop \n" \
1257 : "=r" (mfhi1)); \
1258 mfhi1; \
1259})
1260
1261#define mfhi2() \
1262({ \
1263 long mfhi2; \
1264 __asm__( \
1265 " .set push \n" \
1266 " .set dsp \n" \
1267 " mfhi %0, $ac2 \n" \
1268 " .set pop \n" \
1269 : "=r" (mfhi2)); \
1270 mfhi2; \
1271})
1272
1273#define mfhi3() \
1274({ \
1275 long mfhi3; \
1276 __asm__( \
1277 " .set push \n" \
1278 " .set dsp \n" \
1279 " mfhi %0, $ac3 \n" \
1280 " .set pop \n" \
1281 : "=r" (mfhi3)); \
1282 mfhi3; \
1283})
1284
1285
1286#define mtlo0(x) \
1287({ \
1288 __asm__( \
1289 " .set push \n" \
1290 " .set dsp \n" \
1291 " mtlo %0, $ac0 \n" \
1292 " .set pop \n" \
1293 : \
1294 : "r" (x)); \
1295})
1296
1297#define mtlo1(x) \
1298({ \
1299 __asm__( \
1300 " .set push \n" \
1301 " .set dsp \n" \
1302 " mtlo %0, $ac1 \n" \
1303 " .set pop \n" \
1304 : \
1305 : "r" (x)); \
1306})
1307
1308#define mtlo2(x) \
1309({ \
1310 __asm__( \
1311 " .set push \n" \
1312 " .set dsp \n" \
1313 " mtlo %0, $ac2 \n" \
1314 " .set pop \n" \
1315 : \
1316 : "r" (x)); \
1317})
1318
1319#define mtlo3(x) \
1320({ \
1321 __asm__( \
1322 " .set push \n" \
1323 " .set dsp \n" \
1324 " mtlo %0, $ac3 \n" \
1325 " .set pop \n" \
1326 : \
1327 : "r" (x)); \
1328})
1329
1330#define mthi0(x) \
1331({ \
1332 __asm__( \
1333 " .set push \n" \
1334 " .set dsp \n" \
1335 " mthi %0, $ac0 \n" \
1336 " .set pop \n" \
1337 : \
1338 : "r" (x)); \
1339})
1340
1341#define mthi1(x) \
1342({ \
1343 __asm__( \
1344 " .set push \n" \
1345 " .set dsp \n" \
1346 " mthi %0, $ac1 \n" \
1347 " .set pop \n" \
1348 : \
1349 : "r" (x)); \
1350})
1351
1352#define mthi2(x) \
1353({ \
1354 __asm__( \
1355 " .set push \n" \
1356 " .set dsp \n" \
1357 " mthi %0, $ac2 \n" \
1358 " .set pop \n" \
1359 : \
1360 : "r" (x)); \
1361})
1362
1363#define mthi3(x) \
1364({ \
1365 __asm__( \
1366 " .set push \n" \
1367 " .set dsp \n" \
1368 " mthi %0, $ac3 \n" \
1369 " .set pop \n" \
1370 : \
1371 : "r" (x)); \
1372})
1202 1373
1203#else 1374#else
1204 1375
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index 197f6367c201..8efe5a9e2c3e 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -21,6 +21,6 @@
21#include <asm/sigcontext.h> 21#include <asm/sigcontext.h>
22#include <asm/siginfo.h> 22#include <asm/siginfo.h>
23 23
24#define __ARCH_HAS_ODD_SIGACTION 24#define __ARCH_HAS_IRIX_SIGACTION
25 25
26#endif /* _ASM_SIGNAL_H */ 26#endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index f81d98f6184c..de75fb50562b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
100obj-$(CONFIG_JUMP_LABEL) += jump_label.o 100obj-$(CONFIG_JUMP_LABEL) += jump_label.o
101 101
102# 102#
103# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe 103# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
104# to enable DSP assembler support here even if the MIPS Release 2 CPU we 104# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
105# are targetting does not support DSP because all code-paths making use of 105# here because the compiler may use DSP ASE instructions (such as lwx) in
106# it properly check that the running CPU *actually does* support these 106# code paths where we cannot check that the CPU we are running on supports it.
107# instructions. 107# Proper abstraction using HAVE_AS_DSP and macros is done in
108# arch/mips/include/asm/mipsregs.h.
108# 109#
109ifeq ($(CONFIG_CPU_MIPSR2), y) 110ifeq ($(CONFIG_CPU_MIPSR2), y)
110CFLAGS_DSP = -DHAVE_AS_DSP 111CFLAGS_DSP = -DHAVE_AS_DSP
111 112
112#
113# Check if assembler supports DSP ASE
114#
115ifeq ($(call cc-option-yn,-mdsp), y)
116CFLAGS_DSP += -mdsp
117endif
118
119#
120# Check if assembler supports DSP ASE Rev2
121#
122ifeq ($(call cc-option-yn,-mdspr2), y)
123CFLAGS_DSP += -mdspr2
124endif
125
126CFLAGS_signal.o = $(CFLAGS_DSP) 113CFLAGS_signal.o = $(CFLAGS_DSP)
127CFLAGS_signal32.o = $(CFLAGS_DSP) 114CFLAGS_signal32.o = $(CFLAGS_DSP)
128CFLAGS_process.o = $(CFLAGS_DSP) 115CFLAGS_process.o = $(CFLAGS_DSP)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ed80c3844345..5fe66a0c3224 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
580 c->tlbsize = 48; 580 c->tlbsize = 48;
581 break; 581 break;
582 case PRID_IMP_VR41XX: 582 case PRID_IMP_VR41XX:
583 set_isa(c, MIPS_CPU_ISA_III);
584 c->options = R4K_OPTS;
585 c->tlbsize = 32;
583 switch (c->processor_id & 0xf0) { 586 switch (c->processor_id & 0xf0) {
584 case PRID_REV_VR4111: 587 case PRID_REV_VR4111:
585 c->cputype = CPU_VR4111; 588 c->cputype = CPU_VR4111;
@@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
604 __cpu_name[cpu] = "NEC VR4131"; 607 __cpu_name[cpu] = "NEC VR4131";
605 } else { 608 } else {
606 c->cputype = CPU_VR4133; 609 c->cputype = CPU_VR4133;
610 c->options |= MIPS_CPU_LLSC;
607 __cpu_name[cpu] = "NEC VR4133"; 611 __cpu_name[cpu] = "NEC VR4133";
608 } 612 }
609 break; 613 break;
@@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
613 __cpu_name[cpu] = "NEC Vr41xx"; 617 __cpu_name[cpu] = "NEC Vr41xx";
614 break; 618 break;
615 } 619 }
616 set_isa(c, MIPS_CPU_ISA_III);
617 c->options = R4K_OPTS;
618 c->tlbsize = 32;
619 break; 620 break;
620 case PRID_IMP_R4300: 621 case PRID_IMP_R4300:
621 c->cputype = CPU_R4300; 622 c->cputype = CPU_R4300;
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 8eeee1c860c0..db9655f08892 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
171 err = compat_sys_shmctl(first, second, compat_ptr(ptr)); 171 err = compat_sys_shmctl(first, second, compat_ptr(ptr));
172 break; 172 break;
173 default: 173 default:
174 err = -EINVAL; 174 err = -ENOSYS;
175 break; 175 break;
176 } 176 }
177 177
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 135c4aadccbe..7a54f74b7818 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
67 if (cpu_has_mips_r) { 67 if (cpu_has_mips_r) {
68 seq_printf(m, "isa\t\t\t:"); 68 seq_printf(m, "isa\t\t\t:");
69 if (cpu_has_mips_1) 69 if (cpu_has_mips_1)
70 seq_printf(m, "%s", "mips1"); 70 seq_printf(m, "%s", " mips1");
71 if (cpu_has_mips_2) 71 if (cpu_has_mips_2)
72 seq_printf(m, "%s", " mips2"); 72 seq_printf(m, "%s", " mips2");
73 if (cpu_has_mips_3) 73 if (cpu_has_mips_3)
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
index 81f1dcfdcab8..a64daee740ee 100644
--- a/arch/mips/lib/bitops.c
+++ b/arch/mips/lib/bitops.c
@@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr,
90 unsigned bit = nr & SZLONG_MASK; 90 unsigned bit = nr & SZLONG_MASK;
91 unsigned long mask; 91 unsigned long mask;
92 unsigned long flags; 92 unsigned long flags;
93 unsigned long res; 93 int res;
94 94
95 a += nr >> SZLONG_LOG; 95 a += nr >> SZLONG_LOG;
96 mask = 1UL << bit; 96 mask = 1UL << bit;
97 raw_local_irq_save(flags); 97 raw_local_irq_save(flags);
98 res = (mask & *a); 98 res = (mask & *a) != 0;
99 *a |= mask; 99 *a |= mask;
100 raw_local_irq_restore(flags); 100 raw_local_irq_restore(flags);
101 return res; 101 return res;
@@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr,
116 unsigned bit = nr & SZLONG_MASK; 116 unsigned bit = nr & SZLONG_MASK;
117 unsigned long mask; 117 unsigned long mask;
118 unsigned long flags; 118 unsigned long flags;
119 unsigned long res; 119 int res;
120 120
121 a += nr >> SZLONG_LOG; 121 a += nr >> SZLONG_LOG;
122 mask = 1UL << bit; 122 mask = 1UL << bit;
123 raw_local_irq_save(flags); 123 raw_local_irq_save(flags);
124 res = (mask & *a); 124 res = (mask & *a) != 0;
125 *a |= mask; 125 *a |= mask;
126 raw_local_irq_restore(flags); 126 raw_local_irq_restore(flags);
127 return res; 127 return res;
@@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
141 unsigned bit = nr & SZLONG_MASK; 141 unsigned bit = nr & SZLONG_MASK;
142 unsigned long mask; 142 unsigned long mask;
143 unsigned long flags; 143 unsigned long flags;
144 unsigned long res; 144 int res;
145 145
146 a += nr >> SZLONG_LOG; 146 a += nr >> SZLONG_LOG;
147 mask = 1UL << bit; 147 mask = 1UL << bit;
148 raw_local_irq_save(flags); 148 raw_local_irq_save(flags);
149 res = (mask & *a); 149 res = (mask & *a) != 0;
150 *a &= ~mask; 150 *a &= ~mask;
151 raw_local_irq_restore(flags); 151 raw_local_irq_restore(flags);
152 return res; 152 return res;
@@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
166 unsigned bit = nr & SZLONG_MASK; 166 unsigned bit = nr & SZLONG_MASK;
167 unsigned long mask; 167 unsigned long mask;
168 unsigned long flags; 168 unsigned long flags;
169 unsigned long res; 169 int res;
170 170
171 a += nr >> SZLONG_LOG; 171 a += nr >> SZLONG_LOG;
172 mask = 1UL << bit; 172 mask = 1UL << bit;
173 raw_local_irq_save(flags); 173 raw_local_irq_save(flags);
174 res = (mask & *a); 174 res = (mask & *a) != 0;
175 *a ^= mask; 175 *a ^= mask;
176 raw_local_irq_restore(flags); 176 raw_local_irq_restore(flags);
177 return res; 177 return res;
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 507147aebd41..a6adffbb4e5f 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -270,7 +270,7 @@ LEAF(csum_partial)
270#endif 270#endif
271 271
272 /* odd buffer alignment? */ 272 /* odd buffer alignment? */
273#ifdef CPU_MIPSR2 273#ifdef CONFIG_CPU_MIPSR2
274 wsbh v1, sum 274 wsbh v1, sum
275 movn sum, v1, t7 275 movn sum, v1, t7
276#else 276#else
@@ -670,7 +670,7 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
670 addu sum, v1 670 addu sum, v1
671#endif 671#endif
672 672
673#ifdef CPU_MIPSR2 673#ifdef CONFIG_CPU_MIPSR2
674 wsbh v1, sum 674 wsbh v1, sum
675 movn sum, v1, odd 675 movn sum, v1, odd
676#else 676#else
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 4a2930844d43..4a5443118cfb 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -344,6 +344,7 @@ extern unsigned long MODULES_END;
344#define _REGION3_ENTRY_CO 0x100 /* change-recording override */ 344#define _REGION3_ENTRY_CO 0x100 /* change-recording override */
345 345
346/* Bits in the segment table entry */ 346/* Bits in the segment table entry */
347#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
347#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 348#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
348#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 349#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
349#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 350#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
@@ -1531,7 +1532,8 @@ extern int s390_enable_sie(void);
1531/* 1532/*
1532 * No page table caches to initialise 1533 * No page table caches to initialise
1533 */ 1534 */
1534#define pgtable_cache_init() do { } while (0) 1535static inline void pgtable_cache_init(void) { }
1536static inline void check_pgt_cache(void) { }
1535 1537
1536#include <asm-generic/pgtable.h> 1538#include <asm-generic/pgtable.h>
1537 1539
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index dff631d34b45..466fb3383960 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -77,42 +77,69 @@ static size_t copy_in_kernel(size_t count, void __user *to,
77 * >= -4095 (IS_ERR_VALUE(x) returns true), a fault has occured and the address 77 * >= -4095 (IS_ERR_VALUE(x) returns true), a fault has occured and the address
78 * contains the (negative) exception code. 78 * contains the (negative) exception code.
79 */ 79 */
80static __always_inline unsigned long follow_table(struct mm_struct *mm, 80#ifdef CONFIG_64BIT
81 unsigned long addr, int write) 81static unsigned long follow_table(struct mm_struct *mm,
82 unsigned long address, int write)
82{ 83{
83 pgd_t *pgd; 84 unsigned long *table = (unsigned long *)__pa(mm->pgd);
84 pud_t *pud; 85
85 pmd_t *pmd; 86 switch (mm->context.asce_bits & _ASCE_TYPE_MASK) {
86 pte_t *ptep; 87 case _ASCE_TYPE_REGION1:
88 table = table + ((address >> 53) & 0x7ff);
89 if (unlikely(*table & _REGION_ENTRY_INV))
90 return -0x39UL;
91 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
92 case _ASCE_TYPE_REGION2:
93 table = table + ((address >> 42) & 0x7ff);
94 if (unlikely(*table & _REGION_ENTRY_INV))
95 return -0x3aUL;
96 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
97 case _ASCE_TYPE_REGION3:
98 table = table + ((address >> 31) & 0x7ff);
99 if (unlikely(*table & _REGION_ENTRY_INV))
100 return -0x3bUL;
101 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
102 case _ASCE_TYPE_SEGMENT:
103 table = table + ((address >> 20) & 0x7ff);
104 if (unlikely(*table & _SEGMENT_ENTRY_INV))
105 return -0x10UL;
106 if (unlikely(*table & _SEGMENT_ENTRY_LARGE)) {
107 if (write && (*table & _SEGMENT_ENTRY_RO))
108 return -0x04UL;
109 return (*table & _SEGMENT_ENTRY_ORIGIN_LARGE) +
110 (address & ~_SEGMENT_ENTRY_ORIGIN_LARGE);
111 }
112 table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
113 }
114 table = table + ((address >> 12) & 0xff);
115 if (unlikely(*table & _PAGE_INVALID))
116 return -0x11UL;
117 if (write && (*table & _PAGE_RO))
118 return -0x04UL;
119 return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
120}
87 121
88 pgd = pgd_offset(mm, addr); 122#else /* CONFIG_64BIT */
89 if (pgd_none(*pgd) || unlikely(pgd_bad(*pgd)))
90 return -0x3aUL;
91 123
92 pud = pud_offset(pgd, addr); 124static unsigned long follow_table(struct mm_struct *mm,
93 if (pud_none(*pud) || unlikely(pud_bad(*pud))) 125 unsigned long address, int write)
94 return -0x3bUL; 126{
127 unsigned long *table = (unsigned long *)__pa(mm->pgd);
95 128
96 pmd = pmd_offset(pud, addr); 129 table = table + ((address >> 20) & 0x7ff);
97 if (pmd_none(*pmd)) 130 if (unlikely(*table & _SEGMENT_ENTRY_INV))
98 return -0x10UL; 131 return -0x10UL;
99 if (pmd_large(*pmd)) { 132 table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
100 if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO)) 133 table = table + ((address >> 12) & 0xff);
101 return -0x04UL; 134 if (unlikely(*table & _PAGE_INVALID))
102 return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK);
103 }
104 if (unlikely(pmd_bad(*pmd)))
105 return -0x10UL;
106
107 ptep = pte_offset_map(pmd, addr);
108 if (!pte_present(*ptep))
109 return -0x11UL; 135 return -0x11UL;
110 if (write && (!pte_write(*ptep) || !pte_dirty(*ptep))) 136 if (write && (*table & _PAGE_RO))
111 return -0x04UL; 137 return -0x04UL;
112 138 return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
113 return (pte_val(*ptep) & PAGE_MASK) + (addr & ~PAGE_MASK);
114} 139}
115 140
141#endif /* CONFIG_64BIT */
142
116static __always_inline size_t __user_copy_pt(unsigned long uaddr, void *kptr, 143static __always_inline size_t __user_copy_pt(unsigned long uaddr, void *kptr,
117 size_t n, int write_user) 144 size_t n, int write_user)
118{ 145{
@@ -197,7 +224,7 @@ size_t copy_to_user_pt(size_t n, void __user *to, const void *from)
197 224
198static size_t clear_user_pt(size_t n, void __user *to) 225static size_t clear_user_pt(size_t n, void __user *to)
199{ 226{
200 void *zpage = &empty_zero_page; 227 void *zpage = (void *) empty_zero_page;
201 long done, size, ret; 228 long done, size, ret;
202 229
203 done = 0; 230 done = 0;
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index d1e15f7b59c6..7a5aa1a7864e 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -1004,15 +1004,8 @@ void __cpuinit setup_cpu(int boot)
1004 1004
1005#ifdef CONFIG_BLK_DEV_INITRD 1005#ifdef CONFIG_BLK_DEV_INITRD
1006 1006
1007/*
1008 * Note that the kernel can potentially support other compression
1009 * techniques than gz, though we don't do so by default. If we ever
1010 * decide to do so we can either look for other filename extensions,
1011 * or just allow a file with this name to be compressed with an
1012 * arbitrary compressor (somewhat counterintuitively).
1013 */
1014static int __initdata set_initramfs_file; 1007static int __initdata set_initramfs_file;
1015static char __initdata initramfs_file[128] = "initramfs.cpio.gz"; 1008static char __initdata initramfs_file[128] = "initramfs";
1016 1009
1017static int __init setup_initramfs_file(char *str) 1010static int __init setup_initramfs_file(char *str)
1018{ 1011{
@@ -1026,9 +1019,9 @@ static int __init setup_initramfs_file(char *str)
1026early_param("initramfs_file", setup_initramfs_file); 1019early_param("initramfs_file", setup_initramfs_file);
1027 1020
1028/* 1021/*
1029 * We look for an "initramfs.cpio.gz" file in the hvfs. 1022 * We look for a file called "initramfs" in the hvfs. If there is one, we
1030 * If there is one, we allocate some memory for it and it will be 1023 * allocate some memory for it and it will be unpacked to the initramfs.
1031 * unpacked to the initramfs. 1024 * If it's compressed, the initd code will uncompress it first.
1032 */ 1025 */
1033static void __init load_hv_initrd(void) 1026static void __init load_hv_initrd(void)
1034{ 1027{
@@ -1038,10 +1031,16 @@ static void __init load_hv_initrd(void)
1038 1031
1039 fd = hv_fs_findfile((HV_VirtAddr) initramfs_file); 1032 fd = hv_fs_findfile((HV_VirtAddr) initramfs_file);
1040 if (fd == HV_ENOENT) { 1033 if (fd == HV_ENOENT) {
1041 if (set_initramfs_file) 1034 if (set_initramfs_file) {
1042 pr_warning("No such hvfs initramfs file '%s'\n", 1035 pr_warning("No such hvfs initramfs file '%s'\n",
1043 initramfs_file); 1036 initramfs_file);
1044 return; 1037 return;
1038 } else {
1039 /* Try old backwards-compatible name. */
1040 fd = hv_fs_findfile((HV_VirtAddr)"initramfs.cpio.gz");
1041 if (fd == HV_ENOENT)
1042 return;
1043 }
1045 } 1044 }
1046 BUG_ON(fd < 0); 1045 BUG_ON(fd < 0);
1047 stat = hv_fs_fstat(fd); 1046 stat = hv_fs_fstat(fd);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 22:32:47 -0500