12 files changed, 158 insertions, 12 deletions

diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index 9f509f55d078..dc8e882a6257 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -21,14 +21,17 @@
 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
 
                 .macro  addruart,rp,rv,tmp
+                .arch   armv7-a
 
                 @ Make an educated guess regarding the memory map:
-                @ - the original A9 core tile, which has MPCore peripherals
-                @   located at 0x1e000000, should use UART at 0x10009000
+                @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
+                @   should use UART at 0x10009000
                 @ - all other (RS1 complaint) tiles use UART mapped
                 @   at 0x1c090000
-                mrc     p15, 4, \tmp, c15, c0, 0
-                cmp     \tmp, #0x1e000000
+                mrc     p15, 0, \rp, c0, c0, 0
+                movw    \rv, #0xc091
+                movt    \rv, #0x410f
+                cmp     \rp, \rv
 
                 @ Original memory map
                 moveq   \rp, #DEBUG_LL_UART_OFFSET
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 29b13f249aa9..9ebfcc46feb1 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -3,7 +3,6 @@ menu "CNS3XXX platform type"
 
 config MACH_CNS3420VB
         bool "Support for CNS3420 Validation Board"
-        select MIGHT_HAVE_PCI
         help
           Include support for the Cavium Networks CNS3420 MPCore Platform
           Baseboard.
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index f22572cee49d..f8a99ee6bffc 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -519,13 +519,11 @@ static int dm6444evm_msp430_get_pins(void)
         char buf[4];
         struct i2c_msg msg[2] = {
                 {
-                        .addr = dm6446evm_msp->addr,
                         .flags = 0,
                         .len = 2,
                         .buf = (void __force *)txbuf,
                 },
                 {
-                        .addr = dm6446evm_msp->addr,
                         .flags = I2C_M_RD,
                         .len = 4,
                         .buf = buf,
@@ -536,6 +534,9 @@ static int dm6444evm_msp430_get_pins(void)
         if (!dm6446evm_msp)
                 return -ENXIO;
 
+        msg[0].addr = dm6446evm_msp->addr;
+        msg[1].addr = dm6446evm_msp->addr;
+
         /* Command 4 == get input state, returns port 2 and port3 data
          *   S Addr W [A] len=2 [A] cmd=4 [A]
          *   RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 29b17f7d3a5f..773ab07a71a0 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -374,7 +374,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
          * complete sample conversion in time.
          */
         tsc_clk = clk_get(NULL, "sys_tsc_clk");
-        if (tsc_clk) {
+        if (!IS_ERR(tsc_clk)) {
                 error = clk_set_rate(tsc_clk, 5000000);
                 WARN_ON(error < 0);
                 clk_put(tsc_clk);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 46b3cd11c3c2..86a01fa6d3fe 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -38,7 +38,7 @@
 
 #ifndef __ASSEMBLY__
 struct davinci_uart_config {
-        /* Bit field of UARTs present; bit 0 --> UART1 */
+        /* Bit field of UARTs present; bit 0 --> UART0 */
         unsigned int enabled_uarts;
 };
 
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 18cfd4977155..3a0ff905a69b 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -32,6 +32,9 @@ u32 *uart;
 /* PORT_16C550A, in polled non-fifo mode */
 static void putc(char c)
 {
+        if (!uart)
+                return;
+
         while (!(uart[UART_LSR] & UART_LSR_THRE))
                 barrier();
         uart[UART_TX] = c;
@@ -39,6 +42,9 @@ static void putc(char c)
 
 static inline void flush(void)
 {
+        if (!uart)
+                return;
+
         while (!(uart[UART_LSR] & UART_LSR_THRE))
                 barrier();
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7045e4d61ac3..d29dbaa29621 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -275,6 +275,9 @@ static inline void __iomem *omap4_get_scu_base(void)
 #endif
 
 extern void __init gic_init_irq(void);
+extern void gic_dist_disable(void);
+extern bool gic_dist_disabled(void);
+extern void gic_timer_retrigger(void);
 extern void omap_smc1(u32 fn, u32 arg);
 extern void __iomem *omap4_get_sar_ram_base(void);
 extern void omap_do_wfi(void);
@@ -282,6 +285,7 @@ extern void omap_do_wfi(void);
 #ifdef CONFIG_SMP
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
+extern void omap_secondary_startup_4460(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 502e3135aad3..0ea09faf327b 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,6 +18,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include "omap44xx.h"
+
         __CPUINIT
 
 /* Physical address needed since MMU not enabled yet on secondary core */
@@ -64,3 +66,39 @@ hold:	ldr	r12,=0x103
         b       secondary_startup
 ENDPROC(omap_secondary_startup)
 
+ENTRY(omap_secondary_startup_4460)
+hold_2: ldr     r12,=0x103
+        dsb
+        smc     #0                      @ read from AuxCoreBoot0
+        mov     r0, r0, lsr #9
+        mrc     p15, 0, r4, c0, c0, 5
+        and     r4, r4, #0x0f
+        cmp     r0, r4
+        bne     hold_2
+
+        /*
+         * GIC distributor control register has changed between
+         * CortexA9 r1pX and r2pX. The Control Register secure
+         * banked version is now composed of 2 bits:
+         * bit 0 == Secure Enable
+         * bit 1 == Non-Secure Enable
+         * The Non-Secure banked register has not changed
+         * Because the ROM Code is based on the r1pX GIC, the CPU1
+         * GIC restoration will cause a problem to CPU0 Non-Secure SW.
+         * The workaround must be:
+         * 1) Before doing the CPU1 wakeup, CPU0 must disable
+         * the GIC distributor
+         * 2) CPU1 must re-enable the GIC distributor on
+         * it's wakeup path.
+         */
+        ldr     r1, =OMAP44XX_GIC_DIST_BASE
+        ldr     r0, [r1]
+        orr     r0, #1
+        str     r0, [r1]
+
+        /*
+         * we've been released from the wait loop,secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+ENDPROC(omap_secondary_startup_4460)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index ff4e6a0e9c7c..c8bc3ad85f68 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -67,6 +67,7 @@ struct omap4_cpu_pm_info {
         void __iomem *scu_sar_addr;
         void __iomem *wkup_sar_addr;
         void __iomem *l2x0_sar_addr;
+        void (*secondary_startup)(void);
 };
 
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
@@ -299,6 +300,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 {
         unsigned int cpu_state = 0;
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 
         if (omap_rev() == OMAP4430_REV_ES1_0)
                 return -ENXIO;
@@ -308,7 +310,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 
         clear_cpu_prev_pwrst(cpu);
         set_cpu_next_pwrst(cpu, power_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
+        set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
         scu_pwrst_prepare(cpu, power_state);
 
         /*
@@ -359,6 +361,11 @@ int __init omap4_mpuss_init(void)
         pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
         pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+        if (cpu_is_omap446x())
+                pm_info->secondary_startup = omap_secondary_startup_4460;
+        else
+                pm_info->secondary_startup = omap_secondary_startup;
+
         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
         if (!pm_info->pwrdm) {
                 pr_err("Lookup failed for CPU1 pwrdm\n");
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 4d05fa8a4e48..cd42d921940d 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -32,6 +32,7 @@
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
+#include "pm.h"
 
 #define CPU_MASK                0xff0ffff0
 #define CPU_CORTEX_A9           0x410FC090
@@ -39,6 +40,8 @@
 
 #define OMAP5_CORE_COUNT        0x2
 
+u16 pm44xx_errata;
+
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -118,8 +121,37 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
          *      4.3.4.2 Power States of CPU0 and CPU1
          */
         if (booted) {
+                /*
+                 * GIC distributor control register has changed between
+                 * CortexA9 r1pX and r2pX. The Control Register secure
+                 * banked version is now composed of 2 bits:
+                 * bit 0 == Secure Enable
+                 * bit 1 == Non-Secure Enable
+                 * The Non-Secure banked register has not changed
+                 * Because the ROM Code is based on the r1pX GIC, the CPU1
+                 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
+                 * The workaround must be:
+                 * 1) Before doing the CPU1 wakeup, CPU0 must disable
+                 * the GIC distributor
+                 * 2) CPU1 must re-enable the GIC distributor on
+                 * it's wakeup path.
+                 */
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
+                        local_irq_disable();
+                        gic_dist_disable();
+                }
+
                 clkdm_wakeup(cpu1_clkdm);
                 clkdm_allow_idle(cpu1_clkdm);
+
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
+                        while (gic_dist_disabled()) {
+                                udelay(1);
+                                cpu_relax();
+                        }
+                        gic_timer_retrigger();
+                        local_irq_enable();
+                }
         } else {
                 dsb_sev();
                 booted = true;
@@ -138,7 +170,14 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
 
 static void __init wakeup_secondary(void)
 {
+        void *startup_addr = omap_secondary_startup;
         void __iomem *base = omap_get_wakeupgen_base();
+
+        if (cpu_is_omap446x()) {
+                startup_addr = omap_secondary_startup_4460;
+                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
+        }
+
         /*
          * Write the address of secondary startup routine into the
          * AuxCoreBoot1 where ROM code will jump and start executing
@@ -146,7 +185,7 @@ static void __init wakeup_secondary(void)
          * A barrier is added to ensure that write buffer is drained
          */
         if (omap_secure_apis_support())
-                omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
         else
                 __raw_writel(virt_to_phys(omap5_secondary_startup),
                                                 base + OMAP_AUX_CORE_BOOT_1);
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index e1f289748c5d..6f94b4e7b18d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
 #include <linux/of_irq.h>
@@ -24,6 +25,7 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
+#include <asm/smp_twd.h>
 
 #include <plat/sram.h>
 #include <plat/omap-secure.h>
@@ -41,6 +43,10 @@ static void __iomem *l2cache_base;
 #endif
 
 static void __iomem *sar_ram_base;
+static void __iomem *gic_dist_base_addr;
+static void __iomem *twd_base;
+
+#define IRQ_LOCALTIMER          29
 
 #ifdef CONFIG_OMAP4_ERRATA_I688
 /* Used to implement memory barrier on DRAM path */
@@ -95,12 +101,14 @@ void __init omap_barriers_init(void)
 void __init gic_init_irq(void)
 {
         void __iomem *omap_irq_base;
-        void __iomem *gic_dist_base_addr;
 
         /* Static mapping, never released */
         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
         BUG_ON(!gic_dist_base_addr);
 
+        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
+        BUG_ON(!twd_base);
+
         /* Static mapping, never released */
         omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
         BUG_ON(!omap_irq_base);
@@ -110,6 +118,38 @@ void __init gic_init_irq(void)
         gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 }
 
+void gic_dist_disable(void)
+{
+        if (gic_dist_base_addr)
+                __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
+}
+
+bool gic_dist_disabled(void)
+{
+        return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
+}
+
+void gic_timer_retrigger(void)
+{
+        u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
+        u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
+        u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+
+        if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
+                /*
+                 * The local timer interrupt got lost while the distributor was
+                 * disabled.  Ack the pending interrupt, and retrigger it.
+                 */
+                pr_warn("%s: lost localtimer interrupt\n", __func__);
+                __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+                if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
+                        __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
+                        twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
+                        __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
+                }
+        }
+}
+
 #ifdef CONFIG_CACHE_L2X0
 
 void __iomem *omap4_get_l2cache_base(void)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 67d66131cfa7..fc3c96d5e013 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -102,6 +102,15 @@ extern void enable_omap3630_toggle_l2_on_restore(void);
 static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 
+#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD      (1 << 0)
+
+#if defined(CONFIG_ARCH_OMAP4)
+extern u16 pm44xx_errata;
+#define IS_PM44XX_ERRATUM(id)           (pm44xx_errata & (id))
+#else
+#define IS_PM44XX_ERRATUM(id)           0
+#endif
+
 #ifdef CONFIG_POWER_AVS_OMAP
 extern int omap_devinit_smartreflex(void);
 extern void omap_enable_smartreflex_on_init(void);