552 files changed, 9324 insertions, 16575 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 60219bf94198..ca2da8da6e9c 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -6,6 +6,7 @@ config ALPHA
         select HAVE_OPROFILE
         select HAVE_SYSCALL_WRAPPERS
         select HAVE_IRQ_WORK
+        select HAVE_PCSPKR_PLATFORM
         select HAVE_PERF_EVENTS
         select HAVE_DMA_ATTRS
         select HAVE_GENERIC_HARDIRQS
diff --git a/arch/alpha/include/asm/8253pit.h b/arch/alpha/include/asm/8253pit.h
deleted file mode 100644
index a71c9c1455a7..000000000000
--- a/arch/alpha/include/asm/8253pit.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index 90561c45e7d8..8e47709160f8 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -847,7 +847,7 @@ static void alpha_perf_event_irq_handler(unsigned long la_ptr,
         data.period = event->hw.last_period;
 
         if (alpha_perf_event_set_period(event, hwc, idx)) {
-                if (perf_event_overflow(event, 1, &data, regs)) {
+                if (perf_event_overflow(event, &data, regs)) {
                         /* Interrupts coming too quickly; "throttle" the
                          * counter, i.e., disable it for a little while.
                          */
diff --git a/arch/alpha/kernel/sys_ruffian.c b/arch/alpha/kernel/sys_ruffian.c
index 8de1046fe91e..f33648e4e8cf 100644
--- a/arch/alpha/kernel/sys_ruffian.c
+++ b/arch/alpha/kernel/sys_ruffian.c
@@ -26,7 +26,6 @@
 #include <asm/pgtable.h>
 #include <asm/core_cia.h>
 #include <asm/tlbflush.h>
-#include <asm/8253pit.h>
 
 #include "proto.h"
 #include "irq_impl.h"
diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c
index 818e74ed45dc..e336694ca042 100644
--- a/arch/alpha/kernel/time.c
+++ b/arch/alpha/kernel/time.c
@@ -46,7 +46,6 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/hwrpb.h>
-#include <asm/8253pit.h>
 #include <asm/rtc.h>
 
 #include <linux/mc146818rtc.h>
@@ -91,7 +90,7 @@ DEFINE_PER_CPU(u8, irq_work_pending);
 #define test_irq_work_pending()      __get_cpu_var(irq_work_pending)
 #define clear_irq_work_pending()     __get_cpu_var(irq_work_pending) = 0
 
-void set_irq_work_pending(void)
+void arch_irq_work_raise(void)
 {
         set_irq_work_pending_flag();
 }
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9adc278a22ab..e04fa9d7637c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -642,6 +642,7 @@ config ARCH_SHMOBILE
         select NO_IOPORT
         select SPARSE_IRQ
         select MULTI_IRQ_HANDLER
+        select PM_GENERIC_DOMAINS if PM
         help
           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index e5681636626f..841df7d21c2f 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -255,7 +255,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
                 if (buf == 0) {
                         dev_err(dev, "%s: unable to map unsafe buffer %p!\n",
                                __func__, ptr);
-                        return 0;
+                        return ~0;
                 }
 
                 dev_dbg(dev,
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 47ad3b1a4fee..5a584520db2f 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MMP=y
+CONFIG_MACH_BROWNSTONE=y
 CONFIG_MACH_FLINT=y
 CONFIG_MACH_MARVELL_JASPER=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -63,10 +64,16 @@ CONFIG_BACKLIGHT_MAX8925=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX8925=y
+CONFIG_MMC=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
@@ -81,7 +88,7 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_DYNAMIC_DEBUG is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/include/asm/i8253.h b/arch/arm/include/asm/i8253.h
deleted file mode 100644
index 70656b69d5ce..000000000000
--- a/arch/arm/include/asm/i8253.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __ASMARM_I8253_H
-#define __ASMARM_I8253_H
-
-/* i8253A PIT registers */
-#define PIT_MODE        0x43
-#define PIT_CH0         0x40
-
-#define PIT_LATCH       ((PIT_TICK_RATE + HZ / 2) / HZ)
-
-extern raw_spinlock_t i8253_lock;
-
-#define outb_pit        outb_p
-#define inb_pit         inb_p
-
-#endif
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index d53c0abc4dd3..2b5b1421596c 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -583,7 +583,7 @@ static int armpmu_event_init(struct perf_event *event)
 static void armpmu_enable(struct pmu *pmu)
 {
         /* Enable all of the perf events on hardware. */
-        int idx;
+        int idx, enabled = 0;
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
         if (!armpmu)
@@ -596,9 +596,11 @@ static void armpmu_enable(struct pmu *pmu)
                         continue;
 
                 armpmu->enable(&event->hw, idx);
+                enabled = 1;
         }
 
-        armpmu->start();
+        if (enabled)
+                armpmu->start();
 }
 
 static void armpmu_disable(struct pmu *pmu)
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index f1e8dd94afe8..dd7f3b9f4cb3 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -173,6 +173,20 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                 },
         },
+        [C(NODE)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
 };
 
 enum armv6mpcore_perf_types {
@@ -310,6 +324,20 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
                 },
         },
+        [C(NODE)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
 };
 
 static inline unsigned long
@@ -479,7 +507,7 @@ armv6pmu_handle_irq(int irq_num,
                 if (!armpmu_event_set_period(event, hwc, idx))
                         continue;
 
-                if (perf_event_overflow(event, 0, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         armpmu->disable(hwc, idx);
         }
 
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 4960686afb58..e20ca9cafef5 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -255,6 +255,20 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                 },
         },
+        [C(NODE)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
 };
 
 /*
@@ -371,6 +385,20 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                 },
         },
+        [C(NODE)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
 };
 
 /*
@@ -787,7 +815,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
                 if (!armpmu_event_set_period(event, hwc, idx))
                         continue;
 
-                if (perf_event_overflow(event, 0, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         armpmu->disable(hwc, idx);
         }
 
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 39affbe4fdb2..3c4397491d08 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -144,6 +144,20 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                 },
         },
+        [C(NODE)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
 };
 
 #define XSCALE_PMU_ENABLE       0x001
@@ -251,7 +265,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
                 if (!armpmu_event_set_period(event, hwc, idx))
                         continue;
 
-                if (perf_event_overflow(event, 0, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         armpmu->disable(hwc, idx);
         }
 
@@ -583,7 +597,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
                 if (!armpmu_event_set_period(event, hwc, idx))
                         continue;
 
-                if (perf_event_overflow(event, 0, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         armpmu->disable(hwc, idx);
         }
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 97260060bf26..5c199610719f 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -396,7 +396,7 @@ static long ptrace_hbp_idx_to_num(int idx)
 /*
  * Handle hitting a HW-breakpoint.
  */
-static void ptrace_hbptriggered(struct perf_event *bp, int unused,
+static void ptrace_hbptriggered(struct perf_event *bp,
                                      struct perf_sample_data *data,
                                      struct pt_regs *regs)
 {
@@ -479,7 +479,8 @@ static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
         attr.bp_type    = type;
         attr.disabled   = 1;
 
-        return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, tsk);
+        return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL,
+                                           tsk);
 }
 
 static int ptrace_gethbpregs(struct task_struct *tsk, long num,
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index ed11fb08b05a..acbb447ac6b5 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -73,6 +73,7 @@ __setup("fpe=", fpe_setup);
 #endif
 
 extern void paging_init(struct machine_desc *desc);
+extern void sanity_check_meminfo(void);
 extern void reboot_setup(char *str);
 
 unsigned int processor_id;
@@ -900,6 +901,7 @@ void __init setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+        sanity_check_meminfo();
         arm_memblock_init(&meminfo, mdesc);
 
         paging_init(mdesc);
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 60636f499cb3..2c277d40cee6 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -115,7 +115,7 @@ static void __cpuinit twd_calibrate_rate(void)
                 twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
 
                 printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
-                        (twd_timer_rate / 1000000) % 100);
+                        (twd_timer_rate / 10000) % 100);
         }
 }
 
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index 40ee7e5045e4..5f452f8fde05 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -183,7 +183,7 @@ static int swp_handler(struct pt_regs *regs, unsigned int instr)
         unsigned int address, destreg, data, type;
         unsigned int res = 0;
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, regs->ARM_pc);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->ARM_pc);
 
         if (current->pid != previous_pid) {
                 pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n",
diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h
deleted file mode 100644
index 02182c16a022..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_mci.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_mci.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * MultiMedia Card Interface (MCI) registers.
- * Based on AT91RM9200 datasheet revision F.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_MCI_H
-#define AT91_MCI_H
-
-#define AT91_MCI_CR             0x00            /* Control Register */
-#define         AT91_MCI_MCIEN          (1 <<  0)       /* Multi-Media Interface Enable */
-#define         AT91_MCI_MCIDIS         (1 <<  1)       /* Multi-Media Interface Disable */
-#define         AT91_MCI_PWSEN          (1 <<  2)       /* Power Save Mode Enable */
-#define         AT91_MCI_PWSDIS         (1 <<  3)       /* Power Save Mode Disable */
-#define         AT91_MCI_SWRST          (1 <<  7)       /* Software Reset */
-
-#define AT91_MCI_MR             0x04            /* Mode Register */
-#define         AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
-#define         AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
-#define         AT91_MCI_RDPROOF        (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
-#define         AT91_MCI_WRPROOF        (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
-#define         AT91_MCI_PDCFBYTE       (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
-#define         AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
-#define         AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
-#define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
-
-#define AT91_MCI_DTOR           0x08            /* Data Timeout Register */
-#define         AT91_MCI_DTOCYC         (0xf << 0)      /* Data Timeout Cycle Number */
-#define         AT91_MCI_DTOMUL         (7   << 4)      /* Data Timeout Multiplier */
-#define         AT91_MCI_DTOMUL_1               (0 <<  4)
-#define         AT91_MCI_DTOMUL_16              (1 <<  4)
-#define         AT91_MCI_DTOMUL_128             (2 <<  4)
-#define         AT91_MCI_DTOMUL_256             (3 <<  4)
-#define         AT91_MCI_DTOMUL_1K              (4 <<  4)
-#define         AT91_MCI_DTOMUL_4K              (5 <<  4)
-#define         AT91_MCI_DTOMUL_64K             (6 <<  4)
-#define         AT91_MCI_DTOMUL_1M              (7 <<  4)
-
-#define AT91_MCI_SDCR           0x0c            /* SD Card Register */
-#define         AT91_MCI_SDCSEL         (3 << 0)        /* SD Card Selector */
-#define         AT91_MCI_SDCBUS         (1 << 7)        /* 1-bit or 4-bit bus */
-
-#define AT91_MCI_ARGR           0x10            /* Argument Register */
-
-#define AT91_MCI_CMDR           0x14            /* Command Register */
-#define         AT91_MCI_CMDNB          (0x3f << 0)     /* Command Number */
-#define         AT91_MCI_RSPTYP         (3    << 6)     /* Response Type */
-#define                 AT91_MCI_RSPTYP_NONE    (0 <<  6)
-#define                 AT91_MCI_RSPTYP_48      (1 <<  6)
-#define                 AT91_MCI_RSPTYP_136     (2 <<  6)
-#define         AT91_MCI_SPCMD          (7    << 8)     /* Special Command */
-#define                 AT91_MCI_SPCMD_NONE     (0 <<  8)
-#define                 AT91_MCI_SPCMD_INIT     (1 <<  8)
-#define                 AT91_MCI_SPCMD_SYNC     (2 <<  8)
-#define                 AT91_MCI_SPCMD_ICMD     (4 <<  8)
-#define                 AT91_MCI_SPCMD_IRESP    (5 <<  8)
-#define         AT91_MCI_OPDCMD         (1 << 11)       /* Open Drain Command */
-#define         AT91_MCI_MAXLAT         (1 << 12)       /* Max Latency for Command to Response */
-#define         AT91_MCI_TRCMD          (3 << 16)       /* Transfer Command */
-#define                 AT91_MCI_TRCMD_NONE     (0 << 16)
-#define                 AT91_MCI_TRCMD_START    (1 << 16)
-#define                 AT91_MCI_TRCMD_STOP     (2 << 16)
-#define         AT91_MCI_TRDIR          (1 << 18)       /* Transfer Direction */
-#define         AT91_MCI_TRTYP          (3 << 19)       /* Transfer Type */
-#define                 AT91_MCI_TRTYP_BLOCK    (0 << 19)
-#define                 AT91_MCI_TRTYP_MULTIPLE (1 << 19)
-#define                 AT91_MCI_TRTYP_STREAM   (2 << 19)
-#define                 AT91_MCI_TRTYP_SDIO_BYTE        (4 << 19)
-#define                 AT91_MCI_TRTYP_SDIO_BLOCK       (5 << 19)
-
-#define AT91_MCI_BLKR           0x18            /* Block Register */
-#define         AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
-#define         AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)  /* Block length */
-
-#define AT91_MCI_RSPR(n)        (0x20 + ((n) * 4))      /* Response Registers 0-3 */
-#define AT91_MCR_RDR            0x30            /* Receive Data Register */
-#define AT91_MCR_TDR            0x34            /* Transmit Data Register */
-
-#define AT91_MCI_SR             0x40            /* Status Register */
-#define         AT91_MCI_CMDRDY         (1 <<  0)       /* Command Ready */
-#define         AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
-#define         AT91_MCI_TXRDY          (1 <<  2)       /* Transmit Ready */
-#define         AT91_MCI_BLKE           (1 <<  3)       /* Data Block Ended */
-#define         AT91_MCI_DTIP           (1 <<  4)       /* Data Transfer in Progress */
-#define         AT91_MCI_NOTBUSY        (1 <<  5)       /* Data Not Busy */
-#define         AT91_MCI_ENDRX          (1 <<  6)       /* End of RX Buffer */
-#define         AT91_MCI_ENDTX          (1 <<  7)       /* End fo TX Buffer */
-#define         AT91_MCI_SDIOIRQA       (1 <<  8)       /* SDIO Interrupt for Slot A */
-#define         AT91_MCI_SDIOIRQB       (1 <<  9)       /* SDIO Interrupt for Slot B */
-#define         AT91_MCI_RXBUFF         (1 << 14)       /* RX Buffer Full */
-#define         AT91_MCI_TXBUFE         (1 << 15)       /* TX Buffer Empty */
-#define         AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
-#define         AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
-#define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
-#define         AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
-#define         AT91_MCI_RTOE           (1 << 20)       /* Response Time-out Error */
-#define         AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
-#define         AT91_MCI_DTOE           (1 << 22)       /* Data Time-out Error */
-#define         AT91_MCI_OVRE           (1 << 30)       /* Overrun */
-#define         AT91_MCI_UNRE           (1 << 31)       /* Underrun */
-
-#define AT91_MCI_IER            0x44            /* Interrupt Enable Register */
-#define AT91_MCI_IDR            0x48            /* Interrupt Disable Register */
-#define AT91_MCI_IMR            0x4c            /* Interrupt Mask Register */
-
-#endif
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index c67f684ee3e5..09a87e61ffcf 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -520,7 +520,7 @@ fail:
          */
         if (have_imager()) {
                 label = "HD imager";
-                mux |= 1;
+                mux |= 2;
 
                 /* externally mux MMC1/ENET/AIC33 to imager */
                 mux |= BIT(6) | BIT(5) | BIT(3);
@@ -540,7 +540,7 @@ fail:
                 resets &= ~BIT(1);
 
                 if (have_tvp7002()) {
-                        mux |= 2;
+                        mux |= 1;
                         resets &= ~BIT(2);
                         label = "tvp7002 HD";
                 } else {
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 606a6f27ed6c..5f5d78308873 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -20,6 +20,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
+#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/common.h>
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 1e0f809644bb..e00d61e2efbe 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -8,6 +8,7 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
+#include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index e7221398e5af..cafbe13a82a5 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -254,8 +254,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
         struct davinci_gpio_regs __iomem *g;
         u32 mask = 0xffff;
+        struct davinci_gpio_controller *d;
 
-        g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc);
+        d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
+        g = (struct davinci_gpio_regs __iomem *)d->regs;
 
         /* we only care about one bank */
         if (irq & 1)
@@ -274,11 +276,14 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 if (!status)
                         break;
                 __raw_writel(status, &g->intstat);
-                if (irq & 1)
-                        status >>= 16;
 
                 /* now demux them to the right lowlevel handler */
-                n = (int)irq_get_handler_data(irq);
+                n = d->irq_base;
+                if (irq & 1) {
+                        n += 16;
+                        status >>= 16;
+                }
+
                 while (status) {
                         res = ffs(status);
                         n += res;
@@ -424,7 +429,13 @@ static int __init davinci_gpio_irq_setup(void)
 
                 /* set up all irqs in this bank */
                 irq_set_chained_handler(bank_irq, gpio_irq_handler);
-                irq_set_handler_data(bank_irq, (__force void *)g);
+
+                /*
+                 * Each chip handles 32 gpios, and each irq bank consists of 16
+                 * gpio irqs. Pass the irq bank's corresponding controller to
+                 * the chained irq handler.
+                 */
+                irq_set_handler_data(bank_irq, &chips[gpio / 32]);
 
                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
                         irq_set_chip(irq, &gpio_irqchip);
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index bfe68ec4e1a6..952dc126c390 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -52,8 +52,14 @@ davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
         struct irq_chip_type *ct;
 
         gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
+        if (!gc) {
+                pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
+                       __func__, irq_start);
+                return;
+        }
+
         ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_ack = irq_gc_ack_set_bit;
         ct->chip.irq_mask = irq_gc_mask_clr_bit;
         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index 1bd73a04be20..04c49f7543ef 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -17,6 +17,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/delay.h>
+#include <asm/io.h>
 
 #include <mach/da8xx.h>
 #include <mach/sram.h>
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 33ee2c863d18..3cedcf2d39e5 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -1,11 +1,13 @@
 #
 # Makefile for the linux kernel.
 #
-obj-y                   := core.o clock.o dma-m2p.o gpio.o
+obj-y                   := core.o clock.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
 
+obj-$(CONFIG_EP93XX_DMA)        += dma.o
+
 obj-$(CONFIG_MACH_ADSSPHERE)    += adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)      += edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)    += gesbc9312.o
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 1d4b65fd673e..c60f081e930b 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -174,14 +174,10 @@ struct sys_timer ep93xx_timer = {
 /*************************************************************************
  * EP93xx IRQ handling
  *************************************************************************/
-extern void ep93xx_gpio_init_irq(void);
-
 void __init ep93xx_init_irq(void)
 {
         vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
         vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
-
-        ep93xx_gpio_init_irq();
 }
 
 
@@ -241,6 +237,24 @@ unsigned int ep93xx_chip_revision(void)
 }
 
 /*************************************************************************
+ * EP93xx GPIO
+ *************************************************************************/
+static struct resource ep93xx_gpio_resource[] = {
+        {
+                .start          = EP93XX_GPIO_PHYS_BASE,
+                .end            = EP93XX_GPIO_PHYS_BASE + 0xcc - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device ep93xx_gpio_device = {
+        .name           = "gpio-ep93xx",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ep93xx_gpio_resource),
+        .resource       = ep93xx_gpio_resource,
+};
+
+/*************************************************************************
  * EP93xx peripheral handling
  *************************************************************************/
 #define EP93XX_UART_MCR_OFFSET          (0x0100)
@@ -251,9 +265,9 @@ static void ep93xx_uart_set_mctrl(struct amba_device *dev,
         unsigned int mcr;
 
         mcr = 0;
-        if (!(mctrl & TIOCM_RTS))
+        if (mctrl & TIOCM_RTS)
                 mcr |= 2;
-        if (!(mctrl & TIOCM_DTR))
+        if (mctrl & TIOCM_DTR)
                 mcr |= 1;
 
         __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
@@ -492,11 +506,15 @@ static struct resource ep93xx_spi_resources[] = {
         },
 };
 
+static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
+
 static struct platform_device ep93xx_spi_device = {
         .name           = "ep93xx-spi",
         .id             = 0,
         .dev            = {
-                .platform_data = &ep93xx_spi_master_data,
+                .platform_data          = &ep93xx_spi_master_data,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .dma_mask               = &ep93xx_spi_dma_mask,
         },
         .num_resources  = ARRAY_SIZE(ep93xx_spi_resources),
         .resource       = ep93xx_spi_resources,
@@ -870,14 +888,13 @@ void __init ep93xx_register_ac97(void)
         platform_device_register(&ep93xx_pcm_device);
 }
 
-extern void ep93xx_gpio_init(void);
-
 void __init ep93xx_init_devices(void)
 {
         /* Disallow access to MaverickCrunch initially */
         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
 
-        ep93xx_gpio_init();
+        /* Get the GPIO working early, other devices need it */
+        platform_device_register(&ep93xx_gpio_device);
 
         amba_device_register(&uart1_device, &iomem_resource);
         amba_device_register(&uart2_device, &iomem_resource);
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
deleted file mode 100644
index a696d354b1f8..000000000000
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/dma-m2p.c
- * M2P DMA handling for Cirrus EP93xx chips.
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- * Copyright (C) 2006 Applied Data Systems
- *
- * Copyright (C) 2009 Ryan Mallon <ryan@bluewatersys.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-
-/*
- * On the EP93xx chip the following peripherals my be allocated to the 10
- * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
- *
- *      I2S     contains 3 Tx and 3 Rx DMA Channels
- *      AAC     contains 3 Tx and 3 Rx DMA Channels
- *      UART1   contains 1 Tx and 1 Rx DMA Channels
- *      UART2   contains 1 Tx and 1 Rx DMA Channels
- *      UART3   contains 1 Tx and 1 Rx DMA Channels
- *      IrDA    contains 1 Tx and 1 Rx DMA Channels
- *
- * SSP and IDE use the Memory to Memory (M2M) channels and are not covered
- * with this implementation.
- */
-
-#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include <mach/dma.h>
-#include <mach/hardware.h>
-
-#define M2P_CONTROL                     0x00
-#define  M2P_CONTROL_STALL_IRQ_EN       (1 << 0)
-#define  M2P_CONTROL_NFB_IRQ_EN         (1 << 1)
-#define  M2P_CONTROL_ERROR_IRQ_EN       (1 << 3)
-#define  M2P_CONTROL_ENABLE             (1 << 4)
-#define M2P_INTERRUPT                   0x04
-#define  M2P_INTERRUPT_STALL            (1 << 0)
-#define  M2P_INTERRUPT_NFB              (1 << 1)
-#define  M2P_INTERRUPT_ERROR            (1 << 3)
-#define M2P_PPALLOC                     0x08
-#define M2P_STATUS                      0x0c
-#define M2P_REMAIN                      0x14
-#define M2P_MAXCNT0                     0x20
-#define M2P_BASE0                       0x24
-#define M2P_MAXCNT1                     0x30
-#define M2P_BASE1                       0x34
-
-#define STATE_IDLE      0       /* Channel is inactive.  */
-#define STATE_STALL     1       /* Channel is active, no buffers pending.  */
-#define STATE_ON        2       /* Channel is active, one buffer pending.  */
-#define STATE_NEXT      3       /* Channel is active, two buffers pending.  */
-
-struct m2p_channel {
-        char                            *name;
-        void __iomem                    *base;
-        int                             irq;
-
-        struct clk                      *clk;
-        spinlock_t                      lock;
-
-        void                            *client;
-        unsigned                        next_slot:1;
-        struct ep93xx_dma_buffer        *buffer_xfer;
-        struct ep93xx_dma_buffer        *buffer_next;
-        struct list_head                buffers_pending;
-};
-
-static struct m2p_channel m2p_rx[] = {
-        {"m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1},
-        {"m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3},
-        {"m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5},
-        {"m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7},
-        {"m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9},
-        {NULL},
-};
-
-static struct m2p_channel m2p_tx[] = {
-        {"m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0},
-        {"m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2},
-        {"m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4},
-        {"m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6},
-        {"m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8},
-        {NULL},
-};
-
-static void feed_buf(struct m2p_channel *ch, struct ep93xx_dma_buffer *buf)
-{
-        if (ch->next_slot == 0) {
-                writel(buf->size, ch->base + M2P_MAXCNT0);
-                writel(buf->bus_addr, ch->base + M2P_BASE0);
-        } else {
-                writel(buf->size, ch->base + M2P_MAXCNT1);
-                writel(buf->bus_addr, ch->base + M2P_BASE1);
-        }
-        ch->next_slot ^= 1;
-}
-
-static void choose_buffer_xfer(struct m2p_channel *ch)
-{
-        struct ep93xx_dma_buffer *buf;
-
-        ch->buffer_xfer = NULL;
-        if (!list_empty(&ch->buffers_pending)) {
-                buf = list_entry(ch->buffers_pending.next,
-                                 struct ep93xx_dma_buffer, list);
-                list_del(&buf->list);
-                feed_buf(ch, buf);
-                ch->buffer_xfer = buf;
-        }
-}
-
-static void choose_buffer_next(struct m2p_channel *ch)
-{
-        struct ep93xx_dma_buffer *buf;
-
-        ch->buffer_next = NULL;
-        if (!list_empty(&ch->buffers_pending)) {
-                buf = list_entry(ch->buffers_pending.next,
-                                 struct ep93xx_dma_buffer, list);
-                list_del(&buf->list);
-                feed_buf(ch, buf);
-                ch->buffer_next = buf;
-        }
-}
-
-static inline void m2p_set_control(struct m2p_channel *ch, u32 v)
-{
-        /*
-         * The control register must be read immediately after being written so
-         * that the internal state machine is correctly updated. See the ep93xx
-         * users' guide for details.
-         */
-        writel(v, ch->base + M2P_CONTROL);
-        readl(ch->base + M2P_CONTROL);
-}
-
-static inline int m2p_channel_state(struct m2p_channel *ch)
-{
-        return (readl(ch->base + M2P_STATUS) >> 4) & 0x3;
-}
-
-static irqreturn_t m2p_irq(int irq, void *dev_id)
-{
-        struct m2p_channel *ch = dev_id;
-        struct ep93xx_dma_m2p_client *cl;
-        u32 irq_status, v;
-        int error = 0;
-
-        cl = ch->client;
-
-        spin_lock(&ch->lock);
-        irq_status = readl(ch->base + M2P_INTERRUPT);
-
-        if (irq_status & M2P_INTERRUPT_ERROR) {
-                writel(M2P_INTERRUPT_ERROR, ch->base + M2P_INTERRUPT);
-                error = 1;
-        }
-
-        if ((irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)) == 0) {
-                spin_unlock(&ch->lock);
-                return IRQ_NONE;
-        }
-
-        switch (m2p_channel_state(ch)) {
-        case STATE_IDLE:
-                pr_crit("dma interrupt without a dma buffer\n");
-                BUG();
-                break;
-
-        case STATE_STALL:
-                cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
-                if (ch->buffer_next != NULL) {
-                        cl->buffer_finished(cl->cookie, ch->buffer_next,
-                                            0, error);
-                }
-                choose_buffer_xfer(ch);
-                choose_buffer_next(ch);
-                if (ch->buffer_xfer != NULL)
-                        cl->buffer_started(cl->cookie, ch->buffer_xfer);
-                break;
-
-        case STATE_ON:
-                cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
-                ch->buffer_xfer = ch->buffer_next;
-                choose_buffer_next(ch);
-                cl->buffer_started(cl->cookie, ch->buffer_xfer);
-                break;
-
-        case STATE_NEXT:
-                pr_crit("dma interrupt while next\n");
-                BUG();
-                break;
-        }
-
-        v = readl(ch->base + M2P_CONTROL) & ~(M2P_CONTROL_STALL_IRQ_EN |
-                                              M2P_CONTROL_NFB_IRQ_EN);
-        if (ch->buffer_xfer != NULL)
-                v |= M2P_CONTROL_STALL_IRQ_EN;
-        if (ch->buffer_next != NULL)
-                v |= M2P_CONTROL_NFB_IRQ_EN;
-        m2p_set_control(ch, v);
-
-        spin_unlock(&ch->lock);
-        return IRQ_HANDLED;
-}
-
-static struct m2p_channel *find_free_channel(struct ep93xx_dma_m2p_client *cl)
-{
-        struct m2p_channel *ch;
-        int i;
-
-        if (cl->flags & EP93XX_DMA_M2P_RX)
-                ch = m2p_rx;
-        else
-                ch = m2p_tx;
-
-        for (i = 0; ch[i].base; i++) {
-                struct ep93xx_dma_m2p_client *client;
-
-                client = ch[i].client;
-                if (client != NULL) {
-                        int port;
-
-                        port = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
-                        if (port == (client->flags &
-                                     EP93XX_DMA_M2P_PORT_MASK)) {
-                                pr_warning("DMA channel already used by %s\n",
-                                           cl->name ? : "unknown client");
-                                return ERR_PTR(-EBUSY);
-                        }
-                }
-        }
-
-        for (i = 0; ch[i].base; i++) {
-                if (ch[i].client == NULL)
-                        return ch + i;
-        }
-
-        pr_warning("No free DMA channel for %s\n",
-                   cl->name ? : "unknown client");
-        return ERR_PTR(-ENODEV);
-}
-
-static void channel_enable(struct m2p_channel *ch)
-{
-        struct ep93xx_dma_m2p_client *cl = ch->client;
-        u32 v;
-
-        clk_enable(ch->clk);
-
-        v = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
-        writel(v, ch->base + M2P_PPALLOC);
-
-        v = cl->flags & EP93XX_DMA_M2P_ERROR_MASK;
-        v |= M2P_CONTROL_ENABLE | M2P_CONTROL_ERROR_IRQ_EN;
-        m2p_set_control(ch, v);
-}
-
-static void channel_disable(struct m2p_channel *ch)
-{
-        u32 v;
-
-        v = readl(ch->base + M2P_CONTROL);
-        v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
-        m2p_set_control(ch, v);
-
-        while (m2p_channel_state(ch) >= STATE_ON)
-                cpu_relax();
-
-        m2p_set_control(ch, 0x0);
-
-        while (m2p_channel_state(ch) == STATE_STALL)
-                cpu_relax();
-
-        clk_disable(ch->clk);
-}
-
-int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *cl)
-{
-        struct m2p_channel *ch;
-        int err;
-
-        ch = find_free_channel(cl);
-        if (IS_ERR(ch))
-                return PTR_ERR(ch);
-
-        err = request_irq(ch->irq, m2p_irq, 0, cl->name ? : "dma-m2p", ch);
-        if (err)
-                return err;
-
-        ch->client = cl;
-        ch->next_slot = 0;
-        ch->buffer_xfer = NULL;
-        ch->buffer_next = NULL;
-        INIT_LIST_HEAD(&ch->buffers_pending);
-
-        cl->channel = ch;
-
-        channel_enable(ch);
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_register);
-
-void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *cl)
-{
-        struct m2p_channel *ch = cl->channel;
-
-        channel_disable(ch);
-        free_irq(ch->irq, ch);
-        ch->client = NULL;
-}
-EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_unregister);
-
-void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *cl,
-                           struct ep93xx_dma_buffer *buf)
-{
-        struct m2p_channel *ch = cl->channel;
-        unsigned long flags;
-        u32 v;
-
-        spin_lock_irqsave(&ch->lock, flags);
-        v = readl(ch->base + M2P_CONTROL);
-        if (ch->buffer_xfer == NULL) {
-                ch->buffer_xfer = buf;
-                feed_buf(ch, buf);
-                cl->buffer_started(cl->cookie, buf);
-
-                v |= M2P_CONTROL_STALL_IRQ_EN;
-                m2p_set_control(ch, v);
-
-        } else if (ch->buffer_next == NULL) {
-                ch->buffer_next = buf;
-                feed_buf(ch, buf);
-
-                v |= M2P_CONTROL_NFB_IRQ_EN;
-                m2p_set_control(ch, v);
-        } else {
-                list_add_tail(&buf->list, &ch->buffers_pending);
-        }
-        spin_unlock_irqrestore(&ch->lock, flags);
-}
-EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit);
-
-void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *cl,
-                                     struct ep93xx_dma_buffer *buf)
-{
-        struct m2p_channel *ch = cl->channel;
-
-        list_add_tail(&buf->list, &ch->buffers_pending);
-}
-EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit_recursive);
-
-void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *cl)
-{
-        struct m2p_channel *ch = cl->channel;
-
-        channel_disable(ch);
-        ch->next_slot = 0;
-        ch->buffer_xfer = NULL;
-        ch->buffer_next = NULL;
-        INIT_LIST_HEAD(&ch->buffers_pending);
-        channel_enable(ch);
-}
-EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_flush);
-
-static int init_channel(struct m2p_channel *ch)
-{
-        ch->clk = clk_get(NULL, ch->name);
-        if (IS_ERR(ch->clk))
-                return PTR_ERR(ch->clk);
-
-        spin_lock_init(&ch->lock);
-        ch->client = NULL;
-
-        return 0;
-}
-
-static int __init ep93xx_dma_m2p_init(void)
-{
-        int i;
-        int ret;
-
-        for (i = 0; m2p_rx[i].base; i++) {
-                ret = init_channel(m2p_rx + i);
-                if (ret)
-                        return ret;
-        }
-
-        for (i = 0; m2p_tx[i].base; i++) {
-                ret = init_channel(m2p_tx + i);
-                if (ret)
-                        return ret;
-        }
-
-        pr_info("M2P DMA subsystem initialized\n");
-        return 0;
-}
-arch_initcall(ep93xx_dma_m2p_init);
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
new file mode 100644
index 000000000000..5a2570881255
--- /dev/null
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -0,0 +1,108 @@
+/*
+ * arch/arm/mach-ep93xx/dma.c
+ *
+ * Platform support code for the EP93xx dmaengine driver.
+ *
+ * Copyright (C) 2011 Mika Westerberg
+ *
+ * This work is based on the original dma-m2p implementation with
+ * following copyrights:
+ *
+ *   Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *   Copyright (C) 2006 Applied Data Systems
+ *   Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/dma.h>
+#include <mach/hardware.h>
+
+#define DMA_CHANNEL(_name, _base, _irq) \
+        { .name = (_name), .base = (_base), .irq = (_irq) }
+
+/*
+ * DMA M2P channels.
+ *
+ * On the EP93xx chip the following peripherals my be allocated to the 10
+ * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
+ *
+ *      I2S     contains 3 Tx and 3 Rx DMA Channels
+ *      AAC     contains 3 Tx and 3 Rx DMA Channels
+ *      UART1   contains 1 Tx and 1 Rx DMA Channels
+ *      UART2   contains 1 Tx and 1 Rx DMA Channels
+ *      UART3   contains 1 Tx and 1 Rx DMA Channels
+ *      IrDA    contains 1 Tx and 1 Rx DMA Channels
+ *
+ * Registers are mapped statically in ep93xx_map_io().
+ */
+static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
+        DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
+        DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
+        DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
+        DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
+        DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
+        DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
+        DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
+        DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
+        DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
+        DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
+};
+
+static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
+        .channels               = ep93xx_dma_m2p_channels,
+        .num_channels           = ARRAY_SIZE(ep93xx_dma_m2p_channels),
+};
+
+static struct platform_device ep93xx_dma_m2p_device = {
+        .name                   = "ep93xx-dma-m2p",
+        .id                     = -1,
+        .dev                    = {
+                .platform_data  = &ep93xx_dma_m2p_data,
+        },
+};
+
+/*
+ * DMA M2M channels.
+ *
+ * There are 2 M2M channels which support memcpy/memset and in addition simple
+ * hardware requests from/to SSP and IDE. We do not implement an external
+ * hardware requests.
+ *
+ * Registers are mapped statically in ep93xx_map_io().
+ */
+static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
+        DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
+        DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
+};
+
+static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
+        .channels               = ep93xx_dma_m2m_channels,
+        .num_channels           = ARRAY_SIZE(ep93xx_dma_m2m_channels),
+};
+
+static struct platform_device ep93xx_dma_m2m_device = {
+        .name                   = "ep93xx-dma-m2m",
+        .id                     = -1,
+        .dev                    = {
+                .platform_data  = &ep93xx_dma_m2m_data,
+        },
+};
+
+static int __init ep93xx_dma_init(void)
+{
+        platform_device_register(&ep93xx_dma_m2p_device);
+        platform_device_register(&ep93xx_dma_m2m_device);
+        return 0;
+}
+arch_initcall(ep93xx_dma_init);
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
deleted file mode 100644
index 415dce37b88c..000000000000
--- a/arch/arm/mach-ep93xx/gpio.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * linux/arch/arm/mach-ep93xx/gpio.c
- *
- * Generic EP93xx GPIO handling
- *
- * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
- *
- * Based on code originally from:
- *  linux/arch/arm/mach-ep93xx/core.c
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/seq_file.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-
-#include <mach/hardware.h>
-
-/*************************************************************************
- * Interrupt handling for EP93xx on-chip GPIOs
- *************************************************************************/
-static unsigned char gpio_int_unmasked[3];
-static unsigned char gpio_int_enabled[3];
-static unsigned char gpio_int_type1[3];
-static unsigned char gpio_int_type2[3];
-static unsigned char gpio_int_debounce[3];
-
-/* Port ordering is: A B F */
-static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
-static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
-static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
-static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
-static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
-
-static void ep93xx_gpio_update_int_params(unsigned port)
-{
-        BUG_ON(port > 2);
-
-        __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
-
-        __raw_writeb(gpio_int_type2[port],
-                EP93XX_GPIO_REG(int_type2_register_offset[port]));
-
-        __raw_writeb(gpio_int_type1[port],
-                EP93XX_GPIO_REG(int_type1_register_offset[port]));
-
-        __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
-                EP93XX_GPIO_REG(int_en_register_offset[port]));
-}
-
-static inline void ep93xx_gpio_int_mask(unsigned line)
-{
-        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
-}
-
-static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if (enable)
-                gpio_int_debounce[port] |= port_mask;
-        else
-                gpio_int_debounce[port] &= ~port_mask;
-
-        __raw_writeb(gpio_int_debounce[port],
-                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
-}
-
-static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned char status;
-        int i;
-
-        status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-
-        status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-}
-
-static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        /*
-         * map discontiguous hw irq range to continuous sw irq range:
-         *
-         *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
-         */
-        int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
-        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
-
-        generic_handle_irq(gpio_irq);
-}
-
-static void ep93xx_gpio_irq_ack(struct irq_data *d)
-{
-        int line = irq_to_gpio(d->irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-                ep93xx_gpio_update_int_params(port);
-        }
-
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
-{
-        int line = irq_to_gpio(d->irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-
-        gpio_int_unmasked[port] &= ~port_mask;
-        ep93xx_gpio_update_int_params(port);
-
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask(struct irq_data *d)
-{
-        int line = irq_to_gpio(d->irq);
-        int port = line >> 3;
-
-        gpio_int_unmasked[port] &= ~(1 << (line & 7));
-        ep93xx_gpio_update_int_params(port);
-}
-
-static void ep93xx_gpio_irq_unmask(struct irq_data *d)
-{
-        int line = irq_to_gpio(d->irq);
-        int port = line >> 3;
-
-        gpio_int_unmasked[port] |= 1 << (line & 7);
-        ep93xx_gpio_update_int_params(port);
-}
-
-/*
- * gpio_int_type1 controls whether the interrupt is level (0) or
- * edge (1) triggered, while gpio_int_type2 controls whether it
- * triggers on low/falling (0) or high/rising (1).
- */
-static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
-{
-        const int gpio = irq_to_gpio(d->irq);
-        const int port = gpio >> 3;
-        const int port_mask = 1 << (gpio & 7);
-        irq_flow_handler_t handler;
-
-        gpio_direction_input(gpio);
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] |= port_mask;
-                handler = handle_edge_irq;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                handler = handle_edge_irq;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] |= port_mask;
-                handler = handle_level_irq;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                handler = handle_level_irq;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                gpio_int_type1[port] |= port_mask;
-                /* set initial polarity based on current input level */
-                if (gpio_get_value(gpio))
-                        gpio_int_type2[port] &= ~port_mask; /* falling */
-                else
-                        gpio_int_type2[port] |= port_mask; /* rising */
-                handler = handle_edge_irq;
-                break;
-        default:
-                pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
-                return -EINVAL;
-        }
-
-        __irq_set_handler_locked(d->irq, handler);
-
-        gpio_int_enabled[port] |= port_mask;
-
-        ep93xx_gpio_update_int_params(port);
-
-        return 0;
-}
-
-static struct irq_chip ep93xx_gpio_irq_chip = {
-        .name           = "GPIO",
-        .irq_ack        = ep93xx_gpio_irq_ack,
-        .irq_mask_ack   = ep93xx_gpio_irq_mask_ack,
-        .irq_mask       = ep93xx_gpio_irq_mask,
-        .irq_unmask     = ep93xx_gpio_irq_unmask,
-        .irq_set_type   = ep93xx_gpio_irq_type,
-};
-
-void __init ep93xx_gpio_init_irq(void)
-{
-        int gpio_irq;
-
-        for (gpio_irq = gpio_to_irq(0);
-             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
-                irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
-                                         handle_level_irq);
-                set_irq_flags(gpio_irq, IRQF_VALID);
-        }
-
-        irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
-                                ep93xx_gpio_ab_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
-                                ep93xx_gpio_f_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
-                                ep93xx_gpio_f_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
-                                ep93xx_gpio_f_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
-                                ep93xx_gpio_f_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
-                                ep93xx_gpio_f_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
-                                ep93xx_gpio_f_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
-                                ep93xx_gpio_f_irq_handler);
-        irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
-                                ep93xx_gpio_f_irq_handler);
-}
-
-
-/*************************************************************************
- * gpiolib interface for EP93xx on-chip GPIOs
- *************************************************************************/
-struct ep93xx_gpio_chip {
-        struct gpio_chip        chip;
-
-        void __iomem            *data_reg;
-        void __iomem            *data_dir_reg;
-};
-
-#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
-
-static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
-        unsigned long flags;
-        u8 v;
-
-        local_irq_save(flags);
-        v = __raw_readb(ep93xx_chip->data_dir_reg);
-        v &= ~(1 << offset);
-        __raw_writeb(v, ep93xx_chip->data_dir_reg);
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int val)
-{
-        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
-        unsigned long flags;
-        int line;
-        u8 v;
-
-        local_irq_save(flags);
-
-        /* Set the value */
-        v = __raw_readb(ep93xx_chip->data_reg);
-        if (val)
-                v |= (1 << offset);
-        else
-                v &= ~(1 << offset);
-        __raw_writeb(v, ep93xx_chip->data_reg);
-
-        /* Drive as an output */
-        line = chip->base + offset;
-        if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
-                /* Ports A/B/F */
-                ep93xx_gpio_int_mask(line);
-                ep93xx_gpio_update_int_params(line >> 3);
-        }
-
-        v = __raw_readb(ep93xx_chip->data_dir_reg);
-        v |= (1 << offset);
-        __raw_writeb(v, ep93xx_chip->data_dir_reg);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
-
-        return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
-}
-
-static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
-{
-        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
-        unsigned long flags;
-        u8 v;
-
-        local_irq_save(flags);
-        v = __raw_readb(ep93xx_chip->data_reg);
-        if (val)
-                v |= (1 << offset);
-        else
-                v &= ~(1 << offset);
-        __raw_writeb(v, ep93xx_chip->data_reg);
-        local_irq_restore(flags);
-}
-
-static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
-                                    unsigned offset, unsigned debounce)
-{
-        int gpio = chip->base + offset;
-        int irq = gpio_to_irq(gpio);
-
-        if (irq < 0)
-                return -EINVAL;
-
-        ep93xx_gpio_int_debounce(irq, debounce ? true : false);
-
-        return 0;
-}
-
-#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio)                      \
-        {                                                               \
-                .chip = {                                               \
-                        .label            = name,                       \
-                        .direction_input  = ep93xx_gpio_direction_input, \
-                        .direction_output = ep93xx_gpio_direction_output, \
-                        .get              = ep93xx_gpio_get,            \
-                        .set              = ep93xx_gpio_set,            \
-                        .base             = base_gpio,                  \
-                        .ngpio            = 8,                          \
-                },                                                      \
-                .data_reg       = EP93XX_GPIO_REG(dr),                  \
-                .data_dir_reg   = EP93XX_GPIO_REG(ddr),                 \
-        }
-
-static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
-        EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
-        EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
-        EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
-        EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
-        EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
-        EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
-        EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
-        EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
-};
-
-void __init ep93xx_gpio_init(void)
-{
-        int i;
-
-        /* Set Ports C, D, E, G, and H for GPIO use */
-        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
-                                 EP93XX_SYSCON_DEVCFG_GONK |
-                                 EP93XX_SYSCON_DEVCFG_EONIDE |
-                                 EP93XX_SYSCON_DEVCFG_GONIDE |
-                                 EP93XX_SYSCON_DEVCFG_HONIDE);
-
-        for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
-                struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip;
-
-                /*
-                 * Ports A, B, and F support input debouncing when
-                 * used as interrupts.
-                 */
-                if (!strcmp(chip->label, "A") ||
-                    !strcmp(chip->label, "B") ||
-                    !strcmp(chip->label, "F"))
-                        chip->set_debounce = ep93xx_gpio_set_debounce;
-
-                gpiochip_add(chip);
-        }
-}
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index 5e31b2b25da9..46d4d876e6fb 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -1,149 +1,93 @@
-/**
- * DOC: EP93xx DMA M2P memory to peripheral and peripheral to memory engine
- *
- * The EP93xx DMA M2P subsystem handles DMA transfers between memory and
- * peripherals. DMA M2P channels are available for audio, UARTs and IrDA.
- * See chapter 10 of the EP93xx users guide for full details on the DMA M2P
- * engine.
- *
- * See sound/soc/ep93xx/ep93xx-pcm.c for an example use of the DMA M2P code.
- *
- */
-
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
 
-#include <linux/list.h>
 #include <linux/types.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 
-/**
- * struct ep93xx_dma_buffer - Information about a buffer to be transferred
- * using the DMA M2P engine
+/*
+ * M2P channels.
  *
- * @list: Entry in DMA buffer list
- * @bus_addr: Physical address of the buffer
- * @size: Size of the buffer in bytes
+ * Note that these values are also directly used for setting the PPALLOC
+ * register.
  */
-struct ep93xx_dma_buffer {
-        struct list_head        list;
-        u32                     bus_addr;
-        u16                     size;
-};
+#define EP93XX_DMA_I2S1         0
+#define EP93XX_DMA_I2S2         1
+#define EP93XX_DMA_AAC1         2
+#define EP93XX_DMA_AAC2         3
+#define EP93XX_DMA_AAC3         4
+#define EP93XX_DMA_I2S3         5
+#define EP93XX_DMA_UART1        6
+#define EP93XX_DMA_UART2        7
+#define EP93XX_DMA_UART3        8
+#define EP93XX_DMA_IRDA         9
+/* M2M channels */
+#define EP93XX_DMA_SSP          10
+#define EP93XX_DMA_IDE          11
 
 /**
- * struct ep93xx_dma_m2p_client - Information about a DMA M2P client
- *
- * @name: Unique name for this client
- * @flags: Client flags
- * @cookie: User data to pass to callback functions
- * @buffer_started: Non NULL function to call when a transfer is started.
- *                      The arguments are the user data cookie and the DMA
- *                      buffer which is starting.
- * @buffer_finished: Non NULL function to call when a transfer is completed.
- *                      The arguments are the user data cookie, the DMA buffer
- *                      which has completed, and a boolean flag indicating if
- *                      the transfer had an error.
+ * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
+ * @port: peripheral which is requesting the channel
+ * @direction: TX/RX channel
+ * @name: optional name for the channel, this is displayed in /proc/interrupts
+ *
+ * This information is passed as private channel parameter in a filter
+ * function. Note that this is only needed for slave/cyclic channels.  For
+ * memcpy channels %NULL data should be passed.
  */
-struct ep93xx_dma_m2p_client {
-        char                    *name;
-        u8                      flags;
-        void                    *cookie;
-        void                    (*buffer_started)(void *cookie,
-                                        struct ep93xx_dma_buffer *buf);
-        void                    (*buffer_finished)(void *cookie,
-                                        struct ep93xx_dma_buffer *buf,
-                                        int bytes, int error);
-
-        /* private: Internal use only */
-        void                    *channel;
+struct ep93xx_dma_data {
+        int                             port;
+        enum dma_data_direction         direction;
+        const char                      *name;
 };
 
-/* DMA M2P ports */
-#define EP93XX_DMA_M2P_PORT_I2S1        0x00
-#define EP93XX_DMA_M2P_PORT_I2S2        0x01
-#define EP93XX_DMA_M2P_PORT_AAC1        0x02
-#define EP93XX_DMA_M2P_PORT_AAC2        0x03
-#define EP93XX_DMA_M2P_PORT_AAC3        0x04
-#define EP93XX_DMA_M2P_PORT_I2S3        0x05
-#define EP93XX_DMA_M2P_PORT_UART1       0x06
-#define EP93XX_DMA_M2P_PORT_UART2       0x07
-#define EP93XX_DMA_M2P_PORT_UART3       0x08
-#define EP93XX_DMA_M2P_PORT_IRDA        0x09
-#define EP93XX_DMA_M2P_PORT_MASK        0x0f
-
-/* DMA M2P client flags */
-#define EP93XX_DMA_M2P_TX               0x00    /* Memory to peripheral */
-#define EP93XX_DMA_M2P_RX               0x10    /* Peripheral to memory */
-
-/*
- * DMA M2P client error handling flags. See the EP93xx users guide
- * documentation on the DMA M2P CONTROL register for more details
- */
-#define EP93XX_DMA_M2P_ABORT_ON_ERROR   0x20    /* Abort on peripheral error */
-#define EP93XX_DMA_M2P_IGNORE_ERROR     0x40    /* Ignore peripheral errors */
-#define EP93XX_DMA_M2P_ERROR_MASK       0x60    /* Mask of error bits */
-
 /**
- * ep93xx_dma_m2p_client_register - Register a client with the DMA M2P
- * subsystem
- *
- * @m2p: Client information to register
- * returns 0 on success
- *
- * The DMA M2P subsystem allocates a channel and an interrupt line for the DMA
- * client
+ * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
+ * @name: name of the channel, used for getting the right clock for the channel
+ * @base: mapped registers
+ * @irq: interrupt number used by this channel
  */
-int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
+struct ep93xx_dma_chan_data {
+        const char                      *name;
+        void __iomem                    *base;
+        int                             irq;
+};
 
 /**
- * ep93xx_dma_m2p_client_unregister - Unregister a client from the DMA M2P
- * subsystem
- *
- * @m2p: Client to unregister
+ * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
+ * @channels: array of channels which are passed to the driver
+ * @num_channels: number of channels in the array
  *
- * Any transfers currently in progress will be completed in hardware, but
- * ignored in software.
+ * This structure is passed to the DMA engine driver via platform data. For
+ * M2P channels, contract is that even channels are for TX and odd for RX.
+ * There is no requirement for the M2M channels.
  */
-void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p);
+struct ep93xx_dma_platform_data {
+        struct ep93xx_dma_chan_data     *channels;
+        size_t                          num_channels;
+};
 
-/**
- * ep93xx_dma_m2p_submit - Submit a DMA M2P transfer
- *
- * @m2p: DMA Client to submit the transfer on
- * @buf: DMA Buffer to submit
- *
- * If the current or next transfer positions are free on the M2P client then
- * the transfer is started immediately. If not, the transfer is added to the
- * list of pending transfers. This function must not be called from the
- * buffer_finished callback for an M2P channel.
- *
- */
-void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
-                           struct ep93xx_dma_buffer *buf);
+static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
+{
+        return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");
+}
 
 /**
- * ep93xx_dma_m2p_submit_recursive - Put a DMA transfer on the pending list
- * for an M2P channel
+ * ep93xx_dma_chan_direction - returns direction the channel can be used
+ * @chan: channel
  *
- * @m2p: DMA Client to submit the transfer on
- * @buf: DMA Buffer to submit
- *
- * This function must only be called from the buffer_finished callback for an
- * M2P channel. It is commonly used to add the next transfer in a chained list
- * of DMA transfers.
+ * This function can be used in filter functions to find out whether the
+ * channel supports given DMA direction. Only M2P channels have such
+ * limitation, for M2M channels the direction is configurable.
  */
-void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p,
-                                     struct ep93xx_dma_buffer *buf);
+static inline enum dma_data_direction
+ep93xx_dma_chan_direction(struct dma_chan *chan)
+{
+        if (!ep93xx_dma_chan_is_m2p(chan))
+                return DMA_NONE;
 
-/**
- * ep93xx_dma_m2p_flush - Flush all pending transfers on a DMA M2P client
- *
- * @m2p: DMA client to flush transfers on
- *
- * Any transfers currently in progress will be completed in hardware, but
- * ignored in software.
- *
- */
-void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
+        /* even channels are for TX, odd for RX */
+        return (chan->chan_id % 2 == 0) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+}
 
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 9ac4d1055097..c4a7b84ef06d 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -98,6 +98,7 @@
 
 #define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
 
+#define EP93XX_GPIO_PHYS_BASE           EP93XX_APB_PHYS(0x00040000)
 #define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
 #define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
 #define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
index 0a37961b3453..9bb63ac13f04 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
@@ -7,9 +7,11 @@ struct spi_device;
  * struct ep93xx_spi_info - EP93xx specific SPI descriptor
  * @num_chipselect: number of chip selects on this board, must be
  *                  at least one
+ * @use_dma: use DMA for the transfers
  */
 struct ep93xx_spi_info {
         int     num_chipselect;
+        bool    use_dma;
 };
 
 /**
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 9babe4473e88..bfd621460abf 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -23,6 +23,7 @@
 #include <plat/sdhci.h>
 #include <plat/devs.h>
 #include <plat/fimc-core.h>
+#include <plat/iic-core.h>
 
 #include <mach/regs-irq.h>
 
@@ -132,6 +133,11 @@ void __init exynos4_map_io(void)
         s3c_fimc_setname(1, "exynos4-fimc");
         s3c_fimc_setname(2, "exynos4-fimc");
         s3c_fimc_setname(3, "exynos4-fimc");
+
+        /* The I2C bus controllers are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+        s3c_i2c2_setname("s3c2440-i2c");
 }
 
 void __init exynos4_init_clocks(int xtal)
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index 1eed5f9f7bd3..983069a53239 100644
--- a/arch/arm/mach-exynos4/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -330,7 +330,7 @@ struct platform_device exynos4_device_ac97 = {
 
 static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
 {
-        s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
+        s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
 
         return 0;
 }
diff --git a/arch/arm/mach-exynos4/headsmp.S b/arch/arm/mach-exynos4/headsmp.S
index 6c6cfc50c46b..3cdeb3647542 100644
--- a/arch/arm/mach-exynos4/headsmp.S
+++ b/arch/arm/mach-exynos4/headsmp.S
@@ -13,7 +13,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-        __INIT
+        __CPUINIT
 
 /*
  * exynos4 specific entry point for secondary CPUs.  This provides
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 152676471b67..edd814110da8 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -78,9 +78,7 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
 };
 
 static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
         .max_width              = 8,
@@ -96,9 +94,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
 };
 
 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
         .max_width              = 8,
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index 46adca068f2c..dc26fff22cf0 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -5,6 +5,7 @@ menu "Footbridge Implementations"
 config ARCH_CATS
         bool "CATS"
         select CLKSRC_I8253
+        select CLKEVT_I8253
         select FOOTBRIDGE_HOST
         select ISA
         select ISA_DMA
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
index 7020f1a3feca..c40bb415f4b5 100644
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ b/arch/arm/mach-footbridge/isa-timer.c
@@ -5,64 +5,18 @@
  *  Copyright (C) 1998 Phil Blundell
  */
 #include <linux/clockchips.h>
-#include <linux/clocksource.h>
+#include <linux/i8253.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/io.h>
 #include <linux/spinlock.h>
 #include <linux/timex.h>
 
 #include <asm/irq.h>
-#include <asm/i8253.h>
 #include <asm/mach/time.h>
 
 #include "common.h"
 
-DEFINE_RAW_SPINLOCK(i8253_lock);
-
-static void pit_set_mode(enum clock_event_mode mode,
-        struct clock_event_device *evt)
-{
-        unsigned long flags;
-
-        raw_local_irq_save(flags);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                outb_p(0x34, PIT_MODE);
-                outb_p(PIT_LATCH & 0xff, PIT_CH0);
-                outb_p(PIT_LATCH >> 8, PIT_CH0);
-                break;
-
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-                outb_p(0x30, PIT_MODE);
-                outb_p(0, PIT_CH0);
-                outb_p(0, PIT_CH0);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-        local_irq_restore(flags);
-}
-
-static int pit_set_next_event(unsigned long delta,
-        struct clock_event_device *evt)
-{
-        return 0;
-}
-
-static struct clock_event_device pit_ce = {
-        .name           = "pit",
-        .features       = CLOCK_EVT_FEAT_PERIODIC,
-        .set_mode       = pit_set_mode,
-        .set_next_event = pit_set_next_event,
-        .shift          = 32,
-};
-
 static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *ce = dev_id;
@@ -74,20 +28,15 @@ static struct irqaction pit_timer_irq = {
         .name           = "pit",
         .handler        = pit_timer_interrupt,
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .dev_id         = &pit_ce,
+        .dev_id         = &i8253_clockevent,
 };
 
 static void __init isa_timer_init(void)
 {
-        pit_ce.cpumask = cpumask_of(smp_processor_id());
-        pit_ce.mult = div_sc(PIT_TICK_RATE, NSEC_PER_SEC, pit_ce.shift);
-        pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce);
-        pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce);
-
         clocksource_i8253_init();
 
-        setup_irq(pit_ce.irq, &pit_timer_irq);
-        clockevents_register_device(&pit_ce);
+        setup_irq(i8253_clockevent.irq, &pit_timer_irq);
+        clockevent_i8253_init(false);
 }
 
 struct sys_timer isa_timer = {
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index a65838fc061c..af1c580b06bc 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -282,9 +282,10 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-        _REGISTER_CLOCK("imx25-cspi.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("imx25-cspi.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("imx25-cspi.2", NULL, cspi3_clk)
+        /* i.mx25 has the i.mx35 type cspi */
+        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx35-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index 236f1495efad..f8aa5be0eb15 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/clk.h>
 #include <linux/scatterlist.h>
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 15e45c84e371..59d2a3b137d9 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -115,6 +115,8 @@ static struct platform_device *devices[] __initdata = {
 
 static void __init apf9328_init(void)
 {
+        imx1_soc_init();
+
         mxc_gpio_setup_multiple_pins(apf9328_pins,
                         ARRAY_SIZE(apf9328_pins),
                         "APF9328");
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index ffb40ff619b1..ede2710f8b76 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -490,6 +490,8 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init armadillo5x0_init(void)
 {
+        imx31_soc_init();
+
         mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
                         ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 42e4f078a19c..f49470553bdf 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -42,6 +42,8 @@ static const unsigned int bug_pins[] __initconst = {
 
 static void __init bug_board_init(void)
 {
+        imx31_soc_init();
+
         mxc_iomux_setup_multiple_pins(bug_pins,
                                       ARRAY_SIZE(bug_pins), "uart-4");
         imx31_add_imx_uart4(&uart_pdata);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 46a2e41d43d2..87887ac5806b 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -250,6 +250,8 @@ __setup("otg_mode=", eukrea_cpuimx27_otg_mode);
 
 static void __init eukrea_cpuimx27_init(void)
 {
+        imx27_soc_init();
+
         mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
                 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
 
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 3f8ef825fa6f..f39a478ba1a6 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -156,6 +156,8 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
  */
 static void __init eukrea_cpuimx35_init(void)
 {
+        imx35_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
 
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 148cff2819b9..da36da52969d 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -125,6 +125,8 @@ __setup("otg_mode=", eukrea_cpuimx25_otg_mode);
 
 static void __init eukrea_cpuimx25_init(void)
 {
+        imx25_soc_init();
+
         if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
                         ARRAY_SIZE(eukrea_cpuimx25_pads)))
                 printk(KERN_ERR "error setting cpuimx25 pads !\n");
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 7ae43b1ec517..c6269d60ddbc 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -231,6 +231,8 @@ static void __init visstrim_m10_board_init(void)
 {
         int ret;
 
+        imx27_soc_init();
+
         ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
                         ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
         if (ret)
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 9be6cd6fbf8c..272f793e9247 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -50,6 +50,8 @@ static const int mx27ipcam_pins[] __initconst = {
 
 static void __init mx27ipcam_init(void)
 {
+        imx27_soc_init();
+
         mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
                 "mx27ipcam");
 
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 841140516ede..d81a769fe895 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -59,6 +59,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 
 static void __init mx27lite_init(void)
 {
+        imx27_soc_init();
+
         mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
                 "imx27lite");
         imx27_add_imx_uart0(&uart_pdata);
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 1ecae20cf4e3..e472a1d88058 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -223,6 +223,8 @@ static int kzm_pins[] __initdata = {
  */
 static void __init kzm_board_init(void)
 {
+        imx31_soc_init();
+
         mxc_iomux_setup_multiple_pins(kzm_pins,
                                       ARRAY_SIZE(kzm_pins), "kzm");
         kzm_init_ext_uart();
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 38ec5cbbda9b..5cd8bee46960 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -115,6 +115,8 @@ static struct i2c_board_info mx1ads_i2c_devices[] = {
  */
 static void __init mx1ads_init(void)
 {
+        imx1_soc_init();
+
         mxc_gpio_setup_multiple_pins(mx1ads_pins,
                 ARRAY_SIZE(mx1ads_pins), "mx1ads");
 
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 74ac88978ddd..d389ecf9b5a8 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -279,6 +279,8 @@ static struct platform_device *platform_devices[] __initdata = {
 
 static void __init mx21ads_board_init(void)
 {
+        imx21_soc_init();
+
         mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
                         "mx21ads");
 
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 58ea3fdf0911..01534bb61305 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -219,6 +219,8 @@ static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
 
 static void __init mx25pdk_init(void)
 {
+        imx25_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
                         ARRAY_SIZE(mx25pdk_pads));
 
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 6e1accf93f81..117ce0a50f4e 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -267,6 +267,8 @@ static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
 
 static void __init mx27pdk_init(void)
 {
+        imx27_soc_init();
+
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
                 "mx27pdk");
         mx27_3ds_sdhc1_enable_level_translator();
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 1db79506f5e4..fc26ed71b9ed 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -288,6 +288,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 
 static void __init mx27ads_board_init(void)
 {
+        imx27_soc_init();
+
         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
                         "mx27ads");
 
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 9b982449cb52..441fbb83f39c 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -13,6 +13,7 @@
  */
 
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/clk.h>
@@ -689,6 +690,8 @@ static void __init mx31_3ds_init(void)
 {
         int ret;
 
+        imx31_soc_init();
+
         mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
                                       "mx31_3ds");
 
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index f4dee0254634..0ce49478a479 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -516,6 +516,8 @@ static void __init mx31ads_init_irq(void)
 
 static void __init mx31ads_init(void)
 {
+        imx31_soc_init();
+
         mxc_init_extuart();
         mxc_init_imx_uart();
         mxc_init_i2c();
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 410e676ae087..750368ddf0f9 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -243,6 +243,8 @@ core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
 
 static void __init mx31lilly_board_init(void)
 {
+        imx31_soc_init();
+
         switch (mx31lilly_baseboard) {
         case MX31LILLY_NOBOARD:
                 break;
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index ac9b4cad320e..4b47fd9fdd89 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -230,6 +230,8 @@ static void __init mx31lite_init(void)
 {
         int ret;
 
+        imx31_soc_init();
+
         switch (mx31lite_baseboard) {
         case MX31LITE_NOBOARD:
                 break;
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index eaa51e49ca95..a52fd36e2b52 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -507,6 +507,8 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
  */
 static void __init mx31moboard_init(void)
 {
+        imx31_soc_init();
+
         mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
                 "moboard");
 
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 882880ac1bbc..48b3c6fd5cf0 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -179,6 +179,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+        imx35_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
         imx35_add_fec(NULL);
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 2774541511e7..c85876fed663 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -233,6 +233,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 
 static void __init mxt_td60_board_init(void)
 {
+        imx27_soc_init();
+
         mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
                         "MXT_TD60");
 
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index bbddc5a11c43..71083aa16038 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -357,6 +357,8 @@ static void __init pca100_init(void)
 {
         int ret;
 
+        imx27_soc_init();
+
         /* SSI unit */
         mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
                                   MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 89c213b81295..f45b7cd72c8a 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -576,6 +576,8 @@ static void __init pcm037_init(void)
 {
         int ret;
 
+        imx31_soc_init();
+
         mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 
         mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 853bb871c7ed..2d6a64bbac44 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -295,6 +295,8 @@ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
 
 static void __init pcm038_init(void)
 {
+        imx27_soc_init();
+
         mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
                         "PCM038");
 
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 026441628dfa..163cc318cafb 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -356,6 +356,8 @@ static struct esdhc_platform_data sd1_pdata = {
  */
 static void __init pcm043_init(void)
 {
+        imx35_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 
         mxc_audmux_v2_configure_port(3,
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index c16328715939..3626f486498a 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -244,6 +244,8 @@ static void __init qong_init_fpga(void)
  */
 static void __init qong_init(void)
 {
+        imx31_soc_init();
+
         mxc_init_imx_uart();
         qong_init_nor_mtd();
         qong_init_fpga();
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index dcaee043628e..82805260e19c 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -129,6 +129,8 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init scb9328_init(void)
 {
+        imx1_soc_init();
+
         imx1_add_imx_uart0(&uart_pdata);
 
         printk(KERN_INFO"Scb9328: Adding devices\n");
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index d74e3473d236..7d8e012a6335 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -267,6 +267,8 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init vpr200_board_init(void)
 {
+        imx35_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
 
         imx35_add_fec(NULL);
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 2e482ba5a0e7..2bded591d5c2 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -23,7 +23,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 #include <mach/iomux-v1.h>
 
@@ -44,15 +43,19 @@ void __init imx1_init_early(void)
                         MX1_NUM_GPIO_PORT);
 }
 
-static struct mxc_gpio_port imx1_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
-};
-
 void __init mx1_init_irq(void)
 {
         mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx1_gpio_ports,  ARRAY_SIZE(imx1_gpio_ports));
+}
+
+void __init imx1_soc_init(void)
+{
+        mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
+                                                MX1_GPIO_INT_PORTA, 0);
+        mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256,
+                                                MX1_GPIO_INT_PORTB, 0);
+        mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256,
+                                                MX1_GPIO_INT_PORTC, 0);
+        mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
+                                                MX1_GPIO_INT_PORTD, 0);
 }
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 7a0c500ac2c8..6d7d518686a5 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -24,7 +24,6 @@
 #include <mach/common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 #include <mach/iomux-v1.h>
 
@@ -70,17 +69,17 @@ void __init imx21_init_early(void)
                         MX21_NUM_GPIO_PORT);
 }
 
-static struct mxc_gpio_port imx21_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
-        DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
-        DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
-        DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
-        DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
-        DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
-};
-
 void __init mx21_init_irq(void)
 {
         mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
+}
+
+void __init imx21_soc_init(void)
+{
+        mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 02f7b5c7fa8e..9a1591c2508d 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -27,7 +27,6 @@
 #include <mach/hardware.h>
 #include <mach/mx25.h>
 #include <mach/iomux-v3.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 
 /*
@@ -57,16 +56,16 @@ void __init imx25_init_early(void)
         mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
 }
 
-static struct mxc_gpio_port imx25_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
-};
-
 void __init mx25_init_irq(void)
 {
         mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports));
 }
 
+void __init imx25_soc_init(void)
+{
+        /* i.mx25 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
+        mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
+}
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index a6761a39f08c..133b30003ddb 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -24,7 +24,6 @@
 #include <mach/common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 #include <mach/iomux-v1.h>
 
@@ -70,17 +69,18 @@ void __init imx27_init_early(void)
                         MX27_NUM_GPIO_PORT);
 }
 
-static struct mxc_gpio_port imx27_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
-        DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
-        DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
-        DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
-        DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
-        DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
-};
-
 void __init mx27_init_irq(void)
 {
         mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
+}
+
+void __init imx27_soc_init(void)
+{
+        /* i.mx27 has the i.mx21 type gpio */
+        mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+        mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
 }
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
index 86b9b45864d2..6d103c01b8b9 100644
--- a/arch/arm/mach-imx/mm-imx31.c
+++ b/arch/arm/mach-imx/mm-imx31.c
@@ -26,7 +26,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-v3.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 
 static struct map_desc mx31_io_desc[] __initdata = {
@@ -53,14 +52,14 @@ void __init imx31_init_early(void)
         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 }
 
-static struct mxc_gpio_port imx31_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
-};
-
 void __init mx31_init_irq(void)
 {
         mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
+}
+
+void __init imx31_soc_init(void)
+{
+        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
 }
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
index c880e6d1ae55..bb068bc8dab7 100644
--- a/arch/arm/mach-imx/mm-imx35.c
+++ b/arch/arm/mach-imx/mm-imx35.c
@@ -27,7 +27,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-v3.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 
 static struct map_desc mx35_io_desc[] __initdata = {
@@ -50,14 +49,15 @@ void __init imx35_init_early(void)
         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 }
 
-static struct mxc_gpio_port imx35_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
-};
-
 void __init mx35_init_irq(void)
 {
         mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
+}
+
+void __init imx35_soc_init(void)
+{
+        /* i.mx35 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
+        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
+        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
 }
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 5c147fb66a01..a5b989728b9e 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -17,6 +17,7 @@
  *
  */
 
+#include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #ifdef CONFIG_MTD_PHYSMAP
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 74ed81a3cb1a..07772575d7ab 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -419,14 +419,20 @@ static void notrace ixp4xx_update_sched_clock(void)
 /*
  * clocksource
  */
+
+static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
+{
+        return *IXP4XX_OSTS;
+}
+
 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 EXPORT_SYMBOL(ixp4xx_timer_freq);
 static void __init ixp4xx_clocksource_init(void)
 {
         init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
 
-        clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32,
-                        clocksource_mmio_readl_up);
+        clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
+                        ixp4xx_clocksource_read);
 }
 
 /*
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 7bb78fd5a2a6..c79162a50f28 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -177,9 +177,16 @@ static struct i2c_board_info brownstone_twsi1_info[] = {
 };
 
 static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
-        .max_speed      = 25000000,
+        .clk_delay_cycles = 0x1f,
 };
 
+static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
+        .clk_delay_cycles = 0x1f,
+        .flags = PXA_FLAG_CARD_PERMANENT
+                | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
+};
+
+
 static void __init brownstone_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
@@ -189,6 +196,7 @@ static void __init brownstone_init(void)
         mmp2_add_uart(3);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
         mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
+        mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
 
         /* enable 5v regulator */
         platform_device_register(&brownstone_v_5vp_device);
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index 2cbf6df09b82..de7b88826ad7 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_MACH_MMP2_H
 #define __ASM_MACH_MMP2_H
 
-#include <plat/sdhci.h>
+#include <linux/platform_data/pxa_sdhci.h>
 
 struct sys_timer;
 
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 24172a0aad59..5d6421d63254 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -154,7 +154,7 @@ static struct i2c_board_info jasper_twsi1_info[] = {
 };
 
 static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
-        .max_speed      = 25000000,
+        .clk_delay_cycles = 0x1f,
 };
 
 static void __init jasper_init(void)
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 8e6c3ac7f7c1..079c18861d5c 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -168,10 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
         INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
 };
 
 static int __init mmp2_init(void)
@@ -222,8 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
 MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
 MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
 MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
-MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
-MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
-MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
-MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);
+MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
+MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
+MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
+MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
 
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 72b4e7631583..ab9f999106c7 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -79,7 +79,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 
-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(lcd, LCD, 0x7f, 312000000);
 
 /* device and clock bindings */
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 8f92ccd26edf..1464607aa60d 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
 
-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(u2o, USB, 0x1b, 480000000);
 
 /* device and clock bindings */
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 1516896e8d17..888e92502e15 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -148,22 +148,6 @@ config MACH_MSM8960_RUMI3
 
 endmenu
 
-config MSM_IOMMU
-        bool "MSM IOMMU Support"
-        depends on ARCH_MSM8X60 || ARCH_MSM8960
-        select IOMMU_API
-        default n
-        help
-          Support for the IOMMUs found on certain Qualcomm SOCs.
-          These IOMMUs allow virtualization of the address space used by most
-          cores within the multimedia subsystem.
-
-          If unsure, say N here.
-
-config IOMMU_PGTABLES_L2
-        def_bool y
-        depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n
-
 config MSM_DEBUG_UART
         int
         default 1 if MSM_DEBUG_UART1
@@ -205,9 +189,6 @@ config MSM_GPIOMUX
 config MSM_V2_TLMM
         bool
 
-config IOMMU_API
-        bool
-
 config MSM_SCM
         bool
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 9519fd28a025..b70658c5ae00 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -3,7 +3,7 @@ obj-y += clock.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
-obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o
+obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
 
 obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
deleted file mode 100644
index 1a584e077c61..000000000000
--- a/arch/arm/mach-msm/iommu.c
+++ /dev/null
@@ -1,731 +0,0 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/iommu.h>
-#include <linux/clk.h>
-
-#include <asm/cacheflush.h>
-#include <asm/sizes.h>
-
-#include <mach/iommu_hw-8xxx.h>
-#include <mach/iommu.h>
-
-#define MRC(reg, processor, op1, crn, crm, op2)                         \
-__asm__ __volatile__ (                                                  \
-"   mrc   "   #processor "," #op1 ", %0,"  #crn "," #crm "," #op2 "\n"  \
-: "=r" (reg))
-
-#define RCP15_PRRR(reg)         MRC(reg, p15, 0, c10, c2, 0)
-#define RCP15_NMRR(reg)         MRC(reg, p15, 0, c10, c2, 1)
-
-static int msm_iommu_tex_class[4];
-
-DEFINE_SPINLOCK(msm_iommu_lock);
-
-struct msm_priv {
-        unsigned long *pgtable;
-        struct list_head list_attached;
-};
-
-static int __enable_clocks(struct msm_iommu_drvdata *drvdata)
-{
-        int ret;
-
-        ret = clk_enable(drvdata->pclk);
-        if (ret)
-                goto fail;
-
-        if (drvdata->clk) {
-                ret = clk_enable(drvdata->clk);
-                if (ret)
-                        clk_disable(drvdata->pclk);
-        }
-fail:
-        return ret;
-}
-
-static void __disable_clocks(struct msm_iommu_drvdata *drvdata)
-{
-        if (drvdata->clk)
-                clk_disable(drvdata->clk);
-        clk_disable(drvdata->pclk);
-}
-
-static int __flush_iotlb(struct iommu_domain *domain)
-{
-        struct msm_priv *priv = domain->priv;
-        struct msm_iommu_drvdata *iommu_drvdata;
-        struct msm_iommu_ctx_drvdata *ctx_drvdata;
-        int ret = 0;
-#ifndef CONFIG_IOMMU_PGTABLES_L2
-        unsigned long *fl_table = priv->pgtable;
-        int i;
-
-        if (!list_empty(&priv->list_attached)) {
-                dmac_flush_range(fl_table, fl_table + SZ_16K);
-
-                for (i = 0; i < NUM_FL_PTE; i++)
-                        if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
-                                void *sl_table = __va(fl_table[i] &
-                                                                FL_BASE_MASK);
-                                dmac_flush_range(sl_table, sl_table + SZ_4K);
-                        }
-        }
-#endif
-
-        list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
-                if (!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent)
-                        BUG();
-
-                iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
-                BUG_ON(!iommu_drvdata);
-
-                ret = __enable_clocks(iommu_drvdata);
-                if (ret)
-                        goto fail;
-
-                SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
-                __disable_clocks(iommu_drvdata);
-        }
-fail:
-        return ret;
-}
-
-static void __reset_context(void __iomem *base, int ctx)
-{
-        SET_BPRCOSH(base, ctx, 0);
-        SET_BPRCISH(base, ctx, 0);
-        SET_BPRCNSH(base, ctx, 0);
-        SET_BPSHCFG(base, ctx, 0);
-        SET_BPMTCFG(base, ctx, 0);
-        SET_ACTLR(base, ctx, 0);
-        SET_SCTLR(base, ctx, 0);
-        SET_FSRRESTORE(base, ctx, 0);
-        SET_TTBR0(base, ctx, 0);
-        SET_TTBR1(base, ctx, 0);
-        SET_TTBCR(base, ctx, 0);
-        SET_BFBCR(base, ctx, 0);
-        SET_PAR(base, ctx, 0);
-        SET_FAR(base, ctx, 0);
-        SET_CTX_TLBIALL(base, ctx, 0);
-        SET_TLBFLPTER(base, ctx, 0);
-        SET_TLBSLPTER(base, ctx, 0);
-        SET_TLBLKCR(base, ctx, 0);
-        SET_PRRR(base, ctx, 0);
-        SET_NMRR(base, ctx, 0);
-}
-
-static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
-{
-        unsigned int prrr, nmrr;
-        __reset_context(base, ctx);
-
-        /* Set up HTW mode */
-        /* TLB miss configuration: perform HTW on miss */
-        SET_TLBMCFG(base, ctx, 0x3);
-
-        /* V2P configuration: HTW for access */
-        SET_V2PCFG(base, ctx, 0x3);
-
-        SET_TTBCR(base, ctx, 0);
-        SET_TTBR0_PA(base, ctx, (pgtable >> 14));
-
-        /* Invalidate the TLB for this context */
-        SET_CTX_TLBIALL(base, ctx, 0);
-
-        /* Set interrupt number to "secure" interrupt */
-        SET_IRPTNDX(base, ctx, 0);
-
-        /* Enable context fault interrupt */
-        SET_CFEIE(base, ctx, 1);
-
-        /* Stall access on a context fault and let the handler deal with it */
-        SET_CFCFG(base, ctx, 1);
-
-        /* Redirect all cacheable requests to L2 slave port. */
-        SET_RCISH(base, ctx, 1);
-        SET_RCOSH(base, ctx, 1);
-        SET_RCNSH(base, ctx, 1);
-
-        /* Turn on TEX Remap */
-        SET_TRE(base, ctx, 1);
-
-        /* Set TEX remap attributes */
-        RCP15_PRRR(prrr);
-        RCP15_NMRR(nmrr);
-        SET_PRRR(base, ctx, prrr);
-        SET_NMRR(base, ctx, nmrr);
-
-        /* Turn on BFB prefetch */
-        SET_BFBDFE(base, ctx, 1);
-
-#ifdef CONFIG_IOMMU_PGTABLES_L2
-        /* Configure page tables as inner-cacheable and shareable to reduce
-         * the TLB miss penalty.
-         */
-        SET_TTBR0_SH(base, ctx, 1);
-        SET_TTBR1_SH(base, ctx, 1);
-
-        SET_TTBR0_NOS(base, ctx, 1);
-        SET_TTBR1_NOS(base, ctx, 1);
-
-        SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
-        SET_TTBR0_IRGNL(base, ctx, 1);
-
-        SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
-        SET_TTBR1_IRGNL(base, ctx, 1);
-
-        SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
-        SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
-#endif
-
-        /* Enable the MMU */
-        SET_M(base, ctx, 1);
-}
-
-static int msm_iommu_domain_init(struct iommu_domain *domain)
-{
-        struct msm_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-
-        if (!priv)
-                goto fail_nomem;
-
-        INIT_LIST_HEAD(&priv->list_attached);
-        priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
-                                                          get_order(SZ_16K));
-
-        if (!priv->pgtable)
-                goto fail_nomem;
-
-        memset(priv->pgtable, 0, SZ_16K);
-        domain->priv = priv;
-        return 0;
-
-fail_nomem:
-        kfree(priv);
-        return -ENOMEM;
-}
-
-static void msm_iommu_domain_destroy(struct iommu_domain *domain)
-{
-        struct msm_priv *priv;
-        unsigned long flags;
-        unsigned long *fl_table;
-        int i;
-
-        spin_lock_irqsave(&msm_iommu_lock, flags);
-        priv = domain->priv;
-        domain->priv = NULL;
-
-        if (priv) {
-                fl_table = priv->pgtable;
-
-                for (i = 0; i < NUM_FL_PTE; i++)
-                        if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
-                                free_page((unsigned long) __va(((fl_table[i]) &
-                                                                FL_BASE_MASK)));
-
-                free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
-                priv->pgtable = NULL;
-        }
-
-        kfree(priv);
-        spin_unlock_irqrestore(&msm_iommu_lock, flags);
-}
-
-static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
-{
-        struct msm_priv *priv;
-        struct msm_iommu_ctx_dev *ctx_dev;
-        struct msm_iommu_drvdata *iommu_drvdata;
-        struct msm_iommu_ctx_drvdata *ctx_drvdata;
-        struct msm_iommu_ctx_drvdata *tmp_drvdata;
-        int ret = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&msm_iommu_lock, flags);
-
-        priv = domain->priv;
-
-        if (!priv || !dev) {
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        iommu_drvdata = dev_get_drvdata(dev->parent);
-        ctx_drvdata = dev_get_drvdata(dev);
-        ctx_dev = dev->platform_data;
-
-        if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        if (!list_empty(&ctx_drvdata->attached_elm)) {
-                ret = -EBUSY;
-                goto fail;
-        }
-
-        list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
-                if (tmp_drvdata == ctx_drvdata) {
-                        ret = -EBUSY;
-                        goto fail;
-                }
-
-        ret = __enable_clocks(iommu_drvdata);
-        if (ret)
-                goto fail;
-
-        __program_context(iommu_drvdata->base, ctx_dev->num,
-                          __pa(priv->pgtable));
-
-        __disable_clocks(iommu_drvdata);
-        list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
-        ret = __flush_iotlb(domain);
-
-fail:
-        spin_unlock_irqrestore(&msm_iommu_lock, flags);
-        return ret;
-}
-
-static void msm_iommu_detach_dev(struct iommu_domain *domain,
-                                 struct device *dev)
-{
-        struct msm_priv *priv;
-        struct msm_iommu_ctx_dev *ctx_dev;
-        struct msm_iommu_drvdata *iommu_drvdata;
-        struct msm_iommu_ctx_drvdata *ctx_drvdata;
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&msm_iommu_lock, flags);
-        priv = domain->priv;
-
-        if (!priv || !dev)
-                goto fail;
-
-        iommu_drvdata = dev_get_drvdata(dev->parent);
-        ctx_drvdata = dev_get_drvdata(dev);
-        ctx_dev = dev->platform_data;
-
-        if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
-                goto fail;
-
-        ret = __flush_iotlb(domain);
-        if (ret)
-                goto fail;
-
-        ret = __enable_clocks(iommu_drvdata);
-        if (ret)
-                goto fail;
-
-        __reset_context(iommu_drvdata->base, ctx_dev->num);
-        __disable_clocks(iommu_drvdata);
-        list_del_init(&ctx_drvdata->attached_elm);
-
-fail:
-        spin_unlock_irqrestore(&msm_iommu_lock, flags);
-}
-
-static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
-                         phys_addr_t pa, int order, int prot)
-{
-        struct msm_priv *priv;
-        unsigned long flags;
-        unsigned long *fl_table;
-        unsigned long *fl_pte;
-        unsigned long fl_offset;
-        unsigned long *sl_table;
-        unsigned long *sl_pte;
-        unsigned long sl_offset;
-        unsigned int pgprot;
-        size_t len = 0x1000UL << order;
-        int ret = 0, tex, sh;
-
-        spin_lock_irqsave(&msm_iommu_lock, flags);
-
-        sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0;
-        tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK];
-
-        if (tex < 0 || tex > NUM_TEX_CLASS - 1) {
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        priv = domain->priv;
-        if (!priv) {
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        fl_table = priv->pgtable;
-
-        if (len != SZ_16M && len != SZ_1M &&
-            len != SZ_64K && len != SZ_4K) {
-                pr_debug("Bad size: %d\n", len);
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        if (!fl_table) {
-                pr_debug("Null page table\n");
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        if (len == SZ_16M || len == SZ_1M) {
-                pgprot = sh ? FL_SHARED : 0;
-                pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0;
-                pgprot |= tex & 0x02 ? FL_CACHEABLE : 0;
-                pgprot |= tex & 0x04 ? FL_TEX0 : 0;
-        } else  {
-                pgprot = sh ? SL_SHARED : 0;
-                pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0;
-                pgprot |= tex & 0x02 ? SL_CACHEABLE : 0;
-                pgprot |= tex & 0x04 ? SL_TEX0 : 0;
-        }
-
-        fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
-        fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
-
-        if (len == SZ_16M) {
-                int i = 0;
-                for (i = 0; i < 16; i++)
-                        *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
-                                  FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
-                                  FL_SHARED | FL_NG | pgprot;
-        }
-
-        if (len == SZ_1M)
-                *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG |
-                                            FL_TYPE_SECT | FL_SHARED | pgprot;
-
-        /* Need a 2nd level table */
-        if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
-                unsigned long *sl;
-                sl = (unsigned long *) __get_free_pages(GFP_ATOMIC,
-                                                        get_order(SZ_4K));
-
-                if (!sl) {
-                        pr_debug("Could not allocate second level table\n");
-                        ret = -ENOMEM;
-                        goto fail;
-                }
-
-                memset(sl, 0, SZ_4K);
-                *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
-        }
-
-        sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
-        sl_offset = SL_OFFSET(va);
-        sl_pte = sl_table + sl_offset;
-
-
-        if (len == SZ_4K)
-                *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG |
-                                          SL_SHARED | SL_TYPE_SMALL | pgprot;
-
-        if (len == SZ_64K) {
-                int i;
-
-                for (i = 0; i < 16; i++)
-                        *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
-                            SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
-        }
-
-        ret = __flush_iotlb(domain);
-fail:
-        spin_unlock_irqrestore(&msm_iommu_lock, flags);
-        return ret;
-}
-
-static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
-                            int order)
-{
-        struct msm_priv *priv;
-        unsigned long flags;
-        unsigned long *fl_table;
-        unsigned long *fl_pte;
-        unsigned long fl_offset;
-        unsigned long *sl_table;
-        unsigned long *sl_pte;
-        unsigned long sl_offset;
-        size_t len = 0x1000UL << order;
-        int i, ret = 0;
-
-        spin_lock_irqsave(&msm_iommu_lock, flags);
-
-        priv = domain->priv;
-
-        if (!priv) {
-                ret = -ENODEV;
-                goto fail;
-        }
-
-        fl_table = priv->pgtable;
-
-        if (len != SZ_16M && len != SZ_1M &&
-            len != SZ_64K && len != SZ_4K) {
-                pr_debug("Bad length: %d\n", len);
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        if (!fl_table) {
-                pr_debug("Null page table\n");
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
-        fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
-
-        if (*fl_pte == 0) {
-                pr_debug("First level PTE is 0\n");
-                ret = -ENODEV;
-                goto fail;
-        }
-
-        /* Unmap supersection */
-        if (len == SZ_16M)
-                for (i = 0; i < 16; i++)
-                        *(fl_pte+i) = 0;
-
-        if (len == SZ_1M)
-                *fl_pte = 0;
-
-        sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
-        sl_offset = SL_OFFSET(va);
-        sl_pte = sl_table + sl_offset;
-
-        if (len == SZ_64K) {
-                for (i = 0; i < 16; i++)
-                        *(sl_pte+i) = 0;
-        }
-
-        if (len == SZ_4K)
-                *sl_pte = 0;
-
-        if (len == SZ_4K || len == SZ_64K) {
-                int used = 0;
-
-                for (i = 0; i < NUM_SL_PTE; i++)
-                        if (sl_table[i])
-                                used = 1;
-                if (!used) {
-                        free_page((unsigned long)sl_table);
-                        *fl_pte = 0;
-                }
-        }
-
-        ret = __flush_iotlb(domain);
-fail:
-        spin_unlock_irqrestore(&msm_iommu_lock, flags);
-        return ret;
-}
-
-static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
-                                          unsigned long va)
-{
-        struct msm_priv *priv;
-        struct msm_iommu_drvdata *iommu_drvdata;
-        struct msm_iommu_ctx_drvdata *ctx_drvdata;
-        unsigned int par;
-        unsigned long flags;
-        void __iomem *base;
-        phys_addr_t ret = 0;
-        int ctx;
-
-        spin_lock_irqsave(&msm_iommu_lock, flags);
-
-        priv = domain->priv;
-        if (list_empty(&priv->list_attached))
-                goto fail;
-
-        ctx_drvdata = list_entry(priv->list_attached.next,
-                                 struct msm_iommu_ctx_drvdata, attached_elm);
-        iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
-
-        base = iommu_drvdata->base;
-        ctx = ctx_drvdata->num;
-
-        ret = __enable_clocks(iommu_drvdata);
-        if (ret)
-                goto fail;
-
-        /* Invalidate context TLB */
-        SET_CTX_TLBIALL(base, ctx, 0);
-        SET_V2PPR(base, ctx, va & V2Pxx_VA);
-
-        par = GET_PAR(base, ctx);
-
-        /* We are dealing with a supersection */
-        if (GET_NOFAULT_SS(base, ctx))
-                ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
-        else    /* Upper 20 bits from PAR, lower 12 from VA */
-                ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
-
-        if (GET_FAULT(base, ctx))
-                ret = 0;
-
-        __disable_clocks(iommu_drvdata);
-fail:
-        spin_unlock_irqrestore(&msm_iommu_lock, flags);
-        return ret;
-}
-
-static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
-                                    unsigned long cap)
-{
-        return 0;
-}
-
-static void print_ctx_regs(void __iomem *base, int ctx)
-{
-        unsigned int fsr = GET_FSR(base, ctx);
-        pr_err("FAR    = %08x    PAR    = %08x\n",
-               GET_FAR(base, ctx), GET_PAR(base, ctx));
-        pr_err("FSR    = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
-                        (fsr & 0x02) ? "TF " : "",
-                        (fsr & 0x04) ? "AFF " : "",
-                        (fsr & 0x08) ? "APF " : "",
-                        (fsr & 0x10) ? "TLBMF " : "",
-                        (fsr & 0x20) ? "HTWDEEF " : "",
-                        (fsr & 0x40) ? "HTWSEEF " : "",
-                        (fsr & 0x80) ? "MHF " : "",
-                        (fsr & 0x10000) ? "SL " : "",
-                        (fsr & 0x40000000) ? "SS " : "",
-                        (fsr & 0x80000000) ? "MULTI " : "");
-
-        pr_err("FSYNR0 = %08x    FSYNR1 = %08x\n",
-               GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
-        pr_err("TTBR0  = %08x    TTBR1  = %08x\n",
-               GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
-        pr_err("SCTLR  = %08x    ACTLR  = %08x\n",
-               GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
-        pr_err("PRRR   = %08x    NMRR   = %08x\n",
-               GET_PRRR(base, ctx), GET_NMRR(base, ctx));
-}
-
-irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
-{
-        struct msm_iommu_drvdata *drvdata = dev_id;
-        void __iomem *base;
-        unsigned int fsr;
-        int i, ret;
-
-        spin_lock(&msm_iommu_lock);
-
-        if (!drvdata) {
-                pr_err("Invalid device ID in context interrupt handler\n");
-                goto fail;
-        }
-
-        base = drvdata->base;
-
-        pr_err("Unexpected IOMMU page fault!\n");
-        pr_err("base = %08x\n", (unsigned int) base);
-
-        ret = __enable_clocks(drvdata);
-        if (ret)
-                goto fail;
-
-        for (i = 0; i < drvdata->ncb; i++) {
-                fsr = GET_FSR(base, i);
-                if (fsr) {
-                        pr_err("Fault occurred in context %d.\n", i);
-                        pr_err("Interesting registers:\n");
-                        print_ctx_regs(base, i);
-                        SET_FSR(base, i, 0x4000000F);
-                }
-        }
-        __disable_clocks(drvdata);
-fail:
-        spin_unlock(&msm_iommu_lock);
-        return 0;
-}
-
-static struct iommu_ops msm_iommu_ops = {
-        .domain_init = msm_iommu_domain_init,
-        .domain_destroy = msm_iommu_domain_destroy,
-        .attach_dev = msm_iommu_attach_dev,
-        .detach_dev = msm_iommu_detach_dev,
-        .map = msm_iommu_map,
-        .unmap = msm_iommu_unmap,
-        .iova_to_phys = msm_iommu_iova_to_phys,
-        .domain_has_cap = msm_iommu_domain_has_cap
-};
-
-static int __init get_tex_class(int icp, int ocp, int mt, int nos)
-{
-        int i = 0;
-        unsigned int prrr = 0;
-        unsigned int nmrr = 0;
-        int c_icp, c_ocp, c_mt, c_nos;
-
-        RCP15_PRRR(prrr);
-        RCP15_NMRR(nmrr);
-
-        for (i = 0; i < NUM_TEX_CLASS; i++) {
-                c_nos = PRRR_NOS(prrr, i);
-                c_mt = PRRR_MT(prrr, i);
-                c_icp = NMRR_ICP(nmrr, i);
-                c_ocp = NMRR_OCP(nmrr, i);
-
-                if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos)
-                        return i;
-        }
-
-        return -ENODEV;
-}
-
-static void __init setup_iommu_tex_classes(void)
-{
-        msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] =
-                        get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1);
-
-        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] =
-                        get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1);
-
-        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] =
-                        get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1);
-
-        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] =
-                        get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1);
-}
-
-static int __init msm_iommu_init(void)
-{
-        setup_iommu_tex_classes();
-        register_iommu(&msm_iommu_ops);
-        return 0;
-}
-
-subsys_initcall(msm_iommu_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
deleted file mode 100644
index 8e8fb079852d..000000000000
--- a/arch/arm/mach-msm/iommu_dev.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/iommu.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#include <mach/iommu_hw-8xxx.h>
-#include <mach/iommu.h>
-#include <mach/clk.h>
-
-struct iommu_ctx_iter_data {
-        /* input */
-        const char *name;
-
-        /* output */
-        struct device *dev;
-};
-
-static struct platform_device *msm_iommu_root_dev;
-
-static int each_iommu_ctx(struct device *dev, void *data)
-{
-        struct iommu_ctx_iter_data *res = data;
-        struct msm_iommu_ctx_dev *c = dev->platform_data;
-
-        if (!res || !c || !c->name || !res->name)
-                return -EINVAL;
-
-        if (!strcmp(res->name, c->name)) {
-                res->dev = dev;
-                return 1;
-        }
-        return 0;
-}
-
-static int each_iommu(struct device *dev, void *data)
-{
-        return device_for_each_child(dev, data, each_iommu_ctx);
-}
-
-struct device *msm_iommu_get_ctx(const char *ctx_name)
-{
-        struct iommu_ctx_iter_data r;
-        int found;
-
-        if (!msm_iommu_root_dev) {
-                pr_err("No root IOMMU device.\n");
-                goto fail;
-        }
-
-        r.name = ctx_name;
-        found = device_for_each_child(&msm_iommu_root_dev->dev, &r, each_iommu);
-
-        if (!found) {
-                pr_err("Could not find context <%s>\n", ctx_name);
-                goto fail;
-        }
-
-        return r.dev;
-fail:
-        return NULL;
-}
-EXPORT_SYMBOL(msm_iommu_get_ctx);
-
-static void msm_iommu_reset(void __iomem *base, int ncb)
-{
-        int ctx;
-
-        SET_RPUE(base, 0);
-        SET_RPUEIE(base, 0);
-        SET_ESRRESTORE(base, 0);
-        SET_TBE(base, 0);
-        SET_CR(base, 0);
-        SET_SPDMBE(base, 0);
-        SET_TESTBUSCR(base, 0);
-        SET_TLBRSW(base, 0);
-        SET_GLOBAL_TLBIALL(base, 0);
-        SET_RPU_ACR(base, 0);
-        SET_TLBLKCRWE(base, 1);
-
-        for (ctx = 0; ctx < ncb; ctx++) {
-                SET_BPRCOSH(base, ctx, 0);
-                SET_BPRCISH(base, ctx, 0);
-                SET_BPRCNSH(base, ctx, 0);
-                SET_BPSHCFG(base, ctx, 0);
-                SET_BPMTCFG(base, ctx, 0);
-                SET_ACTLR(base, ctx, 0);
-                SET_SCTLR(base, ctx, 0);
-                SET_FSRRESTORE(base, ctx, 0);
-                SET_TTBR0(base, ctx, 0);
-                SET_TTBR1(base, ctx, 0);
-                SET_TTBCR(base, ctx, 0);
-                SET_BFBCR(base, ctx, 0);
-                SET_PAR(base, ctx, 0);
-                SET_FAR(base, ctx, 0);
-                SET_CTX_TLBIALL(base, ctx, 0);
-                SET_TLBFLPTER(base, ctx, 0);
-                SET_TLBSLPTER(base, ctx, 0);
-                SET_TLBLKCR(base, ctx, 0);
-                SET_PRRR(base, ctx, 0);
-                SET_NMRR(base, ctx, 0);
-                SET_CONTEXTIDR(base, ctx, 0);
-        }
-}
-
-static int msm_iommu_probe(struct platform_device *pdev)
-{
-        struct resource *r, *r2;
-        struct clk *iommu_clk;
-        struct clk *iommu_pclk;
-        struct msm_iommu_drvdata *drvdata;
-        struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
-        void __iomem *regs_base;
-        resource_size_t len;
-        int ret, irq, par;
-
-        if (pdev->id == -1) {
-                msm_iommu_root_dev = pdev;
-                return 0;
-        }
-
-        drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
-
-        if (!drvdata) {
-                ret = -ENOMEM;
-                goto fail;
-        }
-
-        if (!iommu_dev) {
-                ret = -ENODEV;
-                goto fail;
-        }
-
-        iommu_pclk = clk_get(NULL, "smmu_pclk");
-        if (IS_ERR(iommu_pclk)) {
-                ret = -ENODEV;
-                goto fail;
-        }
-
-        ret = clk_enable(iommu_pclk);
-        if (ret)
-                goto fail_enable;
-
-        iommu_clk = clk_get(&pdev->dev, "iommu_clk");
-
-        if (!IS_ERR(iommu_clk)) {
-                if (clk_get_rate(iommu_clk) == 0)
-                        clk_set_min_rate(iommu_clk, 1);
-
-                ret = clk_enable(iommu_clk);
-                if (ret) {
-                        clk_put(iommu_clk);
-                        goto fail_pclk;
-                }
-        } else
-                iommu_clk = NULL;
-
-        r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "physbase");
-
-        if (!r) {
-                ret = -ENODEV;
-                goto fail_clk;
-        }
-
-        len = resource_size(r);
-
-        r2 = request_mem_region(r->start, len, r->name);
-        if (!r2) {
-                pr_err("Could not request memory region: start=%p, len=%d\n",
-                                                        (void *) r->start, len);
-                ret = -EBUSY;
-                goto fail_clk;
-        }
-
-        regs_base = ioremap(r2->start, len);
-
-        if (!regs_base) {
-                pr_err("Could not ioremap: start=%p, len=%d\n",
-                         (void *) r2->start, len);
-                ret = -EBUSY;
-                goto fail_mem;
-        }
-
-        irq = platform_get_irq_byname(pdev, "secure_irq");
-        if (irq < 0) {
-                ret = -ENODEV;
-                goto fail_io;
-        }
-
-        msm_iommu_reset(regs_base, iommu_dev->ncb);
-
-        SET_M(regs_base, 0, 1);
-        SET_PAR(regs_base, 0, 0);
-        SET_V2PCFG(regs_base, 0, 1);
-        SET_V2PPR(regs_base, 0, 0);
-        par = GET_PAR(regs_base, 0);
-        SET_V2PCFG(regs_base, 0, 0);
-        SET_M(regs_base, 0, 0);
-
-        if (!par) {
-                pr_err("%s: Invalid PAR value detected\n", iommu_dev->name);
-                ret = -ENODEV;
-                goto fail_io;
-        }
-
-        ret = request_irq(irq, msm_iommu_fault_handler, 0,
-                        "msm_iommu_secure_irpt_handler", drvdata);
-        if (ret) {
-                pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
-                goto fail_io;
-        }
-
-
-        drvdata->pclk = iommu_pclk;
-        drvdata->clk = iommu_clk;
-        drvdata->base = regs_base;
-        drvdata->irq = irq;
-        drvdata->ncb = iommu_dev->ncb;
-
-        pr_info("device %s mapped at %p, irq %d with %d ctx banks\n",
-                iommu_dev->name, regs_base, irq, iommu_dev->ncb);
-
-        platform_set_drvdata(pdev, drvdata);
-
-        if (iommu_clk)
-                clk_disable(iommu_clk);
-
-        clk_disable(iommu_pclk);
-
-        return 0;
-fail_io:
-        iounmap(regs_base);
-fail_mem:
-        release_mem_region(r->start, len);
-fail_clk:
-        if (iommu_clk) {
-                clk_disable(iommu_clk);
-                clk_put(iommu_clk);
-        }
-fail_pclk:
-        clk_disable(iommu_pclk);
-fail_enable:
-        clk_put(iommu_pclk);
-fail:
-        kfree(drvdata);
-        return ret;
-}
-
-static int msm_iommu_remove(struct platform_device *pdev)
-{
-        struct msm_iommu_drvdata *drv = NULL;
-
-        drv = platform_get_drvdata(pdev);
-        if (drv) {
-                if (drv->clk)
-                        clk_put(drv->clk);
-                clk_put(drv->pclk);
-                memset(drv, 0, sizeof(*drv));
-                kfree(drv);
-                platform_set_drvdata(pdev, NULL);
-        }
-        return 0;
-}
-
-static int msm_iommu_ctx_probe(struct platform_device *pdev)
-{
-        struct msm_iommu_ctx_dev *c = pdev->dev.platform_data;
-        struct msm_iommu_drvdata *drvdata;
-        struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL;
-        int i, ret;
-        if (!c || !pdev->dev.parent) {
-                ret = -EINVAL;
-                goto fail;
-        }
-
-        drvdata = dev_get_drvdata(pdev->dev.parent);
-
-        if (!drvdata) {
-                ret = -ENODEV;
-                goto fail;
-        }
-
-        ctx_drvdata = kzalloc(sizeof(*ctx_drvdata), GFP_KERNEL);
-        if (!ctx_drvdata) {
-                ret = -ENOMEM;
-                goto fail;
-        }
-        ctx_drvdata->num = c->num;
-        ctx_drvdata->pdev = pdev;
-
-        INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
-        platform_set_drvdata(pdev, ctx_drvdata);
-
-        ret = clk_enable(drvdata->pclk);
-        if (ret)
-                goto fail;
-
-        if (drvdata->clk) {
-                ret = clk_enable(drvdata->clk);
-                if (ret) {
-                        clk_disable(drvdata->pclk);
-                        goto fail;
-                }
-        }
-
-        /* Program the M2V tables for this context */
-        for (i = 0; i < MAX_NUM_MIDS; i++) {
-                int mid = c->mids[i];
-                if (mid == -1)
-                        break;
-
-                SET_M2VCBR_N(drvdata->base, mid, 0);
-                SET_CBACR_N(drvdata->base, c->num, 0);
-
-                /* Set VMID = 0 */
-                SET_VMID(drvdata->base, mid, 0);
-
-                /* Set the context number for that MID to this context */
-                SET_CBNDX(drvdata->base, mid, c->num);
-
-                /* Set MID associated with this context bank to 0*/
-                SET_CBVMID(drvdata->base, c->num, 0);
-
-                /* Set the ASID for TLB tagging for this context */
-                SET_CONTEXTIDR_ASID(drvdata->base, c->num, c->num);
-
-                /* Set security bit override to be Non-secure */
-                SET_NSCFG(drvdata->base, mid, 3);
-        }
-
-        if (drvdata->clk)
-                clk_disable(drvdata->clk);
-        clk_disable(drvdata->pclk);
-
-        dev_info(&pdev->dev, "context %s using bank %d\n", c->name, c->num);
-        return 0;
-fail:
-        kfree(ctx_drvdata);
-        return ret;
-}
-
-static int msm_iommu_ctx_remove(struct platform_device *pdev)
-{
-        struct msm_iommu_ctx_drvdata *drv = NULL;
-        drv = platform_get_drvdata(pdev);
-        if (drv) {
-                memset(drv, 0, sizeof(struct msm_iommu_ctx_drvdata));
-                kfree(drv);
-                platform_set_drvdata(pdev, NULL);
-        }
-        return 0;
-}
-
-static struct platform_driver msm_iommu_driver = {
-        .driver = {
-                .name   = "msm_iommu",
-        },
-        .probe          = msm_iommu_probe,
-        .remove         = msm_iommu_remove,
-};
-
-static struct platform_driver msm_iommu_ctx_driver = {
-        .driver = {
-                .name   = "msm_iommu_ctx",
-        },
-        .probe          = msm_iommu_ctx_probe,
-        .remove         = msm_iommu_ctx_remove,
-};
-
-static int __init msm_iommu_driver_init(void)
-{
-        int ret;
-        ret = platform_driver_register(&msm_iommu_driver);
-        if (ret != 0) {
-                pr_err("Failed to register IOMMU driver\n");
-                goto error;
-        }
-
-        ret = platform_driver_register(&msm_iommu_ctx_driver);
-        if (ret != 0) {
-                pr_err("Failed to register IOMMU context driver\n");
-                goto error;
-        }
-
-error:
-        return ret;
-}
-
-static void __exit msm_iommu_driver_exit(void)
-{
-        platform_driver_unregister(&msm_iommu_ctx_driver);
-        platform_driver_unregister(&msm_iommu_driver);
-}
-
-subsys_initcall(msm_iommu_driver_init);
-module_exit(msm_iommu_driver_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 4efa02ee1639..add0d42de7af 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -245,6 +245,8 @@ __setup("otg_mode=", eukrea_cpuimx51_otg_mode);
  */
 static void __init eukrea_cpuimx51_init(void)
 {
+        imx51_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 5ef25a596143..ff096d587299 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -264,6 +264,8 @@ static struct platform_device *platform_devices[] __initdata = {
 
 static void __init eukrea_cpuimx51sd_init(void)
 {
+        imx51_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index 11210e1ae42a..7de25c6712eb 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -192,6 +192,8 @@ static const struct imxi2c_platform_data i2c_data __initconst = {
  */
 static void __init mx50_rdp_board_init(void)
 {
+        imx50_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
                                         ARRAY_SIZE(mx50_rdp_pads));
 
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 63dfbeafbc1e..3112d15feebc 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -135,6 +135,8 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = {
  */
 static void __init mx51_3ds_init(void)
 {
+        imx51_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
                                         ARRAY_SIZE(mx51_3ds_pads));
 
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index c7b3fabf50f9..6021dd00ec75 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -340,6 +340,8 @@ static void __init mx51_babbage_init(void)
         iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
                 MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
 
+        imx51_soc_init();
+
 #if defined(CONFIG_CPU_FREQ_IMX)
         get_cpu_op = mx51_get_cpu_op;
 #endif
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index 6e362315291b..3be603b9075a 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -236,6 +236,8 @@ late_initcall(mx51_efikamx_power_init);
 
 static void __init mx51_efikamx_init(void)
 {
+        imx51_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
                                         ARRAY_SIZE(mx51efikamx_pads));
         efika_board_common_init();
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index 474fc6e4c6df..4b2e522de0f8 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -248,6 +248,8 @@ static void __init mx51_efikasb_board_id(void)
 
 static void __init efikasb_board_init(void)
 {
+        imx51_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
                                         ARRAY_SIZE(mx51efikasb_pads));
         efika_board_common_init();
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index f87d571882c6..0d9218a6e2d2 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -117,6 +117,8 @@ static const struct spi_imx_master mx53_evk_spi_data __initconst = {
 
 static void __init mx53_evk_board_init(void)
 {
+        imx53_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
                                         ARRAY_SIZE(mx53_evk_pads));
         mx53_evk_init_uart();
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 1b947e8c9c0c..359c3e248add 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -227,6 +227,8 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
 
 static void __init mx53_loco_board_init(void)
 {
+        imx53_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
                                         ARRAY_SIZE(mx53_loco_pads));
         imx53_add_imx_uart(0, NULL);
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 817c08938f55..bc02894eafef 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -113,6 +113,8 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
 
 static void __init mx53_smd_board_init(void)
 {
+        imx53_soc_init();
+
         mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
                                         ARRAY_SIZE(mx53_smd_pads));
         mx53_smd_init_uart();
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 6b89c1bf4eb2..cd79e3435e28 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1442,7 +1442,8 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
         _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
         _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
-        _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
+        /* i.mx51 has the i.mx35 type cspi */
+        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
@@ -1471,9 +1472,11 @@ static struct clk_lookup mx53_lookups[] = {
         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
-        _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
-        _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
-        _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
+        /* i.mx53 has the i.mx51 type ecspi */
+        _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+        _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+        /* i.mx53 has the i.mx25 type cspi */
+        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
 };
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 153ada53e575..371ca8c8414c 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -12,7 +12,6 @@
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <linux/gpio.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/irqs.h>
@@ -119,66 +118,3 @@ struct platform_device mxc_usbh2_device = {
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
 };
-
-static struct mxc_gpio_port mxc_gpio_ports[] = {
-        {
-                .chip.label = "gpio-0",
-                .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
-                .irq = MX51_MXC_INT_GPIO1_LOW,
-                .irq_high = MX51_MXC_INT_GPIO1_HIGH,
-                .virtual_irq_start = MXC_GPIO_IRQ_START
-        },
-        {
-                .chip.label = "gpio-1",
-                .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
-                .irq = MX51_MXC_INT_GPIO2_LOW,
-                .irq_high = MX51_MXC_INT_GPIO2_HIGH,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
-        },
-        {
-                .chip.label = "gpio-2",
-                .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
-                .irq = MX51_MXC_INT_GPIO3_LOW,
-                .irq_high = MX51_MXC_INT_GPIO3_HIGH,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
-        },
-        {
-                .chip.label = "gpio-3",
-                .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
-                .irq = MX51_MXC_INT_GPIO4_LOW,
-                .irq_high = MX51_MXC_INT_GPIO4_HIGH,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
-        },
-        {
-                .chip.label = "gpio-4",
-                .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR),
-                .irq = MX53_INT_GPIO5_LOW,
-                .irq_high = MX53_INT_GPIO5_HIGH,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4
-        },
-        {
-                .chip.label = "gpio-5",
-                .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR),
-                .irq = MX53_INT_GPIO6_LOW,
-                .irq_high = MX53_INT_GPIO6_HIGH,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5
-        },
-        {
-                .chip.label = "gpio-6",
-                .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR),
-                .irq = MX53_INT_GPIO7_LOW,
-                .irq_high = MX53_INT_GPIO7_HIGH,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6
-        },
-};
-
-int __init imx51_register_gpios(void)
-{
-        return mxc_gpio_init(mxc_gpio_ports, 4);
-}
-
-int __init imx53_register_gpios(void)
-{
-        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
-}
-
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
index b9c363b514a9..77e374c726fa 100644
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -26,7 +26,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-v3.h>
-#include <mach/gpio.h>
 #include <mach/irqs.h>
 
 /*
@@ -56,17 +55,18 @@ void __init imx50_init_early(void)
         mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
 }
 
-static struct mxc_gpio_port imx50_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-};
-
 void __init mx50_init_irq(void)
 {
         tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-        mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
+}
+
+void __init imx50_soc_init(void)
+{
+        /* i.mx50 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
+        mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
 }
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index ff557301b42b..665843d6c2b2 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -69,8 +69,6 @@ void __init imx53_init_early(void)
         mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 }
 
-int imx51_register_gpios(void);
-
 void __init mx51_init_irq(void)
 {
         unsigned long tzic_addr;
@@ -86,11 +84,8 @@ void __init mx51_init_irq(void)
                 panic("unable to map TZIC interrupt controller\n");
 
         tzic_init_irq(tzic_virt);
-        imx51_register_gpios();
 }
 
-int imx53_register_gpios(void);
-
 void __init mx53_init_irq(void)
 {
         unsigned long tzic_addr;
@@ -103,5 +98,25 @@ void __init mx53_init_irq(void)
                 panic("unable to map TZIC interrupt controller\n");
 
         tzic_init_irq(tzic_virt);
-        imx53_register_gpios();
+}
+
+void __init imx51_soc_init(void)
+{
+        /* i.mx51 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
+}
+
+void __init imx53_soc_init(void)
+{
+        /* i.mx53 has the i.mx31 type gpio */
+        mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
+        mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
+        mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
 }
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 58e892376bf2..6c38262a3aaa 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,5 +1,5 @@
 # Common support
-obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
+obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o
 
 obj-$(CONFIG_MXS_OCOTP) += ocotp.o
 obj-$(CONFIG_PM) += pm.o
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index cfdb6b284702..fe3e847930c9 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -88,3 +88,14 @@ int __init mxs_add_amba_device(const struct amba_device *dev)
 
         return amba_device_register(adev, &iomem_resource);
 }
+
+struct device mxs_apbh_bus = {
+        .init_name      = "mxs_apbh",
+        .parent         = &platform_bus,
+};
+
+static int __init mxs_device_init(void)
+{
+        return device_register(&mxs_apbh_bus);
+}
+core_initcall(mxs_device_init);
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index 324f2824d38d..351915c683ff 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
+obj-y += platform-gpio-mxs.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
index 796606cce0ce..27608f5d2ac8 100644
--- a/arch/arm/mach-mxs/devices/platform-auart.c
+++ b/arch/arm/mach-mxs/devices/platform-auart.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <asm/sizes.h>
 #include <mach/mx23.h>
 #include <mach/mx28.h>
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
index 295c4424d5d9..6a0202b1016c 100644
--- a/arch/arm/mach-mxs/devices/platform-dma.c
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -6,6 +6,7 @@
  * Free Software Foundation.
  */
 #include <linux/compiler.h>
+#include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/init.h>
 
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
index 9859cf283335..ae96a4fd8f14 100644
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <asm/sizes.h>
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
new file mode 100644
index 000000000000..ed0885e414e0
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init mxs_add_gpio(
+        int id, resource_size_t iobase, int irq)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return platform_device_register_resndata(&mxs_apbh_bus,
+                        "gpio-mxs", id, res, ARRAY_SIZE(res), NULL, 0);
+}
+
+static int __init mxs_add_mxs_gpio(void)
+{
+        if (cpu_is_mx23()) {
+                mxs_add_gpio(0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
+                mxs_add_gpio(1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
+                mxs_add_gpio(2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
+        }
+
+        if (cpu_is_mx28()) {
+                mxs_add_gpio(0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
+                mxs_add_gpio(1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
+                mxs_add_gpio(2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
+                mxs_add_gpio(3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
+                mxs_add_gpio(4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
+        }
+
+        return 0;
+}
+postcore_initcall(mxs_add_mxs_gpio);
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
deleted file mode 100644
index 2c950fef71a8..000000000000
--- a/arch/arm/mach-mxs/gpio.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * Based on code from Freescale,
- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <asm-generic/bug.h>
-
-#include "gpio.h"
-
-static struct mxs_gpio_port *mxs_gpio_ports;
-static int gpio_table_size;
-
-#define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
-#define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
-#define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
-#define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
-#define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
-#define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
-#define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
-#define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
-
-#define GPIO_INT_FALL_EDGE      0x0
-#define GPIO_INT_LOW_LEV        0x1
-#define GPIO_INT_RISE_EDGE      0x2
-#define GPIO_INT_HIGH_LEV       0x3
-#define GPIO_INT_LEV_MASK       (1 << 0)
-#define GPIO_INT_POL_MASK       (1 << 1)
-
-/* Note: This driver assumes 32 GPIOs are handled in one register */
-
-static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
-{
-        __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
-}
-
-static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
-                                int enable)
-{
-        if (enable) {
-                __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
-                __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
-        } else {
-                __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
-        }
-}
-
-static void mxs_gpio_ack_irq(struct irq_data *d)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
-}
-
-static void mxs_gpio_mask_irq(struct irq_data *d)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
-}
-
-static void mxs_gpio_unmask_irq(struct irq_data *d)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
-}
-
-static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
-
-static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        u32 pin_mask = 1 << (gpio & 31);
-        struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
-        void __iomem *pin_addr;
-        int edge;
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                edge = GPIO_INT_RISE_EDGE;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                edge = GPIO_INT_FALL_EDGE;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                edge = GPIO_INT_LOW_LEV;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                edge = GPIO_INT_HIGH_LEV;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        /* set level or edge */
-        pin_addr = port->base + PINCTRL_IRQLEV(port->id);
-        if (edge & GPIO_INT_LEV_MASK)
-                __mxs_setl(pin_mask, pin_addr);
-        else
-                __mxs_clrl(pin_mask, pin_addr);
-
-        /* set polarity */
-        pin_addr = port->base + PINCTRL_IRQPOL(port->id);
-        if (edge & GPIO_INT_POL_MASK)
-                __mxs_setl(pin_mask, pin_addr);
-        else
-                __mxs_clrl(pin_mask, pin_addr);
-
-        clear_gpio_irqstatus(port, gpio & 0x1f);
-
-        return 0;
-}
-
-/* MXS has one interrupt *per* gpio port */
-static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
-{
-        u32 irq_stat;
-        struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
-        u32 gpio_irq_no_base = port->virtual_irq_start;
-
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-
-        irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
-                        __raw_readl(port->base + PINCTRL_IRQEN(port->id));
-
-        while (irq_stat != 0) {
-                int irqoffset = fls(irq_stat) - 1;
-                generic_handle_irq(gpio_irq_no_base + irqoffset);
-                irq_stat &= ~(1 << irqoffset);
-        }
-}
-
-/*
- * Set interrupt number "irq" in the GPIO as a wake-up source.
- * While system is running, all registered GPIO interrupts need to have
- * wake-up enabled. When system is suspended, only selected GPIO interrupts
- * need to have wake-up enabled.
- * @param  irq          interrupt source number
- * @param  enable       enable as wake-up if equal to non-zero
- * @return       This function returns 0 on success.
- */
-static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        u32 gpio_idx = gpio & 0x1f;
-        struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
-
-        if (enable) {
-                if (port->irq_high && (gpio_idx >= 16))
-                        enable_irq_wake(port->irq_high);
-                else
-                        enable_irq_wake(port->irq);
-        } else {
-                if (port->irq_high && (gpio_idx >= 16))
-                        disable_irq_wake(port->irq_high);
-                else
-                        disable_irq_wake(port->irq);
-        }
-
-        return 0;
-}
-
-static struct irq_chip gpio_irq_chip = {
-        .name = "mxs gpio",
-        .irq_ack = mxs_gpio_ack_irq,
-        .irq_mask = mxs_gpio_mask_irq,
-        .irq_unmask = mxs_gpio_unmask_irq,
-        .irq_set_type = mxs_gpio_set_irq_type,
-        .irq_set_wake = mxs_gpio_set_wake_irq,
-};
-
-static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
-                                int dir)
-{
-        struct mxs_gpio_port *port =
-                container_of(chip, struct mxs_gpio_port, chip);
-        void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
-
-        if (dir)
-                __mxs_setl(1 << offset, pin_addr);
-        else
-                __mxs_clrl(1 << offset, pin_addr);
-}
-
-static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct mxs_gpio_port *port =
-                container_of(chip, struct mxs_gpio_port, chip);
-
-        return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
-}
-
-static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct mxs_gpio_port *port =
-                container_of(chip, struct mxs_gpio_port, chip);
-        void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
-
-        if (value)
-                __mxs_setl(1 << offset, pin_addr);
-        else
-                __mxs_clrl(1 << offset, pin_addr);
-}
-
-static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct mxs_gpio_port *port =
-                container_of(chip, struct mxs_gpio_port, chip);
-
-        return port->virtual_irq_start + offset;
-}
-
-static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        mxs_set_gpio_direction(chip, offset, 0);
-        return 0;
-}
-
-static int mxs_gpio_direction_output(struct gpio_chip *chip,
-                                     unsigned offset, int value)
-{
-        mxs_gpio_set(chip, offset, value);
-        mxs_set_gpio_direction(chip, offset, 1);
-        return 0;
-}
-
-int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
-{
-        int i, j;
-
-        /* save for local usage */
-        mxs_gpio_ports = port;
-        gpio_table_size = cnt;
-
-        pr_info("MXS GPIO hardware\n");
-
-        for (i = 0; i < cnt; i++) {
-                /* disable the interrupt and clear the status */
-                __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
-                __raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
-
-                /* clear address has to be used to clear IRQSTAT bits */
-                __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
-
-                for (j = port[i].virtual_irq_start;
-                        j < port[i].virtual_irq_start + 32; j++) {
-                        irq_set_chip_and_handler(j, &gpio_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(j, IRQF_VALID);
-                }
-
-                /* setup one handler for each entry */
-                irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
-                irq_set_handler_data(port[i].irq, &port[i]);
-
-                /* register gpio chip */
-                port[i].chip.direction_input = mxs_gpio_direction_input;
-                port[i].chip.direction_output = mxs_gpio_direction_output;
-                port[i].chip.get = mxs_gpio_get;
-                port[i].chip.set = mxs_gpio_set;
-                port[i].chip.to_irq = mxs_gpio_to_irq;
-                port[i].chip.base = i * 32;
-                port[i].chip.ngpio = 32;
-
-                /* its a serious configuration bug when it fails */
-                BUG_ON(gpiochip_add(&port[i].chip) < 0);
-        }
-
-        return 0;
-}
-
-#define MX23_GPIO_BASE  MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
-#define MX28_GPIO_BASE  MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
-
-#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id)                          \
-        {                                                               \
-                .chip.label = "gpio-" #_id,                             \
-                .id = _id,                                              \
-                .irq = _irq,                                            \
-                .base = _base,                                          \
-                .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32,   \
-        }
-
-#ifdef CONFIG_SOC_IMX23
-static struct mxs_gpio_port mx23_gpio_ports[] = {
-        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
-        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
-        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
-};
-
-int __init mx23_register_gpios(void)
-{
-        return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
-}
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-static struct mxs_gpio_port mx28_gpio_ports[] = {
-        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
-        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
-        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
-        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
-        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
-};
-
-int __init mx28_register_gpios(void)
-{
-        return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
-}
-#endif
diff --git a/arch/arm/mach-mxs/gpio.h b/arch/arm/mach-mxs/gpio.h
deleted file mode 100644
index 005bb06630b1..000000000000
--- a/arch/arm/mach-mxs/gpio.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MXS_GPIO_H__
-#define __MXS_GPIO_H__
-
-struct mxs_gpio_port {
-        void __iomem *base;
-        int id;
-        int irq;
-        int irq_high;
-        int virtual_irq_start;
-        struct gpio_chip chip;
-};
-
-int mxs_gpio_init(struct mxs_gpio_port*, int);
-
-#endif /* __MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 7a37469ed5bf..812d7a813a78 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -11,6 +11,8 @@
 #include <linux/init.h>
 #include <linux/amba/bus.h>
 
+extern struct device mxs_apbh_bus;
+
 struct platform_device *mxs_add_platform_device_dmamask(
                 const char *name, int id,
                 const struct resource *res, unsigned int num_resources,
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index eacdc6b0e70a..56767a5cce0e 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -26,7 +26,6 @@
 #include <mach/iomux-mx28.h>
 
 #include "devices-mx28.h"
-#include "gpio.h"
 
 #define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
 #define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c
index 5148cd64a6b7..1b2345ac1a87 100644
--- a/arch/arm/mach-mxs/mm-mx23.c
+++ b/arch/arm/mach-mxs/mm-mx23.c
@@ -41,5 +41,4 @@ void __init mx23_map_io(void)
 void __init mx23_init_irq(void)
 {
         icoll_init_irq();
-        mx23_register_gpios();
 }
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c
index 7e4cea32ebc6..b6e18ddb92c0 100644
--- a/arch/arm/mach-mxs/mm-mx28.c
+++ b/arch/arm/mach-mxs/mm-mx28.c
@@ -41,5 +41,4 @@ void __init mx28_map_io(void)
 void __init mx28_init_irq(void)
 {
         icoll_init_irq();
-        mx28_register_gpios();
 }
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index de88c9297b68..f49ce85d2448 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -215,7 +215,7 @@ static struct omap_kp_platform_data ams_delta_kp_data __initdata = {
         .delay          = 9,
 };
 
-static struct platform_device ams_delta_kp_device __initdata = {
+static struct platform_device ams_delta_kp_device = {
         .name           = "omap-keypad",
         .id             = -1,
         .dev            = {
@@ -225,12 +225,12 @@ static struct platform_device ams_delta_kp_device __initdata = {
         .resource       = ams_delta_kp_resources,
 };
 
-static struct platform_device ams_delta_lcd_device __initdata = {
+static struct platform_device ams_delta_lcd_device = {
         .name   = "lcd_ams_delta",
         .id     = -1,
 };
 
-static struct platform_device ams_delta_led_device __initdata = {
+static struct platform_device ams_delta_led_device = {
         .name   = "ams-delta-led",
         .id     = -1
 };
@@ -267,7 +267,7 @@ static struct soc_camera_link ams_delta_iclink = {
         .power          = ams_delta_camera_power,
 };
 
-static struct platform_device ams_delta_camera_device __initdata = {
+static struct platform_device ams_delta_camera_device = {
         .name   = "soc-camera-pdrv",
         .id     = 0,
         .dev    = {
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 04c4b04cf54e..399da4ce017b 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -34,14 +34,25 @@ static struct __initdata resource omap15xx_mpu_gpio_resources[] = {
         },
 };
 
+static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
+        .revision       = USHRT_MAX,
+        .direction      = OMAP_MPUIO_IO_CNTL,
+        .datain         = OMAP_MPUIO_INPUT_LATCH,
+        .dataout        = OMAP_MPUIO_OUTPUT,
+        .irqstatus      = OMAP_MPUIO_GPIO_INT,
+        .irqenable      = OMAP_MPUIO_GPIO_MASKIT,
+        .irqenable_inv  = true,
+};
+
 static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
         .bank_type              = METHOD_MPUIO,
         .bank_width             = 16,
         .bank_stride            = 1,
+        .regs                   = &omap15xx_mpuio_regs,
 };
 
-static struct __initdata platform_device omap15xx_mpu_gpio = {
+static struct platform_device omap15xx_mpu_gpio = {
         .name           = "omap_gpio",
         .id             = 0,
         .dev            = {
@@ -64,13 +75,24 @@ static struct __initdata resource omap15xx_gpio_resources[] = {
         },
 };
 
+static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
+        .revision       = USHRT_MAX,
+        .direction      = OMAP1510_GPIO_DIR_CONTROL,
+        .datain         = OMAP1510_GPIO_DATA_INPUT,
+        .dataout        = OMAP1510_GPIO_DATA_OUTPUT,
+        .irqstatus      = OMAP1510_GPIO_INT_STATUS,
+        .irqenable      = OMAP1510_GPIO_INT_MASK,
+        .irqenable_inv  = true,
+};
+
 static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
         .bank_type              = METHOD_GPIO_1510,
         .bank_width             = 16,
+        .regs                   = &omap15xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap15xx_gpio = {
+static struct platform_device omap15xx_gpio = {
         .name           = "omap_gpio",
         .id             = 1,
         .dev            = {
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 5dd0d4c82b24..0f399bd0e70e 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -37,14 +37,25 @@ static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
         },
 };
 
+static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
+        .revision       = USHRT_MAX,
+        .direction      = OMAP_MPUIO_IO_CNTL,
+        .datain         = OMAP_MPUIO_INPUT_LATCH,
+        .dataout        = OMAP_MPUIO_OUTPUT,
+        .irqstatus      = OMAP_MPUIO_GPIO_INT,
+        .irqenable      = OMAP_MPUIO_GPIO_MASKIT,
+        .irqenable_inv  = true,
+};
+
 static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
         .bank_type              = METHOD_MPUIO,
         .bank_width             = 16,
         .bank_stride            = 1,
+        .regs                   = &omap16xx_mpuio_regs,
 };
 
-static struct __initdata platform_device omap16xx_mpu_gpio = {
+static struct platform_device omap16xx_mpu_gpio = {
         .name           = "omap_gpio",
         .id             = 0,
         .dev            = {
@@ -67,13 +78,27 @@ static struct __initdata resource omap16xx_gpio1_resources[] = {
         },
 };
 
+static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
+        .revision       = OMAP1610_GPIO_REVISION,
+        .direction      = OMAP1610_GPIO_DIRECTION,
+        .set_dataout    = OMAP1610_GPIO_SET_DATAOUT,
+        .clr_dataout    = OMAP1610_GPIO_CLEAR_DATAOUT,
+        .datain         = OMAP1610_GPIO_DATAIN,
+        .dataout        = OMAP1610_GPIO_DATAOUT,
+        .irqstatus      = OMAP1610_GPIO_IRQSTATUS1,
+        .irqenable      = OMAP1610_GPIO_IRQENABLE1,
+        .set_irqenable  = OMAP1610_GPIO_SET_IRQENABLE1,
+        .clr_irqenable  = OMAP1610_GPIO_CLEAR_IRQENABLE1,
+};
+
 static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
         .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
+        .regs                   = &omap16xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap16xx_gpio1 = {
+static struct platform_device omap16xx_gpio1 = {
         .name           = "omap_gpio",
         .id             = 1,
         .dev            = {
@@ -100,9 +125,10 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 16,
         .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
+        .regs                   = &omap16xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap16xx_gpio2 = {
+static struct platform_device omap16xx_gpio2 = {
         .name           = "omap_gpio",
         .id             = 2,
         .dev            = {
@@ -129,9 +155,10 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 32,
         .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
+        .regs                   = &omap16xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap16xx_gpio3 = {
+static struct platform_device omap16xx_gpio3 = {
         .name           = "omap_gpio",
         .id             = 3,
         .dev            = {
@@ -158,9 +185,10 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 48,
         .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
+        .regs                   = &omap16xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap16xx_gpio4 = {
+static struct platform_device omap16xx_gpio4 = {
         .name           = "omap_gpio",
         .id             = 4,
         .dev            = {
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 1204c8b871af..5ab63eab0ff5 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -39,14 +39,25 @@ static struct __initdata resource omap7xx_mpu_gpio_resources[] = {
         },
 };
 
+static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
+        .revision       = USHRT_MAX,
+        .direction      = OMAP_MPUIO_IO_CNTL / 2,
+        .datain         = OMAP_MPUIO_INPUT_LATCH / 2,
+        .dataout        = OMAP_MPUIO_OUTPUT / 2,
+        .irqstatus      = OMAP_MPUIO_GPIO_INT / 2,
+        .irqenable      = OMAP_MPUIO_GPIO_MASKIT / 2,
+        .irqenable_inv  = true,
+};
+
 static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
         .bank_type              = METHOD_MPUIO,
         .bank_width             = 32,
         .bank_stride            = 2,
+        .regs                   = &omap7xx_mpuio_regs,
 };
 
-static struct __initdata platform_device omap7xx_mpu_gpio = {
+static struct platform_device omap7xx_mpu_gpio = {
         .name           = "omap_gpio",
         .id             = 0,
         .dev            = {
@@ -69,13 +80,24 @@ static struct __initdata resource omap7xx_gpio1_resources[] = {
         },
 };
 
+static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
+        .revision       = USHRT_MAX,
+        .direction      = OMAP7XX_GPIO_DIR_CONTROL,
+        .datain         = OMAP7XX_GPIO_DATA_INPUT,
+        .dataout        = OMAP7XX_GPIO_DATA_OUTPUT,
+        .irqstatus      = OMAP7XX_GPIO_INT_STATUS,
+        .irqenable      = OMAP7XX_GPIO_INT_MASK,
+        .irqenable_inv  = true,
+};
+
 static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
         .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
+        .regs                   = &omap7xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap7xx_gpio1 = {
+static struct platform_device omap7xx_gpio1 = {
         .name           = "omap_gpio",
         .id             = 1,
         .dev            = {
@@ -102,9 +124,10 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 32,
         .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
+        .regs                   = &omap7xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap7xx_gpio2 = {
+static struct platform_device omap7xx_gpio2 = {
         .name           = "omap_gpio",
         .id             = 2,
         .dev            = {
@@ -131,9 +154,10 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 64,
         .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
+        .regs                   = &omap7xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap7xx_gpio3 = {
+static struct platform_device omap7xx_gpio3 = {
         .name           = "omap_gpio",
         .id             = 3,
         .dev            = {
@@ -160,9 +184,10 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 96,
         .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
+        .regs                   = &omap7xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap7xx_gpio4 = {
+static struct platform_device omap7xx_gpio4 = {
         .name           = "omap_gpio",
         .id             = 4,
         .dev            = {
@@ -189,9 +214,10 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 128,
         .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
+        .regs                   = &omap7xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap7xx_gpio5 = {
+static struct platform_device omap7xx_gpio5 = {
         .name           = "omap_gpio",
         .id             = 5,
         .dev            = {
@@ -218,9 +244,10 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 160,
         .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
+        .regs                   = &omap7xx_gpio_regs,
 };
 
-static struct __initdata platform_device omap7xx_gpio6 = {
+static struct platform_device omap7xx_gpio6 = {
         .name           = "omap_gpio",
         .id             = 6,
         .dev            = {
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
index 334fb8871bc3..943072d5a1d5 100644
--- a/arch/arm/mach-omap1/pm_bus.c
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -32,7 +32,7 @@ static int omap1_pm_runtime_suspend(struct device *dev)
         if (ret)
                 return ret;
 
-        ret = pm_runtime_clk_suspend(dev);
+        ret = pm_clk_suspend(dev);
         if (ret) {
                 pm_generic_runtime_resume(dev);
                 return ret;
@@ -45,24 +45,24 @@ static int omap1_pm_runtime_resume(struct device *dev)
 {
         dev_dbg(dev, "%s\n", __func__);
 
-        pm_runtime_clk_resume(dev);
+        pm_clk_resume(dev);
         return pm_generic_runtime_resume(dev);
 }
 
-static struct dev_power_domain default_power_domain = {
+static struct dev_pm_domain default_pm_domain = {
         .ops = {
                 .runtime_suspend = omap1_pm_runtime_suspend,
                 .runtime_resume = omap1_pm_runtime_resume,
                 USE_PLATFORM_PM_SLEEP_OPS
         },
 };
-#define OMAP1_PWR_DOMAIN (&default_power_domain)
+#define OMAP1_PM_DOMAIN (&default_pm_domain)
 #else
-#define OMAP1_PWR_DOMAIN NULL
+#define OMAP1_PM_DOMAIN NULL
 #endif /* CONFIG_PM_RUNTIME */
 
 static struct pm_clk_notifier_block platform_bus_notifier = {
-        .pwr_domain = OMAP1_PWR_DOMAIN,
+        .pm_domain = OMAP1_PM_DOMAIN,
         .con_ids = { "ick", "fck", NULL, },
 };
 
@@ -71,7 +71,7 @@ static int __init omap1_pm_runtime_init(void)
         if (!cpu_class_is_omap1())
                 return -ENODEV;
 
-        pm_runtime_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
+        pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 990366726c58..88bd6f7705f0 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -558,7 +558,7 @@ static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module =
         .subdev_board_info = &rx51_si4713_board_info,
 };
 
-static struct platform_device rx51_si4713_dev __initdata_or_module = {
+static struct platform_device rx51_si4713_dev = {
         .name   = "radio-si4713",
         .id     = -1,
         .dev    = {
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9529842ae054..2765cdc3152d 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -61,13 +61,45 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
         pdata->dbck_flag = dev_attr->dbck_flag;
         pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
 
+        pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("gpio%d: Memory allocation failed\n", id);
+                return -ENOMEM;
+        }
+
         switch (oh->class->rev) {
         case 0:
         case 1:
                 pdata->bank_type = METHOD_GPIO_24XX;
+                pdata->regs->revision = OMAP24XX_GPIO_REVISION;
+                pdata->regs->direction = OMAP24XX_GPIO_OE;
+                pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
+                pdata->regs->dataout = OMAP24XX_GPIO_DATAOUT;
+                pdata->regs->set_dataout = OMAP24XX_GPIO_SETDATAOUT;
+                pdata->regs->clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT;
+                pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
+                pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
+                pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
+                pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
+                pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
+                pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
+                pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
                 break;
         case 2:
                 pdata->bank_type = METHOD_GPIO_44XX;
+                pdata->regs->revision = OMAP4_GPIO_REVISION;
+                pdata->regs->direction = OMAP4_GPIO_OE;
+                pdata->regs->datain = OMAP4_GPIO_DATAIN;
+                pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
+                pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
+                pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
+                pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
+                pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
+                pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+                pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+                pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
+                pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
+                pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
                 break;
         default:
                 WARN(1, "Invalid gpio bank_type\n");
@@ -87,6 +119,8 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 return PTR_ERR(od);
         }
 
+        omap_device_disable_idle_on_suspend(od);
+
         gpio_bank_count++;
         return 0;
 }
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 1ac361b7b8cb..466fc722fa0f 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -805,6 +805,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
              name, oh->name);
 
+        omap_device_disable_idle_on_suspend(od);
         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 
         uart->irq = oh->mpu_irqs[0].irq;
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 87ae3129f4f7..b27544bcafcb 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -347,9 +347,9 @@ static int pxa2xx_mfp_suspend(void)
                 if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
                     (GPDR(i) & GPIO_bit(i))) {
                         if (GPLR(i) & GPIO_bit(i))
-                                PGSR(i) |= GPIO_bit(i);
+                                PGSR(gpio_to_bank(i)) |= GPIO_bit(i);
                         else
-                                PGSR(i) &= ~GPIO_bit(i);
+                                PGSR(gpio_to_bank(i)) &= ~GPIO_bit(i);
                 }
         }
 
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index d130f77b6d11..2f37d43f51b6 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -573,10 +573,10 @@ static struct pxafb_mode_info sharp_lq043t3dx02_mode = {
         .xres           = 480,
         .yres           = 272,
         .bpp            = 16,
-        .hsync_len      = 4,
+        .hsync_len      = 41,
         .left_margin    = 2,
         .right_margin   = 1,
-        .vsync_len      = 1,
+        .vsync_len      = 10,
         .upper_margin   = 3,
         .lower_margin   = 1,
         .sync           = 0,
@@ -596,29 +596,31 @@ static void __init raumfeld_lcd_init(void)
 {
         int ret;
 
-        pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
-
-        /* Earlier devices had the backlight regulator controlled
-         * via PWM, later versions use another controller for that */
-        if ((system_rev & 0xff) < 2) {
-                mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
-                pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
-                platform_device_register(&raumfeld_pwm_backlight_device);
-        } else
-                platform_device_register(&raumfeld_lt3593_device);
-
         ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable");
         if (ret < 0)
                 pr_warning("Unable to request GPIO_TFT_VA_EN\n");
         else
                 gpio_direction_output(GPIO_TFT_VA_EN, 1);
 
+        msleep(100);
+
         ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable");
         if (ret < 0)
                 pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n");
         else
                 gpio_direction_output(GPIO_DISPLAY_ENABLE, 1);
 
+        /* Hardware revision 2 has the backlight regulator controlled
+         * by an LT3593, earlier and later devices use PWM for that. */
+        if ((system_rev & 0xff) == 2) {
+                platform_device_register(&raumfeld_lt3593_device);
+        } else {
+                mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
+                pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
+                platform_device_register(&raumfeld_pwm_backlight_device);
+        }
+
+        pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
         platform_device_register(&pxa3xx_device_gcu);
 }
 
@@ -657,10 +659,10 @@ static struct lis3lv02d_platform_data lis3_pdata = {
 
 #define SPI_AK4104      \
 {                       \
-        .modalias       = "ak4104",     \
-        .max_speed_hz   = 10000,        \
-        .bus_num        = 0,            \
-        .chip_select    = 0,            \
+        .modalias       = "ak4104-codec",       \
+        .max_speed_hz   = 10000,                \
+        .bus_num        = 0,                    \
+        .chip_select    = 0,                    \
         .controller_data = (void *) GPIO_SPDIF_CS,      \
 }
 
diff --git a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
deleted file mode 100644
index dcef2287cb38..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/spi-gpio.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - SPI Controller platform_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SPIGPIO_H
-#define __ASM_ARCH_SPIGPIO_H __FILE__
-
-struct s3c2410_spigpio_info {
-        unsigned long            pin_clk;
-        unsigned long            pin_mosi;
-        unsigned long            pin_miso;
-
-        int                      num_chipselect;
-        int                      bus_num;
-
-        void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
-};
-
-
-#endif /* __ASM_ARCH_SPIGPIO_H */
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index e8f49feef28c..f44f77531b1e 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -32,7 +32,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/spi_bitbang.h>
+#include <linux/spi/spi_gpio.h>
 #include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -53,8 +53,6 @@
 #include <mach/fb.h>
 #include <plat/nand.h>
 #include <plat/udc.h>
-#include <mach/spi.h>
-#include <mach/spi-gpio.h>
 #include <plat/iic.h>
 
 #include <plat/common-smdk.h>
@@ -216,32 +214,16 @@ static struct platform_device qt2410_led = {
 
 /* SPI */
 
-static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
-{
-        switch (cs) {
-        case BITBANG_CS_ACTIVE:
-                gpio_set_value(S3C2410_GPB(5), 0);
-                break;
-        case BITBANG_CS_INACTIVE:
-                gpio_set_value(S3C2410_GPB(5), 1);
-                break;
-        }
-}
-
-static struct s3c2410_spigpio_info spi_gpio_cfg = {
-        .pin_clk        = S3C2410_GPG(7),
-        .pin_mosi       = S3C2410_GPG(6),
-        .pin_miso       = S3C2410_GPG(5),
-        .chip_select    = &spi_gpio_cs,
+static struct spi_gpio_platform_data spi_gpio_cfg = {
+        .sck            = S3C2410_GPG(7),
+        .mosi           = S3C2410_GPG(6),
+        .miso           = S3C2410_GPG(5),
 };
 
-
 static struct platform_device qt2410_spi = {
-        .name             = "s3c24xx-spi-gpio",
-        .id               = 1,
-        .dev = {
-                .platform_data = &spi_gpio_cfg,
-        },
+        .name           = "spi-gpio",
+        .id             = 1,
+        .dev.platform_data = &spi_gpio_cfg,
 };
 
 /* Board devices */
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 85dcaeb9e62f..5eeb47580b0c 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -25,6 +25,7 @@
 #include <video/ili9320.h>
 
 #include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -38,7 +39,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <mach/spi-gpio.h>
 #include <mach/fb.h>
 
 #include <asm/mach-types.h>
@@ -389,45 +389,30 @@ static struct ili9320_platdata jive_lcm_config = {
 
 /* LCD SPI support */
 
-static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
-{
-        gpio_set_value(S3C2410_GPB(7), cs ? 0 : 1);
-}
-
-static struct s3c2410_spigpio_info jive_lcd_spi = {
-        .bus_num        = 1,
-        .pin_clk        = S3C2410_GPG(8),
-        .pin_mosi       = S3C2410_GPB(8),
-        .num_chipselect = 1,
-        .chip_select    = jive_lcd_spi_chipselect,
+static struct spi_gpio_platform_data jive_lcd_spi = {
+        .sck            = S3C2410_GPG(8),
+        .mosi           = S3C2410_GPB(8),
+        .miso           = SPI_GPIO_NO_MISO,
 };
 
 static struct platform_device jive_device_lcdspi = {
-        .name           = "spi_s3c24xx_gpio",
+        .name           = "spi-gpio",
         .id             = 1,
-        .num_resources  = 0,
         .dev.platform_data = &jive_lcd_spi,
 };
 
-/* WM8750 audio code SPI definition */
 
-static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
-{
-        gpio_set_value(S3C2410_GPH(10), cs ? 0 : 1);
-}
+/* WM8750 audio code SPI definition */
 
-static struct s3c2410_spigpio_info jive_wm8750_spi = {
-        .bus_num        = 2,
-        .pin_clk        = S3C2410_GPB(4),
-        .pin_mosi       = S3C2410_GPB(9),
-        .num_chipselect = 1,
-        .chip_select    = jive_wm8750_chipselect,
+static struct spi_gpio_platform_data jive_wm8750_spi = {
+        .sck            = S3C2410_GPB(4),
+        .mosi           = S3C2410_GPB(9),
+        .miso           = SPI_GPIO_NO_MISO,
 };
 
 static struct platform_device jive_device_wm8750 = {
-        .name           = "spi_s3c24xx_gpio",
+        .name           = "spi-gpio",
         .id             = 2,
-        .num_resources  = 0,
         .dev.platform_data = &jive_wm8750_spi,
 };
 
@@ -441,12 +426,14 @@ static struct spi_board_info __initdata jive_spi_devs[] = {
                 .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
                 .max_speed_hz   = 100000,
                 .platform_data  = &jive_lcm_config,
+                .controller_data = (void *)S3C2410_GPB(7),
         }, {
                 .modalias       = "WM8750",
                 .bus_num        = 2,
                 .chip_select    = 0,
                 .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
                 .max_speed_hz   = 100000,
+                .controller_data = (void *)S3C2410_GPH(10),
         },
 };
 
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 716662008ce2..c10ddf4ed7f1 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -74,7 +74,6 @@
 #include <mach/fb.h>
 
 #include <mach/spi.h>
-#include <mach/spi-gpio.h>
 #include <plat/usb-control.h>
 #include <mach/regs-mem.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index dd3120df09fe..fc2dc0b3d4fe 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -552,7 +552,7 @@ struct mini2440_features_t {
         struct platform_device *optional[8];
 };
 
-static void mini2440_parse_features(
+static void __init mini2440_parse_features(
                 struct mini2440_features_t * features,
                 const char * features_str )
 {
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
index 82db072cb836..5e6b42089eb4 100644
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
         .cfg_gpio = s3c64xx_spi_cfg_gpio,
         .fifo_lvl_mask = 0x7f,
         .rx_lvl_offset = 13,
+        .tx_st_done = 21,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
         .cfg_gpio = s3c64xx_spi_cfg_gpio,
         .fifo_lvl_mask = 0x7f,
         .rx_lvl_offset = 13,
+        .tx_st_done = 21,
 };
 
 struct platform_device s3c64xx_device_spi1 = {
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index b197171e7d03..204bfafe4bfc 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -113,7 +113,7 @@ found:
         return chan;
 }
 
-int s3c2410_dma_config(unsigned int channel, int xferunit)
+int s3c2410_dma_config(enum dma_ch channel, int xferunit)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
@@ -297,7 +297,7 @@ static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
         return 0;
 }
 
-int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
+int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
@@ -331,7 +331,7 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
  *
  */
 
-int s3c2410_dma_enqueue(unsigned int channel, void *id,
+int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
                         dma_addr_t data, int size)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
@@ -415,7 +415,7 @@ err_buff:
 EXPORT_SYMBOL(s3c2410_dma_enqueue);
 
 
-int s3c2410_dma_devconfig(unsigned int channel,
+int s3c2410_dma_devconfig(enum dma_ch channel,
                           enum s3c2410_dmasrc source,
                           unsigned long devaddr)
 {
@@ -463,7 +463,7 @@ int s3c2410_dma_devconfig(unsigned int channel,
 EXPORT_SYMBOL(s3c2410_dma_devconfig);
 
 
-int s3c2410_dma_getposition(unsigned int channel,
+int s3c2410_dma_getposition(enum dma_ch channel,
                             dma_addr_t *src, dma_addr_t *dst)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
@@ -487,7 +487,7 @@ EXPORT_SYMBOL(s3c2410_dma_getposition);
  * get control of an dma channel
 */
 
-int s3c2410_dma_request(unsigned int channel,
+int s3c2410_dma_request(enum dma_ch channel,
                         struct s3c2410_dma_client *client,
                         void *dev)
 {
@@ -533,7 +533,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
  * allowed to go through.
 */
 
-int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
+int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
         unsigned long flags;
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index e78ee18c76e3..ac825e826326 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
         .cfg_gpio       = s5p6440_spi_cfg_gpio,
         .fifo_lvl_mask  = 0x1ff,
         .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
 };
 
 static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
         .cfg_gpio       = s5p6450_spi_cfg_gpio,
         .fifo_lvl_mask  = 0x1ff,
         .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
         .cfg_gpio       = s5p6440_spi_cfg_gpio,
         .fifo_lvl_mask  = 0x7f,
         .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
 };
 
 static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
         .cfg_gpio       = s5p6450_spi_cfg_gpio,
         .fifo_lvl_mask  = 0x7f,
         .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
 };
 
 struct platform_device s5p64x0_device_spi1 = {
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
index 57b19794d9bb..e5d6c4dceb56 100644
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -15,6 +15,7 @@
 #include <mach/dma.h>
 #include <mach/map.h>
 #include <mach/spi-clocks.h>
+#include <mach/irqs.h>
 
 #include <plat/s3c64xx-spi.h>
 #include <plat/gpio-cfg.h>
@@ -90,6 +91,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
         .fifo_lvl_mask = 0x7f,
         .rx_lvl_offset = 13,
         .high_speed = 1,
+        .tx_st_done = 21,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -134,6 +136,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
         .fifo_lvl_mask = 0x7f,
         .rx_lvl_offset = 13,
         .high_speed = 1,
+        .tx_st_done = 21,
 };
 
 struct platform_device s5pc100_device_spi1 = {
@@ -176,6 +179,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
         .fifo_lvl_mask = 0x7f,
         .rx_lvl_offset = 13,
         .high_speed = 1,
+        .tx_st_done = 21,
 };
 
 struct platform_device s5pc100_device_spi2 = {
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
index e3249a47e3b1..eaf9a7bff7a0 100644
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ b/arch/arm/mach-s5pv210/dev-spi.c
@@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
         .fifo_lvl_mask = 0x1ff,
         .rx_lvl_offset = 15,
         .high_speed = 1,
+        .tx_st_done = 25,
 };
 
 static u64 spi_dmamask = DMA_BIT_MASK(32);
@@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
         .fifo_lvl_mask = 0x7f,
         .rx_lvl_offset = 15,
         .high_speed = 1,
+        .tx_st_done = 25,
 };
 
 struct platform_device s5pv210_device_spi1 = {
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 803bc6edfca4..b473b8efac68 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1408,9 +1408,14 @@ static void __init ap4evb_init(void)
 
         platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
 
+        sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device);
+        sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
+        sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+
         hdmi_init_pm_clock();
         fsi_init_pm_clock();
         sh7372_pm_init();
+        pm_clk_add(&fsi_device.dev, "spu2");
 }
 
 static void __init ap4evb_timer_init(void)
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 3802f2afabef..5b36b6c5b448 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1582,8 +1582,13 @@ static void __init mackerel_init(void)
 
         platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
 
+        sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
+        sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
+        sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+
         hdmi_init_pm_clock();
         sh7372_pm_init();
+        pm_clk_add(&fsi_device.dev, "spu2");
 }
 
 static void __init mackerel_timer_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index c0800d83971e..91f5779abdd3 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -662,6 +662,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
         CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
         CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
+        CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
 };
 
 void __init sh7372_clock_init(void)
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index df20d7670172..ce595cee86cd 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -12,6 +12,7 @@
 #define __ASM_SH7372_H__
 
 #include <linux/sh_clk.h>
+#include <linux/pm_domain.h>
 
 /*
  * Pin Function Controller:
@@ -470,4 +471,32 @@ extern struct clk sh7372_fsibck_clk;
 extern struct clk sh7372_fsidiva_clk;
 extern struct clk sh7372_fsidivb_clk;
 
+struct platform_device;
+
+struct sh7372_pm_domain {
+        struct generic_pm_domain genpd;
+        unsigned int bit_shift;
+};
+
+static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
+{
+        return container_of(d, struct sh7372_pm_domain, genpd);
+}
+
+#ifdef CONFIG_PM
+extern struct sh7372_pm_domain sh7372_a4lc;
+extern struct sh7372_pm_domain sh7372_a4mp;
+extern struct sh7372_pm_domain sh7372_d4;
+extern struct sh7372_pm_domain sh7372_a3rv;
+extern struct sh7372_pm_domain sh7372_a3ri;
+extern struct sh7372_pm_domain sh7372_a3sg;
+
+extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
+extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
+                                        struct platform_device *pdev);
+#else
+#define sh7372_init_pm_domain(pd) do { } while(0)
+#define sh7372_add_device_to_domain(pd, pdev) do { } while(0)
+#endif /* CONFIG_PM */
+
 #endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 8e4aadf14c9f..933fb411be0f 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -15,16 +15,176 @@
 #include <linux/list.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <mach/common.h>
+#include <mach/sh7372.h>
 
 #define SMFRAM 0xe6a70000
 #define SYSTBCR 0xe6150024
 #define SBAR 0xe6180020
 #define APARMBAREA 0xe6f10020
 
+#define SPDCR 0xe6180008
+#define SWUCR 0xe6180014
+#define PSTR 0xe6180080
+
+#define PSTR_RETRIES 100
+#define PSTR_DELAY_US 10
+
+#ifdef CONFIG_PM
+
+static int pd_power_down(struct generic_pm_domain *genpd)
+{
+        struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
+        unsigned int mask = 1 << sh7372_pd->bit_shift;
+
+        if (__raw_readl(PSTR) & mask) {
+                unsigned int retry_count;
+
+                __raw_writel(mask, SPDCR);
+
+                for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
+                        if (!(__raw_readl(SPDCR) & mask))
+                                break;
+                        cpu_relax();
+                }
+        }
+
+        pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
+                 mask, __raw_readl(PSTR));
+
+        return 0;
+}
+
+static int pd_power_up(struct generic_pm_domain *genpd)
+{
+        struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
+        unsigned int mask = 1 << sh7372_pd->bit_shift;
+        unsigned int retry_count;
+        int ret = 0;
+
+        if (__raw_readl(PSTR) & mask)
+                goto out;
+
+        __raw_writel(mask, SWUCR);
+
+        for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
+                if (!(__raw_readl(SWUCR) & mask))
+                        goto out;
+                if (retry_count > PSTR_RETRIES)
+                        udelay(PSTR_DELAY_US);
+                else
+                        cpu_relax();
+        }
+        if (__raw_readl(SWUCR) & mask)
+                ret = -EIO;
+
+ out:
+        pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
+                 mask, __raw_readl(PSTR));
+
+        return ret;
+}
+
+static int pd_power_up_a3rv(struct generic_pm_domain *genpd)
+{
+        int ret = pd_power_up(genpd);
+
+        /* force A4LC on after A3RV has been requested on */
+        pm_genpd_poweron(&sh7372_a4lc.genpd);
+
+        return ret;
+}
+
+static int pd_power_down_a3rv(struct generic_pm_domain *genpd)
+{
+        int ret = pd_power_down(genpd);
+
+        /* try to power down A4LC after A3RV is requested off */
+        genpd_queue_power_off_work(&sh7372_a4lc.genpd);
+
+        return ret;
+}
+
+static int pd_power_down_a4lc(struct generic_pm_domain *genpd)
+{
+        /* only power down A4LC if A3RV is off */
+        if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift)))
+                return pd_power_down(genpd);
+
+        return -EBUSY;
+}
+
+static bool pd_active_wakeup(struct device *dev)
+{
+        return true;
+}
+
+void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
+{
+        struct generic_pm_domain *genpd = &sh7372_pd->genpd;
+
+        pm_genpd_init(genpd, NULL, false);
+        genpd->stop_device = pm_clk_suspend;
+        genpd->start_device = pm_clk_resume;
+        genpd->active_wakeup = pd_active_wakeup;
+
+        if (sh7372_pd == &sh7372_a4lc) {
+                genpd->power_off = pd_power_down_a4lc;
+                genpd->power_on = pd_power_up;
+        } else if (sh7372_pd == &sh7372_a3rv) {
+                genpd->power_off = pd_power_down_a3rv;
+                genpd->power_on = pd_power_up_a3rv;
+        } else {
+                genpd->power_off = pd_power_down;
+                genpd->power_on = pd_power_up;
+        }
+        genpd->power_on(&sh7372_pd->genpd);
+}
+
+void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
+                                 struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+
+        if (!dev->power.subsys_data) {
+                pm_clk_init(dev);
+                pm_clk_add(dev, NULL);
+        }
+        pm_genpd_add_device(&sh7372_pd->genpd, dev);
+}
+
+struct sh7372_pm_domain sh7372_a4lc = {
+        .bit_shift = 1,
+};
+
+struct sh7372_pm_domain sh7372_a4mp = {
+        .bit_shift = 2,
+};
+
+struct sh7372_pm_domain sh7372_d4 = {
+        .bit_shift = 3,
+};
+
+struct sh7372_pm_domain sh7372_a3rv = {
+        .bit_shift = 6,
+};
+
+struct sh7372_pm_domain sh7372_a3ri = {
+        .bit_shift = 8,
+};
+
+struct sh7372_pm_domain sh7372_a3sg = {
+        .bit_shift = 13,
+};
+
+#endif /* CONFIG_PM */
+
 static void sh7372_enter_core_standby(void)
 {
         void __iomem *smfram = (void __iomem *)SMFRAM;
diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c
index 2d1b67a59e4a..6ec454e1e063 100644
--- a/arch/arm/mach-shmobile/pm_runtime.c
+++ b/arch/arm/mach-shmobile/pm_runtime.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
+#include <linux/pm_domain.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/sh_clk.h>
@@ -28,31 +29,38 @@ static int default_platform_runtime_idle(struct device *dev)
         return pm_runtime_suspend(dev);
 }
 
-static struct dev_power_domain default_power_domain = {
+static struct dev_pm_domain default_pm_domain = {
         .ops = {
-                .runtime_suspend = pm_runtime_clk_suspend,
-                .runtime_resume = pm_runtime_clk_resume,
+                .runtime_suspend = pm_clk_suspend,
+                .runtime_resume = pm_clk_resume,
                 .runtime_idle = default_platform_runtime_idle,
                 USE_PLATFORM_PM_SLEEP_OPS
         },
 };
 
-#define DEFAULT_PWR_DOMAIN_PTR  (&default_power_domain)
+#define DEFAULT_PM_DOMAIN_PTR   (&default_pm_domain)
 
 #else
 
-#define DEFAULT_PWR_DOMAIN_PTR  NULL
+#define DEFAULT_PM_DOMAIN_PTR   NULL
 
 #endif /* CONFIG_PM_RUNTIME */
 
 static struct pm_clk_notifier_block platform_bus_notifier = {
-        .pwr_domain = DEFAULT_PWR_DOMAIN_PTR,
+        .pm_domain = DEFAULT_PM_DOMAIN_PTR,
         .con_ids = { NULL, },
 };
 
 static int __init sh_pm_runtime_init(void)
 {
-        pm_runtime_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
+        pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
         return 0;
 }
 core_initcall(sh_pm_runtime_init);
+
+static int __init sh_pm_runtime_late_init(void)
+{
+        pm_genpd_poweroff_unused();
+        return 0;
+}
+late_initcall(sh_pm_runtime_late_init);
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index cd807eea69e2..79f0413d8725 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -841,11 +841,22 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
 
 void __init sh7372_add_standard_devices(void)
 {
+        sh7372_init_pm_domain(&sh7372_a4lc);
+        sh7372_init_pm_domain(&sh7372_a4mp);
+        sh7372_init_pm_domain(&sh7372_d4);
+        sh7372_init_pm_domain(&sh7372_a3rv);
+        sh7372_init_pm_domain(&sh7372_a3ri);
+        sh7372_init_pm_domain(&sh7372_a3sg);
+
         platform_add_devices(sh7372_early_devices,
                             ARRAY_SIZE(sh7372_early_devices));
 
         platform_add_devices(sh7372_late_devices,
                             ARRAY_SIZE(sh7372_late_devices));
+
+        sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
+        sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
+        sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
 }
 
 void __init sh7372_add_early_devices(void)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 823c703e573c..ed58ef9019b5 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -4,7 +4,6 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
-obj-y                                   += gpio.o
 obj-y                                   += pinmux.o
 obj-y                                   += powergate.o
 obj-y                                   += fuse.o
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index e028320ab423..f8d41ffc0ca9 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -585,7 +585,7 @@ static const struct file_operations possible_parents_fops = {
 
 static int clk_debugfs_register_one(struct clk *c)
 {
-        struct dentry *d, *child, *child_tmp;
+        struct dentry *d;
 
         d = debugfs_create_dir(c->name, clk_debugfs_root);
         if (!d)
@@ -614,10 +614,7 @@ static int clk_debugfs_register_one(struct clk *c)
         return 0;
 
 err_out:
-        d = c->dent;
-        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
-                debugfs_remove(child);
-        debugfs_remove(c->dent);
+        debugfs_remove_recursive(c->dent);
         return -ENOMEM;
 }
 
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
deleted file mode 100644
index 919d63837736..000000000000
--- a/arch/arm/mach-tegra/gpio.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * arch/arm/mach-tegra/gpio.c
- *
- * Copyright (c) 2010 Google, Inc
- *
- * Author:
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
-#define GPIO_BANK(x)            ((x) >> 5)
-#define GPIO_PORT(x)            (((x) >> 3) & 0x3)
-#define GPIO_BIT(x)             ((x) & 0x7)
-
-#define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
-                                 GPIO_BANK(x) * 0x80 +          \
-                                 GPIO_PORT(x) * 4)
-
-#define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
-#define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
-#define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
-#define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
-#define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
-#define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
-#define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
-#define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
-
-#define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x800)
-#define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x810)
-#define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0X820)
-#define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0x840)
-#define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0x850)
-#define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0x860)
-
-#define GPIO_INT_LVL_MASK               0x010101
-#define GPIO_INT_LVL_EDGE_RISING        0x000101
-#define GPIO_INT_LVL_EDGE_FALLING       0x000100
-#define GPIO_INT_LVL_EDGE_BOTH          0x010100
-#define GPIO_INT_LVL_LEVEL_HIGH         0x000001
-#define GPIO_INT_LVL_LEVEL_LOW          0x000000
-
-struct tegra_gpio_bank {
-        int bank;
-        int irq;
-        spinlock_t lvl_lock[4];
-#ifdef CONFIG_PM
-        u32 cnf[4];
-        u32 out[4];
-        u32 oe[4];
-        u32 int_enb[4];
-        u32 int_lvl[4];
-#endif
-};
-
-
-static struct tegra_gpio_bank tegra_gpio_banks[] = {
-        {.bank = 0, .irq = INT_GPIO1},
-        {.bank = 1, .irq = INT_GPIO2},
-        {.bank = 2, .irq = INT_GPIO3},
-        {.bank = 3, .irq = INT_GPIO4},
-        {.bank = 4, .irq = INT_GPIO5},
-        {.bank = 5, .irq = INT_GPIO6},
-        {.bank = 6, .irq = INT_GPIO7},
-};
-
-static int tegra_gpio_compose(int bank, int port, int bit)
-{
-        return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
-}
-
-static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
-{
-        u32 val;
-
-        val = 0x100 << GPIO_BIT(gpio);
-        if (value)
-                val |= 1 << GPIO_BIT(gpio);
-        __raw_writel(val, reg);
-}
-
-void tegra_gpio_enable(int gpio)
-{
-        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
-}
-
-void tegra_gpio_disable(int gpio)
-{
-        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
-}
-
-static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
-}
-
-static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
-}
-
-static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
-        return 0;
-}
-
-static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-                                        int value)
-{
-        tegra_gpio_set(chip, offset, value);
-        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
-        return 0;
-}
-
-
-
-static struct gpio_chip tegra_gpio_chip = {
-        .label                  = "tegra-gpio",
-        .direction_input        = tegra_gpio_direction_input,
-        .get                    = tegra_gpio_get,
-        .direction_output       = tegra_gpio_direction_output,
-        .set                    = tegra_gpio_set,
-        .base                   = 0,
-        .ngpio                  = TEGRA_NR_GPIOS,
-};
-
-static void tegra_gpio_irq_ack(struct irq_data *d)
-{
-        int gpio = d->irq - INT_GPIO_BASE;
-
-        __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
-}
-
-static void tegra_gpio_irq_mask(struct irq_data *d)
-{
-        int gpio = d->irq - INT_GPIO_BASE;
-
-        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
-}
-
-static void tegra_gpio_irq_unmask(struct irq_data *d)
-{
-        int gpio = d->irq - INT_GPIO_BASE;
-
-        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
-}
-
-static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
-{
-        int gpio = d->irq - INT_GPIO_BASE;
-        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        int port = GPIO_PORT(gpio);
-        int lvl_type;
-        int val;
-        unsigned long flags;
-
-        switch (type & IRQ_TYPE_SENSE_MASK) {
-        case IRQ_TYPE_EDGE_RISING:
-                lvl_type = GPIO_INT_LVL_EDGE_RISING;
-                break;
-
-        case IRQ_TYPE_EDGE_FALLING:
-                lvl_type = GPIO_INT_LVL_EDGE_FALLING;
-                break;
-
-        case IRQ_TYPE_EDGE_BOTH:
-                lvl_type = GPIO_INT_LVL_EDGE_BOTH;
-                break;
-
-        case IRQ_TYPE_LEVEL_HIGH:
-                lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
-                break;
-
-        case IRQ_TYPE_LEVEL_LOW:
-                lvl_type = GPIO_INT_LVL_LEVEL_LOW;
-                break;
-
-        default:
-                return -EINVAL;
-        }
-
-        spin_lock_irqsave(&bank->lvl_lock[port], flags);
-
-        val = __raw_readl(GPIO_INT_LVL(gpio));
-        val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
-        val |= lvl_type << GPIO_BIT(gpio);
-        __raw_writel(val, GPIO_INT_LVL(gpio));
-
-        spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
-
-        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-
-        return 0;
-}
-
-static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        struct tegra_gpio_bank *bank;
-        int port;
-        int pin;
-        int unmasked = 0;
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-
-        chained_irq_enter(chip, desc);
-
-        bank = irq_get_handler_data(irq);
-
-        for (port = 0; port < 4; port++) {
-                int gpio = tegra_gpio_compose(bank->bank, port, 0);
-                unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
-                        __raw_readl(GPIO_INT_ENB(gpio));
-                u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
-
-                for_each_set_bit(pin, &sta, 8) {
-                        __raw_writel(1 << pin, GPIO_INT_CLR(gpio));
-
-                        /* if gpio is edge triggered, clear condition
-                         * before executing the hander so that we don't
-                         * miss edges
-                         */
-                        if (lvl & (0x100 << pin)) {
-                                unmasked = 1;
-                                chained_irq_exit(chip, desc);
-                        }
-
-                        generic_handle_irq(gpio_to_irq(gpio + pin));
-                }
-        }
-
-        if (!unmasked)
-                chained_irq_exit(chip, desc);
-
-}
-
-#ifdef CONFIG_PM
-void tegra_gpio_resume(void)
-{
-        unsigned long flags;
-        int b;
-        int p;
-
-        local_irq_save(flags);
-
-        for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
-                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
-
-                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
-                        unsigned int gpio = (b<<5) | (p<<3);
-                        __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
-                        __raw_writel(bank->out[p], GPIO_OUT(gpio));
-                        __raw_writel(bank->oe[p], GPIO_OE(gpio));
-                        __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
-                        __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
-                }
-        }
-
-        local_irq_restore(flags);
-}
-
-void tegra_gpio_suspend(void)
-{
-        unsigned long flags;
-        int b;
-        int p;
-
-        local_irq_save(flags);
-        for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
-                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
-
-                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
-                        unsigned int gpio = (b<<5) | (p<<3);
-                        bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
-                        bank->out[p] = __raw_readl(GPIO_OUT(gpio));
-                        bank->oe[p] = __raw_readl(GPIO_OE(gpio));
-                        bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
-                        bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
-                }
-        }
-        local_irq_restore(flags);
-}
-
-static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
-{
-        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        return irq_set_irq_wake(bank->irq, enable);
-}
-#endif
-
-static struct irq_chip tegra_gpio_irq_chip = {
-        .name           = "GPIO",
-        .irq_ack        = tegra_gpio_irq_ack,
-        .irq_mask       = tegra_gpio_irq_mask,
-        .irq_unmask     = tegra_gpio_irq_unmask,
-        .irq_set_type   = tegra_gpio_irq_set_type,
-#ifdef CONFIG_PM
-        .irq_set_wake   = tegra_gpio_wake_enable,
-#endif
-};
-
-
-/* This lock class tells lockdep that GPIO irqs are in a different
- * category than their parents, so it won't report false recursion.
- */
-static struct lock_class_key gpio_lock_class;
-
-static int __init tegra_gpio_init(void)
-{
-        struct tegra_gpio_bank *bank;
-        int i;
-        int j;
-
-        for (i = 0; i < 7; i++) {
-                for (j = 0; j < 4; j++) {
-                        int gpio = tegra_gpio_compose(i, j, 0);
-                        __raw_writel(0x00, GPIO_INT_ENB(gpio));
-                }
-        }
-
-        gpiochip_add(&tegra_gpio_chip);
-
-        for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
-                bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
-
-                irq_set_lockdep_class(i, &gpio_lock_class);
-                irq_set_chip_data(i, bank);
-                irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
-                                         handle_simple_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-
-        for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
-                bank = &tegra_gpio_banks[i];
-
-                irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
-                irq_set_handler_data(bank->irq, bank);
-
-                for (j = 0; j < 4; j++)
-                        spin_lock_init(&bank->lvl_lock[j]);
-        }
-
-        return 0;
-}
-
-postcore_initcall(tegra_gpio_init);
-
-void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
-{
-        int i;
-
-        for (i = 0; i < num; i++) {
-                int gpio = table[i].gpio;
-
-                if (table[i].enable)
-                        tegra_gpio_enable(gpio);
-                else
-                        tegra_gpio_disable(gpio);
-        }
-}
-
-#ifdef  CONFIG_DEBUG_FS
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-static int dbg_gpio_show(struct seq_file *s, void *unused)
-{
-        int i;
-        int j;
-
-        for (i = 0; i < 7; i++) {
-                for (j = 0; j < 4; j++) {
-                        int gpio = tegra_gpio_compose(i, j, 0);
-                        seq_printf(s,
-                                "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
-                                i, j,
-                                __raw_readl(GPIO_CNF(gpio)),
-                                __raw_readl(GPIO_OE(gpio)),
-                                __raw_readl(GPIO_OUT(gpio)),
-                                __raw_readl(GPIO_IN(gpio)),
-                                __raw_readl(GPIO_INT_STA(gpio)),
-                                __raw_readl(GPIO_INT_ENB(gpio)),
-                                __raw_readl(GPIO_INT_LVL(gpio)));
-                }
-        }
-        return 0;
-}
-
-static int dbg_gpio_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, dbg_gpio_show, &inode->i_private);
-}
-
-static const struct file_operations debug_fops = {
-        .open           = dbg_gpio_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init tegra_gpio_debuginit(void)
-{
-        (void) debugfs_create_file("tegra_gpio", S_IRUGO,
-                                        NULL, NULL, &debug_fops);
-        return 0;
-}
-late_initcall(tegra_gpio_debuginit);
-#endif
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 32ce90840ee1..7d107be63eb4 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -635,16 +635,13 @@ static const struct file_operations set_rate_fops = {
 static struct dentry *clk_debugfs_register_dir(struct clk *c,
                                                 struct dentry *p_dentry)
 {
-        struct dentry *d, *clk_d, *child, *child_tmp;
-        char s[255];
-        char *p = s;
+        struct dentry *d, *clk_d;
+        const char *p = c->name;
 
-        if (c->name == NULL)
-                p += sprintf(p, "BUG");
-        else
-                p += sprintf(p, "%s", c->name);
+        if (!p)
+                p = "BUG";
 
-        clk_d = debugfs_create_dir(s, p_dentry);
+        clk_d = debugfs_create_dir(p, p_dentry);
         if (!clk_d)
                 return NULL;
 
@@ -666,24 +663,10 @@ static struct dentry *clk_debugfs_register_dir(struct clk *c,
         return clk_d;
 
 err_out:
-        d = clk_d;
-        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
-                debugfs_remove(child);
-        debugfs_remove(clk_d);
+        debugfs_remove_recursive(clk_d);
         return NULL;
 }
 
-static void clk_debugfs_remove_dir(struct dentry *cdentry)
-{
-        struct dentry *d, *child, *child_tmp;
-
-        d = cdentry;
-        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
-                debugfs_remove(child);
-        debugfs_remove(cdentry);
-        return ;
-}
-
 static int clk_debugfs_register_one(struct clk *c)
 {
         struct clk *pa = c->parent_periph;
@@ -700,7 +683,7 @@ static int clk_debugfs_register_one(struct clk *c)
                 c->dent_bus = clk_debugfs_register_dir(c,
                                 bpa->dent_bus ? bpa->dent_bus : bpa->dent);
                 if ((!c->dent_bus) &&  (c->dent)) {
-                        clk_debugfs_remove_dir(c->dent);
+                        debugfs_remove_recursive(c->dent);
                         c->dent = NULL;
                         return -ENOMEM;
                 }
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 245140c0df10..642de0408f25 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -39,9 +39,10 @@
 static void __iomem *ic_regbase;
 static void __iomem *sic_regbase;
 
-static void vt8500_irq_mask(unsigned int irq)
+static void vt8500_irq_mask(struct irq_data *d)
 {
         void __iomem *base = ic_regbase;
+        unsigned irq = d->irq;
         u8 edge;
 
         if (irq >= 64) {
@@ -64,9 +65,10 @@ static void vt8500_irq_mask(unsigned int irq)
         }
 }
 
-static void vt8500_irq_unmask(unsigned int irq)
+static void vt8500_irq_unmask(struct irq_data *d)
 {
         void __iomem *base = ic_regbase;
+        unsigned irq = d->irq;
         u8 dctr;
 
         if (irq >= 64) {
@@ -78,10 +80,11 @@ static void vt8500_irq_unmask(unsigned int irq)
         writeb(dctr, base + VT8500_IC_DCTR + irq);
 }
 
-static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
         void __iomem *base = ic_regbase;
-        unsigned int orig_irq = irq;
+        unsigned irq = d->irq;
+        unsigned orig_irq = irq;
         u8 dctr;
 
         if (irq >= 64) {
@@ -114,11 +117,11 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type)
 }
 
 static struct irq_chip vt8500_irq_chip = {
-        .name      = "vt8500",
-        .ack       = vt8500_irq_mask,
-        .mask      = vt8500_irq_mask,
-        .unmask    = vt8500_irq_unmask,
-        .set_type  = vt8500_irq_set_type,
+        .name = "vt8500",
+        .irq_ack = vt8500_irq_mask,
+        .irq_mask = vt8500_irq_mask,
+        .irq_unmask = vt8500_irq_unmask,
+        .irq_set_type = vt8500_irq_set_type,
 };
 
 void __init vt8500_init_irq(void)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index ef59099a5463..44c086710d2b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -120,17 +120,22 @@ static void l2x0_cache_sync(void)
         spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
-static void l2x0_flush_all(void)
+static void __l2x0_flush_all(void)
 {
-        unsigned long flags;
-
-        /* clean all ways */
-        spin_lock_irqsave(&l2x0_lock, flags);
         debug_writel(0x03);
         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
         cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
         cache_sync();
         debug_writel(0x00);
+}
+
+static void l2x0_flush_all(void)
+{
+        unsigned long flags;
+
+        /* clean all ways */
+        spin_lock_irqsave(&l2x0_lock, flags);
+        __l2x0_flush_all();
         spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
@@ -266,7 +271,9 @@ static void l2x0_disable(void)
         unsigned long flags;
 
         spin_lock_irqsave(&l2x0_lock, flags);
-        writel(0, l2x0_base + L2X0_CTRL);
+        __l2x0_flush_all();
+        writel_relaxed(0, l2x0_base + L2X0_CTRL);
+        dsb();
         spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index bc0e1d88fd3b..9ea4f7ddd665 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -318,11 +318,11 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         fault = __do_page_fault(mm, addr, fsr, tsk);
         up_read(&mm->mmap_sem);
 
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, addr);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
         if (fault & VM_FAULT_MAJOR)
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, regs, addr);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, addr);
         else if (fault & VM_FAULT_MINOR)
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, regs, addr);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, addr);
 
         /*
          * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 9d9e736c2b4f..594d677b92c8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -759,7 +759,7 @@ early_param("vmalloc", early_vmalloc);
 
 static phys_addr_t lowmem_limit __initdata = 0;
 
-static void __init sanity_check_meminfo(void)
+void __init sanity_check_meminfo(void)
 {
         int i, j, highmem = 0;
 
@@ -1032,8 +1032,9 @@ void __init paging_init(struct machine_desc *mdesc)
 {
         void *zero_page;
 
+        memblock_set_current_limit(lowmem_limit);
+
         build_mem_type_table();
-        sanity_check_meminfo();
         prepare_page_table();
         map_lowmem();
         devicemaps_init(mdesc);
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 687d02319a41..941a98c9e8aa 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -27,6 +27,10 @@ void __init arm_mm_memblock_reserve(void)
         memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
 }
 
+void __init sanity_check_meminfo(void)
+{
+}
+
 /*
  * paging_init() sets up the page tables, initialises the zone memory
  * maps, and sets up the zero page, bad page and bad page tables.
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index a1387875a491..d53c35fe2ea7 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o
+obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
 # MX51 uses the TZIC interrupt controller, older platforms use AVIC
 obj-$(CONFIG_MXC_TZIC) += tzic.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index eee1b6096a08..fb166b20f60f 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -89,3 +89,14 @@ err:
 
         return pdev;
 }
+
+struct device mxc_aips_bus = {
+        .init_name      = "mxc_aips",
+        .parent         = &platform_bus,
+};
+
+static int __init mxc_device_init(void)
+{
+        return device_register(&mxc_aips_bus);
+}
+core_initcall(mxc_device_init);
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index ad2922acf480..b41bf972b54b 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
+obj-y += platform-gpio-mxc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index ccc789e21daa..4fc6ffc2a13e 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <asm/sizes.h>
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
index 59c33f6e401c..23ce08e6ffd2 100644
--- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
 
diff --git a/arch/arm/plat-mxc/devices/platform-gpio-mxc.c b/arch/arm/plat-mxc/devices/platform-gpio-mxc.c
new file mode 100644
index 000000000000..a7919a241032
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-gpio-mxc.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init mxc_register_gpio(char *name, int id,
+        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = irq_high,
+                        .end = irq_high,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return platform_device_register_resndata(&mxc_aips_bus,
+                        name, id, res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
index 79a1cb18a5b0..2b0b5e0aa998 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-fb.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
 
diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c
index edf65034aea5..79d340ae0af1 100644
--- a/arch/arm/plat-mxc/devices/platform-ipu-core.c
+++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
 
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
index cc488f4b6204..e1763e03e7cb 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
 
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
index 90d762f6f93b..540d3a7d92df 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
@@ -6,6 +6,7 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
 
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index f97eb3615b2c..9bfae8bd5b8d 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -40,9 +40,10 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
 #endif
 
 #ifdef CONFIG_SOC_IMX25
+/* i.mx25 has the i.mx35 type cspi */
 const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
 #define imx25_cspi_data_entry(_id, _hwid)                               \
-        imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
+        imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K)
         imx25_cspi_data_entry(0, 1),
         imx25_cspi_data_entry(1, 2),
         imx25_cspi_data_entry(2, 3),
@@ -79,8 +80,9 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
 #ifdef CONFIG_SOC_IMX51
+/* i.mx51 has the i.mx35 type cspi */
 const struct imx_spi_imx_data imx51_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K);
+        imx_spi_imx_data_entry_single(MX51, CSPI, "imx35-cspi", 2, , SZ_4K);
 
 const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
 #define imx51_ecspi_data_entry(_id, _hwid)                              \
@@ -91,12 +93,14 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
 #ifdef CONFIG_SOC_IMX53
+/* i.mx53 has the i.mx35 type cspi */
 const struct imx_spi_imx_data imx53_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX53, CSPI, "imx53-cspi", 0, , SZ_4K);
+        imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 0, , SZ_4K);
 
+/* i.mx53 has the i.mx51 type ecspi */
 const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
 #define imx53_ecspi_data_entry(_id, _hwid)                              \
-        imx_spi_imx_data_entry(MX53, ECSPI, "imx53-ecspi", _id, _hwid, SZ_4K)
+        imx_spi_imx_data_entry(MX53, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
         imx53_ecspi_data_entry(0, 1),
         imx53_ecspi_data_entry(1, 2),
 };
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
deleted file mode 100644
index 6cd6d7f686f6..000000000000
--- a/arch/arm/plat-mxc/gpio.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * Based on code from Freescale,
- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <mach/hardware.h>
-#include <asm-generic/bug.h>
-
-static struct mxc_gpio_port *mxc_gpio_ports;
-static int gpio_table_size;
-
-#define cpu_is_mx1_mx2()        (cpu_is_mx1() || cpu_is_mx2())
-
-#define GPIO_DR         (cpu_is_mx1_mx2() ? 0x1c : 0x00)
-#define GPIO_GDIR       (cpu_is_mx1_mx2() ? 0x00 : 0x04)
-#define GPIO_PSR        (cpu_is_mx1_mx2() ? 0x24 : 0x08)
-#define GPIO_ICR1       (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
-#define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
-#define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
-#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
-
-#define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
-#define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
-#define GPIO_INT_RISE_EDGE      (cpu_is_mx1_mx2() ? 0x0 : 0x2)
-#define GPIO_INT_FALL_EDGE      (cpu_is_mx1_mx2() ? 0x1 : 0x3)
-#define GPIO_INT_NONE           0x4
-
-/* Note: This driver assumes 32 GPIOs are handled in one register */
-
-static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
-{
-        __raw_writel(1 << index, port->base + GPIO_ISR);
-}
-
-static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
-                                int enable)
-{
-        u32 l;
-
-        l = __raw_readl(port->base + GPIO_IMR);
-        l = (l & (~(1 << index))) | (!!enable << index);
-        __raw_writel(l, port->base + GPIO_IMR);
-}
-
-static void gpio_ack_irq(struct irq_data *d)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
-}
-
-static void gpio_mask_irq(struct irq_data *d)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
-}
-
-static void gpio_unmask_irq(struct irq_data *d)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
-}
-
-static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
-
-static int gpio_set_irq_type(struct irq_data *d, u32 type)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
-        u32 bit, val;
-        int edge;
-        void __iomem *reg = port->base;
-
-        port->both_edges &= ~(1 << (gpio & 31));
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                edge = GPIO_INT_RISE_EDGE;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                edge = GPIO_INT_FALL_EDGE;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                val = mxc_gpio_get(&port->chip, gpio & 31);
-                if (val) {
-                        edge = GPIO_INT_LOW_LEV;
-                        pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
-                } else {
-                        edge = GPIO_INT_HIGH_LEV;
-                        pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
-                }
-                port->both_edges |= 1 << (gpio & 31);
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                edge = GPIO_INT_LOW_LEV;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                edge = GPIO_INT_HIGH_LEV;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
-        bit = gpio & 0xf;
-        val = __raw_readl(reg) & ~(0x3 << (bit << 1));
-        __raw_writel(val | (edge << (bit << 1)), reg);
-        _clear_gpio_irqstatus(port, gpio & 0x1f);
-
-        return 0;
-}
-
-static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
-{
-        void __iomem *reg = port->base;
-        u32 bit, val;
-        int edge;
-
-        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
-        bit = gpio & 0xf;
-        val = __raw_readl(reg);
-        edge = (val >> (bit << 1)) & 3;
-        val &= ~(0x3 << (bit << 1));
-        if (edge == GPIO_INT_HIGH_LEV) {
-                edge = GPIO_INT_LOW_LEV;
-                pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
-        } else if (edge == GPIO_INT_LOW_LEV) {
-                edge = GPIO_INT_HIGH_LEV;
-                pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
-        } else {
-                pr_err("mxc: invalid configuration for GPIO %d: %x\n",
-                       gpio, edge);
-                return;
-        }
-        __raw_writel(val | (edge << (bit << 1)), reg);
-}
-
-/* handle 32 interrupts in one status register */
-static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
-{
-        u32 gpio_irq_no_base = port->virtual_irq_start;
-
-        while (irq_stat != 0) {
-                int irqoffset = fls(irq_stat) - 1;
-
-                if (port->both_edges & (1 << irqoffset))
-                        mxc_flip_edge(port, irqoffset);
-
-                generic_handle_irq(gpio_irq_no_base + irqoffset);
-
-                irq_stat &= ~(1 << irqoffset);
-        }
-}
-
-/* MX1 and MX3 has one interrupt *per* gpio port */
-static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
-{
-        u32 irq_stat;
-        struct mxc_gpio_port *port = irq_get_handler_data(irq);
-
-        irq_stat = __raw_readl(port->base + GPIO_ISR) &
-                        __raw_readl(port->base + GPIO_IMR);
-
-        mxc_gpio_irq_handler(port, irq_stat);
-}
-
-/* MX2 has one interrupt *for all* gpio ports */
-static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
-{
-        int i;
-        u32 irq_msk, irq_stat;
-        struct mxc_gpio_port *port = irq_get_handler_data(irq);
-
-        /* walk through all interrupt status registers */
-        for (i = 0; i < gpio_table_size; i++) {
-                irq_msk = __raw_readl(port[i].base + GPIO_IMR);
-                if (!irq_msk)
-                        continue;
-
-                irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
-                if (irq_stat)
-                        mxc_gpio_irq_handler(&port[i], irq_stat);
-        }
-}
-
-/*
- * Set interrupt number "irq" in the GPIO as a wake-up source.
- * While system is running, all registered GPIO interrupts need to have
- * wake-up enabled. When system is suspended, only selected GPIO interrupts
- * need to have wake-up enabled.
- * @param  irq          interrupt source number
- * @param  enable       enable as wake-up if equal to non-zero
- * @return       This function returns 0 on success.
- */
-static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
-{
-        u32 gpio = irq_to_gpio(d->irq);
-        u32 gpio_idx = gpio & 0x1F;
-        struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
-
-        if (enable) {
-                if (port->irq_high && (gpio_idx >= 16))
-                        enable_irq_wake(port->irq_high);
-                else
-                        enable_irq_wake(port->irq);
-        } else {
-                if (port->irq_high && (gpio_idx >= 16))
-                        disable_irq_wake(port->irq_high);
-                else
-                        disable_irq_wake(port->irq);
-        }
-
-        return 0;
-}
-
-static struct irq_chip gpio_irq_chip = {
-        .name = "GPIO",
-        .irq_ack = gpio_ack_irq,
-        .irq_mask = gpio_mask_irq,
-        .irq_unmask = gpio_unmask_irq,
-        .irq_set_type = gpio_set_irq_type,
-        .irq_set_wake = gpio_set_wake_irq,
-};
-
-static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
-                                int dir)
-{
-        struct mxc_gpio_port *port =
-                container_of(chip, struct mxc_gpio_port, chip);
-        u32 l;
-        unsigned long flags;
-
-        spin_lock_irqsave(&port->lock, flags);
-        l = __raw_readl(port->base + GPIO_GDIR);
-        if (dir)
-                l |= 1 << offset;
-        else
-                l &= ~(1 << offset);
-        __raw_writel(l, port->base + GPIO_GDIR);
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct mxc_gpio_port *port =
-                container_of(chip, struct mxc_gpio_port, chip);
-        void __iomem *reg = port->base + GPIO_DR;
-        u32 l;
-        unsigned long flags;
-
-        spin_lock_irqsave(&port->lock, flags);
-        l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset);
-        __raw_writel(l, reg);
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct mxc_gpio_port *port =
-                container_of(chip, struct mxc_gpio_port, chip);
-
-        return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
-}
-
-static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        _set_gpio_direction(chip, offset, 0);
-        return 0;
-}
-
-static int mxc_gpio_direction_output(struct gpio_chip *chip,
-                                     unsigned offset, int value)
-{
-        mxc_gpio_set(chip, offset, value);
-        _set_gpio_direction(chip, offset, 1);
-        return 0;
-}
-
-/*
- * This lock class tells lockdep that GPIO irqs are in a different
- * category than their parents, so it won't report false recursion.
- */
-static struct lock_class_key gpio_lock_class;
-
-int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
-{
-        int i, j;
-
-        /* save for local usage */
-        mxc_gpio_ports = port;
-        gpio_table_size = cnt;
-
-        printk(KERN_INFO "MXC GPIO hardware\n");
-
-        for (i = 0; i < cnt; i++) {
-                /* disable the interrupt and clear the status */
-                __raw_writel(0, port[i].base + GPIO_IMR);
-                __raw_writel(~0, port[i].base + GPIO_ISR);
-                for (j = port[i].virtual_irq_start;
-                        j < port[i].virtual_irq_start + 32; j++) {
-                        irq_set_lockdep_class(j, &gpio_lock_class);
-                        irq_set_chip_and_handler(j, &gpio_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(j, IRQF_VALID);
-                }
-
-                /* register gpio chip */
-                port[i].chip.direction_input = mxc_gpio_direction_input;
-                port[i].chip.direction_output = mxc_gpio_direction_output;
-                port[i].chip.get = mxc_gpio_get;
-                port[i].chip.set = mxc_gpio_set;
-                port[i].chip.base = i * 32;
-                port[i].chip.ngpio = 32;
-
-                spin_lock_init(&port[i].lock);
-
-                /* its a serious configuration bug when it fails */
-                BUG_ON( gpiochip_add(&port[i].chip) < 0 );
-
-                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
-                        /* setup one handler for each entry */
-                        irq_set_chained_handler(port[i].irq,
-                                                mx3_gpio_irq_handler);
-                        irq_set_handler_data(port[i].irq, &port[i]);
-                        if (port[i].irq_high) {
-                                /* setup handler for GPIO 16 to 31 */
-                                irq_set_chained_handler(port[i].irq_high,
-                                                        mx3_gpio_irq_handler);
-                                irq_set_handler_data(port[i].irq_high,
-                                                     &port[i]);
-                        }
-                }
-        }
-
-        if (cpu_is_mx2()) {
-                /* setup one handler for all GPIO interrupts */
-                irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-                irq_set_handler_data(port[0].irq, port);
-        }
-
-        return 0;
-}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index da7991832af6..4e3d97890d69 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -43,6 +43,15 @@ extern void mx35_init_irq(void);
 extern void mx50_init_irq(void);
 extern void mx51_init_irq(void);
 extern void mx53_init_irq(void);
+extern void imx1_soc_init(void);
+extern void imx21_soc_init(void);
+extern void imx25_soc_init(void);
+extern void imx27_soc_init(void);
+extern void imx31_soc_init(void);
+extern void imx35_soc_init(void);
+extern void imx50_soc_init(void);
+extern void imx51_soc_init(void);
+extern void imx53_soc_init(void);
 extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
 extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
@@ -55,7 +64,8 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
-extern int mxc_register_gpios(void);
+extern struct platform_device *mxc_register_gpio(char *name, int id,
+        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_arch_reset_init(void __iomem *);
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index fa8477337f91..03f626645374 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -10,6 +10,8 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 
+extern struct device mxc_aips_bus;
+
 struct platform_device *imx_add_platform_device_dmamask(
                 const char *name, int id,
                 const struct resource *res, unsigned int num_resources,
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index a2747f12813e..31c820c1b796 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -36,31 +36,4 @@
 #define gpio_to_irq(gpio)       (MXC_GPIO_IRQ_START + (gpio))
 #define irq_to_gpio(irq)        ((irq) - MXC_GPIO_IRQ_START)
 
-struct mxc_gpio_port {
-        void __iomem *base;
-        int irq;
-        int irq_high;
-        int virtual_irq_start;
-        struct gpio_chip chip;
-        u32 both_edges;
-        spinlock_t lock;
-};
-
-#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
-        {                                                               \
-                .chip.label = "gpio-" #_id,                             \
-                .irq = _irq,                                            \
-                .irq_high = _irq_high,                                  \
-                .base = soc ## _IO_ADDRESS(                             \
-                                soc ## _GPIO ## _hwid ## _BASE_ADDR),   \
-                .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32,   \
-        }
-
-#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq)                 \
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
-#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid)                           \
-        DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
-
-int mxc_gpio_init(struct mxc_gpio_port*, int);
-
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 35c89bcdf758..00e812bbd81d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_IRQS_H__
 #define __ASM_ARCH_MXC_IRQS_H__
 
+#include <asm-generic/gpio.h>
+
 /*
  * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
  */
@@ -22,30 +24,13 @@
 
 #define MXC_GPIO_IRQ_START      MXC_INTERNAL_IRQS
 
-/* these are ordered by size to support multi-SoC kernels */
-#if defined CONFIG_SOC_IMX53
-#define MXC_GPIO_IRQS           (32 * 7)
-#elif defined CONFIG_ARCH_MX2
-#define MXC_GPIO_IRQS           (32 * 6)
-#elif defined CONFIG_SOC_IMX50
-#define MXC_GPIO_IRQS           (32 * 6)
-#elif defined CONFIG_ARCH_MX1
-#define MXC_GPIO_IRQS           (32 * 4)
-#elif defined CONFIG_ARCH_MX25
-#define MXC_GPIO_IRQS           (32 * 4)
-#elif defined CONFIG_SOC_IMX51
-#define MXC_GPIO_IRQS           (32 * 4)
-#elif defined CONFIG_ARCH_MX3
-#define MXC_GPIO_IRQS           (32 * 3)
-#endif
-
 /*
  * The next 16 interrupts are for board specific purposes.  Since
  * the kernel can only run on one machine at a time, we can re-use
  * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
  * within sensible limits.
  */
-#define MXC_BOARD_IRQ_START     (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
+#define MXC_BOARD_IRQ_START     (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 #define MXC_BOARD_IRQS  80
diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
index c44886062f8e..685c78716d95 100644
--- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h
+++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
@@ -10,6 +10,7 @@
 #define STE_DMA40_H
 
 #include <linux/dmaengine.h>
+#include <linux/scatterlist.h>
 #include <linux/workqueue.h>
 #include <linux/interrupt.h>
 
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index c9122dd6ee8d..964704f40bbe 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -480,13 +480,10 @@ static struct dentry *clk_debugfs_root;
 static int clk_debugfs_register_one(struct clk *c)
 {
         int err;
-        struct dentry *d, *child, *child_tmp;
+        struct dentry *d;
         struct clk *pa = c->parent;
-        char s[255];
-        char *p = s;
 
-        p += sprintf(p, "%s", c->name);
-        d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
+        d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
         if (!d)
                 return -ENOMEM;
         c->dent = d;
@@ -509,10 +506,7 @@ static int clk_debugfs_register_one(struct clk *c)
         return 0;
 
 err_out:
-        d = c->dent;
-        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
-                debugfs_remove(child);
-        debugfs_remove(c->dent);
+        debugfs_remove_recursive(c->dent);
         return err;
 }
 
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index ec97e00cb581..91e8de3db085 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -174,12 +174,32 @@ struct omap_gpio_dev_attr {
         bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
 };
 
+struct omap_gpio_reg_offs {
+        u16 revision;
+        u16 direction;
+        u16 datain;
+        u16 dataout;
+        u16 set_dataout;
+        u16 clr_dataout;
+        u16 irqstatus;
+        u16 irqstatus2;
+        u16 irqenable;
+        u16 set_irqenable;
+        u16 clr_irqenable;
+        u16 debounce;
+        u16 debounce_en;
+
+        bool irqenable_inv;
+};
+
 struct omap_gpio_platform_data {
         u16 virtual_irq_start;
         int bank_type;
         int bank_width;         /* GPIO bank width */
         int bank_stride;        /* Only needed for omap1 MPUIO */
         bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
+
+        struct omap_gpio_reg_offs *regs;
 };
 
 /* TODO: Analyze removing gpio_bank_count usage from driver code */
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index e4c349ff9fd8..ee405b36df4b 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -44,6 +44,10 @@ extern struct device omap_device_parent;
 #define OMAP_DEVICE_STATE_IDLE          2
 #define OMAP_DEVICE_STATE_SHUTDOWN      3
 
+/* omap_device.flags values */
+#define OMAP_DEVICE_SUSPENDED BIT(0)
+#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
+
 /**
  * struct omap_device - omap_device wrapper for platform_devices
  * @pdev: platform_device
@@ -73,6 +77,7 @@ struct omap_device {
         s8                              pm_lat_level;
         u8                              hwmods_cnt;
         u8                              _state;
+        u8                              flags;
 };
 
 /* Device driver interface (call via platform_data fn ptrs) */
@@ -117,6 +122,10 @@ int omap_device_enable_hwmods(struct omap_device *od);
 int omap_device_disable_clocks(struct omap_device *od);
 int omap_device_enable_clocks(struct omap_device *od);
 
+static inline void omap_device_disable_idle_on_suspend(struct omap_device *od)
+{
+        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
+}
 
 /*
  * Entries should be kept in latency order ascending
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 49fc0df0c21f..2526fa312b8a 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -537,6 +537,7 @@ int omap_early_device_register(struct omap_device *od)
         return 0;
 }
 
+#ifdef CONFIG_PM_RUNTIME
 static int _od_runtime_suspend(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
@@ -563,13 +564,55 @@ static int _od_runtime_resume(struct device *dev)
 
         return pm_generic_runtime_resume(dev);
 }
+#endif
 
-static struct dev_power_domain omap_device_power_domain = {
+#ifdef CONFIG_SUSPEND
+static int _od_suspend_noirq(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od = to_omap_device(pdev);
+        int ret;
+
+        if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
+                return pm_generic_suspend_noirq(dev);
+
+        ret = pm_generic_suspend_noirq(dev);
+
+        if (!ret && !pm_runtime_status_suspended(dev)) {
+                if (pm_generic_runtime_suspend(dev) == 0) {
+                        omap_device_idle(pdev);
+                        od->flags |= OMAP_DEVICE_SUSPENDED;
+                }
+        }
+
+        return ret;
+}
+
+static int _od_resume_noirq(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od = to_omap_device(pdev);
+
+        if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
+                return pm_generic_resume_noirq(dev);
+
+        if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
+            !pm_runtime_status_suspended(dev)) {
+                od->flags &= ~OMAP_DEVICE_SUSPENDED;
+                omap_device_enable(pdev);
+                pm_generic_runtime_resume(dev);
+        }
+
+        return pm_generic_resume_noirq(dev);
+}
+#endif
+
+static struct dev_pm_domain omap_device_pm_domain = {
         .ops = {
-                .runtime_suspend = _od_runtime_suspend,
-                .runtime_idle = _od_runtime_idle,
-                .runtime_resume = _od_runtime_resume,
+                SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
+                                   _od_runtime_idle)
                 USE_PLATFORM_PM_SLEEP_OPS
+                SET_SYSTEM_SLEEP_PM_OPS(_od_suspend_noirq, _od_resume_noirq)
         }
 };
 
@@ -586,7 +629,7 @@ int omap_device_register(struct omap_device *od)
         pr_debug("omap_device: %s: registering\n", od->pdev.name);
 
         od->pdev.dev.parent = &omap_device_parent;
-        od->pdev.dev.pwr_domain = &omap_device_power_domain;
+        od->pdev.dev.pm_domain = &omap_device_pm_domain;
         return platform_device_register(&od->pdev);
 }
 
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 5b4fffab1eb4..41ab97ebe4cf 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -432,7 +432,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
         ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
         ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
         ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_ack = irq_gc_ack_clr_bit;
         ct->chip.irq_mask = irq_gc_mask_clr_bit;
         ct->chip.irq_unmask = irq_gc_mask_set_bit;
         ct->chip.irq_set_type = gpio_irq_set_type;
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index 48ebb9479b61..a11dc3670505 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -50,7 +50,7 @@ static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
         return container_of(c, struct pxa_gpio_chip, chip)->regbase;
 }
 
-static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio)
+static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
 {
         return &pxa_gpio_chips[gpio_to_bank(gpio)];
 }
@@ -161,7 +161,7 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
         int gpio = irq_to_gpio(d->irq);
         unsigned long gpdr, mask = GPIO_bit(gpio);
 
-        c = gpio_to_chip(gpio);
+        c = gpio_to_pxachip(gpio);
 
         if (type == IRQ_TYPE_PROBE) {
                 /* Don't mess with enabled GPIOs using preconfigured edges or
@@ -230,7 +230,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 static void pxa_ack_muxed_gpio(struct irq_data *d)
 {
         int gpio = irq_to_gpio(d->irq);
-        struct pxa_gpio_chip *c = gpio_to_chip(gpio);
+        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
 
         __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
 }
@@ -238,7 +238,7 @@ static void pxa_ack_muxed_gpio(struct irq_data *d)
 static void pxa_mask_muxed_gpio(struct irq_data *d)
 {
         int gpio = irq_to_gpio(d->irq);
-        struct pxa_gpio_chip *c = gpio_to_chip(gpio);
+        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
         uint32_t grer, gfer;
 
         c->irq_mask &= ~GPIO_bit(gpio);
@@ -252,7 +252,7 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)
 static void pxa_unmask_muxed_gpio(struct irq_data *d)
 {
         int gpio = irq_to_gpio(d->irq);
-        struct pxa_gpio_chip *c = gpio_to_chip(gpio);
+        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
 
         c->irq_mask |= GPIO_bit(gpio);
         update_edge_detect(c);
diff --git a/arch/arm/plat-pxa/include/plat/sdhci.h b/arch/arm/plat-pxa/include/plat/sdhci.h
deleted file mode 100644
index 1ab332e37d7d..000000000000
--- a/arch/arm/plat-pxa/include/plat/sdhci.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* linux/arch/arm/plat-pxa/include/plat/sdhci.h
- *
- * Copyright 2010 Marvell
- *      Zhangfei Gao <zhangfei.gao@marvell.com>
- *
- * PXA Platform - SDHCI platform data definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __PLAT_PXA_SDHCI_H
-#define __PLAT_PXA_SDHCI_H
-
-/* pxa specific flag */
-/* Require clock free running */
-#define PXA_FLAG_DISABLE_CLOCK_GATING (1<<0)
-
-/* Board design supports 8-bit data on SD/SDIO BUS */
-#define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2)
-
-/*
- * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
- * @max_speed: the maximum speed supported
- * @quirks: quirks of specific device
- * @flags: flags for platform requirement
- */
-struct sdhci_pxa_platdata {
-        unsigned int    max_speed;
-        unsigned int    quirks;
-        unsigned int    flags;
-};
-
-#endif /* __PLAT_PXA_SDHCI_H */
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 2abf9660bc6c..539bd0e3defd 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -712,7 +712,7 @@ static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
  * get control of an dma channel
 */
 
-int s3c2410_dma_request(unsigned int channel,
+int s3c2410_dma_request(enum dma_ch channel,
                         struct s3c2410_dma_client *client,
                         void *dev)
 {
@@ -783,7 +783,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
  * allowed to go through.
 */
 
-int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
+int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
         unsigned long flags;
@@ -974,7 +974,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
 }
 
 int
-s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
+s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
@@ -1021,23 +1021,19 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
  * xfersize:     size of unit in bytes (1,2,4)
 */
 
-int s3c2410_dma_config(unsigned int channel,
+int s3c2410_dma_config(enum dma_ch channel,
                        int xferunit)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
         unsigned int dcon;
 
-        pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
-                 __func__, channel, xferunit, dcon);
+        pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
 
         if (chan == NULL)
                 return -EINVAL;
 
-        pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
-
         dcon = chan->dcon & dma_sel.dcon_mask;
-
-        pr_debug("%s: New dcon is %08x\n", __func__, dcon);
+        pr_debug("%s: dcon is %08x\n", __func__, dcon);
 
         switch (chan->req_ch) {
         case DMACH_I2S_IN:
@@ -1104,7 +1100,7 @@ EXPORT_SYMBOL(s3c2410_dma_config);
  * devaddr:   physical address of the source
 */
 
-int s3c2410_dma_devconfig(unsigned int channel,
+int s3c2410_dma_devconfig(enum dma_ch channel,
                           enum s3c2410_dmasrc source,
                           unsigned long devaddr)
 {
@@ -1177,7 +1173,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
  * returns the current transfer points for the dma source and destination
 */
 
-int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
+int s3c2410_dma_getposition(enum dma_ch channel, dma_addr_t *src, dma_addr_t *dst)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
@@ -1235,7 +1231,7 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
         /* restore channel's hardware configuration */
 
         if (!cp->in_use)
-                return 0;
+                return;
 
         printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
 
@@ -1246,8 +1242,6 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
 
         if (cp->map != NULL)
                 dma_sel.select(cp, cp->map);
-
-        return 0;
 }
 
 static void s3c2410_dma_resume(void)
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 135abda31c9a..327ab9f662e8 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -152,7 +152,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
         if (!gc)
                 return -ENOMEM;
         ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_ack = irq_gc_ack_set_bit;
         ct->chip.irq_mask = irq_gc_mask_set_bit;
         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
         ct->chip.irq_set_type = s5p_gpioint_set_type,
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 899a8cc011ff..612934c48b0d 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -370,11 +370,11 @@ static void __init s5p_clocksource_init(void)
 
         clock_rate = clk_get_rate(tin_source);
 
-        init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
-
         s5p_time_setup(timer_source.source_id, TCNT_MAX);
         s5p_time_start(timer_source.source_id, PERIODIC);
 
+        init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
+
         if (clocksource_register_hz(&time_clocksource, clock_rate))
                 panic("%s: can't register clocksource\n", time_clocksource.name);
 }
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 772892826ffc..0c9f95d98561 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -458,7 +458,7 @@ static struct dentry *clk_debugfs_root;
 static int clk_debugfs_register_one(struct clk *c)
 {
         int err;
-        struct dentry *d, *child, *child_tmp;
+        struct dentry *d;
         struct clk *pa = c->parent;
         char s[255];
         char *p = s;
@@ -488,10 +488,7 @@ static int clk_debugfs_register_one(struct clk *c)
         return 0;
 
 err_out:
-        d = c->dent;
-        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
-                debugfs_remove(child);
-        debugfs_remove(c->dent);
+        debugfs_remove_recursive(c->dent);
         return err;
 }
 
diff --git a/arch/arm/plat-samsung/dma.c b/arch/arm/plat-samsung/dma.c
index cb459dd95459..6143aa147688 100644
--- a/arch/arm/plat-samsung/dma.c
+++ b/arch/arm/plat-samsung/dma.c
@@ -41,7 +41,7 @@ struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
  * irq?
 */
 
-int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
+int s3c2410_dma_set_opfn(enum dma_ch channel, s3c2410_dma_opfn_t rtn)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
@@ -56,7 +56,7 @@ int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
 }
 EXPORT_SYMBOL(s3c2410_dma_set_opfn);
 
-int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
+int s3c2410_dma_set_buffdone_fn(enum dma_ch channel, s3c2410_dma_cbfn_t rtn)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
@@ -71,7 +71,7 @@ int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
 }
 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
 
-int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
+int s3c2410_dma_setflags(enum dma_ch channel, unsigned int flags)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4af108ff4112..e3b31c26ac3e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -12,6 +12,10 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
+
+#ifndef __PLAT_DEVS_H
+#define __PLAT_DEVS_H __FILE__
+
 #include <linux/platform_device.h>
 
 struct s3c24xx_uart_resources {
@@ -159,3 +163,5 @@ extern struct platform_device s3c_device_ac97;
  */
 extern void *s3c_set_platdata(void *pd, size_t pdsize,
                               struct platform_device *pdev);
+
+#endif /* __PLAT_DEVS_H */
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
index 2e8f8c6560d7..8c273b7a6f56 100644
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -42,6 +42,7 @@ struct s3c2410_dma_client {
 };
 
 struct s3c2410_dma_chan;
+enum dma_ch;
 
 /* s3c2410_dma_cbfn_t
  *
@@ -62,7 +63,7 @@ typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
  * request a dma channel exclusivley
 */
 
-extern int s3c2410_dma_request(unsigned int channel,
+extern int s3c2410_dma_request(enum dma_ch channel,
                                struct s3c2410_dma_client *, void *dev);
 
 
@@ -71,14 +72,14 @@ extern int s3c2410_dma_request(unsigned int channel,
  * change the state of the dma channel
 */
 
-extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
+extern int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op);
 
 /* s3c2410_dma_setflags
  *
  * set the channel's flags to a given state
 */
 
-extern int s3c2410_dma_setflags(unsigned int channel,
+extern int s3c2410_dma_setflags(enum dma_ch channel,
                                 unsigned int flags);
 
 /* s3c2410_dma_free
@@ -86,7 +87,7 @@ extern int s3c2410_dma_setflags(unsigned int channel,
  * free the dma channel (will also abort any outstanding operations)
 */
 
-extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
+extern int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *);
 
 /* s3c2410_dma_enqueue
  *
@@ -95,7 +96,7 @@ extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
  * drained before the buffer is given to the DMA system.
 */
 
-extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
+extern int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
                                dma_addr_t data, int size);
 
 /* s3c2410_dma_config
@@ -103,14 +104,14 @@ extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
  * configure the dma channel
 */
 
-extern int s3c2410_dma_config(unsigned int channel, int xferunit);
+extern int s3c2410_dma_config(enum dma_ch channel, int xferunit);
 
 /* s3c2410_dma_devconfig
  *
  * configure the device we're talking to
 */
 
-extern int s3c2410_dma_devconfig(unsigned int channel,
+extern int s3c2410_dma_devconfig(enum dma_ch channel,
                 enum s3c2410_dmasrc source, unsigned long devaddr);
 
 /* s3c2410_dma_getposition
@@ -118,10 +119,10 @@ extern int s3c2410_dma_devconfig(unsigned int channel,
  * get the position that the dma transfer is currently at
 */
 
-extern int s3c2410_dma_getposition(unsigned int channel,
+extern int s3c2410_dma_getposition(enum dma_ch channel,
                                    dma_addr_t *src, dma_addr_t *dest);
 
-extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
-extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
+extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
+extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
 
 
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 0ffe34a21554..4c16fa3621bb 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo {
  * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
  * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
  * @high_speed: If the controller supports HIGH_SPEED_EN bit
+ * @tx_st_done: Depends on tx fifo_lvl field
  */
 struct s3c64xx_spi_info {
         int src_clk_nr;
@@ -53,6 +54,7 @@ struct s3c64xx_spi_info {
         int fifo_lvl_mask;
         int rx_lvl_offset;
         int high_speed;
+        int tx_st_done;
 };
 
 /**
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 32582c0958e3..657405c481d0 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -54,8 +54,15 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
 
         gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
                                     handle_level_irq);
+
+        if (!gc) {
+                pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
+                       __func__, uirq->base_irq);
+                return;
+        }
+
         ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_ack = irq_gc_ack_set_bit;
         ct->chip.irq_mask = irq_gc_mask_set_bit;
         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
         ct->regs.ack = S3C64XX_UINTP;
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index a607546ddbd0..f714d060370d 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -54,6 +54,13 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
 
         s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
                                          S3C64XX_TINT_CSTAT, handle_level_irq);
+
+        if (!s3c_tgc) {
+                pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
+                       __func__, timer_irq);
+                return;
+        }
+
         ct = s3c_tgc->chip_types;
         ct->chip.irq_mask = irq_gc_mask_clr_bit;
         ct->chip.irq_unmask = irq_gc_mask_set_bit;
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index 6fa474cb398e..67dd00381ea6 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -916,7 +916,7 @@ static struct dentry *clk_debugfs_root;
 static int clk_debugfs_register_one(struct clk *c)
 {
         int err;
-        struct dentry *d, *child;
+        struct dentry *d;
         struct clk *pa = c->pclk;
         char s[255];
         char *p = s;
@@ -951,10 +951,7 @@ static int clk_debugfs_register_one(struct clk *c)
         return 0;
 
 err_out:
-        d = c->dent;
-        list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
-                debugfs_remove(child);
-        debugfs_remove(c->dent);
+        debugfs_remove_recursive(c->dent);
         return err;
 }
 
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index d619b17c4413..c7476295de80 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -953,6 +953,16 @@ config BFIN_GPTIMERS
           To compile this driver as a module, choose M here: the module
           will be called gptimers.
 
+config HAVE_PWM
+        tristate "Enable PWM API support"
+        depends on BFIN_GPTIMERS
+        help
+          Enable support for the Pulse Width Modulation framework (as
+          found in linux/pwm.h).
+
+          To compile this driver as a module, choose M here: the module
+          will be called pwm.
+
 choice
         prompt "Uncached DMA region"
         default DMA_UNCACHED_1M
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 1c0a82a10591..d7ff2aee3fbc 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -58,13 +58,13 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=m
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 9e7c5379d3ff..7a075eaf6041 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,5 +1,48 @@
 include include/asm-generic/Kbuild.asm
 
+generic-y += auxvec.h
+generic-y += bitsperlong.h
+generic-y += bugs.h
+generic-y += cputime.h
+generic-y += current.h
+generic-y += device.h
+generic-y += div64.h
+generic-y += emergency-restart.h
+generic-y += errno.h
+generic-y += fb.h
+generic-y += futex.h
+generic-y += hw_irq.h
+generic-y += ioctl.h
+generic-y += ipcbuf.h
+generic-y += irq_regs.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += local64.h
+generic-y += local.h
+generic-y += mman.h
+generic-y += msgbuf.h
+generic-y += param.h
+generic-y += percpu.h
+generic-y += pgalloc.h
+generic-y += resource.h
+generic-y += scatterlist.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += setup.h
+generic-y += shmbuf.h
+generic-y += shmparam.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += statfs.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += topology.h
+generic-y += types.h
+generic-y += ucontext.h
+generic-y += unaligned.h
+generic-y += user.h
+generic-y += xor.h
+
 header-y += bfin_sport.h
 header-y += cachectl.h
 header-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index e48508957160..4c707dbe1ff9 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef __ARCH_BLACKFIN_ATOMIC__
 #define __ARCH_BLACKFIN_ATOMIC__
@@ -76,11 +76,6 @@ static inline void atomic_set_mask(int mask, atomic_t *v)
         __raw_atomic_set_asm(&v->counter, mask);
 }
 
-static inline int atomic_test_mask(int mask, atomic_t *v)
-{
-        return __raw_atomic_test_asm(&v->counter, mask);
-}
-
 /* Atomic operations are already serializing */
 #define smp_mb__before_atomic_dec()    barrier()
 #define smp_mb__after_atomic_dec() barrier()
diff --git a/arch/blackfin/include/asm/auxvec.h b/arch/blackfin/include/asm/auxvec.h
deleted file mode 100644
index 41fa68b71287..000000000000
--- a/arch/blackfin/include/asm/auxvec.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/auxvec.h>
diff --git a/arch/blackfin/include/asm/bitsperlong.h b/arch/blackfin/include/asm/bitsperlong.h
deleted file mode 100644
index 6dc0bb0c13b2..000000000000
--- a/arch/blackfin/include/asm/bitsperlong.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index eb7c1441d8f9..0928700b6bc4 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -1,9 +1,9 @@
 /*
  * Common header file for Blackfin family of processors.
  *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _BLACKFIN_H_
diff --git a/arch/blackfin/include/asm/bugs.h b/arch/blackfin/include/asm/bugs.h
deleted file mode 100644
index 61791e1ad9f5..000000000000
--- a/arch/blackfin/include/asm/bugs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/bugs.h>
diff --git a/arch/blackfin/include/asm/cputime.h b/arch/blackfin/include/asm/cputime.h
deleted file mode 100644
index 6d68ad7e0ea3..000000000000
--- a/arch/blackfin/include/asm/cputime.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/cputime.h>
diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h
deleted file mode 100644
index 4c51401b5537..000000000000
--- a/arch/blackfin/include/asm/current.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/current.h>
diff --git a/arch/blackfin/include/asm/device.h b/arch/blackfin/include/asm/device.h
deleted file mode 100644
index f0a4c256403b..000000000000
--- a/arch/blackfin/include/asm/device.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/device.h>
diff --git a/arch/blackfin/include/asm/div64.h b/arch/blackfin/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/blackfin/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index edf2a2ad5183..c4ec959dad78 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -117,7 +117,6 @@
 #ifndef __ASSEMBLY__
 
 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void do_hibernate(int wakeup);
 void set_dram_srfs(void);
@@ -134,32 +133,6 @@ struct bfin_dpmc_platform_data {
         unsigned short vr_settling_time; /* in us */
 };
 
-#else
-
-#define PM_PUSH(x) \
-        R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
-        [--SP] =  R0;\
-
-#define PM_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
-
-#define PM_SYS_PUSH(x) \
-        R0 = [P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-
-#define PM_SYS_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - PLL_CTL)] = R0;\
-
-#define PM_SYS_PUSH16(x) \
-        R0 = w[P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-
-#define PM_SYS_POP16(x) \
-        R0 = [SP++];\
-        w[P0 + (x - PLL_CTL)] = R0;\
-
 #endif
 
 #endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/emergency-restart.h b/arch/blackfin/include/asm/emergency-restart.h
deleted file mode 100644
index 3711bd9d50bd..000000000000
--- a/arch/blackfin/include/asm/emergency-restart.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/emergency-restart.h>
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
deleted file mode 100644
index 4c82b503d92f..000000000000
--- a/arch/blackfin/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/blackfin/include/asm/fb.h b/arch/blackfin/include/asm/fb.h
deleted file mode 100644
index 3a4988e8df45..000000000000
--- a/arch/blackfin/include/asm/fb.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/fb.h>
diff --git a/arch/blackfin/include/asm/futex.h b/arch/blackfin/include/asm/futex.h
deleted file mode 100644
index 0b745828f42b..000000000000
--- a/arch/blackfin/include/asm/futex.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/futex.h>
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 1ef8417f5d27..5a25856381ff 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -16,58 +16,13 @@
 
 #include <mach/gpio.h>
 
-#define GPIO_0  0
-#define GPIO_1  1
-#define GPIO_2  2
-#define GPIO_3  3
-#define GPIO_4  4
-#define GPIO_5  5
-#define GPIO_6  6
-#define GPIO_7  7
-#define GPIO_8  8
-#define GPIO_9  9
-#define GPIO_10 10
-#define GPIO_11 11
-#define GPIO_12 12
-#define GPIO_13 13
-#define GPIO_14 14
-#define GPIO_15 15
-#define GPIO_16 16
-#define GPIO_17 17
-#define GPIO_18 18
-#define GPIO_19 19
-#define GPIO_20 20
-#define GPIO_21 21
-#define GPIO_22 22
-#define GPIO_23 23
-#define GPIO_24 24
-#define GPIO_25 25
-#define GPIO_26 26
-#define GPIO_27 27
-#define GPIO_28 28
-#define GPIO_29 29
-#define GPIO_30 30
-#define GPIO_31 31
-#define GPIO_32 32
-#define GPIO_33 33
-#define GPIO_34 34
-#define GPIO_35 35
-#define GPIO_36 36
-#define GPIO_37 37
-#define GPIO_38 38
-#define GPIO_39 39
-#define GPIO_40 40
-#define GPIO_41 41
-#define GPIO_42 42
-#define GPIO_43 43
-#define GPIO_44 44
-#define GPIO_45 45
-#define GPIO_46 46
-#define GPIO_47 47
-
 #define PERIPHERAL_USAGE 1
 #define GPIO_USAGE 0
 
+#ifndef BFIN_GPIO_PINT
+# define BFIN_GPIO_PINT 0
+#endif
+
 #ifndef __ASSEMBLY__
 
 #include <linux/compiler.h>
@@ -89,7 +44,7 @@
 * MODIFICATION HISTORY :
 **************************************************************/
 
-#ifndef CONFIG_BF54x
+#if !BFIN_GPIO_PINT
 void set_gpio_dir(unsigned, unsigned short);
 void set_gpio_inen(unsigned, unsigned short);
 void set_gpio_polar(unsigned, unsigned short);
@@ -164,6 +119,10 @@ struct gpio_port_t {
 #ifdef BFIN_SPECIAL_GPIO_BANKS
 void bfin_special_gpio_free(unsigned gpio);
 int bfin_special_gpio_request(unsigned gpio, const char *label);
+# ifdef CONFIG_PM
+void bfin_special_gpio_pm_hibernate_restore(void);
+void bfin_special_gpio_pm_hibernate_suspend(void);
+# endif
 #endif
 
 #ifdef CONFIG_PM
@@ -182,7 +141,7 @@ static inline void bfin_pm_standby_restore(void)
 void bfin_gpio_pm_hibernate_restore(void);
 void bfin_gpio_pm_hibernate_suspend(void);
 
-#ifndef CONFIG_BF54x
+# if !BFIN_GPIO_PINT
 int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
 
 struct gpio_port_s {
@@ -199,8 +158,9 @@ struct gpio_port_s {
         unsigned short reserved;
         unsigned short mux;
 };
-#endif /*CONFIG_BF54x*/
+# endif
 #endif /*CONFIG_PM*/
+
 /***********************************************************
 *
 * FUNCTIONS: Blackfin GPIO Driver
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 38657dac1235..38bddcb190c8 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -193,6 +193,16 @@ uint16_t get_enabled_gptimers(void);
 uint32_t get_gptimer_status(unsigned int group);
 void     set_gptimer_status(unsigned int group, uint32_t value);
 
+static inline void enable_gptimer(unsigned int timer_id)
+{
+        enable_gptimers(1 << timer_id);
+}
+
+static inline void disable_gptimer(unsigned int timer_id)
+{
+        disable_gptimers(1 << timer_id);
+}
+
 /*
  * All Blackfin system MMRs are padded to 32bits even if the register
  * itself is only 16bits.  So use a helper macro to streamline this.
@@ -209,6 +219,15 @@ struct bfin_gptimer_regs {
         u32 width;
 };
 
+/*
+ * bfin group timer registers layout
+ */
+struct bfin_gptimer_group_regs {
+        __BFP(enable);
+        __BFP(disable);
+        u32 status;
+};
+
 #undef __BFP
 
 #endif
diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h
deleted file mode 100644
index 1f5ef7da0045..000000000000
--- a/arch/blackfin/include/asm/hw_irq.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hw_irq.h>
diff --git a/arch/blackfin/include/asm/ioctl.h b/arch/blackfin/include/asm/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/arch/blackfin/include/asm/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/arch/blackfin/include/asm/ipcbuf.h b/arch/blackfin/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/blackfin/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/blackfin/include/asm/irq_regs.h b/arch/blackfin/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/blackfin/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index b4bbb75a9e15..43eb4749de3d 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -18,12 +18,12 @@
 extern unsigned long bfin_irq_flags;
 #endif
 
-static inline void bfin_sti(unsigned long flags)
+static inline notrace void bfin_sti(unsigned long flags)
 {
         asm volatile("sti %0;" : : "d" (flags));
 }
 
-static inline unsigned long bfin_cli(void)
+static inline notrace unsigned long bfin_cli(void)
 {
         unsigned long flags;
         asm volatile("cli %0;" : "=d" (flags));
@@ -40,22 +40,22 @@ static inline unsigned long bfin_cli(void)
 /*
  * Hard, untraced CPU interrupt flag manipulation and access.
  */
-static inline void __hard_local_irq_disable(void)
+static inline notrace void __hard_local_irq_disable(void)
 {
         bfin_cli();
 }
 
-static inline void __hard_local_irq_enable(void)
+static inline notrace void __hard_local_irq_enable(void)
 {
         bfin_sti(bfin_irq_flags);
 }
 
-static inline unsigned long hard_local_save_flags(void)
+static inline notrace unsigned long hard_local_save_flags(void)
 {
         return bfin_read_IMASK();
 }
 
-static inline unsigned long __hard_local_irq_save(void)
+static inline notrace unsigned long __hard_local_irq_save(void)
 {
         unsigned long flags;
         flags = bfin_cli();
@@ -65,18 +65,18 @@ static inline unsigned long __hard_local_irq_save(void)
         return flags;
 }
 
-static inline int hard_irqs_disabled_flags(unsigned long flags)
+static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
 {
         return (flags & ~0x3f) == 0;
 }
 
-static inline int hard_irqs_disabled(void)
+static inline notrace int hard_irqs_disabled(void)
 {
         unsigned long flags = hard_local_save_flags();
         return hard_irqs_disabled_flags(flags);
 }
 
-static inline void __hard_local_irq_restore(unsigned long flags)
+static inline notrace void __hard_local_irq_restore(unsigned long flags)
 {
         if (!hard_irqs_disabled_flags(flags))
                 __hard_local_irq_enable();
@@ -113,31 +113,31 @@ void ipipe_check_context(struct ipipe_domain *ipd);
 /*
  * Interrupt pipe interface to linux/irqflags.h.
  */
-static inline void arch_local_irq_disable(void)
+static inline notrace void arch_local_irq_disable(void)
 {
         __check_irqop_context();
         __ipipe_stall_root();
         barrier();
 }
 
-static inline void arch_local_irq_enable(void)
+static inline notrace void arch_local_irq_enable(void)
 {
         barrier();
         __check_irqop_context();
         __ipipe_unstall_root();
 }
 
-static inline unsigned long arch_local_save_flags(void)
+static inline notrace unsigned long arch_local_save_flags(void)
 {
         return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
 }
 
-static inline int arch_irqs_disabled_flags(unsigned long flags)
+static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
 {
         return flags == bfin_no_irqs;
 }
 
-static inline unsigned long arch_local_irq_save(void)
+static inline notrace unsigned long arch_local_irq_save(void)
 {
         unsigned long flags;
 
@@ -148,13 +148,13 @@ static inline unsigned long arch_local_irq_save(void)
         return flags;
 }
 
-static inline void arch_local_irq_restore(unsigned long flags)
+static inline notrace void arch_local_irq_restore(unsigned long flags)
 {
         __check_irqop_context();
         __ipipe_restore_root(flags == bfin_no_irqs);
 }
 
-static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
+static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
 {
         /*
          * Merge virtual and real interrupt mask bits into a single
@@ -163,7 +163,7 @@ static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
         return (real & ~(1 << 31)) | ((virt != 0) << 31);
 }
 
-static inline int arch_demangle_irq_bits(unsigned long *x)
+static inline notrace int arch_demangle_irq_bits(unsigned long *x)
 {
         int virt = (*x & (1 << 31)) != 0;
         *x &= ~(1L << 31);
@@ -174,7 +174,7 @@ static inline int arch_demangle_irq_bits(unsigned long *x)
  * Interface to various arch routines that may be traced.
  */
 #ifdef CONFIG_IPIPE_TRACE_IRQSOFF
-static inline void hard_local_irq_disable(void)
+static inline notrace void hard_local_irq_disable(void)
 {
         if (!hard_irqs_disabled()) {
                 __hard_local_irq_disable();
@@ -182,7 +182,7 @@ static inline void hard_local_irq_disable(void)
         }
 }
 
-static inline void hard_local_irq_enable(void)
+static inline notrace void hard_local_irq_enable(void)
 {
         if (hard_irqs_disabled()) {
                 ipipe_trace_end(0x80000000);
@@ -190,7 +190,7 @@ static inline void hard_local_irq_enable(void)
         }
 }
 
-static inline unsigned long hard_local_irq_save(void)
+static inline notrace unsigned long hard_local_irq_save(void)
 {
         unsigned long flags = hard_local_save_flags();
         if (!hard_irqs_disabled_flags(flags)) {
@@ -200,7 +200,7 @@ static inline unsigned long hard_local_irq_save(void)
         return flags;
 }
 
-static inline void hard_local_irq_restore(unsigned long flags)
+static inline notrace void hard_local_irq_restore(unsigned long flags)
 {
         if (!hard_irqs_disabled_flags(flags)) {
                 ipipe_trace_end(0x80000001);
diff --git a/arch/blackfin/include/asm/kdebug.h b/arch/blackfin/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/blackfin/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h
deleted file mode 100644
index 3575c64af42a..000000000000
--- a/arch/blackfin/include/asm/kmap_types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kmap_types.h>
diff --git a/arch/blackfin/include/asm/local.h b/arch/blackfin/include/asm/local.h
deleted file mode 100644
index c11c530f74d0..000000000000
--- a/arch/blackfin/include/asm/local.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local.h>
diff --git a/arch/blackfin/include/asm/local64.h b/arch/blackfin/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/blackfin/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/blackfin/include/asm/mman.h b/arch/blackfin/include/asm/mman.h
deleted file mode 100644
index 8eebf89f5ab1..000000000000
--- a/arch/blackfin/include/asm/mman.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/mman.h>
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
index 4282b169ead9..ed5689b82c9f 100644
--- a/arch/blackfin/include/asm/module.h
+++ b/arch/blackfin/include/asm/module.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef _ASM_BFIN_MODULE_H
 #define _ASM_BFIN_MODULE_H
diff --git a/arch/blackfin/include/asm/msgbuf.h b/arch/blackfin/include/asm/msgbuf.h
deleted file mode 100644
index 809134c644a6..000000000000
--- a/arch/blackfin/include/asm/msgbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/msgbuf.h>
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h
index f726e3a80ad0..ff6101aa2c71 100644
--- a/arch/blackfin/include/asm/mutex.h
+++ b/arch/blackfin/include/asm/mutex.h
@@ -1,76 +1 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_MUTEX_H
-#define _ASM_MUTEX_H
-
-#ifndef CONFIG_SMP
-#include <asm-generic/mutex.h>
-#else
-
-static inline void
-__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-        if (unlikely(atomic_dec_return(count) < 0))
-                fail_fn(count);
-        else
-                smp_mb();
-}
-
-static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-        if (unlikely(atomic_dec_return(count) < 0))
-                return fail_fn(count);
-        else {
-                smp_mb();
-                return 0;
-        }
-}
-
-static inline void
-__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-        smp_mb();
-        if (unlikely(atomic_inc_return(count) <= 0))
-                fail_fn(count);
-}
-
-#define __mutex_slowpath_needs_to_unlock()              1
-
-static inline int
-__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-        /*
-         * We have two variants here. The cmpxchg based one is the best one
-         * because it never induce a false contention state.  It is included
-         * here because architectures using the inc/dec algorithms over the
-         * xchg ones are much more likely to support cmpxchg natively.
-         *
-         * If not we fall back to the spinlock based variant - that is
-         * just as efficient (and simpler) as a 'destructive' probing of
-         * the mutex state would be.
-         */
-#ifdef __HAVE_ARCH_CMPXCHG
-        if (likely(atomic_cmpxchg(count, 1, 0) == 1)) {
-                smp_mb();
-                return 1;
-        }
-        return 0;
-#else
-        return fail_fn(count);
-#endif
-}
-
-#endif
-
-#endif
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index d0ce975bcd48..7202404966f6 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef _BLACKFIN_PAGE_H
 #define _BLACKFIN_PAGE_H
diff --git a/arch/blackfin/include/asm/param.h b/arch/blackfin/include/asm/param.h
deleted file mode 100644
index 965d45427975..000000000000
--- a/arch/blackfin/include/asm/param.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/param.h>
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
index d49bb261d9b7..28c2498c9c98 100644
--- a/arch/blackfin/include/asm/pda.h
+++ b/arch/blackfin/include/asm/pda.h
@@ -54,6 +54,16 @@ struct blackfin_pda {			/* Per-processor Data Area */
 #endif
 };
 
+struct blackfin_initial_pda {
+        void *retx;
+#ifdef CONFIG_DEBUG_DOUBLEFAULT
+        void *dcplb_doublefault_addr;
+        void *icplb_doublefault_addr;
+        void *retx_doublefault;
+        unsigned seqstat_doublefault;
+#endif
+};
+
 extern struct blackfin_pda cpu_pda[];
 
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h
deleted file mode 100644
index 06a959d67234..000000000000
--- a/arch/blackfin/include/asm/percpu.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/percpu.h>
diff --git a/arch/blackfin/include/asm/pgalloc.h b/arch/blackfin/include/asm/pgalloc.h
deleted file mode 100644
index f261cb7dda06..000000000000
--- a/arch/blackfin/include/asm/pgalloc.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/pgalloc.h>
diff --git a/arch/blackfin/include/asm/resource.h b/arch/blackfin/include/asm/resource.h
deleted file mode 100644
index 04bc4db8921b..000000000000
--- a/arch/blackfin/include/asm/resource.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/resource.h>
diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h
deleted file mode 100644
index d177a1588958..000000000000
--- a/arch/blackfin/include/asm/scatterlist.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BLACKFIN_SCATTERLIST_H
-#define _BLACKFIN_SCATTERLIST_H
-
-#include <asm-generic/scatterlist.h>
-
-#endif                          /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 14a3e66d9167..fbd408475725 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef _BLACKFIN_SECTIONS_H
 #define _BLACKFIN_SECTIONS_H
diff --git a/arch/blackfin/include/asm/sembuf.h b/arch/blackfin/include/asm/sembuf.h
deleted file mode 100644
index 7673b83cfef7..000000000000
--- a/arch/blackfin/include/asm/sembuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sembuf.h>
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
deleted file mode 100644
index a0cb0caff152..000000000000
--- a/arch/blackfin/include/asm/serial.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/serial.h>
diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h
deleted file mode 100644
index 552df83f1a49..000000000000
--- a/arch/blackfin/include/asm/setup.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/setup.h>
diff --git a/arch/blackfin/include/asm/shmbuf.h b/arch/blackfin/include/asm/shmbuf.h
deleted file mode 100644
index 83c05fc2de38..000000000000
--- a/arch/blackfin/include/asm/shmbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/shmbuf.h>
diff --git a/arch/blackfin/include/asm/shmparam.h b/arch/blackfin/include/asm/shmparam.h
deleted file mode 100644
index 93f30deb95d0..000000000000
--- a/arch/blackfin/include/asm/shmparam.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/shmparam.h>
diff --git a/arch/blackfin/include/asm/sigcontext.h b/arch/blackfin/include/asm/sigcontext.h
index ce4081a4d815..906bdc1f5fda 100644
--- a/arch/blackfin/include/asm/sigcontext.h
+++ b/arch/blackfin/include/asm/sigcontext.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef _ASM_BLACKFIN_SIGCONTEXT_H
 #define _ASM_BLACKFIN_SIGCONTEXT_H
diff --git a/arch/blackfin/include/asm/socket.h b/arch/blackfin/include/asm/socket.h
deleted file mode 100644
index 6b71384b9d8b..000000000000
--- a/arch/blackfin/include/asm/socket.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/socket.h>
diff --git a/arch/blackfin/include/asm/sockios.h b/arch/blackfin/include/asm/sockios.h
deleted file mode 100644
index def6d4746ee7..000000000000
--- a/arch/blackfin/include/asm/sockios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sockios.h>
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1f286e71c21f..2336093fca23 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef __BFIN_SPINLOCK_H
 #define __BFIN_SPINLOCK_H
diff --git a/arch/blackfin/include/asm/statfs.h b/arch/blackfin/include/asm/statfs.h
deleted file mode 100644
index 0b91fe198c20..000000000000
--- a/arch/blackfin/include/asm/statfs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/statfs.h>
diff --git a/arch/blackfin/include/asm/termbits.h b/arch/blackfin/include/asm/termbits.h
deleted file mode 100644
index 3935b106de79..000000000000
--- a/arch/blackfin/include/asm/termbits.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/termbits.h>
diff --git a/arch/blackfin/include/asm/termios.h b/arch/blackfin/include/asm/termios.h
deleted file mode 100644
index 280d78a9d966..000000000000
--- a/arch/blackfin/include/asm/termios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/termios.h>
diff --git a/arch/blackfin/include/asm/topology.h b/arch/blackfin/include/asm/topology.h
deleted file mode 100644
index 5428f333a02c..000000000000
--- a/arch/blackfin/include/asm/topology.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/topology.h>
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
deleted file mode 100644
index b9e79bc580dd..000000000000
--- a/arch/blackfin/include/asm/types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/types.h>
diff --git a/arch/blackfin/include/asm/ucontext.h b/arch/blackfin/include/asm/ucontext.h
deleted file mode 100644
index 9bc07b9f30fb..000000000000
--- a/arch/blackfin/include/asm/ucontext.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ucontext.h>
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
deleted file mode 100644
index 6cecbbb2111f..000000000000
--- a/arch/blackfin/include/asm/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/unaligned.h>
diff --git a/arch/blackfin/include/asm/user.h b/arch/blackfin/include/asm/user.h
deleted file mode 100644
index 4792a60831e4..000000000000
--- a/arch/blackfin/include/asm/user.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/user.h>
diff --git a/arch/blackfin/include/asm/xor.h b/arch/blackfin/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/blackfin/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index d550b24d9e9b..b7bdc42fe1a3 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_FUNCTION_TRACER)        += ftrace-entry.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)  += ftrace.o
 CFLAGS_REMOVE_ftrace.o = -pg
 
+obj-$(CONFIG_HAVE_PWM)               += pwm.o
 obj-$(CONFIG_IPIPE)                  += ipipe.o
 obj-$(CONFIG_BFIN_GPTIMERS)          += gptimers.o
 obj-$(CONFIG_CPLB_INFO)              += cplbinfo.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index bd32c09b9349..17e35465a416 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -138,6 +138,16 @@ int main(void)
         DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault));
         DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault));
 #endif
+
+        /* PDA initial management */
+        DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx));
+#ifdef CONFIG_DEBUG_DOUBLEFAULT
+        DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr));
+        DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr));
+        DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault));
+        DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault));
+#endif
+
 #ifdef CONFIG_SMP
         /* Inter-core lock (in L2 SRAM) */
         DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index bcf8cf6fe412..02796b88443d 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -118,6 +118,9 @@ static struct str_ident {
 
 #if defined(CONFIG_PM)
 static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
+# ifdef BF538_FAMILY
+static unsigned short port_fer_saved[3];
+# endif
 #endif
 
 static void gpio_error(unsigned gpio)
@@ -604,6 +607,11 @@ void bfin_gpio_pm_hibernate_suspend(void)
 {
         int i, bank;
 
+#ifdef BF538_FAMILY
+        for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
+                port_fer_saved[i] = *port_fer[i];
+#endif
+
         for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                 bank = gpio_bank(i);
 
@@ -625,6 +633,10 @@ void bfin_gpio_pm_hibernate_suspend(void)
                 gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
         }
 
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+        bfin_special_gpio_pm_hibernate_suspend();
+#endif
+
         AWA_DUMMY_READ(maska);
 }
 
@@ -632,6 +644,11 @@ void bfin_gpio_pm_hibernate_restore(void)
 {
         int i, bank;
 
+#ifdef BF538_FAMILY
+        for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
+                *port_fer[i] = port_fer_saved[i];
+#endif
+
         for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                 bank = gpio_bank(i);
 
@@ -653,6 +670,11 @@ void bfin_gpio_pm_hibernate_restore(void)
                 gpio_array[bank]->both  = gpio_bank_saved[bank].both;
                 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
         }
+
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+        bfin_special_gpio_pm_hibernate_restore();
+#endif
+
         AWA_DUMMY_READ(maska);
 }
 
@@ -691,9 +713,9 @@ void bfin_gpio_pm_hibernate_restore(void)
                 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
                 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
                 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
-                gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
                 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
-                                                | gpio_bank_saved[bank].dir;
+                                                & gpio_bank_saved[bank].dir;
+                gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
         }
 }
 #endif
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index fce4807ceef9..92f664826281 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -27,7 +27,7 @@
 #define PORT_MUX BFIN_PORT_MUX
 #endif
 
-#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
+#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
 #define d(name, bits, addr)         _d(name, bits, addr, S_IRUSR|S_IWUSR)
 #define d_RO(name, bits, addr)      _d(name, bits, addr, S_IRUSR)
 #define d_WO(name, bits, addr)      _d(name, bits, addr, S_IWUSR)
@@ -223,7 +223,8 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
         __DMA(CURR_DESC_PTR, curr_desc_ptr);
         __DMA(CURR_ADDR, curr_addr);
         __DMA(IRQ_STATUS, irq_status);
-        __DMA(PERIPHERAL_MAP, peripheral_map);
+        if (strcmp(pfx, "IMDMA") != 0)
+                __DMA(PERIPHERAL_MAP, peripheral_map);
         __DMA(CURR_X_COUNT, curr_x_count);
         __DMA(CURR_Y_COUNT, curr_y_count);
 }
@@ -277,6 +278,32 @@ bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
 }
 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
 
+#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
+#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf;
+
+        if (num == -1) {
+                _buf = buf + sprintf(buf, "TIMER_");
+                __GPTIMER_GROUP(ENABLE, enable);
+                __GPTIMER_GROUP(DISABLE, disable);
+                __GPTIMER_GROUP(STATUS, status);
+        } else {
+                /* These MMRs are a bit odd as the group # is a suffix */
+                _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
+                d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
+
+                _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
+                d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
+
+                _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
+                d(buf, 32, base + GPTIMER_GROUP_OFF(status));
+        }
+}
+#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
+
 /*
  * Handshake MDMA
  */
@@ -296,6 +323,29 @@ bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
 
 /*
+ * Peripheral Interrupts (PINT/GPIO)
+ */
+#ifdef PINT0_MASK_SET
+#define __PINT(uname, lname) __REGS(pint, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
+        __PINT(MASK_SET, mask_set);
+        __PINT(MASK_CLEAR, mask_clear);
+        __PINT(REQUEST, request);
+        __PINT(ASSIGN, assign);
+        __PINT(EDGE_SET, edge_set);
+        __PINT(EDGE_CLEAR, edge_clear);
+        __PINT(INVERT_SET, invert_set);
+        __PINT(INVERT_CLEAR, invert_clear);
+        __PINT(PINSTATE, pinstate);
+        __PINT(LATCH, latch);
+}
+#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
+#endif
+
+/*
  * Port/GPIO
  */
 #define bfin_gpio_regs gpio_port_t
@@ -747,7 +797,7 @@ static int __init bfin_debug_mmrs_init(void)
 #endif
 
         parent = debugfs_create_dir("dmac", top);
-#ifdef DMA_TC_CNT
+#ifdef DMAC_TC_CNT
         D16(DMAC_TC_CNT);
         D16(DMAC_TC_PER);
 #endif
@@ -1005,29 +1055,19 @@ static int __init bfin_debug_mmrs_init(void)
 #endif
 
         parent = debugfs_create_dir("gptimer", top);
-#ifdef TIMER_DISABLE
-        D16(TIMER_DISABLE);
-        D16(TIMER_ENABLE);
-        D32(TIMER_STATUS);
+#ifdef TIMER_ENABLE
+        GPTIMER_GROUP(TIMER_ENABLE, -1);
 #endif
-#ifdef TIMER_DISABLE0
-        D16(TIMER_DISABLE0);
-        D16(TIMER_ENABLE0);
-        D32(TIMER_STATUS0);
+#ifdef TIMER_ENABLE0
+        GPTIMER_GROUP(TIMER_ENABLE0, 0);
 #endif
-#ifdef TIMER_DISABLE1
-        D16(TIMER_DISABLE1);
-        D16(TIMER_ENABLE1);
-        D32(TIMER_STATUS1);
+#ifdef TIMER_ENABLE1
+        GPTIMER_GROUP(TIMER_ENABLE1, 1);
 #endif
         /* XXX: Should convert BF561 MMR names */
 #ifdef TMRS4_DISABLE
-        D16(TMRS4_DISABLE);
-        D16(TMRS4_ENABLE);
-        D32(TMRS4_STATUS);
-        D16(TMRS8_DISABLE);
-        D16(TMRS8_ENABLE);
-        D32(TMRS8_STATUS);
+        GPTIMER_GROUP(TMRS4_ENABLE, 0);
+        GPTIMER_GROUP(TMRS8_ENABLE, 1);
 #endif
         GPTIMER(0);
         GPTIMER(1);
@@ -1253,6 +1293,14 @@ static int __init bfin_debug_mmrs_init(void)
         D32(OTP_DATA3);
 #endif
 
+#ifdef PINT0_MASK_SET
+        parent = debugfs_create_dir("pint", top);
+        PINT(0);
+        PINT(1);
+        PINT(2);
+        PINT(3);
+#endif
+
 #ifdef PIXC_CTL
         parent = debugfs_create_dir("pixc", top);
         D16(PIXC_CTL);
@@ -1816,7 +1864,6 @@ static int __init bfin_debug_mmrs_init(void)
         {
                 int num;
                 unsigned long base;
-                char *_buf, buf[32];
 
                 base = PORTA_FER;
                 for (num = 0; num < 10; ++num) {
@@ -1824,24 +1871,6 @@ static int __init bfin_debug_mmrs_init(void)
                         base += sizeof(struct bfin_gpio_regs);
                 }
 
-#define __PINT(uname, lname) __REGS(pint, #uname, lname)
-                parent = debugfs_create_dir("pint", top);
-                base = PINT0_MASK_SET;
-                for (num = 0; num < 4; ++num) {
-                        _buf = REGS_STR_PFX(buf, PINT, num);
-                        __PINT(MASK_SET, mask_set);
-                        __PINT(MASK_CLEAR, mask_clear);
-                        __PINT(IRQ, irq);
-                        __PINT(ASSIGN, assign);
-                        __PINT(EDGE_SET, edge_set);
-                        __PINT(EDGE_CLEAR, edge_clear);
-                        __PINT(INVERT_SET, invert_set);
-                        __PINT(INVERT_CLEAR, invert_clear);
-                        __PINT(PINSTATE, pinstate);
-                        __PINT(LATCH, latch);
-                        base += sizeof(struct bfin_pint_regs);
-                }
-
         }
 #endif  /* BF54x */
 
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 8b81dc04488a..06459f4bf43a 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -25,49 +25,33 @@
 
 #define BFIN_TIMER_NUM_GROUP  (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
 
-typedef struct {
-        uint16_t config;
-        uint16_t __pad;
-        uint32_t counter;
-        uint32_t period;
-        uint32_t width;
-} GPTIMER_timer_regs;
-
-typedef struct {
-        uint16_t enable;
-        uint16_t __pad0;
-        uint16_t disable;
-        uint16_t __pad1;
-        uint32_t status;
-} GPTIMER_group_regs;
-
-static volatile GPTIMER_timer_regs *const timer_regs[MAX_BLACKFIN_GPTIMERS] =
+static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
 {
-        (GPTIMER_timer_regs *)TIMER0_CONFIG,
-        (GPTIMER_timer_regs *)TIMER1_CONFIG,
-        (GPTIMER_timer_regs *)TIMER2_CONFIG,
+        (void *)TIMER0_CONFIG,
+        (void *)TIMER1_CONFIG,
+        (void *)TIMER2_CONFIG,
 #if (MAX_BLACKFIN_GPTIMERS > 3)
-        (GPTIMER_timer_regs *)TIMER3_CONFIG,
-        (GPTIMER_timer_regs *)TIMER4_CONFIG,
-        (GPTIMER_timer_regs *)TIMER5_CONFIG,
-        (GPTIMER_timer_regs *)TIMER6_CONFIG,
-        (GPTIMER_timer_regs *)TIMER7_CONFIG,
+        (void *)TIMER3_CONFIG,
+        (void *)TIMER4_CONFIG,
+        (void *)TIMER5_CONFIG,
+        (void *)TIMER6_CONFIG,
+        (void *)TIMER7_CONFIG,
 # if (MAX_BLACKFIN_GPTIMERS > 8)
-        (GPTIMER_timer_regs *)TIMER8_CONFIG,
-        (GPTIMER_timer_regs *)TIMER9_CONFIG,
-        (GPTIMER_timer_regs *)TIMER10_CONFIG,
+        (void *)TIMER8_CONFIG,
+        (void *)TIMER9_CONFIG,
+        (void *)TIMER10_CONFIG,
 #  if (MAX_BLACKFIN_GPTIMERS > 11)
-        (GPTIMER_timer_regs *)TIMER11_CONFIG,
+        (void *)TIMER11_CONFIG,
 #  endif
 # endif
 #endif
 };
 
-static volatile GPTIMER_group_regs *const group_regs[BFIN_TIMER_NUM_GROUP] =
+static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] =
 {
-        (GPTIMER_group_regs *)TIMER0_GROUP_REG,
+        (void *)TIMER0_GROUP_REG,
 #if (MAX_BLACKFIN_GPTIMERS > 8)
-        (GPTIMER_group_regs *)TIMER8_GROUP_REG,
+        (void *)TIMER8_GROUP_REG,
 #endif
 };
 
@@ -140,7 +124,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
 void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->width = value;
+        bfin_write(&timer_regs[timer_id]->width, value);
         SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_pwidth);
@@ -148,14 +132,14 @@ EXPORT_SYMBOL(set_gptimer_pwidth);
 uint32_t get_gptimer_pwidth(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->width;
+        return bfin_read(&timer_regs[timer_id]->width);
 }
 EXPORT_SYMBOL(get_gptimer_pwidth);
 
 void set_gptimer_period(unsigned int timer_id, uint32_t period)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->period = period;
+        bfin_write(&timer_regs[timer_id]->period, period);
         SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_period);
@@ -163,71 +147,76 @@ EXPORT_SYMBOL(set_gptimer_period);
 uint32_t get_gptimer_period(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->period;
+        return bfin_read(&timer_regs[timer_id]->period);
 }
 EXPORT_SYMBOL(get_gptimer_period);
 
 uint32_t get_gptimer_count(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->counter;
+        return bfin_read(&timer_regs[timer_id]->counter);
 }
 EXPORT_SYMBOL(get_gptimer_count);
 
 uint32_t get_gptimer_status(unsigned int group)
 {
         tassert(group < BFIN_TIMER_NUM_GROUP);
-        return group_regs[group]->status;
+        return bfin_read(&group_regs[group]->status);
 }
 EXPORT_SYMBOL(get_gptimer_status);
 
 void set_gptimer_status(unsigned int group, uint32_t value)
 {
         tassert(group < BFIN_TIMER_NUM_GROUP);
-        group_regs[group]->status = value;
+        bfin_write(&group_regs[group]->status, value);
         SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_status);
 
+static uint32_t read_gptimer_status(unsigned int timer_id)
+{
+        return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status);
+}
+
 int get_gptimer_intr(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]);
+        return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_intr);
 
 void clear_gptimer_intr(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id];
+        bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]);
 }
 EXPORT_SYMBOL(clear_gptimer_intr);
 
 int get_gptimer_over(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]);
+        return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_over);
 
 void clear_gptimer_over(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id];
+        bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]);
 }
 EXPORT_SYMBOL(clear_gptimer_over);
 
 int get_gptimer_run(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]);
+        return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_run);
 
 void set_gptimer_config(unsigned int timer_id, uint16_t config)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->config = config;
+        bfin_write(&timer_regs[timer_id]->config, config);
         SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_config);
@@ -235,7 +224,7 @@ EXPORT_SYMBOL(set_gptimer_config);
 uint16_t get_gptimer_config(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->config;
+        return bfin_read(&timer_regs[timer_id]->config);
 }
 EXPORT_SYMBOL(get_gptimer_config);
 
@@ -244,7 +233,7 @@ void enable_gptimers(uint16_t mask)
         int i;
         tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
         for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
-                group_regs[i]->enable = mask & 0xFF;
+                bfin_write(&group_regs[i]->enable, mask & 0xFF);
                 mask >>= 8;
         }
         SSYNC();
@@ -257,7 +246,7 @@ static void _disable_gptimers(uint16_t mask)
         uint16_t m = mask;
         tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
         for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
-                group_regs[i]->disable = m & 0xFF;
+                bfin_write(&group_regs[i]->disable, m & 0xFF);
                 m >>= 8;
         }
 }
@@ -268,7 +257,7 @@ void disable_gptimers(uint16_t mask)
         _disable_gptimers(mask);
         for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
                 if (mask & (1 << i))
-                        group_regs[BFIN_TIMER_OCTET(i)]->status = trun_mask[i];
+                        bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
         SSYNC();
 }
 EXPORT_SYMBOL(disable_gptimers);
@@ -283,7 +272,7 @@ EXPORT_SYMBOL(disable_gptimers_sync);
 void set_gptimer_pulse_hi(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->config |= TIMER_PULSE_HI;
+        bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI);
         SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_pulse_hi);
@@ -291,7 +280,7 @@ EXPORT_SYMBOL(set_gptimer_pulse_hi);
 void clear_gptimer_pulse_hi(unsigned int timer_id)
 {
         tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->config &= ~TIMER_PULSE_HI;
+        bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI);
         SSYNC();
 }
 EXPORT_SYMBOL(clear_gptimer_pulse_hi);
@@ -301,7 +290,7 @@ uint16_t get_enabled_gptimers(void)
         int i;
         uint16_t result = 0;
         for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i)
-                result |= (group_regs[i]->enable << (i << 3));
+                result |= (bfin_read(&group_regs[i]->enable) << (i << 3));
         return result;
 }
 EXPORT_SYMBOL(get_enabled_gptimers);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 6a660fa921b5..6a80a9e9fc4a 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -140,7 +140,6 @@ EXPORT_SYMBOL(kernel_thread);
  */
 void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
 {
-        set_fs(USER_DS);
         regs->pc = new_ip;
         if (current->mm)
                 regs->p5 = current->mm->start_data;
diff --git a/arch/blackfin/kernel/pwm.c b/arch/blackfin/kernel/pwm.c
new file mode 100644
index 000000000000..33f5942733bd
--- /dev/null
+++ b/arch/blackfin/kernel/pwm.c
@@ -0,0 +1,100 @@
+/*
+ * Blackfin Pulse Width Modulation (PWM) core
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+
+#include <asm/gptimers.h>
+#include <asm/portmux.h>
+
+struct pwm_device {
+        unsigned id;
+        unsigned short pin;
+};
+
+static const unsigned short pwm_to_gptimer_per[] = {
+        P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
+        P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
+};
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int ret;
+
+        /* XXX: pwm_id really should be unsigned */
+        if (pwm_id < 0)
+                return NULL;
+
+        pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+        if (!pwm)
+                return pwm;
+
+        pwm->id = pwm_id;
+        if (pwm->id >= ARRAY_SIZE(pwm_to_gptimer_per))
+                goto err;
+
+        pwm->pin = pwm_to_gptimer_per[pwm->id];
+        ret = peripheral_request(pwm->pin, label);
+        if (ret)
+                goto err;
+
+        return pwm;
+ err:
+        kfree(pwm);
+        return NULL;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwm)
+{
+        peripheral_free(pwm->pin);
+        kfree(pwm);
+}
+EXPORT_SYMBOL(pwm_free);
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long period, duty;
+        unsigned long long val;
+
+        if (duty_ns < 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        val = (unsigned long long)get_sclk() * period_ns;
+        do_div(val, NSEC_PER_SEC);
+        period = val;
+
+        val = (unsigned long long)period * duty_ns;
+        do_div(val, period_ns);
+        duty = period - val;
+
+        if (duty >= period)
+                duty = period - 1;
+
+        set_gptimer_config(pwm->id, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
+        set_gptimer_pwidth(pwm->id, duty);
+        set_gptimer_period(pwm->id, period);
+
+        return 0;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        enable_gptimer(pwm->id);
+        return 0;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        disable_gptimer(pwm->id);
+}
+EXPORT_SYMBOL(pwm_disable);
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 488bdc51aaa5..c4c0081b1996 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -54,7 +54,9 @@ static void bfin_reset(void)
 
         /* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-        bfin_read_SWRST();
+        /* Seems to be fixed with newer parts though ... */
+        if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
+                bfin_read_SWRST();
 #endif
 
         /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 536bd9d7e0cf..dfa2525a442d 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -54,8 +54,7 @@ EXPORT_SYMBOL(mtd_size);
 #endif
 
 char __initdata command_line[COMMAND_LINE_SIZE];
-void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
-        *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
+struct blackfin_initial_pda __initdata initial_pda;
 
 /* boot memmap, for parsing "memmap=" */
 #define BFIN_MEMMAP_MAX         128 /* number of entries in bfin_memmap */
@@ -957,13 +956,16 @@ void __init setup_arch(char **cmdline_p)
                 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
                 /* We assume the crashing kernel, and the current symbol table match */
-                printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
-                        (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
-                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
-                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
+                printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
+                        initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
+                        initial_pda.retx_doublefault);
+                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
+                        initial_pda.dcplb_doublefault_addr);
+                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
+                        initial_pda.icplb_doublefault_addr);
 #endif
                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
-                        init_retx);
+                        initial_pda.retx);
         } else if (_bfin_swrst & RESET_WDOG)
                 printk(KERN_INFO "Recovering from Watchdog event\n");
         else if (_bfin_swrst & RESET_SOFTWARE)
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 8d73724c0092..ceb2bf63dfe2 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -51,7 +51,7 @@ void __init setup_core_timer(void)
         u32 tcount;
 
         /* power up the timer, but don't enable it just yet */
-        bfin_write_TCNTL(1);
+        bfin_write_TCNTL(TMPWR);
         CSYNC();
 
         /* the TSCALE prescaler counter */
@@ -64,7 +64,7 @@ void __init setup_core_timer(void)
         /* now enable the timer */
         CSYNC();
 
-        bfin_write_TCNTL(7);
+        bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR);
 }
 #endif
 
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 3ac5b66d14aa..ba35864b2b74 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -155,6 +155,7 @@ SECTIONS
                 SECURITY_INITCALL
                 INIT_RAM_FS
 
+                . = ALIGN(PAGE_SIZE);
                 ___per_cpu_load = .;
                 PERCPU_INPUT(32)
 
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 1d9f631a7f94..bde92a19970e 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -11,55 +11,75 @@ menu "BF518 Specific Configuration"
 comment "Alternative Multiplexing Scheme"
 
 choice
-        prompt "SPORT0"
-        default BF518_SPORT0_PORTG
+        prompt "PWM Channel Pins"
+        default BF518_PWM_ALL_PORTF
         help
-          Select PORT used for SPORT0. See Hardware Reference Manual
+          Select pins used for the PWM channels:
+            PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
 
-config BF518_SPORT0_PORTF
-        bool "PORT F"
+          See the Hardware Reference Manual for more details.
+
+config BF518_PWM_ALL_PORTF
+        bool "PF1 - PF6"
         help
-          PORT F
+          PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
 
-config BF518_SPORT0_PORTG
-        bool "PORT G"
+config BF518_PWM_PORTF_PORTG
+        bool "PF11 - PF14 / PG1 - PG2"
         help
-          PORT G
+          PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
+          PG{1,2} <-> PWM_{CH,CL}
+
 endchoice
 
 choice
-        prompt "SPORT0 TSCLK Location"
-        depends on BF518_SPORT0_PORTG
-        default BF518_SPORT0_TSCLK_PG10
+        prompt "PWM Sync Pin"
+        default BF518_PWM_SYNC_PF7
         help
-          Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
+          Select the pin used for PWM_SYNC.
 
-config BF518_SPORT0_TSCLK_PG10
-        bool "PORT PG10"
-        help
-          PORT PG10
+          See the Hardware Reference Manual for more details.
+
+config BF518_PWM_SYNC_PF7
+        bool "PF7"
+config BF518_PWM_SYNC_PF15
+        bool "PF15"
+endchoice
 
-config BF518_SPORT0_TSCLK_PG14
-        bool "PORT PG14"
+choice
+        prompt "PWM Trip B Pin"
+        default BF518_PWM_TRIPB_PG10
         help
-          PORT PG14
+          Select the pin used for PWM_TRIPB.
+
+          See the Hardware Reference Manual for more details.
+
+config BF518_PWM_TRIPB_PG10
+        bool "PG10"
+config BF518_PWM_TRIPB_PG14
+        bool "PG14"
 endchoice
 
 choice
-        prompt "UART1"
-        default BF518_UART1_PORTF
+        prompt "PPI / Timer Pins"
+        default BF518_PPI_TMR_PG5
         help
-          Select PORT used for UART1. See Hardware Reference Manual
+          Select pins used for PPI/Timer:
+            PPICLK PPIFS1 PPIFS2
+            TMRCLK TMR0 TMR1
 
-config BF518_UART1_PORTF
-        bool "PORT F"
+          See the Hardware Reference Manual for more details.
+
+config BF518_PPI_TMR_PG5
+        bool "PG5 - PG7"
         help
-          PORT F
+          PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
 
-config BF518_UART1_PORTG
-        bool "PORT G"
+config BF518_PPI_TMR_PG12
+        bool "PG12 - PG14"
         help
-          PORT G
+          PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
+
 endchoice
 
 comment "Hysteresis/Schmitt Trigger Control"
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index c0ccadcfa44e..d78fc2cc7d16 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -187,43 +187,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-#if defined(CONFIG_NET_DSA_KSZ8893M) \
-        || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
-/* SPI SWITCH CHIP */
-static struct bfin5xx_spi_chip spi_switch_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#endif
-
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -239,21 +212,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -269,18 +227,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 #if defined(CONFIG_NET_DSA_KSZ8893M) \
         || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
@@ -290,7 +236,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 1,
                 .platform_data = NULL,
-                .controller_data = &spi_switch_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -314,7 +259,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
         },
 #endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -324,7 +268,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                 .mode = SPI_MODE_0,
         },
 #endif
@@ -334,7 +277,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -343,7 +285,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &lq035q1_spi_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 50fc5c89e379..55c127908815 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -138,32 +138,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -179,21 +163,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -209,18 +178,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
         {
                 .modalias = "mmc_spi",
@@ -239,7 +196,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
         },
 #endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -249,7 +205,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                 .mode = SPI_MODE_0,
         },
 #endif
@@ -259,7 +214,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -268,7 +222,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &lq035q1_spi_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index d2f076fbbc9e..56383f7cbc07 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -11,10 +11,9 @@
  */
 
 /* This file should be up to date with:
- *  - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
  */
 
-/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
 #if __SILICON_REVISION__ < 0
 # error will not work on BF518 silicon version
 #endif
@@ -77,19 +76,29 @@
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
 /* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
+#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -157,6 +166,5 @@
 #define ANOMALY_05000474 (0)
 #define ANOMALY_05000475 (0)
 #define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
index cd84a569b04e..b3b806f468da 100644
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -81,9 +81,15 @@
 #define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
 #define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
 
+#ifndef CONFIG_BF518_PPI_TMR_PG12
+#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#else
 #define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
 #define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
 #define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#endif
 #define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
 
 /* SPI Port Mux */
@@ -139,9 +145,15 @@
 #define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
 
 /* Timer */
+#ifndef CONFIG_BF518_PPI_TMR_PG12
 #define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
 #define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
 #define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#else
+#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
+#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
+#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#endif
 #define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
 #define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
 #define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
@@ -158,23 +170,33 @@
 #define P_TWI0_SDA      (P_DONTCARE)
 
 /* PWM */
-#define P_PWM0_AH               (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM0_AL               (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM0_BH               (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM0_BL               (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM0_CH               (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM0_CL               (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PWM0_SYNC             (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_PWM1_AH               (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM1_AL               (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM1_BH               (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM1_BL               (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM1_CH               (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM1_CL               (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_PWM1_SYNC             (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
+#ifndef CONFIG_BF518_PWM_PORTF_PORTG
+#define P_PWM_AH                (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#define P_PWM_AL                (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_PWM_BH                (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_PWM_BL                (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_PWM_CH                (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_PWM_CL                (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#else
+#define P_PWM_AH                (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
+#define P_PWM_AL                (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_PWM_BH                (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+#define P_PWM_BL                (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_PWM_CH                (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_PWM_CL                (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#endif
+
+#ifndef CONFIG_BF518_PWM_SYNC_PF15
+#define P_PWM_SYNC              (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+#else
+#define P_PWM_SYNC              (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+#endif
+
+#ifndef CONFIG_BF518_PWM_TRIPB_PG14
+#define P_PWM_TRIPB             (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
+#else
 #define P_PWM_TRIPB             (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#endif
 
 /* RSI */
 #define P_RSI_DATA0             (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index ccab4c689dc3..c04df43f6391 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -265,29 +265,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -328,7 +311,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -347,7 +329,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 };
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index c9d6dc88f0e6..6400341cc230 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -354,40 +354,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -403,21 +379,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -433,18 +394,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
         || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
@@ -452,7 +401,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -473,7 +421,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
         },
 #endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -483,7 +430,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                 .mode = SPI_MODE_0,
         },
 #endif
@@ -493,7 +439,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 };
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index b7101aa6e3aa..6dbb1b403763 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -253,32 +253,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (sst25wf040) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -311,35 +295,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -355,18 +310,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
         {
                 .modalias = "mmc_spi",
@@ -385,7 +328,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
         },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -396,7 +338,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 5,
-                .controller_data = &spi_ad7879_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -407,7 +348,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                 .mode = SPI_MODE_0,
         },
 #endif
@@ -417,7 +357,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -426,7 +365,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &lq035q1_spi_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index e67ac7720668..4e9dc9cf8241 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -409,6 +409,9 @@ static struct resource net2272_bfin_resources[] = {
                 .end = 0x20300000 + 0x100,
                 .flags = IORESOURCE_MEM,
         }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -448,40 +451,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -513,20 +492,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
         defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
 
@@ -574,9 +539,25 @@ static struct resource bfin_snd_resources[][4] = {
         BFIN_SND_RES(0),
         BFIN_SND_RES(1),
 };
+#endif
 
-static struct platform_device bfin_pcm = {
-        .name = "bfin-pcm-audio",
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+static struct platform_device bfin_i2s_pcm = {
+        .name = "bfin-i2s-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+static struct platform_device bfin_tdm_pcm = {
+        .name = "bfin-tdm-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+static struct platform_device bfin_ac97_pcm = {
+        .name = "bfin-ac97-pcm-audio",
         .id = -1,
 };
 #endif
@@ -605,13 +586,6 @@ static struct platform_device bfin_tdm = {
 };
 #endif
 
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
-
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -627,18 +601,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
         || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
@@ -647,7 +609,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 4,
                 .platform_data = "ad1836",
-                .controller_data = &ad1836_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -670,7 +631,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
         },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -681,7 +641,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 3,
-                .controller_data = &spi_ad7879_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -691,7 +650,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -700,7 +658,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 7,
-                .controller_data = &lq035q1_spi_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -1276,9 +1233,16 @@ static struct platform_device *stamp_devices[] __initdata = {
         &ezkit_flash_device,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_pcm,
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+        &bfin_i2s_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+        &bfin_tdm_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_ac97_pcm,
 #endif
 
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 18d303dd5627..ec4bc7429c9f 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -314,29 +314,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 0,         /* use dma transfer with this chip*/
-/*
- * tll6527m V1.0 does not support native spi slave selects
- * hence DMA mode will not be useful since the ADC needs
- * CS to toggle for each sample and cs_change_per_word
- * seems to be removed from spi_bfin5xx.c
- */
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -359,21 +342,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
-        || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 static struct platform_device bfin_i2s = {
         .name = "bfin-i2s",
@@ -382,24 +350,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
-
 #if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
-static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-
-static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-
 #include <linux/spi/mcp23s08.h>
 static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
         .chip[0].is_present = true,
@@ -429,22 +380,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC)
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc",
-                                /* Name of spi_driver for this device */
-                .max_speed_hz = 10000000,
-                                /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
-                 /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-                .mode = SPI_MODE_0,
-        },
-#endif
-
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
         {
                 .modalias = "mmc_spi",
@@ -470,7 +405,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                                         /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
-                .controller_data = &spi_ad7879_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -482,7 +416,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
                 .mode = SPI_CPHA | SPI_CPOL,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -491,7 +424,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,
                 .bus_num = 0,
                 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
-                .controller_data = &lq035q1_spi_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -502,7 +434,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
-                .controller_data = &spi_mcp23s08_sys_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
         {
@@ -511,7 +442,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
-                .controller_data = &spi_mcp23s08_usr_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index e66a7e89cd3c..688470611e15 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -11,8 +11,8 @@
  */
 
 /* This file should be up to date with:
- *  - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -57,7 +57,7 @@
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
 #define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
 /* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
 #define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
@@ -135,7 +135,7 @@
 /* Incorrect Default Internal Voltage Regulator Setting */
 #define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
+#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
 #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* DEB2_URGENT Bit Not Functional */
@@ -181,11 +181,11 @@
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
 /* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (1)
-/* USB DMA Mode 1 Short Packet Data Corruption */
+#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
+/* USB DMA Short Packet Data Corruption */
 #define ANOMALY_05000450 (1)
 /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (1)
+#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
 /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
 #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
@@ -198,19 +198,19 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* USB Rx DMA hang */
+/* USB Rx DMA Hang */
 #define ANOMALY_05000465 (1)
 /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
 #define ANOMALY_05000466 (1)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
 #define ANOMALY_05000467 (1)
 /* PLL Latches Incorrect Settings During Reset */
 #define ANOMALY_05000469 (1)
 /* Incorrect Default MSEL Value in PLL_CTL */
 #define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
@@ -219,11 +219,19 @@
 /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
 #define ANOMALY_05000483 (1)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
 /* The CODEC Zero-Cross Detect Feature is not Functional */
 #define ANOMALY_05000487 (1)
-/* IFLUSH sucks at life */
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index d4bfcea56828..eb325ed6607e 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -159,22 +159,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
@@ -195,24 +179,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 4,     /* actual baudrate is SCLK/(2xspeed_hz) */
-                .bus_num = 1, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
                 .max_speed_hz = 16,
                 .bus_num = 1,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 87b5af3693c1..b0ec825fb4ec 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -102,21 +102,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -151,7 +142,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 7,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 };
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 4d5604eaa7c2..14f54a31e74c 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -59,29 +59,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-/* SPI ADC chip */
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -99,24 +82,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0,               /* Framework bus number */
-                .chip_select = 2,           /* Framework chip select. */
-                .platform_data = NULL,      /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index b67b91d82242..ecd2801f050d 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -210,29 +210,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -250,24 +227,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -276,7 +241,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 };
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index a377d8afea03..fbee77fa9211 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -110,7 +110,6 @@ static struct platform_device dm9000_device2 = {
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,                /* if 1 - block!!! */
-        .bits_per_word = 8,
 };
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 43224ef00b8c..964a8e5f79b4 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -80,6 +80,9 @@ static struct resource net2272_bfin_resources[] = {
                 .end = 0x20300000 + 0x100,
                 .flags = IORESOURCE_MEM,
         }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                 .start = IRQ_PF10,
                 .end = IRQ_PF10,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -172,29 +175,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -221,7 +201,6 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
 
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
         .pio_interrupt = 0,
 };
 #endif
@@ -240,17 +219,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
@@ -258,7 +226,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 4,
                 .platform_data = "ad1836", /* only includes chip name for the moment */
-                .controller_data = &ad1836_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -269,7 +236,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -659,6 +625,41 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 };
 
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+
+        /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
+        ret = gpio_request(GPIO_PF0, "net2272");
+        if (ret)
+                return ret;
+
+        ret = gpio_request(GPIO_PF1, "net2272");
+        if (ret) {
+                gpio_free(GPIO_PF0);
+                return ret;
+        }
+
+        ret = gpio_request(GPIO_PF11, "net2272");
+        if (ret) {
+                gpio_free(GPIO_PF0);
+                gpio_free(GPIO_PF1);
+                return ret;
+        }
+
+        gpio_direction_output(GPIO_PF0, 0);
+        gpio_direction_output(GPIO_PF1, 1);
+
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PF11, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF11, 1);
+#endif
+
+        return 0;
+}
+
 static int __init stamp_init(void)
 {
         int ret;
@@ -685,6 +686,9 @@ static int __init stamp_init(void)
         }
 #endif
 
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
+
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
         return 0;
 }
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 72aa59440f82..03f2b40912a3 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -11,7 +11,7 @@
  */
 
 /* This file should be up to date with:
- *  - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ *  - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -152,7 +152,7 @@
 #define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
@@ -210,18 +210,25 @@
 #define ANOMALY_05000462 (1)
 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
 #define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 
-/* These anomalies have been "phased" out of analog.com anomaly sheets and are
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
  * here to show running on older silicon just isn't feasible.
  */
 
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index d582b810e7a7..44fd8409db10 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -61,29 +61,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -101,24 +84,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 
@@ -766,6 +737,24 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
 #endif
 };
 
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+
+        ret = gpio_request(GPIO_PG14, "net2272");
+        if (ret)
+                return ret;
+
+        /* Reset USB Chip, PG14 */
+        gpio_direction_output(GPIO_PG14, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PG14, 1);
+#endif
+
+        return 0;
+}
+
 static int __init cm_bf537e_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -777,6 +766,10 @@ static int __init cm_bf537e_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
         irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index cbb8098604c5..1b4ac5c64aae 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -62,29 +62,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -102,24 +85,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 
@@ -731,6 +702,36 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
 #endif
 };
 
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+
+        ret = gpio_request(GPIO_PH15, driver_name);
+        if (ret)
+                return ret;
+
+        ret = gpio_request(GPIO_PH13, "net2272");
+        if (ret) {
+                gpio_free(GPIO_PH15);
+                return ret;
+        }
+
+        /* Set PH15 Low make /AMS2 work properly */
+        gpio_direction_output(GPIO_PH15, 0);
+
+        /* enable CLKBUF output */
+        bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PH13, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PH13, 1);
+#endif
+
+        return 0;
+}
+
 static int __init cm_bf537u_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -742,6 +743,10 @@ static int __init cm_bf537u_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
         irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index 6b4ff4605bff..8bc951de979d 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -130,7 +130,6 @@ static struct platform_device asmb_flash_device = {
 
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma    = 0,      /* use no dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 
 #endif
@@ -161,7 +160,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
 
 static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
         .enable_dma    = 0,      /* use no dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index bfb3671a78da..c62f9dccd9f7 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -159,14 +159,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 9389f03e3b0a..3b8151d99b9a 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -184,40 +184,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -248,18 +224,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
         || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
@@ -267,7 +231,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -288,7 +251,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
         .bus_num                = 0,
         .chip_select            = 5,
-        .controller_data = &spi_ad7877_chip_info,
 },
 #endif
 
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 76db1d483173..b52e6728f64f 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -367,6 +367,9 @@ static struct resource net2272_bfin_resources[] = {
                 .end = 0x20300000 + 0x100,
                 .flags = IORESOURCE_MEM,
         }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                 .start = IRQ_PF7,
                 .end = IRQ_PF7,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -533,49 +536,11 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD193X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
-static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \
-        || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
-static struct bfin5xx_spi_chip adav801_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
 #include <linux/input/ad714x.h>
-static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 
 static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
         {
@@ -685,7 +650,6 @@ static struct ad714x_platform_data ad7142_i2c_platform_data = {
 #if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE)
 static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
@@ -697,7 +661,6 @@ static unsigned short ad2s120x_platform_data[] = {
 
 static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
@@ -714,14 +677,12 @@ static unsigned short ad2s1210_platform_data[] = {
 
 static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
 static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
@@ -735,7 +696,6 @@ static unsigned short ad7816_platform_data[] = {
 
 static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -749,7 +709,6 @@ static unsigned long adt7310_platform_data[3] = {
 
 static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -758,11 +717,6 @@ static unsigned short ad7298_platform_data[] = {
         GPIO_PF7, /* busy_pin */
         0,
 };
-
-static struct bfin5xx_spi_chip ad7298_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 #endif
 
 #if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
@@ -773,7 +727,6 @@ static unsigned long adt7316_spi_data[2] = {
 
 static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -800,18 +753,12 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
 
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
         .pio_interrupt = 0,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 #include <linux/spi/ad7877.h>
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -883,39 +830,13 @@ static const struct adxl34x_platform_data adxl34x_info = {
 };
 #endif
 
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
-
 #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
 static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
         .enable_dma     = 1,
-        .bits_per_word  = 8,
 };
 #endif
 
 #if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
-static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
-        .bits_per_word = 16,
-};
-
 #include <linux/spi/adf702x.h>
 #define TXREG 0x0160A470
 static const u32 adf7021_regs[] = {
@@ -959,10 +880,6 @@ static inline void adf702x_mac_init(void) {}
 
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 #include <linux/spi/ads7846.h>
-static struct bfin5xx_spi_chip ad7873_spi_chip_info = {
-        .bits_per_word  = 8,
-};
-
 static int ads7873_get_pendown_state(void)
 {
         return gpio_get_value(GPIO_PF6);
@@ -1009,21 +926,12 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
 /* DataFlash chip */
 static struct bfin5xx_spi_chip data_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
-        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE)
 static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
@@ -1053,17 +961,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .mode = SPI_MODE_3,
         },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
         || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
@@ -1073,7 +970,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 4,
                 .platform_data = "ad1836", /* only includes chip name for the moment */
-                .controller_data = &ad1836_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -1084,7 +980,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 5,
-                .controller_data = &ad1938_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -1095,7 +990,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &adav801_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -1109,7 +1003,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .chip_select = 5,
                 .mode = SPI_MODE_3,
                 .platform_data = &ad7147_spi_platform_data,
-                .controller_data = &ad7147_spi_chip_info,
         },
 #endif
 
@@ -1188,7 +1081,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 4,            /* CS, change it for your board */
                 .platform_data = ad7298_platform_data,
-                .controller_data = &ad7298_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -1225,7 +1117,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select  = 1,
-                .controller_data = &spi_ad7877_chip_info,
         },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -1236,7 +1127,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spi_ad7879_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -1246,7 +1136,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -1255,7 +1144,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 2,
-                .controller_data = &lq035q1_spi_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -1278,7 +1166,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz   = 5000000,    /* max spi clock (SCK) speed in HZ */
                 .bus_num        = 0,
                 .chip_select    = 2,
-                .controller_data = &spi_adxl34x_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -1288,7 +1175,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 16000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
-                .controller_data = &adf7021_spi_chip_info,
                 .platform_data = &adf7021_platform_data,
                 .mode = SPI_MODE_0,
         },
@@ -1300,7 +1186,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .irq = IRQ_PF6,
                 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
-                .controller_data = &ad7873_spi_chip_info,
                 .platform_data = &ad7873_pdata,
                 .mode = SPI_MODE_0,
         },
@@ -2632,9 +2517,25 @@ static struct resource bfin_snd_resources[][4] = {
         BFIN_SND_RES(0),
         BFIN_SND_RES(1),
 };
+#endif
+
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+static struct platform_device bfin_i2s_pcm = {
+        .name = "bfin-i2s-pcm-audio",
+        .id = -1,
+};
+#endif
 
-static struct platform_device bfin_pcm = {
-        .name = "bfin-pcm-audio",
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+static struct platform_device bfin_tdm_pcm = {
+        .name = "bfin-tdm-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+static struct platform_device bfin_ac97_pcm = {
+        .name = "bfin-ac97-pcm-audio",
         .id = -1,
 };
 #endif
@@ -2869,10 +2770,16 @@ static struct platform_device *stamp_devices[] __initdata = {
         &stamp_flash_device,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
-        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
-        &bfin_pcm,
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+        &bfin_i2s_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+        &bfin_tdm_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_ac97_pcm,
 #endif
 
 #if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
@@ -2916,6 +2823,24 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 };
 
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+
+        ret = gpio_request(GPIO_PF6, "net2272");
+        if (ret)
+                return ret;
+
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PF6, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF6, 1);
+#endif
+
+        return 0;
+}
+
 static int __init stamp_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -2926,6 +2851,9 @@ static int __init stamp_init(void)
                                 ARRAY_SIZE(bfin_i2c_board_info));
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 164a7e02c022..9b7287abdfa1 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -62,29 +62,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
         .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -102,24 +85,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 
@@ -733,6 +704,24 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 };
 
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+
+        ret = gpio_request(GPIO_PG14, "net2272");
+        if (ret)
+                return ret;
+
+        /* Reset USB Chip, PG14 */
+        gpio_direction_output(GPIO_PG14, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PG14, 1);
+#endif
+
+        return 0;
+}
+
 static int __init tcm_bf537_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -744,6 +733,10 @@ static int __init tcm_bf537_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
         irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 7f8e5a9f5db6..543cd3fb305e 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -11,7 +11,7 @@
  */
 
 /* This file should be up to date with:
- *  - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -44,18 +44,12 @@
 #define ANOMALY_05000119 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
 #define ANOMALY_05000180 (1)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
 #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (1)
 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
 #define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
 /* EMAC TX DMA Error After an Early Frame Abort */
@@ -98,7 +92,7 @@
 #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
 /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
 #define ANOMALY_05000280 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
@@ -162,9 +156,9 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
@@ -172,8 +166,26 @@
 #define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* Instruction Cache Is Not Functional */
+#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
+/* Buffered CLKIN Output Is Disabled by Default */
+#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index e61424ef35eb..629f3c333415 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -502,7 +502,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
@@ -523,13 +522,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 #include <asm/bfin-lq035q1.h>
 
@@ -559,20 +551,6 @@ static struct platform_device bfin_lq035q1_device = {
 };
 #endif
 
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
-
 static struct spi_board_info bf538_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -595,7 +573,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spi_ad7879_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -605,7 +582,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 2,
-                .controller_data = &lq035q1_spi_chip_info,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
@@ -615,7 +591,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 };
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
index 180b1252679f..471a9b184d5b 100644
--- a/arch/blackfin/mach-bf538/ext-gpio.c
+++ b/arch/blackfin/mach-bf538/ext-gpio.c
@@ -1,7 +1,7 @@
 /*
  * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
  *
- * Copyright 2009 Analog Devices Inc.
+ * Copyright 2009-2011 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -121,3 +121,38 @@ static int __init bf538_extgpio_setup(void)
                 gpiochip_add(&bf538_porte_chip);
 }
 arch_initcall(bf538_extgpio_setup);
+
+#ifdef CONFIG_PM
+static struct {
+        u16 data, dir, inen;
+} gpio_bank_saved[3];
+
+static void __iomem * const port_bases[3] = {
+        (void *)PORTCIO,
+        (void *)PORTDIO,
+        (void *)PORTEIO,
+};
+
+void bfin_special_gpio_pm_hibernate_suspend(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
+                gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
+                gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
+                gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
+        }
+}
+
+void bfin_special_gpio_pm_hibernate_restore(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
+                write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
+                write_PORTIO_SET(port_bases[i],
+                        gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
+                write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
+        }
+}
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 55e7d0712a94..b6ca99788710 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -11,8 +11,8 @@
  */
 
 /* This file should be up to date with:
- *  - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- *  - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ *  - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ *  - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -56,25 +56,21 @@
 #define ANOMALY_05000229 (1)
 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
 #define ANOMALY_05000233 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Maximum External Clock Speed for Timers */
 #define ANOMALY_05000253 (1)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
 #define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
+#define ANOMALY_05000272 (ANOMALY_BF538)
 /* Writes to Synchronous SDRAM Memory May Be Lost */
 #define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
 #define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
@@ -102,8 +98,10 @@
 #define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
 #define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
+/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
+#define ANOMALY_05000317 (__SILICON_REVISION__ < 4)     /* XXX: Same as 05000318 */
 /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
+#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)     /* XXX: Same as 05000317 */
 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
 #define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -134,16 +132,32 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 8a5beeece996..3561c7d8935b 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -8,7 +8,10 @@
 #define _MACH_GPIO_H_
 
 #define MAX_BLACKFIN_GPIOS 16
+#ifdef CONFIG_GPIOLIB
+/* We only use the special logic with GPIOLIB devices */
 #define BFIN_SPECIAL_GPIO_BANKS 3
+#endif
 
 #define GPIO_PF0        0       /* PF */
 #define GPIO_PF1        1
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index d11502ac5623..212b9e0a08c8 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -861,16 +861,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
 
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -886,13 +880,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 static struct spi_board_info bf54x_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -915,7 +902,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
         .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
         .bus_num                = 0,
         .chip_select            = 2,
-        .controller_data = &spi_ad7877_chip_info,
 },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -924,7 +910,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 };
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 311bf9970fe7..cd9cbb68de69 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -1018,24 +1018,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
 
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
         .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -1051,20 +1037,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
-        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -1086,7 +1058,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 1,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
@@ -1097,7 +1068,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num                = 0,
                 .chip_select            = 2,
-                .controller_data = &spi_ad7877_chip_info,
         },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1106,7 +1076,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
@@ -1117,7 +1086,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz           = 5000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num                = 1,
                 .chip_select            = 2,
-                .controller_data = &spi_adxl34x_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 9e70785bdde3..ac96ee83b00e 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -11,7 +11,7 @@
  */
 
 /* This file should be up to date with:
- *  - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ *  - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -29,117 +29,37 @@
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (1)
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
 #define ANOMALY_05000272 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
 /* FIFO Boot Mode Not Functional */
 #define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
 /*
  * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
  *       shows that the fix itself does not cover all cases.
  */
 #define ANOMALY_05000353 (1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
 #define ANOMALY_05000357 (1)
 /* External Memory Read Access Hangs Core With PLL Bypass */
 #define ANOMALY_05000360 (1)
 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
 #define ANOMALY_05000365 (1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
 /* Addressing Conflict between Boot ROM and Asynchronous Memory */
 #define ANOMALY_05000369 (1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
 /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
 #define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
 /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
 #define ANOMALY_05000379 (1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Some ATAPI Modes Are Not Functional */
-#define ANOMALY_05000383 (1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
 /* Lockbox SESR Disallows Certain User Interrupts */
 #define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
@@ -161,7 +81,7 @@
 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 #define ANOMALY_05000416 (1)
 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 #define ANOMALY_05000426 (1)
 /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
@@ -174,8 +94,6 @@
 #define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
 /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
 #define ANOMALY_05000434 (1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
 /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
@@ -186,34 +104,32 @@
 #define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
 /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
 #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Mode 1 Short Packet Data Corruption */
+/* USB DMA Short Packet Data Corruption */
 #define ANOMALY_05000450 (1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
 #define ANOMALY_05000456 (1)
 /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
 #define ANOMALY_05000457 (1)
 /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
+#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
 /* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (1)
+#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
 /* USB TX DMA Hang */
-#define ANOMALY_05000464 (1)
-/* USB Rx DMA hang */
+#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
+/* USB Rx DMA Hang */
 #define ANOMALY_05000465 (1)
 /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
-#define ANOMALY_05000467 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
+#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
-#define ANOMALY_05000474 (1)
+/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
+#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -223,9 +139,111 @@
 /* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
 #define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
-/* IFLUSH sucks at life */
+#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
+#define ANOMALY_05000500 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
+#define ANOMALY_05000502 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* False Hardware Error when ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
+/* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
+/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
+/* Synchronous Burst Flash Boot Mode Is Not Functional */
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
+/* Host DMA Boot Modes Are Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
+/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
+/* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
+/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
+/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
+/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
+/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
+/* Data Lost when Core Reads SDH Data FIFO */
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
+/* PLL Status Register Is Inaccurate */
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 7db433514e3f..35c8ced46158 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -170,6 +170,8 @@
 
 #define MAX_BLACKFIN_GPIOS 160
 
+#define BFIN_GPIO_PINT 1
+
 #ifndef __ASSEMBLY__
 
 struct gpio_port_t {
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 533b8095b540..10dc142c518d 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -438,7 +438,7 @@
 struct bfin_pint_regs {
         u32 mask_set;
         u32 mask_clear;
-        u32 irq;
+        u32 request;
         u32 assign;
         u32 edge_set;
         u32 edge_clear;
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 9231a942892b..972e1347c6bc 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -364,14 +364,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
 /* DataFlash chip */
 static struct bfin5xx_spi_chip data_flash_chip_info = {
         .enable_dma = 0,        /* use dma transfer with this chip */
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -420,7 +412,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
          .max_speed_hz = 3125000,       /* max spi clock (SCK) speed in HZ */
          .bus_num = 0,
          .chip_select = 3,
-         .controller_data = &spidev_chip_info,
          },
 #endif
 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 87595cd38afe..e4f397d1d65b 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -60,29 +60,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 
@@ -100,24 +77,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
         {
                 .modalias = "ad183x",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
         },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -126,7 +91,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &mmc_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -532,6 +496,24 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
 #endif
 };
 
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+
+        ret = gpio_request(GPIO_PF46, "net2272");
+        if (ret)
+                return ret;
+
+        /* Reset USB Chip, PF46 */
+        gpio_direction_output(GPIO_PF46, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF46, 1);
+#endif
+
+        return 0;
+}
+
 static int __init cm_bf561_init(void)
 {
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -543,6 +525,10 @@ static int __init cm_bf561_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
         irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 5067984a62e7..9490dc800ca5 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -108,6 +108,9 @@ static struct resource net2272_bfin_resources[] = {
                 .end = 0x2C000000 + 0x7F,
                 .flags = IORESOURCE_MEM,
         }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                 .start = IRQ_PF10,
                 .end = IRQ_PF10,
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
@@ -283,21 +286,6 @@ static struct platform_device ezkit_flash_device = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
@@ -345,7 +333,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 4,
                 .platform_data = "ad1836", /* only includes chip name for the moment */
-                .controller_data = &ad1836_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -355,7 +342,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 1,
-                .controller_data = &spidev_chip_info,
         },
 #endif
 };
@@ -516,6 +502,24 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 };
 
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+
+        ret = gpio_request(GPIO_PF11, "net2272");
+        if (ret)
+                return ret;
+
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PF11, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF11, 1);
+#endif
+
+        return 0;
+}
+
 static int __init ezkit_init(void)
 {
         int ret;
@@ -542,6 +546,9 @@ static int __init ezkit_init(void)
         udelay(400);
 #endif
 
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
+
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
         return 0;
 }
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 22b5ab773027..836baeed303a 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -11,7 +11,7 @@
  */
 
 /* This file should be up to date with:
- *  - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -26,62 +26,16 @@
 #define ANOMALY_05000074 (1)
 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
 #define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
 /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
 #define ANOMALY_05000120 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
 /* SIGNBITS Instruction Not Functional under Certain Conditions */
 #define ANOMALY_05000127 (1)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
 /* IMDMA S1/D1 Channel May Stall */
 #define ANOMALY_05000149 (1)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
 /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
 #define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
 /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
 #define ANOMALY_05000166 (1)
 /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
@@ -92,10 +46,6 @@
 #define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
 /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
 #define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
 /* Cache Fill Buffer Data lost */
 #define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
 /* Overlapping Sequencer and Memory Stalls */
@@ -124,8 +74,6 @@
 #define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
 /* PPI Not Functional at Core Voltage < 1Volt */
 #define ANOMALY_05000190 (1)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
 #define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
 /* Restarting SPORT in Specific Modes May Cause Data Corruption */
@@ -217,10 +165,10 @@
 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
 #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 /* Temporarily walk around for bug 5423 till this issue is confirmed by
  * official anomaly document. It looks 05000281 still exists on bf561
  * v0.5.
@@ -274,8 +222,6 @@
 #define ANOMALY_05000366 (1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
 /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
@@ -298,16 +244,82 @@
 #define ANOMALY_05000462 (1)
 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
 #define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
+/* Erroneous Exception when Enabling Cache */
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
+/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
+#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
+/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
+#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
+/* Stall in multi-unit DMA operations */
+#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
+/* DMA and TESTSET conflict when both are accessing external memory */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* DMA engine may lose data due to incorrect handshaking */
+#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
+/* DMA stalls when all three controllers read data from the same source */
+#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
+/* Execution stall when executing in L2 and doing external accesses */
+#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
+/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL<12> is not set on Reset */
+#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
+/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* DSPID register values incorrect */
+#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000119 (0)
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index 57d5eab59faf..f9f8b2adf4ba 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -58,9 +58,9 @@
 #define GPIO_PF46       46
 #define GPIO_PF47       47
 
-#define PORT_FIO0 GPIO_0
-#define PORT_FIO1 GPIO_16
-#define PORT_FIO2 GPIO_32
+#define PORT_FIO0 GPIO_PF0
+#define PORT_FIO1 GPIO_PF16
+#define PORT_FIO2 GPIO_PF32
 
 #include <mach-common/ports-f.h>
 
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 4c462838f4e1..01e5408620ac 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -23,108 +23,78 @@
 #define INITIAL_STACK   (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
 
 ENTRY(_coreb_trampoline_start)
-        /* Set the SYSCFG register */
-        R0 = 0x36;
-        SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
-        R0 = 0;
-
-        /*Clear Out All the data and pointer  Registers*/
-        R1 = R0;
-        R2 = R0;
-        R3 = R0;
-        R4 = R0;
-        R5 = R0;
-        R6 = R0;
-        R7 = R0;
-
-        P0 = R0;
-        P1 = R0;
-        P2 = R0;
-        P3 = R0;
-        P4 = R0;
-        P5 = R0;
-
-        LC0 = r0;
-        LC1 = r0;
-        L0 = r0;
-        L1 = r0;
-        L2 = r0;
-        L3 = r0;
-
-        /* Clear Out All the DAG Registers*/
-        B0 = r0;
-        B1 = r0;
-        B2 = r0;
-        B3 = r0;
-
-        I0 = r0;
-        I1 = r0;
-        I2 = r0;
-        I3 = r0;
-
-        M0 = r0;
-        M1 = r0;
-        M2 = r0;
-        M3 = r0;
+        /* Enable Cycle Counter and Nesting Of Interrupts */
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
+        R0 = SYSCFG_SNEN;
+#else
+        R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
+        SYSCFG = R0;
 
-        trace_buffer_init(p0,r0);
+        /* Optimization register tricks: keep a base value in the
+         * reserved P registers so we use the load/store with an
+         * offset syntax.  R0 = [P5 + <constant>];
+         *   P5 - core MMR base
+         *   R6 - 0
+         */
+        r6 = 0;
+        p5.l = 0;
+        p5.h = hi(COREMMR_BASE);
 
-        /* Turn off the icache */
-        p0.l = LO(IMEM_CONTROL);
-        p0.h = HI(IMEM_CONTROL);
-        R1 = [p0];
-        R0 = ~ENICPLB;
-        R0 = R0 & R1;
+        /* Zero out registers required by Blackfin ABI */
 
-        /* Disabling of CPLBs should be proceeded by a CSYNC */
+        /* Disable circular buffers */
+        L0 = r6;
+        L1 = r6;
+        L2 = r6;
+        L3 = r6;
+
+        /* Disable hardware loops in case we were started by 'go' */
+        LC0 = r6;
+        LC1 = r6;
+
+        /*
+         * Clear ITEST_COMMAND and DTEST_COMMAND registers,
+         * Leaving these as non-zero can confuse the emulator
+         */
+        [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
+        [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
         CSYNC;
-        [p0] = R0;
+
+        trace_buffer_init(p0,r0);
+
+        /* Turn off the icache */
+        r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
+        BITCLR (r1, ENICPLB_P);
+        [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
         SSYNC;
 
         /* Turn off the dcache */
-        p0.l = LO(DMEM_CONTROL);
-        p0.h = HI(DMEM_CONTROL);
-        R1 = [p0];
-        R0 = ~ENDCPLB;
-        R0 = R0 & R1;
-
-        /* Disabling of CPLBs should be proceeded by a CSYNC */
-        CSYNC;
-        [p0] = R0;
+        r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
+        BITCLR (r1, ENDCPLB_P);
+        [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
         SSYNC;
 
         /* in case of double faults, save a few things */
-        p0.l = _init_retx_coreb;
-        p0.h = _init_retx_coreb;
-        R0 = RETX;
-        [P0] = R0;
-
+        p1.l = _initial_pda_coreb;
+        p1.h = _initial_pda_coreb;
+        r4 = RETX;
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
         /* Only save these if we are storing them,
          * This happens here, since L1 gets clobbered
          * below
          */
         GET_PDA(p0, r0);
-        r7 = [p0 + PDA_DF_RETX];
-        p1.l = _init_saved_retx_coreb;
-        p1.h = _init_saved_retx_coreb;
-        [p1] = r7;
-
-        r7 = [p0 + PDA_DF_DCPLB];
-        p1.l = _init_saved_dcplb_fault_addr_coreb;
-        p1.h = _init_saved_dcplb_fault_addr_coreb;
-        [p1] = r7;
-
-        r7 = [p0 + PDA_DF_ICPLB];
-        p1.l = _init_saved_icplb_fault_addr_coreb;
-        p1.h = _init_saved_icplb_fault_addr_coreb;
-        [p1] = r7;
-
-        r7 = [p0 + PDA_DF_SEQSTAT];
-        p1.l = _init_saved_seqstat_coreb;
-        p1.h = _init_saved_seqstat_coreb;
-        [p1] = r7;
+        r0 = [p0 + PDA_DF_RETX];
+        r1 = [p0 + PDA_DF_DCPLB];
+        r2 = [p0 + PDA_DF_ICPLB];
+        r3 = [p0 + PDA_DF_SEQSTAT];
+        [p1 + PDA_INIT_DF_RETX] = r0;
+        [p1 + PDA_INIT_DF_DCPLB] = r1;
+        [p1 + PDA_INIT_DF_ICPLB] = r2;
+        [p1 + PDA_INIT_DF_SEQSTAT] = r3;
 #endif
+        [p1 + PDA_INIT_RETX] = r4;
 
         /* Initialize stack pointer */
         sp.l = lo(INITIAL_STACK);
@@ -138,19 +108,13 @@ ENTRY(_coreb_trampoline_start)
 
         /* EVT15 = _real_start */
 
-        p0.l = lo(EVT15);
-        p0.h = hi(EVT15);
         p1.l = _coreb_start;
         p1.h = _coreb_start;
-        [p0] = p1;
+        [p5 + (EVT15 - COREMMR_BASE)] = p1;
         csync;
 
-        p0.l = lo(IMASK);
-        p0.h = hi(IMASK);
-        p1.l = IMASK_IVG15;
-        p1.h = 0x0;
-        [p0] = p1;
-        csync;
+        r0 = EVT_IVG15 (z);
+        sti r0;
 
         raise 15;
         p0.l = .LWAIT_HERE;
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 9cfdd49a3127..1c534d298de4 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -12,8 +12,8 @@
 .section .l1.text
 
 ENTRY(_sleep_mode)
-        [--SP] = ( R7:0, P5:0 );
-        [--SP] =  RETS;
+        [--SP] = (R7:4, P5:3);
+        [--SP] = RETS;
 
         call _set_sic_iwr;
 
@@ -46,15 +46,25 @@ ENTRY(_sleep_mode)
         call _test_pll_locked;
 
         RETS = [SP++];
-        ( R7:0, P5:0 ) = [SP++];
+        (R7:4, P5:3) = [SP++];
         RTS;
 ENDPROC(_sleep_mode)
 
+/*
+ * This func never returns as it puts the part into hibernate, and
+ * is only called from do_hibernate, so we don't bother saving or
+ * restoring any of the normal C runtime state.  When we wake up,
+ * the entry point will be in do_hibernate and not here.
+ *
+ * We accept just one argument -- the value to write to VR_CTL.
+ */
 ENTRY(_hibernate_mode)
-        [--SP] = ( R7:0, P5:0 );
-        [--SP] =  RETS;
+        /* Save/setup the regs we need early for minor pipeline optimization */
+        R4 = R0;
+        P3.H = hi(VR_CTL);
+        P3.L = lo(VR_CTL);
 
-        R3 = R0;
+        /* Disable all wakeup sources */
         R0 = IWR_DISABLE_ALL;
         R1 = IWR_DISABLE_ALL;
         R2 = IWR_DISABLE_ALL;
@@ -62,10 +72,8 @@ ENTRY(_hibernate_mode)
         call _set_dram_srfs;
         SSYNC;
 
-        P0.H = hi(VR_CTL);
-        P0.L = lo(VR_CTL);
-
-        W[P0] = R3.L;
+        /* Finally, we climb into our cave to hibernate */
+        W[P3] = R4.L;
         CLI R2;
         IDLE;
 .Lforever:
@@ -73,8 +81,8 @@ ENTRY(_hibernate_mode)
 ENDPROC(_hibernate_mode)
 
 ENTRY(_sleep_deeper)
-        [--SP] = ( R7:0, P5:0 );
-        [--SP] =  RETS;
+        [--SP] = (R7:4, P5:3);
+        [--SP] = RETS;
 
         CLI R4;
 
@@ -167,7 +175,7 @@ ENTRY(_sleep_deeper)
         STI R4;
 
         RETS = [SP++];
-        ( R7:0, P5:0 ) = [SP++];
+        (R7:4, P5:3) = [SP++];
         RTS;
 ENDPROC(_sleep_deeper)
 
@@ -188,21 +196,20 @@ ENTRY(_set_dram_srfs)
 #else                           /* SDRAM */
         P0.L = lo(EBIU_SDGCTL);
         P0.H = hi(EBIU_SDGCTL);
+        P1.L = lo(EBIU_SDSTAT);
+        P1.H = hi(EBIU_SDSTAT);
+
         R2 = [P0];
         BITSET(R2, 24); /* SRFS enter self-refresh mode */
         [P0] = R2;
         SSYNC;
 
-        P0.L = lo(EBIU_SDSTAT);
-        P0.H = hi(EBIU_SDSTAT);
 1:
-        R2 = w[P0];
+        R2 = w[P1];
         SSYNC;
         cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
         if !cc jump 1b;
 
-        P0.L = lo(EBIU_SDGCTL);
-        P0.H = hi(EBIU_SDGCTL);
         R2 = [P0];
         BITCLR(R2, 0); /* SCTLE disable CLKOUT */
         [P0] = R2;
@@ -212,6 +219,7 @@ ENDPROC(_set_dram_srfs)
 
 ENTRY(_unset_dram_srfs)
         /*  set the dram out of self refresh mode */
+
 #if defined(EBIU_RSTCTL)        /* DDR */
         P0.H = hi(EBIU_RSTCTL);
         P0.L = lo(EBIU_RSTCTL);
@@ -219,42 +227,39 @@ ENTRY(_unset_dram_srfs)
         BITCLR(R2, 3); /* clear SRREQ bit */
         [P0] = R2;
 #elif defined(EBIU_SDGCTL)      /* SDRAM */
-
-        P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
+        /* release CLKOUT from self-refresh */
+        P0.L = lo(EBIU_SDGCTL);
         P0.H = hi(EBIU_SDGCTL);
+
         R2 = [P0];
         BITSET(R2, 0); /* SCTLE enable CLKOUT */
         [P0] = R2
         SSYNC;
 
-        P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
-        P0.H = hi(EBIU_SDGCTL);
+        /* release SDRAM from self-refresh */
         R2 = [P0];
         BITCLR(R2, 24); /* clear SRFS bit */
         [P0] = R2
 #endif
+
         SSYNC;
         RTS;
 ENDPROC(_unset_dram_srfs)
 
 ENTRY(_set_sic_iwr)
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
-        defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
-        P0.H = hi(SIC_IWR0);
-        P0.L = lo(SIC_IWR0);
-        P1.H = hi(SIC_IWR1);
-        P1.L = lo(SIC_IWR1);
-        [P1] = R1;
-#if defined(CONFIG_BF54x)
-        P1.H = hi(SIC_IWR2);
-        P1.L = lo(SIC_IWR2);
-        [P1] = R2;
-#endif
+#ifdef SIC_IWR0
+        P0.H = hi(SYSMMR_BASE);
+        P0.L = lo(SYSMMR_BASE);
+        [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
+        [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
+# ifdef SIC_IWR2
+        [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
+# endif
 #else
         P0.H = hi(SIC_IWR);
         P0.L = lo(SIC_IWR);
-#endif
         [P0] = R0;
+#endif
 
         SSYNC;
         RTS;
@@ -272,206 +277,55 @@ ENDPROC(_test_pll_locked)
 
 .section .text
 
-ENTRY(_do_hibernate)
-        [--SP] = ( R7:0, P5:0 );
-        [--SP] =  RETS;
-        /* Save System MMRs */
-        R2 = R0;
-        P0.H = hi(PLL_CTL);
-        P0.L = lo(PLL_CTL);
-
-#ifdef SIC_IMASK0
-        PM_SYS_PUSH(SIC_IMASK0)
-#endif
-#ifdef SIC_IMASK1
-        PM_SYS_PUSH(SIC_IMASK1)
-#endif
-#ifdef SIC_IMASK2
-        PM_SYS_PUSH(SIC_IMASK2)
-#endif
-#ifdef SIC_IMASK
-        PM_SYS_PUSH(SIC_IMASK)
-#endif
-#ifdef SIC_IAR0
-        PM_SYS_PUSH(SIC_IAR0)
-        PM_SYS_PUSH(SIC_IAR1)
-        PM_SYS_PUSH(SIC_IAR2)
-#endif
-#ifdef SIC_IAR3
-        PM_SYS_PUSH(SIC_IAR3)
-#endif
-#ifdef SIC_IAR4
-        PM_SYS_PUSH(SIC_IAR4)
-        PM_SYS_PUSH(SIC_IAR5)
-        PM_SYS_PUSH(SIC_IAR6)
-#endif
-#ifdef SIC_IAR7
-        PM_SYS_PUSH(SIC_IAR7)
-#endif
-#ifdef SIC_IAR8
-        PM_SYS_PUSH(SIC_IAR8)
-        PM_SYS_PUSH(SIC_IAR9)
-        PM_SYS_PUSH(SIC_IAR10)
-        PM_SYS_PUSH(SIC_IAR11)
-#endif
+#define PM_REG0  R7
+#define PM_REG1  R6
+#define PM_REG2  R5
+#define PM_REG3  R4
+#define PM_REG4  R3
+#define PM_REG5  R2
+#define PM_REG6  R1
+#define PM_REG7  R0
+#define PM_REG8  P5
+#define PM_REG9  P4
+#define PM_REG10 P3
+#define PM_REG11 P2
+#define PM_REG12 P1
+#define PM_REG13 P0
+
+#define PM_REGSET0  R7:7
+#define PM_REGSET1  R7:6
+#define PM_REGSET2  R7:5
+#define PM_REGSET3  R7:4
+#define PM_REGSET4  R7:3
+#define PM_REGSET5  R7:2
+#define PM_REGSET6  R7:1
+#define PM_REGSET7  R7:0
+#define PM_REGSET8  R7:0, P5:5
+#define PM_REGSET9  R7:0, P5:4
+#define PM_REGSET10 R7:0, P5:3
+#define PM_REGSET11 R7:0, P5:2
+#define PM_REGSET12 R7:0, P5:1
+#define PM_REGSET13 R7:0, P5:0
+
+#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
+#define _PM_POP(n, x, w, base)  w[FP + ((x) - (base))] = PM_REG##n;
+#define PM_PUSH_SYNC(n)         [--sp] = (PM_REGSET##n);
+#define PM_POP_SYNC(n)          (PM_REGSET##n) = [sp++];
+#define PM_PUSH(n, x)           PM_REG##n = [FP++];
+#define PM_POP(n, x)            [FP--] = PM_REG##n;
+#define PM_CORE_PUSH(n, x)      _PM_PUSH(n, x, , COREMMR_BASE)
+#define PM_CORE_POP(n, x)       _PM_POP(n, x, , COREMMR_BASE)
+#define PM_SYS_PUSH(n, x)       _PM_PUSH(n, x, , SYSMMR_BASE)
+#define PM_SYS_POP(n, x)        _PM_POP(n, x, , SYSMMR_BASE)
+#define PM_SYS_PUSH16(n, x)     _PM_PUSH(n, x, w, SYSMMR_BASE)
+#define PM_SYS_POP16(n, x)      _PM_POP(n, x, w, SYSMMR_BASE)
 
-#ifdef SIC_IWR
-        PM_SYS_PUSH(SIC_IWR)
-#endif
-#ifdef SIC_IWR0
-        PM_SYS_PUSH(SIC_IWR0)
-#endif
-#ifdef SIC_IWR1
-        PM_SYS_PUSH(SIC_IWR1)
-#endif
-#ifdef SIC_IWR2
-        PM_SYS_PUSH(SIC_IWR2)
-#endif
-
-#ifdef PINT0_ASSIGN
-        PM_SYS_PUSH(PINT0_MASK_SET)
-        PM_SYS_PUSH(PINT1_MASK_SET)
-        PM_SYS_PUSH(PINT2_MASK_SET)
-        PM_SYS_PUSH(PINT3_MASK_SET)
-        PM_SYS_PUSH(PINT0_ASSIGN)
-        PM_SYS_PUSH(PINT1_ASSIGN)
-        PM_SYS_PUSH(PINT2_ASSIGN)
-        PM_SYS_PUSH(PINT3_ASSIGN)
-        PM_SYS_PUSH(PINT0_INVERT_SET)
-        PM_SYS_PUSH(PINT1_INVERT_SET)
-        PM_SYS_PUSH(PINT2_INVERT_SET)
-        PM_SYS_PUSH(PINT3_INVERT_SET)
-        PM_SYS_PUSH(PINT0_EDGE_SET)
-        PM_SYS_PUSH(PINT1_EDGE_SET)
-        PM_SYS_PUSH(PINT2_EDGE_SET)
-        PM_SYS_PUSH(PINT3_EDGE_SET)
-#endif
-
-        PM_SYS_PUSH(EBIU_AMBCTL0)
-        PM_SYS_PUSH(EBIU_AMBCTL1)
-        PM_SYS_PUSH16(EBIU_AMGCTL)
-
-#ifdef EBIU_FCTL
-        PM_SYS_PUSH(EBIU_MBSCTL)
-        PM_SYS_PUSH(EBIU_MODE)
-        PM_SYS_PUSH(EBIU_FCTL)
-#endif
-
-#ifdef PORTCIO_FER
-        PM_SYS_PUSH16(PORTCIO_DIR)
-        PM_SYS_PUSH16(PORTCIO_INEN)
-        PM_SYS_PUSH16(PORTCIO)
-        PM_SYS_PUSH16(PORTCIO_FER)
-        PM_SYS_PUSH16(PORTDIO_DIR)
-        PM_SYS_PUSH16(PORTDIO_INEN)
-        PM_SYS_PUSH16(PORTDIO)
-        PM_SYS_PUSH16(PORTDIO_FER)
-        PM_SYS_PUSH16(PORTEIO_DIR)
-        PM_SYS_PUSH16(PORTEIO_INEN)
-        PM_SYS_PUSH16(PORTEIO)
-        PM_SYS_PUSH16(PORTEIO_FER)
-#endif
-
-        PM_SYS_PUSH16(SYSCR)
-
-        /* Save Core MMRs */
-        P0.H = hi(SRAM_BASE_ADDRESS);
-        P0.L = lo(SRAM_BASE_ADDRESS);
-
-        PM_PUSH(DMEM_CONTROL)
-        PM_PUSH(DCPLB_ADDR0)
-        PM_PUSH(DCPLB_ADDR1)
-        PM_PUSH(DCPLB_ADDR2)
-        PM_PUSH(DCPLB_ADDR3)
-        PM_PUSH(DCPLB_ADDR4)
-        PM_PUSH(DCPLB_ADDR5)
-        PM_PUSH(DCPLB_ADDR6)
-        PM_PUSH(DCPLB_ADDR7)
-        PM_PUSH(DCPLB_ADDR8)
-        PM_PUSH(DCPLB_ADDR9)
-        PM_PUSH(DCPLB_ADDR10)
-        PM_PUSH(DCPLB_ADDR11)
-        PM_PUSH(DCPLB_ADDR12)
-        PM_PUSH(DCPLB_ADDR13)
-        PM_PUSH(DCPLB_ADDR14)
-        PM_PUSH(DCPLB_ADDR15)
-        PM_PUSH(DCPLB_DATA0)
-        PM_PUSH(DCPLB_DATA1)
-        PM_PUSH(DCPLB_DATA2)
-        PM_PUSH(DCPLB_DATA3)
-        PM_PUSH(DCPLB_DATA4)
-        PM_PUSH(DCPLB_DATA5)
-        PM_PUSH(DCPLB_DATA6)
-        PM_PUSH(DCPLB_DATA7)
-        PM_PUSH(DCPLB_DATA8)
-        PM_PUSH(DCPLB_DATA9)
-        PM_PUSH(DCPLB_DATA10)
-        PM_PUSH(DCPLB_DATA11)
-        PM_PUSH(DCPLB_DATA12)
-        PM_PUSH(DCPLB_DATA13)
-        PM_PUSH(DCPLB_DATA14)
-        PM_PUSH(DCPLB_DATA15)
-        PM_PUSH(IMEM_CONTROL)
-        PM_PUSH(ICPLB_ADDR0)
-        PM_PUSH(ICPLB_ADDR1)
-        PM_PUSH(ICPLB_ADDR2)
-        PM_PUSH(ICPLB_ADDR3)
-        PM_PUSH(ICPLB_ADDR4)
-        PM_PUSH(ICPLB_ADDR5)
-        PM_PUSH(ICPLB_ADDR6)
-        PM_PUSH(ICPLB_ADDR7)
-        PM_PUSH(ICPLB_ADDR8)
-        PM_PUSH(ICPLB_ADDR9)
-        PM_PUSH(ICPLB_ADDR10)
-        PM_PUSH(ICPLB_ADDR11)
-        PM_PUSH(ICPLB_ADDR12)
-        PM_PUSH(ICPLB_ADDR13)
-        PM_PUSH(ICPLB_ADDR14)
-        PM_PUSH(ICPLB_ADDR15)
-        PM_PUSH(ICPLB_DATA0)
-        PM_PUSH(ICPLB_DATA1)
-        PM_PUSH(ICPLB_DATA2)
-        PM_PUSH(ICPLB_DATA3)
-        PM_PUSH(ICPLB_DATA4)
-        PM_PUSH(ICPLB_DATA5)
-        PM_PUSH(ICPLB_DATA6)
-        PM_PUSH(ICPLB_DATA7)
-        PM_PUSH(ICPLB_DATA8)
-        PM_PUSH(ICPLB_DATA9)
-        PM_PUSH(ICPLB_DATA10)
-        PM_PUSH(ICPLB_DATA11)
-        PM_PUSH(ICPLB_DATA12)
-        PM_PUSH(ICPLB_DATA13)
-        PM_PUSH(ICPLB_DATA14)
-        PM_PUSH(ICPLB_DATA15)
-        PM_PUSH(EVT0)
-        PM_PUSH(EVT1)
-        PM_PUSH(EVT2)
-        PM_PUSH(EVT3)
-        PM_PUSH(EVT4)
-        PM_PUSH(EVT5)
-        PM_PUSH(EVT6)
-        PM_PUSH(EVT7)
-        PM_PUSH(EVT8)
-        PM_PUSH(EVT9)
-        PM_PUSH(EVT10)
-        PM_PUSH(EVT11)
-        PM_PUSH(EVT12)
-        PM_PUSH(EVT13)
-        PM_PUSH(EVT14)
-        PM_PUSH(EVT15)
-        PM_PUSH(IMASK)
-        PM_PUSH(ILAT)
-        PM_PUSH(IPRIO)
-        PM_PUSH(TCNTL)
-        PM_PUSH(TPERIOD)
-        PM_PUSH(TSCALE)
-        PM_PUSH(TCOUNT)
-        PM_PUSH(TBUFCTL)
-
-        /* Save Core Registers */
-        [--sp] = SYSCFG;
-        [--sp] = ( R7:0, P5:0 );
+ENTRY(_do_hibernate)
+        /*
+         * Save the core regs early so we can blow them away when
+         * saving/restoring MMR states
+         */
+        [--sp] = (R7:0, P5:0);
         [--sp] = fp;
         [--sp] = usp;
 
@@ -506,47 +360,497 @@ ENTRY(_do_hibernate)
         [--sp] = LB0;
         [--sp] = LB1;
 
+        /* We can't push RETI directly as that'll change IPEND[4] */
+        r7 = RETI;
+        [--sp] = RETS;
         [--sp] = ASTAT;
         [--sp] = CYCLES;
         [--sp] = CYCLES2;
-
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
+        [--sp] = SYSCFG;
         [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
         [--sp] = SEQSTAT;
+        [--sp] = r7;
+
+        /* Save first func arg in M3 */
+        M3 = R0;
+
+        /* Save system MMRs */
+        FP.H = hi(SYSMMR_BASE);
+        FP.L = lo(SYSMMR_BASE);
+
+#ifdef SIC_IMASK0
+        PM_SYS_PUSH(0, SIC_IMASK0)
+        PM_SYS_PUSH(1, SIC_IMASK1)
+# ifdef SIC_IMASK2
+        PM_SYS_PUSH(2, SIC_IMASK2)
+# endif
+#else
+        PM_SYS_PUSH(0, SIC_IMASK)
+#endif
+#ifdef SIC_IAR0
+        PM_SYS_PUSH(3, SIC_IAR0)
+        PM_SYS_PUSH(4, SIC_IAR1)
+        PM_SYS_PUSH(5, SIC_IAR2)
+#endif
+#ifdef SIC_IAR3
+        PM_SYS_PUSH(6, SIC_IAR3)
+#endif
+#ifdef SIC_IAR4
+        PM_SYS_PUSH(7, SIC_IAR4)
+        PM_SYS_PUSH(8, SIC_IAR5)
+        PM_SYS_PUSH(9, SIC_IAR6)
+#endif
+#ifdef SIC_IAR7
+        PM_SYS_PUSH(10, SIC_IAR7)
+#endif
+#ifdef SIC_IAR8
+        PM_SYS_PUSH(11, SIC_IAR8)
+        PM_SYS_PUSH(12, SIC_IAR9)
+        PM_SYS_PUSH(13, SIC_IAR10)
+#endif
+        PM_PUSH_SYNC(13)
+#ifdef SIC_IAR11
+        PM_SYS_PUSH(0, SIC_IAR11)
+#endif
+
+#ifdef SIC_IWR
+        PM_SYS_PUSH(1, SIC_IWR)
+#endif
+#ifdef SIC_IWR0
+        PM_SYS_PUSH(1, SIC_IWR0)
+#endif
+#ifdef SIC_IWR1
+        PM_SYS_PUSH(2, SIC_IWR1)
+#endif
+#ifdef SIC_IWR2
+        PM_SYS_PUSH(3, SIC_IWR2)
+#endif
+
+#ifdef PINT0_ASSIGN
+        PM_SYS_PUSH(4, PINT0_MASK_SET)
+        PM_SYS_PUSH(5, PINT1_MASK_SET)
+        PM_SYS_PUSH(6, PINT2_MASK_SET)
+        PM_SYS_PUSH(7, PINT3_MASK_SET)
+        PM_SYS_PUSH(8, PINT0_ASSIGN)
+        PM_SYS_PUSH(9, PINT1_ASSIGN)
+        PM_SYS_PUSH(10, PINT2_ASSIGN)
+        PM_SYS_PUSH(11, PINT3_ASSIGN)
+        PM_SYS_PUSH(12, PINT0_INVERT_SET)
+        PM_SYS_PUSH(13, PINT1_INVERT_SET)
+        PM_PUSH_SYNC(13)
+        PM_SYS_PUSH(0, PINT2_INVERT_SET)
+        PM_SYS_PUSH(1, PINT3_INVERT_SET)
+        PM_SYS_PUSH(2, PINT0_EDGE_SET)
+        PM_SYS_PUSH(3, PINT1_EDGE_SET)
+        PM_SYS_PUSH(4, PINT2_EDGE_SET)
+        PM_SYS_PUSH(5, PINT3_EDGE_SET)
+#endif
+
+        PM_SYS_PUSH16(6, SYSCR)
+
+        PM_SYS_PUSH16(7, EBIU_AMGCTL)
+        PM_SYS_PUSH(8, EBIU_AMBCTL0)
+        PM_SYS_PUSH(9, EBIU_AMBCTL1)
+#ifdef EBIU_FCTL
+        PM_SYS_PUSH(10, EBIU_MBSCTL)
+        PM_SYS_PUSH(11, EBIU_MODE)
+        PM_SYS_PUSH(12, EBIU_FCTL)
+        PM_PUSH_SYNC(12)
+#else
+        PM_PUSH_SYNC(9)
+#endif
+
+        /* Save Core MMRs */
+        I0.H = hi(COREMMR_BASE);
+        I0.L = lo(COREMMR_BASE);
+        I1 = I0;
+        I2 = I0;
+        I3 = I0;
+        B0 = I0;
+        B1 = I0;
+        B2 = I0;
+        B3 = I0;
+        I1.L = lo(DCPLB_ADDR0);
+        I2.L = lo(DCPLB_DATA0);
+        I3.L = lo(ICPLB_ADDR0);
+        B0.L = lo(ICPLB_DATA0);
+        B1.L = lo(EVT2);
+        B2.L = lo(IMASK);
+        B3.L = lo(TCNTL);
+
+        /* DCPLB Addr */
+        FP = I1;
+        PM_PUSH(0, DCPLB_ADDR0)
+        PM_PUSH(1, DCPLB_ADDR1)
+        PM_PUSH(2, DCPLB_ADDR2)
+        PM_PUSH(3, DCPLB_ADDR3)
+        PM_PUSH(4, DCPLB_ADDR4)
+        PM_PUSH(5, DCPLB_ADDR5)
+        PM_PUSH(6, DCPLB_ADDR6)
+        PM_PUSH(7, DCPLB_ADDR7)
+        PM_PUSH(8, DCPLB_ADDR8)
+        PM_PUSH(9, DCPLB_ADDR9)
+        PM_PUSH(10, DCPLB_ADDR10)
+        PM_PUSH(11, DCPLB_ADDR11)
+        PM_PUSH(12, DCPLB_ADDR12)
+        PM_PUSH(13, DCPLB_ADDR13)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, DCPLB_ADDR14)
+        PM_PUSH(1, DCPLB_ADDR15)
+
+        /* DCPLB Data */
+        FP = I2;
+        PM_PUSH(2, DCPLB_DATA0)
+        PM_PUSH(3, DCPLB_DATA1)
+        PM_PUSH(4, DCPLB_DATA2)
+        PM_PUSH(5, DCPLB_DATA3)
+        PM_PUSH(6, DCPLB_DATA4)
+        PM_PUSH(7, DCPLB_DATA5)
+        PM_PUSH(8, DCPLB_DATA6)
+        PM_PUSH(9, DCPLB_DATA7)
+        PM_PUSH(10, DCPLB_DATA8)
+        PM_PUSH(11, DCPLB_DATA9)
+        PM_PUSH(12, DCPLB_DATA10)
+        PM_PUSH(13, DCPLB_DATA11)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, DCPLB_DATA12)
+        PM_PUSH(1, DCPLB_DATA13)
+        PM_PUSH(2, DCPLB_DATA14)
+        PM_PUSH(3, DCPLB_DATA15)
+
+        /* ICPLB Addr */
+        FP = I3;
+        PM_PUSH(4, ICPLB_ADDR0)
+        PM_PUSH(5, ICPLB_ADDR1)
+        PM_PUSH(6, ICPLB_ADDR2)
+        PM_PUSH(7, ICPLB_ADDR3)
+        PM_PUSH(8, ICPLB_ADDR4)
+        PM_PUSH(9, ICPLB_ADDR5)
+        PM_PUSH(10, ICPLB_ADDR6)
+        PM_PUSH(11, ICPLB_ADDR7)
+        PM_PUSH(12, ICPLB_ADDR8)
+        PM_PUSH(13, ICPLB_ADDR9)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, ICPLB_ADDR10)
+        PM_PUSH(1, ICPLB_ADDR11)
+        PM_PUSH(2, ICPLB_ADDR12)
+        PM_PUSH(3, ICPLB_ADDR13)
+        PM_PUSH(4, ICPLB_ADDR14)
+        PM_PUSH(5, ICPLB_ADDR15)
+
+        /* ICPLB Data */
+        FP = B0;
+        PM_PUSH(6, ICPLB_DATA0)
+        PM_PUSH(7, ICPLB_DATA1)
+        PM_PUSH(8, ICPLB_DATA2)
+        PM_PUSH(9, ICPLB_DATA3)
+        PM_PUSH(10, ICPLB_DATA4)
+        PM_PUSH(11, ICPLB_DATA5)
+        PM_PUSH(12, ICPLB_DATA6)
+        PM_PUSH(13, ICPLB_DATA7)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, ICPLB_DATA8)
+        PM_PUSH(1, ICPLB_DATA9)
+        PM_PUSH(2, ICPLB_DATA10)
+        PM_PUSH(3, ICPLB_DATA11)
+        PM_PUSH(4, ICPLB_DATA12)
+        PM_PUSH(5, ICPLB_DATA13)
+        PM_PUSH(6, ICPLB_DATA14)
+        PM_PUSH(7, ICPLB_DATA15)
+
+        /* Event Vectors */
+        FP = B1;
+        PM_PUSH(8, EVT2)
+        PM_PUSH(9, EVT3)
+        FP += 4;        /* EVT4 */
+        PM_PUSH(10, EVT5)
+        PM_PUSH(11, EVT6)
+        PM_PUSH(12, EVT7)
+        PM_PUSH(13, EVT8)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, EVT9)
+        PM_PUSH(1, EVT10)
+        PM_PUSH(2, EVT11)
+        PM_PUSH(3, EVT12)
+        PM_PUSH(4, EVT13)
+        PM_PUSH(5, EVT14)
+        PM_PUSH(6, EVT15)
+
+        /* CEC */
+        FP = B2;
+        PM_PUSH(7, IMASK)
+        FP += 4;        /* IPEND */
+        PM_PUSH(8, ILAT)
+        PM_PUSH(9, IPRIO)
+
+        /* Core Timer */
+        FP = B3;
+        PM_PUSH(10, TCNTL)
+        PM_PUSH(11, TPERIOD)
+        PM_PUSH(12, TSCALE)
+        PM_PUSH(13, TCOUNT)
+        PM_PUSH_SYNC(13)
+
+        /* Misc non-contiguous registers */
+        FP = I0;
+        PM_CORE_PUSH(0, DMEM_CONTROL);
+        PM_CORE_PUSH(1, IMEM_CONTROL);
+        PM_CORE_PUSH(2, TBUFCTL);
+        PM_PUSH_SYNC(2)
+
+        /* Setup args to hibernate mode early for pipeline optimization */
+        R0 = M3;
+        P1.H = _hibernate_mode;
+        P1.L = _hibernate_mode;
 
         /* Save Magic, return address and Stack Pointer */
-        P0.H = 0;
-        P0.L = 0;
-        R0.H = 0xDEAD;  /* Hibernate Magic */
-        R0.L = 0xBEEF;
-        [P0++] = R0;    /* Store Hibernate Magic */
-        R0.H = .Lpm_resume_here;
-        R0.L = .Lpm_resume_here;
-        [P0++] = R0;    /* Save Return Address */
+        P0 = 0;
+        R1.H = 0xDEAD;  /* Hibernate Magic */
+        R1.L = 0xBEEF;
+        R2.H = .Lpm_resume_here;
+        R2.L = .Lpm_resume_here;
+        [P0++] = R1;    /* Store Hibernate Magic */
+        [P0++] = R2;    /* Save Return Address */
         [P0++] = SP;    /* Save Stack Pointer */
-        P0.H = _hibernate_mode;
-        P0.L = _hibernate_mode;
-        R0 = R2;
-        call (P0); /* Goodbye */
+
+        /* Must use an indirect call as we need to jump to L1 */
+        call (P1); /* Goodbye */
 
 .Lpm_resume_here:
 
+        /* Restore Core MMRs */
+        I0.H = hi(COREMMR_BASE);
+        I0.L = lo(COREMMR_BASE);
+        I1 = I0;
+        I2 = I0;
+        I3 = I0;
+        B0 = I0;
+        B1 = I0;
+        B2 = I0;
+        B3 = I0;
+        I1.L = lo(DCPLB_ADDR15);
+        I2.L = lo(DCPLB_DATA15);
+        I3.L = lo(ICPLB_ADDR15);
+        B0.L = lo(ICPLB_DATA15);
+        B1.L = lo(EVT15);
+        B2.L = lo(IPRIO);
+        B3.L = lo(TCOUNT);
+
+        /* Misc non-contiguous registers */
+        FP = I0;
+        PM_POP_SYNC(2)
+        PM_CORE_POP(2, TBUFCTL)
+        PM_CORE_POP(1, IMEM_CONTROL)
+        PM_CORE_POP(0, DMEM_CONTROL)
+
+        /* Core Timer */
+        PM_POP_SYNC(13)
+        FP = B3;
+        PM_POP(13, TCOUNT)
+        PM_POP(12, TSCALE)
+        PM_POP(11, TPERIOD)
+        PM_POP(10, TCNTL)
+
+        /* CEC */
+        FP = B2;
+        PM_POP(9, IPRIO)
+        PM_POP(8, ILAT)
+        FP += -4;       /* IPEND */
+        PM_POP(7, IMASK)
+
+        /* Event Vectors */
+        FP = B1;
+        PM_POP(6, EVT15)
+        PM_POP(5, EVT14)
+        PM_POP(4, EVT13)
+        PM_POP(3, EVT12)
+        PM_POP(2, EVT11)
+        PM_POP(1, EVT10)
+        PM_POP(0, EVT9)
+        PM_POP_SYNC(13)
+        PM_POP(13, EVT8)
+        PM_POP(12, EVT7)
+        PM_POP(11, EVT6)
+        PM_POP(10, EVT5)
+        FP += -4;       /* EVT4 */
+        PM_POP(9, EVT3)
+        PM_POP(8, EVT2)
+
+        /* ICPLB Data */
+        FP = B0;
+        PM_POP(7, ICPLB_DATA15)
+        PM_POP(6, ICPLB_DATA14)
+        PM_POP(5, ICPLB_DATA13)
+        PM_POP(4, ICPLB_DATA12)
+        PM_POP(3, ICPLB_DATA11)
+        PM_POP(2, ICPLB_DATA10)
+        PM_POP(1, ICPLB_DATA9)
+        PM_POP(0, ICPLB_DATA8)
+        PM_POP_SYNC(13)
+        PM_POP(13, ICPLB_DATA7)
+        PM_POP(12, ICPLB_DATA6)
+        PM_POP(11, ICPLB_DATA5)
+        PM_POP(10, ICPLB_DATA4)
+        PM_POP(9, ICPLB_DATA3)
+        PM_POP(8, ICPLB_DATA2)
+        PM_POP(7, ICPLB_DATA1)
+        PM_POP(6, ICPLB_DATA0)
+
+        /* ICPLB Addr */
+        FP = I3;
+        PM_POP(5, ICPLB_ADDR15)
+        PM_POP(4, ICPLB_ADDR14)
+        PM_POP(3, ICPLB_ADDR13)
+        PM_POP(2, ICPLB_ADDR12)
+        PM_POP(1, ICPLB_ADDR11)
+        PM_POP(0, ICPLB_ADDR10)
+        PM_POP_SYNC(13)
+        PM_POP(13, ICPLB_ADDR9)
+        PM_POP(12, ICPLB_ADDR8)
+        PM_POP(11, ICPLB_ADDR7)
+        PM_POP(10, ICPLB_ADDR6)
+        PM_POP(9, ICPLB_ADDR5)
+        PM_POP(8, ICPLB_ADDR4)
+        PM_POP(7, ICPLB_ADDR3)
+        PM_POP(6, ICPLB_ADDR2)
+        PM_POP(5, ICPLB_ADDR1)
+        PM_POP(4, ICPLB_ADDR0)
+
+        /* DCPLB Data */
+        FP = I2;
+        PM_POP(3, DCPLB_DATA15)
+        PM_POP(2, DCPLB_DATA14)
+        PM_POP(1, DCPLB_DATA13)
+        PM_POP(0, DCPLB_DATA12)
+        PM_POP_SYNC(13)
+        PM_POP(13, DCPLB_DATA11)
+        PM_POP(12, DCPLB_DATA10)
+        PM_POP(11, DCPLB_DATA9)
+        PM_POP(10, DCPLB_DATA8)
+        PM_POP(9, DCPLB_DATA7)
+        PM_POP(8, DCPLB_DATA6)
+        PM_POP(7, DCPLB_DATA5)
+        PM_POP(6, DCPLB_DATA4)
+        PM_POP(5, DCPLB_DATA3)
+        PM_POP(4, DCPLB_DATA2)
+        PM_POP(3, DCPLB_DATA1)
+        PM_POP(2, DCPLB_DATA0)
+
+        /* DCPLB Addr */
+        FP = I1;
+        PM_POP(1, DCPLB_ADDR15)
+        PM_POP(0, DCPLB_ADDR14)
+        PM_POP_SYNC(13)
+        PM_POP(13, DCPLB_ADDR13)
+        PM_POP(12, DCPLB_ADDR12)
+        PM_POP(11, DCPLB_ADDR11)
+        PM_POP(10, DCPLB_ADDR10)
+        PM_POP(9, DCPLB_ADDR9)
+        PM_POP(8, DCPLB_ADDR8)
+        PM_POP(7, DCPLB_ADDR7)
+        PM_POP(6, DCPLB_ADDR6)
+        PM_POP(5, DCPLB_ADDR5)
+        PM_POP(4, DCPLB_ADDR4)
+        PM_POP(3, DCPLB_ADDR3)
+        PM_POP(2, DCPLB_ADDR2)
+        PM_POP(1, DCPLB_ADDR1)
+        PM_POP(0, DCPLB_ADDR0)
+
+        /* Restore System MMRs */
+        FP.H = hi(SYSMMR_BASE);
+        FP.L = lo(SYSMMR_BASE);
+
+#ifdef EBIU_FCTL
+        PM_POP_SYNC(12)
+        PM_SYS_POP(12, EBIU_FCTL)
+        PM_SYS_POP(11, EBIU_MODE)
+        PM_SYS_POP(10, EBIU_MBSCTL)
+#else
+        PM_POP_SYNC(9)
+#endif
+        PM_SYS_POP(9, EBIU_AMBCTL1)
+        PM_SYS_POP(8, EBIU_AMBCTL0)
+        PM_SYS_POP16(7, EBIU_AMGCTL)
+
+        PM_SYS_POP16(6, SYSCR)
+
+#ifdef PINT0_ASSIGN
+        PM_SYS_POP(5, PINT3_EDGE_SET)
+        PM_SYS_POP(4, PINT2_EDGE_SET)
+        PM_SYS_POP(3, PINT1_EDGE_SET)
+        PM_SYS_POP(2, PINT0_EDGE_SET)
+        PM_SYS_POP(1, PINT3_INVERT_SET)
+        PM_SYS_POP(0, PINT2_INVERT_SET)
+        PM_POP_SYNC(13)
+        PM_SYS_POP(13, PINT1_INVERT_SET)
+        PM_SYS_POP(12, PINT0_INVERT_SET)
+        PM_SYS_POP(11, PINT3_ASSIGN)
+        PM_SYS_POP(10, PINT2_ASSIGN)
+        PM_SYS_POP(9, PINT1_ASSIGN)
+        PM_SYS_POP(8, PINT0_ASSIGN)
+        PM_SYS_POP(7, PINT3_MASK_SET)
+        PM_SYS_POP(6, PINT2_MASK_SET)
+        PM_SYS_POP(5, PINT1_MASK_SET)
+        PM_SYS_POP(4, PINT0_MASK_SET)
+#endif
+
+#ifdef SIC_IWR2
+        PM_SYS_POP(3, SIC_IWR2)
+#endif
+#ifdef SIC_IWR1
+        PM_SYS_POP(2, SIC_IWR1)
+#endif
+#ifdef SIC_IWR0
+        PM_SYS_POP(1, SIC_IWR0)
+#endif
+#ifdef SIC_IWR
+        PM_SYS_POP(1, SIC_IWR)
+#endif
+
+#ifdef SIC_IAR11
+        PM_SYS_POP(0, SIC_IAR11)
+#endif
+        PM_POP_SYNC(13)
+#ifdef SIC_IAR8
+        PM_SYS_POP(13, SIC_IAR10)
+        PM_SYS_POP(12, SIC_IAR9)
+        PM_SYS_POP(11, SIC_IAR8)
+#endif
+#ifdef SIC_IAR7
+        PM_SYS_POP(10, SIC_IAR7)
+#endif
+#ifdef SIC_IAR6
+        PM_SYS_POP(9, SIC_IAR6)
+        PM_SYS_POP(8, SIC_IAR5)
+        PM_SYS_POP(7, SIC_IAR4)
+#endif
+#ifdef SIC_IAR3
+        PM_SYS_POP(6, SIC_IAR3)
+#endif
+#ifdef SIC_IAR0
+        PM_SYS_POP(5, SIC_IAR2)
+        PM_SYS_POP(4, SIC_IAR1)
+        PM_SYS_POP(3, SIC_IAR0)
+#endif
+#ifdef SIC_IMASK0
+# ifdef SIC_IMASK2
+        PM_SYS_POP(2, SIC_IMASK2)
+# endif
+        PM_SYS_POP(1, SIC_IMASK1)
+        PM_SYS_POP(0, SIC_IMASK0)
+#else
+        PM_SYS_POP(0, SIC_IMASK)
+#endif
+
         /* Restore Core Registers */
+        RETI = [sp++];
         SEQSTAT = [sp++];
-        RETE = [sp++];
-        RETN = [sp++];
         RETX = [sp++];
-        r0 = [sp++];
-        RETI = r0;
-        RETS = [sp++];
-
+        SYSCFG = [sp++];
         CYCLES2 = [sp++];
         CYCLES = [sp++];
         ASTAT = [sp++];
+        RETS = [sp++];
 
         LB1 = [sp++];
         LB0 = [sp++];
@@ -581,204 +885,10 @@ ENTRY(_do_hibernate)
 
         usp = [sp++];
         fp = [sp++];
-
-        ( R7 : 0, P5 : 0) = [ SP ++ ];
-        SYSCFG = [sp++];
-
-        /* Restore Core MMRs */
-
-        PM_POP(TBUFCTL)
-        PM_POP(TCOUNT)
-        PM_POP(TSCALE)
-        PM_POP(TPERIOD)
-        PM_POP(TCNTL)
-        PM_POP(IPRIO)
-        PM_POP(ILAT)
-        PM_POP(IMASK)
-        PM_POP(EVT15)
-        PM_POP(EVT14)
-        PM_POP(EVT13)
-        PM_POP(EVT12)
-        PM_POP(EVT11)
-        PM_POP(EVT10)
-        PM_POP(EVT9)
-        PM_POP(EVT8)
-        PM_POP(EVT7)
-        PM_POP(EVT6)
-        PM_POP(EVT5)
-        PM_POP(EVT4)
-        PM_POP(EVT3)
-        PM_POP(EVT2)
-        PM_POP(EVT1)
-        PM_POP(EVT0)
-        PM_POP(ICPLB_DATA15)
-        PM_POP(ICPLB_DATA14)
-        PM_POP(ICPLB_DATA13)
-        PM_POP(ICPLB_DATA12)
-        PM_POP(ICPLB_DATA11)
-        PM_POP(ICPLB_DATA10)
-        PM_POP(ICPLB_DATA9)
-        PM_POP(ICPLB_DATA8)
-        PM_POP(ICPLB_DATA7)
-        PM_POP(ICPLB_DATA6)
-        PM_POP(ICPLB_DATA5)
-        PM_POP(ICPLB_DATA4)
-        PM_POP(ICPLB_DATA3)
-        PM_POP(ICPLB_DATA2)
-        PM_POP(ICPLB_DATA1)
-        PM_POP(ICPLB_DATA0)
-        PM_POP(ICPLB_ADDR15)
-        PM_POP(ICPLB_ADDR14)
-        PM_POP(ICPLB_ADDR13)
-        PM_POP(ICPLB_ADDR12)
-        PM_POP(ICPLB_ADDR11)
-        PM_POP(ICPLB_ADDR10)
-        PM_POP(ICPLB_ADDR9)
-        PM_POP(ICPLB_ADDR8)
-        PM_POP(ICPLB_ADDR7)
-        PM_POP(ICPLB_ADDR6)
-        PM_POP(ICPLB_ADDR5)
-        PM_POP(ICPLB_ADDR4)
-        PM_POP(ICPLB_ADDR3)
-        PM_POP(ICPLB_ADDR2)
-        PM_POP(ICPLB_ADDR1)
-        PM_POP(ICPLB_ADDR0)
-        PM_POP(IMEM_CONTROL)
-        PM_POP(DCPLB_DATA15)
-        PM_POP(DCPLB_DATA14)
-        PM_POP(DCPLB_DATA13)
-        PM_POP(DCPLB_DATA12)
-        PM_POP(DCPLB_DATA11)
-        PM_POP(DCPLB_DATA10)
-        PM_POP(DCPLB_DATA9)
-        PM_POP(DCPLB_DATA8)
-        PM_POP(DCPLB_DATA7)
-        PM_POP(DCPLB_DATA6)
-        PM_POP(DCPLB_DATA5)
-        PM_POP(DCPLB_DATA4)
-        PM_POP(DCPLB_DATA3)
-        PM_POP(DCPLB_DATA2)
-        PM_POP(DCPLB_DATA1)
-        PM_POP(DCPLB_DATA0)
-        PM_POP(DCPLB_ADDR15)
-        PM_POP(DCPLB_ADDR14)
-        PM_POP(DCPLB_ADDR13)
-        PM_POP(DCPLB_ADDR12)
-        PM_POP(DCPLB_ADDR11)
-        PM_POP(DCPLB_ADDR10)
-        PM_POP(DCPLB_ADDR9)
-        PM_POP(DCPLB_ADDR8)
-        PM_POP(DCPLB_ADDR7)
-        PM_POP(DCPLB_ADDR6)
-        PM_POP(DCPLB_ADDR5)
-        PM_POP(DCPLB_ADDR4)
-        PM_POP(DCPLB_ADDR3)
-        PM_POP(DCPLB_ADDR2)
-        PM_POP(DCPLB_ADDR1)
-        PM_POP(DCPLB_ADDR0)
-        PM_POP(DMEM_CONTROL)
-
-        /* Restore System MMRs */
-
-        P0.H = hi(PLL_CTL);
-        P0.L = lo(PLL_CTL);
-        PM_SYS_POP16(SYSCR)
-
-#ifdef PORTCIO_FER
-        PM_SYS_POP16(PORTEIO_FER)
-        PM_SYS_POP16(PORTEIO)
-        PM_SYS_POP16(PORTEIO_INEN)
-        PM_SYS_POP16(PORTEIO_DIR)
-        PM_SYS_POP16(PORTDIO_FER)
-        PM_SYS_POP16(PORTDIO)
-        PM_SYS_POP16(PORTDIO_INEN)
-        PM_SYS_POP16(PORTDIO_DIR)
-        PM_SYS_POP16(PORTCIO_FER)
-        PM_SYS_POP16(PORTCIO)
-        PM_SYS_POP16(PORTCIO_INEN)
-        PM_SYS_POP16(PORTCIO_DIR)
-#endif
-
-#ifdef EBIU_FCTL
-        PM_SYS_POP(EBIU_FCTL)
-        PM_SYS_POP(EBIU_MODE)
-        PM_SYS_POP(EBIU_MBSCTL)
-#endif
-        PM_SYS_POP16(EBIU_AMGCTL)
-        PM_SYS_POP(EBIU_AMBCTL1)
-        PM_SYS_POP(EBIU_AMBCTL0)
-
-#ifdef PINT0_ASSIGN
-        PM_SYS_POP(PINT3_EDGE_SET)
-        PM_SYS_POP(PINT2_EDGE_SET)
-        PM_SYS_POP(PINT1_EDGE_SET)
-        PM_SYS_POP(PINT0_EDGE_SET)
-        PM_SYS_POP(PINT3_INVERT_SET)
-        PM_SYS_POP(PINT2_INVERT_SET)
-        PM_SYS_POP(PINT1_INVERT_SET)
-        PM_SYS_POP(PINT0_INVERT_SET)
-        PM_SYS_POP(PINT3_ASSIGN)
-        PM_SYS_POP(PINT2_ASSIGN)
-        PM_SYS_POP(PINT1_ASSIGN)
-        PM_SYS_POP(PINT0_ASSIGN)
-        PM_SYS_POP(PINT3_MASK_SET)
-        PM_SYS_POP(PINT2_MASK_SET)
-        PM_SYS_POP(PINT1_MASK_SET)
-        PM_SYS_POP(PINT0_MASK_SET)
-#endif
-
-#ifdef SIC_IWR2
-        PM_SYS_POP(SIC_IWR2)
-#endif
-#ifdef SIC_IWR1
-        PM_SYS_POP(SIC_IWR1)
-#endif
-#ifdef SIC_IWR0
-        PM_SYS_POP(SIC_IWR0)
-#endif
-#ifdef SIC_IWR
-        PM_SYS_POP(SIC_IWR)
-#endif
-
-#ifdef SIC_IAR8
-        PM_SYS_POP(SIC_IAR11)
-        PM_SYS_POP(SIC_IAR10)
-        PM_SYS_POP(SIC_IAR9)
-        PM_SYS_POP(SIC_IAR8)
-#endif
-#ifdef SIC_IAR7
-        PM_SYS_POP(SIC_IAR7)
-#endif
-#ifdef SIC_IAR6
-        PM_SYS_POP(SIC_IAR6)
-        PM_SYS_POP(SIC_IAR5)
-        PM_SYS_POP(SIC_IAR4)
-#endif
-#ifdef SIC_IAR3
-        PM_SYS_POP(SIC_IAR3)
-#endif
-#ifdef SIC_IAR0
-        PM_SYS_POP(SIC_IAR2)
-        PM_SYS_POP(SIC_IAR1)
-        PM_SYS_POP(SIC_IAR0)
-#endif
-#ifdef SIC_IMASK
-        PM_SYS_POP(SIC_IMASK)
-#endif
-#ifdef SIC_IMASK2
-        PM_SYS_POP(SIC_IMASK2)
-#endif
-#ifdef SIC_IMASK1
-        PM_SYS_POP(SIC_IMASK1)
-#endif
-#ifdef SIC_IMASK0
-        PM_SYS_POP(SIC_IMASK0)
-#endif
+        (R7:0, P5:0) = [sp++];
 
         [--sp] = RETI;  /* Clear Global Interrupt Disable */
         SP += 4;
 
-        RETS = [SP++];
-        ( R7:0, P5:0 ) = [SP++];
         RTS;
 ENDPROC(_do_hibernate)
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 76de5724c1e3..8b4d98854403 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -85,37 +85,25 @@ ENTRY(__start)
         SSYNC;
 
         /* in case of double faults, save a few things */
-        p0.l = _init_retx;
-        p0.h = _init_retx;
-        R0 = RETX;
-        [P0] = R0;
-
+        p1.l = _initial_pda;
+        p1.h = _initial_pda;
+        r4 = RETX;
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
         /* Only save these if we are storing them,
          * This happens here, since L1 gets clobbered
          * below
          */
         GET_PDA(p0, r0);
-        r5 = [p0 + PDA_DF_RETX];
-        p1.l = _init_saved_retx;
-        p1.h = _init_saved_retx;
-        [p1] = r5;
-
-        r5 = [p0 + PDA_DF_DCPLB];
-        p1.l = _init_saved_dcplb_fault_addr;
-        p1.h = _init_saved_dcplb_fault_addr;
-        [p1] = r5;
-
-        r5 = [p0 + PDA_DF_ICPLB];
-        p1.l = _init_saved_icplb_fault_addr;
-        p1.h = _init_saved_icplb_fault_addr;
-        [p1] = r5;
-
-        r5 = [p0 + PDA_DF_SEQSTAT];
-        p1.l = _init_saved_seqstat;
-        p1.h = _init_saved_seqstat;
-        [p1] = r5;
+        r0 = [p0 + PDA_DF_RETX];
+        r1 = [p0 + PDA_DF_DCPLB];
+        r2 = [p0 + PDA_DF_ICPLB];
+        r3 = [p0 + PDA_DF_SEQSTAT];
+        [p1 + PDA_INIT_DF_RETX] = r0;
+        [p1 + PDA_INIT_DF_DCPLB] = r1;
+        [p1 + PDA_INIT_DF_ICPLB] = r2;
+        [p1 + PDA_INIT_DF_SEQSTAT] = r3;
 #endif
+        [p1 + PDA_INIT_RETX] = r4;
 
         /* Initialize stack pointer */
         sp.l = _init_thread_union + THREAD_SIZE;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 1177369f9922..332dace6af34 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -444,7 +444,7 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 extern void bfin_gpio_irq_prepare(unsigned gpio);
 
-#if !defined(CONFIG_BF54x)
+#if !BFIN_GPIO_PINT
 
 static void bfin_gpio_ack_irq(struct irq_data *d)
 {
@@ -633,7 +633,7 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
         bfin_demux_gpio_block(irq);
 }
 
-#else                           /* CONFIG_BF54x */
+#else
 
 #define NR_PINT_SYS_IRQS        4
 #define NR_PINT_BITS            32
@@ -647,24 +647,11 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
 static unsigned char irq2pint_lut[NR_PINTS];
 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 
-struct pin_int_t {
-        unsigned int mask_set;
-        unsigned int mask_clear;
-        unsigned int request;
-        unsigned int assign;
-        unsigned int edge_set;
-        unsigned int edge_clear;
-        unsigned int invert_set;
-        unsigned int invert_clear;
-        unsigned int pinstate;
-        unsigned int latch;
-};
-
-static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
-        (struct pin_int_t *)PINT0_MASK_SET,
-        (struct pin_int_t *)PINT1_MASK_SET,
-        (struct pin_int_t *)PINT2_MASK_SET,
-        (struct pin_int_t *)PINT3_MASK_SET,
+static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
+        (struct bfin_pint_regs *)PINT0_MASK_SET,
+        (struct bfin_pint_regs *)PINT1_MASK_SET,
+        (struct bfin_pint_regs *)PINT2_MASK_SET,
+        (struct bfin_pint_regs *)PINT3_MASK_SET,
 };
 
 inline unsigned int get_irq_base(u32 bank, u8 bmap)
@@ -981,7 +968,7 @@ int __init init_arch_irq(void)
 
         local_irq_disable();
 
-#ifdef CONFIG_BF54x
+#if BFIN_GPIO_PINT
 # ifdef CONFIG_PINTx_REASSIGN
         pint[0]->assign = CONFIG_PINT0_ASSIGN;
         pint[1]->assign = CONFIG_PINT1_ASSIGN;
@@ -999,16 +986,16 @@ int __init init_arch_irq(void)
                         irq_set_chip(irq, &bfin_internal_irqchip);
 
                 switch (irq) {
-#if defined(BF537_FAMILY)
-                case IRQ_PH_INTA_MAC_RX:
-                case IRQ_PF_INTA_PG_INTA:
-#elif defined(BF533_FAMILY)
-                case IRQ_PROG_INTA:
-#elif defined(CONFIG_BF54x)
+#if BFIN_GPIO_PINT
                 case IRQ_PINT0:
                 case IRQ_PINT1:
                 case IRQ_PINT2:
                 case IRQ_PINT3:
+#elif defined(BF537_FAMILY)
+                case IRQ_PH_INTA_MAC_RX:
+                case IRQ_PF_INTA_PG_INTA:
+#elif defined(BF533_FAMILY)
+                case IRQ_PROG_INTA:
 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
                 case IRQ_PORTF_INTA:
                 case IRQ_PORTG_INTA:
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 35e7e1eb0188..1c143a4de5f5 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -45,9 +45,7 @@ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
 #endif
 
-void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
-        *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
-        *init_saved_dcplb_fault_addr_coreb;
+struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
 
 #define BFIN_IPI_RESCHEDULE   0
 #define BFIN_IPI_CALL_FUNC    1
@@ -369,13 +367,16 @@ void __cpuinit secondary_start_kernel(void)
         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
-                printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
-                        (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
-                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
-                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
+                printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
+                        initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
+                        initial_pda_coreb.retx_doublefault);
+                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
+                        initial_pda_coreb.dcplb_doublefault_addr);
+                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
+                        initial_pda_coreb.icplb_doublefault_addr);
 #endif
                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
-                        init_retx_coreb);
+                        initial_pda_coreb.retx);
         }
 
         /*
diff --git a/arch/h8300/Kconfig.cpu b/arch/h8300/Kconfig.cpu
index d236ab4232ca..15c22286ae79 100644
--- a/arch/h8300/Kconfig.cpu
+++ b/arch/h8300/Kconfig.cpu
@@ -162,9 +162,7 @@ config H8300_TPU_CH
         int "TPU channel"
         depends on H8300_TPU
 
-config PREEMPT
-        bool "Preemptible Kernel"
-        default n
+source "kernel/Kconfig.preempt"
 
 source "mm/Kconfig"
 
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 38280ef4a2af..137b277f7e56 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -101,6 +101,9 @@ config GENERIC_IOMAP
         bool
         default y
 
+config ARCH_CLOCKSOURCE_DATA
+        def_bool y
+
 config SCHED_OMIT_FRAME_POINTER
         bool
         default y
@@ -627,27 +630,6 @@ source "drivers/pci/hotplug/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
 
-config DMAR
-        bool "Support for DMA Remapping Devices (EXPERIMENTAL)"
-        depends on IA64_GENERIC && ACPI && EXPERIMENTAL
-        help
-          DMA remapping (DMAR) devices support enables independent address
-          translations for Direct Memory Access (DMA) from devices.
-          These DMA remapping devices are reported via ACPI tables
-          and include PCI device scope covered by these DMA
-          remapping devices.
-
-config DMAR_DEFAULT_ON
-        def_bool y
-        prompt "Enable DMA Remapping Devices by default"
-        depends on DMAR
-        help
-          Selecting this option will enable a DMAR device at boot time if
-          one is found. If this option is not selected, DMAR support can
-          be enabled by passing intel_iommu=on to the kernel. It is
-          recommended you say N here while the DMAR code remains
-          experimental.
-
 endmenu
 
 endif
@@ -681,6 +663,3 @@ source "lib/Kconfig"
 
 config IOMMU_HELPER
         def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB)
-
-config IOMMU_API
-        def_bool (DMAR)
diff --git a/arch/ia64/include/asm/clocksource.h b/arch/ia64/include/asm/clocksource.h
new file mode 100644
index 000000000000..5c8596e4cb02
--- /dev/null
+++ b/arch/ia64/include/asm/clocksource.h
@@ -0,0 +1,10 @@
+/* IA64-specific clocksource additions */
+
+#ifndef _ASM_IA64_CLOCKSOURCE_H
+#define _ASM_IA64_CLOCKSOURCE_H
+
+struct arch_clocksource_data {
+        void *fsys_mmio;        /* used by fsyscall asm code */
+};
+
+#endif /* _ASM_IA64_CLOCKSOURCE_H */
diff --git a/arch/ia64/kernel/cyclone.c b/arch/ia64/kernel/cyclone.c
index f64097b5118a..4826ff957a3d 100644
--- a/arch/ia64/kernel/cyclone.c
+++ b/arch/ia64/kernel/cyclone.c
@@ -115,7 +115,7 @@ int __init init_cyclone_clock(void)
         }
         /* initialize last tick */
         cyclone_mc = cyclone_timer;
-        clocksource_cyclone.fsys_mmio = cyclone_timer;
+        clocksource_cyclone.archdata.fsys_mmio = cyclone_timer;
         clocksource_register_hz(&clocksource_cyclone, CYCLONE_TIMER_FREQ);
 
         return 0;
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index 85118dfe9bb5..43920de425f1 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -468,7 +468,7 @@ void update_vsyscall(struct timespec *wall, struct timespec *wtm,
         fsyscall_gtod_data.clk_mask = c->mask;
         fsyscall_gtod_data.clk_mult = mult;
         fsyscall_gtod_data.clk_shift = c->shift;
-        fsyscall_gtod_data.clk_fsys_mmio = c->fsys_mmio;
+        fsyscall_gtod_data.clk_fsys_mmio = c->archdata.fsys_mmio;
         fsyscall_gtod_data.clk_cycle_last = c->cycle_last;
 
         /* copy kernel time structures */
diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig
index fa4d1e59deb0..9806e55f91be 100644
--- a/arch/ia64/kvm/Kconfig
+++ b/arch/ia64/kvm/Kconfig
@@ -49,6 +49,5 @@ config KVM_INTEL
           extensions.
 
 source drivers/vhost/Kconfig
-source drivers/virtio/Kconfig
 
 endif # VIRTUALIZATION
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index 81a1f4e6bcd8..485c42d97e83 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -112,8 +112,6 @@ static void sn_ack_irq(struct irq_data *data)
         irq_move_irq(data);
 }
 
-static void sn_irq_info_free(struct rcu_head *head);
-
 struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
                                        nasid_t nasid, int slice)
 {
@@ -177,7 +175,7 @@ struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
         spin_lock(&sn_irq_info_lock);
         list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
         spin_unlock(&sn_irq_info_lock);
-        call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
+        kfree_rcu(sn_irq_info, rcu);
 
 
 finish_up:
@@ -338,14 +336,6 @@ static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
         rcu_read_unlock();
 }
 
-static void sn_irq_info_free(struct rcu_head *head)
-{
-        struct sn_irq_info *sn_irq_info;
-
-        sn_irq_info = container_of(head, struct sn_irq_info, rcu);
-        kfree(sn_irq_info);
-}
-
 void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
 {
         nasid_t nasid = sn_irq_info->irq_nasid;
@@ -399,7 +389,7 @@ void sn_irq_unfixup(struct pci_dev *pci_dev)
         spin_unlock(&sn_irq_info_lock);
         if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
                 free_irq_vector(sn_irq_info->irq_irq);
-        call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
+        kfree_rcu(sn_irq_info, rcu);
         pci_dev_put(pci_dev);
 
 }
diff --git a/arch/ia64/sn/kernel/sn2/timer.c b/arch/ia64/sn/kernel/sn2/timer.c
index c34efda122e1..0f8844e49363 100644
--- a/arch/ia64/sn/kernel/sn2/timer.c
+++ b/arch/ia64/sn/kernel/sn2/timer.c
@@ -54,7 +54,7 @@ ia64_sn_udelay (unsigned long usecs)
 
 void __init sn_timer_init(void)
 {
-        clocksource_sn2.fsys_mmio = RTC_COUNTER_ADDR;
+        clocksource_sn2.archdata.fsys_mmio = RTC_COUNTER_ADDR;
         clocksource_register_hz(&clocksource_sn2, sn_rtc_cycles_per_second);
 
         ia64_udelay = &ia64_sn_udelay;
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 85b44e858225..b92b9445255d 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -268,17 +268,7 @@ config SCHED_OMIT_FRAME_POINTER
         bool
         default y
 
-config PREEMPT
-        bool "Preemptible Kernel"
-        help
-          This option reduces the latency of the kernel when reacting to
-          real-time or interactive events by allowing a low priority process to
-          be preempted even if it is in kernel mode executing a system call.
-          This allows applications to run more reliably even when the system is
-          under load.
-
-          Say Y here if you are building a kernel for a desktop, embedded
-          or real-time system.  Say N if you are unsure.
+source "kernel/Kconfig.preempt"
 
 config SMP
         bool "Symmetric multi-processing support"
diff --git a/arch/m68k/emu/nfeth.c b/arch/m68k/emu/nfeth.c
index 8b6e201b2c20..c5748bb4ea71 100644
--- a/arch/m68k/emu/nfeth.c
+++ b/arch/m68k/emu/nfeth.c
@@ -16,6 +16,7 @@
 
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
+#include <linux/interrupt.h>
 #include <linux/module.h>
 #include <asm/natfeat.h>
 #include <asm/virtconvert.h>
@@ -204,7 +205,6 @@ static struct net_device * __init nfeth_probe(int unit)
         dev->irq = nfEtherIRQ;
         dev->netdev_ops = &nfeth_netdev_ops;
 
-        dev->flags |= NETIF_F_NO_CSUM;
         memcpy(dev->dev_addr, mac, ETH_ALEN);
 
         priv = netdev_priv(dev);
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index 746df91e5796..242be57a319c 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -19,9 +19,6 @@ enum {
          */
         PCI_REASSIGN_ALL_RSRC   = 0x00000001,
 
-        /* Re-assign all bus numbers */
-        PCI_REASSIGN_ALL_BUS    = 0x00000002,
-
         /* Do not try to assign, just use existing setup */
         PCI_PROBE_ONLY          = 0x00000004,
 
@@ -110,16 +107,6 @@ static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
         return bus->sysdata;
 }
 
-static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
-{
-        struct pci_controller *host;
-
-        if (bus->self)
-                return pci_device_to_OF_node(bus->self);
-        host = pci_bus_to_host(bus);
-        return host ? host->dn : NULL;
-}
-
 static inline int isa_vaddr_is_ioport(void __iomem *address)
 {
         /* No specific ISA handling on ppc32 at this stage, it
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index ba65cf472544..1dd9d6b1e275 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -40,8 +40,7 @@ struct pci_dev;
  * Set this to 1 if you want the kernel to re-assign all PCI
  * bus numbers (don't do that on ppc64 yet !)
  */
-#define pcibios_assign_all_busses() \
-        (pci_has_flag(PCI_REASSIGN_ALL_BUS))
+#define pcibios_assign_all_busses()     0
 
 static inline void pcibios_set_master(struct pci_dev *dev)
 {
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h
index d0890d36ef61..9bd01ecb00d6 100644
--- a/arch/microblaze/include/asm/prom.h
+++ b/arch/microblaze/include/asm/prom.h
@@ -29,21 +29,6 @@
 extern int early_uartlite_console(void);
 extern int early_uart16550_console(void);
 
-#ifdef CONFIG_PCI
-/*
- * PCI <-> OF matching functions
- * (XXX should these be here?)
- */
-struct pci_bus;
-struct pci_dev;
-extern int pci_device_from_OF_node(struct device_node *node,
-                                        u8 *bus, u8 *devfn);
-extern struct device_node *pci_busdev_to_OF_node(struct pci_bus *bus,
-                                                        int devfn);
-extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
-extern void pci_create_OF_bus_map(void);
-#endif
-
 /*
  * OF address retreival & translation
  */
diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile
index 9889cc2e1294..d1114fbd4780 100644
--- a/arch/microblaze/pci/Makefile
+++ b/arch/microblaze/pci/Makefile
@@ -2,5 +2,5 @@
 # Makefile
 #
 
-obj-$(CONFIG_PCI)               += pci_32.o pci-common.o indirect_pci.o iomap.o
+obj-$(CONFIG_PCI)               += pci-common.o indirect_pci.o iomap.o
 obj-$(CONFIG_PCI_XILINX)        += xilinx_pci.o
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 53599067d2f9..041b1d86d75b 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -50,6 +50,11 @@ unsigned int pci_flags;
 
 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 
+unsigned long isa_io_base;
+unsigned long pci_dram_offset;
+static int pci_bus_count;
+
+
 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
 {
         pci_dma_ops = dma_ops;
@@ -1558,6 +1563,112 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
                  (unsigned long)hose->io_base_virt - _IO_BASE);
 }
 
+struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
+{
+        struct pci_controller *hose = bus->sysdata;
+
+        return of_node_get(hose->dn);
+}
+
+static void __devinit pcibios_scan_phb(struct pci_controller *hose)
+{
+        struct pci_bus *bus;
+        struct device_node *node = hose->dn;
+        unsigned long io_offset;
+        struct resource *res = &hose->io_resource;
+
+        pr_debug("PCI: Scanning PHB %s\n",
+                 node ? node->full_name : "<NO NAME>");
+
+        /* Create an empty bus for the toplevel */
+        bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
+        if (bus == NULL) {
+                printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
+                       hose->global_number);
+                return;
+        }
+        bus->secondary = hose->first_busno;
+        hose->bus = bus;
+
+        /* Fixup IO space offset */
+        io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
+        res->start = (res->start + io_offset) & 0xffffffffu;
+        res->end = (res->end + io_offset) & 0xffffffffu;
+
+        /* Wire up PHB bus resources */
+        pcibios_setup_phb_resources(hose);
+
+        /* Scan children */
+        hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
+}
+
+static int __init pcibios_init(void)
+{
+        struct pci_controller *hose, *tmp;
+        int next_busno = 0;
+
+        printk(KERN_INFO "PCI: Probing PCI hardware\n");
+
+        /* Scan all of the recorded PCI controllers.  */
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+                hose->last_busno = 0xff;
+                pcibios_scan_phb(hose);
+                printk(KERN_INFO "calling pci_bus_add_devices()\n");
+                pci_bus_add_devices(hose->bus);
+                if (next_busno <= hose->last_busno)
+                        next_busno = hose->last_busno + 1;
+        }
+        pci_bus_count = next_busno;
+
+        /* Call common code to handle resource allocation */
+        pcibios_resource_survey();
+
+        return 0;
+}
+
+subsys_initcall(pcibios_init);
+
+static struct pci_controller *pci_bus_to_hose(int bus)
+{
+        struct pci_controller *hose, *tmp;
+
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
+                if (bus >= hose->first_busno && bus <= hose->last_busno)
+                        return hose;
+        return NULL;
+}
+
+/* Provide information on locations of various I/O regions in physical
+ * memory.  Do this on a per-card basis so that we choose the right
+ * root bridge.
+ * Note that the returned IO or memory base is a physical address
+ */
+
+long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
+{
+        struct pci_controller *hose;
+        long result = -EOPNOTSUPP;
+
+        hose = pci_bus_to_hose(bus);
+        if (!hose)
+                return -ENODEV;
+
+        switch (which) {
+        case IOBASE_BRIDGE_NUMBER:
+                return (long)hose->first_busno;
+        case IOBASE_MEMORY:
+                return (long)hose->pci_mem_offset;
+        case IOBASE_IO:
+                return (long)hose->io_base_phys;
+        case IOBASE_ISA_IO:
+                return (long)isa_io_base;
+        case IOBASE_ISA_MEM:
+                return (long)isa_mem_base;
+        }
+
+        return result;
+}
+
 /*
  * Null PCI config access functions, for the case when we can't
  * find a hose.
@@ -1626,3 +1737,4 @@ int early_find_capability(struct pci_controller *hose, int bus, int devfn,
 {
         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
 }
+
diff --git a/arch/microblaze/pci/pci_32.c b/arch/microblaze/pci/pci_32.c
deleted file mode 100644
index 92728a6cfd80..000000000000
--- a/arch/microblaze/pci/pci_32.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * Common pmac/prep/chrp pci routines. -- Cort
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/init.h>
-#include <linux/capability.h>
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/bootmem.h>
-#include <linux/irq.h>
-#include <linux/list.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/sections.h>
-#include <asm/pci-bridge.h>
-#include <asm/byteorder.h>
-#include <asm/uaccess.h>
-
-#undef DEBUG
-
-unsigned long isa_io_base;
-unsigned long pci_dram_offset;
-int pcibios_assign_bus_offset = 1;
-
-static u8 *pci_to_OF_bus_map;
-
-/* By default, we don't re-assign bus numbers. We do this only on
- * some pmacs
- */
-static int pci_assign_all_buses;
-
-static int pci_bus_count;
-
-/*
- * Functions below are used on OpenFirmware machines.
- */
-static void
-make_one_node_map(struct device_node *node, u8 pci_bus)
-{
-        const int *bus_range;
-        int len;
-
-        if (pci_bus >= pci_bus_count)
-                return;
-        bus_range = of_get_property(node, "bus-range", &len);
-        if (bus_range == NULL || len < 2 * sizeof(int)) {
-                printk(KERN_WARNING "Can't get bus-range for %s, "
-                       "assuming it starts at 0\n", node->full_name);
-                pci_to_OF_bus_map[pci_bus] = 0;
-        } else
-                pci_to_OF_bus_map[pci_bus] = bus_range[0];
-
-        for_each_child_of_node(node, node) {
-                struct pci_dev *dev;
-                const unsigned int *class_code, *reg;
-
-                class_code = of_get_property(node, "class-code", NULL);
-                if (!class_code ||
-                        ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
-                        (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
-                        continue;
-                reg = of_get_property(node, "reg", NULL);
-                if (!reg)
-                        continue;
-                dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
-                if (!dev || !dev->subordinate) {
-                        pci_dev_put(dev);
-                        continue;
-                }
-                make_one_node_map(node, dev->subordinate->number);
-                pci_dev_put(dev);
-        }
-}
-
-void
-pcibios_make_OF_bus_map(void)
-{
-        int i;
-        struct pci_controller *hose, *tmp;
-        struct property *map_prop;
-        struct device_node *dn;
-
-        pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
-        if (!pci_to_OF_bus_map) {
-                printk(KERN_ERR "Can't allocate OF bus map !\n");
-                return;
-        }
-
-        /* We fill the bus map with invalid values, that helps
-         * debugging.
-         */
-        for (i = 0; i < pci_bus_count; i++)
-                pci_to_OF_bus_map[i] = 0xff;
-
-        /* For each hose, we begin searching bridges */
-        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
-                struct device_node *node = hose->dn;
-
-                if (!node)
-                        continue;
-                make_one_node_map(node, hose->first_busno);
-        }
-        dn = of_find_node_by_path("/");
-        map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
-        if (map_prop) {
-                BUG_ON(pci_bus_count > map_prop->length);
-                memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
-        }
-        of_node_put(dn);
-#ifdef DEBUG
-        printk(KERN_INFO "PCI->OF bus map:\n");
-        for (i = 0; i < pci_bus_count; i++) {
-                if (pci_to_OF_bus_map[i] == 0xff)
-                        continue;
-                printk(KERN_INFO "%d -> %d\n", i, pci_to_OF_bus_map[i]);
-        }
-#endif
-}
-
-typedef int (*pci_OF_scan_iterator)(struct device_node *node, void *data);
-
-static struct device_node *scan_OF_pci_childs(struct device_node *parent,
-                                        pci_OF_scan_iterator filter, void *data)
-{
-        struct device_node *node;
-        struct device_node *sub_node;
-
-        for_each_child_of_node(parent, node) {
-                const unsigned int *class_code;
-
-                if (filter(node, data)) {
-                        of_node_put(node);
-                        return node;
-                }
-
-                /* For PCI<->PCI bridges or CardBus bridges, we go down
-                 * Note: some OFs create a parent node "multifunc-device" as
-                 * a fake root for all functions of a multi-function device,
-                 * we go down them as well.
-                 */
-                class_code = of_get_property(node, "class-code", NULL);
-                if ((!class_code ||
-                        ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
-                        (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
-                        strcmp(node->name, "multifunc-device"))
-                        continue;
-                sub_node = scan_OF_pci_childs(node, filter, data);
-                if (sub_node) {
-                        of_node_put(node);
-                        return sub_node;
-                }
-        }
-        return NULL;
-}
-
-static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
-                                               unsigned int devfn)
-{
-        struct device_node *np, *cnp;
-        const u32 *reg;
-        unsigned int psize;
-
-        for_each_child_of_node(parent, np) {
-                reg = of_get_property(np, "reg", &psize);
-                if (reg && psize >= 4 && ((reg[0] >> 8) & 0xff) == devfn)
-                        return np;
-
-                /* Note: some OFs create a parent node "multifunc-device" as
-                 * a fake root for all functions of a multi-function device,
-                 * we go down them as well. */
-                if (!strcmp(np->name, "multifunc-device")) {
-                        cnp = scan_OF_for_pci_dev(np, devfn);
-                        if (cnp)
-                                return cnp;
-                }
-        }
-        return NULL;
-}
-
-
-static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
-{
-        struct device_node *parent, *np;
-
-        /* Are we a root bus ? */
-        if (bus->self == NULL || bus->parent == NULL) {
-                struct pci_controller *hose = pci_bus_to_host(bus);
-                if (hose == NULL)
-                        return NULL;
-                return of_node_get(hose->dn);
-        }
-
-        /* not a root bus, we need to get our parent */
-        parent = scan_OF_for_pci_bus(bus->parent);
-        if (parent == NULL)
-                return NULL;
-
-        /* now iterate for children for a match */
-        np = scan_OF_for_pci_dev(parent, bus->self->devfn);
-        of_node_put(parent);
-
-        return np;
-}
-
-/*
- * Scans the OF tree for a device node matching a PCI device
- */
-struct device_node *
-pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
-{
-        struct device_node *parent, *np;
-
-        pr_debug("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
-        parent = scan_OF_for_pci_bus(bus);
-        if (parent == NULL)
-                return NULL;
-        pr_debug(" parent is %s\n", parent ? parent->full_name : "<NULL>");
-        np = scan_OF_for_pci_dev(parent, devfn);
-        of_node_put(parent);
-        pr_debug(" result is %s\n", np ? np->full_name : "<NULL>");
-
-        /* XXX most callers don't release the returned node
-         * mostly because ppc64 doesn't increase the refcount,
-         * we need to fix that.
-         */
-        return np;
-}
-EXPORT_SYMBOL(pci_busdev_to_OF_node);
-
-struct device_node*
-pci_device_to_OF_node(struct pci_dev *dev)
-{
-        return pci_busdev_to_OF_node(dev->bus, dev->devfn);
-}
-EXPORT_SYMBOL(pci_device_to_OF_node);
-
-static int
-find_OF_pci_device_filter(struct device_node *node, void *data)
-{
-        return ((void *)node == data);
-}
-
-/*
- * Returns the PCI device matching a given OF node
- */
-int
-pci_device_from_OF_node(struct device_node *node, u8 *bus, u8 *devfn)
-{
-        const unsigned int *reg;
-        struct pci_controller *hose;
-        struct pci_dev *dev = NULL;
-
-        /* Make sure it's really a PCI device */
-        hose = pci_find_hose_for_OF_device(node);
-        if (!hose || !hose->dn)
-                return -ENODEV;
-        if (!scan_OF_pci_childs(hose->dn,
-                        find_OF_pci_device_filter, (void *)node))
-                return -ENODEV;
-        reg = of_get_property(node, "reg", NULL);
-        if (!reg)
-                return -ENODEV;
-        *bus = (reg[0] >> 16) & 0xff;
-        *devfn = ((reg[0] >> 8) & 0xff);
-
-        /* Ok, here we need some tweak. If we have already renumbered
-         * all busses, we can't rely on the OF bus number any more.
-         * the pci_to_OF_bus_map is not enough as several PCI busses
-         * may match the same OF bus number.
-         */
-        if (!pci_to_OF_bus_map)
-                return 0;
-
-        for_each_pci_dev(dev)
-                if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
-                                dev->devfn == *devfn) {
-                        *bus = dev->bus->number;
-                        pci_dev_put(dev);
-                        return 0;
-                }
-
-        return -ENODEV;
-}
-EXPORT_SYMBOL(pci_device_from_OF_node);
-
-/* We create the "pci-OF-bus-map" property now so it appears in the
- * /proc device tree
- */
-void __init
-pci_create_OF_bus_map(void)
-{
-        struct property *of_prop;
-        struct device_node *dn;
-
-        of_prop = (struct property *) alloc_bootmem(sizeof(struct property) + \
-                                                                         256);
-        if (!of_prop)
-                return;
-        dn = of_find_node_by_path("/");
-        if (dn) {
-                memset(of_prop, -1, sizeof(struct property) + 256);
-                of_prop->name = "pci-OF-bus-map";
-                of_prop->length = 256;
-                of_prop->value = &of_prop[1];
-                prom_add_property(dn, of_prop);
-                of_node_put(dn);
-        }
-}
-
-static void __devinit pcibios_scan_phb(struct pci_controller *hose)
-{
-        struct pci_bus *bus;
-        struct device_node *node = hose->dn;
-        unsigned long io_offset;
-        struct resource *res = &hose->io_resource;
-
-        pr_debug("PCI: Scanning PHB %s\n",
-                 node ? node->full_name : "<NO NAME>");
-
-        /* Create an empty bus for the toplevel */
-        bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
-        if (bus == NULL) {
-                printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
-                       hose->global_number);
-                return;
-        }
-        bus.dev->of_node = of_node_get(node);
-        bus->secondary = hose->first_busno;
-        hose->bus = bus;
-
-        /* Fixup IO space offset */
-        io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
-        res->start = (res->start + io_offset) & 0xffffffffu;
-        res->end = (res->end + io_offset) & 0xffffffffu;
-
-        /* Wire up PHB bus resources */
-        pcibios_setup_phb_resources(hose);
-
-        /* Scan children */
-        hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
-}
-
-static int __init pcibios_init(void)
-{
-        struct pci_controller *hose, *tmp;
-        int next_busno = 0;
-
-        printk(KERN_INFO "PCI: Probing PCI hardware\n");
-
-        if (pci_flags & PCI_REASSIGN_ALL_BUS) {
-                printk(KERN_INFO "setting pci_asign_all_busses\n");
-                pci_assign_all_buses = 1;
-        }
-
-        /* Scan all of the recorded PCI controllers.  */
-        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
-                if (pci_assign_all_buses)
-                        hose->first_busno = next_busno;
-                hose->last_busno = 0xff;
-                pcibios_scan_phb(hose);
-                printk(KERN_INFO "calling pci_bus_add_devices()\n");
-                pci_bus_add_devices(hose->bus);
-                if (pci_assign_all_buses || next_busno <= hose->last_busno)
-                        next_busno = hose->last_busno + \
-                                        pcibios_assign_bus_offset;
-        }
-        pci_bus_count = next_busno;
-
-        /* OpenFirmware based machines need a map of OF bus
-         * numbers vs. kernel bus numbers since we may have to
-         * remap them.
-         */
-        if (pci_assign_all_buses)
-                pcibios_make_OF_bus_map();
-
-        /* Call common code to handle resource allocation */
-        pcibios_resource_survey();
-
-        return 0;
-}
-
-subsys_initcall(pcibios_init);
-
-static struct pci_controller*
-pci_bus_to_hose(int bus)
-{
-        struct pci_controller *hose, *tmp;
-
-        list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
-                if (bus >= hose->first_busno && bus <= hose->last_busno)
-                        return hose;
-        return NULL;
-}
-
-/* Provide information on locations of various I/O regions in physical
- * memory.  Do this on a per-card basis so that we choose the right
- * root bridge.
- * Note that the returned IO or memory base is a physical address
- */
-
-long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
-{
-        struct pci_controller *hose;
-        long result = -EOPNOTSUPP;
-
-        hose = pci_bus_to_hose(bus);
-        if (!hose)
-                return -ENODEV;
-
-        switch (which) {
-        case IOBASE_BRIDGE_NUMBER:
-                return (long)hose->first_busno;
-        case IOBASE_MEMORY:
-                return (long)hose->pci_mem_offset;
-        case IOBASE_IO:
-                return (long)hose->io_base_phys;
-        case IOBASE_ISA_IO:
-                return (long)isa_io_base;
-        case IOBASE_ISA_MEM:
-                return (long)isa_mem_base;
-        }
-
-        return result;
-}
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 653da62d0682..177cdaf83564 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -185,6 +185,7 @@ config MACH_JAZZ
         select CSRC_R4K
         select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
         select GENERIC_ISA_DMA
+        select HAVE_PCSPKR_PLATFORM
         select IRQ_CPU
         select I8253
         select I8259
@@ -266,6 +267,7 @@ config MIPS_MALTA
         select CSRC_R4K
         select DMA_NONCOHERENT
         select GENERIC_ISA_DMA
+        select HAVE_PCSPKR_PLATFORM
         select IRQ_CPU
         select IRQ_GIC
         select HW_HAS_PCI
@@ -640,6 +642,7 @@ config SNI_RM
         select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
         select DMA_NONCOHERENT
         select GENERIC_ISA_DMA
+        select HAVE_PCSPKR_PLATFORM
         select HW_HAS_EISA
         select HW_HAS_PCI
         select IRQ_CPU
@@ -2388,6 +2391,7 @@ config MMU
 config I8253
         bool
         select CLKSRC_I8253
+        select CLKEVT_I8253
         select MIPS_EXTERNAL_TIMER
 
 config ZONE_DMA32
@@ -2489,20 +2493,4 @@ source "security/Kconfig"
 
 source "crypto/Kconfig"
 
-menuconfig VIRTUALIZATION
-        bool "Virtualization"
-        default n
-        ---help---
-          Say Y here to get to see options for using your Linux host to run other
-          operating systems inside virtual machines (guests).
-          This option alone does not add any kernel code.
-
-          If you say N, all options in this submenu will be skipped and disabled.
-
-if VIRTUALIZATION
-
-source drivers/virtio/Kconfig
-
-endif # VIRTUALIZATION
-
 source "lib/Kconfig"
diff --git a/arch/mips/cobalt/time.c b/arch/mips/cobalt/time.c
index 0162f9edc693..3bff3b820baf 100644
--- a/arch/mips/cobalt/time.c
+++ b/arch/mips/cobalt/time.c
@@ -17,10 +17,10 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  */
+#include <linux/i8253.h>
 #include <linux/init.h>
 
 #include <asm/gt64120.h>
-#include <asm/i8253.h>
 #include <asm/time.h>
 
 #define GT641XX_BASE_CLOCK      50000000        /* 50MHz */
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
deleted file mode 100644
index 9ad011366f73..000000000000
--- a/arch/mips/include/asm/i8253.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- *  Machine specific IO port address definition for generic.
- *  Written by Osamu Tomita <tomita@cinet.co.jp>
- */
-#ifndef __ASM_I8253_H
-#define __ASM_I8253_H
-
-#include <linux/spinlock.h>
-
-/* i8253A PIT registers */
-#define PIT_MODE                0x43
-#define PIT_CH0                 0x40
-#define PIT_CH2                 0x42
-
-#define PIT_LATCH               LATCH
-
-extern raw_spinlock_t i8253_lock;
-
-extern void setup_pit_timer(void);
-
-#define inb_pit inb_p
-#define outb_pit outb_p
-
-#endif /* __ASM_I8253_H */
diff --git a/arch/mips/include/asm/stacktrace.h b/arch/mips/include/asm/stacktrace.h
index 0bf82818aa53..780ee2c2a2ac 100644
--- a/arch/mips/include/asm/stacktrace.h
+++ b/arch/mips/include/asm/stacktrace.h
@@ -7,6 +7,10 @@
 extern int raw_show_trace;
 extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
                                   unsigned long pc, unsigned long *ra);
+extern unsigned long unwind_stack_by_address(unsigned long stack_page,
+                                             unsigned long *sp,
+                                             unsigned long pc,
+                                             unsigned long *ra);
 #else
 #define raw_show_trace 1
 static inline unsigned long unwind_stack(struct task_struct *task,
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 260df4750949..ca9bd2069142 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -7,6 +7,7 @@
  * Copyright (C) 1994 - 2001, 2003, 07 Ralf Baechle
  */
 #include <linux/clockchips.h>
+#include <linux/i8253.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
@@ -15,7 +16,6 @@
 #include <linux/irq.h>
 
 #include <asm/irq_cpu.h>
-#include <asm/i8253.h>
 #include <asm/i8259.h>
 #include <asm/io.h>
 #include <asm/jazz.h>
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index 391221b6a6aa..be4ee7d63e04 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -3,96 +3,16 @@
  *
  */
 #include <linux/clockchips.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/jiffies.h>
+#include <linux/i8253.h>
 #include <linux/module.h>
 #include <linux/smp.h>
-#include <linux/spinlock.h>
 #include <linux/irq.h>
 
-#include <asm/delay.h>
-#include <asm/i8253.h>
-#include <asm/io.h>
 #include <asm/time.h>
 
-DEFINE_RAW_SPINLOCK(i8253_lock);
-EXPORT_SYMBOL(i8253_lock);
-
-/*
- * Initialize the PIT timer.
- *
- * This is also called after resume to bring the PIT into operation again.
- */
-static void init_pit_timer(enum clock_event_mode mode,
-                           struct clock_event_device *evt)
-{
-        raw_spin_lock(&i8253_lock);
-
-        switch(mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                /* binary, mode 2, LSB/MSB, ch 0 */
-                outb_p(0x34, PIT_MODE);
-                outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
-                outb(LATCH >> 8 , PIT_CH0);     /* MSB */
-                break;
-
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-                if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
-                    evt->mode == CLOCK_EVT_MODE_ONESHOT) {
-                        outb_p(0x30, PIT_MODE);
-                        outb_p(0, PIT_CH0);
-                        outb_p(0, PIT_CH0);
-                }
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* One shot setup */
-                outb_p(0x38, PIT_MODE);
-                break;
-
-        case CLOCK_EVT_MODE_RESUME:
-                /* Nothing to do here */
-                break;
-        }
-        raw_spin_unlock(&i8253_lock);
-}
-
-/*
- * Program the next event in oneshot mode
- *
- * Delta is given in PIT ticks
- */
-static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
-{
-        raw_spin_lock(&i8253_lock);
-        outb_p(delta & 0xff , PIT_CH0); /* LSB */
-        outb(delta >> 8 , PIT_CH0);     /* MSB */
-        raw_spin_unlock(&i8253_lock);
-
-        return 0;
-}
-
-/*
- * On UP the PIT can serve all of the possible timer functions. On SMP systems
- * it can be solely used for the global tick.
- *
- * The profiling and update capabilites are switched off once the local apic is
- * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
- * !using_apic_timer decisions in do_timer_interrupt_hook()
- */
-static struct clock_event_device pit_clockevent = {
-        .name           = "pit",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = init_pit_timer,
-        .set_next_event = pit_next_event,
-        .irq            = 0,
-};
-
 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 {
-        pit_clockevent.event_handler(&pit_clockevent);
+        i8253_clockevent.event_handler(&i8253_clockevent);
 
         return IRQ_HANDLED;
 }
@@ -103,25 +23,9 @@ static struct irqaction irq0  = {
         .name = "timer"
 };
 
-/*
- * Initialize the conversion factor and the min/max deltas of the clock event
- * structure and register the clock event source with the framework.
- */
 void __init setup_pit_timer(void)
 {
-        struct clock_event_device *cd = &pit_clockevent;
-        unsigned int cpu = smp_processor_id();
-
-        /*
-         * Start pit with the boot cpu mask and make it global after the
-         * IO_APIC has been initialized.
-         */
-        cd->cpumask = cpumask_of(cpu);
-        clockevent_set_clock(cd, CLOCK_TICK_RATE);
-        cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
-        cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
-        clockevents_register_device(cd);
-
+        clockevent_i8253_init(true);
         setup_irq(0, &irq0);
 }
 
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index c018696765d4..5c74eb797f08 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -14,7 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
-#include <linux/sysdev.h>
+#include <linux/syscore_ops.h>
 #include <linux/irq.h>
 
 #include <asm/i8259.h>
@@ -215,14 +215,13 @@ spurious_8259A_irq:
         }
 }
 
-static int i8259A_resume(struct sys_device *dev)
+static void i8259A_resume(void)
 {
         if (i8259A_auto_eoi >= 0)
                 init_8259A(i8259A_auto_eoi);
-        return 0;
 }
 
-static int i8259A_shutdown(struct sys_device *dev)
+static void i8259A_shutdown(void)
 {
         /* Put the i8259A into a quiescent state that
          * the kernel initialization code can get it
@@ -232,26 +231,17 @@ static int i8259A_shutdown(struct sys_device *dev)
                 outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
                 outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
         }
-        return 0;
 }
 
-static struct sysdev_class i8259_sysdev_class = {
-        .name = "i8259",
+static struct syscore_ops i8259_syscore_ops = {
         .resume = i8259A_resume,
         .shutdown = i8259A_shutdown,
 };
 
-static struct sys_device device_i8259A = {
-        .id     = 0,
-        .cls    = &i8259_sysdev_class,
-};
-
 static int __init i8259A_init_sysfs(void)
 {
-        int error = sysdev_class_register(&i8259_sysdev_class);
-        if (!error)
-                error = sysdev_register(&device_i8259A);
-        return error;
+        register_syscore_ops(&i8259_syscore_ops);
+        return 0;
 }
 
 device_initcall(i8259A_init_sysfs);
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index a8244854d3dc..d0deaab9ace2 100644
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -527,7 +527,7 @@ handle_associated_event(struct cpu_hw_events *cpuc,
         if (!mipspmu_event_set_period(event, hwc, idx))
                 return;
 
-        if (perf_event_overflow(event, 0, data, regs))
+        if (perf_event_overflow(event, data, regs))
                 mipspmu->disable_event(idx);
 }
 
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 75266ff4cc33..e5ad09a9baf7 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -377,6 +377,20 @@ static const struct mips_perf_event mipsxxcore_cache_map
                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
         },
 },
+[C(NODE)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
 };
 
 /* 74K core has completely different cache event map. */
@@ -480,6 +494,20 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
         },
 },
+[C(NODE)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
 };
 
 #ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index d2112d3cf115..c28fbe6107bc 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -373,18 +373,18 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
 
 
 #ifdef CONFIG_KALLSYMS
-/* used by show_backtrace() */
-unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
-                           unsigned long pc, unsigned long *ra)
+/* generic stack unwinding function */
+unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
+                                              unsigned long *sp,
+                                              unsigned long pc,
+                                              unsigned long *ra)
 {
-        unsigned long stack_page;
         struct mips_frame_info info;
         unsigned long size, ofs;
         int leaf;
         extern void ret_from_irq(void);
         extern void ret_from_exception(void);
 
-        stack_page = (unsigned long)task_stack_page(task);
         if (!stack_page)
                 return 0;
 
@@ -443,6 +443,15 @@ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
         *ra = 0;
         return __kernel_text_address(pc) ? pc : 0;
 }
+EXPORT_SYMBOL(unwind_stack_by_address);
+
+/* used by show_backtrace() */
+unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
+                           unsigned long pc, unsigned long *ra)
+{
+        unsigned long stack_page = (unsigned long)task_stack_page(task);
+        return unwind_stack_by_address(stack_page, sp, pc, ra);
+}
 #endif
 
 /*
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e9b3af27d844..b7517e3abc85 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -578,12 +578,12 @@ static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 {
         if ((opcode & OPCODE) == LL) {
                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
-                                1, 0, regs, 0);
+                                1, regs, 0);
                 return simulate_ll(regs, opcode);
         }
         if ((opcode & OPCODE) == SC) {
                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
-                                1, 0, regs, 0);
+                                1, regs, 0);
                 return simulate_sc(regs, opcode);
         }
 
@@ -602,7 +602,7 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
                 int rd = (opcode & RD) >> 11;
                 int rt = (opcode & RT) >> 16;
                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
-                                1, 0, regs, 0);
+                                1, regs, 0);
                 switch (rd) {
                 case 0:         /* CPU number */
                         regs->regs[rt] = smp_processor_id();
@@ -640,7 +640,7 @@ static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 {
         if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
-                                1, 0, regs, 0);
+                                1, regs, 0);
                 return 0;
         }
 
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index cfea1adfa153..eb319b580353 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -111,8 +111,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
         unsigned long value;
         unsigned int res;
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
-                      1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 
         /*
          * This load never faults.
@@ -517,7 +516,7 @@ asmlinkage void do_ade(struct pt_regs *regs)
         mm_segment_t seg;
 
         perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
-                        1, 0, regs, regs->cp0_badvaddr);
+                        1, regs, regs->cp0_badvaddr);
         /*
          * Did we catch a fault trying to load an instruction?
          * Or are we running in MIPS16 mode?
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index d32cb0503110..dbf2f93a5091 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -272,8 +272,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
         }
 
       emul:
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
-                        1, 0, xcp, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
         MIPS_FPU_EMU_INC_STATS(emulated);
         switch (MIPSInst_OPCODE(ir)) {
         case ldc1_op:{
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 137ee76a0045..937cf3368164 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -145,7 +145,7 @@ good_area:
          * the fault.
          */
         fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
                         goto out_of_memory;
@@ -154,12 +154,10 @@ good_area:
                 BUG();
         }
         if (fault & VM_FAULT_MAJOR) {
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
-                                1, 0, regs, address);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address);
                 tsk->maj_flt++;
         } else {
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
-                                1, 0, regs, address);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address);
                 tsk->min_flt++;
         }
 
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 1620b83cd13e..f8ee945ee411 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -19,6 +19,7 @@
  */
 
 #include <linux/types.h>
+#include <linux/i8253.h>
 #include <linux/init.h>
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
@@ -31,7 +32,6 @@
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/hardirq.h>
-#include <asm/i8253.h>
 #include <asm/irq.h>
 #include <asm/div64.h>
 #include <asm/cpu.h>
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 4b9d7044e26c..29f2f13eb31c 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -8,7 +8,7 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
                 oprofilefs.o oprofile_stats.o \
                 timer_int.o )
 
-oprofile-y                              := $(DRIVER_OBJS) common.o
+oprofile-y                              := $(DRIVER_OBJS) common.o backtrace.o
 
 oprofile-$(CONFIG_CPU_MIPS32)           += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_MIPS64)           += op_model_mipsxx.o
diff --git a/arch/mips/oprofile/backtrace.c b/arch/mips/oprofile/backtrace.c
new file mode 100644
index 000000000000..6854ed5097d2
--- /dev/null
+++ b/arch/mips/oprofile/backtrace.c
@@ -0,0 +1,175 @@
+#include <linux/oprofile.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include <asm/ptrace.h>
+#include <asm/stacktrace.h>
+#include <linux/stacktrace.h>
+#include <linux/kernel.h>
+#include <asm/sections.h>
+#include <asm/inst.h>
+
+struct stackframe {
+        unsigned long sp;
+        unsigned long pc;
+        unsigned long ra;
+};
+
+static inline int get_mem(unsigned long addr, unsigned long *result)
+{
+        unsigned long *address = (unsigned long *) addr;
+        if (!access_ok(VERIFY_READ, addr, sizeof(unsigned long)))
+                return -1;
+        if (__copy_from_user_inatomic(result, address, sizeof(unsigned long)))
+                return -3;
+        return 0;
+}
+
+/*
+ * These two instruction helpers were taken from process.c
+ */
+static inline int is_ra_save_ins(union mips_instruction *ip)
+{
+        /* sw / sd $ra, offset($sp) */
+        return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op)
+                && ip->i_format.rs == 29 && ip->i_format.rt == 31;
+}
+
+static inline int is_sp_move_ins(union mips_instruction *ip)
+{
+        /* addiu/daddiu sp,sp,-imm */
+        if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
+                return 0;
+        if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op)
+                return 1;
+        return 0;
+}
+
+/*
+ * Looks for specific instructions that mark the end of a function.
+ * This usually means we ran into the code area of the previous function.
+ */
+static inline int is_end_of_function_marker(union mips_instruction *ip)
+{
+        /* jr ra */
+        if (ip->r_format.func == jr_op && ip->r_format.rs == 31)
+                return 1;
+        /* lui gp */
+        if (ip->i_format.opcode == lui_op && ip->i_format.rt == 28)
+                return 1;
+        return 0;
+}
+
+/*
+ * TODO for userspace stack unwinding:
+ * - handle cases where the stack is adjusted inside a function
+ *     (generally doesn't happen)
+ * - find optimal value for max_instr_check
+ * - try to find a way to handle leaf functions
+ */
+
+static inline int unwind_user_frame(struct stackframe *old_frame,
+                                    const unsigned int max_instr_check)
+{
+        struct stackframe new_frame = *old_frame;
+        off_t ra_offset = 0;
+        size_t stack_size = 0;
+        unsigned long addr;
+
+        if (old_frame->pc == 0 || old_frame->sp == 0 || old_frame->ra == 0)
+                return -9;
+
+        for (addr = new_frame.pc; (addr + max_instr_check > new_frame.pc)
+                && (!ra_offset || !stack_size); --addr) {
+                union mips_instruction ip;
+
+                if (get_mem(addr, (unsigned long *) &ip))
+                        return -11;
+
+                if (is_sp_move_ins(&ip)) {
+                        int stack_adjustment = ip.i_format.simmediate;
+                        if (stack_adjustment > 0)
+                                /* This marks the end of the previous function,
+                                   which means we overran. */
+                                break;
+                        stack_size = (unsigned) stack_adjustment;
+                } else if (is_ra_save_ins(&ip)) {
+                        int ra_slot = ip.i_format.simmediate;
+                        if (ra_slot < 0)
+                                /* This shouldn't happen. */
+                                break;
+                        ra_offset = ra_slot;
+                } else if (is_end_of_function_marker(&ip))
+                        break;
+        }
+
+        if (!ra_offset || !stack_size)
+                return -1;
+
+        if (ra_offset) {
+                new_frame.ra = old_frame->sp + ra_offset;
+                if (get_mem(new_frame.ra, &(new_frame.ra)))
+                        return -13;
+        }
+
+        if (stack_size) {
+                new_frame.sp = old_frame->sp + stack_size;
+                if (get_mem(new_frame.sp, &(new_frame.sp)))
+                        return -14;
+        }
+
+        if (new_frame.sp > old_frame->sp)
+                return -2;
+
+        new_frame.pc = old_frame->ra;
+        *old_frame = new_frame;
+
+        return 0;
+}
+
+static inline void do_user_backtrace(unsigned long low_addr,
+                                     struct stackframe *frame,
+                                     unsigned int depth)
+{
+        const unsigned int max_instr_check = 512;
+        const unsigned long high_addr = low_addr + THREAD_SIZE;
+
+        while (depth-- && !unwind_user_frame(frame, max_instr_check)) {
+                oprofile_add_trace(frame->ra);
+                if (frame->sp < low_addr || frame->sp > high_addr)
+                        break;
+        }
+}
+
+#ifndef CONFIG_KALLSYMS
+static inline void do_kernel_backtrace(unsigned long low_addr,
+                                       struct stackframe *frame,
+                                       unsigned int depth) { }
+#else
+static inline void do_kernel_backtrace(unsigned long low_addr,
+                                       struct stackframe *frame,
+                                       unsigned int depth)
+{
+        while (depth-- && frame->pc) {
+                frame->pc = unwind_stack_by_address(low_addr,
+                                                    &(frame->sp),
+                                                    frame->pc,
+                                                    &(frame->ra));
+                oprofile_add_trace(frame->ra);
+        }
+}
+#endif
+
+void notrace op_mips_backtrace(struct pt_regs *const regs, unsigned int depth)
+{
+        struct stackframe frame = { .sp = regs->regs[29],
+                                    .pc = regs->cp0_epc,
+                                    .ra = regs->regs[31] };
+        const int userspace = user_mode(regs);
+        const unsigned long low_addr = ALIGN(frame.sp, THREAD_SIZE);
+
+        if (userspace)
+                do_user_backtrace(low_addr, &frame, depth);
+        else
+                do_kernel_backtrace(low_addr, &frame, depth);
+}
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index f9eb1aba6345..d1f2d4c52d42 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -115,6 +115,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         ops->start              = op_mips_start;
         ops->stop               = op_mips_stop;
         ops->cpu_type           = lmodel->cpu_type;
+        ops->backtrace          = op_mips_backtrace;
 
         printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
                lmodel->cpu_type);
diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h
index f04b54fb37d1..7c2da27ece04 100644
--- a/arch/mips/oprofile/op_impl.h
+++ b/arch/mips/oprofile/op_impl.h
@@ -36,4 +36,6 @@ struct op_mips_model {
         unsigned char num_counters;
 };
 
+void op_mips_backtrace(struct pt_regs * const regs, unsigned int depth);
+
 #endif
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index 1a94c9894188..607192449335 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -10,6 +10,7 @@
  * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org)
  */
 #include <linux/bcd.h>
+#include <linux/i8253.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
@@ -20,7 +21,6 @@
 
 #include <asm/cpu.h>
 #include <asm/mipsregs.h>
-#include <asm/i8253.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/time.h>
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 0904d4d30cb3..ec0be14996a4 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -1,11 +1,11 @@
 #include <linux/types.h>
+#include <linux/i8253.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/smp.h>
 #include <linux/time.h>
 #include <linux/clockchips.h>
 
-#include <asm/i8253.h>
 #include <asm/sni.h>
 #include <asm/time.h>
 #include <asm-generic/rtc.h>
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2729c6663d8a..cdf7a0a64406 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -134,6 +134,7 @@ config PPC
         select GENERIC_IRQ_SHOW_LEVEL
         select HAVE_RCU_TABLE_FREE if SMP
         select HAVE_SYSCALL_TRACEPOINTS
+        select HAVE_BPF_JIT if (PPC64 && NET)
 
 config EARLY_PRINTK
         bool
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index b7212b619c52..b94740f36b1a 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -154,7 +154,8 @@ core-y				+= arch/powerpc/kernel/ \
                                    arch/powerpc/lib/ \
                                    arch/powerpc/sysdev/ \
                                    arch/powerpc/platforms/ \
-                                   arch/powerpc/math-emu/
+                                   arch/powerpc/math-emu/ \
+                                   arch/powerpc/net/
 core-$(CONFIG_XMON)             += arch/powerpc/xmon/
 core-$(CONFIG_KVM)              += arch/powerpc/kvm/
 
diff --git a/arch/powerpc/include/asm/8253pit.h b/arch/powerpc/include/asm/8253pit.h
deleted file mode 100644
index a71c9c1455a7..000000000000
--- a/arch/powerpc/include/asm/8253pit.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h
index 45921672b97a..2cc41c715d2b 100644
--- a/arch/powerpc/include/asm/emulated_ops.h
+++ b/arch/powerpc/include/asm/emulated_ops.h
@@ -78,14 +78,14 @@ extern void ppc_warn_emulated_print(const char *type);
 #define PPC_WARN_EMULATED(type, regs)                                   \
         do {                                                            \
                 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,           \
-                        1, 0, regs, 0);                                 \
+                        1, regs, 0);                                    \
                 __PPC_WARN_EMULATED(type);                              \
         } while (0)
 
 #define PPC_WARN_ALIGNMENT(type, regs)                                  \
         do {                                                            \
                 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,           \
-                        1, 0, regs, regs->dar);                         \
+                        1, regs, regs->dar);                            \
                 __PPC_WARN_EMULATED(type);                              \
         } while (0)
 
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h b/arch/powerpc/include/asm/hw_breakpoint.h
index 1c33ec17ca36..80fd4d2b4a62 100644
--- a/arch/powerpc/include/asm/hw_breakpoint.h
+++ b/arch/powerpc/include/asm/hw_breakpoint.h
@@ -57,7 +57,7 @@ void hw_breakpoint_pmu_read(struct perf_event *bp);
 extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
 
 extern struct pmu perf_ops_bp;
-extern void ptrace_triggered(struct perf_event *bp, int nmi,
+extern void ptrace_triggered(struct perf_event *bp,
                         struct perf_sample_data *data, struct pt_regs *regs);
 static inline void hw_breakpoint_disable(void)
 {
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index b90dbf8e5cd9..90bd3ed48165 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -171,15 +171,9 @@ static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 
 #ifndef CONFIG_PPC64
 
-static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
-{
-        struct pci_controller *host;
-
-        if (bus->self)
-                return pci_device_to_OF_node(bus->self);
-        host = pci_bus_to_host(bus);
-        return host ? host->dn : NULL;
-}
+extern int pci_device_from_OF_node(struct device_node *node,
+                                   u8 *bus, u8 *devfn);
+extern void pci_create_OF_bus_map(void);
 
 static inline int isa_vaddr_is_ioport(void __iomem *address)
 {
@@ -223,17 +217,8 @@ struct pci_dn {
 /* Get the pointer to a device_node's pci_dn */
 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 
-extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
 extern void * update_dn_pci_info(struct device_node *dn, void *data);
 
-/* Get a device_node from a pci_dev.  This code must be fast except
- * in the case where the sysdata is incorrect and needs to be fixed
- * up (this will only happen once). */
-static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
-{
-        return dev->dev.of_node ? dev->dev.of_node : fetch_dev_dn(dev);
-}
-
 static inline int pci_device_from_OF_node(struct device_node *np,
                                           u8 *bus, u8 *devfn)
 {
@@ -244,14 +229,6 @@ static inline int pci_device_from_OF_node(struct device_node *np,
         return 0;
 }
 
-static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
-{
-        if (bus->self)
-                return pci_device_to_OF_node(bus->self);
-        else
-                return bus->dev.of_node; /* Must be root bus (PHB) */
-}
-
 /** Find the bus corresponding to the indicated device node */
 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 7d7790954e02..1f522680ea17 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -179,8 +179,7 @@ extern int remove_phb_dynamic(struct pci_controller *phb);
 extern struct pci_dev *of_create_pci_dev(struct device_node *node,
                                         struct pci_bus *bus, int devfn);
 
-extern void of_scan_pci_bridge(struct device_node *node,
-                                struct pci_dev *dev);
+extern void of_scan_pci_bridge(struct pci_dev *dev);
 
 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
 extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index e472659d906c..e980faae4225 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -71,6 +71,42 @@
 #define PPC_INST_ERATSX                 0x7c000126
 #define PPC_INST_ERATSX_DOT             0x7c000127
 
+/* Misc instructions for BPF compiler */
+#define PPC_INST_LD                     0xe8000000
+#define PPC_INST_LHZ                    0xa0000000
+#define PPC_INST_LWZ                    0x80000000
+#define PPC_INST_STD                    0xf8000000
+#define PPC_INST_STDU                   0xf8000001
+#define PPC_INST_MFLR                   0x7c0802a6
+#define PPC_INST_MTLR                   0x7c0803a6
+#define PPC_INST_CMPWI                  0x2c000000
+#define PPC_INST_CMPDI                  0x2c200000
+#define PPC_INST_CMPLW                  0x7c000040
+#define PPC_INST_CMPLWI                 0x28000000
+#define PPC_INST_ADDI                   0x38000000
+#define PPC_INST_ADDIS                  0x3c000000
+#define PPC_INST_ADD                    0x7c000214
+#define PPC_INST_SUB                    0x7c000050
+#define PPC_INST_BLR                    0x4e800020
+#define PPC_INST_BLRL                   0x4e800021
+#define PPC_INST_MULLW                  0x7c0001d6
+#define PPC_INST_MULHWU                 0x7c000016
+#define PPC_INST_MULLI                  0x1c000000
+#define PPC_INST_DIVWU                  0x7c0003d6
+#define PPC_INST_RLWINM                 0x54000000
+#define PPC_INST_RLDICR                 0x78000004
+#define PPC_INST_SLW                    0x7c000030
+#define PPC_INST_SRW                    0x7c000430
+#define PPC_INST_AND                    0x7c000038
+#define PPC_INST_ANDDOT                 0x7c000039
+#define PPC_INST_OR                     0x7c000378
+#define PPC_INST_ANDI                   0x70000000
+#define PPC_INST_ORI                    0x60000000
+#define PPC_INST_ORIS                   0x64000000
+#define PPC_INST_NEG                    0x7c0000d0
+#define PPC_INST_BRANCH                 0x48000000
+#define PPC_INST_BRANCH_COND            0x40800000
+
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
 #define __PPC_RB(b)     (((b) & 0x1f) << 11)
@@ -83,6 +119,10 @@
 #define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
 #define __PPC_WC(w)     (((w) & 0x3) << 21)
 #define __PPC_WS(w)     (((w) & 0x1f) << 11)
+#define __PPC_SH(s)     __PPC_WS(s)
+#define __PPC_MB(s)     (((s) & 0x1f) << 6)
+#define __PPC_ME(s)     (((s) & 0x1f) << 1)
+#define __PPC_BI(s)     (((s) & 0x1f) << 16)
 
 /*
  * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index c189aa5fe1f4..b823536375dc 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -22,20 +22,6 @@
 
 #define HAVE_ARCH_DEVTREE_FIXUPS
 
-#ifdef CONFIG_PPC32
-/*
- * PCI <-> OF matching functions
- * (XXX should these be here?)
- */
-struct pci_bus;
-struct pci_dev;
-extern int pci_device_from_OF_node(struct device_node *node,
-                                   u8* bus, u8* devfn);
-extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
-extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
-extern void pci_create_OF_bus_map(void);
-#endif
-
 /*
  * OF address retreival & translation
  */
diff --git a/arch/powerpc/kernel/e500-pmu.c b/arch/powerpc/kernel/e500-pmu.c
index b150b510510f..cb2e2949c8d1 100644
--- a/arch/powerpc/kernel/e500-pmu.c
+++ b/arch/powerpc/kernel/e500-pmu.c
@@ -75,6 +75,11 @@ static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1      },
                 [C(OP_PREFETCH)] = {    -1,             -1      },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1      },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
 };
 
 static int num_events = 128;
diff --git a/arch/powerpc/kernel/mpc7450-pmu.c b/arch/powerpc/kernel/mpc7450-pmu.c
index 2cc5e0301d0b..845a58478890 100644
--- a/arch/powerpc/kernel/mpc7450-pmu.c
+++ b/arch/powerpc/kernel/mpc7450-pmu.c
@@ -388,6 +388,11 @@ static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1      },
                 [C(OP_PREFETCH)] = {    -1,             -1      },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1      },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
 };
 
 struct power_pmu mpc7450_pmu = {
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 893af2a9cd03..a3c92770e422 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1097,9 +1097,6 @@ void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
                 if (dev->is_added)
                         continue;
 
-                /* Setup OF node pointer in the device */
-                dev->dev.of_node = pci_device_to_OF_node(dev);
-
                 /* Fixup NUMA node as it may not be setup yet by the generic
                  * code and is needed by the DMA init
                  */
@@ -1685,6 +1682,13 @@ int early_find_capability(struct pci_controller *hose, int bus, int devfn,
         return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
 }
 
+struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
+{
+        struct pci_controller *hose = bus->sysdata;
+
+        return of_node_get(hose->dn);
+}
+
 /**
  * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
  * @hose: Pointer to the PCI host controller instance structure
@@ -1705,7 +1709,6 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
                         hose->global_number);
                 return;
         }
-        bus->dev.of_node = of_node_get(node);
         bus->secondary = hose->first_busno;
         hose->bus = bus;
 
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index bedb370459f2..86585508e9c1 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -167,150 +167,26 @@ pcibios_make_OF_bus_map(void)
 #endif
 }
 
-typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
-
-static struct device_node*
-scan_OF_pci_childs(struct device_node *parent, pci_OF_scan_iterator filter, void* data)
-{
-        struct device_node *node;
-        struct device_node* sub_node;
-
-        for_each_child_of_node(parent, node) {
-                const unsigned int *class_code;
-        
-                if (filter(node, data)) {
-                        of_node_put(node);
-                        return node;
-                }
-
-                /* For PCI<->PCI bridges or CardBus bridges, we go down
-                 * Note: some OFs create a parent node "multifunc-device" as
-                 * a fake root for all functions of a multi-function device,
-                 * we go down them as well.
-                 */
-                class_code = of_get_property(node, "class-code", NULL);
-                if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
-                        (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
-                        strcmp(node->name, "multifunc-device"))
-                        continue;
-                sub_node = scan_OF_pci_childs(node, filter, data);
-                if (sub_node) {
-                        of_node_put(node);
-                        return sub_node;
-                }
-        }
-        return NULL;
-}
-
-static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
-                                               unsigned int devfn)
-{
-        struct device_node *np, *cnp;
-        const u32 *reg;
-        unsigned int psize;
-
-        for_each_child_of_node(parent, np) {
-                reg = of_get_property(np, "reg", &psize);
-                if (reg && psize >= 4 && ((reg[0] >> 8) & 0xff) == devfn)
-                        return np;
-
-                /* Note: some OFs create a parent node "multifunc-device" as
-                 * a fake root for all functions of a multi-function device,
-                 * we go down them as well. */
-                if (!strcmp(np->name, "multifunc-device")) {
-                        cnp = scan_OF_for_pci_dev(np, devfn);
-                        if (cnp)
-                                return cnp;
-                }
-        }
-        return NULL;
-}
-
-
-static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
-{
-        struct device_node *parent, *np;
-
-        /* Are we a root bus ? */
-        if (bus->self == NULL || bus->parent == NULL) {
-                struct pci_controller *hose = pci_bus_to_host(bus);
-                if (hose == NULL)
-                        return NULL;
-                return of_node_get(hose->dn);
-        }
-
-        /* not a root bus, we need to get our parent */
-        parent = scan_OF_for_pci_bus(bus->parent);
-        if (parent == NULL)
-                return NULL;
-
-        /* now iterate for children for a match */
-        np = scan_OF_for_pci_dev(parent, bus->self->devfn);
-        of_node_put(parent);
-
-        return np;
-}
-
-/*
- * Scans the OF tree for a device node matching a PCI device
- */
-struct device_node *
-pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
-{
-        struct device_node *parent, *np;
-
-        pr_debug("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
-        parent = scan_OF_for_pci_bus(bus);
-        if (parent == NULL)
-                return NULL;
-        pr_debug(" parent is %s\n", parent ? parent->full_name : "<NULL>");
-        np = scan_OF_for_pci_dev(parent, devfn);
-        of_node_put(parent);
-        pr_debug(" result is %s\n", np ? np->full_name : "<NULL>");
-
-        /* XXX most callers don't release the returned node
-         * mostly because ppc64 doesn't increase the refcount,
-         * we need to fix that.
-         */
-        return np;
-}
-EXPORT_SYMBOL(pci_busdev_to_OF_node);
-
-struct device_node*
-pci_device_to_OF_node(struct pci_dev *dev)
-{
-        return pci_busdev_to_OF_node(dev->bus, dev->devfn);
-}
-EXPORT_SYMBOL(pci_device_to_OF_node);
-
-static int
-find_OF_pci_device_filter(struct device_node* node, void* data)
-{
-        return ((void *)node == data);
-}
 
 /*
  * Returns the PCI device matching a given OF node
  */
-int
-pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
+int pci_device_from_OF_node(struct device_node *node, u8 *bus, u8 *devfn)
 {
-        const unsigned int *reg;
-        struct pci_controller* hose;
-        struct pci_dev* dev = NULL;
-        
-        /* Make sure it's really a PCI device */
-        hose = pci_find_hose_for_OF_device(node);
-        if (!hose || !hose->dn)
-                return -ENODEV;
-        if (!scan_OF_pci_childs(hose->dn,
-                        find_OF_pci_device_filter, (void *)node))
+        struct pci_dev *dev = NULL;
+        const __be32 *reg;
+        int size;
+
+        /* Check if it might have a chance to be a PCI device */
+        if (!pci_find_hose_for_OF_device(node))
                 return -ENODEV;
-        reg = of_get_property(node, "reg", NULL);
-        if (!reg)
+
+        reg = of_get_property(node, "reg", &size);
+        if (!reg || size < 5 * sizeof(u32))
                 return -ENODEV;
-        *bus = (reg[0] >> 16) & 0xff;
-        *devfn = ((reg[0] >> 8) & 0xff);
+
+        *bus = (be32_to_cpup(&reg[0]) >> 16) & 0xff;
+        *devfn = (be32_to_cpup(&reg[0]) >> 8) & 0xff;
 
         /* Ok, here we need some tweak. If we have already renumbered
          * all busses, we can't rely on the OF bus number any more.
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 6baabc13306a..478f8d78716b 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -142,53 +142,6 @@ void __devinit pci_devs_phb_init_dynamic(struct pci_controller *phb)
         traverse_pci_devices(dn, update_dn_pci_info, phb);
 }
 
-/*
- * Traversal func that looks for a <busno,devfcn> value.
- * If found, the pci_dn is returned (thus terminating the traversal).
- */
-static void *is_devfn_node(struct device_node *dn, void *data)
-{
-        int busno = ((unsigned long)data >> 8) & 0xff;
-        int devfn = ((unsigned long)data) & 0xff;
-        struct pci_dn *pci = dn->data;
-
-        if (pci && (devfn == pci->devfn) && (busno == pci->busno))
-                return dn;
-        return NULL;
-}
-
-/*
- * This is the "slow" path for looking up a device_node from a
- * pci_dev.  It will hunt for the device under its parent's
- * phb and then update of_node pointer.
- *
- * It may also do fixups on the actual device since this happens
- * on the first read/write.
- *
- * Note that it also must deal with devices that don't exist.
- * In this case it may probe for real hardware ("just in case")
- * and add a device_node to the device tree if necessary.
- *
- * Is this function necessary anymore now that dev->dev.of_node is
- * used to store the node pointer?
- *
- */
-struct device_node *fetch_dev_dn(struct pci_dev *dev)
-{
-        struct pci_controller *phb = dev->sysdata;
-        struct device_node *dn;
-        unsigned long searchval = (dev->bus->number << 8) | dev->devfn;
-
-        if (WARN_ON(!phb))
-                return NULL;
-
-        dn = traverse_pci_devices(phb->dn, is_devfn_node, (void *)searchval);
-        if (dn)
-                dev->dev.of_node = dn;
-        return dn;
-}
-EXPORT_SYMBOL(fetch_dev_dn);
-
 /** 
  * pci_devs_phb_init - Initialize phbs and pci devs under them.
  * 
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 1e89a72fd030..fe0a5ad6f73e 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -202,9 +202,9 @@ EXPORT_SYMBOL(of_create_pci_dev);
  * this routine in turn call of_scan_bus() recusively to scan for more child
  * devices.
  */
-void __devinit of_scan_pci_bridge(struct device_node *node,
-                                  struct pci_dev *dev)
+void __devinit of_scan_pci_bridge(struct pci_dev *dev)
 {
+        struct device_node *node = dev->dev.of_node;
         struct pci_bus *bus;
         const u32 *busrange, *ranges;
         int len, i, mode;
@@ -238,7 +238,6 @@ void __devinit of_scan_pci_bridge(struct device_node *node,
         bus->primary = dev->bus->number;
         bus->subordinate = busrange[1];
         bus->bridge_ctl = 0;
-        bus->dev.of_node = of_node_get(node);
 
         /* parse ranges property */
         /* PCI #address-cells == 3 and #size-cells == 2 always */
@@ -335,9 +334,7 @@ static void __devinit __of_scan_bus(struct device_node *node,
         list_for_each_entry(dev, &bus->devices, bus_list) {
                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
-                        struct device_node *child = pci_device_to_OF_node(dev);
-                        if (child)
-                                of_scan_pci_bridge(child, dev);
+                        of_scan_pci_bridge(dev);
                 }
         }
 }
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 822f63008ae1..14967de98876 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -1207,7 +1207,7 @@ struct pmu power_pmu = {
  * here so there is no possibility of being interrupted.
  */
 static void record_and_restart(struct perf_event *event, unsigned long val,
-                               struct pt_regs *regs, int nmi)
+                               struct pt_regs *regs)
 {
         u64 period = event->hw.sample_period;
         s64 prev, delta, left;
@@ -1258,7 +1258,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
                 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
                         perf_get_data_addr(regs, &data.addr);
 
-                if (perf_event_overflow(event, nmi, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         power_pmu_stop(event, 0);
         }
 }
@@ -1346,7 +1346,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
                 if ((int)val < 0) {
                         /* event has overflowed */
                         found = 1;
-                        record_and_restart(event, val, regs, nmi);
+                        record_and_restart(event, val, regs);
                 }
         }
 
diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c
index b0dc8f7069cd..0a6d2a9d569c 100644
--- a/arch/powerpc/kernel/perf_event_fsl_emb.c
+++ b/arch/powerpc/kernel/perf_event_fsl_emb.c
@@ -568,7 +568,7 @@ static struct pmu fsl_emb_pmu = {
  * here so there is no possibility of being interrupted.
  */
 static void record_and_restart(struct perf_event *event, unsigned long val,
-                               struct pt_regs *regs, int nmi)
+                               struct pt_regs *regs)
 {
         u64 period = event->hw.sample_period;
         s64 prev, delta, left;
@@ -616,7 +616,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
                 perf_sample_data_init(&data, 0);
                 data.period = event->hw.last_period;
 
-                if (perf_event_overflow(event, nmi, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         fsl_emb_pmu_stop(event, 0);
         }
 }
@@ -644,7 +644,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
                         if (event) {
                                 /* event has overflowed */
                                 found = 1;
-                                record_and_restart(event, val, regs, nmi);
+                                record_and_restart(event, val, regs);
                         } else {
                                 /*
                                  * Disabled counter is negative,
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
index ead8b3c2649e..e9dbc2d35c9c 100644
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -587,6 +587,11 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1      },
                 [C(OP_PREFETCH)] = {    -1,             -1      },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1      },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
 };
 
 static struct power_pmu power4_pmu = {
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index eca0ac595cb6..f58a2bd41b59 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -653,6 +653,11 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1              },
                 [C(OP_PREFETCH)] = {    -1,             -1              },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1              },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
 };
 
 static struct power_pmu power5p_pmu = {
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
index d5ff0f64a5e6..b1acab684142 100644
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -595,6 +595,11 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1              },
                 [C(OP_PREFETCH)] = {    -1,             -1              },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1              },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
 };
 
 static struct power_pmu power5_pmu = {
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index 31603927e376..b24a3a23d073 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -516,6 +516,11 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1              },
                 [C(OP_PREFETCH)] = {    -1,             -1              },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1              },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
 };
 
 static struct power_pmu power6_pmu = {
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
index 593740fcb799..6d9dccb2ea59 100644
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -342,6 +342,11 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1      },
                 [C(OP_PREFETCH)] = {    -1,             -1      },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1      },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
 };
 
 static struct power_pmu power7_pmu = {
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
index 9a6e093858fe..b121de9658eb 100644
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -467,6 +467,11 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                 [C(OP_WRITE)] = {       -1,             -1      },
                 [C(OP_PREFETCH)] = {    -1,             -1      },
         },
+        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        -1,             -1      },
+                [C(OP_WRITE)] = {       -1,             -1      },
+                [C(OP_PREFETCH)] = {    -1,             -1      },
+        },
 };
 
 static struct power_pmu ppc970_pmu = {
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index cb22024f2b42..05b7dd217f60 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -882,7 +882,7 @@ void user_disable_single_step(struct task_struct *task)
 }
 
 #ifdef CONFIG_HAVE_HW_BREAKPOINT
-void ptrace_triggered(struct perf_event *bp, int nmi,
+void ptrace_triggered(struct perf_event *bp,
                       struct perf_sample_data *data, struct pt_regs *regs)
 {
         struct perf_event_attr attr;
@@ -973,7 +973,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
                                                                 &attr.bp_type);
 
         thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
-                                                        ptrace_triggered, task);
+                                               ptrace_triggered, NULL, task);
         if (IS_ERR(bp)) {
                 thread->ptrace_bps[0] = NULL;
                 ptrace_put_breakpoints(task);
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index f33acfd872ad..03b29a6759ab 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -544,7 +544,7 @@ DEFINE_PER_CPU(u8, irq_work_pending);
 
 #endif /* 32 vs 64 bit */
 
-void set_irq_work_pending(void)
+void arch_irq_work_raise(void)
 {
         preempt_disable();
         set_irq_work_pending_flag();
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index eeb42e06f2d7..78133deb4b64 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -129,6 +129,5 @@ config KVM_E500
           If unsure, say N.
 
 source drivers/vhost/Kconfig
-source drivers/virtio/Kconfig
 
 endif # VIRTUALIZATION
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index ad35f66c69e8..5efe8c96d37f 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -174,7 +174,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
                 die("Weird page fault", regs, SIGSEGV);
         }
 
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
 
         /* When running in the kernel we expect faults to occur only to
          * addresses in user space.  All other faults represent errors in the
@@ -320,7 +320,7 @@ good_area:
         }
         if (ret & VM_FAULT_MAJOR) {
                 current->maj_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
                                      regs, address);
 #ifdef CONFIG_PPC_SMLPAR
                 if (firmware_has_feature(FW_FEATURE_CMO)) {
@@ -331,7 +331,7 @@ good_area:
 #endif
         } else {
                 current->min_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
                                      regs, address);
         }
         up_read(&mm->mmap_sem);
diff --git a/arch/powerpc/net/Makefile b/arch/powerpc/net/Makefile
new file mode 100644
index 000000000000..266b3950c3ac
--- /dev/null
+++ b/arch/powerpc/net/Makefile
@@ -0,0 +1,4 @@
+#
+# Arch-specific network modules
+#
+obj-$(CONFIG_BPF_JIT) += bpf_jit_64.o bpf_jit_comp.o
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
new file mode 100644
index 000000000000..af1ab5e9a691
--- /dev/null
+++ b/arch/powerpc/net/bpf_jit.h
@@ -0,0 +1,227 @@
+/* bpf_jit.h: BPF JIT compiler for PPC64
+ *
+ * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+#ifndef _BPF_JIT_H
+#define _BPF_JIT_H
+
+#define BPF_PPC_STACK_LOCALS    32
+#define BPF_PPC_STACK_BASIC     (48+64)
+#define BPF_PPC_STACK_SAVE      (18*8)
+#define BPF_PPC_STACKFRAME      (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
+                                 BPF_PPC_STACK_SAVE)
+#define BPF_PPC_SLOWPATH_FRAME  (48+64)
+
+/*
+ * Generated code register usage:
+ *
+ * As normal PPC C ABI (e.g. r1=sp, r2=TOC), with:
+ *
+ * skb          r3      (Entry parameter)
+ * A register   r4
+ * X register   r5
+ * addr param   r6
+ * r7-r10       scratch
+ * skb->data    r14
+ * skb headlen  r15     (skb->len - skb->data_len)
+ * m[0]         r16
+ * m[...]       ...
+ * m[15]        r31
+ */
+#define r_skb           3
+#define r_ret           3
+#define r_A             4
+#define r_X             5
+#define r_addr          6
+#define r_scratch1      7
+#define r_D             14
+#define r_HL            15
+#define r_M             16
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Assembly helpers from arch/powerpc/net/bpf_jit.S:
+ */
+extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[];
+
+#define FUNCTION_DESCR_SIZE     24
+
+/*
+ * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
+ * (e.g. LD, ADDI).  If the bottom 16 bits is "-ve", add another bit into the
+ * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
+ */
+#define IMM_H(i)                ((uintptr_t)(i)>>16)
+#define IMM_HA(i)               (((uintptr_t)(i)>>16) +                       \
+                                 (((uintptr_t)(i) & 0x8000) >> 15))
+#define IMM_L(i)                ((uintptr_t)(i) & 0xffff)
+
+#define PLANT_INSTR(d, idx, instr)                                            \
+        do { if (d) { (d)[idx] = instr; } idx++; } while (0)
+#define EMIT(instr)             PLANT_INSTR(image, ctx->idx, instr)
+
+#define PPC_NOP()               EMIT(PPC_INST_NOP)
+#define PPC_BLR()               EMIT(PPC_INST_BLR)
+#define PPC_BLRL()              EMIT(PPC_INST_BLRL)
+#define PPC_MTLR(r)             EMIT(PPC_INST_MTLR | __PPC_RT(r))
+#define PPC_ADDI(d, a, i)       EMIT(PPC_INST_ADDI | __PPC_RT(d) |            \
+                                     __PPC_RA(a) | IMM_L(i))
+#define PPC_MR(d, a)            PPC_OR(d, a, a)
+#define PPC_LI(r, i)            PPC_ADDI(r, 0, i)
+#define PPC_ADDIS(d, a, i)      EMIT(PPC_INST_ADDIS |                         \
+                                     __PPC_RS(d) | __PPC_RA(a) | IMM_L(i))
+#define PPC_LIS(r, i)           PPC_ADDIS(r, 0, i)
+#define PPC_STD(r, base, i)     EMIT(PPC_INST_STD | __PPC_RS(r) |             \
+                                     __PPC_RA(base) | ((i) & 0xfffc))
+
+#define PPC_LD(r, base, i)      EMIT(PPC_INST_LD | __PPC_RT(r) |              \
+                                     __PPC_RA(base) | IMM_L(i))
+#define PPC_LWZ(r, base, i)     EMIT(PPC_INST_LWZ | __PPC_RT(r) |             \
+                                     __PPC_RA(base) | IMM_L(i))
+#define PPC_LHZ(r, base, i)     EMIT(PPC_INST_LHZ | __PPC_RT(r) |             \
+                                     __PPC_RA(base) | IMM_L(i))
+/* Convenience helpers for the above with 'far' offsets: */
+#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i);     \
+                else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
+                        PPC_LD(r, r, IMM_L(i)); } } while(0)
+
+#define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i);   \
+                else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
+                        PPC_LWZ(r, r, IMM_L(i)); } } while(0)
+
+#define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i);   \
+                else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
+                        PPC_LHZ(r, r, IMM_L(i)); } } while(0)
+
+#define PPC_CMPWI(a, i)         EMIT(PPC_INST_CMPWI | __PPC_RA(a) | IMM_L(i))
+#define PPC_CMPDI(a, i)         EMIT(PPC_INST_CMPDI | __PPC_RA(a) | IMM_L(i))
+#define PPC_CMPLWI(a, i)        EMIT(PPC_INST_CMPLWI | __PPC_RA(a) | IMM_L(i))
+#define PPC_CMPLW(a, b)         EMIT(PPC_INST_CMPLW | __PPC_RA(a) | __PPC_RB(b))
+
+#define PPC_SUB(d, a, b)        EMIT(PPC_INST_SUB | __PPC_RT(d) |             \
+                                     __PPC_RB(a) | __PPC_RA(b))
+#define PPC_ADD(d, a, b)        EMIT(PPC_INST_ADD | __PPC_RT(d) |             \
+                                     __PPC_RA(a) | __PPC_RB(b))
+#define PPC_MUL(d, a, b)        EMIT(PPC_INST_MULLW | __PPC_RT(d) |           \
+                                     __PPC_RA(a) | __PPC_RB(b))
+#define PPC_MULHWU(d, a, b)     EMIT(PPC_INST_MULHWU | __PPC_RT(d) |          \
+                                     __PPC_RA(a) | __PPC_RB(b))
+#define PPC_MULI(d, a, i)       EMIT(PPC_INST_MULLI | __PPC_RT(d) |           \
+                                     __PPC_RA(a) | IMM_L(i))
+#define PPC_DIVWU(d, a, b)      EMIT(PPC_INST_DIVWU | __PPC_RT(d) |           \
+                                     __PPC_RA(a) | __PPC_RB(b))
+#define PPC_AND(d, a, b)        EMIT(PPC_INST_AND | __PPC_RA(d) |             \
+                                     __PPC_RS(a) | __PPC_RB(b))
+#define PPC_ANDI(d, a, i)       EMIT(PPC_INST_ANDI | __PPC_RA(d) |            \
+                                     __PPC_RS(a) | IMM_L(i))
+#define PPC_AND_DOT(d, a, b)    EMIT(PPC_INST_ANDDOT | __PPC_RA(d) |          \
+                                     __PPC_RS(a) | __PPC_RB(b))
+#define PPC_OR(d, a, b)         EMIT(PPC_INST_OR | __PPC_RA(d) |              \
+                                     __PPC_RS(a) | __PPC_RB(b))
+#define PPC_ORI(d, a, i)        EMIT(PPC_INST_ORI | __PPC_RA(d) |             \
+                                     __PPC_RS(a) | IMM_L(i))
+#define PPC_ORIS(d, a, i)       EMIT(PPC_INST_ORIS | __PPC_RA(d) |            \
+                                     __PPC_RS(a) | IMM_L(i))
+#define PPC_SLW(d, a, s)        EMIT(PPC_INST_SLW | __PPC_RA(d) |             \
+                                     __PPC_RS(a) | __PPC_RB(s))
+#define PPC_SRW(d, a, s)        EMIT(PPC_INST_SRW | __PPC_RA(d) |             \
+                                     __PPC_RS(a) | __PPC_RB(s))
+/* slwi = rlwinm Rx, Ry, n, 0, 31-n */
+#define PPC_SLWI(d, a, i)       EMIT(PPC_INST_RLWINM | __PPC_RA(d) |          \
+                                     __PPC_RS(a) | __PPC_SH(i) |              \
+                                     __PPC_MB(0) | __PPC_ME(31-(i)))
+/* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
+#define PPC_SRWI(d, a, i)       EMIT(PPC_INST_RLWINM | __PPC_RA(d) |          \
+                                     __PPC_RS(a) | __PPC_SH(32-(i)) |         \
+                                     __PPC_MB(i) | __PPC_ME(31))
+/* sldi = rldicr Rx, Ry, n, 63-n */
+#define PPC_SLDI(d, a, i)       EMIT(PPC_INST_RLDICR | __PPC_RA(d) |          \
+                                     __PPC_RS(a) | __PPC_SH(i) |              \
+                                     __PPC_MB(63-(i)) | (((i) & 0x20) >> 4))
+#define PPC_NEG(d, a)           EMIT(PPC_INST_NEG | __PPC_RT(d) | __PPC_RA(a))
+
+/* Long jump; (unconditional 'branch') */
+#define PPC_JMP(dest)           EMIT(PPC_INST_BRANCH |                        \
+                                     (((dest) - (ctx->idx * 4)) & 0x03fffffc))
+/* "cond" here covers BO:BI fields. */
+#define PPC_BCC_SHORT(cond, dest)       EMIT(PPC_INST_BRANCH_COND |           \
+                                             (((cond) & 0x3ff) << 16) |       \
+                                             (((dest) - (ctx->idx * 4)) &     \
+                                              0xfffc))
+#define PPC_LI32(d, i)          do { PPC_LI(d, IMM_L(i));                     \
+                if ((u32)(uintptr_t)(i) >= 32768) {                           \
+                        PPC_ADDIS(d, d, IMM_HA(i));                           \
+                } } while(0)
+#define PPC_LI64(d, i)          do {                                          \
+                if (!((uintptr_t)(i) & 0xffffffff00000000ULL))                \
+                        PPC_LI32(d, i);                                       \
+                else {                                                        \
+                        PPC_LIS(d, ((uintptr_t)(i) >> 48));                   \
+                        if ((uintptr_t)(i) & 0x0000ffff00000000ULL)           \
+                                PPC_ORI(d, d,                                 \
+                                        ((uintptr_t)(i) >> 32) & 0xffff);     \
+                        PPC_SLDI(d, d, 32);                                   \
+                        if ((uintptr_t)(i) & 0x00000000ffff0000ULL)           \
+                                PPC_ORIS(d, d,                                \
+                                         ((uintptr_t)(i) >> 16) & 0xffff);    \
+                        if ((uintptr_t)(i) & 0x000000000000ffffULL)           \
+                                PPC_ORI(d, d, (uintptr_t)(i) & 0xffff);       \
+                } } while (0);
+
+static inline bool is_nearbranch(int offset)
+{
+        return (offset < 32768) && (offset >= -32768);
+}
+
+/*
+ * The fly in the ointment of code size changing from pass to pass is
+ * avoided by padding the short branch case with a NOP.  If code size differs
+ * with different branch reaches we will have the issue of code moving from
+ * one pass to the next and will need a few passes to converge on a stable
+ * state.
+ */
+#define PPC_BCC(cond, dest)     do {                                          \
+                if (is_nearbranch((dest) - (ctx->idx * 4))) {                 \
+                        PPC_BCC_SHORT(cond, dest);                            \
+                        PPC_NOP();                                            \
+                } else {                                                      \
+                        /* Flip the 'T or F' bit to invert comparison */      \
+                        PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4);  \
+                        PPC_JMP(dest);                                        \
+                } } while(0)
+
+/* To create a branch condition, select a bit of cr0... */
+#define CR0_LT          0
+#define CR0_GT          1
+#define CR0_EQ          2
+/* ...and modify BO[3] */
+#define COND_CMP_TRUE   0x100
+#define COND_CMP_FALSE  0x000
+/* Together, they make all required comparisons: */
+#define COND_GT         (CR0_GT | COND_CMP_TRUE)
+#define COND_GE         (CR0_LT | COND_CMP_FALSE)
+#define COND_EQ         (CR0_EQ | COND_CMP_TRUE)
+#define COND_NE         (CR0_EQ | COND_CMP_FALSE)
+#define COND_LT         (CR0_LT | COND_CMP_TRUE)
+
+#define SEEN_DATAREF 0x10000 /* might call external helpers */
+#define SEEN_XREG    0x20000 /* X reg is used */
+#define SEEN_MEM     0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary
+                              * storage */
+#define SEEN_MEM_MSK 0x0ffff
+
+struct codegen_context {
+        unsigned int seen;
+        unsigned int idx;
+        int pc_ret0; /* bpf index of first RET #0 instruction (if any) */
+};
+
+#endif
+
+#endif
diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
new file mode 100644
index 000000000000..ff4506e85cce
--- /dev/null
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -0,0 +1,138 @@
+/* bpf_jit.S: Packet/header access helper functions
+ * for PPC64 BPF compiler.
+ *
+ * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#include <asm/ppc_asm.h>
+#include "bpf_jit.h"
+
+/*
+ * All of these routines are called directly from generated code,
+ * whose register usage is:
+ *
+ * r3           skb
+ * r4,r5        A,X
+ * r6           *** address parameter to helper ***
+ * r7-r10       scratch
+ * r14          skb->data
+ * r15          skb headlen
+ * r16-31       M[]
+ */
+
+/*
+ * To consider: These helpers are so small it could be better to just
+ * generate them inline.  Inline code can do the simple headlen check
+ * then branch directly to slow_path_XXX if required.  (In fact, could
+ * load a spare GPR with the address of slow_path_generic and pass size
+ * as an argument, making the call site a mtlr, li and bllr.)
+ *
+ * Technically, the "is addr < 0" check is unnecessary & slowing down
+ * the ABS path, as it's statically checked on generation.
+ */
+        .globl  sk_load_word
+sk_load_word:
+        cmpdi   r_addr, 0
+        blt     bpf_error
+        /* Are we accessing past headlen? */
+        subi    r_scratch1, r_HL, 4
+        cmpd    r_scratch1, r_addr
+        blt     bpf_slow_path_word
+        /* Nope, just hitting the header.  cr0 here is eq or gt! */
+        lwzx    r_A, r_D, r_addr
+        /* When big endian we don't need to byteswap. */
+        blr     /* Return success, cr0 != LT */
+
+        .globl  sk_load_half
+sk_load_half:
+        cmpdi   r_addr, 0
+        blt     bpf_error
+        subi    r_scratch1, r_HL, 2
+        cmpd    r_scratch1, r_addr
+        blt     bpf_slow_path_half
+        lhzx    r_A, r_D, r_addr
+        blr
+
+        .globl  sk_load_byte
+sk_load_byte:
+        cmpdi   r_addr, 0
+        blt     bpf_error
+        cmpd    r_HL, r_addr
+        ble     bpf_slow_path_byte
+        lbzx    r_A, r_D, r_addr
+        blr
+
+/*
+ * BPF_S_LDX_B_MSH: ldxb  4*([offset]&0xf)
+ * r_addr is the offset value, already known positive
+ */
+        .globl sk_load_byte_msh
+sk_load_byte_msh:
+        cmpd    r_HL, r_addr
+        ble     bpf_slow_path_byte_msh
+        lbzx    r_X, r_D, r_addr
+        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
+        blr
+
+bpf_error:
+        /* Entered with cr0 = lt */
+        li      r3, 0
+        /* Generated code will 'blt epilogue', returning 0. */
+        blr
+
+/* Call out to skb_copy_bits:
+ * We'll need to back up our volatile regs first; we have
+ * local variable space at r1+(BPF_PPC_STACK_BASIC).
+ * Allocate a new stack frame here to remain ABI-compliant in
+ * stashing LR.
+ */
+#define bpf_slow_path_common(SIZE)                              \
+        mflr    r0;                                             \
+        std     r0, 16(r1);                                     \
+        /* R3 goes in parameter space of caller's frame */      \
+        std     r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        std     r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        std     r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        addi    r5, r1, BPF_PPC_STACK_BASIC+(2*8);              \
+        stdu    r1, -BPF_PPC_SLOWPATH_FRAME(r1);                \
+        /* R3 = r_skb, as passed */                             \
+        mr      r4, r_addr;                                     \
+        li      r6, SIZE;                                       \
+        bl      skb_copy_bits;                                  \
+        /* R3 = 0 on success */                                 \
+        addi    r1, r1, BPF_PPC_SLOWPATH_FRAME;                 \
+        ld      r0, 16(r1);                                     \
+        ld      r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        ld      r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        mtlr    r0;                                             \
+        cmpdi   r3, 0;                                          \
+        blt     bpf_error;      /* cr0 = LT */                  \
+        ld      r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        /* Great success! */
+
+bpf_slow_path_word:
+        bpf_slow_path_common(4)
+        /* Data value is on stack, and cr0 != LT */
+        lwz     r_A, BPF_PPC_STACK_BASIC+(2*8)(r1)
+        blr
+
+bpf_slow_path_half:
+        bpf_slow_path_common(2)
+        lhz     r_A, BPF_PPC_STACK_BASIC+(2*8)(r1)
+        blr
+
+bpf_slow_path_byte:
+        bpf_slow_path_common(1)
+        lbz     r_A, BPF_PPC_STACK_BASIC+(2*8)(r1)
+        blr
+
+bpf_slow_path_byte_msh:
+        bpf_slow_path_common(1)
+        lbz     r_X, BPF_PPC_STACK_BASIC+(2*8)(r1)
+        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
+        blr
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
new file mode 100644
index 000000000000..73619d3aeb6c
--- /dev/null
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -0,0 +1,694 @@
+/* bpf_jit_comp.c: BPF JIT compiler for PPC64
+ *
+ * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
+ *
+ * Based on the x86 BPF compiler, by Eric Dumazet (eric.dumazet@gmail.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+#include <linux/moduleloader.h>
+#include <asm/cacheflush.h>
+#include <linux/netdevice.h>
+#include <linux/filter.h>
+#include "bpf_jit.h"
+
+#ifndef __BIG_ENDIAN
+/* There are endianness assumptions herein. */
+#error "Little-endian PPC not supported in BPF compiler"
+#endif
+
+int bpf_jit_enable __read_mostly;
+
+
+static inline void bpf_flush_icache(void *start, void *end)
+{
+        smp_wmb();
+        flush_icache_range((unsigned long)start, (unsigned long)end);
+}
+
+static void bpf_jit_build_prologue(struct sk_filter *fp, u32 *image,
+                                   struct codegen_context *ctx)
+{
+        int i;
+        const struct sock_filter *filter = fp->insns;
+
+        if (ctx->seen & (SEEN_MEM | SEEN_DATAREF)) {
+                /* Make stackframe */
+                if (ctx->seen & SEEN_DATAREF) {
+                        /* If we call any helpers (for loads), save LR */
+                        EMIT(PPC_INST_MFLR | __PPC_RT(0));
+                        PPC_STD(0, 1, 16);
+
+                        /* Back up non-volatile regs. */
+                        PPC_STD(r_D, 1, -(8*(32-r_D)));
+                        PPC_STD(r_HL, 1, -(8*(32-r_HL)));
+                }
+                if (ctx->seen & SEEN_MEM) {
+                        /*
+                         * Conditionally save regs r15-r31 as some will be used
+                         * for M[] data.
+                         */
+                        for (i = r_M; i < (r_M+16); i++) {
+                                if (ctx->seen & (1 << (i-r_M)))
+                                        PPC_STD(i, 1, -(8*(32-i)));
+                        }
+                }
+                EMIT(PPC_INST_STDU | __PPC_RS(1) | __PPC_RA(1) |
+                     (-BPF_PPC_STACKFRAME & 0xfffc));
+        }
+
+        if (ctx->seen & SEEN_DATAREF) {
+                /*
+                 * If this filter needs to access skb data,
+                 * prepare r_D and r_HL:
+                 *  r_HL = skb->len - skb->data_len
+                 *  r_D  = skb->data
+                 */
+                PPC_LWZ_OFFS(r_scratch1, r_skb, offsetof(struct sk_buff,
+                                                         data_len));
+                PPC_LWZ_OFFS(r_HL, r_skb, offsetof(struct sk_buff, len));
+                PPC_SUB(r_HL, r_HL, r_scratch1);
+                PPC_LD_OFFS(r_D, r_skb, offsetof(struct sk_buff, data));
+        }
+
+        if (ctx->seen & SEEN_XREG) {
+                /*
+                 * TODO: Could also detect whether first instr. sets X and
+                 * avoid this (as below, with A).
+                 */
+                PPC_LI(r_X, 0);
+        }
+
+        switch (filter[0].code) {
+        case BPF_S_RET_K:
+        case BPF_S_LD_W_LEN:
+        case BPF_S_ANC_PROTOCOL:
+        case BPF_S_ANC_IFINDEX:
+        case BPF_S_ANC_MARK:
+        case BPF_S_ANC_RXHASH:
+        case BPF_S_ANC_CPU:
+        case BPF_S_ANC_QUEUE:
+        case BPF_S_LD_W_ABS:
+        case BPF_S_LD_H_ABS:
+        case BPF_S_LD_B_ABS:
+                /* first instruction sets A register (or is RET 'constant') */
+                break;
+        default:
+                /* make sure we dont leak kernel information to user */
+                PPC_LI(r_A, 0);
+        }
+}
+
+static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
+{
+        int i;
+
+        if (ctx->seen & (SEEN_MEM | SEEN_DATAREF)) {
+                PPC_ADDI(1, 1, BPF_PPC_STACKFRAME);
+                if (ctx->seen & SEEN_DATAREF) {
+                        PPC_LD(0, 1, 16);
+                        PPC_MTLR(0);
+                        PPC_LD(r_D, 1, -(8*(32-r_D)));
+                        PPC_LD(r_HL, 1, -(8*(32-r_HL)));
+                }
+                if (ctx->seen & SEEN_MEM) {
+                        /* Restore any saved non-vol registers */
+                        for (i = r_M; i < (r_M+16); i++) {
+                                if (ctx->seen & (1 << (i-r_M)))
+                                        PPC_LD(i, 1, -(8*(32-i)));
+                        }
+                }
+        }
+        /* The RETs have left a return value in R3. */
+
+        PPC_BLR();
+}
+
+/* Assemble the body code between the prologue & epilogue. */
+static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
+                              struct codegen_context *ctx,
+                              unsigned int *addrs)
+{
+        const struct sock_filter *filter = fp->insns;
+        int flen = fp->len;
+        u8 *func;
+        unsigned int true_cond;
+        int i;
+
+        /* Start of epilogue code */
+        unsigned int exit_addr = addrs[flen];
+
+        for (i = 0; i < flen; i++) {
+                unsigned int K = filter[i].k;
+
+                /*
+                 * addrs[] maps a BPF bytecode address into a real offset from
+                 * the start of the body code.
+                 */
+                addrs[i] = ctx->idx * 4;
+
+                switch (filter[i].code) {
+                        /*** ALU ops ***/
+                case BPF_S_ALU_ADD_X: /* A += X; */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_ADD(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_ADD_K: /* A += K; */
+                        if (!K)
+                                break;
+                        PPC_ADDI(r_A, r_A, IMM_L(K));
+                        if (K >= 32768)
+                                PPC_ADDIS(r_A, r_A, IMM_HA(K));
+                        break;
+                case BPF_S_ALU_SUB_X: /* A -= X; */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_SUB(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_SUB_K: /* A -= K */
+                        if (!K)
+                                break;
+                        PPC_ADDI(r_A, r_A, IMM_L(-K));
+                        if (K >= 32768)
+                                PPC_ADDIS(r_A, r_A, IMM_HA(-K));
+                        break;
+                case BPF_S_ALU_MUL_X: /* A *= X; */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_MUL(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_MUL_K: /* A *= K */
+                        if (K < 32768)
+                                PPC_MULI(r_A, r_A, K);
+                        else {
+                                PPC_LI32(r_scratch1, K);
+                                PPC_MUL(r_A, r_A, r_scratch1);
+                        }
+                        break;
+                case BPF_S_ALU_DIV_X: /* A /= X; */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_CMPWI(r_X, 0);
+                        if (ctx->pc_ret0 != -1) {
+                                PPC_BCC(COND_EQ, addrs[ctx->pc_ret0]);
+                        } else {
+                                /*
+                                 * Exit, returning 0; first pass hits here
+                                 * (longer worst-case code size).
+                                 */
+                                PPC_BCC_SHORT(COND_NE, (ctx->idx*4)+12);
+                                PPC_LI(r_ret, 0);
+                                PPC_JMP(exit_addr);
+                        }
+                        PPC_DIVWU(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_DIV_K: /* A = reciprocal_divide(A, K); */
+                        PPC_LI32(r_scratch1, K);
+                        /* Top 32 bits of 64bit result -> A */
+                        PPC_MULHWU(r_A, r_A, r_scratch1);
+                        break;
+                case BPF_S_ALU_AND_X:
+                        ctx->seen |= SEEN_XREG;
+                        PPC_AND(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_AND_K:
+                        if (!IMM_H(K))
+                                PPC_ANDI(r_A, r_A, K);
+                        else {
+                                PPC_LI32(r_scratch1, K);
+                                PPC_AND(r_A, r_A, r_scratch1);
+                        }
+                        break;
+                case BPF_S_ALU_OR_X:
+                        ctx->seen |= SEEN_XREG;
+                        PPC_OR(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_OR_K:
+                        if (IMM_L(K))
+                                PPC_ORI(r_A, r_A, IMM_L(K));
+                        if (K >= 65536)
+                                PPC_ORIS(r_A, r_A, IMM_H(K));
+                        break;
+                case BPF_S_ALU_LSH_X: /* A <<= X; */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_SLW(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_LSH_K:
+                        if (K == 0)
+                                break;
+                        else
+                                PPC_SLWI(r_A, r_A, K);
+                        break;
+                case BPF_S_ALU_RSH_X: /* A >>= X; */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_SRW(r_A, r_A, r_X);
+                        break;
+                case BPF_S_ALU_RSH_K: /* A >>= K; */
+                        if (K == 0)
+                                break;
+                        else
+                                PPC_SRWI(r_A, r_A, K);
+                        break;
+                case BPF_S_ALU_NEG:
+                        PPC_NEG(r_A, r_A);
+                        break;
+                case BPF_S_RET_K:
+                        PPC_LI32(r_ret, K);
+                        if (!K) {
+                                if (ctx->pc_ret0 == -1)
+                                        ctx->pc_ret0 = i;
+                        }
+                        /*
+                         * If this isn't the very last instruction, branch to
+                         * the epilogue if we've stuff to clean up.  Otherwise,
+                         * if there's nothing to tidy, just return.  If we /are/
+                         * the last instruction, we're about to fall through to
+                         * the epilogue to return.
+                         */
+                        if (i != flen - 1) {
+                                /*
+                                 * Note: 'seen' is properly valid only on pass
+                                 * #2.  Both parts of this conditional are the
+                                 * same instruction size though, meaning the
+                                 * first pass will still correctly determine the
+                                 * code size/addresses.
+                                 */
+                                if (ctx->seen)
+                                        PPC_JMP(exit_addr);
+                                else
+                                        PPC_BLR();
+                        }
+                        break;
+                case BPF_S_RET_A:
+                        PPC_MR(r_ret, r_A);
+                        if (i != flen - 1) {
+                                if (ctx->seen)
+                                        PPC_JMP(exit_addr);
+                                else
+                                        PPC_BLR();
+                        }
+                        break;
+                case BPF_S_MISC_TAX: /* X = A */
+                        PPC_MR(r_X, r_A);
+                        break;
+                case BPF_S_MISC_TXA: /* A = X */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_MR(r_A, r_X);
+                        break;
+
+                        /*** Constant loads/M[] access ***/
+                case BPF_S_LD_IMM: /* A = K */
+                        PPC_LI32(r_A, K);
+                        break;
+                case BPF_S_LDX_IMM: /* X = K */
+                        PPC_LI32(r_X, K);
+                        break;
+                case BPF_S_LD_MEM: /* A = mem[K] */
+                        PPC_MR(r_A, r_M + (K & 0xf));
+                        ctx->seen |= SEEN_MEM | (1<<(K & 0xf));
+                        break;
+                case BPF_S_LDX_MEM: /* X = mem[K] */
+                        PPC_MR(r_X, r_M + (K & 0xf));
+                        ctx->seen |= SEEN_MEM | (1<<(K & 0xf));
+                        break;
+                case BPF_S_ST: /* mem[K] = A */
+                        PPC_MR(r_M + (K & 0xf), r_A);
+                        ctx->seen |= SEEN_MEM | (1<<(K & 0xf));
+                        break;
+                case BPF_S_STX: /* mem[K] = X */
+                        PPC_MR(r_M + (K & 0xf), r_X);
+                        ctx->seen |= SEEN_XREG | SEEN_MEM | (1<<(K & 0xf));
+                        break;
+                case BPF_S_LD_W_LEN: /* A = skb->len; */
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
+                        PPC_LWZ_OFFS(r_A, r_skb, offsetof(struct sk_buff, len));
+                        break;
+                case BPF_S_LDX_W_LEN: /* X = skb->len; */
+                        PPC_LWZ_OFFS(r_X, r_skb, offsetof(struct sk_buff, len));
+                        break;
+
+                        /*** Ancillary info loads ***/
+
+                        /* None of the BPF_S_ANC* codes appear to be passed by
+                         * sk_chk_filter().  The interpreter and the x86 BPF
+                         * compiler implement them so we do too -- they may be
+                         * planted in future.
+                         */
+                case BPF_S_ANC_PROTOCOL: /* A = ntohs(skb->protocol); */
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
+                                                  protocol) != 2);
+                        PPC_LHZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
+                                                          protocol));
+                        /* ntohs is a NOP with BE loads. */
+                        break;
+                case BPF_S_ANC_IFINDEX:
+                        PPC_LD_OFFS(r_scratch1, r_skb, offsetof(struct sk_buff,
+                                                                dev));
+                        PPC_CMPDI(r_scratch1, 0);
+                        if (ctx->pc_ret0 != -1) {
+                                PPC_BCC(COND_EQ, addrs[ctx->pc_ret0]);
+                        } else {
+                                /* Exit, returning 0; first pass hits here. */
+                                PPC_BCC_SHORT(COND_NE, (ctx->idx*4)+12);
+                                PPC_LI(r_ret, 0);
+                                PPC_JMP(exit_addr);
+                        }
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
+                                                  ifindex) != 4);
+                        PPC_LWZ_OFFS(r_A, r_scratch1,
+                                     offsetof(struct net_device, ifindex));
+                        break;
+                case BPF_S_ANC_MARK:
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
+                        PPC_LWZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
+                                                          mark));
+                        break;
+                case BPF_S_ANC_RXHASH:
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
+                        PPC_LWZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
+                                                          rxhash));
+                        break;
+                case BPF_S_ANC_QUEUE:
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
+                                                  queue_mapping) != 2);
+                        PPC_LHZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
+                                                          queue_mapping));
+                        break;
+                case BPF_S_ANC_CPU:
+#ifdef CONFIG_SMP
+                        /*
+                         * PACA ptr is r13:
+                         * raw_smp_processor_id() = local_paca->paca_index
+                         */
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct paca_struct,
+                                                  paca_index) != 2);
+                        PPC_LHZ_OFFS(r_A, 13,
+                                     offsetof(struct paca_struct, paca_index));
+#else
+                        PPC_LI(r_A, 0);
+#endif
+                        break;
+
+                        /*** Absolute loads from packet header/data ***/
+                case BPF_S_LD_W_ABS:
+                        func = sk_load_word;
+                        goto common_load;
+                case BPF_S_LD_H_ABS:
+                        func = sk_load_half;
+                        goto common_load;
+                case BPF_S_LD_B_ABS:
+                        func = sk_load_byte;
+                common_load:
+                        /*
+                         * Load from [K].  Reference with the (negative)
+                         * SKF_NET_OFF/SKF_LL_OFF offsets is unsupported.
+                         */
+                        ctx->seen |= SEEN_DATAREF;
+                        if ((int)K < 0)
+                                return -ENOTSUPP;
+                        PPC_LI64(r_scratch1, func);
+                        PPC_MTLR(r_scratch1);
+                        PPC_LI32(r_addr, K);
+                        PPC_BLRL();
+                        /*
+                         * Helper returns 'lt' condition on error, and an
+                         * appropriate return value in r3
+                         */
+                        PPC_BCC(COND_LT, exit_addr);
+                        break;
+
+                        /*** Indirect loads from packet header/data ***/
+                case BPF_S_LD_W_IND:
+                        func = sk_load_word;
+                        goto common_load_ind;
+                case BPF_S_LD_H_IND:
+                        func = sk_load_half;
+                        goto common_load_ind;
+                case BPF_S_LD_B_IND:
+                        func = sk_load_byte;
+                common_load_ind:
+                        /*
+                         * Load from [X + K].  Negative offsets are tested for
+                         * in the helper functions, and result in a 'ret 0'.
+                         */
+                        ctx->seen |= SEEN_DATAREF | SEEN_XREG;
+                        PPC_LI64(r_scratch1, func);
+                        PPC_MTLR(r_scratch1);
+                        PPC_ADDI(r_addr, r_X, IMM_L(K));
+                        if (K >= 32768)
+                                PPC_ADDIS(r_addr, r_addr, IMM_HA(K));
+                        PPC_BLRL();
+                        /* If error, cr0.LT set */
+                        PPC_BCC(COND_LT, exit_addr);
+                        break;
+
+                case BPF_S_LDX_B_MSH:
+                        /*
+                         * x86 version drops packet (RET 0) when K<0, whereas
+                         * interpreter does allow K<0 (__load_pointer, special
+                         * ancillary data).  common_load returns ENOTSUPP if K<0,
+                         * so we fall back to interpreter & filter works.
+                         */
+                        func = sk_load_byte_msh;
+                        goto common_load;
+                        break;
+
+                        /*** Jump and branches ***/
+                case BPF_S_JMP_JA:
+                        if (K != 0)
+                                PPC_JMP(addrs[i + 1 + K]);
+                        break;
+
+                case BPF_S_JMP_JGT_K:
+                case BPF_S_JMP_JGT_X:
+                        true_cond = COND_GT;
+                        goto cond_branch;
+                case BPF_S_JMP_JGE_K:
+                case BPF_S_JMP_JGE_X:
+                        true_cond = COND_GE;
+                        goto cond_branch;
+                case BPF_S_JMP_JEQ_K:
+                case BPF_S_JMP_JEQ_X:
+                        true_cond = COND_EQ;
+                        goto cond_branch;
+                case BPF_S_JMP_JSET_K:
+                case BPF_S_JMP_JSET_X:
+                        true_cond = COND_NE;
+                        /* Fall through */
+                cond_branch:
+                        /* same targets, can avoid doing the test :) */
+                        if (filter[i].jt == filter[i].jf) {
+                                if (filter[i].jt > 0)
+                                        PPC_JMP(addrs[i + 1 + filter[i].jt]);
+                                break;
+                        }
+
+                        switch (filter[i].code) {
+                        case BPF_S_JMP_JGT_X:
+                        case BPF_S_JMP_JGE_X:
+                        case BPF_S_JMP_JEQ_X:
+                                ctx->seen |= SEEN_XREG;
+                                PPC_CMPLW(r_A, r_X);
+                                break;
+                        case BPF_S_JMP_JSET_X:
+                                ctx->seen |= SEEN_XREG;
+                                PPC_AND_DOT(r_scratch1, r_A, r_X);
+                                break;
+                        case BPF_S_JMP_JEQ_K:
+                        case BPF_S_JMP_JGT_K:
+                        case BPF_S_JMP_JGE_K:
+                                if (K < 32768)
+                                        PPC_CMPLWI(r_A, K);
+                                else {
+                                        PPC_LI32(r_scratch1, K);
+                                        PPC_CMPLW(r_A, r_scratch1);
+                                }
+                                break;
+                        case BPF_S_JMP_JSET_K:
+                                if (K < 32768)
+                                        /* PPC_ANDI is /only/ dot-form */
+                                        PPC_ANDI(r_scratch1, r_A, K);
+                                else {
+                                        PPC_LI32(r_scratch1, K);
+                                        PPC_AND_DOT(r_scratch1, r_A,
+                                                    r_scratch1);
+                                }
+                                break;
+                        }
+                        /* Sometimes branches are constructed "backward", with
+                         * the false path being the branch and true path being
+                         * a fallthrough to the next instruction.
+                         */
+                        if (filter[i].jt == 0)
+                                /* Swap the sense of the branch */
+                                PPC_BCC(true_cond ^ COND_CMP_TRUE,
+                                        addrs[i + 1 + filter[i].jf]);
+                        else {
+                                PPC_BCC(true_cond, addrs[i + 1 + filter[i].jt]);
+                                if (filter[i].jf != 0)
+                                        PPC_JMP(addrs[i + 1 + filter[i].jf]);
+                        }
+                        break;
+                default:
+                        /* The filter contains something cruel & unusual.
+                         * We don't handle it, but also there shouldn't be
+                         * anything missing from our list.
+                         */
+                        if (printk_ratelimit())
+                                pr_err("BPF filter opcode %04x (@%d) unsupported\n",
+                                       filter[i].code, i);
+                        return -ENOTSUPP;
+                }
+
+        }
+        /* Set end-of-body-code address for exit. */
+        addrs[i] = ctx->idx * 4;
+
+        return 0;
+}
+
+void bpf_jit_compile(struct sk_filter *fp)
+{
+        unsigned int proglen;
+        unsigned int alloclen;
+        u32 *image = NULL;
+        u32 *code_base;
+        unsigned int *addrs;
+        struct codegen_context cgctx;
+        int pass;
+        int flen = fp->len;
+
+        if (!bpf_jit_enable)
+                return;
+
+        addrs = kzalloc((flen+1) * sizeof(*addrs), GFP_KERNEL);
+        if (addrs == NULL)
+                return;
+
+        /*
+         * There are multiple assembly passes as the generated code will change
+         * size as it settles down, figuring out the max branch offsets/exit
+         * paths required.
+         *
+         * The range of standard conditional branches is +/- 32Kbytes.  Since
+         * BPF_MAXINSNS = 4096, we can only jump from (worst case) start to
+         * finish with 8 bytes/instruction.  Not feasible, so long jumps are
+         * used, distinct from short branches.
+         *
+         * Current:
+         *
+         * For now, both branch types assemble to 2 words (short branches padded
+         * with a NOP); this is less efficient, but assembly will always complete
+         * after exactly 3 passes:
+         *
+         * First pass: No code buffer; Program is "faux-generated" -- no code
+         * emitted but maximum size of output determined (and addrs[] filled
+         * in).  Also, we note whether we use M[], whether we use skb data, etc.
+         * All generation choices assumed to be 'worst-case', e.g. branches all
+         * far (2 instructions), return path code reduction not available, etc.
+         *
+         * Second pass: Code buffer allocated with size determined previously.
+         * Prologue generated to support features we have seen used.  Exit paths
+         * determined and addrs[] is filled in again, as code may be slightly
+         * smaller as a result.
+         *
+         * Third pass: Code generated 'for real', and branch destinations
+         * determined from now-accurate addrs[] map.
+         *
+         * Ideal:
+         *
+         * If we optimise this, near branches will be shorter.  On the
+         * first assembly pass, we should err on the side of caution and
+         * generate the biggest code.  On subsequent passes, branches will be
+         * generated short or long and code size will reduce.  With smaller
+         * code, more branches may fall into the short category, and code will
+         * reduce more.
+         *
+         * Finally, if we see one pass generate code the same size as the
+         * previous pass we have converged and should now generate code for
+         * real.  Allocating at the end will also save the memory that would
+         * otherwise be wasted by the (small) current code shrinkage.
+         * Preferably, we should do a small number of passes (e.g. 5) and if we
+         * haven't converged by then, get impatient and force code to generate
+         * as-is, even if the odd branch would be left long.  The chances of a
+         * long jump are tiny with all but the most enormous of BPF filter
+         * inputs, so we should usually converge on the third pass.
+         */
+
+        cgctx.idx = 0;
+        cgctx.seen = 0;
+        cgctx.pc_ret0 = -1;
+        /* Scouting faux-generate pass 0 */
+        if (bpf_jit_build_body(fp, 0, &cgctx, addrs))
+                /* We hit something illegal or unsupported. */
+                goto out;
+
+        /*
+         * Pretend to build prologue, given the features we've seen.  This will
+         * update ctgtx.idx as it pretends to output instructions, then we can
+         * calculate total size from idx.
+         */
+        bpf_jit_build_prologue(fp, 0, &cgctx);
+        bpf_jit_build_epilogue(0, &cgctx);
+
+        proglen = cgctx.idx * 4;
+        alloclen = proglen + FUNCTION_DESCR_SIZE;
+        image = module_alloc(max_t(unsigned int, alloclen,
+                                   sizeof(struct work_struct)));
+        if (!image)
+                goto out;
+
+        code_base = image + (FUNCTION_DESCR_SIZE/4);
+
+        /* Code generation passes 1-2 */
+        for (pass = 1; pass < 3; pass++) {
+                /* Now build the prologue, body code & epilogue for real. */
+                cgctx.idx = 0;
+                bpf_jit_build_prologue(fp, code_base, &cgctx);
+                bpf_jit_build_body(fp, code_base, &cgctx, addrs);
+                bpf_jit_build_epilogue(code_base, &cgctx);
+
+                if (bpf_jit_enable > 1)
+                        pr_info("Pass %d: shrink = %d, seen = 0x%x\n", pass,
+                                proglen - (cgctx.idx * 4), cgctx.seen);
+        }
+
+        if (bpf_jit_enable > 1)
+                pr_info("flen=%d proglen=%u pass=%d image=%p\n",
+                       flen, proglen, pass, image);
+
+        if (image) {
+                if (bpf_jit_enable > 1)
+                        print_hex_dump(KERN_ERR, "JIT code: ",
+                                       DUMP_PREFIX_ADDRESS,
+                                       16, 1, code_base,
+                                       proglen, false);
+
+                bpf_flush_icache(code_base, code_base + (proglen/4));
+                /* Function descriptor nastiness: Address + TOC */
+                ((u64 *)image)[0] = (u64)code_base;
+                ((u64 *)image)[1] = local_paca->kernel_toc;
+                fp->bpf_func = (void *)image;
+        }
+out:
+        kfree(addrs);
+        return;
+}
+
+static void jit_free_defer(struct work_struct *arg)
+{
+        module_free(NULL, arg);
+}
+
+/* run from softirq, we must use a work_struct to call
+ * module_free() from process context
+ */
+void bpf_jit_free(struct sk_filter *fp)
+{
+        if (fp->bpf_func != sk_run_filter) {
+                struct work_struct *work = (struct work_struct *)fp->bpf_func;
+
+                INIT_WORK(work, jit_free_defer);
+                schedule_work(work);
+        }
+}
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index 47ea1be1481b..90f4496017e4 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -55,14 +55,6 @@ config PPC_MPC5200_BUGFIX
 
           It is safe to say 'Y' here
 
-config PPC_MPC5200_GPIO
-        bool "MPC5200 GPIO support"
-        depends on PPC_MPC52xx
-        select ARCH_REQUIRE_GPIOLIB
-        select GENERIC_GPIO
-        help
-          Enable gpiolib support for mpc5200 based boards
-
 config PPC_MPC5200_LPBFIFO
         tristate "MPC5200 LocalPlus bus FIFO driver"
         depends on PPC_MPC52xx
diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile
index 2bc8cd0c5cfc..4e62486791e9 100644
--- a/arch/powerpc/platforms/52xx/Makefile
+++ b/arch/powerpc/platforms/52xx/Makefile
@@ -14,5 +14,4 @@ ifeq ($(CONFIG_PPC_LITE5200),y)
         obj-$(CONFIG_PM)        += lite5200_sleep.o lite5200_pm.o
 endif
 
-obj-$(CONFIG_PPC_MPC5200_GPIO)  += mpc52xx_gpio.o
 obj-$(CONFIG_PPC_MPC5200_LPBFIFO)       += mpc52xx_lpbfifo.o
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
deleted file mode 100644
index 1757d1db4b51..000000000000
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * MPC52xx gpio driver
- *
- * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/of.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/of_gpio.h>
-#include <linux/io.h>
-#include <linux/of_platform.h>
-
-#include <asm/gpio.h>
-#include <asm/mpc52xx.h>
-#include <sysdev/fsl_soc.h>
-
-static DEFINE_SPINLOCK(gpio_lock);
-
-struct mpc52xx_gpiochip {
-        struct of_mm_gpio_chip mmchip;
-        unsigned int shadow_dvo;
-        unsigned int shadow_gpioe;
-        unsigned int shadow_ddr;
-};
-
-/*
- * GPIO LIB API implementation for wakeup GPIOs.
- *
- * There's a maximum of 8 wakeup GPIOs. Which of these are available
- * for use depends on your board setup.
- *
- * 0 -> GPIO_WKUP_7
- * 1 -> GPIO_WKUP_6
- * 2 -> PSC6_1
- * 3 -> PSC6_0
- * 4 -> ETH_17
- * 5 -> PSC3_9
- * 6 -> PSC2_4
- * 7 -> PSC1_4
- *
- */
-static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
-        unsigned int ret;
-
-        ret = (in_8(&regs->wkup_ival) >> (7 - gpio)) & 1;
-
-        pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
-
-        return ret;
-}
-
-static inline void
-__mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpiochip *chip = container_of(mm_gc,
-                        struct mpc52xx_gpiochip, mmchip);
-        struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
-
-        if (val)
-                chip->shadow_dvo |= 1 << (7 - gpio);
-        else
-                chip->shadow_dvo &= ~(1 << (7 - gpio));
-
-        out_8(&regs->wkup_dvo, chip->shadow_dvo);
-}
-
-static void
-mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        __mpc52xx_wkup_gpio_set(gc, gpio, val);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-
-        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
-}
-
-static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpiochip *chip = container_of(mm_gc,
-                        struct mpc52xx_gpiochip, mmchip);
-        struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* set the direction */
-        chip->shadow_ddr &= ~(1 << (7 - gpio));
-        out_8(&regs->wkup_ddr, chip->shadow_ddr);
-
-        /* and enable the pin */
-        chip->shadow_gpioe |= 1 << (7 - gpio);
-        out_8(&regs->wkup_gpioe, chip->shadow_gpioe);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-
-        return 0;
-}
-
-static int
-mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
-        struct mpc52xx_gpiochip *chip = container_of(mm_gc,
-                        struct mpc52xx_gpiochip, mmchip);
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        __mpc52xx_wkup_gpio_set(gc, gpio, val);
-
-        /* Then set direction */
-        chip->shadow_ddr |= 1 << (7 - gpio);
-        out_8(&regs->wkup_ddr, chip->shadow_ddr);
-
-        /* Finally enable the pin */
-        chip->shadow_gpioe |= 1 << (7 - gpio);
-        out_8(&regs->wkup_gpioe, chip->shadow_gpioe);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-
-        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
-
-        return 0;
-}
-
-static int __devinit mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev)
-{
-        struct mpc52xx_gpiochip *chip;
-        struct mpc52xx_gpio_wkup __iomem *regs;
-        struct gpio_chip *gc;
-        int ret;
-
-        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
-        if (!chip)
-                return -ENOMEM;
-
-        gc = &chip->mmchip.gc;
-
-        gc->ngpio            = 8;
-        gc->direction_input  = mpc52xx_wkup_gpio_dir_in;
-        gc->direction_output = mpc52xx_wkup_gpio_dir_out;
-        gc->get              = mpc52xx_wkup_gpio_get;
-        gc->set              = mpc52xx_wkup_gpio_set;
-
-        ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip);
-        if (ret)
-                return ret;
-
-        regs = chip->mmchip.regs;
-        chip->shadow_gpioe = in_8(&regs->wkup_gpioe);
-        chip->shadow_ddr = in_8(&regs->wkup_ddr);
-        chip->shadow_dvo = in_8(&regs->wkup_dvo);
-
-        return 0;
-}
-
-static int mpc52xx_gpiochip_remove(struct platform_device *ofdev)
-{
-        return -EBUSY;
-}
-
-static const struct of_device_id mpc52xx_wkup_gpiochip_match[] = {
-        {
-                .compatible = "fsl,mpc5200-gpio-wkup",
-        },
-        {}
-};
-
-static struct platform_driver mpc52xx_wkup_gpiochip_driver = {
-        .driver = {
-                .name = "gpio_wkup",
-                .owner = THIS_MODULE,
-                .of_match_table = mpc52xx_wkup_gpiochip_match,
-        },
-        .probe = mpc52xx_wkup_gpiochip_probe,
-        .remove = mpc52xx_gpiochip_remove,
-};
-
-/*
- * GPIO LIB API implementation for simple GPIOs
- *
- * There's a maximum of 32 simple GPIOs. Which of these are available
- * for use depends on your board setup.
- * The numbering reflects the bit numbering in the port registers:
- *
- *  0..1  > reserved
- *  2..3  > IRDA
- *  4..7  > ETHR
- *  8..11 > reserved
- * 12..15 > USB
- * 16..17 > reserved
- * 18..23 > PSC3
- * 24..27 > PSC2
- * 28..31 > PSC1
- */
-static int mpc52xx_simple_gpio_get(struct gpio_chip *gc, unsigned int gpio)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
-        unsigned int ret;
-
-        ret = (in_be32(&regs->simple_ival) >> (31 - gpio)) & 1;
-
-        return ret;
-}
-
-static inline void
-__mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpiochip *chip = container_of(mm_gc,
-                        struct mpc52xx_gpiochip, mmchip);
-        struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
-
-        if (val)
-                chip->shadow_dvo |= 1 << (31 - gpio);
-        else
-                chip->shadow_dvo &= ~(1 << (31 - gpio));
-        out_be32(&regs->simple_dvo, chip->shadow_dvo);
-}
-
-static void
-mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        __mpc52xx_simple_gpio_set(gc, gpio, val);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-
-        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
-}
-
-static int mpc52xx_simple_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpiochip *chip = container_of(mm_gc,
-                        struct mpc52xx_gpiochip, mmchip);
-        struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* set the direction */
-        chip->shadow_ddr &= ~(1 << (31 - gpio));
-        out_be32(&regs->simple_ddr, chip->shadow_ddr);
-
-        /* and enable the pin */
-        chip->shadow_gpioe |= 1 << (31 - gpio);
-        out_be32(&regs->simple_gpioe, chip->shadow_gpioe);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-
-        return 0;
-}
-
-static int
-mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct mpc52xx_gpiochip *chip = container_of(mm_gc,
-                        struct mpc52xx_gpiochip, mmchip);
-        struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* First set initial value */
-        __mpc52xx_simple_gpio_set(gc, gpio, val);
-
-        /* Then set direction */
-        chip->shadow_ddr |= 1 << (31 - gpio);
-        out_be32(&regs->simple_ddr, chip->shadow_ddr);
-
-        /* Finally enable the pin */
-        chip->shadow_gpioe |= 1 << (31 - gpio);
-        out_be32(&regs->simple_gpioe, chip->shadow_gpioe);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-
-        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
-
-        return 0;
-}
-
-static int __devinit mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev)
-{
-        struct mpc52xx_gpiochip *chip;
-        struct gpio_chip *gc;
-        struct mpc52xx_gpio __iomem *regs;
-        int ret;
-
-        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
-        if (!chip)
-                return -ENOMEM;
-
-        gc = &chip->mmchip.gc;
-
-        gc->ngpio            = 32;
-        gc->direction_input  = mpc52xx_simple_gpio_dir_in;
-        gc->direction_output = mpc52xx_simple_gpio_dir_out;
-        gc->get              = mpc52xx_simple_gpio_get;
-        gc->set              = mpc52xx_simple_gpio_set;
-
-        ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip);
-        if (ret)
-                return ret;
-
-        regs = chip->mmchip.regs;
-        chip->shadow_gpioe = in_be32(&regs->simple_gpioe);
-        chip->shadow_ddr = in_be32(&regs->simple_ddr);
-        chip->shadow_dvo = in_be32(&regs->simple_dvo);
-
-        return 0;
-}
-
-static const struct of_device_id mpc52xx_simple_gpiochip_match[] = {
-        {
-                .compatible = "fsl,mpc5200-gpio",
-        },
-        {}
-};
-
-static struct platform_driver mpc52xx_simple_gpiochip_driver = {
-        .driver = {
-                .name = "gpio",
-                .owner = THIS_MODULE,
-                .of_match_table = mpc52xx_simple_gpiochip_match,
-        },
-        .probe = mpc52xx_simple_gpiochip_probe,
-        .remove = mpc52xx_gpiochip_remove,
-};
-
-static int __init mpc52xx_gpio_init(void)
-{
-        if (platform_driver_register(&mpc52xx_wkup_gpiochip_driver))
-                printk(KERN_ERR "Unable to register wakeup GPIO driver\n");
-
-        if (platform_driver_register(&mpc52xx_simple_gpiochip_driver))
-                printk(KERN_ERR "Unable to register simple GPIO driver\n");
-
-        return 0;
-}
-
-
-/* Make sure we get initialised before anyone else tries to use us */
-subsys_initcall(mpc52xx_gpio_init);
-
-/* No exit call at the moment as we cannot unregister of gpio chips */
-
-MODULE_DESCRIPTION("Freescale MPC52xx gpio driver");
-MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de");
-MODULE_LICENSE("GPL v2");
-
diff --git a/arch/powerpc/platforms/amigaone/Kconfig b/arch/powerpc/platforms/amigaone/Kconfig
index 022476717718..128de25cc284 100644
--- a/arch/powerpc/platforms/amigaone/Kconfig
+++ b/arch/powerpc/platforms/amigaone/Kconfig
@@ -8,7 +8,7 @@ config AMIGAONE
         select NOT_COHERENT_CACHE
         select CHECK_CACHE_COHERENCY
         select DEFAULT_UIMAGE
-        select PCSPKR_PLATFORM
+        select HAVE_PCSPKR_PLATFORM
         help
         Select AmigaOne for the following machines:
         - AmigaOne SE/Teron CX (G3 only)
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index 3c7c3f82d842..fb59c46e9e9e 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -1850,9 +1850,16 @@ out:
         return ret;
 }
 
-static int spufs_mfc_fsync(struct file *file, int datasync)
+static int spufs_mfc_fsync(struct file *file, loff_t start, loff_t end, int datasync)
 {
-        return spufs_mfc_flush(file, NULL);
+        struct inode *inode = file->f_path.dentry->d_inode;
+        int err = filemap_write_and_wait_range(inode->i_mapping, start, end);
+        if (!err) {
+                mutex_lock(&inode->i_mutex);
+                err = spufs_mfc_flush(file, NULL);
+                mutex_unlock(&inode->i_mutex);
+        }
+        return err;
 }
 
 static int spufs_mfc_fasync(int fd, struct file *file, int on)
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 856e9c398068..e481f6b9a789 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -611,15 +611,14 @@ out:
 
 static struct file_system_type spufs_type;
 
-long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode,
-                                                        struct file *filp)
+long spufs_create(struct path *path, struct dentry *dentry,
+                unsigned int flags, mode_t mode, struct file *filp)
 {
-        struct dentry *dentry;
         int ret;
 
         ret = -EINVAL;
         /* check if we are on spufs */
-        if (nd->path.dentry->d_sb->s_type != &spufs_type)
+        if (path->dentry->d_sb->s_type != &spufs_type)
                 goto out;
 
         /* don't accept undefined flags */
@@ -627,33 +626,27 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode,
                 goto out;
 
         /* only threads can be underneath a gang */
-        if (nd->path.dentry != nd->path.dentry->d_sb->s_root) {
+        if (path->dentry != path->dentry->d_sb->s_root) {
                 if ((flags & SPU_CREATE_GANG) ||
-                    !SPUFS_I(nd->path.dentry->d_inode)->i_gang)
+                    !SPUFS_I(path->dentry->d_inode)->i_gang)
                         goto out;
         }
 
-        dentry = lookup_create(nd, 1);
-        ret = PTR_ERR(dentry);
-        if (IS_ERR(dentry))
-                goto out_dir;
-
         mode &= ~current_umask();
 
         if (flags & SPU_CREATE_GANG)
-                ret = spufs_create_gang(nd->path.dentry->d_inode,
-                                         dentry, nd->path.mnt, mode);
+                ret = spufs_create_gang(path->dentry->d_inode,
+                                         dentry, path->mnt, mode);
         else
-                ret = spufs_create_context(nd->path.dentry->d_inode,
-                                            dentry, nd->path.mnt, flags, mode,
+                ret = spufs_create_context(path->dentry->d_inode,
+                                            dentry, path->mnt, flags, mode,
                                             filp);
         if (ret >= 0)
-                fsnotify_mkdir(nd->path.dentry->d_inode, dentry);
+                fsnotify_mkdir(path->dentry->d_inode, dentry);
         return ret;
 
-out_dir:
-        mutex_unlock(&nd->path.dentry->d_inode->i_mutex);
 out:
+        mutex_unlock(&path->dentry->d_inode->i_mutex);
         return ret;
 }
 
diff --git a/arch/powerpc/platforms/cell/spufs/spufs.h b/arch/powerpc/platforms/cell/spufs/spufs.h
index c448bac65518..099245f230b2 100644
--- a/arch/powerpc/platforms/cell/spufs/spufs.h
+++ b/arch/powerpc/platforms/cell/spufs/spufs.h
@@ -248,7 +248,7 @@ extern const struct spufs_tree_descr spufs_dir_debug_contents[];
 /* system call implementation */
 extern struct spufs_calls spufs_calls;
 long spufs_run_spu(struct spu_context *ctx, u32 *npc, u32 *status);
-long spufs_create(struct nameidata *nd, unsigned int flags,
+long spufs_create(struct path *nd, struct dentry *dentry, unsigned int flags,
                         mode_t mode, struct file *filp);
 /* ELF coredump callbacks for writing SPU ELF notes */
 extern int spufs_coredump_extra_notes_size(void);
diff --git a/arch/powerpc/platforms/cell/spufs/syscalls.c b/arch/powerpc/platforms/cell/spufs/syscalls.c
index a3d2ce54ea2e..609e016e92d0 100644
--- a/arch/powerpc/platforms/cell/spufs/syscalls.c
+++ b/arch/powerpc/platforms/cell/spufs/syscalls.c
@@ -62,21 +62,17 @@ out:
 static long do_spu_create(const char __user *pathname, unsigned int flags,
                 mode_t mode, struct file *neighbor)
 {
-        char *tmp;
+        struct path path;
+        struct dentry *dentry;
         int ret;
 
-        tmp = getname(pathname);
-        ret = PTR_ERR(tmp);
-        if (!IS_ERR(tmp)) {
-                struct nameidata nd;
-
-                ret = kern_path_parent(tmp, &nd);
-                if (!ret) {
-                        nd.flags |= LOOKUP_OPEN | LOOKUP_CREATE;
-                        ret = spufs_create(&nd, flags, mode, neighbor);
-                        path_put(&nd.path);
-                }
-                putname(tmp);
+        dentry = user_path_create(AT_FDCWD, pathname, &path, 1);
+        ret = PTR_ERR(dentry);
+        if (!IS_ERR(dentry)) {
+                ret = spufs_create(&path, dentry, flags, mode, neighbor);
+                mutex_unlock(&path.dentry->d_inode->i_mutex);
+                dput(dentry);
+                path_put(&path);
         }
 
         return ret;
diff --git a/arch/powerpc/platforms/chrp/Kconfig b/arch/powerpc/platforms/chrp/Kconfig
index bc0b0efdc5fe..d3cdab582c5d 100644
--- a/arch/powerpc/platforms/chrp/Kconfig
+++ b/arch/powerpc/platforms/chrp/Kconfig
@@ -1,6 +1,7 @@
 config PPC_CHRP
         bool "Common Hardware Reference Platform (CHRP) based machines"
         depends on 6xx
+        select HAVE_PCSPKR_PLATFORM
         select MPIC
         select PPC_I8259
         select PPC_INDIRECT_PCI
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index f33e08d573ce..abe8d7e2ebeb 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/bootmem.h>
 #include <linux/irq.h>
+#include <linux/of_pci.h>
 
 #include <asm/sections.h>
 #include <asm/io.h>
@@ -235,7 +236,7 @@ static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
 
         if (offset >= 0x100)
                 return  PCIBIOS_BAD_REGISTER_NUMBER;
-        np = pci_busdev_to_OF_node(bus, devfn);
+        np = of_pci_find_child_device(bus->dev.of_node, devfn);
         if (np == NULL)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
diff --git a/arch/powerpc/platforms/prep/Kconfig b/arch/powerpc/platforms/prep/Kconfig
index bf8330ef2e76..f0536c7cda9f 100644
--- a/arch/powerpc/platforms/prep/Kconfig
+++ b/arch/powerpc/platforms/prep/Kconfig
@@ -1,6 +1,7 @@
 config PPC_PREP
         bool "PowerPC Reference Platform (PReP) based machines"
         depends on 6xx && BROKEN
+        select HAVE_PCSPKR_PLATFORM
         select MPIC
         select PPC_I8259
         select PPC_INDIRECT_PCI
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 71af4c5d6c05..05cf4769b88c 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -1,6 +1,7 @@
 config PPC_PSERIES
         depends on PPC64 && PPC_BOOK3S
         bool "IBM pSeries & new (POWER5-based) iSeries"
+        select HAVE_PCSPKR_PLATFORM
         select MPIC
         select PCI_MSI
         select PPC_XICS
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 33867ec4a234..9d6a8effeda2 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -12,6 +12,8 @@
 #include <linux/of.h>
 #include <linux/memblock.h>
 #include <linux/vmalloc.h>
+#include <linux/memory.h>
+
 #include <asm/firmware.h>
 #include <asm/machdep.h>
 #include <asm/pSeries_reconfig.h>
@@ -20,24 +22,25 @@
 static unsigned long get_memblock_size(void)
 {
         struct device_node *np;
-        unsigned int memblock_size = 0;
+        unsigned int memblock_size = MIN_MEMORY_BLOCK_SIZE;
+        struct resource r;
 
         np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
         if (np) {
-                const unsigned long *size;
+                const __be64 *size;
 
                 size = of_get_property(np, "ibm,lmb-size", NULL);
-                memblock_size = size ? *size : 0;
-
+                if (size)
+                        memblock_size = be64_to_cpup(size);
                 of_node_put(np);
-        } else {
+        } else  if (machine_is(pseries)) {
+                /* This fallback really only applies to pseries */
                 unsigned int memzero_size = 0;
-                const unsigned int *regs;
 
                 np = of_find_node_by_path("/memory@0");
                 if (np) {
-                        regs = of_get_property(np, "reg", NULL);
-                        memzero_size = regs ? regs[3] : 0;
+                        if (!of_address_to_resource(np, 0, &r))
+                                memzero_size = resource_size(&r);
                         of_node_put(np);
                 }
 
@@ -50,16 +53,21 @@ static unsigned long get_memblock_size(void)
                         sprintf(buf, "/memory@%x", memzero_size);
                         np = of_find_node_by_path(buf);
                         if (np) {
-                                regs = of_get_property(np, "reg", NULL);
-                                memblock_size = regs ? regs[3] : 0;
+                                if (!of_address_to_resource(np, 0, &r))
+                                        memblock_size = resource_size(&r);
                                 of_node_put(np);
                         }
                 }
         }
-
         return memblock_size;
 }
 
+/* WARNING: This is going to override the generic definition whenever
+ * pseries is built-in regardless of what platform is active at boot
+ * time. This is fine for now as this is the only "option" and it
+ * should work everywhere. If not, we'll have to turn this into a
+ * ppc_md. callback
+ */
 unsigned long memory_block_size_bytes(void)
 {
         return get_memblock_size();
diff --git a/arch/s390/crypto/sha256_s390.c b/arch/s390/crypto/sha256_s390.c
index 5ed8d64fc2ed..0317a3547cb9 100644
--- a/arch/s390/crypto/sha256_s390.c
+++ b/arch/s390/crypto/sha256_s390.c
@@ -1,15 +1,12 @@
 /*
  * Cryptographic API.
  *
- * s390 implementation of the SHA256 Secure Hash Algorithm.
+ * s390 implementation of the SHA256 and SHA224 Secure Hash Algorithm.
  *
  * s390 Version:
- *   Copyright IBM Corp. 2005,2007
+ *   Copyright IBM Corp. 2005,2011
  *   Author(s): Jan Glauber (jang@de.ibm.com)
  *
- * Derived from "crypto/sha256_generic.c"
- * and "arch/s390/crypto/sha1_s390.c"
- *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the Free
  * Software Foundation; either version 2 of the License, or (at your option)
@@ -65,7 +62,7 @@ static int sha256_import(struct shash_desc *desc, const void *in)
         return 0;
 }
 
-static struct shash_alg alg = {
+static struct shash_alg sha256_alg = {
         .digestsize     =       SHA256_DIGEST_SIZE,
         .init           =       sha256_init,
         .update         =       s390_sha_update,
@@ -84,22 +81,69 @@ static struct shash_alg alg = {
         }
 };
 
-static int sha256_s390_init(void)
+static int sha224_init(struct shash_desc *desc)
 {
+        struct s390_sha_ctx *sctx = shash_desc_ctx(desc);
+
+        sctx->state[0] = SHA224_H0;
+        sctx->state[1] = SHA224_H1;
+        sctx->state[2] = SHA224_H2;
+        sctx->state[3] = SHA224_H3;
+        sctx->state[4] = SHA224_H4;
+        sctx->state[5] = SHA224_H5;
+        sctx->state[6] = SHA224_H6;
+        sctx->state[7] = SHA224_H7;
+        sctx->count = 0;
+        sctx->func = KIMD_SHA_256;
+
+        return 0;
+}
+
+static struct shash_alg sha224_alg = {
+        .digestsize     =       SHA224_DIGEST_SIZE,
+        .init           =       sha224_init,
+        .update         =       s390_sha_update,
+        .final          =       s390_sha_final,
+        .export         =       sha256_export,
+        .import         =       sha256_import,
+        .descsize       =       sizeof(struct s390_sha_ctx),
+        .statesize      =       sizeof(struct sha256_state),
+        .base           =       {
+                .cra_name       =       "sha224",
+                .cra_driver_name=       "sha224-s390",
+                .cra_priority   =       CRYPT_S390_PRIORITY,
+                .cra_flags      =       CRYPTO_ALG_TYPE_SHASH,
+                .cra_blocksize  =       SHA224_BLOCK_SIZE,
+                .cra_module     =       THIS_MODULE,
+        }
+};
+
+static int __init sha256_s390_init(void)
+{
+        int ret;
+
         if (!crypt_s390_func_available(KIMD_SHA_256, CRYPT_S390_MSA))
                 return -EOPNOTSUPP;
-
-        return crypto_register_shash(&alg);
+        ret = crypto_register_shash(&sha256_alg);
+        if (ret < 0)
+                goto out;
+        ret = crypto_register_shash(&sha224_alg);
+        if (ret < 0)
+                crypto_unregister_shash(&sha256_alg);
+out:
+        return ret;
 }
 
 static void __exit sha256_s390_fini(void)
 {
-        crypto_unregister_shash(&alg);
+        crypto_unregister_shash(&sha224_alg);
+        crypto_unregister_shash(&sha256_alg);
 }
 
 module_init(sha256_s390_init);
 module_exit(sha256_s390_fini);
 
 MODULE_ALIAS("sha256");
+MODULE_ALIAS("sha224");
 MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm");
+MODULE_DESCRIPTION("SHA256 and SHA224 Secure Hash Algorithm");
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index a65d2e82f61d..a63d34c3611e 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -331,7 +331,7 @@ void __kprobes do_per_trap(struct pt_regs *regs)
 {
         if (notify_die(DIE_SSTEP, "sstep", regs, 0, 0, SIGTRAP) == NOTIFY_STOP)
                 return;
-        if (tracehook_consider_fatal_signal(current, SIGTRAP))
+        if (current->ptrace)
                 force_sig(SIGTRAP, current);
 }
 
@@ -425,7 +425,7 @@ static void __kprobes illegal_op(struct pt_regs *regs, long pgm_int_code,
                 if (get_user(*((__u16 *) opcode), (__u16 __user *) location))
                         return;
                 if (*((__u16 *) opcode) == S390_BREAKPOINT_U16) {
-                        if (tracehook_consider_fatal_signal(current, SIGTRAP))
+                        if (current->ptrace)
                                 force_sig(SIGTRAP, current);
                         else
                                 signal = SIGILL;
diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig
index f66a1bdbb61d..a21634173a66 100644
--- a/arch/s390/kvm/Kconfig
+++ b/arch/s390/kvm/Kconfig
@@ -37,6 +37,5 @@ config KVM
 # OK, it's a little counter-intuitive to do this, but it puts it neatly under
 # the virtualization menu.
 source drivers/vhost/Kconfig
-source drivers/virtio/Kconfig
 
 endif # VIRTUALIZATION
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index fe103e891e7a..095f782a5512 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -299,7 +299,7 @@ static inline int do_exception(struct pt_regs *regs, int access,
                 goto out;
 
         address = trans_exc_code & __FAIL_ADDR_MASK;
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
         flags = FAULT_FLAG_ALLOW_RETRY;
         if (access == VM_WRITE || (trans_exc_code & store_indication) == 0x400)
                 flags |= FAULT_FLAG_WRITE;
@@ -345,11 +345,11 @@ retry:
         if (flags & FAULT_FLAG_ALLOW_RETRY) {
                 if (fault & VM_FAULT_MAJOR) {
                         tsk->maj_flt++;
-                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
                                       regs, address);
                 } else {
                         tsk->min_flt++;
-                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
                                       regs, address);
                 }
                 if (fault & VM_FAULT_RETRY) {
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index bbdeb48bbf8e..748ff1920068 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -897,20 +897,4 @@ source "security/Kconfig"
 
 source "crypto/Kconfig"
 
-menuconfig VIRTUALIZATION
-        bool "Virtualization"
-        default n
-        ---help---
-          Say Y here to get to see options for using your Linux host to run other
-          operating systems inside virtual machines (guests).
-          This option alone does not add any kernel code.
-
-          If you say N, all options in this submenu will be skipped and disabled.
-
-if VIRTUALIZATION
-
-source drivers/virtio/Kconfig
-
-endif # VIRTUALIZATION
-
 source "lib/Kconfig"
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
index 748955df018d..fa4f724b295a 100644
--- a/arch/sh/kernel/cpu/sh4/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -180,6 +180,21 @@ static const int sh7750_cache_events
                         [ C(RESULT_MISS)   ] = -1,
                 },
         },
+
+        [ C(NODE) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
 };
 
 static int sh7750_event_map(int event)
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index 17e6bebfede0..84a2c396ceee 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -205,6 +205,21 @@ static const int sh4a_cache_events
                         [ C(RESULT_MISS)   ] = -1,
                 },
         },
+
+        [ C(NODE) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
 };
 
 static int sh4a_event_map(int event)
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
index 64c807c39208..bf280c812d2f 100644
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -256,7 +256,7 @@ out:
         return ret;
 }
 
-static struct dev_power_domain default_power_domain = {
+static struct dev_pm_domain default_pm_domain = {
         .ops = {
                 .runtime_suspend = default_platform_runtime_suspend,
                 .runtime_resume = default_platform_runtime_resume,
@@ -285,7 +285,7 @@ static int platform_bus_notify(struct notifier_block *nb,
                 hwblk_disable(hwblk_info, hwblk);
                 /* make sure driver re-inits itself once */
                 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
-                dev->pwr_domain = &default_power_domain;
+                dev->pm_domain = &default_pm_domain;
                 break;
         /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
         case BUS_NOTIFY_BOUND_DRIVER:
@@ -299,7 +299,7 @@ static int platform_bus_notify(struct notifier_block *nb,
                 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
                 break;
         case BUS_NOTIFY_DEL_DEVICE:
-                dev->pwr_domain = NULL;
+                dev->pm_domain = NULL;
                 break;
         }
         return 0;
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 3d7b209b2178..92b3c276339a 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -63,7 +63,7 @@ static inline int put_stack_long(struct task_struct *task, int offset,
         return 0;
 }
 
-void ptrace_triggered(struct perf_event *bp, int nmi,
+void ptrace_triggered(struct perf_event *bp,
                       struct perf_sample_data *data, struct pt_regs *regs)
 {
         struct perf_event_attr attr;
@@ -91,7 +91,8 @@ static int set_single_step(struct task_struct *tsk, unsigned long addr)
                 attr.bp_len = HW_BREAKPOINT_LEN_2;
                 attr.bp_type = HW_BREAKPOINT_R;
 
-                bp = register_user_hw_breakpoint(&attr, ptrace_triggered, tsk);
+                bp = register_user_hw_breakpoint(&attr, ptrace_triggered,
+                                                 NULL, tsk);
                 if (IS_ERR(bp))
                         return PTR_ERR(bp);
 
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index b51a17104b5f..d9006f8ffc14 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -393,7 +393,7 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
          */
         if (!expected) {
                 unaligned_fixups_notify(current, instruction, regs);
-                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0,
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
                               regs, address);
         }
 
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index 6713ca97e553..67110be83fd7 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -434,7 +434,7 @@ static int misaligned_load(struct pt_regs *regs,
                 return error;
         }
 
-        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 
         destreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
@@ -512,7 +512,7 @@ static int misaligned_store(struct pt_regs *regs,
                 return error;
         }
 
-        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 
         srcreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
@@ -588,7 +588,7 @@ static int misaligned_fpu_load(struct pt_regs *regs,
                 return error;
         }
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 
         destreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
@@ -665,7 +665,7 @@ static int misaligned_fpu_store(struct pt_regs *regs,
                 return error;
         }
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 
         srcreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
diff --git a/arch/sh/math-emu/math.c b/arch/sh/math-emu/math.c
index f76a5090d5d1..977195210653 100644
--- a/arch/sh/math-emu/math.c
+++ b/arch/sh/math-emu/math.c
@@ -620,7 +620,7 @@ int do_fpu_inst(unsigned short inst, struct pt_regs *regs)
         struct task_struct *tsk = current;
         struct sh_fpu_soft_struct *fpu = &(tsk->thread.xstate->softfpu);
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 
         if (!(task_thread_info(tsk)->status & TS_USEDFPU)) {
                 /* initialize once. */
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index d4c34d757f0d..7bebd044f2a1 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -160,7 +160,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
         if ((regs->sr & SR_IMASK) != SR_IMASK)
                 local_irq_enable();
 
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
 
         /*
          * If we're in an interrupt, have no user context or are running
@@ -210,11 +210,11 @@ good_area:
         }
         if (fault & VM_FAULT_MAJOR) {
                 tsk->maj_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
                                      regs, address);
         } else {
                 tsk->min_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
                                      regs, address);
         }
 
diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c
index 7f5810f5dfdc..e3430e093d43 100644
--- a/arch/sh/mm/tlbflush_64.c
+++ b/arch/sh/mm/tlbflush_64.c
@@ -116,7 +116,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
         /* Not an IO address, so reenable interrupts */
         local_irq_enable();
 
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
 
         /*
          * If we're in an interrupt or have no user
@@ -200,11 +200,11 @@ good_area:
 
         if (fault & VM_FAULT_MAJOR) {
                 tsk->maj_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
                                      regs, address);
         } else {
                 tsk->min_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
                                      regs, address);
         }
 
diff --git a/arch/sparc/include/asm/irqflags_32.h b/arch/sparc/include/asm/irqflags_32.h
index d4d0711de0f9..14848909e0de 100644
--- a/arch/sparc/include/asm/irqflags_32.h
+++ b/arch/sparc/include/asm/irqflags_32.h
@@ -18,7 +18,7 @@ extern void arch_local_irq_restore(unsigned long);
 extern unsigned long arch_local_irq_save(void);
 extern void arch_local_irq_enable(void);
 
-static inline unsigned long arch_local_save_flags(void)
+static inline notrace unsigned long arch_local_save_flags(void)
 {
         unsigned long flags;
 
@@ -26,17 +26,17 @@ static inline unsigned long arch_local_save_flags(void)
         return flags;
 }
 
-static inline void arch_local_irq_disable(void)
+static inline notrace void arch_local_irq_disable(void)
 {
         arch_local_irq_save();
 }
 
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
+static inline notrace bool arch_irqs_disabled_flags(unsigned long flags)
 {
         return (flags & PSR_PIL) != 0;
 }
 
-static inline bool arch_irqs_disabled(void)
+static inline notrace bool arch_irqs_disabled(void)
 {
         return arch_irqs_disabled_flags(arch_local_save_flags());
 }
diff --git a/arch/sparc/include/asm/irqflags_64.h b/arch/sparc/include/asm/irqflags_64.h
index aab969c82c2b..23cd27f6beb4 100644
--- a/arch/sparc/include/asm/irqflags_64.h
+++ b/arch/sparc/include/asm/irqflags_64.h
@@ -14,7 +14,7 @@
 
 #ifndef __ASSEMBLY__
 
-static inline unsigned long arch_local_save_flags(void)
+static inline notrace unsigned long arch_local_save_flags(void)
 {
         unsigned long flags;
 
@@ -26,7 +26,7 @@ static inline unsigned long arch_local_save_flags(void)
         return flags;
 }
 
-static inline void arch_local_irq_restore(unsigned long flags)
+static inline notrace void arch_local_irq_restore(unsigned long flags)
 {
         __asm__ __volatile__(
                 "wrpr   %0, %%pil"
@@ -36,7 +36,7 @@ static inline void arch_local_irq_restore(unsigned long flags)
         );
 }
 
-static inline void arch_local_irq_disable(void)
+static inline notrace void arch_local_irq_disable(void)
 {
         __asm__ __volatile__(
                 "wrpr   %0, %%pil"
@@ -46,7 +46,7 @@ static inline void arch_local_irq_disable(void)
         );
 }
 
-static inline void arch_local_irq_enable(void)
+static inline notrace void arch_local_irq_enable(void)
 {
         __asm__ __volatile__(
                 "wrpr   0, %%pil"
@@ -56,17 +56,17 @@ static inline void arch_local_irq_enable(void)
         );
 }
 
-static inline int arch_irqs_disabled_flags(unsigned long flags)
+static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
 {
         return (flags > 0);
 }
 
-static inline int arch_irqs_disabled(void)
+static inline notrace int arch_irqs_disabled(void)
 {
         return arch_irqs_disabled_flags(arch_local_save_flags());
 }
 
-static inline unsigned long arch_local_irq_save(void)
+static inline notrace unsigned long arch_local_irq_save(void)
 {
         unsigned long flags, tmp;
 
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
index 862e3ce92b15..02939abd356c 100644
--- a/arch/sparc/include/asm/pci_32.h
+++ b/arch/sparc/include/asm/pci_32.h
@@ -42,9 +42,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-struct device_node;
-extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
-
 #endif /* __KERNEL__ */
 
 #ifndef CONFIG_LEON_PCI
diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h
index 948b686ec089..2614d96141c9 100644
--- a/arch/sparc/include/asm/pci_64.h
+++ b/arch/sparc/include/asm/pci_64.h
@@ -91,9 +91,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return PCI_IRQ_NONE;
 }
 
-struct device_node;
-extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
-
 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
 extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
                                  const struct resource *rsrc,
diff --git a/arch/sparc/include/asm/ptrace.h b/arch/sparc/include/asm/ptrace.h
index c7ad3fe2b252..b928b31424b1 100644
--- a/arch/sparc/include/asm/ptrace.h
+++ b/arch/sparc/include/asm/ptrace.h
@@ -205,6 +205,7 @@ do {	current_thread_info()->syscall_noerror = 1; \
 } while (0)
 #define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
 #define instruction_pointer(regs) ((regs)->tpc)
+#define instruction_pointer_set(regs, val) ((regs)->tpc = (val))
 #define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP])
 #define regs_return_value(regs) ((regs)->u_regs[UREG_I0])
 #ifdef CONFIG_SMP
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 9fe08a1ea6c6..f445e98463e6 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -293,7 +293,7 @@ maybe_smp4m_msg:
         WRITE_PAUSE
         wr      %l4, PSR_ET, %psr
         WRITE_PAUSE
-        sll     %o3, 28, %o2            ! shift for simpler checks below
+        srl     %o3, 28, %o2            ! shift for simpler checks below
 maybe_smp4m_msg_check_single:
         andcc   %o2, 0x1, %g0
         beq,a   maybe_smp4m_msg_check_mask
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 713dc91020a6..80a87e2a3e7c 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -284,7 +284,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
         dev->sysdata = node;
         dev->dev.parent = bus->bridge;
         dev->dev.bus = &pci_bus_type;
-        dev->dev.of_node = node;
+        dev->dev.of_node = of_node_get(node);
         dev->devfn = devfn;
         dev->multifunction = 0;         /* maybe a lie? */
         set_pcie_port_type(dev);
@@ -1021,12 +1021,6 @@ void arch_teardown_msi_irq(unsigned int irq)
 }
 #endif /* !(CONFIG_PCI_MSI) */
 
-struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
-{
-        return pdev->dev.of_node;
-}
-EXPORT_SYMBOL(pci_device_to_OF_node);
-
 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
 {
         struct pci_dev *ali_isa_bridge;
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index 948601a066ff..a19f04195478 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -885,14 +885,6 @@ int pcibios_assign_resource(struct pci_dev *pdev, int resource)
         return -ENXIO;
 }
 
-struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
-{
-        struct pcidev_cookie *pc = pdev->sysdata;
-
-        return pc->prom_node;
-}
-EXPORT_SYMBOL(pci_device_to_OF_node);
-
 /*
  * This probably belongs here rather than ioport.c because
  * we do not want this crud linked into SBus kernels.
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 2cb0e1c001e2..62a034318b18 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -246,6 +246,20 @@ static const cache_map_t ultra3_cache_map = {
                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
         },
 },
+[C(NODE)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
 };
 
 static const struct sparc_pmu ultra3_pmu = {
@@ -361,6 +375,20 @@ static const cache_map_t niagara1_cache_map = {
                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
         },
 },
+[C(NODE)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
 };
 
 static const struct sparc_pmu niagara1_pmu = {
@@ -473,6 +501,20 @@ static const cache_map_t niagara2_cache_map = {
                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
         },
 },
+[C(NODE)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
 };
 
 static const struct sparc_pmu niagara2_pmu = {
@@ -1277,7 +1319,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
                 if (!sparc_perf_event_set_period(event, hwc, idx))
                         continue;
 
-                if (perf_event_overflow(event, 1, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         sparc_pmu_stop(event, 0);
         }
 
diff --git a/arch/sparc/kernel/unaligned_32.c b/arch/sparc/kernel/unaligned_32.c
index 4491f4cb2695..7efbb2f9e77f 100644
--- a/arch/sparc/kernel/unaligned_32.c
+++ b/arch/sparc/kernel/unaligned_32.c
@@ -247,7 +247,7 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
                 unsigned long addr = compute_effective_address(regs, insn);
                 int err;
 
-                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, addr);
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
                 switch (dir) {
                 case load:
                         err = do_int_load(fetch_reg_addr(((insn>>25)&0x1f),
@@ -338,7 +338,7 @@ asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn)
                 }
 
                 addr = compute_effective_address(regs, insn);
-                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, addr);
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
                 switch(dir) {
                 case load:
                         err = do_int_load(fetch_reg_addr(((insn>>25)&0x1f),
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c
index b2b019ea8caa..35cff1673aa4 100644
--- a/arch/sparc/kernel/unaligned_64.c
+++ b/arch/sparc/kernel/unaligned_64.c
@@ -317,7 +317,7 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
 
                 addr = compute_effective_address(regs, insn,
                                                  ((insn >> 25) & 0x1f));
-                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, addr);
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
                 switch (asi) {
                 case ASI_NL:
                 case ASI_AIUPL:
@@ -384,7 +384,7 @@ int handle_popc(u32 insn, struct pt_regs *regs)
         int ret, i, rd = ((insn >> 25) & 0x1f);
         int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
                                 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
         if (insn & 0x2000) {
                 maybe_flush_windows(0, 0, rd, from_kernel);
                 value = sign_extend_imm13(insn);
@@ -431,7 +431,7 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs)
         int asi = decode_asi(insn, regs);
         int flag = (freg < 32) ? FPRS_DL : FPRS_DU;
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 
         save_and_clear_fpu();
         current_thread_info()->xfsr[0] &= ~0x1c000;
@@ -554,7 +554,7 @@ void handle_ld_nf(u32 insn, struct pt_regs *regs)
         int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
         unsigned long *reg;
                                 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 
         maybe_flush_windows(0, 0, rd, from_kernel);
         reg = fetch_reg_addr(rd, regs);
@@ -586,7 +586,7 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
 
         if (tstate & TSTATE_PRIV)
                 die_if_kernel("lddfmna from kernel", regs);
-        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, sfar);
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
@@ -647,7 +647,7 @@ void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
 
         if (tstate & TSTATE_PRIV)
                 die_if_kernel("stdfmna from kernel", regs);
-        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, sfar);
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
diff --git a/arch/sparc/kernel/visemul.c b/arch/sparc/kernel/visemul.c
index 36357717d691..32b626c9d815 100644
--- a/arch/sparc/kernel/visemul.c
+++ b/arch/sparc/kernel/visemul.c
@@ -802,7 +802,7 @@ int vis_emul(struct pt_regs *regs, unsigned int insn)
 
         BUG_ON(regs->tstate & TSTATE_PRIV);
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
diff --git a/arch/sparc/math-emu/math_32.c b/arch/sparc/math-emu/math_32.c
index a3fccde894ec..aa4d55b0bdf0 100644
--- a/arch/sparc/math-emu/math_32.c
+++ b/arch/sparc/math-emu/math_32.c
@@ -164,7 +164,7 @@ int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
         int retcode = 0;                               /* assume all succeed */
         unsigned long insn;
 
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
 
 #ifdef DEBUG_MATHEMU
         printk("In do_mathemu()... pc is %08lx\n", regs->pc);
diff --git a/arch/sparc/math-emu/math_64.c b/arch/sparc/math-emu/math_64.c
index 56d2c44747b8..e575bd2fe381 100644
--- a/arch/sparc/math-emu/math_64.c
+++ b/arch/sparc/math-emu/math_64.c
@@ -184,7 +184,7 @@ int do_mathemu(struct pt_regs *regs, struct fpustate *f)
 
         if (tstate & TSTATE_PRIV)
                 die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
         if (test_thread_flag(TIF_32BIT))
                 pc = (u32)pc;
         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index 7543ddbdadb2..aa1c1b1ce5cc 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -251,7 +251,7 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
         if (in_atomic() || !mm)
                 goto no_context;
 
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
 
         down_read(&mm->mmap_sem);
 
@@ -301,12 +301,10 @@ good_area:
         }
         if (fault & VM_FAULT_MAJOR) {
                 current->maj_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
-                              regs, address);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address);
         } else {
                 current->min_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
-                              regs, address);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address);
         }
         up_read(&mm->mmap_sem);
         return;
diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c
index f92ce56a8b22..504c0622f729 100644
--- a/arch/sparc/mm/fault_64.c
+++ b/arch/sparc/mm/fault_64.c
@@ -325,7 +325,7 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
         if (in_atomic() || !mm)
                 goto intr_or_no_mm;
 
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
 
         if (!down_read_trylock(&mm->mmap_sem)) {
                 if ((regs->tstate & TSTATE_PRIV) &&
@@ -433,12 +433,10 @@ good_area:
         }
         if (fault & VM_FAULT_MAJOR) {
                 current->maj_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
-                              regs, address);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address);
         } else {
                 current->min_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
-                              regs, address);
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address);
         }
         up_read(&mm->mmap_sem);
 
diff --git a/arch/sparc/mm/leon_mm.c b/arch/sparc/mm/leon_mm.c
index c0e01297e64e..e485a6804998 100644
--- a/arch/sparc/mm/leon_mm.c
+++ b/arch/sparc/mm/leon_mm.c
@@ -226,7 +226,7 @@ void leon3_getCacheRegs(struct leon3_cacheregs *regs)
  * Leon2 and Leon3 differ in their way of telling cache information
  *
  */
-int leon_flush_needed(void)
+int __init leon_flush_needed(void)
 {
         int flush_needed = -1;
         unsigned int ssize, sets;
diff --git a/arch/tile/kvm/Kconfig b/arch/tile/kvm/Kconfig
index b88f9c047781..669fcdba31ea 100644
--- a/arch/tile/kvm/Kconfig
+++ b/arch/tile/kvm/Kconfig
@@ -33,6 +33,5 @@ config KVM
           If unsure, say N.
 
 source drivers/vhost/Kconfig
-source drivers/virtio/Kconfig
 
 endif # VIRTUALIZATION
diff --git a/arch/um/sys-i386/Makefile b/arch/um/sys-i386/Makefile
index b1da91c1b200..87b659dadf3f 100644
--- a/arch/um/sys-i386/Makefile
+++ b/arch/um/sys-i386/Makefile
@@ -8,7 +8,8 @@ obj-y = bug.o bugs.o checksum.o delay.o fault.o ksyms.o ldt.o ptrace.o \
 
 obj-$(CONFIG_BINFMT_ELF) += elfcore.o
 
-subarch-obj-y = lib/semaphore_32.o lib/string_32.o
+subarch-obj-y = lib/string_32.o
+subarch-obj-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += lib/rwsem.o
 subarch-obj-$(CONFIG_HIGHMEM) += mm/highmem_32.o
 subarch-obj-$(CONFIG_MODULES) += kernel/module.o
 
diff --git a/arch/um/sys-x86_64/Makefile b/arch/um/sys-x86_64/Makefile
index c1ea9eb04466..61fc99a42e10 100644
--- a/arch/um/sys-x86_64/Makefile
+++ b/arch/um/sys-x86_64/Makefile
@@ -9,7 +9,7 @@ obj-y = bug.o bugs.o delay.o fault.o ldt.o mem.o ptrace.o ptrace_user.o \
         sysrq.o ksyms.o tls.o
 
 subarch-obj-y = lib/csum-partial_64.o lib/memcpy_64.o lib/thunk_64.o \
-                lib/rwsem_64.o
+                lib/rwsem.o
 subarch-obj-$(CONFIG_MODULES) += kernel/module.o
 
 ldt-y = ../sys-i386/ldt.o
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1f03e221a01e..a67e014e4e44 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -20,6 +20,7 @@ config X86
         select HAVE_UNSTABLE_SCHED_CLOCK
         select HAVE_IDE
         select HAVE_OPROFILE
+        select HAVE_PCSPKR_PLATFORM
         select HAVE_PERF_EVENTS
         select HAVE_IRQ_WORK
         select HAVE_IOREMAP_PROT
@@ -70,6 +71,7 @@ config X86
         select IRQ_FORCED_THREADING
         select USE_GENERIC_SMP_HELPERS if SMP
         select HAVE_BPF_JIT if (X86_64 && NET)
+        select CLKEVT_I8253
 
 config INSTRUCTION_DECODER
         def_bool (KPROBES || PERF_EVENTS)
@@ -93,6 +95,10 @@ config CLOCKSOURCE_WATCHDOG
 config GENERIC_CLOCKEVENTS
         def_bool y
 
+config ARCH_CLOCKSOURCE_DATA
+        def_bool y
+        depends on X86_64
+
 config GENERIC_CLOCKEVENTS_BROADCAST
         def_bool y
         depends on X86_64 || (X86_32 && X86_LOCAL_APIC)
@@ -384,12 +390,21 @@ config X86_INTEL_CE
           This option compiles in support for the CE4100 SOC for settop
           boxes and media devices.
 
+config X86_INTEL_MID
+        bool "Intel MID platform support"
+        depends on X86_32
+        depends on X86_EXTENDED_PLATFORM
+        ---help---
+          Select to build a kernel capable of supporting Intel MID platform
+          systems which do not have the PCI legacy interfaces (Moorestown,
+          Medfield). If you are building for a PC class system say N here.
+
+if X86_INTEL_MID
+
 config X86_MRST
        bool "Moorestown MID platform"
         depends on PCI
         depends on PCI_GOANY
-        depends on X86_32
-        depends on X86_EXTENDED_PLATFORM
         depends on X86_IO_APIC
         select APB_TIMER
         select I2C
@@ -404,6 +419,8 @@ config X86_MRST
           nor standard legacy replacement devices/features. e.g. Moorestown does
           not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
 
+endif
+
 config X86_RDC321X
         bool "RDC R-321x SoC"
         depends on X86_32
@@ -629,6 +646,7 @@ config HPET_EMULATE_RTC
 config APB_TIMER
        def_bool y if MRST
        prompt "Langwell APB Timer Support" if X86_MRST
+       select DW_APB_TIMER
        help
          APB timer is the replacement for 8254, HPET on X86 MID platforms.
          The APBT provides a stable time base on SMP
@@ -692,33 +710,6 @@ config CALGARY_IOMMU_ENABLED_BY_DEFAULT
           Calgary anyway, pass 'iommu=calgary' on the kernel command line.
           If unsure, say Y.
 
-config AMD_IOMMU
-        bool "AMD IOMMU support"
-        select SWIOTLB
-        select PCI_MSI
-        select PCI_IOV
-        depends on X86_64 && PCI && ACPI
-        ---help---
-          With this option you can enable support for AMD IOMMU hardware in
-          your system. An IOMMU is a hardware component which provides
-          remapping of DMA memory accesses from devices. With an AMD IOMMU you
-          can isolate the the DMA memory of different devices and protect the
-          system from misbehaving device drivers or hardware.
-
-          You can find out if your system has an AMD IOMMU if you look into
-          your BIOS for an option to enable it or if you have an IVRS ACPI
-          table.
-
-config AMD_IOMMU_STATS
-        bool "Export AMD IOMMU statistics to debugfs"
-        depends on AMD_IOMMU
-        select DEBUG_FS
-        ---help---
-          This option enables code in the AMD IOMMU driver to collect various
-          statistics about whats happening in the driver and exports that
-          information to userspace via debugfs.
-          If unsure, say N.
-
 # need this always selected by IOMMU for the VIA workaround
 config SWIOTLB
         def_bool y if X86_64
@@ -732,9 +723,6 @@ config SWIOTLB
 config IOMMU_HELPER
         def_bool (CALGARY_IOMMU || GART_IOMMU || SWIOTLB || AMD_IOMMU)
 
-config IOMMU_API
-        def_bool (AMD_IOMMU || DMAR)
-
 config MAXSMP
         bool "Enable Maximum number of SMP Processors and NUMA Nodes"
         depends on X86_64 && SMP && DEBUG_KERNEL && EXPERIMENTAL
@@ -1182,7 +1170,7 @@ comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI"
 config AMD_NUMA
         def_bool y
         prompt "Old style AMD Opteron NUMA detection"
-        depends on NUMA && PCI
+        depends on X86_64 && NUMA && PCI
         ---help---
           Enable AMD NUMA node topology detection.  You should say Y here if
           you have a multi processor AMD system. This uses an old method to
@@ -1954,55 +1942,6 @@ config PCI_CNB20LE_QUIRK
 
           You should say N unless you know you need this.
 
-config DMAR
-        bool "Support for DMA Remapping Devices (EXPERIMENTAL)"
-        depends on PCI_MSI && ACPI && EXPERIMENTAL
-        help
-          DMA remapping (DMAR) devices support enables independent address
-          translations for Direct Memory Access (DMA) from devices.
-          These DMA remapping devices are reported via ACPI tables
-          and include PCI device scope covered by these DMA
-          remapping devices.
-
-config DMAR_DEFAULT_ON
-        def_bool y
-        prompt "Enable DMA Remapping Devices by default"
-        depends on DMAR
-        help
-          Selecting this option will enable a DMAR device at boot time if
-          one is found. If this option is not selected, DMAR support can
-          be enabled by passing intel_iommu=on to the kernel. It is
-          recommended you say N here while the DMAR code remains
-          experimental.
-
-config DMAR_BROKEN_GFX_WA
-        bool "Workaround broken graphics drivers (going away soon)"
-        depends on DMAR && BROKEN
-        ---help---
-          Current Graphics drivers tend to use physical address
-          for DMA and avoid using DMA APIs. Setting this config
-          option permits the IOMMU driver to set a unity map for
-          all the OS-visible memory. Hence the driver can continue
-          to use physical addresses for DMA, at least until this
-          option is removed in the 2.6.32 kernel.
-
-config DMAR_FLOPPY_WA
-        def_bool y
-        depends on DMAR
-        ---help---
-          Floppy disk drivers are known to bypass DMA API calls
-          thereby failing to work when IOMMU is enabled. This
-          workaround will setup a 1:1 mapping for the first
-          16MiB to make floppy (an ISA device) work.
-
-config INTR_REMAP
-        bool "Support for Interrupt Remapping (EXPERIMENTAL)"
-        depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI && EXPERIMENTAL
-        ---help---
-          Supports Interrupt remapping for IO-APIC and MSI devices.
-          To use x2apic mode in the CPU's which support x2APIC enhancements or
-          to support platforms with CPU's having > 8 bit APIC ID, say Y.
-
 source "drivers/pci/pcie/Kconfig"
 
 source "drivers/pci/Kconfig"
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 6a7cfdf8ff69..e3ca7e0d858c 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -312,6 +312,9 @@ config X86_CMPXCHG
 config CMPXCHG_LOCAL
         def_bool X86_64 || (X86_32 && !M386)
 
+config CMPXCHG_DOUBLE
+        def_bool y
+
 config X86_L1_CACHE_SHIFT
         int
         default "7" if MPENTIUM4 || MPSC
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index f7cb086b4add..95365a82b6a0 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -9,12 +9,6 @@
 # Changed by many, many contributors over the years.
 #
 
-# ROOT_DEV specifies the default root-device when making the image.
-# This can be either FLOPPY, CURRENT, /dev/xxxx or empty, in which case
-# the default of FLOPPY is used by 'build'.
-
-ROOT_DEV        := CURRENT
-
 # If you want to preset the SVGA mode, uncomment the next line and
 # set SVGA_MODE to whatever number you want.
 # Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode.
@@ -75,8 +69,7 @@ GCOV_PROFILE := n
 $(obj)/bzImage: asflags-y  := $(SVGA_MODE)
 
 quiet_cmd_image = BUILD   $@
-cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin \
-        $(ROOT_DEV) > $@
+cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin > $@
 
 $(obj)/bzImage: $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/tools/build FORCE
         $(call if_changed,image)
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index ee3a4ea923ac..fdc60a0b3c20 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -130,7 +130,7 @@ static void die(const char * str, ...)
 
 static void usage(void)
 {
-        die("Usage: build setup system [rootdev] [> image]");
+        die("Usage: build setup system [> image]");
 }
 
 int main(int argc, char ** argv)
@@ -138,39 +138,14 @@ int main(int argc, char ** argv)
         unsigned int i, sz, setup_sectors;
         int c;
         u32 sys_size;
-        u8 major_root, minor_root;
         struct stat sb;
         FILE *file;
         int fd;
         void *kernel;
         u32 crc = 0xffffffffUL;
 
-        if ((argc < 3) || (argc > 4))
+        if (argc != 3)
                 usage();
-        if (argc > 3) {
-                if (!strcmp(argv[3], "CURRENT")) {
-                        if (stat("/", &sb)) {
-                                perror("/");
-                                die("Couldn't stat /");
-                        }
-                        major_root = major(sb.st_dev);
-                        minor_root = minor(sb.st_dev);
-                } else if (strcmp(argv[3], "FLOPPY")) {
-                        if (stat(argv[3], &sb)) {
-                                perror(argv[3]);
-                                die("Couldn't stat root device.");
-                        }
-                        major_root = major(sb.st_rdev);
-                        minor_root = minor(sb.st_rdev);
-                } else {
-                        major_root = 0;
-                        minor_root = 0;
-                }
-        } else {
-                major_root = DEFAULT_MAJOR_ROOT;
-                minor_root = DEFAULT_MINOR_ROOT;
-        }
-        fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
 
         /* Copy the setup code */
         file = fopen(argv[1], "r");
@@ -193,8 +168,8 @@ int main(int argc, char ** argv)
         memset(buf+c, 0, i-c);
 
         /* Set the default root device */
-        buf[508] = minor_root;
-        buf[509] = major_root;
+        buf[508] = DEFAULT_MINOR_ROOT;
+        buf[509] = DEFAULT_MAJOR_ROOT;
 
         fprintf(stderr, "Setup is %d bytes (padded to %d bytes).\n", c, i);
 
diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c
index 7a6e68e4f748..976aa64d9a20 100644
--- a/arch/x86/crypto/ghash-clmulni-intel_glue.c
+++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c
@@ -245,7 +245,7 @@ static int ghash_async_setkey(struct crypto_ahash *tfm, const u8 *key,
         crypto_ahash_set_flags(tfm, crypto_ahash_get_flags(child)
                                & CRYPTO_TFM_RES_MASK);
 
-        return 0;
+        return err;
 }
 
 static int ghash_async_init_tfm(struct crypto_tfm *tfm)
diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c
index 588a7aa937e1..65577698cab2 100644
--- a/arch/x86/ia32/ia32_signal.c
+++ b/arch/x86/ia32/ia32_signal.c
@@ -127,15 +127,17 @@ int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
 
 asmlinkage long sys32_sigsuspend(int history0, int history1, old_sigset_t mask)
 {
-        mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
+        sigset_t blocked;
+
         current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+
+        mask &= _BLOCKABLE;
+        siginitset(&blocked, mask);
+        set_current_blocked(&blocked);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
+
         set_restore_sigmask();
         return -ERESTARTNOHAND;
 }
@@ -279,10 +281,7 @@ asmlinkage long sys32_sigreturn(struct pt_regs *regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         if (ia32_restore_sigcontext(regs, &frame->sc, &ax))
                 goto badframe;
@@ -308,10 +307,7 @@ asmlinkage long sys32_rt_sigreturn(struct pt_regs *regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         if (ia32_restore_sigcontext(regs, &frame->uc.uc_mcontext, &ax))
                 goto badframe;
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index c1870dddd322..a0e866d233ee 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -143,7 +143,7 @@ ENTRY(ia32_sysenter_target)
         CFI_REL_OFFSET rip,0
         pushq_cfi %rax
         cld
-        SAVE_ARGS 0,0,1
+        SAVE_ARGS 0,1,0
         /* no need to do an access_ok check here because rbp has been
            32bit zero extended */ 
 1:      movl    (%rbp),%ebp
@@ -173,7 +173,7 @@ sysexit_from_sys_call:
         andl  $~0x200,EFLAGS-R11(%rsp) 
         movl    RIP-R11(%rsp),%edx              /* User %eip */
         CFI_REGISTER rip,rdx
-        RESTORE_ARGS 1,24,1,1,1,1
+        RESTORE_ARGS 0,24,0,0,0,0
         xorq    %r8,%r8
         xorq    %r9,%r9
         xorq    %r10,%r10
@@ -289,7 +289,7 @@ ENTRY(ia32_cstar_target)
          * disabled irqs and here we enable it straight after entry:
          */
         ENABLE_INTERRUPTS(CLBR_NONE)
-        SAVE_ARGS 8,1,1
+        SAVE_ARGS 8,0,0
         movl    %eax,%eax       /* zero extension */
         movq    %rax,ORIG_RAX-ARGOFFSET(%rsp)
         movq    %rcx,RIP-ARGOFFSET(%rsp)
@@ -328,7 +328,7 @@ cstar_dispatch:
         jnz sysretl_audit
 sysretl_from_sys_call:
         andl $~TS_COMPAT,TI_status(%r10)
-        RESTORE_ARGS 1,-ARG_SKIP,1,1,1
+        RESTORE_ARGS 0,-ARG_SKIP,0,0,0
         movl RIP-ARGOFFSET(%rsp),%ecx
         CFI_REGISTER rip,rcx
         movl EFLAGS-ARGOFFSET(%rsp),%r11d       
@@ -419,7 +419,7 @@ ENTRY(ia32_syscall)
         cld
         /* note the registers are not zero extended to the sf.
            this could be a problem. */
-        SAVE_ARGS 0,0,1
+        SAVE_ARGS 0,1,0
         GET_THREAD_INFO(%r10)
         orl   $TS_COMPAT,TI_status(%r10)
         testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)
diff --git a/arch/x86/include/asm/alternative-asm.h b/arch/x86/include/asm/alternative-asm.h
index 94d420b360d1..4554cc6fb96a 100644
--- a/arch/x86/include/asm/alternative-asm.h
+++ b/arch/x86/include/asm/alternative-asm.h
@@ -17,8 +17,8 @@
 
 .macro altinstruction_entry orig alt feature orig_len alt_len
         .align 8
-        .quad \orig
-        .quad \alt
+        .long \orig - .
+        .long \alt - .
         .word \feature
         .byte \orig_len
         .byte \alt_len
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index bf535f947e8c..23fb6d79f209 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -43,8 +43,8 @@
 #endif
 
 struct alt_instr {
-        u8 *instr;              /* original instruction */
-        u8 *replacement;
+        s32 instr_offset;       /* original instruction */
+        s32 repl_offset;        /* offset to replacement instruction */
         u16 cpuid;              /* cpuid bit set for replacement */
         u8  instrlen;           /* length of original instruction */
         u8  replacementlen;     /* length of new instruction, <= instrlen */
@@ -84,8 +84,8 @@ static inline int alternatives_text_reserved(void *start, void *end)
       "661:\n\t" oldinstr "\n662:\n"                                    \
       ".section .altinstructions,\"a\"\n"                               \
       _ASM_ALIGN "\n"                                                   \
-      _ASM_PTR "661b\n"                         /* label           */   \
-      _ASM_PTR "663f\n"                         /* new instruction */   \
+      "  .long 661b - .\n"                      /* label           */   \
+      "  .long 663f - .\n"                      /* new instruction */   \
       "  .word " __stringify(feature) "\n"      /* feature bit     */   \
       "  .byte 662b-661b\n"                     /* sourcelen       */   \
       "  .byte 664f-663f\n"                     /* replacementlen  */   \
diff --git a/arch/x86/include/asm/amd_iommu.h b/arch/x86/include/asm/amd_iommu.h
deleted file mode 100644
index a6863a2dec1f..000000000000
--- a/arch/x86/include/asm/amd_iommu.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *         Leo Duran <leo.duran@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ASM_X86_AMD_IOMMU_H
-#define _ASM_X86_AMD_IOMMU_H
-
-#include <linux/irqreturn.h>
-
-#ifdef CONFIG_AMD_IOMMU
-
-extern int amd_iommu_detect(void);
-
-#else
-
-static inline int amd_iommu_detect(void) { return -ENODEV; }
-
-#endif
-
-#endif /* _ASM_X86_AMD_IOMMU_H */
diff --git a/arch/x86/include/asm/amd_iommu_proto.h b/arch/x86/include/asm/amd_iommu_proto.h
deleted file mode 100644
index 55d95eb789b3..000000000000
--- a/arch/x86/include/asm/amd_iommu_proto.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ASM_X86_AMD_IOMMU_PROTO_H
-#define _ASM_X86_AMD_IOMMU_PROTO_H
-
-#include <asm/amd_iommu_types.h>
-
-extern int amd_iommu_init_dma_ops(void);
-extern int amd_iommu_init_passthrough(void);
-extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
-extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
-extern void amd_iommu_apply_erratum_63(u16 devid);
-extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
-extern int amd_iommu_init_devices(void);
-extern void amd_iommu_uninit_devices(void);
-extern void amd_iommu_init_notifier(void);
-extern void amd_iommu_init_api(void);
-#ifndef CONFIG_AMD_IOMMU_STATS
-
-static inline void amd_iommu_stats_init(void) { }
-
-#endif /* !CONFIG_AMD_IOMMU_STATS */
-
-static inline bool is_rd890_iommu(struct pci_dev *pdev)
-{
-        return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
-               (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
-}
-
-static inline bool iommu_feature(struct amd_iommu *iommu, u64 f)
-{
-        if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))
-                return false;
-
-        return !!(iommu->features & f);
-}
-
-#endif /* _ASM_X86_AMD_IOMMU_PROTO_H  */
diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h
deleted file mode 100644
index 4c9982995414..000000000000
--- a/arch/x86/include/asm/amd_iommu_types.h
+++ /dev/null
@@ -1,580 +0,0 @@
-/*
- * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *         Leo Duran <leo.duran@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ASM_X86_AMD_IOMMU_TYPES_H
-#define _ASM_X86_AMD_IOMMU_TYPES_H
-
-#include <linux/types.h>
-#include <linux/mutex.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-
-/*
- * Maximum number of IOMMUs supported
- */
-#define MAX_IOMMUS      32
-
-/*
- * some size calculation constants
- */
-#define DEV_TABLE_ENTRY_SIZE            32
-#define ALIAS_TABLE_ENTRY_SIZE          2
-#define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
-
-/* Length of the MMIO region for the AMD IOMMU */
-#define MMIO_REGION_LENGTH       0x4000
-
-/* Capability offsets used by the driver */
-#define MMIO_CAP_HDR_OFFSET     0x00
-#define MMIO_RANGE_OFFSET       0x0c
-#define MMIO_MISC_OFFSET        0x10
-
-/* Masks, shifts and macros to parse the device range capability */
-#define MMIO_RANGE_LD_MASK      0xff000000
-#define MMIO_RANGE_FD_MASK      0x00ff0000
-#define MMIO_RANGE_BUS_MASK     0x0000ff00
-#define MMIO_RANGE_LD_SHIFT     24
-#define MMIO_RANGE_FD_SHIFT     16
-#define MMIO_RANGE_BUS_SHIFT    8
-#define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
-#define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
-#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
-#define MMIO_MSI_NUM(x) ((x) & 0x1f)
-
-/* Flag masks for the AMD IOMMU exclusion range */
-#define MMIO_EXCL_ENABLE_MASK 0x01ULL
-#define MMIO_EXCL_ALLOW_MASK  0x02ULL
-
-/* Used offsets into the MMIO space */
-#define MMIO_DEV_TABLE_OFFSET   0x0000
-#define MMIO_CMD_BUF_OFFSET     0x0008
-#define MMIO_EVT_BUF_OFFSET     0x0010
-#define MMIO_CONTROL_OFFSET     0x0018
-#define MMIO_EXCL_BASE_OFFSET   0x0020
-#define MMIO_EXCL_LIMIT_OFFSET  0x0028
-#define MMIO_EXT_FEATURES       0x0030
-#define MMIO_CMD_HEAD_OFFSET    0x2000
-#define MMIO_CMD_TAIL_OFFSET    0x2008
-#define MMIO_EVT_HEAD_OFFSET    0x2010
-#define MMIO_EVT_TAIL_OFFSET    0x2018
-#define MMIO_STATUS_OFFSET      0x2020
-
-
-/* Extended Feature Bits */
-#define FEATURE_PREFETCH        (1ULL<<0)
-#define FEATURE_PPR             (1ULL<<1)
-#define FEATURE_X2APIC          (1ULL<<2)
-#define FEATURE_NX              (1ULL<<3)
-#define FEATURE_GT              (1ULL<<4)
-#define FEATURE_IA              (1ULL<<6)
-#define FEATURE_GA              (1ULL<<7)
-#define FEATURE_HE              (1ULL<<8)
-#define FEATURE_PC              (1ULL<<9)
-
-/* MMIO status bits */
-#define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
-
-/* event logging constants */
-#define EVENT_ENTRY_SIZE        0x10
-#define EVENT_TYPE_SHIFT        28
-#define EVENT_TYPE_MASK         0xf
-#define EVENT_TYPE_ILL_DEV      0x1
-#define EVENT_TYPE_IO_FAULT     0x2
-#define EVENT_TYPE_DEV_TAB_ERR  0x3
-#define EVENT_TYPE_PAGE_TAB_ERR 0x4
-#define EVENT_TYPE_ILL_CMD      0x5
-#define EVENT_TYPE_CMD_HARD_ERR 0x6
-#define EVENT_TYPE_IOTLB_INV_TO 0x7
-#define EVENT_TYPE_INV_DEV_REQ  0x8
-#define EVENT_DEVID_MASK        0xffff
-#define EVENT_DEVID_SHIFT       0
-#define EVENT_DOMID_MASK        0xffff
-#define EVENT_DOMID_SHIFT       0
-#define EVENT_FLAGS_MASK        0xfff
-#define EVENT_FLAGS_SHIFT       0x10
-
-/* feature control bits */
-#define CONTROL_IOMMU_EN        0x00ULL
-#define CONTROL_HT_TUN_EN       0x01ULL
-#define CONTROL_EVT_LOG_EN      0x02ULL
-#define CONTROL_EVT_INT_EN      0x03ULL
-#define CONTROL_COMWAIT_EN      0x04ULL
-#define CONTROL_PASSPW_EN       0x08ULL
-#define CONTROL_RESPASSPW_EN    0x09ULL
-#define CONTROL_COHERENT_EN     0x0aULL
-#define CONTROL_ISOC_EN         0x0bULL
-#define CONTROL_CMDBUF_EN       0x0cULL
-#define CONTROL_PPFLOG_EN       0x0dULL
-#define CONTROL_PPFINT_EN       0x0eULL
-
-/* command specific defines */
-#define CMD_COMPL_WAIT          0x01
-#define CMD_INV_DEV_ENTRY       0x02
-#define CMD_INV_IOMMU_PAGES     0x03
-#define CMD_INV_IOTLB_PAGES     0x04
-#define CMD_INV_ALL             0x08
-
-#define CMD_COMPL_WAIT_STORE_MASK       0x01
-#define CMD_COMPL_WAIT_INT_MASK         0x02
-#define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
-#define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
-
-#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
-
-/* macros and definitions for device table entries */
-#define DEV_ENTRY_VALID         0x00
-#define DEV_ENTRY_TRANSLATION   0x01
-#define DEV_ENTRY_IR            0x3d
-#define DEV_ENTRY_IW            0x3e
-#define DEV_ENTRY_NO_PAGE_FAULT 0x62
-#define DEV_ENTRY_EX            0x67
-#define DEV_ENTRY_SYSMGT1       0x68
-#define DEV_ENTRY_SYSMGT2       0x69
-#define DEV_ENTRY_INIT_PASS     0xb8
-#define DEV_ENTRY_EINT_PASS     0xb9
-#define DEV_ENTRY_NMI_PASS      0xba
-#define DEV_ENTRY_LINT0_PASS    0xbe
-#define DEV_ENTRY_LINT1_PASS    0xbf
-#define DEV_ENTRY_MODE_MASK     0x07
-#define DEV_ENTRY_MODE_SHIFT    0x09
-
-/* constants to configure the command buffer */
-#define CMD_BUFFER_SIZE    8192
-#define CMD_BUFFER_UNINITIALIZED 1
-#define CMD_BUFFER_ENTRIES 512
-#define MMIO_CMD_SIZE_SHIFT 56
-#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
-
-/* constants for event buffer handling */
-#define EVT_BUFFER_SIZE         8192 /* 512 entries */
-#define EVT_LEN_MASK            (0x9ULL << 56)
-
-#define PAGE_MODE_NONE    0x00
-#define PAGE_MODE_1_LEVEL 0x01
-#define PAGE_MODE_2_LEVEL 0x02
-#define PAGE_MODE_3_LEVEL 0x03
-#define PAGE_MODE_4_LEVEL 0x04
-#define PAGE_MODE_5_LEVEL 0x05
-#define PAGE_MODE_6_LEVEL 0x06
-
-#define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
-#define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
-                                  ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
-                                   (0xffffffffffffffffULL))
-#define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
-#define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
-#define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
-                                 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
-#define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
-
-#define PM_MAP_4k               0
-#define PM_ADDR_MASK            0x000ffffffffff000ULL
-#define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
-                                (~((1ULL << (12 + ((lvl) * 9))) - 1)))
-#define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
-
-/*
- * Returns the page table level to use for a given page size
- * Pagesize is expected to be a power-of-two
- */
-#define PAGE_SIZE_LEVEL(pagesize) \
-                ((__ffs(pagesize) - 12) / 9)
-/*
- * Returns the number of ptes to use for a given page size
- * Pagesize is expected to be a power-of-two
- */
-#define PAGE_SIZE_PTE_COUNT(pagesize) \
-                (1ULL << ((__ffs(pagesize) - 12) % 9))
-
-/*
- * Aligns a given io-virtual address to a given page size
- * Pagesize is expected to be a power-of-two
- */
-#define PAGE_SIZE_ALIGN(address, pagesize) \
-                ((address) & ~((pagesize) - 1))
-/*
- * Creates an IOMMU PTE for an address an a given pagesize
- * The PTE has no permission bits set
- * Pagesize is expected to be a power-of-two larger than 4096
- */
-#define PAGE_SIZE_PTE(address, pagesize)                \
-                (((address) | ((pagesize) - 1)) &       \
-                 (~(pagesize >> 1)) & PM_ADDR_MASK)
-
-/*
- * Takes a PTE value with mode=0x07 and returns the page size it maps
- */
-#define PTE_PAGE_SIZE(pte) \
-        (1ULL << (1 + ffz(((pte) | 0xfffULL))))
-
-#define IOMMU_PTE_P  (1ULL << 0)
-#define IOMMU_PTE_TV (1ULL << 1)
-#define IOMMU_PTE_U  (1ULL << 59)
-#define IOMMU_PTE_FC (1ULL << 60)
-#define IOMMU_PTE_IR (1ULL << 61)
-#define IOMMU_PTE_IW (1ULL << 62)
-
-#define DTE_FLAG_IOTLB  0x01
-
-#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
-#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
-#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
-#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
-
-#define IOMMU_PROT_MASK 0x03
-#define IOMMU_PROT_IR 0x01
-#define IOMMU_PROT_IW 0x02
-
-/* IOMMU capabilities */
-#define IOMMU_CAP_IOTLB   24
-#define IOMMU_CAP_NPCACHE 26
-#define IOMMU_CAP_EFR     27
-
-#define MAX_DOMAIN_ID 65536
-
-/* FIXME: move this macro to <linux/pci.h> */
-#define PCI_BUS(x) (((x) >> 8) & 0xff)
-
-/* Protection domain flags */
-#define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
-#define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
-                                              domain for an IOMMU */
-#define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
-                                              translation */
-
-extern bool amd_iommu_dump;
-#define DUMP_printk(format, arg...)                                     \
-        do {                                                            \
-                if (amd_iommu_dump)                                             \
-                        printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
-        } while(0);
-
-/* global flag if IOMMUs cache non-present entries */
-extern bool amd_iommu_np_cache;
-/* Only true if all IOMMUs support device IOTLBs */
-extern bool amd_iommu_iotlb_sup;
-
-/*
- * Make iterating over all IOMMUs easier
- */
-#define for_each_iommu(iommu) \
-        list_for_each_entry((iommu), &amd_iommu_list, list)
-#define for_each_iommu_safe(iommu, next) \
-        list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
-
-#define APERTURE_RANGE_SHIFT    27      /* 128 MB */
-#define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
-#define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
-#define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
-#define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
-#define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
-
-/*
- * This structure contains generic data for  IOMMU protection domains
- * independent of their use.
- */
-struct protection_domain {
-        struct list_head list;  /* for list of all protection domains */
-        struct list_head dev_list; /* List of all devices in this domain */
-        spinlock_t lock;        /* mostly used to lock the page table*/
-        struct mutex api_lock;  /* protect page tables in the iommu-api path */
-        u16 id;                 /* the domain id written to the device table */
-        int mode;               /* paging mode (0-6 levels) */
-        u64 *pt_root;           /* page table root pointer */
-        unsigned long flags;    /* flags to find out type of domain */
-        bool updated;           /* complete domain flush required */
-        unsigned dev_cnt;       /* devices assigned to this domain */
-        unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
-        void *priv;             /* private data */
-
-};
-
-/*
- * This struct contains device specific data for the IOMMU
- */
-struct iommu_dev_data {
-        struct list_head list;            /* For domain->dev_list */
-        struct device *dev;               /* Device this data belong to */
-        struct device *alias;             /* The Alias Device */
-        struct protection_domain *domain; /* Domain the device is bound to */
-        atomic_t bind;                    /* Domain attach reverent count */
-};
-
-/*
- * For dynamic growth the aperture size is split into ranges of 128MB of
- * DMA address space each. This struct represents one such range.
- */
-struct aperture_range {
-
-        /* address allocation bitmap */
-        unsigned long *bitmap;
-
-        /*
-         * Array of PTE pages for the aperture. In this array we save all the
-         * leaf pages of the domain page table used for the aperture. This way
-         * we don't need to walk the page table to find a specific PTE. We can
-         * just calculate its address in constant time.
-         */
-        u64 *pte_pages[64];
-
-        unsigned long offset;
-};
-
-/*
- * Data container for a dma_ops specific protection domain
- */
-struct dma_ops_domain {
-        struct list_head list;
-
-        /* generic protection domain information */
-        struct protection_domain domain;
-
-        /* size of the aperture for the mappings */
-        unsigned long aperture_size;
-
-        /* address we start to search for free addresses */
-        unsigned long next_address;
-
-        /* address space relevant data */
-        struct aperture_range *aperture[APERTURE_MAX_RANGES];
-
-        /* This will be set to true when TLB needs to be flushed */
-        bool need_flush;
-
-        /*
-         * if this is a preallocated domain, keep the device for which it was
-         * preallocated in this variable
-         */
-        u16 target_dev;
-};
-
-/*
- * Structure where we save information about one hardware AMD IOMMU in the
- * system.
- */
-struct amd_iommu {
-        struct list_head list;
-
-        /* Index within the IOMMU array */
-        int index;
-
-        /* locks the accesses to the hardware */
-        spinlock_t lock;
-
-        /* Pointer to PCI device of this IOMMU */
-        struct pci_dev *dev;
-
-        /* physical address of MMIO space */
-        u64 mmio_phys;
-        /* virtual address of MMIO space */
-        u8 *mmio_base;
-
-        /* capabilities of that IOMMU read from ACPI */
-        u32 cap;
-
-        /* flags read from acpi table */
-        u8 acpi_flags;
-
-        /* Extended features */
-        u64 features;
-
-        /*
-         * Capability pointer. There could be more than one IOMMU per PCI
-         * device function if there are more than one AMD IOMMU capability
-         * pointers.
-         */
-        u16 cap_ptr;
-
-        /* pci domain of this IOMMU */
-        u16 pci_seg;
-
-        /* first device this IOMMU handles. read from PCI */
-        u16 first_device;
-        /* last device this IOMMU handles. read from PCI */
-        u16 last_device;
-
-        /* start of exclusion range of that IOMMU */
-        u64 exclusion_start;
-        /* length of exclusion range of that IOMMU */
-        u64 exclusion_length;
-
-        /* command buffer virtual address */
-        u8 *cmd_buf;
-        /* size of command buffer */
-        u32 cmd_buf_size;
-
-        /* size of event buffer */
-        u32 evt_buf_size;
-        /* event buffer virtual address */
-        u8 *evt_buf;
-        /* MSI number for event interrupt */
-        u16 evt_msi_num;
-
-        /* true if interrupts for this IOMMU are already enabled */
-        bool int_enabled;
-
-        /* if one, we need to send a completion wait command */
-        bool need_sync;
-
-        /* default dma_ops domain for that IOMMU */
-        struct dma_ops_domain *default_dom;
-
-        /*
-         * We can't rely on the BIOS to restore all values on reinit, so we
-         * need to stash them
-         */
-
-        /* The iommu BAR */
-        u32 stored_addr_lo;
-        u32 stored_addr_hi;
-
-        /*
-         * Each iommu has 6 l1s, each of which is documented as having 0x12
-         * registers
-         */
-        u32 stored_l1[6][0x12];
-
-        /* The l2 indirect registers */
-        u32 stored_l2[0x83];
-};
-
-/*
- * List with all IOMMUs in the system. This list is not locked because it is
- * only written and read at driver initialization or suspend time
- */
-extern struct list_head amd_iommu_list;
-
-/*
- * Array with pointers to each IOMMU struct
- * The indices are referenced in the protection domains
- */
-extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
-
-/* Number of IOMMUs present in the system */
-extern int amd_iommus_present;
-
-/*
- * Declarations for the global list of all protection domains
- */
-extern spinlock_t amd_iommu_pd_lock;
-extern struct list_head amd_iommu_pd_list;
-
-/*
- * Structure defining one entry in the device table
- */
-struct dev_table_entry {
-        u32 data[8];
-};
-
-/*
- * One entry for unity mappings parsed out of the ACPI table.
- */
-struct unity_map_entry {
-        struct list_head list;
-
-        /* starting device id this entry is used for (including) */
-        u16 devid_start;
-        /* end device id this entry is used for (including) */
-        u16 devid_end;
-
-        /* start address to unity map (including) */
-        u64 address_start;
-        /* end address to unity map (including) */
-        u64 address_end;
-
-        /* required protection */
-        int prot;
-};
-
-/*
- * List of all unity mappings. It is not locked because as runtime it is only
- * read. It is created at ACPI table parsing time.
- */
-extern struct list_head amd_iommu_unity_map;
-
-/*
- * Data structures for device handling
- */
-
-/*
- * Device table used by hardware. Read and write accesses by software are
- * locked with the amd_iommu_pd_table lock.
- */
-extern struct dev_table_entry *amd_iommu_dev_table;
-
-/*
- * Alias table to find requestor ids to device ids. Not locked because only
- * read on runtime.
- */
-extern u16 *amd_iommu_alias_table;
-
-/*
- * Reverse lookup table to find the IOMMU which translates a specific device.
- */
-extern struct amd_iommu **amd_iommu_rlookup_table;
-
-/* size of the dma_ops aperture as power of 2 */
-extern unsigned amd_iommu_aperture_order;
-
-/* largest PCI device id we expect translation requests for */
-extern u16 amd_iommu_last_bdf;
-
-/* allocation bitmap for domain ids */
-extern unsigned long *amd_iommu_pd_alloc_bitmap;
-
-/*
- * If true, the addresses will be flushed on unmap time, not when
- * they are reused
- */
-extern bool amd_iommu_unmap_flush;
-
-/* takes bus and device/function and returns the device id
- * FIXME: should that be in generic PCI code? */
-static inline u16 calc_devid(u8 bus, u8 devfn)
-{
-        return (((u16)bus) << 8) | devfn;
-}
-
-#ifdef CONFIG_AMD_IOMMU_STATS
-
-struct __iommu_counter {
-        char *name;
-        struct dentry *dent;
-        u64 value;
-};
-
-#define DECLARE_STATS_COUNTER(nm) \
-        static struct __iommu_counter nm = {    \
-                .name = #nm,                    \
-        }
-
-#define INC_STATS_COUNTER(name)         name.value += 1
-#define ADD_STATS_COUNTER(name, x)      name.value += (x)
-#define SUB_STATS_COUNTER(name, x)      name.value -= (x)
-
-#else /* CONFIG_AMD_IOMMU_STATS */
-
-#define DECLARE_STATS_COUNTER(name)
-#define INC_STATS_COUNTER(name)
-#define ADD_STATS_COUNTER(name, x)
-#define SUB_STATS_COUNTER(name, x)
-
-#endif /* CONFIG_AMD_IOMMU_STATS */
-
-#endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index af60d8a2e288..0acbac299e49 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -18,24 +18,6 @@
 
 #ifdef CONFIG_APB_TIMER
 
-/* Langwell DW APB timer registers */
-#define APBTMR_N_LOAD_COUNT    0x00
-#define APBTMR_N_CURRENT_VALUE 0x04
-#define APBTMR_N_CONTROL       0x08
-#define APBTMR_N_EOI           0x0c
-#define APBTMR_N_INT_STATUS    0x10
-
-#define APBTMRS_INT_STATUS     0xa0
-#define APBTMRS_EOI            0xa4
-#define APBTMRS_RAW_INT_STATUS 0xa8
-#define APBTMRS_COMP_VERSION   0xac
-#define APBTMRS_REG_SIZE       0x14
-
-/* register bits */
-#define APBTMR_CONTROL_ENABLE  (1<<0)
-#define APBTMR_CONTROL_MODE_PERIODIC   (1<<1) /*1: periodic 0:free running */
-#define APBTMR_CONTROL_INT     (1<<2)
-
 /* default memory mapped register base */
 #define LNW_SCU_ADDR           0xFF100000
 #define LNW_EXT_TIMER_OFFSET   0x1B800
@@ -43,14 +25,13 @@
 #define LNW_EXT_TIMER_PGOFFSET         0x800
 
 /* APBT clock speed range from PCLK to fabric base, 25-100MHz */
-#define APBT_MAX_FREQ          50
-#define APBT_MIN_FREQ          1
+#define APBT_MAX_FREQ          50000000
+#define APBT_MIN_FREQ          1000000
 #define APBT_MMAP_SIZE         1024
 
 #define APBT_DEV_USED  1
 
 extern void apbt_time_init(void);
-extern struct clock_event_device *global_clock_event;
 extern unsigned long apbt_quick_calibrate(void);
 extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
 extern void apbt_setup_secondary_clock(void);
diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h
index b3ed1e1460ff..9412d6558c88 100644
--- a/arch/x86/include/asm/asm.h
+++ b/arch/x86/include/asm/asm.h
@@ -3,9 +3,11 @@
 
 #ifdef __ASSEMBLY__
 # define __ASM_FORM(x)  x
+# define __ASM_FORM_COMMA(x) x,
 # define __ASM_EX_SEC   .section __ex_table, "a"
 #else
 # define __ASM_FORM(x)  " " #x " "
+# define __ASM_FORM_COMMA(x) " " #x ","
 # define __ASM_EX_SEC   " .section __ex_table,\"a\"\n"
 #endif
 
@@ -15,7 +17,8 @@
 # define __ASM_SEL(a,b) __ASM_FORM(b)
 #endif
 
-#define __ASM_SIZE(inst)        __ASM_SEL(inst##l, inst##q)
+#define __ASM_SIZE(inst, ...)   __ASM_SEL(inst##l##__VA_ARGS__, \
+                                          inst##q##__VA_ARGS__)
 #define __ASM_REG(reg)          __ASM_SEL(e##reg, r##reg)
 
 #define _ASM_PTR        __ASM_SEL(.long, .quad)
diff --git a/arch/x86/include/asm/calling.h b/arch/x86/include/asm/calling.h
index 30af5a832163..a9e3a740f697 100644
--- a/arch/x86/include/asm/calling.h
+++ b/arch/x86/include/asm/calling.h
@@ -46,6 +46,7 @@ For 32-bit we have the following conventions - kernel is built with
 
 */
 
+#include "dwarf2.h"
 
 /*
  * 64-bit system call stack frame layout defines and helpers, for
@@ -84,72 +85,57 @@ For 32-bit we have the following conventions - kernel is built with
 #define ARGOFFSET       R11
 #define SWFRAME         ORIG_RAX
 
-        .macro SAVE_ARGS addskip=0, norcx=0, nor891011=0
+        .macro SAVE_ARGS addskip=0, save_rcx=1, save_r891011=1
         subq  $9*8+\addskip, %rsp
         CFI_ADJUST_CFA_OFFSET   9*8+\addskip
-        movq  %rdi, 8*8(%rsp)
-        CFI_REL_OFFSET  rdi, 8*8
-        movq  %rsi, 7*8(%rsp)
-        CFI_REL_OFFSET  rsi, 7*8
-        movq  %rdx, 6*8(%rsp)
-        CFI_REL_OFFSET  rdx, 6*8
-        .if \norcx
-        .else
-        movq  %rcx, 5*8(%rsp)
-        CFI_REL_OFFSET  rcx, 5*8
+        movq_cfi rdi, 8*8
+        movq_cfi rsi, 7*8
+        movq_cfi rdx, 6*8
+
+        .if \save_rcx
+        movq_cfi rcx, 5*8
         .endif
-        movq  %rax, 4*8(%rsp)
-        CFI_REL_OFFSET  rax, 4*8
-        .if \nor891011
-        .else
-        movq  %r8, 3*8(%rsp)
-        CFI_REL_OFFSET  r8,  3*8
-        movq  %r9, 2*8(%rsp)
-        CFI_REL_OFFSET  r9,  2*8
-        movq  %r10, 1*8(%rsp)
-        CFI_REL_OFFSET  r10, 1*8
-        movq  %r11, (%rsp)
-        CFI_REL_OFFSET  r11, 0*8
+
+        movq_cfi rax, 4*8
+
+        .if \save_r891011
+        movq_cfi r8,  3*8
+        movq_cfi r9,  2*8
+        movq_cfi r10, 1*8
+        movq_cfi r11, 0*8
         .endif
+
         .endm
 
 #define ARG_SKIP        (9*8)
 
-        .macro RESTORE_ARGS skiprax=0, addskip=0, skiprcx=0, skipr11=0, \
-                            skipr8910=0, skiprdx=0
-        .if \skipr11
-        .else
-        movq (%rsp), %r11
-        CFI_RESTORE r11
+        .macro RESTORE_ARGS rstor_rax=1, addskip=0, rstor_rcx=1, rstor_r11=1, \
+                            rstor_r8910=1, rstor_rdx=1
+        .if \rstor_r11
+        movq_cfi_restore 0*8, r11
         .endif
-        .if \skipr8910
-        .else
-        movq 1*8(%rsp), %r10
-        CFI_RESTORE r10
-        movq 2*8(%rsp), %r9
-        CFI_RESTORE r9
-        movq 3*8(%rsp), %r8
-        CFI_RESTORE r8
+
+        .if \rstor_r8910
+        movq_cfi_restore 1*8, r10
+        movq_cfi_restore 2*8, r9
+        movq_cfi_restore 3*8, r8
         .endif
-        .if \skiprax
-        .else
-        movq 4*8(%rsp), %rax
-        CFI_RESTORE rax
+
+        .if \rstor_rax
+        movq_cfi_restore 4*8, rax
         .endif
-        .if \skiprcx
-        .else
-        movq 5*8(%rsp), %rcx
-        CFI_RESTORE rcx
+
+        .if \rstor_rcx
+        movq_cfi_restore 5*8, rcx
         .endif
-        .if \skiprdx
-        .else
-        movq 6*8(%rsp), %rdx
-        CFI_RESTORE rdx
+
+        .if \rstor_rdx
+        movq_cfi_restore 6*8, rdx
         .endif
-        movq 7*8(%rsp), %rsi
-        CFI_RESTORE rsi
-        movq 8*8(%rsp), %rdi
-        CFI_RESTORE rdi
+
+        movq_cfi_restore 7*8, rsi
+        movq_cfi_restore 8*8, rdi
+
         .if ARG_SKIP+\addskip > 0
         addq $ARG_SKIP+\addskip, %rsp
         CFI_ADJUST_CFA_OFFSET   -(ARG_SKIP+\addskip)
@@ -176,33 +162,21 @@ For 32-bit we have the following conventions - kernel is built with
         .macro SAVE_REST
         subq $REST_SKIP, %rsp
         CFI_ADJUST_CFA_OFFSET   REST_SKIP
-        movq %rbx, 5*8(%rsp)
-        CFI_REL_OFFSET  rbx, 5*8
-        movq %rbp, 4*8(%rsp)
-        CFI_REL_OFFSET  rbp, 4*8
-        movq %r12, 3*8(%rsp)
-        CFI_REL_OFFSET  r12, 3*8
-        movq %r13, 2*8(%rsp)
-        CFI_REL_OFFSET  r13, 2*8
-        movq %r14, 1*8(%rsp)
-        CFI_REL_OFFSET  r14, 1*8
-        movq %r15, (%rsp)
-        CFI_REL_OFFSET  r15, 0*8
+        movq_cfi rbx, 5*8
+        movq_cfi rbp, 4*8
+        movq_cfi r12, 3*8
+        movq_cfi r13, 2*8
+        movq_cfi r14, 1*8
+        movq_cfi r15, 0*8
         .endm
 
         .macro RESTORE_REST
-        movq (%rsp),     %r15
-        CFI_RESTORE r15
-        movq 1*8(%rsp),  %r14
-        CFI_RESTORE r14
-        movq 2*8(%rsp),  %r13
-        CFI_RESTORE r13
-        movq 3*8(%rsp),  %r12
-        CFI_RESTORE r12
-        movq 4*8(%rsp),  %rbp
-        CFI_RESTORE rbp
-        movq 5*8(%rsp),  %rbx
-        CFI_RESTORE rbx
+        movq_cfi_restore 0*8, r15
+        movq_cfi_restore 1*8, r14
+        movq_cfi_restore 2*8, r13
+        movq_cfi_restore 3*8, r12
+        movq_cfi_restore 4*8, rbp
+        movq_cfi_restore 5*8, rbx
         addq $REST_SKIP, %rsp
         CFI_ADJUST_CFA_OFFSET   -(REST_SKIP)
         .endm
@@ -214,7 +188,7 @@ For 32-bit we have the following conventions - kernel is built with
 
         .macro RESTORE_ALL addskip=0
         RESTORE_REST
-        RESTORE_ARGS 0, \addskip
+        RESTORE_ARGS 1, \addskip
         .endm
 
         .macro icebp
diff --git a/arch/x86/include/asm/clocksource.h b/arch/x86/include/asm/clocksource.h
new file mode 100644
index 000000000000..0bdbbb3b9ce7
--- /dev/null
+++ b/arch/x86/include/asm/clocksource.h
@@ -0,0 +1,18 @@
+/* x86-specific clocksource additions */
+
+#ifndef _ASM_X86_CLOCKSOURCE_H
+#define _ASM_X86_CLOCKSOURCE_H
+
+#ifdef CONFIG_X86_64
+
+#define VCLOCK_NONE 0  /* No vDSO clock available.      */
+#define VCLOCK_TSC  1  /* vDSO should use vread_tsc.    */
+#define VCLOCK_HPET 2  /* vDSO should use vread_hpet.   */
+
+struct arch_clocksource_data {
+        int vclock_mode;
+};
+
+#endif /* CONFIG_X86_64 */
+
+#endif /* _ASM_X86_CLOCKSOURCE_H */
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index 284a6e8f7ce1..3deb7250624c 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -280,4 +280,52 @@ static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
 
 #endif
 
+#define cmpxchg8b(ptr, o1, o2, n1, n2)                          \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __dummy;                                 \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile(LOCK_PREFIX "cmpxchg8b %2; setz %1"        \
+                       : "=d"(__dummy), "=a" (__ret), "+m" (*ptr)\
+                       : "a" (__old1), "d"(__old2),             \
+                         "b" (__new1), "c" (__new2)             \
+                       : "memory");                             \
+        __ret; })
+
+
+#define cmpxchg8b_local(ptr, o1, o2, n1, n2)                    \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __dummy;                                 \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile("cmpxchg8b %2; setz %1"                    \
+                       : "=d"(__dummy), "=a"(__ret), "+m" (*ptr)\
+                       : "a" (__old), "d"(__old2),              \
+                         "b" (__new1), "c" (__new2),            \
+                       : "memory");                             \
+        __ret; })
+
+
+#define cmpxchg_double(ptr, o1, o2, n1, n2)                             \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 4);                              \
+        VM_BUG_ON((unsigned long)(ptr) % 8);                            \
+        cmpxchg8b((ptr), (o1), (o2), (n1), (n2));                       \
+})
+
+#define cmpxchg_double_local(ptr, o1, o2, n1, n2)                       \
+({                                                                      \
+       BUILD_BUG_ON(sizeof(*(ptr)) != 4);                               \
+       VM_BUG_ON((unsigned long)(ptr) % 8);                             \
+       cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2));                 \
+})
+
+#define system_has_cmpxchg_double() cpu_has_cx8
+
 #endif /* _ASM_X86_CMPXCHG_32_H */
diff --git a/arch/x86/include/asm/cmpxchg_64.h b/arch/x86/include/asm/cmpxchg_64.h
index 423ae58aa020..7cf5c0a24434 100644
--- a/arch/x86/include/asm/cmpxchg_64.h
+++ b/arch/x86/include/asm/cmpxchg_64.h
@@ -151,4 +151,49 @@ extern void __cmpxchg_wrong_size(void);
         cmpxchg_local((ptr), (o), (n));                                 \
 })
 
+#define cmpxchg16b(ptr, o1, o2, n1, n2)                         \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __junk;                                  \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile(LOCK_PREFIX "cmpxchg16b %2;setz %1"        \
+                       : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
+                       : "b"(__new1), "c"(__new2),              \
+                         "a"(__old1), "d"(__old2));             \
+        __ret; })
+
+
+#define cmpxchg16b_local(ptr, o1, o2, n1, n2)                   \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __junk;                                  \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile("cmpxchg16b %2;setz %1"                    \
+                       : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
+                       : "b"(__new1), "c"(__new2),              \
+                         "a"(__old1), "d"(__old2));             \
+        __ret; })
+
+#define cmpxchg_double(ptr, o1, o2, n1, n2)                             \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        VM_BUG_ON((unsigned long)(ptr) % 16);                           \
+        cmpxchg16b((ptr), (o1), (o2), (n1), (n2));                      \
+})
+
+#define cmpxchg_double_local(ptr, o1, o2, n1, n2)                       \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        VM_BUG_ON((unsigned long)(ptr) % 16);                           \
+        cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2));                \
+})
+
+#define system_has_cmpxchg_double() cpu_has_cx16
+
 #endif /* _ASM_X86_CMPXCHG_64_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 71cc3800712c..4258aac99a6e 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -288,6 +288,8 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_hypervisor      boot_cpu_has(X86_FEATURE_HYPERVISOR)
 #define cpu_has_pclmulqdq       boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 #define cpu_has_perfctr_core    boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
+#define cpu_has_cx8             boot_cpu_has(X86_FEATURE_CX8)
+#define cpu_has_cx16            boot_cpu_has(X86_FEATURE_CX16)
 
 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 # define cpu_has_invlpg         1
@@ -331,8 +333,8 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
                          "2:\n"
                          ".section .altinstructions,\"a\"\n"
                          _ASM_ALIGN "\n"
-                         _ASM_PTR "1b\n"
-                         _ASM_PTR "0\n"         /* no replacement */
+                         " .long 1b - .\n"
+                         " .long 0\n"           /* no replacement */
                          " .word %P0\n"         /* feature bit */
                          " .byte 2b - 1b\n"     /* source len */
                          " .byte 0\n"           /* replacement len */
@@ -349,8 +351,8 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
                              "2:\n"
                              ".section .altinstructions,\"a\"\n"
                              _ASM_ALIGN "\n"
-                             _ASM_PTR "1b\n"
-                             _ASM_PTR "3f\n"
+                             " .long 1b - .\n"
+                             " .long 3f - .\n"
                              " .word %P1\n"             /* feature bit */
                              " .byte 2b - 1b\n"         /* source len */
                              " .byte 4f - 3f\n"         /* replacement len */
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 1cd6d26a0a8d..0baa628e330c 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -53,8 +53,4 @@ BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
 BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)
 #endif
 
-#ifdef CONFIG_X86_MCE
-BUILD_INTERRUPT(mce_self_interrupt,MCE_SELF_VECTOR)
-#endif
-
 #endif
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 4729b2b63117..460c74e4852c 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -78,6 +78,7 @@ enum fixed_addresses {
         VSYSCALL_LAST_PAGE,
         VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE
                             + ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1,
+        VVAR_PAGE,
         VSYSCALL_HPET,
 #endif
         FIX_DBGP_BASE,
diff --git a/arch/x86/include/asm/frame.h b/arch/x86/include/asm/frame.h
index 2c6fc9e62812..3b629f47eb65 100644
--- a/arch/x86/include/asm/frame.h
+++ b/arch/x86/include/asm/frame.h
@@ -1,5 +1,6 @@
 #ifdef __ASSEMBLY__
 
+#include <asm/asm.h>
 #include <asm/dwarf2.h>
 
 /* The annotation hides the frame from the unwinder and makes it look
@@ -7,13 +8,13 @@
    frame pointer later */
 #ifdef CONFIG_FRAME_POINTER
         .macro FRAME
-        pushl_cfi %ebp
-        CFI_REL_OFFSET ebp,0
-        movl %esp,%ebp
+        __ASM_SIZE(push,_cfi)   %__ASM_REG(bp)
+        CFI_REL_OFFSET          __ASM_REG(bp), 0
+        __ASM_SIZE(mov)         %__ASM_REG(sp), %__ASM_REG(bp)
         .endm
         .macro ENDFRAME
-        popl_cfi %ebp
-        CFI_RESTORE ebp
+        __ASM_SIZE(pop,_cfi)    %__ASM_REG(bp)
+        CFI_RESTORE             __ASM_REG(bp)
         .endm
 #else
         .macro FRAME
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index bb9efe8706e2..13f5504c76c0 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -34,7 +34,6 @@ extern void irq_work_interrupt(void);
 extern void spurious_interrupt(void);
 extern void thermal_interrupt(void);
 extern void reschedule_interrupt(void);
-extern void mce_self_interrupt(void);
 
 extern void invalidate_interrupt(void);
 extern void invalidate_interrupt0(void);
diff --git a/arch/x86/include/asm/i8253.h b/arch/x86/include/asm/i8253.h
deleted file mode 100644
index 65aaa91d5850..000000000000
--- a/arch/x86/include/asm/i8253.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_X86_I8253_H
-#define _ASM_X86_I8253_H
-
-/* i8253A PIT registers */
-#define PIT_MODE                0x43
-#define PIT_CH0                 0x40
-#define PIT_CH2                 0x42
-
-#define PIT_LATCH       LATCH
-
-extern raw_spinlock_t i8253_lock;
-
-extern struct clock_event_device *global_clock_event;
-
-extern void setup_pit_timer(void);
-
-#define inb_pit         inb_p
-#define outb_pit        outb_p
-
-#endif /* _ASM_X86_I8253_H */
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 6e976ee3b3ef..f9a320984a10 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -17,7 +17,8 @@
  *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events
  *  Vectors  32 ... 127 : device interrupts
  *  Vector  128         : legacy int80 syscall interface
- *  Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 : device interrupts
+ *  Vector  204         : legacy x86_64 vsyscall emulation
+ *  Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts
  *  Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts
  *
  * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
@@ -50,6 +51,9 @@
 #ifdef CONFIG_X86_32
 # define SYSCALL_VECTOR                 0x80
 #endif
+#ifdef CONFIG_X86_64
+# define VSYSCALL_EMU_VECTOR            0xcc
+#endif
 
 /*
  * Vectors 0x30-0x3f are used for ISA interrupts.
@@ -109,11 +113,6 @@
 
 #define UV_BAU_MESSAGE                  0xf5
 
-/*
- * Self IPI vector for machine checks
- */
-#define MCE_SELF_VECTOR                 0xf4
-
 /* Xen vector callback to receive events in a HVM domain */
 #define XEN_HVM_EVTCHN_CALLBACK         0xf3
 
diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h
index 5745ce8bf108..bba3cf88e624 100644
--- a/arch/x86/include/asm/irqflags.h
+++ b/arch/x86/include/asm/irqflags.h
@@ -60,23 +60,24 @@ static inline void native_halt(void)
 #include <asm/paravirt.h>
 #else
 #ifndef __ASSEMBLY__
+#include <linux/types.h>
 
-static inline unsigned long arch_local_save_flags(void)
+static inline notrace unsigned long arch_local_save_flags(void)
 {
         return native_save_fl();
 }
 
-static inline void arch_local_irq_restore(unsigned long flags)
+static inline notrace void arch_local_irq_restore(unsigned long flags)
 {
         native_restore_fl(flags);
 }
 
-static inline void arch_local_irq_disable(void)
+static inline notrace void arch_local_irq_disable(void)
 {
         native_irq_disable();
 }
 
-static inline void arch_local_irq_enable(void)
+static inline notrace void arch_local_irq_enable(void)
 {
         native_irq_enable();
 }
@@ -102,7 +103,7 @@ static inline void halt(void)
 /*
  * For spinlocks, etc:
  */
-static inline unsigned long arch_local_irq_save(void)
+static inline notrace unsigned long arch_local_irq_save(void)
 {
         unsigned long flags = arch_local_save_flags();
         arch_local_irq_disable();
diff --git a/arch/x86/include/asm/lguest_hcall.h b/arch/x86/include/asm/lguest_hcall.h
index b60f2924c413..879fd7d33877 100644
--- a/arch/x86/include/asm/lguest_hcall.h
+++ b/arch/x86/include/asm/lguest_hcall.h
@@ -61,6 +61,7 @@ hcall(unsigned long call,
                      : "memory");
         return call;
 }
+/*:*/
 
 /* Can't use our min() macro here: needs to be a constant */
 #define LGUEST_IRQS (NR_IRQS < 32 ? NR_IRQS: 32)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 021979a6e23f..716b48af7863 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -8,6 +8,7 @@
  * Machine Check support for x86
  */
 
+/* MCG_CAP register defines */
 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
@@ -17,10 +18,12 @@
 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
 
+/* MCG_STATUS register defines */
 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
 
+/* MCi_STATUS register defines */
 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
@@ -31,12 +34,14 @@
 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
 
-/* MISC register defines */
-#define MCM_ADDR_SEGOFF  0      /* segment offset */
-#define MCM_ADDR_LINEAR  1      /* linear address */
-#define MCM_ADDR_PHYS    2      /* physical address */
-#define MCM_ADDR_MEM     3      /* memory address */
-#define MCM_ADDR_GENERIC 7      /* generic */
+/* MCi_MISC register defines */
+#define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
+#define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
+#define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
+#define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
+#define  MCI_MISC_ADDR_PHYS     2       /* physical address */
+#define  MCI_MISC_ADDR_MEM      3       /* memory address */
+#define  MCI_MISC_ADDR_GENERIC  7       /* generic */
 
 /* CTL2 register defines */
 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
@@ -144,7 +149,7 @@ static inline void enable_p5_mce(void) {}
 
 void mce_setup(struct mce *m);
 void mce_log(struct mce *m);
-DECLARE_PER_CPU(struct sys_device, mce_dev);
+DECLARE_PER_CPU(struct sys_device, mce_sysdev);
 
 /*
  * Maximum banks number.
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h
index 224e8c5eb307..55728e121473 100644
--- a/arch/x86/include/asm/mmzone_32.h
+++ b/arch/x86/include/asm/mmzone_32.h
@@ -34,15 +34,15 @@ static inline void resume_map_numa_kva(pgd_t *pgd) {}
  *    64Gb / 4096bytes/page = 16777216 pages
  */
 #define MAX_NR_PAGES 16777216
-#define MAX_ELEMENTS 1024
-#define PAGES_PER_ELEMENT (MAX_NR_PAGES/MAX_ELEMENTS)
+#define MAX_SECTIONS 1024
+#define PAGES_PER_SECTION (MAX_NR_PAGES/MAX_SECTIONS)
 
 extern s8 physnode_map[];
 
 static inline int pfn_to_nid(unsigned long pfn)
 {
 #ifdef CONFIG_NUMA
-        return((int) physnode_map[(pfn) / PAGES_PER_ELEMENT]);
+        return((int) physnode_map[(pfn) / PAGES_PER_SECTION]);
 #else
         return 0;
 #endif
@@ -57,6 +57,8 @@ static inline int pfn_valid(int pfn)
         return 0;
 }
 
+#define early_pfn_valid(pfn)    pfn_valid((pfn))
+
 #endif /* CONFIG_DISCONTIGMEM */
 
 #ifdef CONFIG_NEED_MULTIPLE_NODES
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e3022ccff33b..d52609aeeab8 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -259,6 +259,9 @@
 #define MSR_IA32_TEMPERATURE_TARGET     0x000001a2
 
 #define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
+#define ENERGY_PERF_BIAS_PERFORMANCE    0
+#define ENERGY_PERF_BIAS_NORMAL         6
+#define ENERGY_PERF_BIAS_POWERSAVE      15
 
 #define MSR_IA32_PACKAGE_THERM_STATUS           0x000001b1
 
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index a0a9779084d1..3470c9d0ebba 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -388,12 +388,9 @@ do {									\
 #define __this_cpu_xor_1(pcp, val)      percpu_to_op("xor", (pcp), val)
 #define __this_cpu_xor_2(pcp, val)      percpu_to_op("xor", (pcp), val)
 #define __this_cpu_xor_4(pcp, val)      percpu_to_op("xor", (pcp), val)
-/*
- * Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much
- * faster than an xchg with forced lock semantics.
- */
-#define __this_cpu_xchg_8(pcp, nval)    percpu_xchg_op(pcp, nval)
-#define __this_cpu_cmpxchg_8(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+#define __this_cpu_xchg_1(pcp, val)     percpu_xchg_op(pcp, val)
+#define __this_cpu_xchg_2(pcp, val)     percpu_xchg_op(pcp, val)
+#define __this_cpu_xchg_4(pcp, val)     percpu_xchg_op(pcp, val)
 
 #define this_cpu_read_1(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
 #define this_cpu_read_2(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
@@ -485,6 +482,8 @@ do {									\
 #define __this_cpu_or_8(pcp, val)       percpu_to_op("or", (pcp), val)
 #define __this_cpu_xor_8(pcp, val)      percpu_to_op("xor", (pcp), val)
 #define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
+#define __this_cpu_xchg_8(pcp, nval)    percpu_xchg_op(pcp, nval)
+#define __this_cpu_cmpxchg_8(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
 
 #define this_cpu_read_8(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
 #define this_cpu_write_8(pcp, val)      percpu_to_op("mov", (pcp), val)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index d9d4dae305f6..094fb30817ab 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -152,6 +152,11 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
         (regs)->bp = caller_frame_pointer();                    \
         (regs)->cs = __KERNEL_CS;                               \
         regs->flags = 0;                                        \
+        asm volatile(                                           \
+                _ASM_MOV "%%"_ASM_SP ", %0\n"                   \
+                : "=m" ((regs)->sp)                             \
+                :: "memory"                                     \
+        );                                                      \
 }
 
 #else
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 56fd9e3abbda..4f7e67e2345e 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -102,6 +102,14 @@
 #define P4_CONFIG_HT                    (1ULL << P4_CONFIG_HT_SHIFT)
 
 /*
+ * If an event has alias it should be marked
+ * with a special bit. (Don't forget to check
+ * P4_PEBS_CONFIG_MASK and related bits on
+ * modification.)
+ */
+#define P4_CONFIG_ALIASABLE             (1 << 9)
+
+/*
  * The bits we allow to pass for RAW events
  */
 #define P4_CONFIG_MASK_ESCR             \
@@ -123,6 +131,31 @@
         (p4_config_pack_escr(P4_CONFIG_MASK_ESCR))      | \
         (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))
 
+/*
+ * In case of event aliasing we need to preserve some
+ * caller bits, otherwise the mapping won't be complete.
+ */
+#define P4_CONFIG_EVENT_ALIAS_MASK                        \
+        (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)       | \
+         p4_config_pack_cccr(P4_CCCR_EDGE               | \
+                             P4_CCCR_THRESHOLD_MASK     | \
+                             P4_CCCR_COMPLEMENT         | \
+                             P4_CCCR_COMPARE))
+
+#define  P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS             \
+        ((P4_CONFIG_HT)                                 | \
+         p4_config_pack_escr(P4_ESCR_T0_OS              | \
+                             P4_ESCR_T0_USR             | \
+                             P4_ESCR_T1_OS              | \
+                             P4_ESCR_T1_USR)            | \
+         p4_config_pack_cccr(P4_CCCR_OVF                | \
+                             P4_CCCR_CASCADE            | \
+                             P4_CCCR_FORCE_OVF          | \
+                             P4_CCCR_THREAD_ANY         | \
+                             P4_CCCR_OVF_PMI_T0         | \
+                             P4_CCCR_OVF_PMI_T1         | \
+                             P4_CONFIG_ALIASABLE))
+
 static inline bool p4_is_event_cascaded(u64 config)
 {
         u32 cccr = p4_config_unpack_cccr(config);
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index d56187c6b838..013286a10c2c 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -107,7 +107,8 @@
 #define __PAGE_KERNEL_NOCACHE           (__PAGE_KERNEL | _PAGE_PCD | _PAGE_PWT)
 #define __PAGE_KERNEL_UC_MINUS          (__PAGE_KERNEL | _PAGE_PCD)
 #define __PAGE_KERNEL_VSYSCALL          (__PAGE_KERNEL_RX | _PAGE_USER)
-#define __PAGE_KERNEL_VSYSCALL_NOCACHE  (__PAGE_KERNEL_VSYSCALL | _PAGE_PCD | _PAGE_PWT)
+#define __PAGE_KERNEL_VVAR              (__PAGE_KERNEL_RO | _PAGE_USER)
+#define __PAGE_KERNEL_VVAR_NOCACHE      (__PAGE_KERNEL_VVAR | _PAGE_PCD | _PAGE_PWT)
 #define __PAGE_KERNEL_LARGE             (__PAGE_KERNEL | _PAGE_PSE)
 #define __PAGE_KERNEL_LARGE_NOCACHE     (__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE)
 #define __PAGE_KERNEL_LARGE_EXEC        (__PAGE_KERNEL_EXEC | _PAGE_PSE)
@@ -129,7 +130,8 @@
 #define PAGE_KERNEL_LARGE_NOCACHE       __pgprot(__PAGE_KERNEL_LARGE_NOCACHE)
 #define PAGE_KERNEL_LARGE_EXEC          __pgprot(__PAGE_KERNEL_LARGE_EXEC)
 #define PAGE_KERNEL_VSYSCALL            __pgprot(__PAGE_KERNEL_VSYSCALL)
-#define PAGE_KERNEL_VSYSCALL_NOCACHE    __pgprot(__PAGE_KERNEL_VSYSCALL_NOCACHE)
+#define PAGE_KERNEL_VVAR                __pgprot(__PAGE_KERNEL_VVAR)
+#define PAGE_KERNEL_VVAR_NOCACHE        __pgprot(__PAGE_KERNEL_VVAR_NOCACHE)
 
 #define PAGE_KERNEL_IO                  __pgprot(__PAGE_KERNEL_IO)
 #define PAGE_KERNEL_IO_NOCACHE          __pgprot(__PAGE_KERNEL_IO_NOCACHE)
diff --git a/arch/x86/include/asm/prom.h b/arch/x86/include/asm/prom.h
index 971e0b46446e..df1287019e6d 100644
--- a/arch/x86/include/asm/prom.h
+++ b/arch/x86/include/asm/prom.h
@@ -30,17 +30,6 @@ extern void add_dtb(u64 data);
 extern void x86_add_irq_domains(void);
 void __cpuinit x86_of_pci_init(void);
 void x86_dtb_init(void);
-
-static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
-{
-        return pdev ? pdev->dev.of_node : NULL;
-}
-
-static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
-{
-        return pci_device_to_OF_node(bus->self);
-}
-
 #else
 static inline void add_dtb(u64 data) { }
 static inline void x86_add_irq_domains(void) { }
diff --git a/arch/x86/include/asm/rwlock.h b/arch/x86/include/asm/rwlock.h
index 6a8c0d645108..a5370a03d90c 100644
--- a/arch/x86/include/asm/rwlock.h
+++ b/arch/x86/include/asm/rwlock.h
@@ -1,7 +1,48 @@
 #ifndef _ASM_X86_RWLOCK_H
 #define _ASM_X86_RWLOCK_H
 
-#define RW_LOCK_BIAS             0x01000000
+#include <asm/asm.h>
+
+#if CONFIG_NR_CPUS <= 2048
+
+#ifndef __ASSEMBLY__
+typedef union {
+        s32 lock;
+        s32 write;
+} arch_rwlock_t;
+#endif
+
+#define RW_LOCK_BIAS            0x00100000
+#define READ_LOCK_SIZE(insn)    __ASM_FORM(insn##l)
+#define READ_LOCK_ATOMIC(n)     atomic_##n
+#define WRITE_LOCK_ADD(n)       __ASM_FORM_COMMA(addl n)
+#define WRITE_LOCK_SUB(n)       __ASM_FORM_COMMA(subl n)
+#define WRITE_LOCK_CMP          RW_LOCK_BIAS
+
+#else /* CONFIG_NR_CPUS > 2048 */
+
+#include <linux/const.h>
+
+#ifndef __ASSEMBLY__
+typedef union {
+        s64 lock;
+        struct {
+                u32 read;
+                s32 write;
+        };
+} arch_rwlock_t;
+#endif
+
+#define RW_LOCK_BIAS            (_AC(1,L) << 32)
+#define READ_LOCK_SIZE(insn)    __ASM_FORM(insn##q)
+#define READ_LOCK_ATOMIC(n)     atomic64_##n
+#define WRITE_LOCK_ADD(n)       __ASM_FORM(incl)
+#define WRITE_LOCK_SUB(n)       __ASM_FORM(decl)
+#define WRITE_LOCK_CMP          1
+
+#endif /* CONFIG_NR_CPUS */
+
+#define __ARCH_RW_LOCK_UNLOCKED         { RW_LOCK_BIAS }
 
 /* Actual code is in asm/spinlock.h or in arch/x86/lib/rwlock.S */
 
diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h
index cd84f7208f76..5e641715c3fe 100644
--- a/arch/x86/include/asm/segment.h
+++ b/arch/x86/include/asm/segment.h
@@ -162,7 +162,7 @@
 #define GDT_ENTRY_DEFAULT_USER32_CS 4
 #define GDT_ENTRY_DEFAULT_USER_DS 5
 #define GDT_ENTRY_DEFAULT_USER_CS 6
-#define __USER32_CS   (GDT_ENTRY_DEFAULT_USER32_CS * 8 + 3)
+#define __USER32_CS   (GDT_ENTRY_DEFAULT_USER32_CS*8+3)
 #define __USER32_DS     __USER_DS
 
 #define GDT_ENTRY_TSS 8 /* needs two entries */
diff --git a/arch/x86/include/asm/smpboot_hooks.h b/arch/x86/include/asm/smpboot_hooks.h
index 725b77831993..49adfd7bb4a4 100644
--- a/arch/x86/include/asm/smpboot_hooks.h
+++ b/arch/x86/include/asm/smpboot_hooks.h
@@ -10,7 +10,11 @@ static inline void smpboot_clear_io_apic_irqs(void)
 
 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
 {
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtc_lock, flags);
         CMOS_WRITE(0xa, 0xf);
+        spin_unlock_irqrestore(&rtc_lock, flags);
         local_flush_tlb();
         pr_debug("1.\n");
         *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_high)) =
@@ -23,6 +27,8 @@ static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
 
 static inline void smpboot_restore_warm_reset_vector(void)
 {
+        unsigned long flags;
+
         /*
          * Install writable page 0 entry to set BIOS data area.
          */
@@ -32,7 +38,9 @@ static inline void smpboot_restore_warm_reset_vector(void)
          * Paranoid:  Set warm reset code and vector here back
          * to default values.
          */
+        spin_lock_irqsave(&rtc_lock, flags);
         CMOS_WRITE(0, 0xf);
+        spin_unlock_irqrestore(&rtc_lock, flags);
 
         *((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0;
 }
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index 3089f70c0c52..e9e51f710e6c 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -2,7 +2,6 @@
 #define _ASM_X86_SPINLOCK_H
 
 #include <asm/atomic.h>
-#include <asm/rwlock.h>
 #include <asm/page.h>
 #include <asm/processor.h>
 #include <linux/compiler.h>
@@ -234,7 +233,7 @@ static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
  */
 static inline int arch_read_can_lock(arch_rwlock_t *lock)
 {
-        return (int)(lock)->lock > 0;
+        return lock->lock > 0;
 }
 
 /**
@@ -243,12 +242,12 @@ static inline int arch_read_can_lock(arch_rwlock_t *lock)
  */
 static inline int arch_write_can_lock(arch_rwlock_t *lock)
 {
-        return (lock)->lock == RW_LOCK_BIAS;
+        return lock->write == WRITE_LOCK_CMP;
 }
 
 static inline void arch_read_lock(arch_rwlock_t *rw)
 {
-        asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
+        asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
                      "jns 1f\n"
                      "call __read_lock_failed\n\t"
                      "1:\n"
@@ -257,47 +256,55 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
 
 static inline void arch_write_lock(arch_rwlock_t *rw)
 {
-        asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
+        asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
                      "jz 1f\n"
                      "call __write_lock_failed\n\t"
                      "1:\n"
-                     ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
+                     ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
+                     : "memory");
 }
 
 static inline int arch_read_trylock(arch_rwlock_t *lock)
 {
-        atomic_t *count = (atomic_t *)lock;
+        READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
 
-        if (atomic_dec_return(count) >= 0)
+        if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
                 return 1;
-        atomic_inc(count);
+        READ_LOCK_ATOMIC(inc)(count);
         return 0;
 }
 
 static inline int arch_write_trylock(arch_rwlock_t *lock)
 {
-        atomic_t *count = (atomic_t *)lock;
+        atomic_t *count = (atomic_t *)&lock->write;
 
-        if (atomic_sub_and_test(RW_LOCK_BIAS, count))
+        if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
                 return 1;
-        atomic_add(RW_LOCK_BIAS, count);
+        atomic_add(WRITE_LOCK_CMP, count);
         return 0;
 }
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
-        asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
+        asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
+                     :"+m" (rw->lock) : : "memory");
 }
 
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
-        asm volatile(LOCK_PREFIX "addl %1, %0"
-                     : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
+        asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
+                     : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
 }
 
 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 
+#undef READ_LOCK_SIZE
+#undef READ_LOCK_ATOMIC
+#undef WRITE_LOCK_ADD
+#undef WRITE_LOCK_SUB
+#undef WRITE_LOCK_CMP
+
 #define arch_spin_relax(lock)   cpu_relax()
 #define arch_read_relax(lock)   cpu_relax()
 #define arch_write_relax(lock)  cpu_relax()
diff --git a/arch/x86/include/asm/spinlock_types.h b/arch/x86/include/asm/spinlock_types.h
index dcb48b2edc11..7c7a486fcb68 100644
--- a/arch/x86/include/asm/spinlock_types.h
+++ b/arch/x86/include/asm/spinlock_types.h
@@ -11,10 +11,6 @@ typedef struct arch_spinlock {
 
 #define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
-typedef struct {
-        unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED         { RW_LOCK_BIAS }
+#include <asm/rwlock.h>
 
 #endif /* _ASM_X86_SPINLOCK_TYPES_H */
diff --git a/arch/x86/include/asm/time.h b/arch/x86/include/asm/time.h
index 7bdec4e9b739..92b8aec06970 100644
--- a/arch/x86/include/asm/time.h
+++ b/arch/x86/include/asm/time.h
@@ -1,10 +1,12 @@
 #ifndef _ASM_X86_TIME_H
 #define _ASM_X86_TIME_H
 
-extern void hpet_time_init(void);
-
+#include <linux/clocksource.h>
 #include <asm/mc146818rtc.h>
 
+extern void hpet_time_init(void);
 extern void time_init(void);
 
+extern struct clock_event_device *global_clock_event;
+
 #endif /* _ASM_X86_TIME_H */
diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
index 0310da67307f..2bae0a513b40 100644
--- a/arch/x86/include/asm/traps.h
+++ b/arch/x86/include/asm/traps.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_X86_TRAPS_H
 #define _ASM_X86_TRAPS_H
 
+#include <linux/kprobes.h>
+
 #include <asm/debugreg.h>
 #include <asm/siginfo.h>                        /* TRAP_TRACE, ... */
 
@@ -38,6 +40,7 @@ asmlinkage void alignment_check(void);
 asmlinkage void machine_check(void);
 #endif /* CONFIG_X86_MCE */
 asmlinkage void simd_coprocessor_error(void);
+asmlinkage void emulate_vsyscall(void);
 
 dotraplinkage void do_divide_error(struct pt_regs *, long);
 dotraplinkage void do_debug(struct pt_regs *, long);
@@ -64,6 +67,7 @@ dotraplinkage void do_alignment_check(struct pt_regs *, long);
 dotraplinkage void do_machine_check(struct pt_regs *, long);
 #endif
 dotraplinkage void do_simd_coprocessor_error(struct pt_regs *, long);
+dotraplinkage void do_emulate_vsyscall(struct pt_regs *, long);
 #ifdef CONFIG_X86_32
 dotraplinkage void do_iret_error(struct pt_regs *, long);
 #endif
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 9db5583b6d38..83e2efd181e2 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -51,10 +51,6 @@ extern int unsynchronized_tsc(void);
 extern int check_tsc_unstable(void);
 extern unsigned long native_calibrate_tsc(void);
 
-#ifdef CONFIG_X86_64
-extern cycles_t vread_tsc(void);
-#endif
-
 /*
  * Boot-time check whether the TSCs are synchronized across
  * all CPUs/cores:
diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h
index 99ddd148a760..36361bf6fdd1 100644
--- a/arch/x86/include/asm/uaccess.h
+++ b/arch/x86/include/asm/uaccess.h
@@ -555,6 +555,9 @@ struct __large_struct { unsigned long buf[100]; };
 
 #endif /* CONFIG_X86_WP_WORKS_OK */
 
+extern unsigned long
+copy_from_user_nmi(void *to, const void __user *from, unsigned long n);
+
 /*
  * movsl can be slow when source and dest are not both 8-byte aligned
  */
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index a291c40efd43..37d369859c8e 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -67,7 +67,7 @@
  *  we're using 655us, similar to UV1: 65 units of 10us
  */
 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
-#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL)
+#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
 
 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ?                 \
                 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD :                      \
@@ -106,12 +106,20 @@
 #define DS_SOURCE_TIMEOUT               3
 /*
  * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
- * values 1 and 5 will not occur
+ * values 1 and 3 will not occur
+ *        Decoded meaning              ERROR  BUSY    AUX ERR
+ * -------------------------------     ----   -----   -------
+ * IDLE                                 0       0        0
+ * BUSY (active)                        0       1        0
+ * SW Ack Timeout (destination)         1       0        0
+ * SW Ack INTD rejected (strong NACK)   1       0        1
+ * Source Side Time Out Detected        1       1        0
+ * Destination Side PUT Failed          1       1        1
  */
 #define UV2H_DESC_IDLE                  0
-#define UV2H_DESC_DEST_TIMEOUT          2
-#define UV2H_DESC_DEST_STRONG_NACK      3
-#define UV2H_DESC_BUSY                  4
+#define UV2H_DESC_BUSY                  2
+#define UV2H_DESC_DEST_TIMEOUT          4
+#define UV2H_DESC_DEST_STRONG_NACK      5
 #define UV2H_DESC_SOURCE_TIMEOUT        6
 #define UV2H_DESC_DEST_PUT_ERR          7
 
@@ -183,7 +191,7 @@
  * 'base_dest_nasid' field of the header corresponds to the
  * destination nodeID associated with that specified bit.
  */
-struct bau_targ_hubmask {
+struct pnmask {
         unsigned long           bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
 };
 
@@ -314,7 +322,7 @@ struct bau_msg_header {
  * Should be 64 bytes
  */
 struct bau_desc {
-        struct bau_targ_hubmask distribution;
+        struct pnmask                   distribution;
         /*
          * message template, consisting of header and payload:
          */
@@ -488,6 +496,7 @@ struct bau_control {
         struct bau_control      *uvhub_master;
         struct bau_control      *socket_master;
         struct ptc_stats        *statp;
+        cpumask_t               *cpumask;
         unsigned long           timeout_interval;
         unsigned long           set_bau_on_time;
         atomic_t                active_descriptor_count;
@@ -526,90 +535,90 @@ struct bau_control {
         struct hub_and_pnode    *thp;
 };
 
-static unsigned long read_mmr_uv2_status(void)
+static inline unsigned long read_mmr_uv2_status(void)
 {
         return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
 }
 
-static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
+static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
 {
         write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
 }
 
-static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
+static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
 {
         write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
 }
 
-static void write_mmr_activation(unsigned long index)
+static inline void write_mmr_activation(unsigned long index)
 {
         write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
 }
 
-static void write_gmmr_activation(int pnode, unsigned long mmr_image)
+static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
 {
         write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
 }
 
-static void write_mmr_payload_first(int pnode, unsigned long mmr_image)
+static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
 {
         write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
 }
 
-static void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
+static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
 {
         write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
 }
 
-static void write_mmr_payload_last(int pnode, unsigned long mmr_image)
+static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
 {
         write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
 }
 
-static void write_mmr_misc_control(int pnode, unsigned long mmr_image)
+static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
 {
         write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
 }
 
-static unsigned long read_mmr_misc_control(int pnode)
+static inline unsigned long read_mmr_misc_control(int pnode)
 {
         return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
 }
 
-static void write_mmr_sw_ack(unsigned long mr)
+static inline void write_mmr_sw_ack(unsigned long mr)
 {
         uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
 }
 
-static unsigned long read_mmr_sw_ack(void)
+static inline unsigned long read_mmr_sw_ack(void)
 {
         return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
 }
 
-static unsigned long read_gmmr_sw_ack(int pnode)
+static inline unsigned long read_gmmr_sw_ack(int pnode)
 {
         return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
 }
 
-static void write_mmr_data_config(int pnode, unsigned long mr)
+static inline void write_mmr_data_config(int pnode, unsigned long mr)
 {
         uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
 }
 
-static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp)
+static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
 {
         return constant_test_bit(uvhub, &dstp->bits[0]);
 }
-static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp)
+static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
 {
         __set_bit(pnode, &dstp->bits[0]);
 }
-static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp,
+static inline void bau_uvhubs_clear(struct pnmask *dstp,
                                     int nbits)
 {
         bitmap_zero(&dstp->bits[0], nbits);
 }
-static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp)
+static inline int bau_uvhub_weight(struct pnmask *dstp)
 {
         return bitmap_weight((unsigned long *)&dstp->bits[0],
                                 UV_DISTRIBUTION_SIZE);
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index 4be52c863448..10474fb1185d 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -61,1689 +61,2016 @@
 /* Compat: if this #define is present, UV headers support UV2 */
 #define UV2_HUB_IS_SUPPORTED    1
 
-/* KABI compat: if this #define is present, KABI hacks are present */
-#define UV2_HUB_KABI_HACKS      1
-
 /* ========================================================================= */
 /*                          UVH_BAU_DATA_BROADCAST                           */
 /* ========================================================================= */
-#define UVH_BAU_DATA_BROADCAST 0x61688UL
-#define UVH_BAU_DATA_BROADCAST_32 0x440
+#define UVH_BAU_DATA_BROADCAST                          0x61688UL
+#define UVH_BAU_DATA_BROADCAST_32                       0x440
 
-#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
-#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
+#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT              0
+#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK              0x0000000000000001UL
 
 union uvh_bau_data_broadcast_u {
-    unsigned long       v;
-    struct uvh_bau_data_broadcast_s {
-        unsigned long   enable :  1;  /* RW */
-        unsigned long   rsvd_1_63: 63;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_bau_data_broadcast_s {
+                unsigned long   enable:1;                       /* RW */
+                unsigned long   rsvd_1_63:63;
+        } s;
 };
 
 /* ========================================================================= */
 /*                           UVH_BAU_DATA_CONFIG                             */
 /* ========================================================================= */
-#define UVH_BAU_DATA_CONFIG 0x61680UL
-#define UVH_BAU_DATA_CONFIG_32 0x438
-
-#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
-#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
-#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
-#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
-#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_BAU_DATA_CONFIG_P_SHFT 13
-#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_BAU_DATA_CONFIG_T_SHFT 15
-#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_BAU_DATA_CONFIG_M_SHFT 16
-#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
-#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+#define UVH_BAU_DATA_CONFIG                             0x61680UL
+#define UVH_BAU_DATA_CONFIG_32                          0x438
+
+#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT                 0
+#define UVH_BAU_DATA_CONFIG_DM_SHFT                     8
+#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT               11
+#define UVH_BAU_DATA_CONFIG_STATUS_SHFT                 12
+#define UVH_BAU_DATA_CONFIG_P_SHFT                      13
+#define UVH_BAU_DATA_CONFIG_T_SHFT                      15
+#define UVH_BAU_DATA_CONFIG_M_SHFT                      16
+#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT                32
+#define UVH_BAU_DATA_CONFIG_VECTOR_MASK                 0x00000000000000ffUL
+#define UVH_BAU_DATA_CONFIG_DM_MASK                     0x0000000000000700UL
+#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK               0x0000000000000800UL
+#define UVH_BAU_DATA_CONFIG_STATUS_MASK                 0x0000000000001000UL
+#define UVH_BAU_DATA_CONFIG_P_MASK                      0x0000000000002000UL
+#define UVH_BAU_DATA_CONFIG_T_MASK                      0x0000000000008000UL
+#define UVH_BAU_DATA_CONFIG_M_MASK                      0x0000000000010000UL
+#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
 
 union uvh_bau_data_config_u {
-    unsigned long       v;
-    struct uvh_bau_data_config_s {
-        unsigned long   vector_  :  8;  /* RW */
-        unsigned long   dm       :  3;  /* RW */
-        unsigned long   destmode :  1;  /* RW */
-        unsigned long   status   :  1;  /* RO */
-        unsigned long   p        :  1;  /* RO */
-        unsigned long   rsvd_14  :  1;  /*    */
-        unsigned long   t        :  1;  /* RO */
-        unsigned long   m        :  1;  /* RW */
-        unsigned long   rsvd_17_31: 15;  /*    */
-        unsigned long   apic_id  : 32;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_bau_data_config_s {
+                unsigned long   vector_:8;                      /* RW */
+                unsigned long   dm:3;                           /* RW */
+                unsigned long   destmode:1;                     /* RW */
+                unsigned long   status:1;                       /* RO */
+                unsigned long   p:1;                            /* RO */
+                unsigned long   rsvd_14:1;
+                unsigned long   t:1;                            /* RO */
+                unsigned long   m:1;                            /* RW */
+                unsigned long   rsvd_17_31:15;
+                unsigned long   apic_id:32;                     /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                           UVH_EVENT_OCCURRED0                             */
 /* ========================================================================= */
-#define UVH_EVENT_OCCURRED0 0x70000UL
-#define UVH_EVENT_OCCURRED0_32 0x5e8
-
-#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
-#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
-#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
-#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
-#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
-#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
-#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
-#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
-#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4
-#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
-#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5
-#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
-#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6
-#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
-#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
-#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
-#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
-#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
-#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
-#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
-#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
-#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
-#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
-#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
-#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
-#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
-#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
-#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
-#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
-#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
-#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
-#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
-#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
-#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
-#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
-#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
-#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
-#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
-#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
-#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
-#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
-#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
-#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
-#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
-#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
-#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
-#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43
-#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
-#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
-#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
-#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45
-#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
-#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
-#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
-#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51
-#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
-#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52
-#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
-#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53
-#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
-#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
-#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
-#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
-#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
-#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
-#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
-
-#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
-#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
-#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
-#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
-#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
-#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
-#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
-#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
-#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
-#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
-#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
-#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
-#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
-#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
-#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
-#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
-#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
-#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
-#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
-#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
-#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
-#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
-#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
-#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
-#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
-#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
-#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
-#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
-#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
-#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
-#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
-#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
-#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
-#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
-#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
-#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
-#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
-#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
-#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
-#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
-#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
-#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
-#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
-#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
-#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
-#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
-#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
-#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
-#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
-#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
-#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
-#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
-#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
-#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
+#define UVH_EVENT_OCCURRED0                             0x70000UL
+#define UVH_EVENT_OCCURRED0_32                          0x5e8
+
+#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT              0
+#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT             1
+#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT             2
+#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT              3
+#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT              4
+#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT              5
+#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT              6
+#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT             7
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT            8
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT            9
+#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT             10
+#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT             11
+#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT             12
+#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT             13
+#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT             14
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            15
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            16
+#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT             17
+#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT             18
+#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT             19
+#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT             20
+#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT            21
+#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   22
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          23
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          24
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          25
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          26
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          27
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          28
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          29
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          30
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          31
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          32
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         33
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         34
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         35
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         36
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         37
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         38
+#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            39
+#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            40
+#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            41
+#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            42
+#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT               43
+#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        44
+#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT               45
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            46
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            47
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            48
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            49
+#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT           50
+#define UV1H_EVENT_OCCURRED0_RTC0_SHFT                  51
+#define UV1H_EVENT_OCCURRED0_RTC1_SHFT                  52
+#define UV1H_EVENT_OCCURRED0_RTC2_SHFT                  53
+#define UV1H_EVENT_OCCURRED0_RTC3_SHFT                  54
+#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT              55
+#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT  56
+#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK              0x0000000000000001UL
+#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000002UL
+#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000004UL
+#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK              0x0000000000000008UL
+#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000010UL
+#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK              0x0000000000000020UL
+#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK              0x0000000000000040UL
+#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000080UL
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000000100UL
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000000200UL
+#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK             0x0000000000000400UL
+#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK             0x0000000000000800UL
+#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK             0x0000000000001000UL
+#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK             0x0000000000002000UL
+#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000004000UL
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000000008000UL
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000000010000UL
+#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK             0x0000000000020000UL
+#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000040000UL
+#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK             0x0000000000080000UL
+#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK             0x0000000000100000UL
+#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK            0x0000000000200000UL
+#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000000400000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000000800000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000001000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000002000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000004000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000000008000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000000010000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000000020000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000000040000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000000080000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000000100000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000000200000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000000400000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000000800000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000001000000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000002000000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000004000000000UL
+#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0000008000000000UL
+#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0000010000000000UL
+#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0000020000000000UL
+#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0000040000000000UL
+#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK               0x0000080000000000UL
+#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0000100000000000UL
+#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK               0x0000200000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0000400000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0000800000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0001000000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0002000000000000UL
+#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0004000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC0_MASK                  0x0008000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC1_MASK                  0x0010000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC2_MASK                  0x0020000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC3_MASK                  0x0040000000000000UL
+#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK              0x0080000000000000UL
+#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK  0x0100000000000000UL
+
+#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT              0
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT              1
+#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT              2
+#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT             3
+#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT             4
+#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT             5
+#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT             6
+#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT             7
+#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT             8
+#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT             9
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT             10
+#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT             11
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT            12
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT            13
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT            14
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT            15
+#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT             16
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT             17
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT            18
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT            19
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT             20
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT             21
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT             22
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT            23
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT            24
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT            25
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT            26
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT             27
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT             28
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT            29
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT            30
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT   31
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT          32
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT          33
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT          34
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT          35
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT          36
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT          37
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT          38
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT          39
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT          40
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT          41
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT         42
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT         43
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT         44
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT         45
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT         46
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT         47
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT            48
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT            49
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT            50
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT            51
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT        52
+#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT               53
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT            54
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT            55
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT            56
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT            57
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT           58
+#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK              0x0000000000000001UL
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK              0x0000000000000002UL
+#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK              0x0000000000000004UL
+#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK             0x0000000000000008UL
+#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK             0x0000000000000010UL
+#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK             0x0000000000000020UL
+#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK             0x0000000000000040UL
+#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK             0x0000000000000080UL
+#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK             0x0000000000000100UL
+#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK             0x0000000000000200UL
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK             0x0000000000000400UL
+#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK             0x0000000000000800UL
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK            0x0000000000001000UL
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK            0x0000000000002000UL
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK            0x0000000000004000UL
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK            0x0000000000008000UL
+#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK             0x0000000000010000UL
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK             0x0000000000020000UL
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK            0x0000000000040000UL
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK            0x0000000000080000UL
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK             0x0000000000100000UL
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK             0x0000000000200000UL
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK             0x0000000000400000UL
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK            0x0000000000800000UL
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK            0x0000000001000000UL
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK            0x0000000002000000UL
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK            0x0000000004000000UL
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK             0x0000000008000000UL
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK             0x0000000010000000UL
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK            0x0000000020000000UL
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK            0x0000000040000000UL
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK   0x0000000080000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK          0x0000000100000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK          0x0000000200000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK          0x0000000400000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK          0x0000000800000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK          0x0000001000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK          0x0000002000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK          0x0000004000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK          0x0000008000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK          0x0000010000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK          0x0000020000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK         0x0000040000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK         0x0000080000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK         0x0000100000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK         0x0000200000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK         0x0000400000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK         0x0000800000000000UL
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK            0x0001000000000000UL
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK            0x0002000000000000UL
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK            0x0004000000000000UL
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK            0x0008000000000000UL
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK        0x0010000000000000UL
+#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK               0x0020000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK            0x0040000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK            0x0080000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK            0x0100000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK            0x0200000000000000UL
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK           0x0400000000000000UL
 
 union uvh_event_occurred0_u {
-    unsigned long       v;
-    struct uv1h_event_occurred0_s {
-        unsigned long   lb_hcerr             :  1;  /* RW, W1C */
-        unsigned long   gr0_hcerr            :  1;  /* RW, W1C */
-        unsigned long   gr1_hcerr            :  1;  /* RW, W1C */
-        unsigned long   lh_hcerr             :  1;  /* RW, W1C */
-        unsigned long   rh_hcerr             :  1;  /* RW, W1C */
-        unsigned long   xn_hcerr             :  1;  /* RW, W1C */
-        unsigned long   si_hcerr             :  1;  /* RW, W1C */
-        unsigned long   lb_aoerr0            :  1;  /* RW, W1C */
-        unsigned long   gr0_aoerr0           :  1;  /* RW, W1C */
-        unsigned long   gr1_aoerr0           :  1;  /* RW, W1C */
-        unsigned long   lh_aoerr0            :  1;  /* RW, W1C */
-        unsigned long   rh_aoerr0            :  1;  /* RW, W1C */
-        unsigned long   xn_aoerr0            :  1;  /* RW, W1C */
-        unsigned long   si_aoerr0            :  1;  /* RW, W1C */
-        unsigned long   lb_aoerr1            :  1;  /* RW, W1C */
-        unsigned long   gr0_aoerr1           :  1;  /* RW, W1C */
-        unsigned long   gr1_aoerr1           :  1;  /* RW, W1C */
-        unsigned long   lh_aoerr1            :  1;  /* RW, W1C */
-        unsigned long   rh_aoerr1            :  1;  /* RW, W1C */
-        unsigned long   xn_aoerr1            :  1;  /* RW, W1C */
-        unsigned long   si_aoerr1            :  1;  /* RW, W1C */
-        unsigned long   rh_vpi_int           :  1;  /* RW, W1C */
-        unsigned long   system_shutdown_int  :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_0         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_1         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_2         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_3         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_4         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_5         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_6         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_7         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_8         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_9         :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_10        :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_11        :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_12        :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_13        :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_14        :  1;  /* RW, W1C */
-        unsigned long   lb_irq_int_15        :  1;  /* RW, W1C */
-        unsigned long   l1_nmi_int           :  1;  /* RW, W1C */
-        unsigned long   stop_clock           :  1;  /* RW, W1C */
-        unsigned long   asic_to_l1           :  1;  /* RW, W1C */
-        unsigned long   l1_to_asic           :  1;  /* RW, W1C */
-        unsigned long   ltc_int              :  1;  /* RW, W1C */
-        unsigned long   la_seq_trigger       :  1;  /* RW, W1C */
-        unsigned long   ipi_int              :  1;  /* RW, W1C */
-        unsigned long   extio_int0           :  1;  /* RW, W1C */
-        unsigned long   extio_int1           :  1;  /* RW, W1C */
-        unsigned long   extio_int2           :  1;  /* RW, W1C */
-        unsigned long   extio_int3           :  1;  /* RW, W1C */
-        unsigned long   profile_int          :  1;  /* RW, W1C */
-        unsigned long   rtc0                 :  1;  /* RW, W1C */
-        unsigned long   rtc1                 :  1;  /* RW, W1C */
-        unsigned long   rtc2                 :  1;  /* RW, W1C */
-        unsigned long   rtc3                 :  1;  /* RW, W1C */
-        unsigned long   bau_data             :  1;  /* RW, W1C */
-        unsigned long   power_management_req :  1;  /* RW, W1C */
-        unsigned long   rsvd_57_63           :  7;  /*    */
-    } s1;
-    struct uv2h_event_occurred0_s {
-        unsigned long   lb_hcerr            :  1;  /* RW */
-        unsigned long   qp_hcerr            :  1;  /* RW */
-        unsigned long   rh_hcerr            :  1;  /* RW */
-        unsigned long   lh0_hcerr           :  1;  /* RW */
-        unsigned long   lh1_hcerr           :  1;  /* RW */
-        unsigned long   gr0_hcerr           :  1;  /* RW */
-        unsigned long   gr1_hcerr           :  1;  /* RW */
-        unsigned long   ni0_hcerr           :  1;  /* RW */
-        unsigned long   ni1_hcerr           :  1;  /* RW */
-        unsigned long   lb_aoerr0           :  1;  /* RW */
-        unsigned long   qp_aoerr0           :  1;  /* RW */
-        unsigned long   rh_aoerr0           :  1;  /* RW */
-        unsigned long   lh0_aoerr0          :  1;  /* RW */
-        unsigned long   lh1_aoerr0          :  1;  /* RW */
-        unsigned long   gr0_aoerr0          :  1;  /* RW */
-        unsigned long   gr1_aoerr0          :  1;  /* RW */
-        unsigned long   xb_aoerr0           :  1;  /* RW */
-        unsigned long   rt_aoerr0           :  1;  /* RW */
-        unsigned long   ni0_aoerr0          :  1;  /* RW */
-        unsigned long   ni1_aoerr0          :  1;  /* RW */
-        unsigned long   lb_aoerr1           :  1;  /* RW */
-        unsigned long   qp_aoerr1           :  1;  /* RW */
-        unsigned long   rh_aoerr1           :  1;  /* RW */
-        unsigned long   lh0_aoerr1          :  1;  /* RW */
-        unsigned long   lh1_aoerr1          :  1;  /* RW */
-        unsigned long   gr0_aoerr1          :  1;  /* RW */
-        unsigned long   gr1_aoerr1          :  1;  /* RW */
-        unsigned long   xb_aoerr1           :  1;  /* RW */
-        unsigned long   rt_aoerr1           :  1;  /* RW */
-        unsigned long   ni0_aoerr1          :  1;  /* RW */
-        unsigned long   ni1_aoerr1          :  1;  /* RW */
-        unsigned long   system_shutdown_int :  1;  /* RW */
-        unsigned long   lb_irq_int_0        :  1;  /* RW */
-        unsigned long   lb_irq_int_1        :  1;  /* RW */
-        unsigned long   lb_irq_int_2        :  1;  /* RW */
-        unsigned long   lb_irq_int_3        :  1;  /* RW */
-        unsigned long   lb_irq_int_4        :  1;  /* RW */
-        unsigned long   lb_irq_int_5        :  1;  /* RW */
-        unsigned long   lb_irq_int_6        :  1;  /* RW */
-        unsigned long   lb_irq_int_7        :  1;  /* RW */
-        unsigned long   lb_irq_int_8        :  1;  /* RW */
-        unsigned long   lb_irq_int_9        :  1;  /* RW */
-        unsigned long   lb_irq_int_10       :  1;  /* RW */
-        unsigned long   lb_irq_int_11       :  1;  /* RW */
-        unsigned long   lb_irq_int_12       :  1;  /* RW */
-        unsigned long   lb_irq_int_13       :  1;  /* RW */
-        unsigned long   lb_irq_int_14       :  1;  /* RW */
-        unsigned long   lb_irq_int_15       :  1;  /* RW */
-        unsigned long   l1_nmi_int          :  1;  /* RW */
-        unsigned long   stop_clock          :  1;  /* RW */
-        unsigned long   asic_to_l1          :  1;  /* RW */
-        unsigned long   l1_to_asic          :  1;  /* RW */
-        unsigned long   la_seq_trigger      :  1;  /* RW */
-        unsigned long   ipi_int             :  1;  /* RW */
-        unsigned long   extio_int0          :  1;  /* RW */
-        unsigned long   extio_int1          :  1;  /* RW */
-        unsigned long   extio_int2          :  1;  /* RW */
-        unsigned long   extio_int3          :  1;  /* RW */
-        unsigned long   profile_int         :  1;  /* RW */
-        unsigned long   rsvd_59_63          :  5;  /*    */
-    } s2;
+        unsigned long   v;
+        struct uv1h_event_occurred0_s {
+                unsigned long   lb_hcerr:1;                     /* RW, W1C */
+                unsigned long   gr0_hcerr:1;                    /* RW, W1C */
+                unsigned long   gr1_hcerr:1;                    /* RW, W1C */
+                unsigned long   lh_hcerr:1;                     /* RW, W1C */
+                unsigned long   rh_hcerr:1;                     /* RW, W1C */
+                unsigned long   xn_hcerr:1;                     /* RW, W1C */
+                unsigned long   si_hcerr:1;                     /* RW, W1C */
+                unsigned long   lb_aoerr0:1;                    /* RW, W1C */
+                unsigned long   gr0_aoerr0:1;                   /* RW, W1C */
+                unsigned long   gr1_aoerr0:1;                   /* RW, W1C */
+                unsigned long   lh_aoerr0:1;                    /* RW, W1C */
+                unsigned long   rh_aoerr0:1;                    /* RW, W1C */
+                unsigned long   xn_aoerr0:1;                    /* RW, W1C */
+                unsigned long   si_aoerr0:1;                    /* RW, W1C */
+                unsigned long   lb_aoerr1:1;                    /* RW, W1C */
+                unsigned long   gr0_aoerr1:1;                   /* RW, W1C */
+                unsigned long   gr1_aoerr1:1;                   /* RW, W1C */
+                unsigned long   lh_aoerr1:1;                    /* RW, W1C */
+                unsigned long   rh_aoerr1:1;                    /* RW, W1C */
+                unsigned long   xn_aoerr1:1;                    /* RW, W1C */
+                unsigned long   si_aoerr1:1;                    /* RW, W1C */
+                unsigned long   rh_vpi_int:1;                   /* RW, W1C */
+                unsigned long   system_shutdown_int:1;          /* RW, W1C */
+                unsigned long   lb_irq_int_0:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_1:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_2:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_3:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_4:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_5:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_6:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_7:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_8:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_9:1;                 /* RW, W1C */
+                unsigned long   lb_irq_int_10:1;                /* RW, W1C */
+                unsigned long   lb_irq_int_11:1;                /* RW, W1C */
+                unsigned long   lb_irq_int_12:1;                /* RW, W1C */
+                unsigned long   lb_irq_int_13:1;                /* RW, W1C */
+                unsigned long   lb_irq_int_14:1;                /* RW, W1C */
+                unsigned long   lb_irq_int_15:1;                /* RW, W1C */
+                unsigned long   l1_nmi_int:1;                   /* RW, W1C */
+                unsigned long   stop_clock:1;                   /* RW, W1C */
+                unsigned long   asic_to_l1:1;                   /* RW, W1C */
+                unsigned long   l1_to_asic:1;                   /* RW, W1C */
+                unsigned long   ltc_int:1;                      /* RW, W1C */
+                unsigned long   la_seq_trigger:1;               /* RW, W1C */
+                unsigned long   ipi_int:1;                      /* RW, W1C */
+                unsigned long   extio_int0:1;                   /* RW, W1C */
+                unsigned long   extio_int1:1;                   /* RW, W1C */
+                unsigned long   extio_int2:1;                   /* RW, W1C */
+                unsigned long   extio_int3:1;                   /* RW, W1C */
+                unsigned long   profile_int:1;                  /* RW, W1C */
+                unsigned long   rtc0:1;                         /* RW, W1C */
+                unsigned long   rtc1:1;                         /* RW, W1C */
+                unsigned long   rtc2:1;                         /* RW, W1C */
+                unsigned long   rtc3:1;                         /* RW, W1C */
+                unsigned long   bau_data:1;                     /* RW, W1C */
+                unsigned long   power_management_req:1;         /* RW, W1C */
+                unsigned long   rsvd_57_63:7;
+        } s1;
+        struct uv2h_event_occurred0_s {
+                unsigned long   lb_hcerr:1;                     /* RW */
+                unsigned long   qp_hcerr:1;                     /* RW */
+                unsigned long   rh_hcerr:1;                     /* RW */
+                unsigned long   lh0_hcerr:1;                    /* RW */
+                unsigned long   lh1_hcerr:1;                    /* RW */
+                unsigned long   gr0_hcerr:1;                    /* RW */
+                unsigned long   gr1_hcerr:1;                    /* RW */
+                unsigned long   ni0_hcerr:1;                    /* RW */
+                unsigned long   ni1_hcerr:1;                    /* RW */
+                unsigned long   lb_aoerr0:1;                    /* RW */
+                unsigned long   qp_aoerr0:1;                    /* RW */
+                unsigned long   rh_aoerr0:1;                    /* RW */
+                unsigned long   lh0_aoerr0:1;                   /* RW */
+                unsigned long   lh1_aoerr0:1;                   /* RW */
+                unsigned long   gr0_aoerr0:1;                   /* RW */
+                unsigned long   gr1_aoerr0:1;                   /* RW */
+                unsigned long   xb_aoerr0:1;                    /* RW */
+                unsigned long   rt_aoerr0:1;                    /* RW */
+                unsigned long   ni0_aoerr0:1;                   /* RW */
+                unsigned long   ni1_aoerr0:1;                   /* RW */
+                unsigned long   lb_aoerr1:1;                    /* RW */
+                unsigned long   qp_aoerr1:1;                    /* RW */
+                unsigned long   rh_aoerr1:1;                    /* RW */
+                unsigned long   lh0_aoerr1:1;                   /* RW */
+                unsigned long   lh1_aoerr1:1;                   /* RW */
+                unsigned long   gr0_aoerr1:1;                   /* RW */
+                unsigned long   gr1_aoerr1:1;                   /* RW */
+                unsigned long   xb_aoerr1:1;                    /* RW */
+                unsigned long   rt_aoerr1:1;                    /* RW */
+                unsigned long   ni0_aoerr1:1;                   /* RW */
+                unsigned long   ni1_aoerr1:1;                   /* RW */
+                unsigned long   system_shutdown_int:1;          /* RW */
+                unsigned long   lb_irq_int_0:1;                 /* RW */
+                unsigned long   lb_irq_int_1:1;                 /* RW */
+                unsigned long   lb_irq_int_2:1;                 /* RW */
+                unsigned long   lb_irq_int_3:1;                 /* RW */
+                unsigned long   lb_irq_int_4:1;                 /* RW */
+                unsigned long   lb_irq_int_5:1;                 /* RW */
+                unsigned long   lb_irq_int_6:1;                 /* RW */
+                unsigned long   lb_irq_int_7:1;                 /* RW */
+                unsigned long   lb_irq_int_8:1;                 /* RW */
+                unsigned long   lb_irq_int_9:1;                 /* RW */
+                unsigned long   lb_irq_int_10:1;                /* RW */
+                unsigned long   lb_irq_int_11:1;                /* RW */
+                unsigned long   lb_irq_int_12:1;                /* RW */
+                unsigned long   lb_irq_int_13:1;                /* RW */
+                unsigned long   lb_irq_int_14:1;                /* RW */
+                unsigned long   lb_irq_int_15:1;                /* RW */
+                unsigned long   l1_nmi_int:1;                   /* RW */
+                unsigned long   stop_clock:1;                   /* RW */
+                unsigned long   asic_to_l1:1;                   /* RW */
+                unsigned long   l1_to_asic:1;                   /* RW */
+                unsigned long   la_seq_trigger:1;               /* RW */
+                unsigned long   ipi_int:1;                      /* RW */
+                unsigned long   extio_int0:1;                   /* RW */
+                unsigned long   extio_int1:1;                   /* RW */
+                unsigned long   extio_int2:1;                   /* RW */
+                unsigned long   extio_int3:1;                   /* RW */
+                unsigned long   profile_int:1;                  /* RW */
+                unsigned long   rsvd_59_63:5;
+        } s2;
 };
 
 /* ========================================================================= */
 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
 /* ========================================================================= */
-#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
-#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
+#define UVH_EVENT_OCCURRED0_ALIAS                       0x0000000000070008UL
+#define UVH_EVENT_OCCURRED0_ALIAS_32                    0x5f0
 
 /* ========================================================================= */
 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
 /* ========================================================================= */
-#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
-
-#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
-#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
-#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
-#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
-#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
-#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
-#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
-#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
-#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+#define UVH_GR0_TLB_INT0_CONFIG                         0x61b00UL
+
+#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT             0
+#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT                 8
+#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT           11
+#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT             12
+#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT                  13
+#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT                  15
+#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT                  16
+#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT            32
+#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
+#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
+#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
+#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
+#define UVH_GR0_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
+#define UVH_GR0_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
+#define UVH_GR0_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
+#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
 union uvh_gr0_tlb_int0_config_u {
-    unsigned long       v;
-    struct uvh_gr0_tlb_int0_config_s {
-        unsigned long   vector_  :  8;  /* RW */
-        unsigned long   dm       :  3;  /* RW */
-        unsigned long   destmode :  1;  /* RW */
-        unsigned long   status   :  1;  /* RO */
-        unsigned long   p        :  1;  /* RO */
-        unsigned long   rsvd_14  :  1;  /*    */
-        unsigned long   t        :  1;  /* RO */
-        unsigned long   m        :  1;  /* RW */
-        unsigned long   rsvd_17_31: 15;  /*    */
-        unsigned long   apic_id  : 32;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_gr0_tlb_int0_config_s {
+                unsigned long   vector_:8;                      /* RW */
+                unsigned long   dm:3;                           /* RW */
+                unsigned long   destmode:1;                     /* RW */
+                unsigned long   status:1;                       /* RO */
+                unsigned long   p:1;                            /* RO */
+                unsigned long   rsvd_14:1;
+                unsigned long   t:1;                            /* RO */
+                unsigned long   m:1;                            /* RW */
+                unsigned long   rsvd_17_31:15;
+                unsigned long   apic_id:32;                     /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
 /* ========================================================================= */
-#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
-
-#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
-#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
-#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
-#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
-#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
-#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
-#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
-#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
-#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+#define UVH_GR0_TLB_INT1_CONFIG                         0x61b40UL
+
+#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT             0
+#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT                 8
+#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT           11
+#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT             12
+#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT                  13
+#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT                  15
+#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT                  16
+#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT            32
+#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
+#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
+#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
+#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
+#define UVH_GR0_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
+#define UVH_GR0_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
+#define UVH_GR0_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
+#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
 union uvh_gr0_tlb_int1_config_u {
-    unsigned long       v;
-    struct uvh_gr0_tlb_int1_config_s {
-        unsigned long   vector_  :  8;  /* RW */
-        unsigned long   dm       :  3;  /* RW */
-        unsigned long   destmode :  1;  /* RW */
-        unsigned long   status   :  1;  /* RO */
-        unsigned long   p        :  1;  /* RO */
-        unsigned long   rsvd_14  :  1;  /*    */
-        unsigned long   t        :  1;  /* RO */
-        unsigned long   m        :  1;  /* RW */
-        unsigned long   rsvd_17_31: 15;  /*    */
-        unsigned long   apic_id  : 32;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_gr0_tlb_int1_config_s {
+                unsigned long   vector_:8;                      /* RW */
+                unsigned long   dm:3;                           /* RW */
+                unsigned long   destmode:1;                     /* RW */
+                unsigned long   status:1;                       /* RO */
+                unsigned long   p:1;                            /* RO */
+                unsigned long   rsvd_14:1;
+                unsigned long   t:1;                            /* RO */
+                unsigned long   m:1;                            /* RW */
+                unsigned long   rsvd_17_31:15;
+                unsigned long   apic_id:32;                     /* RW */
+        } s;
+};
+
+/* ========================================================================= */
+/*                         UVH_GR0_TLB_MMR_CONTROL                           */
+/* ========================================================================= */
+#define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
+#define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
+#define UVH_GR0_TLB_MMR_CONTROL (is_uv1_hub() ?                         \
+                        UV1H_GR0_TLB_MMR_CONTROL :                      \
+                        UV2H_GR0_TLB_MMR_CONTROL)
+
+#define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT              0
+#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
+#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
+#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
+#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
+#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT           31
+#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
+#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
+#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
+#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
+#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
+#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
+
+#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
+#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
+#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
+#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
+#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
+#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
+
+#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT             0
+#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
+#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT          31
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
+#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
+#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
+#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
+#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
+
+union uvh_gr0_tlb_mmr_control_u {
+        unsigned long   v;
+        struct uvh_gr0_tlb_mmr_control_s {
+                unsigned long   index:12;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_14_15:2;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   rsvd_21_29:9;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   rsvd_32_63:32;
+        } s;
+        struct uv1h_gr0_tlb_mmr_control_s {
+                unsigned long   index:12;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_14_15:2;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   rsvd_21_29:9;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   rsvd_32_47:16;
+                unsigned long   mmr_inj_con:1;                  /* RW */
+                unsigned long   rsvd_49_51:3;
+                unsigned long   mmr_inj_tlbram:1;               /* RW */
+                unsigned long   rsvd_53:1;
+                unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
+                unsigned long   rsvd_55:1;
+                unsigned long   mmr_inj_tlbrreg:1;              /* RW */
+                unsigned long   rsvd_57_59:3;
+                unsigned long   mmr_inj_tlblruv:1;              /* RW */
+                unsigned long   rsvd_61_63:3;
+        } s1;
+        struct uv2h_gr0_tlb_mmr_control_s {
+                unsigned long   index:12;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_14_15:2;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   rsvd_21_29:9;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   mmr_op_done:1;                  /* RW */
+                unsigned long   rsvd_33_47:15;
+                unsigned long   mmr_inj_con:1;                  /* RW */
+                unsigned long   rsvd_49_51:3;
+                unsigned long   mmr_inj_tlbram:1;               /* RW */
+                unsigned long   rsvd_53_63:11;
+        } s2;
+};
+
+/* ========================================================================= */
+/*                       UVH_GR0_TLB_MMR_READ_DATA_HI                        */
+/* ========================================================================= */
+#define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
+#define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
+#define UVH_GR0_TLB_MMR_READ_DATA_HI (is_uv1_hub() ?                    \
+                        UV1H_GR0_TLB_MMR_READ_DATA_HI :                 \
+                        UV2H_GR0_TLB_MMR_READ_DATA_HI)
+
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
+#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
+
+union uvh_gr0_tlb_mmr_read_data_hi_u {
+        unsigned long   v;
+        struct uvh_gr0_tlb_mmr_read_data_hi_s {
+                unsigned long   pfn:41;                         /* RO */
+                unsigned long   gaa:2;                          /* RO */
+                unsigned long   dirty:1;                        /* RO */
+                unsigned long   larger:1;                       /* RO */
+                unsigned long   rsvd_45_63:19;
+        } s;
+};
+
+/* ========================================================================= */
+/*                       UVH_GR0_TLB_MMR_READ_DATA_LO                        */
+/* ========================================================================= */
+#define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
+#define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
+#define UVH_GR0_TLB_MMR_READ_DATA_LO (is_uv1_hub() ?                    \
+                        UV1H_GR0_TLB_MMR_READ_DATA_LO :                 \
+                        UV2H_GR0_TLB_MMR_READ_DATA_LO)
+
+#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
+#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
+#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
+#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
+#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
+#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
+
+union uvh_gr0_tlb_mmr_read_data_lo_u {
+        unsigned long   v;
+        struct uvh_gr0_tlb_mmr_read_data_lo_s {
+                unsigned long   vpn:39;                         /* RO */
+                unsigned long   asid:24;                        /* RO */
+                unsigned long   valid:1;                        /* RO */
+        } s;
 };
 
 /* ========================================================================= */
 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
 /* ========================================================================= */
-#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
-
-#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
-#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
-#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
-#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
-#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
-#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
-#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
-#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
-#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+#define UVH_GR1_TLB_INT0_CONFIG                         0x61f00UL
+
+#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT             0
+#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT                 8
+#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT           11
+#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT             12
+#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT                  13
+#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT                  15
+#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT                  16
+#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT            32
+#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK             0x00000000000000ffUL
+#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK                 0x0000000000000700UL
+#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK           0x0000000000000800UL
+#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK             0x0000000000001000UL
+#define UVH_GR1_TLB_INT0_CONFIG_P_MASK                  0x0000000000002000UL
+#define UVH_GR1_TLB_INT0_CONFIG_T_MASK                  0x0000000000008000UL
+#define UVH_GR1_TLB_INT0_CONFIG_M_MASK                  0x0000000000010000UL
+#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
 union uvh_gr1_tlb_int0_config_u {
-    unsigned long       v;
-    struct uvh_gr1_tlb_int0_config_s {
-        unsigned long   vector_  :  8;  /* RW */
-        unsigned long   dm       :  3;  /* RW */
-        unsigned long   destmode :  1;  /* RW */
-        unsigned long   status   :  1;  /* RO */
-        unsigned long   p        :  1;  /* RO */
-        unsigned long   rsvd_14  :  1;  /*    */
-        unsigned long   t        :  1;  /* RO */
-        unsigned long   m        :  1;  /* RW */
-        unsigned long   rsvd_17_31: 15;  /*    */
-        unsigned long   apic_id  : 32;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_gr1_tlb_int0_config_s {
+                unsigned long   vector_:8;                      /* RW */
+                unsigned long   dm:3;                           /* RW */
+                unsigned long   destmode:1;                     /* RW */
+                unsigned long   status:1;                       /* RO */
+                unsigned long   p:1;                            /* RO */
+                unsigned long   rsvd_14:1;
+                unsigned long   t:1;                            /* RO */
+                unsigned long   m:1;                            /* RW */
+                unsigned long   rsvd_17_31:15;
+                unsigned long   apic_id:32;                     /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
 /* ========================================================================= */
-#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
-
-#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
-#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
-#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
-#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
-#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
-#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
-#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
-#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
-#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+#define UVH_GR1_TLB_INT1_CONFIG                         0x61f40UL
+
+#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT             0
+#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT                 8
+#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT           11
+#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT             12
+#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT                  13
+#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT                  15
+#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT                  16
+#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT            32
+#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK             0x00000000000000ffUL
+#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK                 0x0000000000000700UL
+#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK           0x0000000000000800UL
+#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK             0x0000000000001000UL
+#define UVH_GR1_TLB_INT1_CONFIG_P_MASK                  0x0000000000002000UL
+#define UVH_GR1_TLB_INT1_CONFIG_T_MASK                  0x0000000000008000UL
+#define UVH_GR1_TLB_INT1_CONFIG_M_MASK                  0x0000000000010000UL
+#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK            0xffffffff00000000UL
 
 union uvh_gr1_tlb_int1_config_u {
-    unsigned long       v;
-    struct uvh_gr1_tlb_int1_config_s {
-        unsigned long   vector_  :  8;  /* RW */
-        unsigned long   dm       :  3;  /* RW */
-        unsigned long   destmode :  1;  /* RW */
-        unsigned long   status   :  1;  /* RO */
-        unsigned long   p        :  1;  /* RO */
-        unsigned long   rsvd_14  :  1;  /*    */
-        unsigned long   t        :  1;  /* RO */
-        unsigned long   m        :  1;  /* RW */
-        unsigned long   rsvd_17_31: 15;  /*    */
-        unsigned long   apic_id  : 32;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_gr1_tlb_int1_config_s {
+                unsigned long   vector_:8;                      /* RW */
+                unsigned long   dm:3;                           /* RW */
+                unsigned long   destmode:1;                     /* RW */
+                unsigned long   status:1;                       /* RO */
+                unsigned long   p:1;                            /* RO */
+                unsigned long   rsvd_14:1;
+                unsigned long   t:1;                            /* RO */
+                unsigned long   m:1;                            /* RW */
+                unsigned long   rsvd_17_31:15;
+                unsigned long   apic_id:32;                     /* RW */
+        } s;
+};
+
+/* ========================================================================= */
+/*                         UVH_GR1_TLB_MMR_CONTROL                           */
+/* ========================================================================= */
+#define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
+#define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
+#define UVH_GR1_TLB_MMR_CONTROL (is_uv1_hub() ?                         \
+                        UV1H_GR1_TLB_MMR_CONTROL :                      \
+                        UV2H_GR1_TLB_MMR_CONTROL)
+
+#define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT              0
+#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT            12
+#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT      16
+#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT  20
+#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT          30
+#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT           31
+#define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK              0x0000000000000fffUL
+#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK            0x0000000000003000UL
+#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK      0x0000000000010000UL
+#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK  0x0000000000100000UL
+#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK          0x0000000040000000UL
+#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK           0x0000000080000000UL
+
+#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
+#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
+#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT   56
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT   60
+#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
+#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK   0x0100000000000000UL
+#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK   0x1000000000000000UL
+
+#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT             0
+#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT           12
+#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT     16
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT         30
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT          31
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT       32
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT       48
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT    52
+#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK             0x0000000000000fffUL
+#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK           0x0000000000003000UL
+#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK     0x0000000000010000UL
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK         0x0000000040000000UL
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK          0x0000000080000000UL
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK       0x0000000100000000UL
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK       0x0001000000000000UL
+#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK    0x0010000000000000UL
+
+union uvh_gr1_tlb_mmr_control_u {
+        unsigned long   v;
+        struct uvh_gr1_tlb_mmr_control_s {
+                unsigned long   index:12;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_14_15:2;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   rsvd_21_29:9;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   rsvd_32_63:32;
+        } s;
+        struct uv1h_gr1_tlb_mmr_control_s {
+                unsigned long   index:12;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_14_15:2;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   rsvd_21_29:9;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   rsvd_32_47:16;
+                unsigned long   mmr_inj_con:1;                  /* RW */
+                unsigned long   rsvd_49_51:3;
+                unsigned long   mmr_inj_tlbram:1;               /* RW */
+                unsigned long   rsvd_53:1;
+                unsigned long   mmr_inj_tlbpgsize:1;            /* RW */
+                unsigned long   rsvd_55:1;
+                unsigned long   mmr_inj_tlbrreg:1;              /* RW */
+                unsigned long   rsvd_57_59:3;
+                unsigned long   mmr_inj_tlblruv:1;              /* RW */
+                unsigned long   rsvd_61_63:3;
+        } s1;
+        struct uv2h_gr1_tlb_mmr_control_s {
+                unsigned long   index:12;                       /* RW */
+                unsigned long   mem_sel:2;                      /* RW */
+                unsigned long   rsvd_14_15:2;
+                unsigned long   auto_valid_en:1;                /* RW */
+                unsigned long   rsvd_17_19:3;
+                unsigned long   mmr_hash_index_en:1;            /* RW */
+                unsigned long   rsvd_21_29:9;
+                unsigned long   mmr_write:1;                    /* WP */
+                unsigned long   mmr_read:1;                     /* WP */
+                unsigned long   mmr_op_done:1;                  /* RW */
+                unsigned long   rsvd_33_47:15;
+                unsigned long   mmr_inj_con:1;                  /* RW */
+                unsigned long   rsvd_49_51:3;
+                unsigned long   mmr_inj_tlbram:1;               /* RW */
+                unsigned long   rsvd_53_63:11;
+        } s2;
+};
+
+/* ========================================================================= */
+/*                       UVH_GR1_TLB_MMR_READ_DATA_HI                        */
+/* ========================================================================= */
+#define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
+#define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
+#define UVH_GR1_TLB_MMR_READ_DATA_HI (is_uv1_hub() ?                    \
+                        UV1H_GR1_TLB_MMR_READ_DATA_HI :                 \
+                        UV2H_GR1_TLB_MMR_READ_DATA_HI)
+
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT           0
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT           41
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT         43
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT        44
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK           0x000001ffffffffffUL
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK           0x0000060000000000UL
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK         0x0000080000000000UL
+#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK        0x0000100000000000UL
+
+union uvh_gr1_tlb_mmr_read_data_hi_u {
+        unsigned long   v;
+        struct uvh_gr1_tlb_mmr_read_data_hi_s {
+                unsigned long   pfn:41;                         /* RO */
+                unsigned long   gaa:2;                          /* RO */
+                unsigned long   dirty:1;                        /* RO */
+                unsigned long   larger:1;                       /* RO */
+                unsigned long   rsvd_45_63:19;
+        } s;
+};
+
+/* ========================================================================= */
+/*                       UVH_GR1_TLB_MMR_READ_DATA_LO                        */
+/* ========================================================================= */
+#define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
+#define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
+#define UVH_GR1_TLB_MMR_READ_DATA_LO (is_uv1_hub() ?                    \
+                        UV1H_GR1_TLB_MMR_READ_DATA_LO :                 \
+                        UV2H_GR1_TLB_MMR_READ_DATA_LO)
+
+#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT           0
+#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT          39
+#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT         63
+#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK           0x0000007fffffffffUL
+#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK          0x7fffff8000000000UL
+#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK         0x8000000000000000UL
+
+union uvh_gr1_tlb_mmr_read_data_lo_u {
+        unsigned long   v;
+        struct uvh_gr1_tlb_mmr_read_data_lo_s {
+                unsigned long   vpn:39;                         /* RO */
+                unsigned long   asid:24;                        /* RO */
+                unsigned long   valid:1;                        /* RO */
+        } s;
 };
 
 /* ========================================================================= */
 /*                               UVH_INT_CMPB                                */
 /* ========================================================================= */
-#define UVH_INT_CMPB 0x22080UL
+#define UVH_INT_CMPB                                    0x22080UL
 
-#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
-#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
+#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT                0
+#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK                0x00ffffffffffffffUL
 
 union uvh_int_cmpb_u {
-    unsigned long       v;
-    struct uvh_int_cmpb_s {
-        unsigned long   real_time_cmpb : 56;  /* RW */
-        unsigned long   rsvd_56_63     :  8;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_int_cmpb_s {
+                unsigned long   real_time_cmpb:56;              /* RW */
+                unsigned long   rsvd_56_63:8;
+        } s;
 };
 
 /* ========================================================================= */
 /*                               UVH_INT_CMPC                                */
 /* ========================================================================= */
-#define UVH_INT_CMPC 0x22100UL
+#define UVH_INT_CMPC                                    0x22100UL
 
-#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT       0
-#define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT       0
-#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT        (is_uv1_hub() ?         \
-                        UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT :     \
-                        UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT)
-#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK       0xffffffffffffffUL
-#define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK       0xffffffffffffffUL
-#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK        (is_uv1_hub() ?         \
-                        UV1H_INT_CMPC_REAL_TIME_CMPC_MASK :     \
-                        UV2H_INT_CMPC_REAL_TIME_CMPC_MASK)
+#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT                0
+#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK                0xffffffffffffffUL
 
 union uvh_int_cmpc_u {
-    unsigned long       v;
-    struct uvh_int_cmpc_s {
-        unsigned long   real_time_cmpc : 56;  /* RW */
-        unsigned long   rsvd_56_63     :  8;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_int_cmpc_s {
+                unsigned long   real_time_cmpc:56;              /* RW */
+                unsigned long   rsvd_56_63:8;
+        } s;
 };
 
 /* ========================================================================= */
 /*                               UVH_INT_CMPD                                */
 /* ========================================================================= */
-#define UVH_INT_CMPD 0x22180UL
+#define UVH_INT_CMPD                                    0x22180UL
 
-#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT       0
-#define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT       0
-#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT        (is_uv1_hub() ?         \
-                        UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT :     \
-                        UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT)
-#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK       0xffffffffffffffUL
-#define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK       0xffffffffffffffUL
-#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK        (is_uv1_hub() ?         \
-                        UV1H_INT_CMPD_REAL_TIME_CMPD_MASK :     \
-                        UV2H_INT_CMPD_REAL_TIME_CMPD_MASK)
+#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT                0
+#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK                0xffffffffffffffUL
 
 union uvh_int_cmpd_u {
-    unsigned long       v;
-    struct uvh_int_cmpd_s {
-        unsigned long   real_time_cmpd : 56;  /* RW */
-        unsigned long   rsvd_56_63     :  8;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_int_cmpd_s {
+                unsigned long   real_time_cmpd:56;              /* RW */
+                unsigned long   rsvd_56_63:8;
+        } s;
 };
 
 /* ========================================================================= */
 /*                               UVH_IPI_INT                                 */
 /* ========================================================================= */
-#define UVH_IPI_INT 0x60500UL
-#define UVH_IPI_INT_32 0x348
+#define UVH_IPI_INT                                     0x60500UL
+#define UVH_IPI_INT_32                                  0x348
 
-#define UVH_IPI_INT_VECTOR_SHFT 0
-#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
-#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
-#define UVH_IPI_INT_DESTMODE_SHFT 11
-#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_IPI_INT_APIC_ID_SHFT 16
-#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
-#define UVH_IPI_INT_SEND_SHFT 63
-#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
+#define UVH_IPI_INT_VECTOR_SHFT                         0
+#define UVH_IPI_INT_DELIVERY_MODE_SHFT                  8
+#define UVH_IPI_INT_DESTMODE_SHFT                       11
+#define UVH_IPI_INT_APIC_ID_SHFT                        16
+#define UVH_IPI_INT_SEND_SHFT                           63
+#define UVH_IPI_INT_VECTOR_MASK                         0x00000000000000ffUL
+#define UVH_IPI_INT_DELIVERY_MODE_MASK                  0x0000000000000700UL
+#define UVH_IPI_INT_DESTMODE_MASK                       0x0000000000000800UL
+#define UVH_IPI_INT_APIC_ID_MASK                        0x0000ffffffff0000UL
+#define UVH_IPI_INT_SEND_MASK                           0x8000000000000000UL
 
 union uvh_ipi_int_u {
-    unsigned long       v;
-    struct uvh_ipi_int_s {
-        unsigned long   vector_       :  8;  /* RW */
-        unsigned long   delivery_mode :  3;  /* RW */
-        unsigned long   destmode      :  1;  /* RW */
-        unsigned long   rsvd_12_15    :  4;  /*    */
-        unsigned long   apic_id       : 32;  /* RW */
-        unsigned long   rsvd_48_62    : 15;  /*    */
-        unsigned long   send          :  1;  /* WP */
-    } s;
+        unsigned long   v;
+        struct uvh_ipi_int_s {
+                unsigned long   vector_:8;                      /* RW */
+                unsigned long   delivery_mode:3;                /* RW */
+                unsigned long   destmode:1;                     /* RW */
+                unsigned long   rsvd_12_15:4;
+                unsigned long   apic_id:32;                     /* RW */
+                unsigned long   rsvd_48_62:15;
+                unsigned long   send:1;                         /* WP */
+        } s;
 };
 
 /* ========================================================================= */
 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST             0x320050UL
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32          0x9c0
 
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
 
 union uvh_lb_bau_intd_payload_queue_first_u {
-    unsigned long       v;
-    struct uvh_lb_bau_intd_payload_queue_first_s {
-        unsigned long   rsvd_0_3:  4;  /*    */
-        unsigned long   address : 39;  /* RW */
-        unsigned long   rsvd_43_48:  6;  /*    */
-        unsigned long   node_id : 14;  /* RW */
-        unsigned long   rsvd_63 :  1;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_intd_payload_queue_first_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_48:6;
+                unsigned long   node_id:14;                     /* RW */
+                unsigned long   rsvd_63:1;
+        } s;
 };
 
 /* ========================================================================= */
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST              0x320060UL
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32           0x9c8
 
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
 
 union uvh_lb_bau_intd_payload_queue_last_u {
-    unsigned long       v;
-    struct uvh_lb_bau_intd_payload_queue_last_s {
-        unsigned long   rsvd_0_3:  4;  /*    */
-        unsigned long   address : 39;  /* RW */
-        unsigned long   rsvd_43_63: 21;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_intd_payload_queue_last_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_63:21;
+        } s;
 };
 
 /* ========================================================================= */
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL              0x320070UL
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32           0x9d0
 
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
 
 union uvh_lb_bau_intd_payload_queue_tail_u {
-    unsigned long       v;
-    struct uvh_lb_bau_intd_payload_queue_tail_s {
-        unsigned long   rsvd_0_3:  4;  /*    */
-        unsigned long   address : 39;  /* RW */
-        unsigned long   rsvd_43_63: 21;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_intd_payload_queue_tail_s {
+                unsigned long   rsvd_0_3:4;
+                unsigned long   address:39;                     /* RW */
+                unsigned long   rsvd_43_63:21;
+        } s;
 };
 
 /* ========================================================================= */
 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE            0x320080UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32         0xa68
 
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
 
 union uvh_lb_bau_intd_software_acknowledge_u {
-    unsigned long       v;
-    struct uvh_lb_bau_intd_software_acknowledge_s {
-        unsigned long   pending_0 :  1;  /* RW, W1C */
-        unsigned long   pending_1 :  1;  /* RW, W1C */
-        unsigned long   pending_2 :  1;  /* RW, W1C */
-        unsigned long   pending_3 :  1;  /* RW, W1C */
-        unsigned long   pending_4 :  1;  /* RW, W1C */
-        unsigned long   pending_5 :  1;  /* RW, W1C */
-        unsigned long   pending_6 :  1;  /* RW, W1C */
-        unsigned long   pending_7 :  1;  /* RW, W1C */
-        unsigned long   timeout_0 :  1;  /* RW, W1C */
-        unsigned long   timeout_1 :  1;  /* RW, W1C */
-        unsigned long   timeout_2 :  1;  /* RW, W1C */
-        unsigned long   timeout_3 :  1;  /* RW, W1C */
-        unsigned long   timeout_4 :  1;  /* RW, W1C */
-        unsigned long   timeout_5 :  1;  /* RW, W1C */
-        unsigned long   timeout_6 :  1;  /* RW, W1C */
-        unsigned long   timeout_7 :  1;  /* RW, W1C */
-        unsigned long   rsvd_16_63: 48;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_intd_software_acknowledge_s {
+                unsigned long   pending_0:1;                    /* RW, W1C */
+                unsigned long   pending_1:1;                    /* RW, W1C */
+                unsigned long   pending_2:1;                    /* RW, W1C */
+                unsigned long   pending_3:1;                    /* RW, W1C */
+                unsigned long   pending_4:1;                    /* RW, W1C */
+                unsigned long   pending_5:1;                    /* RW, W1C */
+                unsigned long   pending_6:1;                    /* RW, W1C */
+                unsigned long   pending_7:1;                    /* RW, W1C */
+                unsigned long   timeout_0:1;                    /* RW, W1C */
+                unsigned long   timeout_1:1;                    /* RW, W1C */
+                unsigned long   timeout_2:1;                    /* RW, W1C */
+                unsigned long   timeout_3:1;                    /* RW, W1C */
+                unsigned long   timeout_4:1;                    /* RW, W1C */
+                unsigned long   timeout_5:1;                    /* RW, W1C */
+                unsigned long   timeout_6:1;                    /* RW, W1C */
+                unsigned long   timeout_7:1;                    /* RW, W1C */
+                unsigned long   rsvd_16_63:48;
+        } s;
 };
 
 /* ========================================================================= */
 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 /* ========================================================================= */
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS      0x0000000000320088UL
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32   0xa70
 
 /* ========================================================================= */
 /*                         UVH_LB_BAU_MISC_CONTROL                           */
 /* ========================================================================= */
-#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
-#define UVH_LB_BAU_MISC_CONTROL_32 0xa10
-
-#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
-#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
-#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
-#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
+#define UVH_LB_BAU_MISC_CONTROL                         0x320170UL
+#define UVH_LB_BAU_MISC_CONTROL_32                      0xa10
+
+#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT    0
+#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT          8
+#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT    9
+#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT     10
 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
-#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
-#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
-#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
-#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
-#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
-#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
-#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
-#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
+#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK    0x00000000000000ffUL
+#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK          0x0000000000000100UL
+#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK    0x0000000000000200UL
+#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK     0x0000000000000400UL
+#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
+#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
+#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
+#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
+#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
+#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
+#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
+#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
+#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
+#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
 
-#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
-#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
-#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
-#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
+#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
+#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
-#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
-#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
-#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
-#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
-#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
-#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
-#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
-#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
+#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
+#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
+#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
+#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
+#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
+#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
+#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
+#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
+#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
+#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
+#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
-#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
-#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
-
-#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
-#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
+#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
+
+#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT   0
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT         8
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT   9
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT    10
 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
-#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
-#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
-#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
-#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
-#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
-#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
-#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT  30
 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
+#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT               48
+#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK   0x00000000000000ffUL
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK         0x0000000000000100UL
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK   0x0000000000000200UL
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK    0x0000000000000400UL
+#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
+#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
+#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
+#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
+#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
+#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK  0x0000000040000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
-#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
-#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK               0xffff000000000000UL
 
 union uvh_lb_bau_misc_control_u {
-    unsigned long       v;
-    struct uvh_lb_bau_misc_control_s {
-        unsigned long   rejection_delay                    :  8;  /* RW */
-        unsigned long   apic_mode                          :  1;  /* RW */
-        unsigned long   force_broadcast                    :  1;  /* RW */
-        unsigned long   force_lock_nop                     :  1;  /* RW */
-        unsigned long   qpi_agent_presence_vector          :  3;  /* RW */
-        unsigned long   descriptor_fetch_mode              :  1;  /* RW */
-        unsigned long   enable_intd_soft_ack_mode          :  1;  /* RW */
-        unsigned long   intd_soft_ack_timeout_period       :  4;  /* RW */
-        unsigned long   enable_dual_mapping_mode           :  1;  /* RW */
-        unsigned long   vga_io_port_decode_enable          :  1;  /* RW */
-        unsigned long   vga_io_port_16_bit_decode          :  1;  /* RW */
-        unsigned long   suppress_dest_registration         :  1;  /* RW */
-        unsigned long   programmed_initial_priority        :  3;  /* RW */
-        unsigned long   use_incoming_priority              :  1;  /* RW */
-        unsigned long   enable_programmed_initial_priority :  1;  /* RW */
-        unsigned long   rsvd_29_63    : 35;
-    } s;
-    struct uv1h_lb_bau_misc_control_s {
-        unsigned long   rejection_delay                    :  8;  /* RW */
-        unsigned long   apic_mode                          :  1;  /* RW */
-        unsigned long   force_broadcast                    :  1;  /* RW */
-        unsigned long   force_lock_nop                     :  1;  /* RW */
-        unsigned long   qpi_agent_presence_vector          :  3;  /* RW */
-        unsigned long   descriptor_fetch_mode              :  1;  /* RW */
-        unsigned long   enable_intd_soft_ack_mode          :  1;  /* RW */
-        unsigned long   intd_soft_ack_timeout_period       :  4;  /* RW */
-        unsigned long   enable_dual_mapping_mode           :  1;  /* RW */
-        unsigned long   vga_io_port_decode_enable          :  1;  /* RW */
-        unsigned long   vga_io_port_16_bit_decode          :  1;  /* RW */
-        unsigned long   suppress_dest_registration         :  1;  /* RW */
-        unsigned long   programmed_initial_priority        :  3;  /* RW */
-        unsigned long   use_incoming_priority              :  1;  /* RW */
-        unsigned long   enable_programmed_initial_priority :  1;  /* RW */
-        unsigned long   rsvd_29_47                         : 19;  /*    */
-        unsigned long   fun                                : 16;  /* RW */
-    } s1;
-    struct uv2h_lb_bau_misc_control_s {
-        unsigned long   rejection_delay                      :  8;  /* RW */
-        unsigned long   apic_mode                            :  1;  /* RW */
-        unsigned long   force_broadcast                      :  1;  /* RW */
-        unsigned long   force_lock_nop                       :  1;  /* RW */
-        unsigned long   qpi_agent_presence_vector            :  3;  /* RW */
-        unsigned long   descriptor_fetch_mode                :  1;  /* RW */
-        unsigned long   enable_intd_soft_ack_mode            :  1;  /* RW */
-        unsigned long   intd_soft_ack_timeout_period         :  4;  /* RW */
-        unsigned long   enable_dual_mapping_mode             :  1;  /* RW */
-        unsigned long   vga_io_port_decode_enable            :  1;  /* RW */
-        unsigned long   vga_io_port_16_bit_decode            :  1;  /* RW */
-        unsigned long   suppress_dest_registration           :  1;  /* RW */
-        unsigned long   programmed_initial_priority          :  3;  /* RW */
-        unsigned long   use_incoming_priority                :  1;  /* RW */
-        unsigned long   enable_programmed_initial_priority   :  1;  /* RW */
-        unsigned long   enable_automatic_apic_mode_selection :  1;  /* RW */
-        unsigned long   apic_mode_status                     :  1;  /* RO */
-        unsigned long   suppress_interrupts_to_self          :  1;  /* RW */
-        unsigned long   enable_lock_based_system_flush       :  1;  /* RW */
-        unsigned long   enable_extended_sb_status            :  1;  /* RW */
-        unsigned long   suppress_int_prio_udt_to_self        :  1;  /* RW */
-        unsigned long   use_legacy_descriptor_formats        :  1;  /* RW */
-        unsigned long   rsvd_36_47                           : 12;  /*    */
-        unsigned long   fun                                  : 16;  /* RW */
-    } s2;
+        unsigned long   v;
+        struct uvh_lb_bau_misc_control_s {
+                unsigned long   rejection_delay:8;              /* RW */
+                unsigned long   apic_mode:1;                    /* RW */
+                unsigned long   force_broadcast:1;              /* RW */
+                unsigned long   force_lock_nop:1;               /* RW */
+                unsigned long   qpi_agent_presence_vector:3;    /* RW */
+                unsigned long   descriptor_fetch_mode:1;        /* RW */
+                unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
+                unsigned long   intd_soft_ack_timeout_period:4; /* RW */
+                unsigned long   enable_dual_mapping_mode:1;     /* RW */
+                unsigned long   vga_io_port_decode_enable:1;    /* RW */
+                unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
+                unsigned long   suppress_dest_registration:1;   /* RW */
+                unsigned long   programmed_initial_priority:3;  /* RW */
+                unsigned long   use_incoming_priority:1;        /* RW */
+                unsigned long   enable_programmed_initial_priority:1;/* RW */
+                unsigned long   rsvd_29_63:35;
+        } s;
+        struct uv1h_lb_bau_misc_control_s {
+                unsigned long   rejection_delay:8;              /* RW */
+                unsigned long   apic_mode:1;                    /* RW */
+                unsigned long   force_broadcast:1;              /* RW */
+                unsigned long   force_lock_nop:1;               /* RW */
+                unsigned long   qpi_agent_presence_vector:3;    /* RW */
+                unsigned long   descriptor_fetch_mode:1;        /* RW */
+                unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
+                unsigned long   intd_soft_ack_timeout_period:4; /* RW */
+                unsigned long   enable_dual_mapping_mode:1;     /* RW */
+                unsigned long   vga_io_port_decode_enable:1;    /* RW */
+                unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
+                unsigned long   suppress_dest_registration:1;   /* RW */
+                unsigned long   programmed_initial_priority:3;  /* RW */
+                unsigned long   use_incoming_priority:1;        /* RW */
+                unsigned long   enable_programmed_initial_priority:1;/* RW */
+                unsigned long   rsvd_29_47:19;
+                unsigned long   fun:16;                         /* RW */
+        } s1;
+        struct uv2h_lb_bau_misc_control_s {
+                unsigned long   rejection_delay:8;              /* RW */
+                unsigned long   apic_mode:1;                    /* RW */
+                unsigned long   force_broadcast:1;              /* RW */
+                unsigned long   force_lock_nop:1;               /* RW */
+                unsigned long   qpi_agent_presence_vector:3;    /* RW */
+                unsigned long   descriptor_fetch_mode:1;        /* RW */
+                unsigned long   enable_intd_soft_ack_mode:1;    /* RW */
+                unsigned long   intd_soft_ack_timeout_period:4; /* RW */
+                unsigned long   enable_dual_mapping_mode:1;     /* RW */
+                unsigned long   vga_io_port_decode_enable:1;    /* RW */
+                unsigned long   vga_io_port_16_bit_decode:1;    /* RW */
+                unsigned long   suppress_dest_registration:1;   /* RW */
+                unsigned long   programmed_initial_priority:3;  /* RW */
+                unsigned long   use_incoming_priority:1;        /* RW */
+                unsigned long   enable_programmed_initial_priority:1;/* RW */
+                unsigned long   enable_automatic_apic_mode_selection:1;/* RW */
+                unsigned long   apic_mode_status:1;             /* RO */
+                unsigned long   suppress_interrupts_to_self:1;  /* RW */
+                unsigned long   enable_lock_based_system_flush:1;/* RW */
+                unsigned long   enable_extended_sb_status:1;    /* RW */
+                unsigned long   suppress_int_prio_udt_to_self:1;/* RW */
+                unsigned long   use_legacy_descriptor_formats:1;/* RW */
+                unsigned long   rsvd_36_47:12;
+                unsigned long   fun:16;                         /* RW */
+        } s2;
 };
 
 /* ========================================================================= */
 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL                0x320020UL
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32             0x9a8
 
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT     0
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT      62
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT      63
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK     0x000000000000003fUL
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK      0x4000000000000000UL
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK      0x8000000000000000UL
 
 union uvh_lb_bau_sb_activation_control_u {
-    unsigned long       v;
-    struct uvh_lb_bau_sb_activation_control_s {
-        unsigned long   index :  6;  /* RW */
-        unsigned long   rsvd_6_61: 56;  /*    */
-        unsigned long   push  :  1;  /* WP */
-        unsigned long   init  :  1;  /* WP */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_sb_activation_control_s {
+                unsigned long   index:6;                        /* RW */
+                unsigned long   rsvd_6_61:56;
+                unsigned long   push:1;                         /* WP */
+                unsigned long   init:1;                         /* WP */
+        } s;
 };
 
 /* ========================================================================= */
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0               0x320030UL
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32            0x9b0
 
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT   0
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK   0xffffffffffffffffUL
 
 union uvh_lb_bau_sb_activation_status_0_u {
-    unsigned long       v;
-    struct uvh_lb_bau_sb_activation_status_0_s {
-        unsigned long   status : 64;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_sb_activation_status_0_s {
+                unsigned long   status:64;                      /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1               0x320040UL
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32            0x9b8
 
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT   0
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK   0xffffffffffffffffUL
 
 union uvh_lb_bau_sb_activation_status_1_u {
-    unsigned long       v;
-    struct uvh_lb_bau_sb_activation_status_1_s {
-        unsigned long   status : 64;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_sb_activation_status_1_s {
+                unsigned long   status:64;                      /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
 /* ========================================================================= */
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE                   0x320010UL
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32                0x9a0
 
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT      49
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK      0x7ffe000000000000UL
 
 union uvh_lb_bau_sb_descriptor_base_u {
-    unsigned long       v;
-    struct uvh_lb_bau_sb_descriptor_base_s {
-        unsigned long   rsvd_0_11    : 12;  /*    */
-        unsigned long   page_address : 31;  /* RW */
-        unsigned long   rsvd_43_48   :  6;  /*    */
-        unsigned long   node_id      : 14;  /* RW */
-        unsigned long   rsvd_63      :  1;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_lb_bau_sb_descriptor_base_s {
+                unsigned long   rsvd_0_11:12;
+                unsigned long   page_address:31;                /* RW */
+                unsigned long   rsvd_43_48:6;
+                unsigned long   node_id:14;                     /* RW */
+                unsigned long   rsvd_63:1;
+        } s;
 };
 
 /* ========================================================================= */
 /*                               UVH_NODE_ID                                 */
 /* ========================================================================= */
-#define UVH_NODE_ID 0x0UL
-
-#define UVH_NODE_ID_FORCE1_SHFT 0
-#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
-#define UVH_NODE_ID_MANUFACTURER_SHFT 1
-#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
-#define UVH_NODE_ID_PART_NUMBER_SHFT 12
-#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
-#define UVH_NODE_ID_REVISION_SHFT 28
-#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
-#define UVH_NODE_ID_NODE_ID_SHFT 32
-#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
-
-#define UV1H_NODE_ID_FORCE1_SHFT 0
-#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
-#define UV1H_NODE_ID_MANUFACTURER_SHFT 1
-#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
-#define UV1H_NODE_ID_PART_NUMBER_SHFT 12
-#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
-#define UV1H_NODE_ID_REVISION_SHFT 28
-#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
-#define UV1H_NODE_ID_NODE_ID_SHFT 32
-#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
-#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48
-#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
-#define UV1H_NODE_ID_NI_PORT_SHFT 56
-#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
-
-#define UV2H_NODE_ID_FORCE1_SHFT 0
-#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
-#define UV2H_NODE_ID_MANUFACTURER_SHFT 1
-#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
-#define UV2H_NODE_ID_PART_NUMBER_SHFT 12
-#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
-#define UV2H_NODE_ID_REVISION_SHFT 28
-#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
-#define UV2H_NODE_ID_NODE_ID_SHFT 32
-#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
-#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50
-#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
-#define UV2H_NODE_ID_NI_PORT_SHFT 57
-#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
+#define UVH_NODE_ID                                     0x0UL
+
+#define UVH_NODE_ID_FORCE1_SHFT                         0
+#define UVH_NODE_ID_MANUFACTURER_SHFT                   1
+#define UVH_NODE_ID_PART_NUMBER_SHFT                    12
+#define UVH_NODE_ID_REVISION_SHFT                       28
+#define UVH_NODE_ID_NODE_ID_SHFT                        32
+#define UVH_NODE_ID_FORCE1_MASK                         0x0000000000000001UL
+#define UVH_NODE_ID_MANUFACTURER_MASK                   0x0000000000000ffeUL
+#define UVH_NODE_ID_PART_NUMBER_MASK                    0x000000000ffff000UL
+#define UVH_NODE_ID_REVISION_MASK                       0x00000000f0000000UL
+#define UVH_NODE_ID_NODE_ID_MASK                        0x00007fff00000000UL
+
+#define UV1H_NODE_ID_FORCE1_SHFT                        0
+#define UV1H_NODE_ID_MANUFACTURER_SHFT                  1
+#define UV1H_NODE_ID_PART_NUMBER_SHFT                   12
+#define UV1H_NODE_ID_REVISION_SHFT                      28
+#define UV1H_NODE_ID_NODE_ID_SHFT                       32
+#define UV1H_NODE_ID_NODES_PER_BIT_SHFT                 48
+#define UV1H_NODE_ID_NI_PORT_SHFT                       56
+#define UV1H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
+#define UV1H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
+#define UV1H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
+#define UV1H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
+#define UV1H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
+#define UV1H_NODE_ID_NODES_PER_BIT_MASK                 0x007f000000000000UL
+#define UV1H_NODE_ID_NI_PORT_MASK                       0x0f00000000000000UL
+
+#define UV2H_NODE_ID_FORCE1_SHFT                        0
+#define UV2H_NODE_ID_MANUFACTURER_SHFT                  1
+#define UV2H_NODE_ID_PART_NUMBER_SHFT                   12
+#define UV2H_NODE_ID_REVISION_SHFT                      28
+#define UV2H_NODE_ID_NODE_ID_SHFT                       32
+#define UV2H_NODE_ID_NODES_PER_BIT_SHFT                 50
+#define UV2H_NODE_ID_NI_PORT_SHFT                       57
+#define UV2H_NODE_ID_FORCE1_MASK                        0x0000000000000001UL
+#define UV2H_NODE_ID_MANUFACTURER_MASK                  0x0000000000000ffeUL
+#define UV2H_NODE_ID_PART_NUMBER_MASK                   0x000000000ffff000UL
+#define UV2H_NODE_ID_REVISION_MASK                      0x00000000f0000000UL
+#define UV2H_NODE_ID_NODE_ID_MASK                       0x00007fff00000000UL
+#define UV2H_NODE_ID_NODES_PER_BIT_MASK                 0x01fc000000000000UL
+#define UV2H_NODE_ID_NI_PORT_MASK                       0x3e00000000000000UL
 
 union uvh_node_id_u {
-    unsigned long       v;
-    struct uvh_node_id_s {
-        unsigned long   force1        :  1;  /* RO */
-        unsigned long   manufacturer  : 11;  /* RO */
-        unsigned long   part_number   : 16;  /* RO */
-        unsigned long   revision      :  4;  /* RO */
-        unsigned long   node_id       : 15;  /* RW */
-        unsigned long   rsvd_47_63    : 17;
-    } s;
-    struct uv1h_node_id_s {
-        unsigned long   force1        :  1;  /* RO */
-        unsigned long   manufacturer  : 11;  /* RO */
-        unsigned long   part_number   : 16;  /* RO */
-        unsigned long   revision      :  4;  /* RO */
-        unsigned long   node_id       : 15;  /* RW */
-        unsigned long   rsvd_47       :  1;  /*    */
-        unsigned long   nodes_per_bit :  7;  /* RW */
-        unsigned long   rsvd_55       :  1;  /*    */
-        unsigned long   ni_port       :  4;  /* RO */
-        unsigned long   rsvd_60_63    :  4;  /*    */
-    } s1;
-    struct uv2h_node_id_s {
-        unsigned long   force1        :  1;  /* RO */
-        unsigned long   manufacturer  : 11;  /* RO */
-        unsigned long   part_number   : 16;  /* RO */
-        unsigned long   revision      :  4;  /* RO */
-        unsigned long   node_id       : 15;  /* RW */
-        unsigned long   rsvd_47_49    :  3;  /*    */
-        unsigned long   nodes_per_bit :  7;  /* RO */
-        unsigned long   ni_port       :  5;  /* RO */
-        unsigned long   rsvd_62_63    :  2;  /*    */
-    } s2;
+        unsigned long   v;
+        struct uvh_node_id_s {
+                unsigned long   force1:1;                       /* RO */
+                unsigned long   manufacturer:11;                /* RO */
+                unsigned long   part_number:16;                 /* RO */
+                unsigned long   revision:4;                     /* RO */
+                unsigned long   node_id:15;                     /* RW */
+                unsigned long   rsvd_47_63:17;
+        } s;
+        struct uv1h_node_id_s {
+                unsigned long   force1:1;                       /* RO */
+                unsigned long   manufacturer:11;                /* RO */
+                unsigned long   part_number:16;                 /* RO */
+                unsigned long   revision:4;                     /* RO */
+                unsigned long   node_id:15;                     /* RW */
+                unsigned long   rsvd_47:1;
+                unsigned long   nodes_per_bit:7;                /* RW */
+                unsigned long   rsvd_55:1;
+                unsigned long   ni_port:4;                      /* RO */
+                unsigned long   rsvd_60_63:4;
+        } s1;
+        struct uv2h_node_id_s {
+                unsigned long   force1:1;                       /* RO */
+                unsigned long   manufacturer:11;                /* RO */
+                unsigned long   part_number:16;                 /* RO */
+                unsigned long   revision:4;                     /* RO */
+                unsigned long   node_id:15;                     /* RW */
+                unsigned long   rsvd_47_49:3;
+                unsigned long   nodes_per_bit:7;                /* RO */
+                unsigned long   ni_port:5;                      /* RO */
+                unsigned long   rsvd_62_63:2;
+        } s2;
 };
 
 /* ========================================================================= */
 /*                          UVH_NODE_PRESENT_TABLE                           */
 /* ========================================================================= */
-#define UVH_NODE_PRESENT_TABLE 0x1400UL
-#define UVH_NODE_PRESENT_TABLE_DEPTH 16
+#define UVH_NODE_PRESENT_TABLE                          0x1400UL
+#define UVH_NODE_PRESENT_TABLE_DEPTH                    16
 
-#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
-#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
+#define UVH_NODE_PRESENT_TABLE_NODES_SHFT               0
+#define UVH_NODE_PRESENT_TABLE_NODES_MASK               0xffffffffffffffffUL
 
 union uvh_node_present_table_u {
-    unsigned long       v;
-    struct uvh_node_present_table_s {
-        unsigned long   nodes : 64;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_node_present_table_s {
+                unsigned long   nodes:64;                       /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR        0x16000c8UL
 
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
 
 union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
-        unsigned long   rsvd_0_23: 24;  /*    */
-        unsigned long   base    :  8;  /* RW */
-        unsigned long   rsvd_32_47: 16;  /*    */
-        unsigned long   m_alias :  5;  /* RW */
-        unsigned long   rsvd_53_62: 10;  /*    */
-        unsigned long   enable  :  1;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
+                unsigned long   rsvd_0_23:24;
+                unsigned long   base:8;                         /* RW */
+                unsigned long   rsvd_32_47:16;
+                unsigned long   m_alias:5;                      /* RW */
+                unsigned long   rsvd_53_62:10;
+                unsigned long   enable:1;                       /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR        0x16000d8UL
 
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
 
 union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
-        unsigned long   rsvd_0_23: 24;  /*    */
-        unsigned long   base    :  8;  /* RW */
-        unsigned long   rsvd_32_47: 16;  /*    */
-        unsigned long   m_alias :  5;  /* RW */
-        unsigned long   rsvd_53_62: 10;  /*    */
-        unsigned long   enable  :  1;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
+                unsigned long   rsvd_0_23:24;
+                unsigned long   base:8;                         /* RW */
+                unsigned long   rsvd_32_47:16;
+                unsigned long   m_alias:5;                      /* RW */
+                unsigned long   rsvd_53_62:10;
+                unsigned long   enable:1;                       /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR        0x16000e8UL
 
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
 
 union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
-        unsigned long   rsvd_0_23: 24;  /*    */
-        unsigned long   base    :  8;  /* RW */
-        unsigned long   rsvd_32_47: 16;  /*    */
-        unsigned long   m_alias :  5;  /* RW */
-        unsigned long   rsvd_53_62: 10;  /*    */
-        unsigned long   enable  :  1;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
+                unsigned long   rsvd_0_23:24;
+                unsigned long   base:8;                         /* RW */
+                unsigned long   rsvd_32_47:16;
+                unsigned long   m_alias:5;                      /* RW */
+                unsigned long   rsvd_53_62:10;
+                unsigned long   enable:1;                       /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR       0x16000d0UL
 
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
 
 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
-        unsigned long   rsvd_0_23 : 24;  /*    */
-        unsigned long   dest_base : 22;  /* RW */
-        unsigned long   rsvd_46_63: 18;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
+                unsigned long   rsvd_0_23:24;
+                unsigned long   dest_base:22;                   /* RW */
+                unsigned long   rsvd_46_63:18;
+        } s;
 };
 
 /* ========================================================================= */
 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR       0x16000e0UL
 
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
 
 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
-        unsigned long   rsvd_0_23 : 24;  /*    */
-        unsigned long   dest_base : 22;  /* RW */
-        unsigned long   rsvd_46_63: 18;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
+                unsigned long   rsvd_0_23:24;
+                unsigned long   dest_base:22;                   /* RW */
+                unsigned long   rsvd_46_63:18;
+        } s;
 };
 
 /* ========================================================================= */
 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
 /* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR       0x16000f0UL
 
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
 
 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
-        unsigned long   rsvd_0_23 : 24;  /*    */
-        unsigned long   dest_base : 22;  /* RW */
-        unsigned long   rsvd_46_63: 18;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
+                unsigned long   rsvd_0_23:24;
+                unsigned long   dest_base:22;                   /* RW */
+                unsigned long   rsvd_46_63:18;
+        } s;
 };
 
 /* ========================================================================= */
 /*                          UVH_RH_GAM_CONFIG_MMR                            */
 /* ========================================================================= */
-#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
+#define UVH_RH_GAM_CONFIG_MMR                           0x1600000UL
 
-#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
-#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
-#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
-#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
+#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT                0
+#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT                6
+#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK                0x000000000000003fUL
+#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK                0x00000000000003c0UL
 
-#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
-#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
-#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
-#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
-#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
-#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
+#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
+#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
+#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT           12
+#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
+#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
+#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK           0x0000000000001000UL
 
-#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
-#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
-#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
-#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
+#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT               0
+#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT               6
+#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK               0x000000000000003fUL
+#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK               0x00000000000003c0UL
 
 union uvh_rh_gam_config_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_config_mmr_s {
-        unsigned long   m_skt     :  6;  /* RW */
-        unsigned long   n_skt     :  4;  /* RW */
-        unsigned long   rsvd_10_63    : 54;
-    } s;
-    struct uv1h_rh_gam_config_mmr_s {
-        unsigned long   m_skt     :  6;  /* RW */
-        unsigned long   n_skt     :  4;  /* RW */
-        unsigned long   rsvd_10_11:  2;  /*    */
-        unsigned long   mmiol_cfg :  1;  /* RW */
-        unsigned long   rsvd_13_63: 51;  /*    */
-    } s1;
-    struct uv2h_rh_gam_config_mmr_s {
-        unsigned long   m_skt :  6;  /* RW */
-        unsigned long   n_skt :  4;  /* RW */
-        unsigned long   rsvd_10_63: 54;  /*    */
-    } s2;
+        unsigned long   v;
+        struct uvh_rh_gam_config_mmr_s {
+                unsigned long   m_skt:6;                        /* RW */
+                unsigned long   n_skt:4;                        /* RW */
+                unsigned long   rsvd_10_63:54;
+        } s;
+        struct uv1h_rh_gam_config_mmr_s {
+                unsigned long   m_skt:6;                        /* RW */
+                unsigned long   n_skt:4;                        /* RW */
+                unsigned long   rsvd_10_11:2;
+                unsigned long   mmiol_cfg:1;                    /* RW */
+                unsigned long   rsvd_13_63:51;
+        } s1;
+        struct uv2h_rh_gam_config_mmr_s {
+                unsigned long   m_skt:6;                        /* RW */
+                unsigned long   n_skt:4;                        /* RW */
+                unsigned long   rsvd_10_63:54;
+        } s2;
 };
 
 /* ========================================================================= */
 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
 /* ========================================================================= */
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR               0x1600010UL
 
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT     28
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK     0x00003ffff0000000UL
 
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT     48
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK     0x0001000000000000UL
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT    28
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT   52
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffff0000000UL
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK   0x00f0000000000000UL
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
 union uvh_rh_gam_gru_overlay_config_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_gru_overlay_config_mmr_s {
-        unsigned long   rsvd_0_27: 28;  /*    */
-        unsigned long   base   : 18;  /* RW */
-        unsigned long   rsvd_46_62    : 17;
-        unsigned long   enable :  1;  /* RW */
-    } s;
-    struct uv1h_rh_gam_gru_overlay_config_mmr_s {
-        unsigned long   rsvd_0_27: 28;  /*    */
-        unsigned long   base   : 18;  /* RW */
-        unsigned long   rsvd_46_47:  2;  /*    */
-        unsigned long   gr4    :  1;  /* RW */
-        unsigned long   rsvd_49_51:  3;  /*    */
-        unsigned long   n_gru  :  4;  /* RW */
-        unsigned long   rsvd_56_62:  7;  /*    */
-        unsigned long   enable :  1;  /* RW */
-    } s1;
-    struct uv2h_rh_gam_gru_overlay_config_mmr_s {
-        unsigned long   rsvd_0_27: 28;  /*    */
-        unsigned long   base   : 18;  /* RW */
-        unsigned long   rsvd_46_51:  6;  /*    */
-        unsigned long   n_gru  :  4;  /* RW */
-        unsigned long   rsvd_56_62:  7;  /*    */
-        unsigned long   enable :  1;  /* RW */
-    } s2;
+        unsigned long   v;
+        struct uvh_rh_gam_gru_overlay_config_mmr_s {
+                unsigned long   rsvd_0_27:28;
+                unsigned long   base:18;                        /* RW */
+                unsigned long   rsvd_46_62:17;
+                unsigned long   enable:1;                       /* RW */
+        } s;
+        struct uv1h_rh_gam_gru_overlay_config_mmr_s {
+                unsigned long   rsvd_0_27:28;
+                unsigned long   base:18;                        /* RW */
+                unsigned long   rsvd_46_47:2;
+                unsigned long   gr4:1;                          /* RW */
+                unsigned long   rsvd_49_51:3;
+                unsigned long   n_gru:4;                        /* RW */
+                unsigned long   rsvd_56_62:7;
+                unsigned long   enable:1;                       /* RW */
+        } s1;
+        struct uv2h_rh_gam_gru_overlay_config_mmr_s {
+                unsigned long   rsvd_0_27:28;
+                unsigned long   base:18;                        /* RW */
+                unsigned long   rsvd_46_51:6;
+                unsigned long   n_gru:4;                        /* RW */
+                unsigned long   rsvd_56_62:7;
+                unsigned long   enable:1;                       /* RW */
+        } s2;
 };
 
 /* ========================================================================= */
 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
 /* ========================================================================= */
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR             0x1600030UL
 
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  30
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT  52
 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK  0x00003fffc0000000UL
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK  0x000fc00000000000UL
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT  27
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT  46
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT  52
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK  0x00003ffff8000000UL
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK  0x000fc00000000000UL
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK  0x00f0000000000000UL
 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 
 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
-    unsigned long       v;
-    struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
-        unsigned long   rsvd_0_29: 30;  /*    */
-        unsigned long   base   : 16;  /* RW */
-        unsigned long   m_io   :  6;  /* RW */
-        unsigned long   n_io   :  4;  /* RW */
-        unsigned long   rsvd_56_62:  7;  /*    */
-        unsigned long   enable :  1;  /* RW */
-    } s1;
-    struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
-        unsigned long   rsvd_0_26: 27;  /*    */
-        unsigned long   base   : 19;  /* RW */
-        unsigned long   m_io   :  6;  /* RW */
-        unsigned long   n_io   :  4;  /* RW */
-        unsigned long   rsvd_56_62:  7;  /*    */
-        unsigned long   enable :  1;  /* RW */
-    } s2;
+        unsigned long   v;
+        struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
+                unsigned long   rsvd_0_29:30;
+                unsigned long   base:16;                        /* RW */
+                unsigned long   m_io:6;                         /* RW */
+                unsigned long   n_io:4;                         /* RW */
+                unsigned long   rsvd_56_62:7;
+                unsigned long   enable:1;                       /* RW */
+        } s1;
+        struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
+                unsigned long   rsvd_0_26:27;
+                unsigned long   base:19;                        /* RW */
+                unsigned long   m_io:6;                         /* RW */
+                unsigned long   n_io:4;                         /* RW */
+                unsigned long   rsvd_56_62:7;
+                unsigned long   enable:1;                       /* RW */
+        } s2;
 };
 
 /* ========================================================================= */
 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
 /* ========================================================================= */
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR               0x1600028UL
 
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT     26
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK     0x00003ffffc000000UL
 
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT    26
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT  63
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK    0x00003ffffc000000UL
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK  0x8000000000000000UL
 
 union uvh_rh_gam_mmr_overlay_config_mmr_u {
-    unsigned long       v;
-    struct uvh_rh_gam_mmr_overlay_config_mmr_s {
-        unsigned long   rsvd_0_25: 26;  /*    */
-        unsigned long   base     : 20;  /* RW */
-        unsigned long   rsvd_46_62    : 17;
-        unsigned long   enable   :  1;  /* RW */
-    } s;
-    struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
-        unsigned long   rsvd_0_25: 26;  /*    */
-        unsigned long   base     : 20;  /* RW */
-        unsigned long   dual_hub :  1;  /* RW */
-        unsigned long   rsvd_47_62: 16;  /*    */
-        unsigned long   enable   :  1;  /* RW */
-    } s1;
-    struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
-        unsigned long   rsvd_0_25: 26;  /*    */
-        unsigned long   base   : 20;  /* RW */
-        unsigned long   rsvd_46_62: 17;  /*    */
-        unsigned long   enable :  1;  /* RW */
-    } s2;
+        unsigned long   v;
+        struct uvh_rh_gam_mmr_overlay_config_mmr_s {
+                unsigned long   rsvd_0_25:26;
+                unsigned long   base:20;                        /* RW */
+                unsigned long   rsvd_46_62:17;
+                unsigned long   enable:1;                       /* RW */
+        } s;
+        struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
+                unsigned long   rsvd_0_25:26;
+                unsigned long   base:20;                        /* RW */
+                unsigned long   dual_hub:1;                     /* RW */
+                unsigned long   rsvd_47_62:16;
+                unsigned long   enable:1;                       /* RW */
+        } s1;
+        struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
+                unsigned long   rsvd_0_25:26;
+                unsigned long   base:20;                        /* RW */
+                unsigned long   rsvd_46_62:17;
+                unsigned long   enable:1;                       /* RW */
+        } s2;
 };
 
 /* ========================================================================= */
 /*                                 UVH_RTC                                   */
 /* ========================================================================= */
-#define UVH_RTC 0x340000UL
+#define UVH_RTC                                         0x340000UL
 
-#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
-#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
+#define UVH_RTC_REAL_TIME_CLOCK_SHFT                    0
+#define UVH_RTC_REAL_TIME_CLOCK_MASK                    0x00ffffffffffffffUL
 
 union uvh_rtc_u {
-    unsigned long       v;
-    struct uvh_rtc_s {
-        unsigned long   real_time_clock : 56;  /* RW */
-        unsigned long   rsvd_56_63      :  8;  /*    */
-    } s;
+        unsigned long   v;
+        struct uvh_rtc_s {
+                unsigned long   real_time_clock:56;             /* RW */
+                unsigned long   rsvd_56_63:8;
+        } s;
 };
 
 /* ========================================================================= */
 /*                           UVH_RTC1_INT_CONFIG                             */
 /* ========================================================================= */
-#define UVH_RTC1_INT_CONFIG 0x615c0UL
-
-#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
-#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
-#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
-#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
-#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_RTC1_INT_CONFIG_P_SHFT 13
-#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_RTC1_INT_CONFIG_T_SHFT 15
-#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_RTC1_INT_CONFIG_M_SHFT 16
-#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
-#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+#define UVH_RTC1_INT_CONFIG                             0x615c0UL
+
+#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT                 0
+#define UVH_RTC1_INT_CONFIG_DM_SHFT                     8
+#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT               11
+#define UVH_RTC1_INT_CONFIG_STATUS_SHFT                 12
+#define UVH_RTC1_INT_CONFIG_P_SHFT                      13
+#define UVH_RTC1_INT_CONFIG_T_SHFT                      15
+#define UVH_RTC1_INT_CONFIG_M_SHFT                      16
+#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT                32
+#define UVH_RTC1_INT_CONFIG_VECTOR_MASK                 0x00000000000000ffUL
+#define UVH_RTC1_INT_CONFIG_DM_MASK                     0x0000000000000700UL
+#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK               0x0000000000000800UL
+#define UVH_RTC1_INT_CONFIG_STATUS_MASK                 0x0000000000001000UL
+#define UVH_RTC1_INT_CONFIG_P_MASK                      0x0000000000002000UL
+#define UVH_RTC1_INT_CONFIG_T_MASK                      0x0000000000008000UL
+#define UVH_RTC1_INT_CONFIG_M_MASK                      0x0000000000010000UL
+#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK                0xffffffff00000000UL
 
 union uvh_rtc1_int_config_u {
-    unsigned long       v;
-    struct uvh_rtc1_int_config_s {
-        unsigned long   vector_  :  8;  /* RW */
-        unsigned long   dm       :  3;  /* RW */
-        unsigned long   destmode :  1;  /* RW */
-        unsigned long   status   :  1;  /* RO */
-        unsigned long   p        :  1;  /* RO */
-        unsigned long   rsvd_14  :  1;  /*    */
-        unsigned long   t        :  1;  /* RO */
-        unsigned long   m        :  1;  /* RW */
-        unsigned long   rsvd_17_31: 15;  /*    */
-        unsigned long   apic_id  : 32;  /* RW */
-    } s;
+        unsigned long   v;
+        struct uvh_rtc1_int_config_s {
+                unsigned long   vector_:8;                      /* RW */
+                unsigned long   dm:3;                           /* RW */
+                unsigned long   destmode:1;                     /* RW */
+                unsigned long   status:1;                       /* RO */
+                unsigned long   p:1;                            /* RO */
+                unsigned long   rsvd_14:1;
+                unsigned long   t:1;                            /* RO */
+                unsigned long   m:1;                            /* RW */
+                unsigned long   rsvd_17_31:15;
+                unsigned long   apic_id:32;                     /* RW */
+        } s;
 };
 
 /* ========================================================================= */
 /*                               UVH_SCRATCH5                                */
 /* ========================================================================= */
-#define UVH_SCRATCH5 0x2d0200UL
-#define UVH_SCRATCH5_32 0x778
+#define UVH_SCRATCH5                                    0x2d0200UL
+#define UVH_SCRATCH5_32                                 0x778
 
-#define UVH_SCRATCH5_SCRATCH5_SHFT 0
-#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
+#define UVH_SCRATCH5_SCRATCH5_SHFT                      0
+#define UVH_SCRATCH5_SCRATCH5_MASK                      0xffffffffffffffffUL
 
 union uvh_scratch5_u {
-    unsigned long       v;
-    struct uvh_scratch5_s {
-        unsigned long   scratch5 : 64;  /* RW, W1CS */
-    } s;
+        unsigned long   v;
+        struct uvh_scratch5_s {
+                unsigned long   scratch5:64;                    /* RW, W1CS */
+        } s;
 };
 
 /* ========================================================================= */
 /*                           UV2H_EVENT_OCCURRED2                            */
 /* ========================================================================= */
-#define UV2H_EVENT_OCCURRED2 0x70100UL
-#define UV2H_EVENT_OCCURRED2_32 0xb68
-
-#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
-#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
-#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
-#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
-#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
-#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
-#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
-#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
-#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
-#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
-#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
-#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
-#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
-#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
-#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
-#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
-#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
-#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
-#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
-#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
-#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
-#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
-#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
-#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
-#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
-#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
-#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
-#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
-#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
-#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
-#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
-#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
-#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
-#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
-#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
-#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
-#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
-#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
-#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
-#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
-#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
-#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
-#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
-#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
-#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
-#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
-#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
-#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
-#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
-#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
-#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
-#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
-#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
-#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
-#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
-#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
-#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
-#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
-#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
-#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
-#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
-#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
-#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
-#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
+#define UV2H_EVENT_OCCURRED2                            0x70100UL
+#define UV2H_EVENT_OCCURRED2_32                         0xb68
+
+#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT                 0
+#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT                 1
+#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT                 2
+#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT                 3
+#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT                 4
+#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT                 5
+#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT                 6
+#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT                 7
+#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT                 8
+#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT                 9
+#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT                10
+#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT                11
+#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT                12
+#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT                13
+#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT                14
+#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT                15
+#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT                16
+#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT                17
+#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT                18
+#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT                19
+#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT                20
+#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT                21
+#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT                22
+#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT                23
+#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT                24
+#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT                25
+#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT                26
+#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT                27
+#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT                28
+#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT                29
+#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT                30
+#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT                31
+#define UV2H_EVENT_OCCURRED2_RTC_0_MASK                 0x0000000000000001UL
+#define UV2H_EVENT_OCCURRED2_RTC_1_MASK                 0x0000000000000002UL
+#define UV2H_EVENT_OCCURRED2_RTC_2_MASK                 0x0000000000000004UL
+#define UV2H_EVENT_OCCURRED2_RTC_3_MASK                 0x0000000000000008UL
+#define UV2H_EVENT_OCCURRED2_RTC_4_MASK                 0x0000000000000010UL
+#define UV2H_EVENT_OCCURRED2_RTC_5_MASK                 0x0000000000000020UL
+#define UV2H_EVENT_OCCURRED2_RTC_6_MASK                 0x0000000000000040UL
+#define UV2H_EVENT_OCCURRED2_RTC_7_MASK                 0x0000000000000080UL
+#define UV2H_EVENT_OCCURRED2_RTC_8_MASK                 0x0000000000000100UL
+#define UV2H_EVENT_OCCURRED2_RTC_9_MASK                 0x0000000000000200UL
+#define UV2H_EVENT_OCCURRED2_RTC_10_MASK                0x0000000000000400UL
+#define UV2H_EVENT_OCCURRED2_RTC_11_MASK                0x0000000000000800UL
+#define UV2H_EVENT_OCCURRED2_RTC_12_MASK                0x0000000000001000UL
+#define UV2H_EVENT_OCCURRED2_RTC_13_MASK                0x0000000000002000UL
+#define UV2H_EVENT_OCCURRED2_RTC_14_MASK                0x0000000000004000UL
+#define UV2H_EVENT_OCCURRED2_RTC_15_MASK                0x0000000000008000UL
+#define UV2H_EVENT_OCCURRED2_RTC_16_MASK                0x0000000000010000UL
+#define UV2H_EVENT_OCCURRED2_RTC_17_MASK                0x0000000000020000UL
+#define UV2H_EVENT_OCCURRED2_RTC_18_MASK                0x0000000000040000UL
+#define UV2H_EVENT_OCCURRED2_RTC_19_MASK                0x0000000000080000UL
+#define UV2H_EVENT_OCCURRED2_RTC_20_MASK                0x0000000000100000UL
+#define UV2H_EVENT_OCCURRED2_RTC_21_MASK                0x0000000000200000UL
+#define UV2H_EVENT_OCCURRED2_RTC_22_MASK                0x0000000000400000UL
+#define UV2H_EVENT_OCCURRED2_RTC_23_MASK                0x0000000000800000UL
+#define UV2H_EVENT_OCCURRED2_RTC_24_MASK                0x0000000001000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_25_MASK                0x0000000002000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_26_MASK                0x0000000004000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_27_MASK                0x0000000008000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_28_MASK                0x0000000010000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_29_MASK                0x0000000020000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_30_MASK                0x0000000040000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_31_MASK                0x0000000080000000UL
 
 union uv2h_event_occurred2_u {
-    unsigned long       v;
-    struct uv2h_event_occurred2_s {
-        unsigned long   rtc_0  :  1;  /* RW */
-        unsigned long   rtc_1  :  1;  /* RW */
-        unsigned long   rtc_2  :  1;  /* RW */
-        unsigned long   rtc_3  :  1;  /* RW */
-        unsigned long   rtc_4  :  1;  /* RW */
-        unsigned long   rtc_5  :  1;  /* RW */
-        unsigned long   rtc_6  :  1;  /* RW */
-        unsigned long   rtc_7  :  1;  /* RW */
-        unsigned long   rtc_8  :  1;  /* RW */
-        unsigned long   rtc_9  :  1;  /* RW */
-        unsigned long   rtc_10 :  1;  /* RW */
-        unsigned long   rtc_11 :  1;  /* RW */
-        unsigned long   rtc_12 :  1;  /* RW */
-        unsigned long   rtc_13 :  1;  /* RW */
-        unsigned long   rtc_14 :  1;  /* RW */
-        unsigned long   rtc_15 :  1;  /* RW */
-        unsigned long   rtc_16 :  1;  /* RW */
-        unsigned long   rtc_17 :  1;  /* RW */
-        unsigned long   rtc_18 :  1;  /* RW */
-        unsigned long   rtc_19 :  1;  /* RW */
-        unsigned long   rtc_20 :  1;  /* RW */
-        unsigned long   rtc_21 :  1;  /* RW */
-        unsigned long   rtc_22 :  1;  /* RW */
-        unsigned long   rtc_23 :  1;  /* RW */
-        unsigned long   rtc_24 :  1;  /* RW */
-        unsigned long   rtc_25 :  1;  /* RW */
-        unsigned long   rtc_26 :  1;  /* RW */
-        unsigned long   rtc_27 :  1;  /* RW */
-        unsigned long   rtc_28 :  1;  /* RW */
-        unsigned long   rtc_29 :  1;  /* RW */
-        unsigned long   rtc_30 :  1;  /* RW */
-        unsigned long   rtc_31 :  1;  /* RW */
-        unsigned long   rsvd_32_63: 32;  /*    */
-    } s1;
+        unsigned long   v;
+        struct uv2h_event_occurred2_s {
+                unsigned long   rtc_0:1;                        /* RW */
+                unsigned long   rtc_1:1;                        /* RW */
+                unsigned long   rtc_2:1;                        /* RW */
+                unsigned long   rtc_3:1;                        /* RW */
+                unsigned long   rtc_4:1;                        /* RW */
+                unsigned long   rtc_5:1;                        /* RW */
+                unsigned long   rtc_6:1;                        /* RW */
+                unsigned long   rtc_7:1;                        /* RW */
+                unsigned long   rtc_8:1;                        /* RW */
+                unsigned long   rtc_9:1;                        /* RW */
+                unsigned long   rtc_10:1;                       /* RW */
+                unsigned long   rtc_11:1;                       /* RW */
+                unsigned long   rtc_12:1;                       /* RW */
+                unsigned long   rtc_13:1;                       /* RW */
+                unsigned long   rtc_14:1;                       /* RW */
+                unsigned long   rtc_15:1;                       /* RW */
+                unsigned long   rtc_16:1;                       /* RW */
+                unsigned long   rtc_17:1;                       /* RW */
+                unsigned long   rtc_18:1;                       /* RW */
+                unsigned long   rtc_19:1;                       /* RW */
+                unsigned long   rtc_20:1;                       /* RW */
+                unsigned long   rtc_21:1;                       /* RW */
+                unsigned long   rtc_22:1;                       /* RW */
+                unsigned long   rtc_23:1;                       /* RW */
+                unsigned long   rtc_24:1;                       /* RW */
+                unsigned long   rtc_25:1;                       /* RW */
+                unsigned long   rtc_26:1;                       /* RW */
+                unsigned long   rtc_27:1;                       /* RW */
+                unsigned long   rtc_28:1;                       /* RW */
+                unsigned long   rtc_29:1;                       /* RW */
+                unsigned long   rtc_30:1;                       /* RW */
+                unsigned long   rtc_31:1;                       /* RW */
+                unsigned long   rsvd_32_63:32;
+        } s1;
 };
 
 /* ========================================================================= */
 /*                        UV2H_EVENT_OCCURRED2_ALIAS                         */
 /* ========================================================================= */
-#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
-#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
+#define UV2H_EVENT_OCCURRED2_ALIAS                      0x70108UL
+#define UV2H_EVENT_OCCURRED2_ALIAS_32                   0xb70
 
 /* ========================================================================= */
 /*                    UV2H_LB_BAU_SB_ACTIVATION_STATUS_2                     */
 /* ========================================================================= */
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2              0x320130UL
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32           0x9f0
 
 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
 
 union uv2h_lb_bau_sb_activation_status_2_u {
-    unsigned long       v;
-    struct uv2h_lb_bau_sb_activation_status_2_s {
-        unsigned long   aux_error : 64;  /* RW */
-    } s1;
+        unsigned long   v;
+        struct uv2h_lb_bau_sb_activation_status_2_s {
+                unsigned long   aux_error:64;                   /* RW */
+        } s1;
 };
 
 /* ========================================================================= */
 /*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
 /* ========================================================================= */
-#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
-#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0
+#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK            0x320130UL
+#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32         0x9f0
 
 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
 
 union uv1h_lb_target_physical_apic_id_mask_u {
-    unsigned long       v;
-    struct uv1h_lb_target_physical_apic_id_mask_s {
-        unsigned long   bit_enables : 32;  /* RW */
-        unsigned long   rsvd_32_63  : 32;  /*    */
-    } s1;
+        unsigned long   v;
+        struct uv1h_lb_target_physical_apic_id_mask_s {
+                unsigned long   bit_enables:32;                 /* RW */
+                unsigned long   rsvd_32_63:32;
+        } s1;
 };
 
 
-#endif /* __ASM_UV_MMRS_X86_H__ */
+#endif /* _ASM_X86_UV_UV_MMRS_H */
diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h
index 646b4c1ca695..815285bcaceb 100644
--- a/arch/x86/include/asm/vgtod.h
+++ b/arch/x86/include/asm/vgtod.h
@@ -11,10 +11,9 @@ struct vsyscall_gtod_data {
         time_t          wall_time_sec;
         u32             wall_time_nsec;
 
-        int             sysctl_enabled;
         struct timezone sys_tz;
         struct { /* extract of a clocksource struct */
-                cycle_t (*vread)(void);
+                int vclock_mode;
                 cycle_t cycle_last;
                 cycle_t mask;
                 u32     mult;
diff --git a/arch/x86/include/asm/vsyscall.h b/arch/x86/include/asm/vsyscall.h
index d55597351f6a..60107072c28b 100644
--- a/arch/x86/include/asm/vsyscall.h
+++ b/arch/x86/include/asm/vsyscall.h
@@ -16,10 +16,6 @@ enum vsyscall_num {
 #ifdef __KERNEL__
 #include <linux/seqlock.h>
 
-/* Definitions for CONFIG_GENERIC_TIME definitions */
-#define __vsyscall_fn \
-        __attribute__ ((unused, __section__(".vsyscall_fn"))) notrace
-
 #define VGETCPU_RDTSCP  1
 #define VGETCPU_LSL     2
 
diff --git a/arch/x86/include/asm/vvar.h b/arch/x86/include/asm/vvar.h
index 341b3559452b..de656ac2af41 100644
--- a/arch/x86/include/asm/vvar.h
+++ b/arch/x86/include/asm/vvar.h
@@ -10,15 +10,14 @@
  * In normal kernel code, they are used like any other variable.
  * In user code, they are accessed through the VVAR macro.
  *
- * Each of these variables lives in the vsyscall page, and each
- * one needs a unique offset within the little piece of the page
- * reserved for vvars.  Specify that offset in DECLARE_VVAR.
- * (There are 896 bytes available.  If you mess up, the linker will
- * catch it.)
+ * These variables live in a page of kernel data that has an extra RO
+ * mapping for userspace.  Each variable needs a unique offset within
+ * that page; specify that offset with the DECLARE_VVAR macro.  (If
+ * you mess up, the linker will catch it.)
  */
 
-/* Offset of vars within vsyscall page */
-#define VSYSCALL_VARS_OFFSET (3072 + 128)
+/* Base address of vvars.  This is not ABI. */
+#define VVAR_ADDRESS (-10*1024*1024 - 4096)
 
 #if defined(__VVAR_KERNEL_LDS)
 
@@ -26,17 +25,17 @@
  * right place.
  */
 #define DECLARE_VVAR(offset, type, name) \
-        EMIT_VVAR(name, VSYSCALL_VARS_OFFSET + offset)
+        EMIT_VVAR(name, offset)
 
 #else
 
 #define DECLARE_VVAR(offset, type, name)                                \
         static type const * const vvaraddr_ ## name =                   \
-                (void *)(VSYSCALL_START + VSYSCALL_VARS_OFFSET + (offset));
+                (void *)(VVAR_ADDRESS + (offset));
 
 #define DEFINE_VVAR(type, name)                                         \
-        type __vvar_ ## name                                            \
-        __attribute__((section(".vsyscall_var_" #name), aligned(16)))
+        type name                                                       \
+        __attribute__((section(".vvar_" #name), aligned(16)))
 
 #define VVAR(name) (*vvaraddr_ ## name)
 
@@ -45,8 +44,7 @@
 /* DECLARE_VVAR(offset, type, name) */
 
 DECLARE_VVAR(0, volatile unsigned long, jiffies)
-DECLARE_VVAR(8, int, vgetcpu_mode)
+DECLARE_VVAR(16, int, vgetcpu_mode)
 DECLARE_VVAR(128, struct vsyscall_gtod_data, vsyscall_gtod_data)
 
 #undef DECLARE_VVAR
-#undef VSYSCALL_VARS_OFFSET
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index d240ea950519..417777de5a40 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -39,6 +39,8 @@
 #include <linux/string.h>
 #include <linux/types.h>
 
+#include <trace/events/xen.h>
+
 #include <asm/page.h>
 #include <asm/pgtable.h>
 
@@ -459,6 +461,8 @@ MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set)
 {
         mcl->op = __HYPERVISOR_fpu_taskswitch;
         mcl->args[0] = set;
+
+        trace_xen_mc_entry(mcl, 1);
 }
 
 static inline void
@@ -475,6 +479,8 @@ MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
                 mcl->args[2] = new_val.pte >> 32;
                 mcl->args[3] = flags;
         }
+
+        trace_xen_mc_entry(mcl, sizeof(new_val) == sizeof(long) ? 3 : 4);
 }
 
 static inline void
@@ -485,6 +491,8 @@ MULTI_grant_table_op(struct multicall_entry *mcl, unsigned int cmd,
         mcl->args[0] = cmd;
         mcl->args[1] = (unsigned long)uop;
         mcl->args[2] = count;
+
+        trace_xen_mc_entry(mcl, 3);
 }
 
 static inline void
@@ -504,6 +512,8 @@ MULTI_update_va_mapping_otherdomain(struct multicall_entry *mcl, unsigned long v
                 mcl->args[3] = flags;
                 mcl->args[4] = domid;
         }
+
+        trace_xen_mc_entry(mcl, sizeof(new_val) == sizeof(long) ? 4 : 5);
 }
 
 static inline void
@@ -520,6 +530,8 @@ MULTI_update_descriptor(struct multicall_entry *mcl, u64 maddr,
                 mcl->args[2] = desc.a;
                 mcl->args[3] = desc.b;
         }
+
+        trace_xen_mc_entry(mcl, sizeof(maddr) == sizeof(long) ? 2 : 4);
 }
 
 static inline void
@@ -528,6 +540,8 @@ MULTI_memory_op(struct multicall_entry *mcl, unsigned int cmd, void *arg)
         mcl->op = __HYPERVISOR_memory_op;
         mcl->args[0] = cmd;
         mcl->args[1] = (unsigned long)arg;
+
+        trace_xen_mc_entry(mcl, 2);
 }
 
 static inline void
@@ -539,6 +553,8 @@ MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
         mcl->args[1] = count;
         mcl->args[2] = (unsigned long)success_count;
         mcl->args[3] = domid;
+
+        trace_xen_mc_entry(mcl, 4);
 }
 
 static inline void
@@ -550,6 +566,8 @@ MULTI_mmuext_op(struct multicall_entry *mcl, struct mmuext_op *op, int count,
         mcl->args[1] = count;
         mcl->args[2] = (unsigned long)success_count;
         mcl->args[3] = domid;
+
+        trace_xen_mc_entry(mcl, 4);
 }
 
 static inline void
@@ -558,6 +576,8 @@ MULTI_set_gdt(struct multicall_entry *mcl, unsigned long *frames, int entries)
         mcl->op = __HYPERVISOR_set_gdt;
         mcl->args[0] = (unsigned long)frames;
         mcl->args[1] = entries;
+
+        trace_xen_mc_entry(mcl, 2);
 }
 
 static inline void
@@ -567,6 +587,8 @@ MULTI_stack_switch(struct multicall_entry *mcl,
         mcl->op = __HYPERVISOR_stack_switch;
         mcl->args[0] = ss;
         mcl->args[1] = esp;
+
+        trace_xen_mc_entry(mcl, 2);
 }
 
 #endif /* _ASM_X86_XEN_HYPERCALL_H */
diff --git a/arch/x86/include/asm/xen/pci.h b/arch/x86/include/asm/xen/pci.h
index 4fbda9a3f339..968d57dd54c9 100644
--- a/arch/x86/include/asm/xen/pci.h
+++ b/arch/x86/include/asm/xen/pci.h
@@ -14,13 +14,14 @@ static inline int pci_xen_hvm_init(void)
 }
 #endif
 #if defined(CONFIG_XEN_DOM0)
-void __init xen_setup_pirqs(void);
+int __init pci_xen_initial_domain(void);
 int xen_find_device_domain_owner(struct pci_dev *dev);
 int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain);
 int xen_unregister_device_domain_owner(struct pci_dev *dev);
 #else
-static inline void __init xen_setup_pirqs(void)
+static inline int __init pci_xen_initial_domain(void)
 {
+        return -1;
 }
 static inline int xen_find_device_domain_owner(struct pci_dev *dev)
 {
diff --git a/arch/x86/include/asm/xen/trace_types.h b/arch/x86/include/asm/xen/trace_types.h
new file mode 100644
index 000000000000..21e1874c0a0b
--- /dev/null
+++ b/arch/x86/include/asm/xen/trace_types.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_XEN_TRACE_TYPES_H
+#define _ASM_XEN_TRACE_TYPES_H
+
+enum xen_mc_flush_reason {
+        XEN_MC_FL_NONE,         /* explicit flush */
+        XEN_MC_FL_BATCH,        /* out of hypercall space */
+        XEN_MC_FL_ARGS,         /* out of argument space */
+        XEN_MC_FL_CALLBACK,     /* out of callback space */
+};
+
+enum xen_mc_extend_args {
+        XEN_MC_XE_OK,
+        XEN_MC_XE_BAD_OP,
+        XEN_MC_XE_NO_SPACE
+};
+typedef void (*xen_mc_callback_fn_t)(void *);
+
+#endif  /* _ASM_XEN_TRACE_TYPES_H */
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 90b06d4daee2..04105574c8e9 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -24,17 +24,12 @@ endif
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_vsyscall_64.o    := $(PROFILING) -g0 $(nostackp)
 CFLAGS_hpet.o           := $(nostackp)
-CFLAGS_vread_tsc_64.o   := $(nostackp)
 CFLAGS_paravirt.o       := $(nostackp)
 GCOV_PROFILE_vsyscall_64.o      := n
 GCOV_PROFILE_hpet.o             := n
 GCOV_PROFILE_tsc.o              := n
-GCOV_PROFILE_vread_tsc_64.o     := n
 GCOV_PROFILE_paravirt.o         := n
 
-# vread_tsc_64 is hot and should be fully optimized:
-CFLAGS_REMOVE_vread_tsc_64.o = -pg -fno-optimize-sibling-calls
-
 obj-y                   := process_$(BITS).o signal.o entry_$(BITS).o
 obj-y                   += traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o
 obj-y                   += time.o ioport.o ldt.o dumpstack.o
@@ -43,7 +38,8 @@ obj-$(CONFIG_IRQ_WORK)  += irq_work.o
 obj-y                   += probe_roms.o
 obj-$(CONFIG_X86_32)    += sys_i386_32.o i386_ksyms_32.o
 obj-$(CONFIG_X86_64)    += sys_x86_64.o x8664_ksyms_64.o
-obj-$(CONFIG_X86_64)    += syscall_64.o vsyscall_64.o vread_tsc_64.o
+obj-$(CONFIG_X86_64)    += syscall_64.o vsyscall_64.o
+obj-$(CONFIG_X86_64)    += vsyscall_emu_64.o
 obj-y                   += bootflag.o e820.o
 obj-y                   += pci-dma.o quirks.o topology.o kdebugfs.o
 obj-y                   += alternative.o i8253.o pci-nommu.o hw_breakpoint.o
@@ -123,7 +119,6 @@ ifeq ($(CONFIG_X86_64),y)
 
         obj-$(CONFIG_GART_IOMMU)        += amd_gart_64.o aperture_64.o
         obj-$(CONFIG_CALGARY_IOMMU)     += pci-calgary_64.o tce_64.o
-        obj-$(CONFIG_AMD_IOMMU)         += amd_iommu_init.o amd_iommu.o
 
         obj-$(CONFIG_PCI_MMCONFIG)      += mmconf-fam10h_64.o
         obj-y                           += vsmp_64.o
diff --git a/arch/x86/kernel/acpi/realmode/wakeup.S b/arch/x86/kernel/acpi/realmode/wakeup.S
index ead21b663117..b4fd836e4053 100644
--- a/arch/x86/kernel/acpi/realmode/wakeup.S
+++ b/arch/x86/kernel/acpi/realmode/wakeup.S
@@ -28,6 +28,8 @@ pmode_cr3:	.long	0	/* Saved %cr3 */
 pmode_cr4:      .long   0       /* Saved %cr4 */
 pmode_efer:     .quad   0       /* Saved EFER */
 pmode_gdt:      .quad   0
+pmode_misc_en:  .quad   0       /* Saved MISC_ENABLE MSR */
+pmode_behavior: .long   0       /* Wakeup behavior flags */
 realmode_flags: .long   0
 real_magic:     .long   0
 trampoline_segment:     .word 0
@@ -91,6 +93,18 @@ wakeup_code:
         /* Call the C code */
         calll   main
 
+        /* Restore MISC_ENABLE before entering protected mode, in case
+           BIOS decided to clear XD_DISABLE during S3. */
+        movl    pmode_behavior, %eax
+        btl     $WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE, %eax
+        jnc     1f
+
+        movl    pmode_misc_en, %eax
+        movl    pmode_misc_en + 4, %edx
+        movl    $MSR_IA32_MISC_ENABLE, %ecx
+        wrmsr
+1:
+
         /* Do any other stuff... */
 
 #ifndef CONFIG_64BIT
diff --git a/arch/x86/kernel/acpi/realmode/wakeup.h b/arch/x86/kernel/acpi/realmode/wakeup.h
index e1828c07e79c..97a29e1430e3 100644
--- a/arch/x86/kernel/acpi/realmode/wakeup.h
+++ b/arch/x86/kernel/acpi/realmode/wakeup.h
@@ -21,6 +21,9 @@ struct wakeup_header {
         u32 pmode_efer_low;     /* Protected mode EFER */
         u32 pmode_efer_high;
         u64 pmode_gdt;
+        u32 pmode_misc_en_low;  /* Protected mode MISC_ENABLE */
+        u32 pmode_misc_en_high;
+        u32 pmode_behavior;     /* Wakeup routine behavior flags */
         u32 realmode_flags;
         u32 real_magic;
         u16 trampoline_segment; /* segment with trampoline code, 64-bit only */
@@ -39,4 +42,7 @@ extern struct wakeup_header wakeup_header;
 #define WAKEUP_HEADER_SIGNATURE 0x51ee1111
 #define WAKEUP_END_SIGNATURE    0x65a22c82
 
+/* Wakeup behavior bits */
+#define WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE     0
+
 #endif /* ARCH_X86_KERNEL_ACPI_RM_WAKEUP_H */
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 18a857ba7a25..103b6ab368d3 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -77,6 +77,12 @@ int acpi_suspend_lowlevel(void)
 
         header->pmode_cr0 = read_cr0();
         header->pmode_cr4 = read_cr4_safe();
+        header->pmode_behavior = 0;
+        if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
+                        &header->pmode_misc_en_low,
+                        &header->pmode_misc_en_high))
+                header->pmode_behavior |=
+                        (1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
         header->realmode_flags = acpi_realmode_flags;
         header->real_magic = 0x12345678;
 
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index a81f2d52f869..c63822816249 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -14,7 +14,6 @@
 #include <asm/pgtable.h>
 #include <asm/mce.h>
 #include <asm/nmi.h>
-#include <asm/vsyscall.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/io.h>
@@ -250,7 +249,6 @@ static void __init_or_module add_nops(void *insns, unsigned int len)
 
 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
 extern s32 __smp_locks[], __smp_locks_end[];
-extern char __vsyscall_0;
 void *text_poke_early(void *addr, const void *opcode, size_t len);
 
 /* Replace instructions with better alternatives for this CPU type.
@@ -263,6 +261,7 @@ void __init_or_module apply_alternatives(struct alt_instr *start,
                                          struct alt_instr *end)
 {
         struct alt_instr *a;
+        u8 *instr, *replacement;
         u8 insnbuf[MAX_PATCH_LEN];
 
         DPRINTK("%s: alt table %p -> %p\n", __func__, start, end);
@@ -276,25 +275,23 @@ void __init_or_module apply_alternatives(struct alt_instr *start,
          * order.
          */
         for (a = start; a < end; a++) {
-                u8 *instr = a->instr;
+                instr = (u8 *)&a->instr_offset + a->instr_offset;
+                replacement = (u8 *)&a->repl_offset + a->repl_offset;
                 BUG_ON(a->replacementlen > a->instrlen);
                 BUG_ON(a->instrlen > sizeof(insnbuf));
                 BUG_ON(a->cpuid >= NCAPINTS*32);
                 if (!boot_cpu_has(a->cpuid))
                         continue;
-#ifdef CONFIG_X86_64
-                /* vsyscall code is not mapped yet. resolve it manually. */
-                if (instr >= (u8 *)VSYSCALL_START && instr < (u8*)VSYSCALL_END) {
-                        instr = __va(instr - (u8*)VSYSCALL_START + (u8*)__pa_symbol(&__vsyscall_0));
-                        DPRINTK("%s: vsyscall fixup: %p => %p\n",
-                                __func__, a->instr, instr);
-                }
-#endif
-                memcpy(insnbuf, a->replacement, a->replacementlen);
+
+                memcpy(insnbuf, replacement, a->replacementlen);
+
+                /* 0xe8 is a relative jump; fix the offset. */
                 if (*insnbuf == 0xe8 && a->replacementlen == 5)
-                    *(s32 *)(insnbuf + 1) += a->replacement - a->instr;
+                    *(s32 *)(insnbuf + 1) += replacement - instr;
+
                 add_nops(insnbuf + a->replacementlen,
                          a->instrlen - a->replacementlen);
+
                 text_poke_early(instr, insnbuf, a->instrlen);
         }
 }
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
deleted file mode 100644
index 7c3a95e54ec5..000000000000
--- a/arch/x86/kernel/amd_iommu.c
+++ /dev/null
@@ -1,2764 +0,0 @@
-/*
- * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *         Leo Duran <leo.duran@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <linux/pci.h>
-#include <linux/pci-ats.h>
-#include <linux/bitmap.h>
-#include <linux/slab.h>
-#include <linux/debugfs.h>
-#include <linux/scatterlist.h>
-#include <linux/dma-mapping.h>
-#include <linux/iommu-helper.h>
-#include <linux/iommu.h>
-#include <linux/delay.h>
-#include <asm/proto.h>
-#include <asm/iommu.h>
-#include <asm/gart.h>
-#include <asm/dma.h>
-#include <asm/amd_iommu_proto.h>
-#include <asm/amd_iommu_types.h>
-#include <asm/amd_iommu.h>
-
-#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
-
-#define LOOP_TIMEOUT    100000
-
-static DEFINE_RWLOCK(amd_iommu_devtable_lock);
-
-/* A list of preallocated protection domains */
-static LIST_HEAD(iommu_pd_list);
-static DEFINE_SPINLOCK(iommu_pd_list_lock);
-
-/*
- * Domain for untranslated devices - only allocated
- * if iommu=pt passed on kernel cmd line.
- */
-static struct protection_domain *pt_domain;
-
-static struct iommu_ops amd_iommu_ops;
-
-/*
- * general struct to manage commands send to an IOMMU
- */
-struct iommu_cmd {
-        u32 data[4];
-};
-
-static void update_domain(struct protection_domain *domain);
-
-/****************************************************************************
- *
- * Helper functions
- *
- ****************************************************************************/
-
-static inline u16 get_device_id(struct device *dev)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-
-        return calc_devid(pdev->bus->number, pdev->devfn);
-}
-
-static struct iommu_dev_data *get_dev_data(struct device *dev)
-{
-        return dev->archdata.iommu;
-}
-
-/*
- * In this function the list of preallocated protection domains is traversed to
- * find the domain for a specific device
- */
-static struct dma_ops_domain *find_protection_domain(u16 devid)
-{
-        struct dma_ops_domain *entry, *ret = NULL;
-        unsigned long flags;
-        u16 alias = amd_iommu_alias_table[devid];
-
-        if (list_empty(&iommu_pd_list))
-                return NULL;
-
-        spin_lock_irqsave(&iommu_pd_list_lock, flags);
-
-        list_for_each_entry(entry, &iommu_pd_list, list) {
-                if (entry->target_dev == devid ||
-                    entry->target_dev == alias) {
-                        ret = entry;
-                        break;
-                }
-        }
-
-        spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
-
-        return ret;
-}
-
-/*
- * This function checks if the driver got a valid device from the caller to
- * avoid dereferencing invalid pointers.
- */
-static bool check_device(struct device *dev)
-{
-        u16 devid;
-
-        if (!dev || !dev->dma_mask)
-                return false;
-
-        /* No device or no PCI device */
-        if (dev->bus != &pci_bus_type)
-                return false;
-
-        devid = get_device_id(dev);
-
-        /* Out of our scope? */
-        if (devid > amd_iommu_last_bdf)
-                return false;
-
-        if (amd_iommu_rlookup_table[devid] == NULL)
-                return false;
-
-        return true;
-}
-
-static int iommu_init_device(struct device *dev)
-{
-        struct iommu_dev_data *dev_data;
-        struct pci_dev *pdev;
-        u16 devid, alias;
-
-        if (dev->archdata.iommu)
-                return 0;
-
-        dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
-        if (!dev_data)
-                return -ENOMEM;
-
-        dev_data->dev = dev;
-
-        devid = get_device_id(dev);
-        alias = amd_iommu_alias_table[devid];
-        pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
-        if (pdev)
-                dev_data->alias = &pdev->dev;
-        else {
-                kfree(dev_data);
-                return -ENOTSUPP;
-        }
-
-        atomic_set(&dev_data->bind, 0);
-
-        dev->archdata.iommu = dev_data;
-
-
-        return 0;
-}
-
-static void iommu_ignore_device(struct device *dev)
-{
-        u16 devid, alias;
-
-        devid = get_device_id(dev);
-        alias = amd_iommu_alias_table[devid];
-
-        memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
-        memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
-
-        amd_iommu_rlookup_table[devid] = NULL;
-        amd_iommu_rlookup_table[alias] = NULL;
-}
-
-static void iommu_uninit_device(struct device *dev)
-{
-        kfree(dev->archdata.iommu);
-}
-
-void __init amd_iommu_uninit_devices(void)
-{
-        struct pci_dev *pdev = NULL;
-
-        for_each_pci_dev(pdev) {
-
-                if (!check_device(&pdev->dev))
-                        continue;
-
-                iommu_uninit_device(&pdev->dev);
-        }
-}
-
-int __init amd_iommu_init_devices(void)
-{
-        struct pci_dev *pdev = NULL;
-        int ret = 0;
-
-        for_each_pci_dev(pdev) {
-
-                if (!check_device(&pdev->dev))
-                        continue;
-
-                ret = iommu_init_device(&pdev->dev);
-                if (ret == -ENOTSUPP)
-                        iommu_ignore_device(&pdev->dev);
-                else if (ret)
-                        goto out_free;
-        }
-
-        return 0;
-
-out_free:
-
-        amd_iommu_uninit_devices();
-
-        return ret;
-}
-#ifdef CONFIG_AMD_IOMMU_STATS
-
-/*
- * Initialization code for statistics collection
- */
-
-DECLARE_STATS_COUNTER(compl_wait);
-DECLARE_STATS_COUNTER(cnt_map_single);
-DECLARE_STATS_COUNTER(cnt_unmap_single);
-DECLARE_STATS_COUNTER(cnt_map_sg);
-DECLARE_STATS_COUNTER(cnt_unmap_sg);
-DECLARE_STATS_COUNTER(cnt_alloc_coherent);
-DECLARE_STATS_COUNTER(cnt_free_coherent);
-DECLARE_STATS_COUNTER(cross_page);
-DECLARE_STATS_COUNTER(domain_flush_single);
-DECLARE_STATS_COUNTER(domain_flush_all);
-DECLARE_STATS_COUNTER(alloced_io_mem);
-DECLARE_STATS_COUNTER(total_map_requests);
-
-static struct dentry *stats_dir;
-static struct dentry *de_fflush;
-
-static void amd_iommu_stats_add(struct __iommu_counter *cnt)
-{
-        if (stats_dir == NULL)
-                return;
-
-        cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
-                                       &cnt->value);
-}
-
-static void amd_iommu_stats_init(void)
-{
-        stats_dir = debugfs_create_dir("amd-iommu", NULL);
-        if (stats_dir == NULL)
-                return;
-
-        de_fflush  = debugfs_create_bool("fullflush", 0444, stats_dir,
-                                         (u32 *)&amd_iommu_unmap_flush);
-
-        amd_iommu_stats_add(&compl_wait);
-        amd_iommu_stats_add(&cnt_map_single);
-        amd_iommu_stats_add(&cnt_unmap_single);
-        amd_iommu_stats_add(&cnt_map_sg);
-        amd_iommu_stats_add(&cnt_unmap_sg);
-        amd_iommu_stats_add(&cnt_alloc_coherent);
-        amd_iommu_stats_add(&cnt_free_coherent);
-        amd_iommu_stats_add(&cross_page);
-        amd_iommu_stats_add(&domain_flush_single);
-        amd_iommu_stats_add(&domain_flush_all);
-        amd_iommu_stats_add(&alloced_io_mem);
-        amd_iommu_stats_add(&total_map_requests);
-}
-
-#endif
-
-/****************************************************************************
- *
- * Interrupt handling functions
- *
- ****************************************************************************/
-
-static void dump_dte_entry(u16 devid)
-{
-        int i;
-
-        for (i = 0; i < 8; ++i)
-                pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
-                        amd_iommu_dev_table[devid].data[i]);
-}
-
-static void dump_command(unsigned long phys_addr)
-{
-        struct iommu_cmd *cmd = phys_to_virt(phys_addr);
-        int i;
-
-        for (i = 0; i < 4; ++i)
-                pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
-}
-
-static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
-{
-        u32 *event = __evt;
-        int type  = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;
-        int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
-        int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
-        int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
-        u64 address = (u64)(((u64)event[3]) << 32) | event[2];
-
-        printk(KERN_ERR "AMD-Vi: Event logged [");
-
-        switch (type) {
-        case EVENT_TYPE_ILL_DEV:
-                printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
-                       "address=0x%016llx flags=0x%04x]\n",
-                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
-                       address, flags);
-                dump_dte_entry(devid);
-                break;
-        case EVENT_TYPE_IO_FAULT:
-                printk("IO_PAGE_FAULT device=%02x:%02x.%x "
-                       "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
-                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
-                       domid, address, flags);
-                break;
-        case EVENT_TYPE_DEV_TAB_ERR:
-                printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
-                       "address=0x%016llx flags=0x%04x]\n",
-                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
-                       address, flags);
-                break;
-        case EVENT_TYPE_PAGE_TAB_ERR:
-                printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
-                       "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
-                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
-                       domid, address, flags);
-                break;
-        case EVENT_TYPE_ILL_CMD:
-                printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
-                dump_command(address);
-                break;
-        case EVENT_TYPE_CMD_HARD_ERR:
-                printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
-                       "flags=0x%04x]\n", address, flags);
-                break;
-        case EVENT_TYPE_IOTLB_INV_TO:
-                printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
-                       "address=0x%016llx]\n",
-                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
-                       address);
-                break;
-        case EVENT_TYPE_INV_DEV_REQ:
-                printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
-                       "address=0x%016llx flags=0x%04x]\n",
-                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
-                       address, flags);
-                break;
-        default:
-                printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
-        }
-}
-
-static void iommu_poll_events(struct amd_iommu *iommu)
-{
-        u32 head, tail;
-        unsigned long flags;
-
-        spin_lock_irqsave(&iommu->lock, flags);
-
-        head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
-        tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
-
-        while (head != tail) {
-                iommu_print_event(iommu, iommu->evt_buf + head);
-                head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
-        }
-
-        writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
-
-        spin_unlock_irqrestore(&iommu->lock, flags);
-}
-
-irqreturn_t amd_iommu_int_thread(int irq, void *data)
-{
-        struct amd_iommu *iommu;
-
-        for_each_iommu(iommu)
-                iommu_poll_events(iommu);
-
-        return IRQ_HANDLED;
-}
-
-irqreturn_t amd_iommu_int_handler(int irq, void *data)
-{
-        return IRQ_WAKE_THREAD;
-}
-
-/****************************************************************************
- *
- * IOMMU command queuing functions
- *
- ****************************************************************************/
-
-static int wait_on_sem(volatile u64 *sem)
-{
-        int i = 0;
-
-        while (*sem == 0 && i < LOOP_TIMEOUT) {
-                udelay(1);
-                i += 1;
-        }
-
-        if (i == LOOP_TIMEOUT) {
-                pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
-                return -EIO;
-        }
-
-        return 0;
-}
-
-static void copy_cmd_to_buffer(struct amd_iommu *iommu,
-                               struct iommu_cmd *cmd,
-                               u32 tail)
-{
-        u8 *target;
-
-        target = iommu->cmd_buf + tail;
-        tail   = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
-
-        /* Copy command to buffer */
-        memcpy(target, cmd, sizeof(*cmd));
-
-        /* Tell the IOMMU about it */
-        writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
-}
-
-static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
-{
-        WARN_ON(address & 0x7ULL);
-
-        memset(cmd, 0, sizeof(*cmd));
-        cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
-        cmd->data[1] = upper_32_bits(__pa(address));
-        cmd->data[2] = 1;
-        CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
-}
-
-static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
-{
-        memset(cmd, 0, sizeof(*cmd));
-        cmd->data[0] = devid;
-        CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
-}
-
-static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
-                                  size_t size, u16 domid, int pde)
-{
-        u64 pages;
-        int s;
-
-        pages = iommu_num_pages(address, size, PAGE_SIZE);
-        s     = 0;
-
-        if (pages > 1) {
-                /*
-                 * If we have to flush more than one page, flush all
-                 * TLB entries for this domain
-                 */
-                address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
-                s = 1;
-        }
-
-        address &= PAGE_MASK;
-
-        memset(cmd, 0, sizeof(*cmd));
-        cmd->data[1] |= domid;
-        cmd->data[2]  = lower_32_bits(address);
-        cmd->data[3]  = upper_32_bits(address);
-        CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
-        if (s) /* size bit - we flush more than one 4kb page */
-                cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
-        if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
-                cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
-}
-
-static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
-                                  u64 address, size_t size)
-{
-        u64 pages;
-        int s;
-
-        pages = iommu_num_pages(address, size, PAGE_SIZE);
-        s     = 0;
-
-        if (pages > 1) {
-                /*
-                 * If we have to flush more than one page, flush all
-                 * TLB entries for this domain
-                 */
-                address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
-                s = 1;
-        }
-
-        address &= PAGE_MASK;
-
-        memset(cmd, 0, sizeof(*cmd));
-        cmd->data[0]  = devid;
-        cmd->data[0] |= (qdep & 0xff) << 24;
-        cmd->data[1]  = devid;
-        cmd->data[2]  = lower_32_bits(address);
-        cmd->data[3]  = upper_32_bits(address);
-        CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
-        if (s)
-                cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
-}
-
-static void build_inv_all(struct iommu_cmd *cmd)
-{
-        memset(cmd, 0, sizeof(*cmd));
-        CMD_SET_TYPE(cmd, CMD_INV_ALL);
-}
-
-/*
- * Writes the command to the IOMMUs command buffer and informs the
- * hardware about the new command.
- */
-static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
-{
-        u32 left, tail, head, next_tail;
-        unsigned long flags;
-
-        WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
-
-again:
-        spin_lock_irqsave(&iommu->lock, flags);
-
-        head      = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
-        tail      = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
-        next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
-        left      = (head - next_tail) % iommu->cmd_buf_size;
-
-        if (left <= 2) {
-                struct iommu_cmd sync_cmd;
-                volatile u64 sem = 0;
-                int ret;
-
-                build_completion_wait(&sync_cmd, (u64)&sem);
-                copy_cmd_to_buffer(iommu, &sync_cmd, tail);
-
-                spin_unlock_irqrestore(&iommu->lock, flags);
-
-                if ((ret = wait_on_sem(&sem)) != 0)
-                        return ret;
-
-                goto again;
-        }
-
-        copy_cmd_to_buffer(iommu, cmd, tail);
-
-        /* We need to sync now to make sure all commands are processed */
-        iommu->need_sync = true;
-
-        spin_unlock_irqrestore(&iommu->lock, flags);
-
-        return 0;
-}
-
-/*
- * This function queues a completion wait command into the command
- * buffer of an IOMMU
- */
-static int iommu_completion_wait(struct amd_iommu *iommu)
-{
-        struct iommu_cmd cmd;
-        volatile u64 sem = 0;
-        int ret;
-
-        if (!iommu->need_sync)
-                return 0;
-
-        build_completion_wait(&cmd, (u64)&sem);
-
-        ret = iommu_queue_command(iommu, &cmd);
-        if (ret)
-                return ret;
-
-        return wait_on_sem(&sem);
-}
-
-static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
-{
-        struct iommu_cmd cmd;
-
-        build_inv_dte(&cmd, devid);
-
-        return iommu_queue_command(iommu, &cmd);
-}
-
-static void iommu_flush_dte_all(struct amd_iommu *iommu)
-{
-        u32 devid;
-
-        for (devid = 0; devid <= 0xffff; ++devid)
-                iommu_flush_dte(iommu, devid);
-
-        iommu_completion_wait(iommu);
-}
-
-/*
- * This function uses heavy locking and may disable irqs for some time. But
- * this is no issue because it is only called during resume.
- */
-static void iommu_flush_tlb_all(struct amd_iommu *iommu)
-{
-        u32 dom_id;
-
-        for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
-                struct iommu_cmd cmd;
-                build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
-                                      dom_id, 1);
-                iommu_queue_command(iommu, &cmd);
-        }
-
-        iommu_completion_wait(iommu);
-}
-
-static void iommu_flush_all(struct amd_iommu *iommu)
-{
-        struct iommu_cmd cmd;
-
-        build_inv_all(&cmd);
-
-        iommu_queue_command(iommu, &cmd);
-        iommu_completion_wait(iommu);
-}
-
-void iommu_flush_all_caches(struct amd_iommu *iommu)
-{
-        if (iommu_feature(iommu, FEATURE_IA)) {
-                iommu_flush_all(iommu);
-        } else {
-                iommu_flush_dte_all(iommu);
-                iommu_flush_tlb_all(iommu);
-        }
-}
-
-/*
- * Command send function for flushing on-device TLB
- */
-static int device_flush_iotlb(struct device *dev, u64 address, size_t size)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-        struct amd_iommu *iommu;
-        struct iommu_cmd cmd;
-        u16 devid;
-        int qdep;
-
-        qdep  = pci_ats_queue_depth(pdev);
-        devid = get_device_id(dev);
-        iommu = amd_iommu_rlookup_table[devid];
-
-        build_inv_iotlb_pages(&cmd, devid, qdep, address, size);
-
-        return iommu_queue_command(iommu, &cmd);
-}
-
-/*
- * Command send function for invalidating a device table entry
- */
-static int device_flush_dte(struct device *dev)
-{
-        struct amd_iommu *iommu;
-        struct pci_dev *pdev;
-        u16 devid;
-        int ret;
-
-        pdev  = to_pci_dev(dev);
-        devid = get_device_id(dev);
-        iommu = amd_iommu_rlookup_table[devid];
-
-        ret = iommu_flush_dte(iommu, devid);
-        if (ret)
-                return ret;
-
-        if (pci_ats_enabled(pdev))
-                ret = device_flush_iotlb(dev, 0, ~0UL);
-
-        return ret;
-}
-
-/*
- * TLB invalidation function which is called from the mapping functions.
- * It invalidates a single PTE if the range to flush is within a single
- * page. Otherwise it flushes the whole TLB of the IOMMU.
- */
-static void __domain_flush_pages(struct protection_domain *domain,
-                                 u64 address, size_t size, int pde)
-{
-        struct iommu_dev_data *dev_data;
-        struct iommu_cmd cmd;
-        int ret = 0, i;
-
-        build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
-
-        for (i = 0; i < amd_iommus_present; ++i) {
-                if (!domain->dev_iommu[i])
-                        continue;
-
-                /*
-                 * Devices of this domain are behind this IOMMU
-                 * We need a TLB flush
-                 */
-                ret |= iommu_queue_command(amd_iommus[i], &cmd);
-        }
-
-        list_for_each_entry(dev_data, &domain->dev_list, list) {
-                struct pci_dev *pdev = to_pci_dev(dev_data->dev);
-
-                if (!pci_ats_enabled(pdev))
-                        continue;
-
-                ret |= device_flush_iotlb(dev_data->dev, address, size);
-        }
-
-        WARN_ON(ret);
-}
-
-static void domain_flush_pages(struct protection_domain *domain,
-                               u64 address, size_t size)
-{
-        __domain_flush_pages(domain, address, size, 0);
-}
-
-/* Flush the whole IO/TLB for a given protection domain */
-static void domain_flush_tlb(struct protection_domain *domain)
-{
-        __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
-}
-
-/* Flush the whole IO/TLB for a given protection domain - including PDE */
-static void domain_flush_tlb_pde(struct protection_domain *domain)
-{
-        __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
-}
-
-static void domain_flush_complete(struct protection_domain *domain)
-{
-        int i;
-
-        for (i = 0; i < amd_iommus_present; ++i) {
-                if (!domain->dev_iommu[i])
-                        continue;
-
-                /*
-                 * Devices of this domain are behind this IOMMU
-                 * We need to wait for completion of all commands.
-                 */
-                iommu_completion_wait(amd_iommus[i]);
-        }
-}
-
-
-/*
- * This function flushes the DTEs for all devices in domain
- */
-static void domain_flush_devices(struct protection_domain *domain)
-{
-        struct iommu_dev_data *dev_data;
-        unsigned long flags;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        list_for_each_entry(dev_data, &domain->dev_list, list)
-                device_flush_dte(dev_data->dev);
-
-        spin_unlock_irqrestore(&domain->lock, flags);
-}
-
-/****************************************************************************
- *
- * The functions below are used the create the page table mappings for
- * unity mapped regions.
- *
- ****************************************************************************/
-
-/*
- * This function is used to add another level to an IO page table. Adding
- * another level increases the size of the address space by 9 bits to a size up
- * to 64 bits.
- */
-static bool increase_address_space(struct protection_domain *domain,
-                                   gfp_t gfp)
-{
-        u64 *pte;
-
-        if (domain->mode == PAGE_MODE_6_LEVEL)
-                /* address space already 64 bit large */
-                return false;
-
-        pte = (void *)get_zeroed_page(gfp);
-        if (!pte)
-                return false;
-
-        *pte             = PM_LEVEL_PDE(domain->mode,
-                                        virt_to_phys(domain->pt_root));
-        domain->pt_root  = pte;
-        domain->mode    += 1;
-        domain->updated  = true;
-
-        return true;
-}
-
-static u64 *alloc_pte(struct protection_domain *domain,
-                      unsigned long address,
-                      unsigned long page_size,
-                      u64 **pte_page,
-                      gfp_t gfp)
-{
-        int level, end_lvl;
-        u64 *pte, *page;
-
-        BUG_ON(!is_power_of_2(page_size));
-
-        while (address > PM_LEVEL_SIZE(domain->mode))
-                increase_address_space(domain, gfp);
-
-        level   = domain->mode - 1;
-        pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
-        address = PAGE_SIZE_ALIGN(address, page_size);
-        end_lvl = PAGE_SIZE_LEVEL(page_size);
-
-        while (level > end_lvl) {
-                if (!IOMMU_PTE_PRESENT(*pte)) {
-                        page = (u64 *)get_zeroed_page(gfp);
-                        if (!page)
-                                return NULL;
-                        *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
-                }
-
-                /* No level skipping support yet */
-                if (PM_PTE_LEVEL(*pte) != level)
-                        return NULL;
-
-                level -= 1;
-
-                pte = IOMMU_PTE_PAGE(*pte);
-
-                if (pte_page && level == end_lvl)
-                        *pte_page = pte;
-
-                pte = &pte[PM_LEVEL_INDEX(level, address)];
-        }
-
-        return pte;
-}
-
-/*
- * This function checks if there is a PTE for a given dma address. If
- * there is one, it returns the pointer to it.
- */
-static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
-{
-        int level;
-        u64 *pte;
-
-        if (address > PM_LEVEL_SIZE(domain->mode))
-                return NULL;
-
-        level   =  domain->mode - 1;
-        pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
-
-        while (level > 0) {
-
-                /* Not Present */
-                if (!IOMMU_PTE_PRESENT(*pte))
-                        return NULL;
-
-                /* Large PTE */
-                if (PM_PTE_LEVEL(*pte) == 0x07) {
-                        unsigned long pte_mask, __pte;
-
-                        /*
-                         * If we have a series of large PTEs, make
-                         * sure to return a pointer to the first one.
-                         */
-                        pte_mask = PTE_PAGE_SIZE(*pte);
-                        pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
-                        __pte    = ((unsigned long)pte) & pte_mask;
-
-                        return (u64 *)__pte;
-                }
-
-                /* No level skipping support yet */
-                if (PM_PTE_LEVEL(*pte) != level)
-                        return NULL;
-
-                level -= 1;
-
-                /* Walk to the next level */
-                pte = IOMMU_PTE_PAGE(*pte);
-                pte = &pte[PM_LEVEL_INDEX(level, address)];
-        }
-
-        return pte;
-}
-
-/*
- * Generic mapping functions. It maps a physical address into a DMA
- * address space. It allocates the page table pages if necessary.
- * In the future it can be extended to a generic mapping function
- * supporting all features of AMD IOMMU page tables like level skipping
- * and full 64 bit address spaces.
- */
-static int iommu_map_page(struct protection_domain *dom,
-                          unsigned long bus_addr,
-                          unsigned long phys_addr,
-                          int prot,
-                          unsigned long page_size)
-{
-        u64 __pte, *pte;
-        int i, count;
-
-        if (!(prot & IOMMU_PROT_MASK))
-                return -EINVAL;
-
-        bus_addr  = PAGE_ALIGN(bus_addr);
-        phys_addr = PAGE_ALIGN(phys_addr);
-        count     = PAGE_SIZE_PTE_COUNT(page_size);
-        pte       = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
-
-        for (i = 0; i < count; ++i)
-                if (IOMMU_PTE_PRESENT(pte[i]))
-                        return -EBUSY;
-
-        if (page_size > PAGE_SIZE) {
-                __pte = PAGE_SIZE_PTE(phys_addr, page_size);
-                __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
-        } else
-                __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
-
-        if (prot & IOMMU_PROT_IR)
-                __pte |= IOMMU_PTE_IR;
-        if (prot & IOMMU_PROT_IW)
-                __pte |= IOMMU_PTE_IW;
-
-        for (i = 0; i < count; ++i)
-                pte[i] = __pte;
-
-        update_domain(dom);
-
-        return 0;
-}
-
-static unsigned long iommu_unmap_page(struct protection_domain *dom,
-                                      unsigned long bus_addr,
-                                      unsigned long page_size)
-{
-        unsigned long long unmap_size, unmapped;
-        u64 *pte;
-
-        BUG_ON(!is_power_of_2(page_size));
-
-        unmapped = 0;
-
-        while (unmapped < page_size) {
-
-                pte = fetch_pte(dom, bus_addr);
-
-                if (!pte) {
-                        /*
-                         * No PTE for this address
-                         * move forward in 4kb steps
-                         */
-                        unmap_size = PAGE_SIZE;
-                } else if (PM_PTE_LEVEL(*pte) == 0) {
-                        /* 4kb PTE found for this address */
-                        unmap_size = PAGE_SIZE;
-                        *pte       = 0ULL;
-                } else {
-                        int count, i;
-
-                        /* Large PTE found which maps this address */
-                        unmap_size = PTE_PAGE_SIZE(*pte);
-                        count      = PAGE_SIZE_PTE_COUNT(unmap_size);
-                        for (i = 0; i < count; i++)
-                                pte[i] = 0ULL;
-                }
-
-                bus_addr  = (bus_addr & ~(unmap_size - 1)) + unmap_size;
-                unmapped += unmap_size;
-        }
-
-        BUG_ON(!is_power_of_2(unmapped));
-
-        return unmapped;
-}
-
-/*
- * This function checks if a specific unity mapping entry is needed for
- * this specific IOMMU.
- */
-static int iommu_for_unity_map(struct amd_iommu *iommu,
-                               struct unity_map_entry *entry)
-{
-        u16 bdf, i;
-
-        for (i = entry->devid_start; i <= entry->devid_end; ++i) {
-                bdf = amd_iommu_alias_table[i];
-                if (amd_iommu_rlookup_table[bdf] == iommu)
-                        return 1;
-        }
-
-        return 0;
-}
-
-/*
- * This function actually applies the mapping to the page table of the
- * dma_ops domain.
- */
-static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
-                             struct unity_map_entry *e)
-{
-        u64 addr;
-        int ret;
-
-        for (addr = e->address_start; addr < e->address_end;
-             addr += PAGE_SIZE) {
-                ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
-                                     PAGE_SIZE);
-                if (ret)
-                        return ret;
-                /*
-                 * if unity mapping is in aperture range mark the page
-                 * as allocated in the aperture
-                 */
-                if (addr < dma_dom->aperture_size)
-                        __set_bit(addr >> PAGE_SHIFT,
-                                  dma_dom->aperture[0]->bitmap);
-        }
-
-        return 0;
-}
-
-/*
- * Init the unity mappings for a specific IOMMU in the system
- *
- * Basically iterates over all unity mapping entries and applies them to
- * the default domain DMA of that IOMMU if necessary.
- */
-static int iommu_init_unity_mappings(struct amd_iommu *iommu)
-{
-        struct unity_map_entry *entry;
-        int ret;
-
-        list_for_each_entry(entry, &amd_iommu_unity_map, list) {
-                if (!iommu_for_unity_map(iommu, entry))
-                        continue;
-                ret = dma_ops_unity_map(iommu->default_dom, entry);
-                if (ret)
-                        return ret;
-        }
-
-        return 0;
-}
-
-/*
- * Inits the unity mappings required for a specific device
- */
-static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
-                                          u16 devid)
-{
-        struct unity_map_entry *e;
-        int ret;
-
-        list_for_each_entry(e, &amd_iommu_unity_map, list) {
-                if (!(devid >= e->devid_start && devid <= e->devid_end))
-                        continue;
-                ret = dma_ops_unity_map(dma_dom, e);
-                if (ret)
-                        return ret;
-        }
-
-        return 0;
-}
-
-/****************************************************************************
- *
- * The next functions belong to the address allocator for the dma_ops
- * interface functions. They work like the allocators in the other IOMMU
- * drivers. Its basically a bitmap which marks the allocated pages in
- * the aperture. Maybe it could be enhanced in the future to a more
- * efficient allocator.
- *
- ****************************************************************************/
-
-/*
- * The address allocator core functions.
- *
- * called with domain->lock held
- */
-
-/*
- * Used to reserve address ranges in the aperture (e.g. for exclusion
- * ranges.
- */
-static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
-                                      unsigned long start_page,
-                                      unsigned int pages)
-{
-        unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
-
-        if (start_page + pages > last_page)
-                pages = last_page - start_page;
-
-        for (i = start_page; i < start_page + pages; ++i) {
-                int index = i / APERTURE_RANGE_PAGES;
-                int page  = i % APERTURE_RANGE_PAGES;
-                __set_bit(page, dom->aperture[index]->bitmap);
-        }
-}
-
-/*
- * This function is used to add a new aperture range to an existing
- * aperture in case of dma_ops domain allocation or address allocation
- * failure.
- */
-static int alloc_new_range(struct dma_ops_domain *dma_dom,
-                           bool populate, gfp_t gfp)
-{
-        int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
-        struct amd_iommu *iommu;
-        unsigned long i;
-
-#ifdef CONFIG_IOMMU_STRESS
-        populate = false;
-#endif
-
-        if (index >= APERTURE_MAX_RANGES)
-                return -ENOMEM;
-
-        dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
-        if (!dma_dom->aperture[index])
-                return -ENOMEM;
-
-        dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
-        if (!dma_dom->aperture[index]->bitmap)
-                goto out_free;
-
-        dma_dom->aperture[index]->offset = dma_dom->aperture_size;
-
-        if (populate) {
-                unsigned long address = dma_dom->aperture_size;
-                int i, num_ptes = APERTURE_RANGE_PAGES / 512;
-                u64 *pte, *pte_page;
-
-                for (i = 0; i < num_ptes; ++i) {
-                        pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
-                                        &pte_page, gfp);
-                        if (!pte)
-                                goto out_free;
-
-                        dma_dom->aperture[index]->pte_pages[i] = pte_page;
-
-                        address += APERTURE_RANGE_SIZE / 64;
-                }
-        }
-
-        dma_dom->aperture_size += APERTURE_RANGE_SIZE;
-
-        /* Initialize the exclusion range if necessary */
-        for_each_iommu(iommu) {
-                if (iommu->exclusion_start &&
-                    iommu->exclusion_start >= dma_dom->aperture[index]->offset
-                    && iommu->exclusion_start < dma_dom->aperture_size) {
-                        unsigned long startpage;
-                        int pages = iommu_num_pages(iommu->exclusion_start,
-                                                    iommu->exclusion_length,
-                                                    PAGE_SIZE);
-                        startpage = iommu->exclusion_start >> PAGE_SHIFT;
-                        dma_ops_reserve_addresses(dma_dom, startpage, pages);
-                }
-        }
-
-        /*
-         * Check for areas already mapped as present in the new aperture
-         * range and mark those pages as reserved in the allocator. Such
-         * mappings may already exist as a result of requested unity
-         * mappings for devices.
-         */
-        for (i = dma_dom->aperture[index]->offset;
-             i < dma_dom->aperture_size;
-             i += PAGE_SIZE) {
-                u64 *pte = fetch_pte(&dma_dom->domain, i);
-                if (!pte || !IOMMU_PTE_PRESENT(*pte))
-                        continue;
-
-                dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
-        }
-
-        update_domain(&dma_dom->domain);
-
-        return 0;
-
-out_free:
-        update_domain(&dma_dom->domain);
-
-        free_page((unsigned long)dma_dom->aperture[index]->bitmap);
-
-        kfree(dma_dom->aperture[index]);
-        dma_dom->aperture[index] = NULL;
-
-        return -ENOMEM;
-}
-
-static unsigned long dma_ops_area_alloc(struct device *dev,
-                                        struct dma_ops_domain *dom,
-                                        unsigned int pages,
-                                        unsigned long align_mask,
-                                        u64 dma_mask,
-                                        unsigned long start)
-{
-        unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
-        int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
-        int i = start >> APERTURE_RANGE_SHIFT;
-        unsigned long boundary_size;
-        unsigned long address = -1;
-        unsigned long limit;
-
-        next_bit >>= PAGE_SHIFT;
-
-        boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
-                        PAGE_SIZE) >> PAGE_SHIFT;
-
-        for (;i < max_index; ++i) {
-                unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
-
-                if (dom->aperture[i]->offset >= dma_mask)
-                        break;
-
-                limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
-                                               dma_mask >> PAGE_SHIFT);
-
-                address = iommu_area_alloc(dom->aperture[i]->bitmap,
-                                           limit, next_bit, pages, 0,
-                                            boundary_size, align_mask);
-                if (address != -1) {
-                        address = dom->aperture[i]->offset +
-                                  (address << PAGE_SHIFT);
-                        dom->next_address = address + (pages << PAGE_SHIFT);
-                        break;
-                }
-
-                next_bit = 0;
-        }
-
-        return address;
-}
-
-static unsigned long dma_ops_alloc_addresses(struct device *dev,
-                                             struct dma_ops_domain *dom,
-                                             unsigned int pages,
-                                             unsigned long align_mask,
-                                             u64 dma_mask)
-{
-        unsigned long address;
-
-#ifdef CONFIG_IOMMU_STRESS
-        dom->next_address = 0;
-        dom->need_flush = true;
-#endif
-
-        address = dma_ops_area_alloc(dev, dom, pages, align_mask,
-                                     dma_mask, dom->next_address);
-
-        if (address == -1) {
-                dom->next_address = 0;
-                address = dma_ops_area_alloc(dev, dom, pages, align_mask,
-                                             dma_mask, 0);
-                dom->need_flush = true;
-        }
-
-        if (unlikely(address == -1))
-                address = DMA_ERROR_CODE;
-
-        WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
-
-        return address;
-}
-
-/*
- * The address free function.
- *
- * called with domain->lock held
- */
-static void dma_ops_free_addresses(struct dma_ops_domain *dom,
-                                   unsigned long address,
-                                   unsigned int pages)
-{
-        unsigned i = address >> APERTURE_RANGE_SHIFT;
-        struct aperture_range *range = dom->aperture[i];
-
-        BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
-
-#ifdef CONFIG_IOMMU_STRESS
-        if (i < 4)
-                return;
-#endif
-
-        if (address >= dom->next_address)
-                dom->need_flush = true;
-
-        address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
-
-        bitmap_clear(range->bitmap, address, pages);
-
-}
-
-/****************************************************************************
- *
- * The next functions belong to the domain allocation. A domain is
- * allocated for every IOMMU as the default domain. If device isolation
- * is enabled, every device get its own domain. The most important thing
- * about domains is the page table mapping the DMA address space they
- * contain.
- *
- ****************************************************************************/
-
-/*
- * This function adds a protection domain to the global protection domain list
- */
-static void add_domain_to_list(struct protection_domain *domain)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&amd_iommu_pd_lock, flags);
-        list_add(&domain->list, &amd_iommu_pd_list);
-        spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
-}
-
-/*
- * This function removes a protection domain to the global
- * protection domain list
- */
-static void del_domain_from_list(struct protection_domain *domain)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&amd_iommu_pd_lock, flags);
-        list_del(&domain->list);
-        spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
-}
-
-static u16 domain_id_alloc(void)
-{
-        unsigned long flags;
-        int id;
-
-        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
-        id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
-        BUG_ON(id == 0);
-        if (id > 0 && id < MAX_DOMAIN_ID)
-                __set_bit(id, amd_iommu_pd_alloc_bitmap);
-        else
-                id = 0;
-        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
-
-        return id;
-}
-
-static void domain_id_free(int id)
-{
-        unsigned long flags;
-
-        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
-        if (id > 0 && id < MAX_DOMAIN_ID)
-                __clear_bit(id, amd_iommu_pd_alloc_bitmap);
-        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
-}
-
-static void free_pagetable(struct protection_domain *domain)
-{
-        int i, j;
-        u64 *p1, *p2, *p3;
-
-        p1 = domain->pt_root;
-
-        if (!p1)
-                return;
-
-        for (i = 0; i < 512; ++i) {
-                if (!IOMMU_PTE_PRESENT(p1[i]))
-                        continue;
-
-                p2 = IOMMU_PTE_PAGE(p1[i]);
-                for (j = 0; j < 512; ++j) {
-                        if (!IOMMU_PTE_PRESENT(p2[j]))
-                                continue;
-                        p3 = IOMMU_PTE_PAGE(p2[j]);
-                        free_page((unsigned long)p3);
-                }
-
-                free_page((unsigned long)p2);
-        }
-
-        free_page((unsigned long)p1);
-
-        domain->pt_root = NULL;
-}
-
-/*
- * Free a domain, only used if something went wrong in the
- * allocation path and we need to free an already allocated page table
- */
-static void dma_ops_domain_free(struct dma_ops_domain *dom)
-{
-        int i;
-
-        if (!dom)
-                return;
-
-        del_domain_from_list(&dom->domain);
-
-        free_pagetable(&dom->domain);
-
-        for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
-                if (!dom->aperture[i])
-                        continue;
-                free_page((unsigned long)dom->aperture[i]->bitmap);
-                kfree(dom->aperture[i]);
-        }
-
-        kfree(dom);
-}
-
-/*
- * Allocates a new protection domain usable for the dma_ops functions.
- * It also initializes the page table and the address allocator data
- * structures required for the dma_ops interface
- */
-static struct dma_ops_domain *dma_ops_domain_alloc(void)
-{
-        struct dma_ops_domain *dma_dom;
-
-        dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
-        if (!dma_dom)
-                return NULL;
-
-        spin_lock_init(&dma_dom->domain.lock);
-
-        dma_dom->domain.id = domain_id_alloc();
-        if (dma_dom->domain.id == 0)
-                goto free_dma_dom;
-        INIT_LIST_HEAD(&dma_dom->domain.dev_list);
-        dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
-        dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
-        dma_dom->domain.flags = PD_DMA_OPS_MASK;
-        dma_dom->domain.priv = dma_dom;
-        if (!dma_dom->domain.pt_root)
-                goto free_dma_dom;
-
-        dma_dom->need_flush = false;
-        dma_dom->target_dev = 0xffff;
-
-        add_domain_to_list(&dma_dom->domain);
-
-        if (alloc_new_range(dma_dom, true, GFP_KERNEL))
-                goto free_dma_dom;
-
-        /*
-         * mark the first page as allocated so we never return 0 as
-         * a valid dma-address. So we can use 0 as error value
-         */
-        dma_dom->aperture[0]->bitmap[0] = 1;
-        dma_dom->next_address = 0;
-
-
-        return dma_dom;
-
-free_dma_dom:
-        dma_ops_domain_free(dma_dom);
-
-        return NULL;
-}
-
-/*
- * little helper function to check whether a given protection domain is a
- * dma_ops domain
- */
-static bool dma_ops_domain(struct protection_domain *domain)
-{
-        return domain->flags & PD_DMA_OPS_MASK;
-}
-
-static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
-{
-        u64 pte_root = virt_to_phys(domain->pt_root);
-        u32 flags = 0;
-
-        pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
-                    << DEV_ENTRY_MODE_SHIFT;
-        pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
-
-        if (ats)
-                flags |= DTE_FLAG_IOTLB;
-
-        amd_iommu_dev_table[devid].data[3] |= flags;
-        amd_iommu_dev_table[devid].data[2]  = domain->id;
-        amd_iommu_dev_table[devid].data[1]  = upper_32_bits(pte_root);
-        amd_iommu_dev_table[devid].data[0]  = lower_32_bits(pte_root);
-}
-
-static void clear_dte_entry(u16 devid)
-{
-        /* remove entry from the device table seen by the hardware */
-        amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
-        amd_iommu_dev_table[devid].data[1] = 0;
-        amd_iommu_dev_table[devid].data[2] = 0;
-
-        amd_iommu_apply_erratum_63(devid);
-}
-
-static void do_attach(struct device *dev, struct protection_domain *domain)
-{
-        struct iommu_dev_data *dev_data;
-        struct amd_iommu *iommu;
-        struct pci_dev *pdev;
-        bool ats = false;
-        u16 devid;
-
-        devid    = get_device_id(dev);
-        iommu    = amd_iommu_rlookup_table[devid];
-        dev_data = get_dev_data(dev);
-        pdev     = to_pci_dev(dev);
-
-        if (amd_iommu_iotlb_sup)
-                ats = pci_ats_enabled(pdev);
-
-        /* Update data structures */
-        dev_data->domain = domain;
-        list_add(&dev_data->list, &domain->dev_list);
-        set_dte_entry(devid, domain, ats);
-
-        /* Do reference counting */
-        domain->dev_iommu[iommu->index] += 1;
-        domain->dev_cnt                 += 1;
-
-        /* Flush the DTE entry */
-        device_flush_dte(dev);
-}
-
-static void do_detach(struct device *dev)
-{
-        struct iommu_dev_data *dev_data;
-        struct amd_iommu *iommu;
-        u16 devid;
-
-        devid    = get_device_id(dev);
-        iommu    = amd_iommu_rlookup_table[devid];
-        dev_data = get_dev_data(dev);
-
-        /* decrease reference counters */
-        dev_data->domain->dev_iommu[iommu->index] -= 1;
-        dev_data->domain->dev_cnt                 -= 1;
-
-        /* Update data structures */
-        dev_data->domain = NULL;
-        list_del(&dev_data->list);
-        clear_dte_entry(devid);
-
-        /* Flush the DTE entry */
-        device_flush_dte(dev);
-}
-
-/*
- * If a device is not yet associated with a domain, this function does
- * assigns it visible for the hardware
- */
-static int __attach_device(struct device *dev,
-                           struct protection_domain *domain)
-{
-        struct iommu_dev_data *dev_data, *alias_data;
-        int ret;
-
-        dev_data   = get_dev_data(dev);
-        alias_data = get_dev_data(dev_data->alias);
-
-        if (!alias_data)
-                return -EINVAL;
-
-        /* lock domain */
-        spin_lock(&domain->lock);
-
-        /* Some sanity checks */
-        ret = -EBUSY;
-        if (alias_data->domain != NULL &&
-            alias_data->domain != domain)
-                goto out_unlock;
-
-        if (dev_data->domain != NULL &&
-            dev_data->domain != domain)
-                goto out_unlock;
-
-        /* Do real assignment */
-        if (dev_data->alias != dev) {
-                alias_data = get_dev_data(dev_data->alias);
-                if (alias_data->domain == NULL)
-                        do_attach(dev_data->alias, domain);
-
-                atomic_inc(&alias_data->bind);
-        }
-
-        if (dev_data->domain == NULL)
-                do_attach(dev, domain);
-
-        atomic_inc(&dev_data->bind);
-
-        ret = 0;
-
-out_unlock:
-
-        /* ready */
-        spin_unlock(&domain->lock);
-
-        return ret;
-}
-
-/*
- * If a device is not yet associated with a domain, this function does
- * assigns it visible for the hardware
- */
-static int attach_device(struct device *dev,
-                         struct protection_domain *domain)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-        unsigned long flags;
-        int ret;
-
-        if (amd_iommu_iotlb_sup)
-                pci_enable_ats(pdev, PAGE_SHIFT);
-
-        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
-        ret = __attach_device(dev, domain);
-        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
-
-        /*
-         * We might boot into a crash-kernel here. The crashed kernel
-         * left the caches in the IOMMU dirty. So we have to flush
-         * here to evict all dirty stuff.
-         */
-        domain_flush_tlb_pde(domain);
-
-        return ret;
-}
-
-/*
- * Removes a device from a protection domain (unlocked)
- */
-static void __detach_device(struct device *dev)
-{
-        struct iommu_dev_data *dev_data = get_dev_data(dev);
-        struct iommu_dev_data *alias_data;
-        struct protection_domain *domain;
-        unsigned long flags;
-
-        BUG_ON(!dev_data->domain);
-
-        domain = dev_data->domain;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        if (dev_data->alias != dev) {
-                alias_data = get_dev_data(dev_data->alias);
-                if (atomic_dec_and_test(&alias_data->bind))
-                        do_detach(dev_data->alias);
-        }
-
-        if (atomic_dec_and_test(&dev_data->bind))
-                do_detach(dev);
-
-        spin_unlock_irqrestore(&domain->lock, flags);
-
-        /*
-         * If we run in passthrough mode the device must be assigned to the
-         * passthrough domain if it is detached from any other domain.
-         * Make sure we can deassign from the pt_domain itself.
-         */
-        if (iommu_pass_through &&
-            (dev_data->domain == NULL && domain != pt_domain))
-                __attach_device(dev, pt_domain);
-}
-
-/*
- * Removes a device from a protection domain (with devtable_lock held)
- */
-static void detach_device(struct device *dev)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-        unsigned long flags;
-
-        /* lock device table */
-        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
-        __detach_device(dev);
-        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
-
-        if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev))
-                pci_disable_ats(pdev);
-}
-
-/*
- * Find out the protection domain structure for a given PCI device. This
- * will give us the pointer to the page table root for example.
- */
-static struct protection_domain *domain_for_device(struct device *dev)
-{
-        struct protection_domain *dom;
-        struct iommu_dev_data *dev_data, *alias_data;
-        unsigned long flags;
-        u16 devid;
-
-        devid      = get_device_id(dev);
-        dev_data   = get_dev_data(dev);
-        alias_data = get_dev_data(dev_data->alias);
-        if (!alias_data)
-                return NULL;
-
-        read_lock_irqsave(&amd_iommu_devtable_lock, flags);
-        dom = dev_data->domain;
-        if (dom == NULL &&
-            alias_data->domain != NULL) {
-                __attach_device(dev, alias_data->domain);
-                dom = alias_data->domain;
-        }
-
-        read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
-
-        return dom;
-}
-
-static int device_change_notifier(struct notifier_block *nb,
-                                  unsigned long action, void *data)
-{
-        struct device *dev = data;
-        u16 devid;
-        struct protection_domain *domain;
-        struct dma_ops_domain *dma_domain;
-        struct amd_iommu *iommu;
-        unsigned long flags;
-
-        if (!check_device(dev))
-                return 0;
-
-        devid  = get_device_id(dev);
-        iommu  = amd_iommu_rlookup_table[devid];
-
-        switch (action) {
-        case BUS_NOTIFY_UNBOUND_DRIVER:
-
-                domain = domain_for_device(dev);
-
-                if (!domain)
-                        goto out;
-                if (iommu_pass_through)
-                        break;
-                detach_device(dev);
-                break;
-        case BUS_NOTIFY_ADD_DEVICE:
-
-                iommu_init_device(dev);
-
-                domain = domain_for_device(dev);
-
-                /* allocate a protection domain if a device is added */
-                dma_domain = find_protection_domain(devid);
-                if (dma_domain)
-                        goto out;
-                dma_domain = dma_ops_domain_alloc();
-                if (!dma_domain)
-                        goto out;
-                dma_domain->target_dev = devid;
-
-                spin_lock_irqsave(&iommu_pd_list_lock, flags);
-                list_add_tail(&dma_domain->list, &iommu_pd_list);
-                spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
-
-                break;
-        case BUS_NOTIFY_DEL_DEVICE:
-
-                iommu_uninit_device(dev);
-
-        default:
-                goto out;
-        }
-
-        device_flush_dte(dev);
-        iommu_completion_wait(iommu);
-
-out:
-        return 0;
-}
-
-static struct notifier_block device_nb = {
-        .notifier_call = device_change_notifier,
-};
-
-void amd_iommu_init_notifier(void)
-{
-        bus_register_notifier(&pci_bus_type, &device_nb);
-}
-
-/*****************************************************************************
- *
- * The next functions belong to the dma_ops mapping/unmapping code.
- *
- *****************************************************************************/
-
-/*
- * In the dma_ops path we only have the struct device. This function
- * finds the corresponding IOMMU, the protection domain and the
- * requestor id for a given device.
- * If the device is not yet associated with a domain this is also done
- * in this function.
- */
-static struct protection_domain *get_domain(struct device *dev)
-{
-        struct protection_domain *domain;
-        struct dma_ops_domain *dma_dom;
-        u16 devid = get_device_id(dev);
-
-        if (!check_device(dev))
-                return ERR_PTR(-EINVAL);
-
-        domain = domain_for_device(dev);
-        if (domain != NULL && !dma_ops_domain(domain))
-                return ERR_PTR(-EBUSY);
-
-        if (domain != NULL)
-                return domain;
-
-        /* Device not bount yet - bind it */
-        dma_dom = find_protection_domain(devid);
-        if (!dma_dom)
-                dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
-        attach_device(dev, &dma_dom->domain);
-        DUMP_printk("Using protection domain %d for device %s\n",
-                    dma_dom->domain.id, dev_name(dev));
-
-        return &dma_dom->domain;
-}
-
-static void update_device_table(struct protection_domain *domain)
-{
-        struct iommu_dev_data *dev_data;
-
-        list_for_each_entry(dev_data, &domain->dev_list, list) {
-                struct pci_dev *pdev = to_pci_dev(dev_data->dev);
-                u16 devid = get_device_id(dev_data->dev);
-                set_dte_entry(devid, domain, pci_ats_enabled(pdev));
-        }
-}
-
-static void update_domain(struct protection_domain *domain)
-{
-        if (!domain->updated)
-                return;
-
-        update_device_table(domain);
-
-        domain_flush_devices(domain);
-        domain_flush_tlb_pde(domain);
-
-        domain->updated = false;
-}
-
-/*
- * This function fetches the PTE for a given address in the aperture
- */
-static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
-                            unsigned long address)
-{
-        struct aperture_range *aperture;
-        u64 *pte, *pte_page;
-
-        aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
-        if (!aperture)
-                return NULL;
-
-        pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
-        if (!pte) {
-                pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
-                                GFP_ATOMIC);
-                aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
-        } else
-                pte += PM_LEVEL_INDEX(0, address);
-
-        update_domain(&dom->domain);
-
-        return pte;
-}
-
-/*
- * This is the generic map function. It maps one 4kb page at paddr to
- * the given address in the DMA address space for the domain.
- */
-static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
-                                     unsigned long address,
-                                     phys_addr_t paddr,
-                                     int direction)
-{
-        u64 *pte, __pte;
-
-        WARN_ON(address > dom->aperture_size);
-
-        paddr &= PAGE_MASK;
-
-        pte  = dma_ops_get_pte(dom, address);
-        if (!pte)
-                return DMA_ERROR_CODE;
-
-        __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
-
-        if (direction == DMA_TO_DEVICE)
-                __pte |= IOMMU_PTE_IR;
-        else if (direction == DMA_FROM_DEVICE)
-                __pte |= IOMMU_PTE_IW;
-        else if (direction == DMA_BIDIRECTIONAL)
-                __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
-
-        WARN_ON(*pte);
-
-        *pte = __pte;
-
-        return (dma_addr_t)address;
-}
-
-/*
- * The generic unmapping function for on page in the DMA address space.
- */
-static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
-                                 unsigned long address)
-{
-        struct aperture_range *aperture;
-        u64 *pte;
-
-        if (address >= dom->aperture_size)
-                return;
-
-        aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
-        if (!aperture)
-                return;
-
-        pte  = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
-        if (!pte)
-                return;
-
-        pte += PM_LEVEL_INDEX(0, address);
-
-        WARN_ON(!*pte);
-
-        *pte = 0ULL;
-}
-
-/*
- * This function contains common code for mapping of a physically
- * contiguous memory region into DMA address space. It is used by all
- * mapping functions provided with this IOMMU driver.
- * Must be called with the domain lock held.
- */
-static dma_addr_t __map_single(struct device *dev,
-                               struct dma_ops_domain *dma_dom,
-                               phys_addr_t paddr,
-                               size_t size,
-                               int dir,
-                               bool align,
-                               u64 dma_mask)
-{
-        dma_addr_t offset = paddr & ~PAGE_MASK;
-        dma_addr_t address, start, ret;
-        unsigned int pages;
-        unsigned long align_mask = 0;
-        int i;
-
-        pages = iommu_num_pages(paddr, size, PAGE_SIZE);
-        paddr &= PAGE_MASK;
-
-        INC_STATS_COUNTER(total_map_requests);
-
-        if (pages > 1)
-                INC_STATS_COUNTER(cross_page);
-
-        if (align)
-                align_mask = (1UL << get_order(size)) - 1;
-
-retry:
-        address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
-                                          dma_mask);
-        if (unlikely(address == DMA_ERROR_CODE)) {
-                /*
-                 * setting next_address here will let the address
-                 * allocator only scan the new allocated range in the
-                 * first run. This is a small optimization.
-                 */
-                dma_dom->next_address = dma_dom->aperture_size;
-
-                if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
-                        goto out;
-
-                /*
-                 * aperture was successfully enlarged by 128 MB, try
-                 * allocation again
-                 */
-                goto retry;
-        }
-
-        start = address;
-        for (i = 0; i < pages; ++i) {
-                ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
-                if (ret == DMA_ERROR_CODE)
-                        goto out_unmap;
-
-                paddr += PAGE_SIZE;
-                start += PAGE_SIZE;
-        }
-        address += offset;
-
-        ADD_STATS_COUNTER(alloced_io_mem, size);
-
-        if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
-                domain_flush_tlb(&dma_dom->domain);
-                dma_dom->need_flush = false;
-        } else if (unlikely(amd_iommu_np_cache))
-                domain_flush_pages(&dma_dom->domain, address, size);
-
-out:
-        return address;
-
-out_unmap:
-
-        for (--i; i >= 0; --i) {
-                start -= PAGE_SIZE;
-                dma_ops_domain_unmap(dma_dom, start);
-        }
-
-        dma_ops_free_addresses(dma_dom, address, pages);
-
-        return DMA_ERROR_CODE;
-}
-
-/*
- * Does the reverse of the __map_single function. Must be called with
- * the domain lock held too
- */
-static void __unmap_single(struct dma_ops_domain *dma_dom,
-                           dma_addr_t dma_addr,
-                           size_t size,
-                           int dir)
-{
-        dma_addr_t flush_addr;
-        dma_addr_t i, start;
-        unsigned int pages;
-
-        if ((dma_addr == DMA_ERROR_CODE) ||
-            (dma_addr + size > dma_dom->aperture_size))
-                return;
-
-        flush_addr = dma_addr;
-        pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
-        dma_addr &= PAGE_MASK;
-        start = dma_addr;
-
-        for (i = 0; i < pages; ++i) {
-                dma_ops_domain_unmap(dma_dom, start);
-                start += PAGE_SIZE;
-        }
-
-        SUB_STATS_COUNTER(alloced_io_mem, size);
-
-        dma_ops_free_addresses(dma_dom, dma_addr, pages);
-
-        if (amd_iommu_unmap_flush || dma_dom->need_flush) {
-                domain_flush_pages(&dma_dom->domain, flush_addr, size);
-                dma_dom->need_flush = false;
-        }
-}
-
-/*
- * The exported map_single function for dma_ops.
- */
-static dma_addr_t map_page(struct device *dev, struct page *page,
-                           unsigned long offset, size_t size,
-                           enum dma_data_direction dir,
-                           struct dma_attrs *attrs)
-{
-        unsigned long flags;
-        struct protection_domain *domain;
-        dma_addr_t addr;
-        u64 dma_mask;
-        phys_addr_t paddr = page_to_phys(page) + offset;
-
-        INC_STATS_COUNTER(cnt_map_single);
-
-        domain = get_domain(dev);
-        if (PTR_ERR(domain) == -EINVAL)
-                return (dma_addr_t)paddr;
-        else if (IS_ERR(domain))
-                return DMA_ERROR_CODE;
-
-        dma_mask = *dev->dma_mask;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        addr = __map_single(dev, domain->priv, paddr, size, dir, false,
-                            dma_mask);
-        if (addr == DMA_ERROR_CODE)
-                goto out;
-
-        domain_flush_complete(domain);
-
-out:
-        spin_unlock_irqrestore(&domain->lock, flags);
-
-        return addr;
-}
-
-/*
- * The exported unmap_single function for dma_ops.
- */
-static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
-                       enum dma_data_direction dir, struct dma_attrs *attrs)
-{
-        unsigned long flags;
-        struct protection_domain *domain;
-
-        INC_STATS_COUNTER(cnt_unmap_single);
-
-        domain = get_domain(dev);
-        if (IS_ERR(domain))
-                return;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        __unmap_single(domain->priv, dma_addr, size, dir);
-
-        domain_flush_complete(domain);
-
-        spin_unlock_irqrestore(&domain->lock, flags);
-}
-
-/*
- * This is a special map_sg function which is used if we should map a
- * device which is not handled by an AMD IOMMU in the system.
- */
-static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
-                           int nelems, int dir)
-{
-        struct scatterlist *s;
-        int i;
-
-        for_each_sg(sglist, s, nelems, i) {
-                s->dma_address = (dma_addr_t)sg_phys(s);
-                s->dma_length  = s->length;
-        }
-
-        return nelems;
-}
-
-/*
- * The exported map_sg function for dma_ops (handles scatter-gather
- * lists).
- */
-static int map_sg(struct device *dev, struct scatterlist *sglist,
-                  int nelems, enum dma_data_direction dir,
-                  struct dma_attrs *attrs)
-{
-        unsigned long flags;
-        struct protection_domain *domain;
-        int i;
-        struct scatterlist *s;
-        phys_addr_t paddr;
-        int mapped_elems = 0;
-        u64 dma_mask;
-
-        INC_STATS_COUNTER(cnt_map_sg);
-
-        domain = get_domain(dev);
-        if (PTR_ERR(domain) == -EINVAL)
-                return map_sg_no_iommu(dev, sglist, nelems, dir);
-        else if (IS_ERR(domain))
-                return 0;
-
-        dma_mask = *dev->dma_mask;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        for_each_sg(sglist, s, nelems, i) {
-                paddr = sg_phys(s);
-
-                s->dma_address = __map_single(dev, domain->priv,
-                                              paddr, s->length, dir, false,
-                                              dma_mask);
-
-                if (s->dma_address) {
-                        s->dma_length = s->length;
-                        mapped_elems++;
-                } else
-                        goto unmap;
-        }
-
-        domain_flush_complete(domain);
-
-out:
-        spin_unlock_irqrestore(&domain->lock, flags);
-
-        return mapped_elems;
-unmap:
-        for_each_sg(sglist, s, mapped_elems, i) {
-                if (s->dma_address)
-                        __unmap_single(domain->priv, s->dma_address,
-                                       s->dma_length, dir);
-                s->dma_address = s->dma_length = 0;
-        }
-
-        mapped_elems = 0;
-
-        goto out;
-}
-
-/*
- * The exported map_sg function for dma_ops (handles scatter-gather
- * lists).
- */
-static void unmap_sg(struct device *dev, struct scatterlist *sglist,
-                     int nelems, enum dma_data_direction dir,
-                     struct dma_attrs *attrs)
-{
-        unsigned long flags;
-        struct protection_domain *domain;
-        struct scatterlist *s;
-        int i;
-
-        INC_STATS_COUNTER(cnt_unmap_sg);
-
-        domain = get_domain(dev);
-        if (IS_ERR(domain))
-                return;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        for_each_sg(sglist, s, nelems, i) {
-                __unmap_single(domain->priv, s->dma_address,
-                               s->dma_length, dir);
-                s->dma_address = s->dma_length = 0;
-        }
-
-        domain_flush_complete(domain);
-
-        spin_unlock_irqrestore(&domain->lock, flags);
-}
-
-/*
- * The exported alloc_coherent function for dma_ops.
- */
-static void *alloc_coherent(struct device *dev, size_t size,
-                            dma_addr_t *dma_addr, gfp_t flag)
-{
-        unsigned long flags;
-        void *virt_addr;
-        struct protection_domain *domain;
-        phys_addr_t paddr;
-        u64 dma_mask = dev->coherent_dma_mask;
-
-        INC_STATS_COUNTER(cnt_alloc_coherent);
-
-        domain = get_domain(dev);
-        if (PTR_ERR(domain) == -EINVAL) {
-                virt_addr = (void *)__get_free_pages(flag, get_order(size));
-                *dma_addr = __pa(virt_addr);
-                return virt_addr;
-        } else if (IS_ERR(domain))
-                return NULL;
-
-        dma_mask  = dev->coherent_dma_mask;
-        flag     &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
-        flag     |= __GFP_ZERO;
-
-        virt_addr = (void *)__get_free_pages(flag, get_order(size));
-        if (!virt_addr)
-                return NULL;
-
-        paddr = virt_to_phys(virt_addr);
-
-        if (!dma_mask)
-                dma_mask = *dev->dma_mask;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        *dma_addr = __map_single(dev, domain->priv, paddr,
-                                 size, DMA_BIDIRECTIONAL, true, dma_mask);
-
-        if (*dma_addr == DMA_ERROR_CODE) {
-                spin_unlock_irqrestore(&domain->lock, flags);
-                goto out_free;
-        }
-
-        domain_flush_complete(domain);
-
-        spin_unlock_irqrestore(&domain->lock, flags);
-
-        return virt_addr;
-
-out_free:
-
-        free_pages((unsigned long)virt_addr, get_order(size));
-
-        return NULL;
-}
-
-/*
- * The exported free_coherent function for dma_ops.
- */
-static void free_coherent(struct device *dev, size_t size,
-                          void *virt_addr, dma_addr_t dma_addr)
-{
-        unsigned long flags;
-        struct protection_domain *domain;
-
-        INC_STATS_COUNTER(cnt_free_coherent);
-
-        domain = get_domain(dev);
-        if (IS_ERR(domain))
-                goto free_mem;
-
-        spin_lock_irqsave(&domain->lock, flags);
-
-        __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
-
-        domain_flush_complete(domain);
-
-        spin_unlock_irqrestore(&domain->lock, flags);
-
-free_mem:
-        free_pages((unsigned long)virt_addr, get_order(size));
-}
-
-/*
- * This function is called by the DMA layer to find out if we can handle a
- * particular device. It is part of the dma_ops.
- */
-static int amd_iommu_dma_supported(struct device *dev, u64 mask)
-{
-        return check_device(dev);
-}
-
-/*
- * The function for pre-allocating protection domains.
- *
- * If the driver core informs the DMA layer if a driver grabs a device
- * we don't need to preallocate the protection domains anymore.
- * For now we have to.
- */
-static void prealloc_protection_domains(void)
-{
-        struct pci_dev *dev = NULL;
-        struct dma_ops_domain *dma_dom;
-        u16 devid;
-
-        for_each_pci_dev(dev) {
-
-                /* Do we handle this device? */
-                if (!check_device(&dev->dev))
-                        continue;
-
-                /* Is there already any domain for it? */
-                if (domain_for_device(&dev->dev))
-                        continue;
-
-                devid = get_device_id(&dev->dev);
-
-                dma_dom = dma_ops_domain_alloc();
-                if (!dma_dom)
-                        continue;
-                init_unity_mappings_for_device(dma_dom, devid);
-                dma_dom->target_dev = devid;
-
-                attach_device(&dev->dev, &dma_dom->domain);
-
-                list_add_tail(&dma_dom->list, &iommu_pd_list);
-        }
-}
-
-static struct dma_map_ops amd_iommu_dma_ops = {
-        .alloc_coherent = alloc_coherent,
-        .free_coherent = free_coherent,
-        .map_page = map_page,
-        .unmap_page = unmap_page,
-        .map_sg = map_sg,
-        .unmap_sg = unmap_sg,
-        .dma_supported = amd_iommu_dma_supported,
-};
-
-static unsigned device_dma_ops_init(void)
-{
-        struct pci_dev *pdev = NULL;
-        unsigned unhandled = 0;
-
-        for_each_pci_dev(pdev) {
-                if (!check_device(&pdev->dev)) {
-                        unhandled += 1;
-                        continue;
-                }
-
-                pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
-        }
-
-        return unhandled;
-}
-
-/*
- * The function which clues the AMD IOMMU driver into dma_ops.
- */
-
-void __init amd_iommu_init_api(void)
-{
-        register_iommu(&amd_iommu_ops);
-}
-
-int __init amd_iommu_init_dma_ops(void)
-{
-        struct amd_iommu *iommu;
-        int ret, unhandled;
-
-        /*
-         * first allocate a default protection domain for every IOMMU we
-         * found in the system. Devices not assigned to any other
-         * protection domain will be assigned to the default one.
-         */
-        for_each_iommu(iommu) {
-                iommu->default_dom = dma_ops_domain_alloc();
-                if (iommu->default_dom == NULL)
-                        return -ENOMEM;
-                iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
-                ret = iommu_init_unity_mappings(iommu);
-                if (ret)
-                        goto free_domains;
-        }
-
-        /*
-         * Pre-allocate the protection domains for each device.
-         */
-        prealloc_protection_domains();
-
-        iommu_detected = 1;
-        swiotlb = 0;
-
-        /* Make the driver finally visible to the drivers */
-        unhandled = device_dma_ops_init();
-        if (unhandled && max_pfn > MAX_DMA32_PFN) {
-                /* There are unhandled devices - initialize swiotlb for them */
-                swiotlb = 1;
-        }
-
-        amd_iommu_stats_init();
-
-        return 0;
-
-free_domains:
-
-        for_each_iommu(iommu) {
-                if (iommu->default_dom)
-                        dma_ops_domain_free(iommu->default_dom);
-        }
-
-        return ret;
-}
-
-/*****************************************************************************
- *
- * The following functions belong to the exported interface of AMD IOMMU
- *
- * This interface allows access to lower level functions of the IOMMU
- * like protection domain handling and assignement of devices to domains
- * which is not possible with the dma_ops interface.
- *
- *****************************************************************************/
-
-static void cleanup_domain(struct protection_domain *domain)
-{
-        struct iommu_dev_data *dev_data, *next;
-        unsigned long flags;
-
-        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
-
-        list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
-                struct device *dev = dev_data->dev;
-
-                __detach_device(dev);
-                atomic_set(&dev_data->bind, 0);
-        }
-
-        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
-}
-
-static void protection_domain_free(struct protection_domain *domain)
-{
-        if (!domain)
-                return;
-
-        del_domain_from_list(domain);
-
-        if (domain->id)
-                domain_id_free(domain->id);
-
-        kfree(domain);
-}
-
-static struct protection_domain *protection_domain_alloc(void)
-{
-        struct protection_domain *domain;
-
-        domain = kzalloc(sizeof(*domain), GFP_KERNEL);
-        if (!domain)
-                return NULL;
-
-        spin_lock_init(&domain->lock);
-        mutex_init(&domain->api_lock);
-        domain->id = domain_id_alloc();
-        if (!domain->id)
-                goto out_err;
-        INIT_LIST_HEAD(&domain->dev_list);
-
-        add_domain_to_list(domain);
-
-        return domain;
-
-out_err:
-        kfree(domain);
-
-        return NULL;
-}
-
-static int amd_iommu_domain_init(struct iommu_domain *dom)
-{
-        struct protection_domain *domain;
-
-        domain = protection_domain_alloc();
-        if (!domain)
-                goto out_free;
-
-        domain->mode    = PAGE_MODE_3_LEVEL;
-        domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
-        if (!domain->pt_root)
-                goto out_free;
-
-        dom->priv = domain;
-
-        return 0;
-
-out_free:
-        protection_domain_free(domain);
-
-        return -ENOMEM;
-}
-
-static void amd_iommu_domain_destroy(struct iommu_domain *dom)
-{
-        struct protection_domain *domain = dom->priv;
-
-        if (!domain)
-                return;
-
-        if (domain->dev_cnt > 0)
-                cleanup_domain(domain);
-
-        BUG_ON(domain->dev_cnt != 0);
-
-        free_pagetable(domain);
-
-        protection_domain_free(domain);
-
-        dom->priv = NULL;
-}
-
-static void amd_iommu_detach_device(struct iommu_domain *dom,
-                                    struct device *dev)
-{
-        struct iommu_dev_data *dev_data = dev->archdata.iommu;
-        struct amd_iommu *iommu;
-        u16 devid;
-
-        if (!check_device(dev))
-                return;
-
-        devid = get_device_id(dev);
-
-        if (dev_data->domain != NULL)
-                detach_device(dev);
-
-        iommu = amd_iommu_rlookup_table[devid];
-        if (!iommu)
-                return;
-
-        device_flush_dte(dev);
-        iommu_completion_wait(iommu);
-}
-
-static int amd_iommu_attach_device(struct iommu_domain *dom,
-                                   struct device *dev)
-{
-        struct protection_domain *domain = dom->priv;
-        struct iommu_dev_data *dev_data;
-        struct amd_iommu *iommu;
-        int ret;
-        u16 devid;
-
-        if (!check_device(dev))
-                return -EINVAL;
-
-        dev_data = dev->archdata.iommu;
-
-        devid = get_device_id(dev);
-
-        iommu = amd_iommu_rlookup_table[devid];
-        if (!iommu)
-                return -EINVAL;
-
-        if (dev_data->domain)
-                detach_device(dev);
-
-        ret = attach_device(dev, domain);
-
-        iommu_completion_wait(iommu);
-
-        return ret;
-}
-
-static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
-                         phys_addr_t paddr, int gfp_order, int iommu_prot)
-{
-        unsigned long page_size = 0x1000UL << gfp_order;
-        struct protection_domain *domain = dom->priv;
-        int prot = 0;
-        int ret;
-
-        if (iommu_prot & IOMMU_READ)
-                prot |= IOMMU_PROT_IR;
-        if (iommu_prot & IOMMU_WRITE)
-                prot |= IOMMU_PROT_IW;
-
-        mutex_lock(&domain->api_lock);
-        ret = iommu_map_page(domain, iova, paddr, prot, page_size);
-        mutex_unlock(&domain->api_lock);
-
-        return ret;
-}
-
-static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
-                           int gfp_order)
-{
-        struct protection_domain *domain = dom->priv;
-        unsigned long page_size, unmap_size;
-
-        page_size  = 0x1000UL << gfp_order;
-
-        mutex_lock(&domain->api_lock);
-        unmap_size = iommu_unmap_page(domain, iova, page_size);
-        mutex_unlock(&domain->api_lock);
-
-        domain_flush_tlb_pde(domain);
-
-        return get_order(unmap_size);
-}
-
-static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
-                                          unsigned long iova)
-{
-        struct protection_domain *domain = dom->priv;
-        unsigned long offset_mask;
-        phys_addr_t paddr;
-        u64 *pte, __pte;
-
-        pte = fetch_pte(domain, iova);
-
-        if (!pte || !IOMMU_PTE_PRESENT(*pte))
-                return 0;
-
-        if (PM_PTE_LEVEL(*pte) == 0)
-                offset_mask = PAGE_SIZE - 1;
-        else
-                offset_mask = PTE_PAGE_SIZE(*pte) - 1;
-
-        __pte = *pte & PM_ADDR_MASK;
-        paddr = (__pte & ~offset_mask) | (iova & offset_mask);
-
-        return paddr;
-}
-
-static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
-                                    unsigned long cap)
-{
-        switch (cap) {
-        case IOMMU_CAP_CACHE_COHERENCY:
-                return 1;
-        }
-
-        return 0;
-}
-
-static struct iommu_ops amd_iommu_ops = {
-        .domain_init = amd_iommu_domain_init,
-        .domain_destroy = amd_iommu_domain_destroy,
-        .attach_dev = amd_iommu_attach_device,
-        .detach_dev = amd_iommu_detach_device,
-        .map = amd_iommu_map,
-        .unmap = amd_iommu_unmap,
-        .iova_to_phys = amd_iommu_iova_to_phys,
-        .domain_has_cap = amd_iommu_domain_has_cap,
-};
-
-/*****************************************************************************
- *
- * The next functions do a basic initialization of IOMMU for pass through
- * mode
- *
- * In passthrough mode the IOMMU is initialized and enabled but not used for
- * DMA-API translation.
- *
- *****************************************************************************/
-
-int __init amd_iommu_init_passthrough(void)
-{
-        struct amd_iommu *iommu;
-        struct pci_dev *dev = NULL;
-        u16 devid;
-
-        /* allocate passthrough domain */
-        pt_domain = protection_domain_alloc();
-        if (!pt_domain)
-                return -ENOMEM;
-
-        pt_domain->mode |= PAGE_MODE_NONE;
-
-        for_each_pci_dev(dev) {
-                if (!check_device(&dev->dev))
-                        continue;
-
-                devid = get_device_id(&dev->dev);
-
-                iommu = amd_iommu_rlookup_table[devid];
-                if (!iommu)
-                        continue;
-
-                attach_device(&dev->dev, pt_domain);
-        }
-
-        pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
-
-        return 0;
-}
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
deleted file mode 100644
index bfc8453bd98d..000000000000
--- a/arch/x86/kernel/amd_iommu_init.c
+++ /dev/null
@@ -1,1572 +0,0 @@
-/*
- * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *         Leo Duran <leo.duran@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <linux/pci.h>
-#include <linux/acpi.h>
-#include <linux/list.h>
-#include <linux/slab.h>
-#include <linux/syscore_ops.h>
-#include <linux/interrupt.h>
-#include <linux/msi.h>
-#include <asm/pci-direct.h>
-#include <asm/amd_iommu_proto.h>
-#include <asm/amd_iommu_types.h>
-#include <asm/amd_iommu.h>
-#include <asm/iommu.h>
-#include <asm/gart.h>
-#include <asm/x86_init.h>
-#include <asm/iommu_table.h>
-/*
- * definitions for the ACPI scanning code
- */
-#define IVRS_HEADER_LENGTH 48
-
-#define ACPI_IVHD_TYPE                  0x10
-#define ACPI_IVMD_TYPE_ALL              0x20
-#define ACPI_IVMD_TYPE                  0x21
-#define ACPI_IVMD_TYPE_RANGE            0x22
-
-#define IVHD_DEV_ALL                    0x01
-#define IVHD_DEV_SELECT                 0x02
-#define IVHD_DEV_SELECT_RANGE_START     0x03
-#define IVHD_DEV_RANGE_END              0x04
-#define IVHD_DEV_ALIAS                  0x42
-#define IVHD_DEV_ALIAS_RANGE            0x43
-#define IVHD_DEV_EXT_SELECT             0x46
-#define IVHD_DEV_EXT_SELECT_RANGE       0x47
-
-#define IVHD_FLAG_HT_TUN_EN_MASK        0x01
-#define IVHD_FLAG_PASSPW_EN_MASK        0x02
-#define IVHD_FLAG_RESPASSPW_EN_MASK     0x04
-#define IVHD_FLAG_ISOC_EN_MASK          0x08
-
-#define IVMD_FLAG_EXCL_RANGE            0x08
-#define IVMD_FLAG_UNITY_MAP             0x01
-
-#define ACPI_DEVFLAG_INITPASS           0x01
-#define ACPI_DEVFLAG_EXTINT             0x02
-#define ACPI_DEVFLAG_NMI                0x04
-#define ACPI_DEVFLAG_SYSMGT1            0x10
-#define ACPI_DEVFLAG_SYSMGT2            0x20
-#define ACPI_DEVFLAG_LINT0              0x40
-#define ACPI_DEVFLAG_LINT1              0x80
-#define ACPI_DEVFLAG_ATSDIS             0x10000000
-
-/*
- * ACPI table definitions
- *
- * These data structures are laid over the table to parse the important values
- * out of it.
- */
-
-/*
- * structure describing one IOMMU in the ACPI table. Typically followed by one
- * or more ivhd_entrys.
- */
-struct ivhd_header {
-        u8 type;
-        u8 flags;
-        u16 length;
-        u16 devid;
-        u16 cap_ptr;
-        u64 mmio_phys;
-        u16 pci_seg;
-        u16 info;
-        u32 reserved;
-} __attribute__((packed));
-
-/*
- * A device entry describing which devices a specific IOMMU translates and
- * which requestor ids they use.
- */
-struct ivhd_entry {
-        u8 type;
-        u16 devid;
-        u8 flags;
-        u32 ext;
-} __attribute__((packed));
-
-/*
- * An AMD IOMMU memory definition structure. It defines things like exclusion
- * ranges for devices and regions that should be unity mapped.
- */
-struct ivmd_header {
-        u8 type;
-        u8 flags;
-        u16 length;
-        u16 devid;
-        u16 aux;
-        u64 resv;
-        u64 range_start;
-        u64 range_length;
-} __attribute__((packed));
-
-bool amd_iommu_dump;
-
-static int __initdata amd_iommu_detected;
-static bool __initdata amd_iommu_disabled;
-
-u16 amd_iommu_last_bdf;                 /* largest PCI device id we have
-                                           to handle */
-LIST_HEAD(amd_iommu_unity_map);         /* a list of required unity mappings
-                                           we find in ACPI */
-bool amd_iommu_unmap_flush;             /* if true, flush on every unmap */
-
-LIST_HEAD(amd_iommu_list);              /* list of all AMD IOMMUs in the
-                                           system */
-
-/* Array to assign indices to IOMMUs*/
-struct amd_iommu *amd_iommus[MAX_IOMMUS];
-int amd_iommus_present;
-
-/* IOMMUs have a non-present cache? */
-bool amd_iommu_np_cache __read_mostly;
-bool amd_iommu_iotlb_sup __read_mostly = true;
-
-/*
- * The ACPI table parsing functions set this variable on an error
- */
-static int __initdata amd_iommu_init_err;
-
-/*
- * List of protection domains - used during resume
- */
-LIST_HEAD(amd_iommu_pd_list);
-spinlock_t amd_iommu_pd_lock;
-
-/*
- * Pointer to the device table which is shared by all AMD IOMMUs
- * it is indexed by the PCI device id or the HT unit id and contains
- * information about the domain the device belongs to as well as the
- * page table root pointer.
- */
-struct dev_table_entry *amd_iommu_dev_table;
-
-/*
- * The alias table is a driver specific data structure which contains the
- * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
- * More than one device can share the same requestor id.
- */
-u16 *amd_iommu_alias_table;
-
-/*
- * The rlookup table is used to find the IOMMU which is responsible
- * for a specific device. It is also indexed by the PCI device id.
- */
-struct amd_iommu **amd_iommu_rlookup_table;
-
-/*
- * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
- * to know which ones are already in use.
- */
-unsigned long *amd_iommu_pd_alloc_bitmap;
-
-static u32 dev_table_size;      /* size of the device table */
-static u32 alias_table_size;    /* size of the alias table */
-static u32 rlookup_table_size;  /* size if the rlookup table */
-
-/*
- * This function flushes all internal caches of
- * the IOMMU used by this driver.
- */
-extern void iommu_flush_all_caches(struct amd_iommu *iommu);
-
-static inline void update_last_devid(u16 devid)
-{
-        if (devid > amd_iommu_last_bdf)
-                amd_iommu_last_bdf = devid;
-}
-
-static inline unsigned long tbl_size(int entry_size)
-{
-        unsigned shift = PAGE_SHIFT +
-                         get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
-
-        return 1UL << shift;
-}
-
-/* Access to l1 and l2 indexed register spaces */
-
-static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
-{
-        u32 val;
-
-        pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
-        pci_read_config_dword(iommu->dev, 0xfc, &val);
-        return val;
-}
-
-static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
-{
-        pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
-        pci_write_config_dword(iommu->dev, 0xfc, val);
-        pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
-}
-
-static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
-{
-        u32 val;
-
-        pci_write_config_dword(iommu->dev, 0xf0, address);
-        pci_read_config_dword(iommu->dev, 0xf4, &val);
-        return val;
-}
-
-static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
-{
-        pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
-        pci_write_config_dword(iommu->dev, 0xf4, val);
-}
-
-/****************************************************************************
- *
- * AMD IOMMU MMIO register space handling functions
- *
- * These functions are used to program the IOMMU device registers in
- * MMIO space required for that driver.
- *
- ****************************************************************************/
-
-/*
- * This function set the exclusion range in the IOMMU. DMA accesses to the
- * exclusion range are passed through untranslated
- */
-static void iommu_set_exclusion_range(struct amd_iommu *iommu)
-{
-        u64 start = iommu->exclusion_start & PAGE_MASK;
-        u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
-        u64 entry;
-
-        if (!iommu->exclusion_start)
-                return;
-
-        entry = start | MMIO_EXCL_ENABLE_MASK;
-        memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
-                        &entry, sizeof(entry));
-
-        entry = limit;
-        memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
-                        &entry, sizeof(entry));
-}
-
-/* Programs the physical address of the device table into the IOMMU hardware */
-static void __init iommu_set_device_table(struct amd_iommu *iommu)
-{
-        u64 entry;
-
-        BUG_ON(iommu->mmio_base == NULL);
-
-        entry = virt_to_phys(amd_iommu_dev_table);
-        entry |= (dev_table_size >> 12) - 1;
-        memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
-                        &entry, sizeof(entry));
-}
-
-/* Generic functions to enable/disable certain features of the IOMMU. */
-static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
-{
-        u32 ctrl;
-
-        ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
-        ctrl |= (1 << bit);
-        writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
-}
-
-static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
-{
-        u32 ctrl;
-
-        ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
-        ctrl &= ~(1 << bit);
-        writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
-}
-
-/* Function to enable the hardware */
-static void iommu_enable(struct amd_iommu *iommu)
-{
-        static const char * const feat_str[] = {
-                "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
-                "IA", "GA", "HE", "PC", NULL
-        };
-        int i;
-
-        printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
-               dev_name(&iommu->dev->dev), iommu->cap_ptr);
-
-        if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
-                printk(KERN_CONT " extended features: ");
-                for (i = 0; feat_str[i]; ++i)
-                        if (iommu_feature(iommu, (1ULL << i)))
-                                printk(KERN_CONT " %s", feat_str[i]);
-        }
-        printk(KERN_CONT "\n");
-
-        iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
-}
-
-static void iommu_disable(struct amd_iommu *iommu)
-{
-        /* Disable command buffer */
-        iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
-
-        /* Disable event logging and event interrupts */
-        iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
-        iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
-
-        /* Disable IOMMU hardware itself */
-        iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
-}
-
-/*
- * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
- * the system has one.
- */
-static u8 * __init iommu_map_mmio_space(u64 address)
-{
-        u8 *ret;
-
-        if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
-                pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
-                        address);
-                pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
-                return NULL;
-        }
-
-        ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
-        if (ret != NULL)
-                return ret;
-
-        release_mem_region(address, MMIO_REGION_LENGTH);
-
-        return NULL;
-}
-
-static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
-{
-        if (iommu->mmio_base)
-                iounmap(iommu->mmio_base);
-        release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
-}
-
-/****************************************************************************
- *
- * The functions below belong to the first pass of AMD IOMMU ACPI table
- * parsing. In this pass we try to find out the highest device id this
- * code has to handle. Upon this information the size of the shared data
- * structures is determined later.
- *
- ****************************************************************************/
-
-/*
- * This function calculates the length of a given IVHD entry
- */
-static inline int ivhd_entry_length(u8 *ivhd)
-{
-        return 0x04 << (*ivhd >> 6);
-}
-
-/*
- * This function reads the last device id the IOMMU has to handle from the PCI
- * capability header for this IOMMU
- */
-static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
-{
-        u32 cap;
-
-        cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
-        update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
-
-        return 0;
-}
-
-/*
- * After reading the highest device id from the IOMMU PCI capability header
- * this function looks if there is a higher device id defined in the ACPI table
- */
-static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
-{
-        u8 *p = (void *)h, *end = (void *)h;
-        struct ivhd_entry *dev;
-
-        p += sizeof(*h);
-        end += h->length;
-
-        find_last_devid_on_pci(PCI_BUS(h->devid),
-                        PCI_SLOT(h->devid),
-                        PCI_FUNC(h->devid),
-                        h->cap_ptr);
-
-        while (p < end) {
-                dev = (struct ivhd_entry *)p;
-                switch (dev->type) {
-                case IVHD_DEV_SELECT:
-                case IVHD_DEV_RANGE_END:
-                case IVHD_DEV_ALIAS:
-                case IVHD_DEV_EXT_SELECT:
-                        /* all the above subfield types refer to device ids */
-                        update_last_devid(dev->devid);
-                        break;
-                default:
-                        break;
-                }
-                p += ivhd_entry_length(p);
-        }
-
-        WARN_ON(p != end);
-
-        return 0;
-}
-
-/*
- * Iterate over all IVHD entries in the ACPI table and find the highest device
- * id which we need to handle. This is the first of three functions which parse
- * the ACPI table. So we check the checksum here.
- */
-static int __init find_last_devid_acpi(struct acpi_table_header *table)
-{
-        int i;
-        u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
-        struct ivhd_header *h;
-
-        /*
-         * Validate checksum here so we don't need to do it when
-         * we actually parse the table
-         */
-        for (i = 0; i < table->length; ++i)
-                checksum += p[i];
-        if (checksum != 0) {
-                /* ACPI table corrupt */
-                amd_iommu_init_err = -ENODEV;
-                return 0;
-        }
-
-        p += IVRS_HEADER_LENGTH;
-
-        end += table->length;
-        while (p < end) {
-                h = (struct ivhd_header *)p;
-                switch (h->type) {
-                case ACPI_IVHD_TYPE:
-                        find_last_devid_from_ivhd(h);
-                        break;
-                default:
-                        break;
-                }
-                p += h->length;
-        }
-        WARN_ON(p != end);
-
-        return 0;
-}
-
-/****************************************************************************
- *
- * The following functions belong the the code path which parses the ACPI table
- * the second time. In this ACPI parsing iteration we allocate IOMMU specific
- * data structures, initialize the device/alias/rlookup table and also
- * basically initialize the hardware.
- *
- ****************************************************************************/
-
-/*
- * Allocates the command buffer. This buffer is per AMD IOMMU. We can
- * write commands to that buffer later and the IOMMU will execute them
- * asynchronously
- */
-static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
-{
-        u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
-                        get_order(CMD_BUFFER_SIZE));
-
-        if (cmd_buf == NULL)
-                return NULL;
-
-        iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
-
-        return cmd_buf;
-}
-
-/*
- * This function resets the command buffer if the IOMMU stopped fetching
- * commands from it.
- */
-void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
-{
-        iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
-
-        writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
-        writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
-
-        iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
-}
-
-/*
- * This function writes the command buffer address to the hardware and
- * enables it.
- */
-static void iommu_enable_command_buffer(struct amd_iommu *iommu)
-{
-        u64 entry;
-
-        BUG_ON(iommu->cmd_buf == NULL);
-
-        entry = (u64)virt_to_phys(iommu->cmd_buf);
-        entry |= MMIO_CMD_SIZE_512;
-
-        memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
-                    &entry, sizeof(entry));
-
-        amd_iommu_reset_cmd_buffer(iommu);
-        iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
-}
-
-static void __init free_command_buffer(struct amd_iommu *iommu)
-{
-        free_pages((unsigned long)iommu->cmd_buf,
-                   get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
-}
-
-/* allocates the memory where the IOMMU will log its events to */
-static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
-{
-        iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
-                                                get_order(EVT_BUFFER_SIZE));
-
-        if (iommu->evt_buf == NULL)
-                return NULL;
-
-        iommu->evt_buf_size = EVT_BUFFER_SIZE;
-
-        return iommu->evt_buf;
-}
-
-static void iommu_enable_event_buffer(struct amd_iommu *iommu)
-{
-        u64 entry;
-
-        BUG_ON(iommu->evt_buf == NULL);
-
-        entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
-
-        memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
-                    &entry, sizeof(entry));
-
-        /* set head and tail to zero manually */
-        writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
-        writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
-
-        iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
-}
-
-static void __init free_event_buffer(struct amd_iommu *iommu)
-{
-        free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
-}
-
-/* sets a specific bit in the device table entry. */
-static void set_dev_entry_bit(u16 devid, u8 bit)
-{
-        int i = (bit >> 5) & 0x07;
-        int _bit = bit & 0x1f;
-
-        amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
-}
-
-static int get_dev_entry_bit(u16 devid, u8 bit)
-{
-        int i = (bit >> 5) & 0x07;
-        int _bit = bit & 0x1f;
-
-        return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
-}
-
-
-void amd_iommu_apply_erratum_63(u16 devid)
-{
-        int sysmgt;
-
-        sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
-                 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
-
-        if (sysmgt == 0x01)
-                set_dev_entry_bit(devid, DEV_ENTRY_IW);
-}
-
-/* Writes the specific IOMMU for a device into the rlookup table */
-static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
-{
-        amd_iommu_rlookup_table[devid] = iommu;
-}
-
-/*
- * This function takes the device specific flags read from the ACPI
- * table and sets up the device table entry with that information
- */
-static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
-                                           u16 devid, u32 flags, u32 ext_flags)
-{
-        if (flags & ACPI_DEVFLAG_INITPASS)
-                set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
-        if (flags & ACPI_DEVFLAG_EXTINT)
-                set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
-        if (flags & ACPI_DEVFLAG_NMI)
-                set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
-        if (flags & ACPI_DEVFLAG_SYSMGT1)
-                set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
-        if (flags & ACPI_DEVFLAG_SYSMGT2)
-                set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
-        if (flags & ACPI_DEVFLAG_LINT0)
-                set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
-        if (flags & ACPI_DEVFLAG_LINT1)
-                set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
-
-        amd_iommu_apply_erratum_63(devid);
-
-        set_iommu_for_device(iommu, devid);
-}
-
-/*
- * Reads the device exclusion range from ACPI and initialize IOMMU with
- * it
- */
-static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
-{
-        struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
-
-        if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
-                return;
-
-        if (iommu) {
-                /*
-                 * We only can configure exclusion ranges per IOMMU, not
-                 * per device. But we can enable the exclusion range per
-                 * device. This is done here
-                 */
-                set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
-                iommu->exclusion_start = m->range_start;
-                iommu->exclusion_length = m->range_length;
-        }
-}
-
-/*
- * This function reads some important data from the IOMMU PCI space and
- * initializes the driver data structure with it. It reads the hardware
- * capabilities and the first/last device entries
- */
-static void __init init_iommu_from_pci(struct amd_iommu *iommu)
-{
-        int cap_ptr = iommu->cap_ptr;
-        u32 range, misc, low, high;
-        int i, j;
-
-        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
-                              &iommu->cap);
-        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
-                              &range);
-        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
-                              &misc);
-
-        iommu->first_device = calc_devid(MMIO_GET_BUS(range),
-                                         MMIO_GET_FD(range));
-        iommu->last_device = calc_devid(MMIO_GET_BUS(range),
-                                        MMIO_GET_LD(range));
-        iommu->evt_msi_num = MMIO_MSI_NUM(misc);
-
-        if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
-                amd_iommu_iotlb_sup = false;
-
-        /* read extended feature bits */
-        low  = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
-        high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
-
-        iommu->features = ((u64)high << 32) | low;
-
-        if (!is_rd890_iommu(iommu->dev))
-                return;
-
-        /*
-         * Some rd890 systems may not be fully reconfigured by the BIOS, so
-         * it's necessary for us to store this information so it can be
-         * reprogrammed on resume
-         */
-
-        pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
-                              &iommu->stored_addr_lo);
-        pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
-                              &iommu->stored_addr_hi);
-
-        /* Low bit locks writes to configuration space */
-        iommu->stored_addr_lo &= ~1;
-
-        for (i = 0; i < 6; i++)
-                for (j = 0; j < 0x12; j++)
-                        iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
-
-        for (i = 0; i < 0x83; i++)
-                iommu->stored_l2[i] = iommu_read_l2(iommu, i);
-}
-
-/*
- * Takes a pointer to an AMD IOMMU entry in the ACPI table and
- * initializes the hardware and our data structures with it.
- */
-static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
-                                        struct ivhd_header *h)
-{
-        u8 *p = (u8 *)h;
-        u8 *end = p, flags = 0;
-        u16 devid = 0, devid_start = 0, devid_to = 0;
-        u32 dev_i, ext_flags = 0;
-        bool alias = false;
-        struct ivhd_entry *e;
-
-        /*
-         * First save the recommended feature enable bits from ACPI
-         */
-        iommu->acpi_flags = h->flags;
-
-        /*
-         * Done. Now parse the device entries
-         */
-        p += sizeof(struct ivhd_header);
-        end += h->length;
-
-
-        while (p < end) {
-                e = (struct ivhd_entry *)p;
-                switch (e->type) {
-                case IVHD_DEV_ALL:
-
-                        DUMP_printk("  DEV_ALL\t\t\t first devid: %02x:%02x.%x"
-                                    " last device %02x:%02x.%x flags: %02x\n",
-                                    PCI_BUS(iommu->first_device),
-                                    PCI_SLOT(iommu->first_device),
-                                    PCI_FUNC(iommu->first_device),
-                                    PCI_BUS(iommu->last_device),
-                                    PCI_SLOT(iommu->last_device),
-                                    PCI_FUNC(iommu->last_device),
-                                    e->flags);
-
-                        for (dev_i = iommu->first_device;
-                                        dev_i <= iommu->last_device; ++dev_i)
-                                set_dev_entry_from_acpi(iommu, dev_i,
-                                                        e->flags, 0);
-                        break;
-                case IVHD_DEV_SELECT:
-
-                        DUMP_printk("  DEV_SELECT\t\t\t devid: %02x:%02x.%x "
-                                    "flags: %02x\n",
-                                    PCI_BUS(e->devid),
-                                    PCI_SLOT(e->devid),
-                                    PCI_FUNC(e->devid),
-                                    e->flags);
-
-                        devid = e->devid;
-                        set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
-                        break;
-                case IVHD_DEV_SELECT_RANGE_START:
-
-                        DUMP_printk("  DEV_SELECT_RANGE_START\t "
-                                    "devid: %02x:%02x.%x flags: %02x\n",
-                                    PCI_BUS(e->devid),
-                                    PCI_SLOT(e->devid),
-                                    PCI_FUNC(e->devid),
-                                    e->flags);
-
-                        devid_start = e->devid;
-                        flags = e->flags;
-                        ext_flags = 0;
-                        alias = false;
-                        break;
-                case IVHD_DEV_ALIAS:
-
-                        DUMP_printk("  DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
-                                    "flags: %02x devid_to: %02x:%02x.%x\n",
-                                    PCI_BUS(e->devid),
-                                    PCI_SLOT(e->devid),
-                                    PCI_FUNC(e->devid),
-                                    e->flags,
-                                    PCI_BUS(e->ext >> 8),
-                                    PCI_SLOT(e->ext >> 8),
-                                    PCI_FUNC(e->ext >> 8));
-
-                        devid = e->devid;
-                        devid_to = e->ext >> 8;
-                        set_dev_entry_from_acpi(iommu, devid   , e->flags, 0);
-                        set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
-                        amd_iommu_alias_table[devid] = devid_to;
-                        break;
-                case IVHD_DEV_ALIAS_RANGE:
-
-                        DUMP_printk("  DEV_ALIAS_RANGE\t\t "
-                                    "devid: %02x:%02x.%x flags: %02x "
-                                    "devid_to: %02x:%02x.%x\n",
-                                    PCI_BUS(e->devid),
-                                    PCI_SLOT(e->devid),
-                                    PCI_FUNC(e->devid),
-                                    e->flags,
-                                    PCI_BUS(e->ext >> 8),
-                                    PCI_SLOT(e->ext >> 8),
-                                    PCI_FUNC(e->ext >> 8));
-
-                        devid_start = e->devid;
-                        flags = e->flags;
-                        devid_to = e->ext >> 8;
-                        ext_flags = 0;
-                        alias = true;
-                        break;
-                case IVHD_DEV_EXT_SELECT:
-
-                        DUMP_printk("  DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
-                                    "flags: %02x ext: %08x\n",
-                                    PCI_BUS(e->devid),
-                                    PCI_SLOT(e->devid),
-                                    PCI_FUNC(e->devid),
-                                    e->flags, e->ext);
-
-                        devid = e->devid;
-                        set_dev_entry_from_acpi(iommu, devid, e->flags,
-                                                e->ext);
-                        break;
-                case IVHD_DEV_EXT_SELECT_RANGE:
-
-                        DUMP_printk("  DEV_EXT_SELECT_RANGE\t devid: "
-                                    "%02x:%02x.%x flags: %02x ext: %08x\n",
-                                    PCI_BUS(e->devid),
-                                    PCI_SLOT(e->devid),
-                                    PCI_FUNC(e->devid),
-                                    e->flags, e->ext);
-
-                        devid_start = e->devid;
-                        flags = e->flags;
-                        ext_flags = e->ext;
-                        alias = false;
-                        break;
-                case IVHD_DEV_RANGE_END:
-
-                        DUMP_printk("  DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
-                                    PCI_BUS(e->devid),
-                                    PCI_SLOT(e->devid),
-                                    PCI_FUNC(e->devid));
-
-                        devid = e->devid;
-                        for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
-                                if (alias) {
-                                        amd_iommu_alias_table[dev_i] = devid_to;
-                                        set_dev_entry_from_acpi(iommu,
-                                                devid_to, flags, ext_flags);
-                                }
-                                set_dev_entry_from_acpi(iommu, dev_i,
-                                                        flags, ext_flags);
-                        }
-                        break;
-                default:
-                        break;
-                }
-
-                p += ivhd_entry_length(p);
-        }
-}
-
-/* Initializes the device->iommu mapping for the driver */
-static int __init init_iommu_devices(struct amd_iommu *iommu)
-{
-        u32 i;
-
-        for (i = iommu->first_device; i <= iommu->last_device; ++i)
-                set_iommu_for_device(iommu, i);
-
-        return 0;
-}
-
-static void __init free_iommu_one(struct amd_iommu *iommu)
-{
-        free_command_buffer(iommu);
-        free_event_buffer(iommu);
-        iommu_unmap_mmio_space(iommu);
-}
-
-static void __init free_iommu_all(void)
-{
-        struct amd_iommu *iommu, *next;
-
-        for_each_iommu_safe(iommu, next) {
-                list_del(&iommu->list);
-                free_iommu_one(iommu);
-                kfree(iommu);
-        }
-}
-
-/*
- * This function clues the initialization function for one IOMMU
- * together and also allocates the command buffer and programs the
- * hardware. It does NOT enable the IOMMU. This is done afterwards.
- */
-static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
-{
-        spin_lock_init(&iommu->lock);
-
-        /* Add IOMMU to internal data structures */
-        list_add_tail(&iommu->list, &amd_iommu_list);
-        iommu->index             = amd_iommus_present++;
-
-        if (unlikely(iommu->index >= MAX_IOMMUS)) {
-                WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
-                return -ENOSYS;
-        }
-
-        /* Index is fine - add IOMMU to the array */
-        amd_iommus[iommu->index] = iommu;
-
-        /*
-         * Copy data from ACPI table entry to the iommu struct
-         */
-        iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
-        if (!iommu->dev)
-                return 1;
-
-        iommu->cap_ptr = h->cap_ptr;
-        iommu->pci_seg = h->pci_seg;
-        iommu->mmio_phys = h->mmio_phys;
-        iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
-        if (!iommu->mmio_base)
-                return -ENOMEM;
-
-        iommu->cmd_buf = alloc_command_buffer(iommu);
-        if (!iommu->cmd_buf)
-                return -ENOMEM;
-
-        iommu->evt_buf = alloc_event_buffer(iommu);
-        if (!iommu->evt_buf)
-                return -ENOMEM;
-
-        iommu->int_enabled = false;
-
-        init_iommu_from_pci(iommu);
-        init_iommu_from_acpi(iommu, h);
-        init_iommu_devices(iommu);
-
-        if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
-                amd_iommu_np_cache = true;
-
-        return pci_enable_device(iommu->dev);
-}
-
-/*
- * Iterates over all IOMMU entries in the ACPI table, allocates the
- * IOMMU structure and initializes it with init_iommu_one()
- */
-static int __init init_iommu_all(struct acpi_table_header *table)
-{
-        u8 *p = (u8 *)table, *end = (u8 *)table;
-        struct ivhd_header *h;
-        struct amd_iommu *iommu;
-        int ret;
-
-        end += table->length;
-        p += IVRS_HEADER_LENGTH;
-
-        while (p < end) {
-                h = (struct ivhd_header *)p;
-                switch (*p) {
-                case ACPI_IVHD_TYPE:
-
-                        DUMP_printk("device: %02x:%02x.%01x cap: %04x "
-                                    "seg: %d flags: %01x info %04x\n",
-                                    PCI_BUS(h->devid), PCI_SLOT(h->devid),
-                                    PCI_FUNC(h->devid), h->cap_ptr,
-                                    h->pci_seg, h->flags, h->info);
-                        DUMP_printk("       mmio-addr: %016llx\n",
-                                    h->mmio_phys);
-
-                        iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
-                        if (iommu == NULL) {
-                                amd_iommu_init_err = -ENOMEM;
-                                return 0;
-                        }
-
-                        ret = init_iommu_one(iommu, h);
-                        if (ret) {
-                                amd_iommu_init_err = ret;
-                                return 0;
-                        }
-                        break;
-                default:
-                        break;
-                }
-                p += h->length;
-
-        }
-        WARN_ON(p != end);
-
-        return 0;
-}
-
-/****************************************************************************
- *
- * The following functions initialize the MSI interrupts for all IOMMUs
- * in the system. Its a bit challenging because there could be multiple
- * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
- * pci_dev.
- *
- ****************************************************************************/
-
-static int iommu_setup_msi(struct amd_iommu *iommu)
-{
-        int r;
-
-        if (pci_enable_msi(iommu->dev))
-                return 1;
-
-        r = request_threaded_irq(iommu->dev->irq,
-                                 amd_iommu_int_handler,
-                                 amd_iommu_int_thread,
-                                 0, "AMD-Vi",
-                                 iommu->dev);
-
-        if (r) {
-                pci_disable_msi(iommu->dev);
-                return 1;
-        }
-
-        iommu->int_enabled = true;
-        iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
-
-        return 0;
-}
-
-static int iommu_init_msi(struct amd_iommu *iommu)
-{
-        if (iommu->int_enabled)
-                return 0;
-
-        if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
-                return iommu_setup_msi(iommu);
-
-        return 1;
-}
-
-/****************************************************************************
- *
- * The next functions belong to the third pass of parsing the ACPI
- * table. In this last pass the memory mapping requirements are
- * gathered (like exclusion and unity mapping reanges).
- *
- ****************************************************************************/
-
-static void __init free_unity_maps(void)
-{
-        struct unity_map_entry *entry, *next;
-
-        list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
-                list_del(&entry->list);
-                kfree(entry);
-        }
-}
-
-/* called when we find an exclusion range definition in ACPI */
-static int __init init_exclusion_range(struct ivmd_header *m)
-{
-        int i;
-
-        switch (m->type) {
-        case ACPI_IVMD_TYPE:
-                set_device_exclusion_range(m->devid, m);
-                break;
-        case ACPI_IVMD_TYPE_ALL:
-                for (i = 0; i <= amd_iommu_last_bdf; ++i)
-                        set_device_exclusion_range(i, m);
-                break;
-        case ACPI_IVMD_TYPE_RANGE:
-                for (i = m->devid; i <= m->aux; ++i)
-                        set_device_exclusion_range(i, m);
-                break;
-        default:
-                break;
-        }
-
-        return 0;
-}
-
-/* called for unity map ACPI definition */
-static int __init init_unity_map_range(struct ivmd_header *m)
-{
-        struct unity_map_entry *e = 0;
-        char *s;
-
-        e = kzalloc(sizeof(*e), GFP_KERNEL);
-        if (e == NULL)
-                return -ENOMEM;
-
-        switch (m->type) {
-        default:
-                kfree(e);
-                return 0;
-        case ACPI_IVMD_TYPE:
-                s = "IVMD_TYPEi\t\t\t";
-                e->devid_start = e->devid_end = m->devid;
-                break;
-        case ACPI_IVMD_TYPE_ALL:
-                s = "IVMD_TYPE_ALL\t\t";
-                e->devid_start = 0;
-                e->devid_end = amd_iommu_last_bdf;
-                break;
-        case ACPI_IVMD_TYPE_RANGE:
-                s = "IVMD_TYPE_RANGE\t\t";
-                e->devid_start = m->devid;
-                e->devid_end = m->aux;
-                break;
-        }
-        e->address_start = PAGE_ALIGN(m->range_start);
-        e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
-        e->prot = m->flags >> 1;
-
-        DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
-                    " range_start: %016llx range_end: %016llx flags: %x\n", s,
-                    PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
-                    PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
-                    PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
-                    e->address_start, e->address_end, m->flags);
-
-        list_add_tail(&e->list, &amd_iommu_unity_map);
-
-        return 0;
-}
-
-/* iterates over all memory definitions we find in the ACPI table */
-static int __init init_memory_definitions(struct acpi_table_header *table)
-{
-        u8 *p = (u8 *)table, *end = (u8 *)table;
-        struct ivmd_header *m;
-
-        end += table->length;
-        p += IVRS_HEADER_LENGTH;
-
-        while (p < end) {
-                m = (struct ivmd_header *)p;
-                if (m->flags & IVMD_FLAG_EXCL_RANGE)
-                        init_exclusion_range(m);
-                else if (m->flags & IVMD_FLAG_UNITY_MAP)
-                        init_unity_map_range(m);
-
-                p += m->length;
-        }
-
-        return 0;
-}
-
-/*
- * Init the device table to not allow DMA access for devices and
- * suppress all page faults
- */
-static void init_device_table(void)
-{
-        u32 devid;
-
-        for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
-                set_dev_entry_bit(devid, DEV_ENTRY_VALID);
-                set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
-        }
-}
-
-static void iommu_init_flags(struct amd_iommu *iommu)
-{
-        iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
-                iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
-
-        iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
-                iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
-
-        iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
-                iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
-
-        iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
-                iommu_feature_disable(iommu, CONTROL_ISOC_EN);
-
-        /*
-         * make IOMMU memory accesses cache coherent
-         */
-        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
-}
-
-static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
-{
-        int i, j;
-        u32 ioc_feature_control;
-        struct pci_dev *pdev = NULL;
-
-        /* RD890 BIOSes may not have completely reconfigured the iommu */
-        if (!is_rd890_iommu(iommu->dev))
-                return;
-
-        /*
-         * First, we need to ensure that the iommu is enabled. This is
-         * controlled by a register in the northbridge
-         */
-        pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
-
-        if (!pdev)
-                return;
-
-        /* Select Northbridge indirect register 0x75 and enable writing */
-        pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
-        pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
-
-        /* Enable the iommu */
-        if (!(ioc_feature_control & 0x1))
-                pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
-
-        pci_dev_put(pdev);
-
-        /* Restore the iommu BAR */
-        pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
-                               iommu->stored_addr_lo);
-        pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
-                               iommu->stored_addr_hi);
-
-        /* Restore the l1 indirect regs for each of the 6 l1s */
-        for (i = 0; i < 6; i++)
-                for (j = 0; j < 0x12; j++)
-                        iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
-
-        /* Restore the l2 indirect regs */
-        for (i = 0; i < 0x83; i++)
-                iommu_write_l2(iommu, i, iommu->stored_l2[i]);
-
-        /* Lock PCI setup registers */
-        pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
-                               iommu->stored_addr_lo | 1);
-}
-
-/*
- * This function finally enables all IOMMUs found in the system after
- * they have been initialized
- */
-static void enable_iommus(void)
-{
-        struct amd_iommu *iommu;
-
-        for_each_iommu(iommu) {
-                iommu_disable(iommu);
-                iommu_init_flags(iommu);
-                iommu_set_device_table(iommu);
-                iommu_enable_command_buffer(iommu);
-                iommu_enable_event_buffer(iommu);
-                iommu_set_exclusion_range(iommu);
-                iommu_init_msi(iommu);
-                iommu_enable(iommu);
-                iommu_flush_all_caches(iommu);
-        }
-}
-
-static void disable_iommus(void)
-{
-        struct amd_iommu *iommu;
-
-        for_each_iommu(iommu)
-                iommu_disable(iommu);
-}
-
-/*
- * Suspend/Resume support
- * disable suspend until real resume implemented
- */
-
-static void amd_iommu_resume(void)
-{
-        struct amd_iommu *iommu;
-
-        for_each_iommu(iommu)
-                iommu_apply_resume_quirks(iommu);
-
-        /* re-load the hardware */
-        enable_iommus();
-
-        /*
-         * we have to flush after the IOMMUs are enabled because a
-         * disabled IOMMU will never execute the commands we send
-         */
-        for_each_iommu(iommu)
-                iommu_flush_all_caches(iommu);
-}
-
-static int amd_iommu_suspend(void)
-{
-        /* disable IOMMUs to go out of the way for BIOS */
-        disable_iommus();
-
-        return 0;
-}
-
-static struct syscore_ops amd_iommu_syscore_ops = {
-        .suspend = amd_iommu_suspend,
-        .resume = amd_iommu_resume,
-};
-
-/*
- * This is the core init function for AMD IOMMU hardware in the system.
- * This function is called from the generic x86 DMA layer initialization
- * code.
- *
- * This function basically parses the ACPI table for AMD IOMMU (IVRS)
- * three times:
- *
- *      1 pass) Find the highest PCI device id the driver has to handle.
- *              Upon this information the size of the data structures is
- *              determined that needs to be allocated.
- *
- *      2 pass) Initialize the data structures just allocated with the
- *              information in the ACPI table about available AMD IOMMUs
- *              in the system. It also maps the PCI devices in the
- *              system to specific IOMMUs
- *
- *      3 pass) After the basic data structures are allocated and
- *              initialized we update them with information about memory
- *              remapping requirements parsed out of the ACPI table in
- *              this last pass.
- *
- * After that the hardware is initialized and ready to go. In the last
- * step we do some Linux specific things like registering the driver in
- * the dma_ops interface and initializing the suspend/resume support
- * functions. Finally it prints some information about AMD IOMMUs and
- * the driver state and enables the hardware.
- */
-static int __init amd_iommu_init(void)
-{
-        int i, ret = 0;
-
-        /*
-         * First parse ACPI tables to find the largest Bus/Dev/Func
-         * we need to handle. Upon this information the shared data
-         * structures for the IOMMUs in the system will be allocated
-         */
-        if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
-                return -ENODEV;
-
-        ret = amd_iommu_init_err;
-        if (ret)
-                goto out;
-
-        dev_table_size     = tbl_size(DEV_TABLE_ENTRY_SIZE);
-        alias_table_size   = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
-        rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
-
-        ret = -ENOMEM;
-
-        /* Device table - directly used by all IOMMUs */
-        amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
-                                      get_order(dev_table_size));
-        if (amd_iommu_dev_table == NULL)
-                goto out;
-
-        /*
-         * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
-         * IOMMU see for that device
-         */
-        amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
-                        get_order(alias_table_size));
-        if (amd_iommu_alias_table == NULL)
-                goto free;
-
-        /* IOMMU rlookup table - find the IOMMU for a specific device */
-        amd_iommu_rlookup_table = (void *)__get_free_pages(
-                        GFP_KERNEL | __GFP_ZERO,
-                        get_order(rlookup_table_size));
-        if (amd_iommu_rlookup_table == NULL)
-                goto free;
-
-        amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
-                                            GFP_KERNEL | __GFP_ZERO,
-                                            get_order(MAX_DOMAIN_ID/8));
-        if (amd_iommu_pd_alloc_bitmap == NULL)
-                goto free;
-
-        /* init the device table */
-        init_device_table();
-
-        /*
-         * let all alias entries point to itself
-         */
-        for (i = 0; i <= amd_iommu_last_bdf; ++i)
-                amd_iommu_alias_table[i] = i;
-
-        /*
-         * never allocate domain 0 because its used as the non-allocated and
-         * error value placeholder
-         */
-        amd_iommu_pd_alloc_bitmap[0] = 1;
-
-        spin_lock_init(&amd_iommu_pd_lock);
-
-        /*
-         * now the data structures are allocated and basically initialized
-         * start the real acpi table scan
-         */
-        ret = -ENODEV;
-        if (acpi_table_parse("IVRS", init_iommu_all) != 0)
-                goto free;
-
-        if (amd_iommu_init_err) {
-                ret = amd_iommu_init_err;
-                goto free;
-        }
-
-        if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
-                goto free;
-
-        if (amd_iommu_init_err) {
-                ret = amd_iommu_init_err;
-                goto free;
-        }
-
-        ret = amd_iommu_init_devices();
-        if (ret)
-                goto free;
-
-        enable_iommus();
-
-        if (iommu_pass_through)
-                ret = amd_iommu_init_passthrough();
-        else
-                ret = amd_iommu_init_dma_ops();
-
-        if (ret)
-                goto free_disable;
-
-        amd_iommu_init_api();
-
-        amd_iommu_init_notifier();
-
-        register_syscore_ops(&amd_iommu_syscore_ops);
-
-        if (iommu_pass_through)
-                goto out;
-
-        if (amd_iommu_unmap_flush)
-                printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
-        else
-                printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
-
-        x86_platform.iommu_shutdown = disable_iommus;
-out:
-        return ret;
-
-free_disable:
-        disable_iommus();
-
-free:
-        amd_iommu_uninit_devices();
-
-        free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
-                   get_order(MAX_DOMAIN_ID/8));
-
-        free_pages((unsigned long)amd_iommu_rlookup_table,
-                   get_order(rlookup_table_size));
-
-        free_pages((unsigned long)amd_iommu_alias_table,
-                   get_order(alias_table_size));
-
-        free_pages((unsigned long)amd_iommu_dev_table,
-                   get_order(dev_table_size));
-
-        free_iommu_all();
-
-        free_unity_maps();
-
-#ifdef CONFIG_GART_IOMMU
-        /*
-         * We failed to initialize the AMD IOMMU - try fallback to GART
-         * if possible.
-         */
-        gart_iommu_init();
-
-#endif
-
-        goto out;
-}
-
-/****************************************************************************
- *
- * Early detect code. This code runs at IOMMU detection time in the DMA
- * layer. It just looks if there is an IVRS ACPI table to detect AMD
- * IOMMUs
- *
- ****************************************************************************/
-static int __init early_amd_iommu_detect(struct acpi_table_header *table)
-{
-        return 0;
-}
-
-int __init amd_iommu_detect(void)
-{
-        if (no_iommu || (iommu_detected && !gart_iommu_aperture))
-                return -ENODEV;
-
-        if (amd_iommu_disabled)
-                return -ENODEV;
-
-        if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
-                iommu_detected = 1;
-                amd_iommu_detected = 1;
-                x86_init.iommu.iommu_init = amd_iommu_init;
-
-                /* Make sure ACS will be enabled */
-                pci_request_acs();
-                return 1;
-        }
-        return -ENODEV;
-}
-
-/****************************************************************************
- *
- * Parsing functions for the AMD IOMMU specific kernel command line
- * options.
- *
- ****************************************************************************/
-
-static int __init parse_amd_iommu_dump(char *str)
-{
-        amd_iommu_dump = true;
-
-        return 1;
-}
-
-static int __init parse_amd_iommu_options(char *str)
-{
-        for (; *str; ++str) {
-                if (strncmp(str, "fullflush", 9) == 0)
-                        amd_iommu_unmap_flush = true;
-                if (strncmp(str, "off", 3) == 0)
-                        amd_iommu_disabled = true;
-        }
-
-        return 1;
-}
-
-__setup("amd_iommu_dump", parse_amd_iommu_dump);
-__setup("amd_iommu=", parse_amd_iommu_options);
-
-IOMMU_INIT_FINISH(amd_iommu_detect,
-                  gart_iommu_hole_init,
-                  0,
-                  0);
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 289e92862fd9..afdc3f756dea 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -27,15 +27,12 @@
  * timer, but by default APB timer has higher rating than local APIC timers.
  */
 
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
 #include <linux/delay.h>
+#include <linux/dw_apb_timer.h>
 #include <linux/errno.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
 #include <linux/slab.h>
 #include <linux/pm.h>
-#include <linux/pci.h>
 #include <linux/sfi.h>
 #include <linux/interrupt.h>
 #include <linux/cpu.h>
@@ -44,76 +41,48 @@
 #include <asm/fixmap.h>
 #include <asm/apb_timer.h>
 #include <asm/mrst.h>
+#include <asm/time.h>
 
-#define APBT_MASK                       CLOCKSOURCE_MASK(32)
-#define APBT_SHIFT                      22
 #define APBT_CLOCKEVENT_RATING          110
 #define APBT_CLOCKSOURCE_RATING         250
-#define APBT_MIN_DELTA_USEC             200
 
-#define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt)
 #define APBT_CLOCKEVENT0_NUM   (0)
-#define APBT_CLOCKEVENT1_NUM   (1)
 #define APBT_CLOCKSOURCE_NUM   (2)
 
-static unsigned long apbt_address;
+static phys_addr_t apbt_address;
 static int apb_timer_block_enabled;
 static void __iomem *apbt_virt_address;
-static int phy_cs_timer_id;
 
 /*
  * Common DW APB timer info
  */
-static uint64_t apbt_freq;
-
-static void apbt_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt);
-static int apbt_next_event(unsigned long delta,
-                           struct clock_event_device *evt);
-static cycle_t apbt_read_clocksource(struct clocksource *cs);
-static void apbt_restart_clocksource(struct clocksource *cs);
+static unsigned long apbt_freq;
 
 struct apbt_dev {
-        struct clock_event_device evt;
-        unsigned int num;
-        int cpu;
-        unsigned int irq;
-        unsigned int tick;
-        unsigned int count;
-        unsigned int flags;
-        char name[10];
+        struct dw_apb_clock_event_device        *timer;
+        unsigned int                            num;
+        int                                     cpu;
+        unsigned int                            irq;
+        char                                    name[10];
 };
 
-static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
+static struct dw_apb_clocksource *clocksource_apbt;
 
-#ifdef CONFIG_SMP
-static unsigned int apbt_num_timers_used;
-static struct apbt_dev *apbt_devs;
-#endif
-
-static  inline unsigned long apbt_readl_reg(unsigned long a)
+static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
 {
-        return readl(apbt_virt_address + a);
+        return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
 }
 
-static inline void apbt_writel_reg(unsigned long d, unsigned long a)
-{
-        writel(d, apbt_virt_address + a);
-}
-
-static inline unsigned long apbt_readl(int n, unsigned long a)
-{
-        return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE);
-}
+static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
 
-static inline void apbt_writel(int n, unsigned long d, unsigned long a)
-{
-        writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE);
-}
+#ifdef CONFIG_SMP
+static unsigned int apbt_num_timers_used;
+#endif
 
 static inline void apbt_set_mapping(void)
 {
         struct sfi_timer_table_entry *mtmr;
+        int phy_cs_timer_id = 0;
 
         if (apbt_virt_address) {
                 pr_debug("APBT base already mapped\n");
@@ -125,21 +94,18 @@ static inline void apbt_set_mapping(void)
                        APBT_CLOCKEVENT0_NUM);
                 return;
         }
-        apbt_address = (unsigned long)mtmr->phys_addr;
+        apbt_address = (phys_addr_t)mtmr->phys_addr;
         if (!apbt_address) {
                 printk(KERN_WARNING "No timer base from SFI, use default\n");
                 apbt_address = APBT_DEFAULT_BASE;
         }
         apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
-        if (apbt_virt_address) {
-                pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\
-                         (void *)apbt_address, (void *)apbt_virt_address);
-        } else {
-                pr_debug("Failed mapping APBT phy address at %p\n",\
-                         (void *)apbt_address);
+        if (!apbt_virt_address) {
+                pr_debug("Failed mapping APBT phy address at %lu\n",\
+                         (unsigned long)apbt_address);
                 goto panic_noapbt;
         }
-        apbt_freq = mtmr->freq_hz / USEC_PER_SEC;
+        apbt_freq = mtmr->freq_hz;
         sfi_free_mtmr(mtmr);
 
         /* Now figure out the physical timer id for clocksource device */
@@ -148,9 +114,14 @@ static inline void apbt_set_mapping(void)
                 goto panic_noapbt;
 
         /* Now figure out the physical timer id */
-        phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff)
-                / APBTMRS_REG_SIZE;
-        pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id);
+        pr_debug("Use timer %d for clocksource\n",
+                 (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
+        phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
+                APBTMRS_REG_SIZE;
+
+        clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
+                "apbt0", apbt_virt_address + phy_cs_timer_id *
+                APBTMRS_REG_SIZE, apbt_freq);
         return;
 
 panic_noapbt:
@@ -172,82 +143,6 @@ static inline int is_apbt_capable(void)
         return apbt_virt_address ? 1 : 0;
 }
 
-static struct clocksource clocksource_apbt = {
-        .name           = "apbt",
-        .rating         = APBT_CLOCKSOURCE_RATING,
-        .read           = apbt_read_clocksource,
-        .mask           = APBT_MASK,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-        .resume         = apbt_restart_clocksource,
-};
-
-/* boot APB clock event device */
-static struct clock_event_device apbt_clockevent = {
-        .name           = "apbt0",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = apbt_set_mode,
-        .set_next_event = apbt_next_event,
-        .shift          = APBT_SHIFT,
-        .irq            = 0,
-        .rating         = APBT_CLOCKEVENT_RATING,
-};
-
-/*
- * start count down from 0xffff_ffff. this is done by toggling the enable bit
- * then load initial load count to ~0.
- */
-static void apbt_start_counter(int n)
-{
-        unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
-
-        ctrl &= ~APBTMR_CONTROL_ENABLE;
-        apbt_writel(n, ctrl, APBTMR_N_CONTROL);
-        apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT);
-        /* enable, mask interrupt */
-        ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
-        ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
-        apbt_writel(n, ctrl, APBTMR_N_CONTROL);
-        /* read it once to get cached counter value initialized */
-        apbt_read_clocksource(&clocksource_apbt);
-}
-
-static irqreturn_t apbt_interrupt_handler(int irq, void *data)
-{
-        struct apbt_dev *dev = (struct apbt_dev *)data;
-        struct clock_event_device *aevt = &dev->evt;
-
-        if (!aevt->event_handler) {
-                printk(KERN_INFO "Spurious APBT timer interrupt on %d\n",
-                       dev->num);
-                return IRQ_NONE;
-        }
-        aevt->event_handler(aevt);
-        return IRQ_HANDLED;
-}
-
-static void apbt_restart_clocksource(struct clocksource *cs)
-{
-        apbt_start_counter(phy_cs_timer_id);
-}
-
-static void apbt_enable_int(int n)
-{
-        unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
-        /* clear pending intr */
-        apbt_readl(n, APBTMR_N_EOI);
-        ctrl &= ~APBTMR_CONTROL_INT;
-        apbt_writel(n, ctrl, APBTMR_N_CONTROL);
-}
-
-static void apbt_disable_int(int n)
-{
-        unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
-
-        ctrl |= APBTMR_CONTROL_INT;
-        apbt_writel(n, ctrl, APBTMR_N_CONTROL);
-}
-
-
 static int __init apbt_clockevent_register(void)
 {
         struct sfi_timer_table_entry *mtmr;
@@ -260,45 +155,21 @@ static int __init apbt_clockevent_register(void)
                 return -ENODEV;
         }
 
-        /*
-         * We need to calculate the scaled math multiplication factor for
-         * nanosecond to apbt tick conversion.
-         * mult = (nsec/cycle)*2^APBT_SHIFT
-         */
-        apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz
-                                      , NSEC_PER_SEC, APBT_SHIFT);
-
-        /* Calculate the min / max delta */
-        apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
-                                                           &apbt_clockevent);
-        apbt_clockevent.min_delta_ns = clockevent_delta2ns(
-                APBT_MIN_DELTA_USEC*apbt_freq,
-                &apbt_clockevent);
-        /*
-         * Start apbt with the boot cpu mask and make it
-         * global if not used for per cpu timer.
-         */
-        apbt_clockevent.cpumask = cpumask_of(smp_processor_id());
         adev->num = smp_processor_id();
-        memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
+        adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
+                mrst_timer_options == MRST_TIMER_LAPIC_APBT ?
+                APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
+                adev_virt_addr(adev), 0, apbt_freq);
+        /* Firmware does EOI handling for us. */
+        adev->timer->eoi = NULL;
 
         if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
-                adev->evt.rating = APBT_CLOCKEVENT_RATING - 100;
-                global_clock_event = &adev->evt;
+                global_clock_event = &adev->timer->ced;
                 printk(KERN_DEBUG "%s clockevent registered as global\n",
                        global_clock_event->name);
         }
 
-        if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler,
-                        IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
-                        apbt_clockevent.name, adev)) {
-                printk(KERN_ERR "Failed request IRQ for APBT%d\n",
-                       apbt_clockevent.irq);
-        }
-
-        clockevents_register_device(&adev->evt);
-        /* Start APBT 0 interrupts */
-        apbt_enable_int(APBT_CLOCKEVENT0_NUM);
+        dw_apb_clockevent_register(adev->timer);
 
         sfi_free_mtmr(mtmr);
         return 0;
@@ -316,52 +187,34 @@ static void apbt_setup_irq(struct apbt_dev *adev)
         irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
         /* APB timer irqs are set up as mp_irqs, timer is edge type */
         __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
-
-        if (system_state == SYSTEM_BOOTING) {
-                if (request_irq(adev->irq, apbt_interrupt_handler,
-                                        IRQF_TIMER | IRQF_DISABLED |
-                                        IRQF_NOBALANCING,
-                                        adev->name, adev)) {
-                        printk(KERN_ERR "Failed request IRQ for APBT%d\n",
-                               adev->num);
-                }
-        } else
-                enable_irq(adev->irq);
 }
 
 /* Should be called with per cpu */
 void apbt_setup_secondary_clock(void)
 {
         struct apbt_dev *adev;
-        struct clock_event_device *aevt;
         int cpu;
 
         /* Don't register boot CPU clockevent */
         cpu = smp_processor_id();
         if (!cpu)
                 return;
-        /*
-         * We need to calculate the scaled math multiplication factor for
-         * nanosecond to apbt tick conversion.
-         * mult = (nsec/cycle)*2^APBT_SHIFT
-         */
-        printk(KERN_INFO "Init per CPU clockevent %d\n", cpu);
-        adev = &per_cpu(cpu_apbt_dev, cpu);
-        aevt = &adev->evt;
 
-        memcpy(aevt, &apbt_clockevent, sizeof(*aevt));
-        aevt->cpumask = cpumask_of(cpu);
-        aevt->name = adev->name;
-        aevt->mode = CLOCK_EVT_MODE_UNUSED;
+        adev = &__get_cpu_var(cpu_apbt_dev);
+        if (!adev->timer) {
+                adev->timer = dw_apb_clockevent_init(cpu, adev->name,
+                        APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
+                        adev->irq, apbt_freq);
+                adev->timer->eoi = NULL;
+        } else {
+                dw_apb_clockevent_resume(adev->timer);
+        }
 
-        printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n",
-               cpu, aevt->name, *(u32 *)aevt->cpumask);
+        printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
+               cpu, adev->name, adev->cpu);
 
         apbt_setup_irq(adev);
-
-        clockevents_register_device(aevt);
-
-        apbt_enable_int(cpu);
+        dw_apb_clockevent_register(adev->timer);
 
         return;
 }
@@ -384,13 +237,12 @@ static int apbt_cpuhp_notify(struct notifier_block *n,
 
         switch (action & 0xf) {
         case CPU_DEAD:
-                disable_irq(adev->irq);
-                apbt_disable_int(cpu);
+                dw_apb_clockevent_pause(adev->timer);
                 if (system_state == SYSTEM_RUNNING) {
                         pr_debug("skipping APBT CPU %lu offline\n", cpu);
                 } else if (adev) {
                         pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
-                        free_irq(adev->irq, adev);
+                        dw_apb_clockevent_stop(adev->timer);
                 }
                 break;
         default:
@@ -415,116 +267,16 @@ void apbt_setup_secondary_clock(void) {}
 
 #endif /* CONFIG_SMP */
 
-static void apbt_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt)
-{
-        unsigned long ctrl;
-        uint64_t delta;
-        int timer_num;
-        struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
-
-        BUG_ON(!apbt_virt_address);
-
-        timer_num = adev->num;
-        pr_debug("%s CPU %d timer %d mode=%d\n",
-                 __func__, first_cpu(*evt->cpumask), timer_num, mode);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult;
-                delta >>= apbt_clockevent.shift;
-                ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
-                ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
-                apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-                /*
-                 * DW APB p. 46, have to disable timer before load counter,
-                 * may cause sync problem.
-                 */
-                ctrl &= ~APBTMR_CONTROL_ENABLE;
-                apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-                udelay(1);
-                pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ);
-                apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
-                ctrl |= APBTMR_CONTROL_ENABLE;
-                apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-                break;
-                /* APB timer does not have one-shot mode, use free running mode */
-        case CLOCK_EVT_MODE_ONESHOT:
-                ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
-                /*
-                 * set free running mode, this mode will let timer reload max
-                 * timeout which will give time (3min on 25MHz clock) to rearm
-                 * the next event, therefore emulate the one-shot mode.
-                 */
-                ctrl &= ~APBTMR_CONTROL_ENABLE;
-                ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
-
-                apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-                /* write again to set free running mode */
-                apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-
-                /*
-                 * DW APB p. 46, load counter with all 1s before starting free
-                 * running mode.
-                 */
-                apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT);
-                ctrl &= ~APBTMR_CONTROL_INT;
-                ctrl |= APBTMR_CONTROL_ENABLE;
-                apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-                break;
-
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                apbt_disable_int(timer_num);
-                ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
-                ctrl &= ~APBTMR_CONTROL_ENABLE;
-                apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-                break;
-
-        case CLOCK_EVT_MODE_RESUME:
-                apbt_enable_int(timer_num);
-                break;
-        }
-}
-
-static int apbt_next_event(unsigned long delta,
-                           struct clock_event_device *evt)
-{
-        unsigned long ctrl;
-        int timer_num;
-
-        struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
-
-        timer_num = adev->num;
-        /* Disable timer */
-        ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
-        ctrl &= ~APBTMR_CONTROL_ENABLE;
-        apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-        /* write new count */
-        apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
-        ctrl |= APBTMR_CONTROL_ENABLE;
-        apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
-        return 0;
-}
-
-static cycle_t apbt_read_clocksource(struct clocksource *cs)
-{
-        unsigned long current_count;
-
-        current_count = apbt_readl(phy_cs_timer_id, APBTMR_N_CURRENT_VALUE);
-        return (cycle_t)~current_count;
-}
-
 static int apbt_clocksource_register(void)
 {
         u64 start, now;
         cycle_t t1;
 
         /* Start the counter, use timer 2 as source, timer 0/1 for event */
-        apbt_start_counter(phy_cs_timer_id);
+        dw_apb_clocksource_start(clocksource_apbt);
 
         /* Verify whether apbt counter works */
-        t1 = apbt_read_clocksource(&clocksource_apbt);
+        t1 = dw_apb_clocksource_read(clocksource_apbt);
         rdtscll(start);
 
         /*
@@ -539,10 +291,10 @@ static int apbt_clocksource_register(void)
         } while ((now - start) < 200000UL);
 
         /* APBT is the only always on clocksource, it has to work! */
-        if (t1 == apbt_read_clocksource(&clocksource_apbt))
+        if (t1 == dw_apb_clocksource_read(clocksource_apbt))
                 panic("APBT counter not counting. APBT disabled\n");
 
-        clocksource_register_khz(&clocksource_apbt, (u32)apbt_freq*1000);
+        dw_apb_clocksource_register(clocksource_apbt);
 
         return 0;
 }
@@ -566,10 +318,7 @@ void __init apbt_time_init(void)
         if (apb_timer_block_enabled)
                 return;
         apbt_set_mapping();
-        if (apbt_virt_address) {
-                pr_debug("Found APBT version 0x%lx\n",\
-                         apbt_readl_reg(APBTMRS_COMP_VERSION));
-        } else
+        if (!apbt_virt_address)
                 goto out_noapbt;
         /*
          * Read the frequency and check for a sane value, for ESL model
@@ -577,7 +326,7 @@ void __init apbt_time_init(void)
          */
 
         if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
-                pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq);
+                pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
                 goto out_noapbt;
         }
         if (apbt_clocksource_register()) {
@@ -603,30 +352,20 @@ void __init apbt_time_init(void)
         } else {
                 percpu_timer = 0;
                 apbt_num_timers_used = 1;
-                adev = &per_cpu(cpu_apbt_dev, 0);
-                adev->flags &= ~APBT_DEV_USED;
         }
         pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
 
         /* here we set up per CPU timer data structure */
-        apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used,
-                            GFP_KERNEL);
-        if (!apbt_devs) {
-                printk(KERN_ERR "Failed to allocate APB timer devices\n");
-                return;
-        }
         for (i = 0; i < apbt_num_timers_used; i++) {
                 adev = &per_cpu(cpu_apbt_dev, i);
                 adev->num = i;
                 adev->cpu = i;
                 p_mtmr = sfi_get_mtmr(i);
-                if (p_mtmr) {
-                        adev->tick = p_mtmr->freq_hz;
+                if (p_mtmr)
                         adev->irq = p_mtmr->irq;
-                } else
+                else
                         printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
-                adev->count = 0;
-                sprintf(adev->name, "apbt%d", i);
+                snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
         }
 #endif
 
@@ -638,17 +377,8 @@ out_noapbt:
         panic("failed to enable APB timer\n");
 }
 
-static inline void apbt_disable(int n)
-{
-        if (is_apbt_capable()) {
-                unsigned long ctrl =  apbt_readl(n, APBTMR_N_CONTROL);
-                ctrl &= ~APBTMR_CONTROL_ENABLE;
-                apbt_writel(n, ctrl, APBTMR_N_CONTROL);
-        }
-}
-
 /* called before apb_timer_enable, use early map */
-unsigned long apbt_quick_calibrate()
+unsigned long apbt_quick_calibrate(void)
 {
         int i, scale;
         u64 old, new;
@@ -657,31 +387,31 @@ unsigned long apbt_quick_calibrate()
         u32 loop, shift;
 
         apbt_set_mapping();
-        apbt_start_counter(phy_cs_timer_id);
+        dw_apb_clocksource_start(clocksource_apbt);
 
         /* check if the timer can count down, otherwise return */
-        old = apbt_read_clocksource(&clocksource_apbt);
+        old = dw_apb_clocksource_read(clocksource_apbt);
         i = 10000;
         while (--i) {
-                if (old != apbt_read_clocksource(&clocksource_apbt))
+                if (old != dw_apb_clocksource_read(clocksource_apbt))
                         break;
         }
         if (!i)
                 goto failed;
 
         /* count 16 ms */
-        loop = (apbt_freq * 1000) << 4;
+        loop = (apbt_freq / 1000) << 4;
 
         /* restart the timer to ensure it won't get to 0 in the calibration */
-        apbt_start_counter(phy_cs_timer_id);
+        dw_apb_clocksource_start(clocksource_apbt);
 
-        old = apbt_read_clocksource(&clocksource_apbt);
+        old = dw_apb_clocksource_read(clocksource_apbt);
         old += loop;
 
         t1 = __native_read_tsc();
 
         do {
-                new = apbt_read_clocksource(&clocksource_apbt);
+                new = dw_apb_clocksource_read(clocksource_apbt);
         } while (new < old);
 
         t2 = __native_read_tsc();
@@ -693,7 +423,7 @@ unsigned long apbt_quick_calibrate()
                 return 0;
         }
         scale = (int)div_u64((t2 - t1), loop >> shift);
-        khz = (scale * apbt_freq * 1000) >> shift;
+        khz = (scale * (apbt_freq / 1000)) >> shift;
         printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
         return khz;
 failed:
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b9338b8cf420..b24be38c8cf8 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -27,6 +27,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/delay.h>
 #include <linux/timex.h>
+#include <linux/i8253.h>
 #include <linux/dmar.h>
 #include <linux/init.h>
 #include <linux/cpu.h>
@@ -39,7 +40,6 @@
 #include <asm/pgalloc.h>
 #include <asm/atomic.h>
 #include <asm/mpspec.h>
-#include <asm/i8253.h>
 #include <asm/i8259.h>
 #include <asm/proto.h>
 #include <asm/apic.h>
@@ -48,6 +48,7 @@
 #include <asm/hpet.h>
 #include <asm/idle.h>
 #include <asm/mtrr.h>
+#include <asm/time.h>
 #include <asm/smp.h>
 #include <asm/mce.h>
 #include <asm/tsc.h>
@@ -1429,7 +1430,7 @@ void enable_x2apic(void)
         rdmsr(MSR_IA32_APICBASE, msr, msr2);
         if (!(msr & X2APIC_ENABLE)) {
                 printk_once(KERN_INFO "Enabling x2apic\n");
-                wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+                wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
         }
 }
 #endif /* CONFIG_X86_X2APIC */
@@ -1943,10 +1944,28 @@ void disconnect_bsp_APIC(int virt_wire_setup)
 
 void __cpuinit generic_processor_info(int apicid, int version)
 {
-        int cpu;
+        int cpu, max = nr_cpu_ids;
+        bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
+                                phys_cpu_present_map);
+
+        /*
+         * If boot cpu has not been detected yet, then only allow upto
+         * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
+         */
+        if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
+            apicid != boot_cpu_physical_apicid) {
+                int thiscpu = max + disabled_cpus - 1;
+
+                pr_warning(
+                        "ACPI: NR_CPUS/possible_cpus limit of %i almost"
+                        " reached. Keeping one slot for boot cpu."
+                        "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
+
+                disabled_cpus++;
+                return;
+        }
 
         if (num_processors >= nr_cpu_ids) {
-                int max = nr_cpu_ids;
                 int thiscpu = max + disabled_cpus;
 
                 pr_warning(
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index e5293394b548..8eb863e27ea6 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1295,6 +1295,16 @@ static int setup_ioapic_entry(int apic_id, int irq,
                  * irq handler will do the explicit EOI to the io-apic.
                  */
                 ir_entry->vector = pin;
+
+                apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
+                        "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
+                        "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
+                        "Avail:%X Vector:%02X Dest:%08X "
+                        "SID:%04X SQ:%X SVT:%X)\n",
+                        apic_id, irte.present, irte.fpd, irte.dst_mode,
+                        irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
+                        irte.avail, irte.vector, irte.dest_id,
+                        irte.sid, irte.sq, irte.svt);
         } else {
                 entry->delivery_mode = apic->irq_delivery_mode;
                 entry->dest_mode = apic->irq_dest_mode;
@@ -1337,9 +1347,9 @@ static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
 
         apic_printk(APIC_VERBOSE,KERN_DEBUG
                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
-                    "IRQ %d Mode:%i Active:%i)\n",
+                    "IRQ %d Mode:%i Active:%i Dest:%d)\n",
                     apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector,
-                    irq, trigger, polarity);
+                    irq, trigger, polarity, dest);
 
 
         if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry,
@@ -1522,10 +1532,12 @@ __apicdebuginit(void) print_IO_APIC(void)
         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
 
         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
-        printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
+        printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
+                reg_01.bits.entries);
 
         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
-        printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
+        printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
+                reg_01.bits.version);
 
         /*
          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
@@ -1550,31 +1562,60 @@ __apicdebuginit(void) print_IO_APIC(void)
 
         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 
-        printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
-                          " Stat Dmod Deli Vect:\n");
+        if (intr_remapping_enabled) {
+                printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
+                        " Pol Stat Indx2 Zero Vect:\n");
+        } else {
+                printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
+                        " Stat Dmod Deli Vect:\n");
+        }
 
         for (i = 0; i <= reg_01.bits.entries; i++) {
-                struct IO_APIC_route_entry entry;
-
-                entry = ioapic_read_entry(apic, i);
-
-                printk(KERN_DEBUG " %02x %03X ",
-                        i,
-                        entry.dest
-                );
+                if (intr_remapping_enabled) {
+                        struct IO_APIC_route_entry entry;
+                        struct IR_IO_APIC_route_entry *ir_entry;
+
+                        entry = ioapic_read_entry(apic, i);
+                        ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
+                        printk(KERN_DEBUG " %02x %04X ",
+                                i,
+                                ir_entry->index
+                        );
+                        printk("%1d   %1d    %1d    %1d   %1d   "
+                                "%1d    %1d     %X    %02X\n",
+                                ir_entry->format,
+                                ir_entry->mask,
+                                ir_entry->trigger,
+                                ir_entry->irr,
+                                ir_entry->polarity,
+                                ir_entry->delivery_status,
+                                ir_entry->index2,
+                                ir_entry->zero,
+                                ir_entry->vector
+                        );
+                } else {
+                        struct IO_APIC_route_entry entry;
 
-                printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
-                        entry.mask,
-                        entry.trigger,
-                        entry.irr,
-                        entry.polarity,
-                        entry.delivery_status,
-                        entry.dest_mode,
-                        entry.delivery_mode,
-                        entry.vector
-                );
+                        entry = ioapic_read_entry(apic, i);
+                        printk(KERN_DEBUG " %02x %02X  ",
+                                i,
+                                entry.dest
+                        );
+                        printk("%1d    %1d    %1d   %1d   %1d    "
+                                "%1d    %1d    %02X\n",
+                                entry.mask,
+                                entry.trigger,
+                                entry.irr,
+                                entry.polarity,
+                                entry.delivery_status,
+                                entry.dest_mode,
+                                entry.delivery_mode,
+                                entry.vector
+                        );
+                }
         }
         }
+
         printk(KERN_DEBUG "IRQ to pin mappings:\n");
         for_each_active_irq(irq) {
                 struct irq_pin_list *entry;
@@ -1792,7 +1833,7 @@ __apicdebuginit(int) print_ICs(void)
         return 0;
 }
 
-fs_initcall(print_ICs);
+late_initcall(print_ICs);
 
 
 /* Where if anywhere is the i8259 connect in external int mode */
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 965a7666c283..0371c484bb8a 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -229,11 +229,11 @@
 #include <linux/jiffies.h>
 #include <linux/acpi.h>
 #include <linux/syscore_ops.h>
+#include <linux/i8253.h>
 
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/desc.h>
-#include <asm/i8253.h>
 #include <asm/olpc.h>
 #include <asm/paravirt.h>
 #include <asm/reboot.h>
@@ -1220,11 +1220,11 @@ static void reinit_timer(void)
 
         raw_spin_lock_irqsave(&i8253_lock, flags);
         /* set the clock to HZ */
-        outb_pit(0x34, PIT_MODE);               /* binary, mode 2, LSB/MSB, ch 0 */
+        outb_p(0x34, PIT_MODE);         /* binary, mode 2, LSB/MSB, ch 0 */
         udelay(10);
-        outb_pit(LATCH & 0xff, PIT_CH0);        /* LSB */
+        outb_p(LATCH & 0xff, PIT_CH0);  /* LSB */
         udelay(10);
-        outb_pit(LATCH >> 8, PIT_CH0);  /* MSB */
+        outb_p(LATCH >> 8, PIT_CH0);    /* MSB */
         udelay(10);
         raw_spin_unlock_irqrestore(&i8253_lock, flags);
 #endif
diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
index c29d631af6fc..395a10e68067 100644
--- a/arch/x86/kernel/asm-offsets_32.c
+++ b/arch/x86/kernel/asm-offsets_32.c
@@ -63,7 +63,6 @@ void foo(void)
         BLANK();
         OFFSET(LGUEST_DATA_irq_enabled, lguest_data, irq_enabled);
         OFFSET(LGUEST_DATA_irq_pending, lguest_data, irq_pending);
-        OFFSET(LGUEST_DATA_pgdir, lguest_data, pgdir);
 
         BLANK();
         OFFSET(LGUEST_PAGES_host_gdt_desc, lguest_pages, state.host_gdt_desc);
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 525514cf33c3..46674fbb62ba 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -62,6 +62,8 @@ static void __init check_fpu(void)
                 return;
         }
 
+        kernel_fpu_begin();
+
         /*
          * trap_init() enabled FXSR and company _before_ testing for FP
          * problems here.
@@ -80,6 +82,8 @@ static void __init check_fpu(void)
                 : "=m" (*&fdiv_bug)
                 : "m" (*&x), "m" (*&y));
 
+        kernel_fpu_end();
+
         boot_cpu_data.fdiv_bug = fdiv_bug;
         if (boot_cpu_data.fdiv_bug)
                 printk(KERN_WARNING "Hmm, FPU with FDIV bug.\n");
diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c
index 8095f8611f8a..755f64fb0743 100644
--- a/arch/x86/kernel/cpu/hypervisor.c
+++ b/arch/x86/kernel/cpu/hypervisor.c
@@ -32,11 +32,11 @@
  */
 static const __initconst struct hypervisor_x86 * const hypervisors[] =
 {
-        &x86_hyper_vmware,
-        &x86_hyper_ms_hyperv,
 #ifdef CONFIG_XEN_PVHVM
         &x86_hyper_xen_hvm,
 #endif
+        &x86_hyper_vmware,
+        &x86_hyper_ms_hyperv,
 };
 
 const struct hypervisor_x86 *x86_hyper;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1edf5ba4fb2b..ed6086eedf1d 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -456,6 +456,24 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
         if (cpu_has(c, X86_FEATURE_VMX))
                 detect_vmx_virtcap(c);
+
+        /*
+         * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
+         * x86_energy_perf_policy(8) is available to change it at run-time
+         */
+        if (cpu_has(c, X86_FEATURE_EPB)) {
+                u64 epb;
+
+                rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
+                if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
+                        printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
+                                " Set to 'normal', was 'performance'\n"
+                                "ENERGY_PERF_BIAS: View and update with"
+                                " x86_energy_perf_policy(8)\n");
+                        epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
+                        wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
+                }
+        }
 }
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 1e8d66c1336a..7395d5f4272d 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -43,61 +43,105 @@ static struct severity {
         unsigned char covered;
         char *msg;
 } severities[] = {
-#define KERNEL .context = IN_KERNEL
-#define USER .context = IN_USER
-#define SER .ser = SER_REQUIRED
-#define NOSER .ser = NO_SER
-#define SEV(s) .sev = MCE_ ## s ## _SEVERITY
-#define BITCLR(x, s, m, r...) { .mask = x, .result = 0, SEV(s), .msg = m, ## r }
-#define BITSET(x, s, m, r...) { .mask = x, .result = x, SEV(s), .msg = m, ## r }
-#define MCGMASK(x, res, s, m, r...) \
-        { .mcgmask = x, .mcgres = res, SEV(s), .msg = m, ## r }
-#define MASK(x, y, s, m, r...) \
-        { .mask = x, .result = y, SEV(s), .msg = m, ## r }
+#define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
+#define  KERNEL         .context = IN_KERNEL
+#define  USER           .context = IN_USER
+#define  SER            .ser = SER_REQUIRED
+#define  NOSER          .ser = NO_SER
+#define  BITCLR(x)      .mask = x, .result = 0
+#define  BITSET(x)      .mask = x, .result = x
+#define  MCGMASK(x, y)  .mcgmask = x, .mcgres = y
+#define  MASK(x, y)     .mask = x, .result = y
 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
 #define MCACOD 0xffff
 
-        BITCLR(MCI_STATUS_VAL, NO, "Invalid"),
-        BITCLR(MCI_STATUS_EN, NO, "Not enabled"),
-        BITSET(MCI_STATUS_PCC, PANIC, "Processor context corrupt"),
+        MCESEV(
+                NO, "Invalid",
+                BITCLR(MCI_STATUS_VAL)
+                ),
+        MCESEV(
+                NO, "Not enabled",
+                BITCLR(MCI_STATUS_EN)
+                ),
+        MCESEV(
+                PANIC, "Processor context corrupt",
+                BITSET(MCI_STATUS_PCC)
+                ),
         /* When MCIP is not set something is very confused */
-        MCGMASK(MCG_STATUS_MCIP, 0, PANIC, "MCIP not set in MCA handler"),
+        MCESEV(
+                PANIC, "MCIP not set in MCA handler",
+                MCGMASK(MCG_STATUS_MCIP, 0)
+                ),
         /* Neither return not error IP -- no chance to recover -> PANIC */
-        MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0, PANIC,
-                "Neither restart nor error IP"),
-        MCGMASK(MCG_STATUS_RIPV, 0, PANIC, "In kernel and no restart IP",
-                KERNEL),
-        BITCLR(MCI_STATUS_UC, KEEP, "Corrected error", NOSER),
-        MASK(MCI_STATUS_OVER|MCI_STATUS_UC|MCI_STATUS_EN, MCI_STATUS_UC, SOME,
-             "Spurious not enabled", SER),
+        MCESEV(
+                PANIC, "Neither restart nor error IP",
+                MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
+                ),
+        MCESEV(
+                PANIC, "In kernel and no restart IP",
+                KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
+                ),
+        MCESEV(
+                KEEP, "Corrected error",
+                NOSER, BITCLR(MCI_STATUS_UC)
+                ),
 
         /* ignore OVER for UCNA */
-        MASK(MCI_UC_SAR, MCI_STATUS_UC, KEEP,
-             "Uncorrected no action required", SER),
-        MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR, PANIC,
-             "Illegal combination (UCNA with AR=1)", SER),
-        MASK(MCI_STATUS_S, 0, KEEP, "Non signalled machine check", SER),
+        MCESEV(
+                KEEP, "Uncorrected no action required",
+                SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
+                ),
+        MCESEV(
+                PANIC, "Illegal combination (UCNA with AR=1)",
+                SER,
+                MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
+                ),
+        MCESEV(
+                KEEP, "Non signalled machine check",
+                SER, BITCLR(MCI_STATUS_S)
+                ),
 
         /* AR add known MCACODs here */
-        MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_SAR, PANIC,
-             "Action required with lost events", SER),
-        MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD, MCI_UC_SAR, PANIC,
-             "Action required; unknown MCACOD", SER),
+        MCESEV(
+                PANIC, "Action required with lost events",
+                SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR)
+                ),
+        MCESEV(
+                PANIC, "Action required: unknown MCACOD",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
+                ),
 
         /* known AO MCACODs: */
-        MASK(MCI_UC_SAR|MCI_STATUS_OVER|0xfff0, MCI_UC_S|0xc0, AO,
-             "Action optional: memory scrubbing error", SER),
-        MASK(MCI_UC_SAR|MCI_STATUS_OVER|MCACOD, MCI_UC_S|0x17a, AO,
-             "Action optional: last level cache writeback error", SER),
-
-        MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S, SOME,
-             "Action optional unknown MCACOD", SER),
-        MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S|MCI_STATUS_OVER, SOME,
-             "Action optional with lost events", SER),
-        BITSET(MCI_STATUS_UC|MCI_STATUS_OVER, PANIC, "Overflowed uncorrected"),
-        BITSET(MCI_STATUS_UC, UC, "Uncorrected"),
-        BITSET(0, SOME, "No match")     /* always matches. keep at end */
+        MCESEV(
+                AO, "Action optional: memory scrubbing error",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|0xfff0, MCI_UC_S|0x00c0)
+                ),
+        MCESEV(
+                AO, "Action optional: last level cache writeback error",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD, MCI_UC_S|0x017a)
+                ),
+        MCESEV(
+                SOME, "Action optional: unknown MCACOD",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S)
+                ),
+        MCESEV(
+                SOME, "Action optional with lost events",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S)
+                ),
+
+        MCESEV(
+                PANIC, "Overflowed uncorrected",
+                BITSET(MCI_STATUS_OVER|MCI_STATUS_UC)
+                ),
+        MCESEV(
+                UC, "Uncorrected",
+                BITSET(MCI_STATUS_UC)
+                ),
+        MCESEV(
+                SOME, "No match",
+                BITSET(0)
+                )       /* always matches. keep at end */
 };
 
 /*
@@ -112,15 +156,15 @@ static int error_context(struct mce *m)
         return IN_KERNEL;
 }
 
-int mce_severity(struct mce *a, int tolerant, char **msg)
+int mce_severity(struct mce *m, int tolerant, char **msg)
 {
-        enum context ctx = error_context(a);
+        enum context ctx = error_context(m);
         struct severity *s;
 
         for (s = severities;; s++) {
-                if ((a->status & s->mask) != s->result)
+                if ((m->status & s->mask) != s->result)
                         continue;
-                if ((a->mcgstatus & s->mcgmask) != s->mcgres)
+                if ((m->mcgstatus & s->mcgmask) != s->mcgres)
                         continue;
                 if (s->ser == SER_REQUIRED && !mce_ser)
                         continue;
@@ -197,15 +241,15 @@ static const struct file_operations severities_coverage_fops = {
 
 static int __init severities_debugfs_init(void)
 {
-        struct dentry *dmce = NULL, *fseverities_coverage = NULL;
+        struct dentry *dmce, *fsev;
 
         dmce = mce_get_debugfs_dir();
-        if (dmce == NULL)
+        if (!dmce)
                 goto err_out;
-        fseverities_coverage = debugfs_create_file("severities-coverage",
-                                                   0444, dmce, NULL,
-                                                   &severities_coverage_fops);
-        if (fseverities_coverage == NULL)
+
+        fsev = debugfs_create_file("severities-coverage", 0444, dmce, NULL,
+                                   &severities_coverage_fops);
+        if (!fsev)
                 goto err_out;
 
         return 0;
@@ -214,4 +258,4 @@ err_out:
         return -ENOMEM;
 }
 late_initcall(severities_debugfs_init);
-#endif
+#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index ff1ae9b6464d..08363b042122 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -10,7 +10,6 @@
 #include <linux/thread_info.h>
 #include <linux/capability.h>
 #include <linux/miscdevice.h>
-#include <linux/interrupt.h>
 #include <linux/ratelimit.h>
 #include <linux/kallsyms.h>
 #include <linux/rcupdate.h>
@@ -38,23 +37,20 @@
 #include <linux/mm.h>
 #include <linux/debugfs.h>
 #include <linux/edac_mce.h>
+#include <linux/irq_work.h>
 
 #include <asm/processor.h>
-#include <asm/hw_irq.h>
-#include <asm/apic.h>
-#include <asm/idle.h>
-#include <asm/ipi.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
 
 #include "mce-internal.h"
 
-static DEFINE_MUTEX(mce_read_mutex);
+static DEFINE_MUTEX(mce_chrdev_read_mutex);
 
 #define rcu_dereference_check_mce(p) \
         rcu_dereference_index_check((p), \
                               rcu_read_lock_sched_held() || \
-                              lockdep_is_held(&mce_read_mutex))
+                              lockdep_is_held(&mce_chrdev_read_mutex))
 
 #define CREATE_TRACE_POINTS
 #include <trace/events/mce.h>
@@ -94,7 +90,8 @@ static unsigned long		mce_need_notify;
 static char                     mce_helper[128];
 static char                     *mce_helper_argv[2] = { mce_helper, NULL };
 
-static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
+static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
+
 static DEFINE_PER_CPU(struct mce, mces_seen);
 static int                      cpu_missing;
 
@@ -373,6 +370,31 @@ static void mce_wrmsrl(u32 msr, u64 v)
 }
 
 /*
+ * Collect all global (w.r.t. this processor) status about this machine
+ * check into our "mce" struct so that we can use it later to assess
+ * the severity of the problem as we read per-bank specific details.
+ */
+static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
+{
+        mce_setup(m);
+
+        m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+        if (regs) {
+                /*
+                 * Get the address of the instruction at the time of
+                 * the machine check error.
+                 */
+                if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
+                        m->ip = regs->ip;
+                        m->cs = regs->cs;
+                }
+                /* Use accurate RIP reporting if available. */
+                if (rip_msr)
+                        m->ip = mce_rdmsrl(rip_msr);
+        }
+}
+
+/*
  * Simple lockless ring to communicate PFNs from the exception handler with the
  * process context work function. This is vastly simplified because there's
  * only a single reader and a single writer.
@@ -443,40 +465,13 @@ static void mce_schedule_work(void)
         }
 }
 
-/*
- * Get the address of the instruction at the time of the machine check
- * error.
- */
-static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
-{
-
-        if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
-                m->ip = regs->ip;
-                m->cs = regs->cs;
-        } else {
-                m->ip = 0;
-                m->cs = 0;
-        }
-        if (rip_msr)
-                m->ip = mce_rdmsrl(rip_msr);
-}
+DEFINE_PER_CPU(struct irq_work, mce_irq_work);
 
-#ifdef CONFIG_X86_LOCAL_APIC
-/*
- * Called after interrupts have been reenabled again
- * when a MCE happened during an interrupts off region
- * in the kernel.
- */
-asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
+static void mce_irq_work_cb(struct irq_work *entry)
 {
-        ack_APIC_irq();
-        exit_idle();
-        irq_enter();
         mce_notify_irq();
         mce_schedule_work();
-        irq_exit();
 }
-#endif
 
 static void mce_report_event(struct pt_regs *regs)
 {
@@ -492,29 +487,7 @@ static void mce_report_event(struct pt_regs *regs)
                 return;
         }
 
-#ifdef CONFIG_X86_LOCAL_APIC
-        /*
-         * Without APIC do not notify. The event will be picked
-         * up eventually.
-         */
-        if (!cpu_has_apic)
-                return;
-
-        /*
-         * When interrupts are disabled we cannot use
-         * kernel services safely. Trigger an self interrupt
-         * through the APIC to instead do the notification
-         * after interrupts are reenabled again.
-         */
-        apic->send_IPI_self(MCE_SELF_VECTOR);
-
-        /*
-         * Wait for idle afterwards again so that we don't leave the
-         * APIC in a non idle state because the normal APIC writes
-         * cannot exclude us.
-         */
-        apic_wait_icr_idle();
-#endif
+        irq_work_queue(&__get_cpu_var(mce_irq_work));
 }
 
 DEFINE_PER_CPU(unsigned, mce_poll_count);
@@ -541,9 +514,8 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 
         percpu_inc(mce_poll_count);
 
-        mce_setup(&m);
+        mce_gather_info(&m, NULL);
 
-        m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
         for (i = 0; i < banks; i++) {
                 if (!mce_banks[i].ctl || !test_bit(i, *b))
                         continue;
@@ -879,9 +851,9 @@ static int mce_usable_address(struct mce *m)
 {
         if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
                 return 0;
-        if ((m->misc & 0x3f) > PAGE_SHIFT)
+        if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
                 return 0;
-        if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
+        if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
                 return 0;
         return 1;
 }
@@ -942,9 +914,8 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         if (!banks)
                 goto out;
 
-        mce_setup(&m);
+        mce_gather_info(&m, regs);
 
-        m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
         final = &__get_cpu_var(mces_seen);
         *final = m;
 
@@ -1028,7 +999,6 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
                         mce_ring_add(m.addr >> PAGE_SHIFT);
 
-                mce_get_rip(&m, regs);
                 mce_log(&m);
 
                 if (severity > worst) {
@@ -1190,7 +1160,8 @@ int mce_notify_irq(void)
         clear_thread_flag(TIF_MCE_NOTIFY);
 
         if (test_and_clear_bit(0, &mce_need_notify)) {
-                wake_up_interruptible(&mce_wait);
+                /* wake processes polling /dev/mcelog */
+                wake_up_interruptible(&mce_chrdev_wait);
 
                 /*
                  * There is no risk of missing notifications because
@@ -1363,18 +1334,23 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
         return 0;
 }
 
-static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
+static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
 {
         if (c->x86 != 5)
-                return;
+                return 0;
+
         switch (c->x86_vendor) {
         case X86_VENDOR_INTEL:
                 intel_p5_mcheck_init(c);
+                return 1;
                 break;
         case X86_VENDOR_CENTAUR:
                 winchip_mcheck_init(c);
+                return 1;
                 break;
         }
+
+        return 0;
 }
 
 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
@@ -1428,7 +1404,8 @@ void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
         if (mce_disabled)
                 return;
 
-        __mcheck_cpu_ancient_init(c);
+        if (__mcheck_cpu_ancient_init(c))
+                return;
 
         if (!mce_available(c))
                 return;
@@ -1444,44 +1421,45 @@ void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
         __mcheck_cpu_init_vendor(c);
         __mcheck_cpu_init_timer();
         INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
-
+        init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
 }
 
 /*
- * Character device to read and clear the MCE log.
+ * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
  */
 
-static DEFINE_SPINLOCK(mce_state_lock);
-static int              open_count;             /* #times opened */
-static int              open_exclu;             /* already open exclusive? */
+static DEFINE_SPINLOCK(mce_chrdev_state_lock);
+static int mce_chrdev_open_count;       /* #times opened */
+static int mce_chrdev_open_exclu;       /* already open exclusive? */
 
-static int mce_open(struct inode *inode, struct file *file)
+static int mce_chrdev_open(struct inode *inode, struct file *file)
 {
-        spin_lock(&mce_state_lock);
+        spin_lock(&mce_chrdev_state_lock);
 
-        if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
-                spin_unlock(&mce_state_lock);
+        if (mce_chrdev_open_exclu ||
+            (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
+                spin_unlock(&mce_chrdev_state_lock);
 
                 return -EBUSY;
         }
 
         if (file->f_flags & O_EXCL)
-                open_exclu = 1;
-        open_count++;
+                mce_chrdev_open_exclu = 1;
+        mce_chrdev_open_count++;
 
-        spin_unlock(&mce_state_lock);
+        spin_unlock(&mce_chrdev_state_lock);
 
         return nonseekable_open(inode, file);
 }
 
-static int mce_release(struct inode *inode, struct file *file)
+static int mce_chrdev_release(struct inode *inode, struct file *file)
 {
-        spin_lock(&mce_state_lock);
+        spin_lock(&mce_chrdev_state_lock);
 
-        open_count--;
-        open_exclu = 0;
+        mce_chrdev_open_count--;
+        mce_chrdev_open_exclu = 0;
 
-        spin_unlock(&mce_state_lock);
+        spin_unlock(&mce_chrdev_state_lock);
 
         return 0;
 }
@@ -1530,8 +1508,8 @@ static int __mce_read_apei(char __user **ubuf, size_t usize)
         return 0;
 }
 
-static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
-                        loff_t *off)
+static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
+                                size_t usize, loff_t *off)
 {
         char __user *buf = ubuf;
         unsigned long *cpu_tsc;
@@ -1542,7 +1520,7 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
         if (!cpu_tsc)
                 return -ENOMEM;
 
-        mutex_lock(&mce_read_mutex);
+        mutex_lock(&mce_chrdev_read_mutex);
 
         if (!mce_apei_read_done) {
                 err = __mce_read_apei(&buf, usize);
@@ -1562,19 +1540,18 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
         do {
                 for (i = prev; i < next; i++) {
                         unsigned long start = jiffies;
+                        struct mce *m = &mcelog.entry[i];
 
-                        while (!mcelog.entry[i].finished) {
+                        while (!m->finished) {
                                 if (time_after_eq(jiffies, start + 2)) {
-                                        memset(mcelog.entry + i, 0,
-                                               sizeof(struct mce));
+                                        memset(m, 0, sizeof(*m));
                                         goto timeout;
                                 }
                                 cpu_relax();
                         }
                         smp_rmb();
-                        err |= copy_to_user(buf, mcelog.entry + i,
-                                            sizeof(struct mce));
-                        buf += sizeof(struct mce);
+                        err |= copy_to_user(buf, m, sizeof(*m));
+                        buf += sizeof(*m);
 timeout:
                         ;
                 }
@@ -1594,13 +1571,13 @@ timeout:
         on_each_cpu(collect_tscs, cpu_tsc, 1);
 
         for (i = next; i < MCE_LOG_LEN; i++) {
-                if (mcelog.entry[i].finished &&
-                    mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
-                        err |= copy_to_user(buf, mcelog.entry+i,
-                                            sizeof(struct mce));
+                struct mce *m = &mcelog.entry[i];
+
+                if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
+                        err |= copy_to_user(buf, m, sizeof(*m));
                         smp_rmb();
-                        buf += sizeof(struct mce);
-                        memset(&mcelog.entry[i], 0, sizeof(struct mce));
+                        buf += sizeof(*m);
+                        memset(m, 0, sizeof(*m));
                 }
         }
 
@@ -1608,15 +1585,15 @@ timeout:
                 err = -EFAULT;
 
 out:
-        mutex_unlock(&mce_read_mutex);
+        mutex_unlock(&mce_chrdev_read_mutex);
         kfree(cpu_tsc);
 
         return err ? err : buf - ubuf;
 }
 
-static unsigned int mce_poll(struct file *file, poll_table *wait)
+static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
 {
-        poll_wait(file, &mce_wait, wait);
+        poll_wait(file, &mce_chrdev_wait, wait);
         if (rcu_access_index(mcelog.next))
                 return POLLIN | POLLRDNORM;
         if (!mce_apei_read_done && apei_check_mce())
@@ -1624,7 +1601,8 @@ static unsigned int mce_poll(struct file *file, poll_table *wait)
         return 0;
 }
 
-static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
+static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
+                                unsigned long arg)
 {
         int __user *p = (int __user *)arg;
 
@@ -1652,16 +1630,16 @@ static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
 
 /* Modified in mce-inject.c, so not static or const */
 struct file_operations mce_chrdev_ops = {
-        .open                   = mce_open,
-        .release                = mce_release,
-        .read                   = mce_read,
-        .poll                   = mce_poll,
-        .unlocked_ioctl         = mce_ioctl,
-        .llseek         = no_llseek,
+        .open                   = mce_chrdev_open,
+        .release                = mce_chrdev_release,
+        .read                   = mce_chrdev_read,
+        .poll                   = mce_chrdev_poll,
+        .unlocked_ioctl         = mce_chrdev_ioctl,
+        .llseek                 = no_llseek,
 };
 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
 
-static struct miscdevice mce_log_device = {
+static struct miscdevice mce_chrdev_device = {
         MISC_MCELOG_MINOR,
         "mcelog",
         &mce_chrdev_ops,
@@ -1719,7 +1697,7 @@ int __init mcheck_init(void)
 }
 
 /*
- * Sysfs support
+ * mce_syscore: PM support
  */
 
 /*
@@ -1739,12 +1717,12 @@ static int mce_disable_error_reporting(void)
         return 0;
 }
 
-static int mce_suspend(void)
+static int mce_syscore_suspend(void)
 {
         return mce_disable_error_reporting();
 }
 
-static void mce_shutdown(void)
+static void mce_syscore_shutdown(void)
 {
         mce_disable_error_reporting();
 }
@@ -1754,18 +1732,22 @@ static void mce_shutdown(void)
  * Only one CPU is active at this time, the others get re-added later using
  * CPU hotplug:
  */
-static void mce_resume(void)
+static void mce_syscore_resume(void)
 {
         __mcheck_cpu_init_generic();
         __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
 }
 
 static struct syscore_ops mce_syscore_ops = {
-        .suspend        = mce_suspend,
-        .shutdown       = mce_shutdown,
-        .resume         = mce_resume,
+        .suspend        = mce_syscore_suspend,
+        .shutdown       = mce_syscore_shutdown,
+        .resume         = mce_syscore_resume,
 };
 
+/*
+ * mce_sysdev: Sysfs support
+ */
+
 static void mce_cpu_restart(void *data)
 {
         del_timer_sync(&__get_cpu_var(mce_timer));
@@ -1801,11 +1783,11 @@ static void mce_enable_ce(void *all)
                 __mcheck_cpu_init_timer();
 }
 
-static struct sysdev_class mce_sysclass = {
+static struct sysdev_class mce_sysdev_class = {
         .name           = "machinecheck",
 };
 
-DEFINE_PER_CPU(struct sys_device, mce_dev);
+DEFINE_PER_CPU(struct sys_device, mce_sysdev);
 
 __cpuinitdata
 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
@@ -1934,7 +1916,7 @@ static struct sysdev_ext_attribute attr_cmci_disabled = {
         &mce_cmci_disabled
 };
 
-static struct sysdev_attribute *mce_attrs[] = {
+static struct sysdev_attribute *mce_sysdev_attrs[] = {
         &attr_tolerant.attr,
         &attr_check_interval.attr,
         &attr_trigger,
@@ -1945,66 +1927,67 @@ static struct sysdev_attribute *mce_attrs[] = {
         NULL
 };
 
-static cpumask_var_t mce_dev_initialized;
+static cpumask_var_t mce_sysdev_initialized;
 
 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
-static __cpuinit int mce_create_device(unsigned int cpu)
+static __cpuinit int mce_sysdev_create(unsigned int cpu)
 {
+        struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
         int err;
         int i, j;
 
         if (!mce_available(&boot_cpu_data))
                 return -EIO;
 
-        memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
-        per_cpu(mce_dev, cpu).id        = cpu;
-        per_cpu(mce_dev, cpu).cls       = &mce_sysclass;
+        memset(&sysdev->kobj, 0, sizeof(struct kobject));
+        sysdev->id  = cpu;
+        sysdev->cls = &mce_sysdev_class;
 
-        err = sysdev_register(&per_cpu(mce_dev, cpu));
+        err = sysdev_register(sysdev);
         if (err)
                 return err;
 
-        for (i = 0; mce_attrs[i]; i++) {
-                err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
+        for (i = 0; mce_sysdev_attrs[i]; i++) {
+                err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
                 if (err)
                         goto error;
         }
         for (j = 0; j < banks; j++) {
-                err = sysdev_create_file(&per_cpu(mce_dev, cpu),
-                                        &mce_banks[j].attr);
+                err = sysdev_create_file(sysdev, &mce_banks[j].attr);
                 if (err)
                         goto error2;
         }
-        cpumask_set_cpu(cpu, mce_dev_initialized);
+        cpumask_set_cpu(cpu, mce_sysdev_initialized);
 
         return 0;
 error2:
         while (--j >= 0)
-                sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
+                sysdev_remove_file(sysdev, &mce_banks[j].attr);
 error:
         while (--i >= 0)
-                sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
+                sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
 
-        sysdev_unregister(&per_cpu(mce_dev, cpu));
+        sysdev_unregister(sysdev);
 
         return err;
 }
 
-static __cpuinit void mce_remove_device(unsigned int cpu)
+static __cpuinit void mce_sysdev_remove(unsigned int cpu)
 {
+        struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
         int i;
 
-        if (!cpumask_test_cpu(cpu, mce_dev_initialized))
+        if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
                 return;
 
-        for (i = 0; mce_attrs[i]; i++)
-                sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
+        for (i = 0; mce_sysdev_attrs[i]; i++)
+                sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
 
         for (i = 0; i < banks; i++)
-                sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
+                sysdev_remove_file(sysdev, &mce_banks[i].attr);
 
-        sysdev_unregister(&per_cpu(mce_dev, cpu));
-        cpumask_clear_cpu(cpu, mce_dev_initialized);
+        sysdev_unregister(sysdev);
+        cpumask_clear_cpu(cpu, mce_sysdev_initialized);
 }
 
 /* Make sure there are no machine checks on offlined CPUs. */
@@ -2054,7 +2037,7 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
         switch (action) {
         case CPU_ONLINE:
         case CPU_ONLINE_FROZEN:
-                mce_create_device(cpu);
+                mce_sysdev_create(cpu);
                 if (threshold_cpu_callback)
                         threshold_cpu_callback(action, cpu);
                 break;
@@ -2062,7 +2045,7 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
         case CPU_DEAD_FROZEN:
                 if (threshold_cpu_callback)
                         threshold_cpu_callback(action, cpu);
-                mce_remove_device(cpu);
+                mce_sysdev_remove(cpu);
                 break;
         case CPU_DOWN_PREPARE:
         case CPU_DOWN_PREPARE_FROZEN:
@@ -2116,27 +2099,28 @@ static __init int mcheck_init_device(void)
         if (!mce_available(&boot_cpu_data))
                 return -EIO;
 
-        zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
+        zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
 
         mce_init_banks();
 
-        err = sysdev_class_register(&mce_sysclass);
+        err = sysdev_class_register(&mce_sysdev_class);
         if (err)
                 return err;
 
         for_each_online_cpu(i) {
-                err = mce_create_device(i);
+                err = mce_sysdev_create(i);
                 if (err)
                         return err;
         }
 
         register_syscore_ops(&mce_syscore_ops);
         register_hotcpu_notifier(&mce_cpu_notifier);
-        misc_register(&mce_log_device);
+
+        /* register character device /dev/mcelog */
+        misc_register(&mce_chrdev_device);
 
         return err;
 }
-
 device_initcall(mcheck_init_device);
 
 /*
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index bb0adad35143..f5474218cffe 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -548,7 +548,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                 if (!b)
                         goto out;
 
-                err = sysfs_create_link(&per_cpu(mce_dev, cpu).kobj,
+                err = sysfs_create_link(&per_cpu(mce_sysdev, cpu).kobj,
                                         b->kobj, name);
                 if (err)
                         goto out;
@@ -571,7 +571,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                 goto out;
         }
 
-        b->kobj = kobject_create_and_add(name, &per_cpu(mce_dev, cpu).kobj);
+        b->kobj = kobject_create_and_add(name, &per_cpu(mce_sysdev, cpu).kobj);
         if (!b->kobj)
                 goto out_free;
 
@@ -591,7 +591,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                 if (i == cpu)
                         continue;
 
-                err = sysfs_create_link(&per_cpu(mce_dev, i).kobj,
+                err = sysfs_create_link(&per_cpu(mce_sysdev, i).kobj,
                                         b->kobj, name);
                 if (err)
                         goto out;
@@ -669,7 +669,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
 #ifdef CONFIG_SMP
         /* sibling symlink */
         if (shared_bank[bank] && b->blocks->cpu != cpu) {
-                sysfs_remove_link(&per_cpu(mce_dev, cpu).kobj, name);
+                sysfs_remove_link(&per_cpu(mce_sysdev, cpu).kobj, name);
                 per_cpu(threshold_banks, cpu)[bank] = NULL;
 
                 return;
@@ -681,7 +681,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
                 if (i == cpu)
                         continue;
 
-                sysfs_remove_link(&per_cpu(mce_dev, i).kobj, name);
+                sysfs_remove_link(&per_cpu(mce_sysdev, i).kobj, name);
                 per_cpu(threshold_banks, i)[bank] = NULL;
         }
 
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 929739a653d1..08119a37e53c 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -79,7 +79,6 @@ void set_mtrr_ops(const struct mtrr_ops *ops)
 static int have_wrcomb(void)
 {
         struct pci_dev *dev;
-        u8 rev;
 
         dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
         if (dev != NULL) {
@@ -89,13 +88,11 @@ static int have_wrcomb(void)
                  * chipsets to be tagged
                  */
                 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
-                    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
-                        pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
-                        if (rev <= 5) {
-                                pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
-                                pci_dev_put(dev);
-                                return 0;
-                        }
+                    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
+                    dev->revision <= 5) {
+                        pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
+                        pci_dev_put(dev);
+                        return 0;
                 }
                 /*
                  * Intel 450NX errata # 23. Non ascending cacheline evictions to
@@ -137,55 +134,43 @@ static void __init init_table(void)
 }
 
 struct set_mtrr_data {
-        atomic_t        count;
-        atomic_t        gate;
         unsigned long   smp_base;
         unsigned long   smp_size;
         unsigned int    smp_reg;
         mtrr_type       smp_type;
 };
 
-static DEFINE_PER_CPU(struct cpu_stop_work, mtrr_work);
-
 /**
- * mtrr_work_handler - Synchronisation handler. Executed by "other" CPUs.
+ * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
+ * by all the CPUs.
  * @info: pointer to mtrr configuration data
  *
  * Returns nothing.
  */
-static int mtrr_work_handler(void *info)
+static int mtrr_rendezvous_handler(void *info)
 {
 #ifdef CONFIG_SMP
         struct set_mtrr_data *data = info;
-        unsigned long flags;
-
-        atomic_dec(&data->count);
-        while (!atomic_read(&data->gate))
-                cpu_relax();
-
-        local_irq_save(flags);
-
-        atomic_dec(&data->count);
-        while (atomic_read(&data->gate))
-                cpu_relax();
 
-        /*  The master has cleared me to execute  */
+        /*
+         * We use this same function to initialize the mtrrs during boot,
+         * resume, runtime cpu online and on an explicit request to set a
+         * specific MTRR.
+         *
+         * During boot or suspend, the state of the boot cpu's mtrrs has been
+         * saved, and we want to replicate that across all the cpus that come
+         * online (either at the end of boot or resume or during a runtime cpu
+         * online). If we're doing that, @reg is set to something special and on
+         * all the cpu's we do mtrr_if->set_all() (On the logical cpu that
+         * started the boot/resume sequence, this might be a duplicate
+         * set_all()).
+         */
         if (data->smp_reg != ~0U) {
                 mtrr_if->set(data->smp_reg, data->smp_base,
                              data->smp_size, data->smp_type);
-        } else if (mtrr_aps_delayed_init) {
-                /*
-                 * Initialize the MTRRs inaddition to the synchronisation.
-                 */
+        } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) {
                 mtrr_if->set_all();
         }
-
-        atomic_dec(&data->count);
-        while (!atomic_read(&data->gate))
-                cpu_relax();
-
-        atomic_dec(&data->count);
-        local_irq_restore(flags);
 #endif
         return 0;
 }
@@ -223,20 +208,11 @@ static inline int types_compatible(mtrr_type type1, mtrr_type type2)
  * 14. Wait for buddies to catch up
  * 15. Enable interrupts.
  *
- * What does that mean for us? Well, first we set data.count to the number
- * of CPUs. As each CPU announces that it started the rendezvous handler by
- * decrementing the count, We reset data.count and set the data.gate flag
- * allowing all the cpu's to proceed with the work. As each cpu disables
- * interrupts, it'll decrement data.count once. We wait until it hits 0 and
- * proceed. We clear the data.gate flag and reset data.count. Meanwhile, they
- * are waiting for that flag to be cleared. Once it's cleared, each
- * CPU goes through the transition of updating MTRRs.
- * The CPU vendors may each do it differently,
- * so we call mtrr_if->set() callback and let them take care of it.
- * When they're done, they again decrement data->count and wait for data.gate
- * to be set.
- * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag
- * Everyone then enables interrupts and we all continue on.
+ * What does that mean for us? Well, stop_machine() will ensure that
+ * the rendezvous handler is started on each CPU. And in lockstep they
+ * do the state transition of disabling interrupts, updating MTRR's
+ * (the CPU vendors may each do it differently, so we call mtrr_if->set()
+ * callback and let them take care of it.) and enabling interrupts.
  *
  * Note that the mechanism is the same for UP systems, too; all the SMP stuff
  * becomes nops.
@@ -244,92 +220,26 @@ static inline int types_compatible(mtrr_type type1, mtrr_type type2)
 static void
 set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
 {
-        struct set_mtrr_data data;
-        unsigned long flags;
-        int cpu;
-
-        preempt_disable();
-
-        data.smp_reg = reg;
-        data.smp_base = base;
-        data.smp_size = size;
-        data.smp_type = type;
-        atomic_set(&data.count, num_booting_cpus() - 1);
-
-        /* Make sure data.count is visible before unleashing other CPUs */
-        smp_wmb();
-        atomic_set(&data.gate, 0);
-
-        /* Start the ball rolling on other CPUs */
-        for_each_online_cpu(cpu) {
-                struct cpu_stop_work *work = &per_cpu(mtrr_work, cpu);
-
-                if (cpu == smp_processor_id())
-                        continue;
-
-                stop_one_cpu_nowait(cpu, mtrr_work_handler, &data, work);
-        }
-
-
-        while (atomic_read(&data.count))
-                cpu_relax();
-
-        /* Ok, reset count and toggle gate */
-        atomic_set(&data.count, num_booting_cpus() - 1);
-        smp_wmb();
-        atomic_set(&data.gate, 1);
-
-        local_irq_save(flags);
-
-        while (atomic_read(&data.count))
-                cpu_relax();
-
-        /* Ok, reset count and toggle gate */
-        atomic_set(&data.count, num_booting_cpus() - 1);
-        smp_wmb();
-        atomic_set(&data.gate, 0);
-
-        /* Do our MTRR business */
-
-        /*
-         * HACK!
-         *
-         * We use this same function to initialize the mtrrs during boot,
-         * resume, runtime cpu online and on an explicit request to set a
-         * specific MTRR.
-         *
-         * During boot or suspend, the state of the boot cpu's mtrrs has been
-         * saved, and we want to replicate that across all the cpus that come
-         * online (either at the end of boot or resume or during a runtime cpu
-         * online). If we're doing that, @reg is set to something special and on
-         * this cpu we still do mtrr_if->set_all(). During boot/resume, this
-         * is unnecessary if at this point we are still on the cpu that started
-         * the boot/resume sequence. But there is no guarantee that we are still
-         * on the same cpu. So we do mtrr_if->set_all() on this cpu aswell to be
-         * sure that we are in sync with everyone else.
-         */
-        if (reg != ~0U)
-                mtrr_if->set(reg, base, size, type);
-        else
-                mtrr_if->set_all();
+        struct set_mtrr_data data = { .smp_reg = reg,
+                                      .smp_base = base,
+                                      .smp_size = size,
+                                      .smp_type = type
+                                    };
 
-        /* Wait for the others */
-        while (atomic_read(&data.count))
-                cpu_relax();
-
-        atomic_set(&data.count, num_booting_cpus() - 1);
-        smp_wmb();
-        atomic_set(&data.gate, 1);
-
-        /*
-         * Wait here for everyone to have seen the gate change
-         * So we're the last ones to touch 'data'
-         */
-        while (atomic_read(&data.count))
-                cpu_relax();
+        stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask);
+}
 
-        local_irq_restore(flags);
-        preempt_enable();
+static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base,
+                                      unsigned long size, mtrr_type type)
+{
+        struct set_mtrr_data data = { .smp_reg = reg,
+                                      .smp_base = base,
+                                      .smp_size = size,
+                                      .smp_type = type
+                                    };
+
+        stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data,
+                                       cpu_callout_mask);
 }
 
 /**
@@ -783,7 +693,7 @@ void mtrr_ap_init(void)
          *   2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
          *      lock to prevent mtrr entry changes
          */
-        set_mtrr(~0U, 0, 0, 0);
+        set_mtrr_from_inactive_cpu(~0U, 0, 0, 0);
 }
 
 /**
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 3a0338b4b179..4ee3abf20ed6 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -22,7 +22,6 @@
 #include <linux/sched.h>
 #include <linux/uaccess.h>
 #include <linux/slab.h>
-#include <linux/highmem.h>
 #include <linux/cpu.h>
 #include <linux/bitops.h>
 
@@ -45,38 +44,27 @@ do {								\
 #endif
 
 /*
- * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
+ *          |   NHM/WSM    |      SNB     |
+ * register -------------------------------
+ *          |  HT  | no HT |  HT  | no HT |
+ *-----------------------------------------
+ * offcore  | core | core  | cpu  | core  |
+ * lbr_sel  | core | core  | cpu  | core  |
+ * ld_lat   | cpu  | core  | cpu  | core  |
+ *-----------------------------------------
+ *
+ * Given that there is a small number of shared regs,
+ * we can pre-allocate their slot in the per-cpu
+ * per-core reg tables.
  */
-static unsigned long
-copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
-{
-        unsigned long offset, addr = (unsigned long)from;
-        unsigned long size, len = 0;
-        struct page *page;
-        void *map;
-        int ret;
-
-        do {
-                ret = __get_user_pages_fast(addr, 1, 0, &page);
-                if (!ret)
-                        break;
-
-                offset = addr & (PAGE_SIZE - 1);
-                size = min(PAGE_SIZE - offset, n - len);
-
-                map = kmap_atomic(page);
-                memcpy(to, map+offset, size);
-                kunmap_atomic(map);
-                put_page(page);
+enum extra_reg_type {
+        EXTRA_REG_NONE  = -1,   /* not used */
 
-                len  += size;
-                to   += size;
-                addr += size;
+        EXTRA_REG_RSP_0 = 0,    /* offcore_response_0 */
+        EXTRA_REG_RSP_1 = 1,    /* offcore_response_1 */
 
-        } while (len < n);
-
-        return len;
-}
+        EXTRA_REG_MAX           /* number of entries needed */
+};
 
 struct event_constraint {
         union {
@@ -132,11 +120,10 @@ struct cpu_hw_events {
         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 
         /*
-         * Intel percore register state.
-         * Coordinate shared resources between HT threads.
+         * manage shared (per-core, per-cpu) registers
+         * used on Intel NHM/WSM/SNB
          */
-        int                             percore_used; /* Used by this CPU? */
-        struct intel_percore            *per_core;
+        struct intel_shared_regs        *shared_regs;
 
         /*
          * AMD specific bits
@@ -187,26 +174,45 @@ struct cpu_hw_events {
         for ((e) = (c); (e)->weight; (e)++)
 
 /*
+ * Per register state.
+ */
+struct er_account {
+        raw_spinlock_t          lock;   /* per-core: protect structure */
+        u64                     config; /* extra MSR config */
+        u64                     reg;    /* extra MSR number */
+        atomic_t                ref;    /* reference count */
+};
+
+/*
  * Extra registers for specific events.
+ *
  * Some events need large masks and require external MSRs.
- * Define a mapping to these extra registers.
+ * Those extra MSRs end up being shared for all events on
+ * a PMU and sometimes between PMU of sibling HT threads.
+ * In either case, the kernel needs to handle conflicting
+ * accesses to those extra, shared, regs. The data structure
+ * to manage those registers is stored in cpu_hw_event.
  */
 struct extra_reg {
         unsigned int            event;
         unsigned int            msr;
         u64                     config_mask;
         u64                     valid_mask;
+        int                     idx;  /* per_xxx->regs[] reg index */
 };
 
-#define EVENT_EXTRA_REG(e, ms, m, vm) { \
+#define EVENT_EXTRA_REG(e, ms, m, vm, i) {      \
         .event = (e),           \
         .msr = (ms),            \
         .config_mask = (m),     \
         .valid_mask = (vm),     \
+        .idx = EXTRA_REG_##i    \
         }
-#define INTEL_EVENT_EXTRA_REG(event, msr, vm)   \
-        EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
-#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)
+
+#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)      \
+        EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
+
+#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
 
 union perf_capabilities {
         struct {
@@ -252,7 +258,6 @@ struct x86_pmu {
         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
                                                  struct perf_event *event);
         struct event_constraint *event_constraints;
-        struct event_constraint *percore_constraints;
         void            (*quirks)(void);
         int             perfctr_second_write;
 
@@ -286,8 +291,12 @@ struct x86_pmu {
          * Extra registers for events
          */
         struct extra_reg *extra_regs;
+        unsigned int er_flags;
 };
 
+#define ERF_NO_HT_SHARING       1
+#define ERF_HAS_RSP_1           2
+
 static struct x86_pmu x86_pmu __read_mostly;
 
 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
@@ -393,10 +402,10 @@ static inline unsigned int x86_pmu_event_addr(int index)
  */
 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 {
+        struct hw_perf_event_extra *reg;
         struct extra_reg *er;
 
-        event->hw.extra_reg = 0;
-        event->hw.extra_config = 0;
+        reg = &event->hw.extra_reg;
 
         if (!x86_pmu.extra_regs)
                 return 0;
@@ -406,8 +415,10 @@ static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
                         continue;
                 if (event->attr.config1 & ~er->valid_mask)
                         return -EINVAL;
-                event->hw.extra_reg = er->msr;
-                event->hw.extra_config = event->attr.config1;
+
+                reg->idx = er->idx;
+                reg->config = event->attr.config1;
+                reg->reg = er->msr;
                 break;
         }
         return 0;
@@ -706,6 +717,9 @@ static int __x86_pmu_event_init(struct perf_event *event)
         event->hw.last_cpu = -1;
         event->hw.last_tag = ~0ULL;
 
+        /* mark unused */
+        event->hw.extra_reg.idx = EXTRA_REG_NONE;
+
         return x86_pmu.hw_config(event);
 }
 
@@ -747,8 +761,8 @@ static void x86_pmu_disable(struct pmu *pmu)
 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
                                           u64 enable_mask)
 {
-        if (hwc->extra_reg)
-                wrmsrl(hwc->extra_reg, hwc->extra_config);
+        if (hwc->extra_reg.reg)
+                wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
         wrmsrl(hwc->config_base, hwc->config | enable_mask);
 }
 
@@ -1332,7 +1346,7 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
                 if (!x86_perf_event_set_period(event))
                         continue;
 
-                if (perf_event_overflow(event, 1, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         x86_pmu_stop(event, 0);
         }
 
@@ -1637,6 +1651,40 @@ static int x86_pmu_commit_txn(struct pmu *pmu)
         perf_pmu_enable(pmu);
         return 0;
 }
+/*
+ * a fake_cpuc is used to validate event groups. Due to
+ * the extra reg logic, we need to also allocate a fake
+ * per_core and per_cpu structure. Otherwise, group events
+ * using extra reg may conflict without the kernel being
+ * able to catch this when the last event gets added to
+ * the group.
+ */
+static void free_fake_cpuc(struct cpu_hw_events *cpuc)
+{
+        kfree(cpuc->shared_regs);
+        kfree(cpuc);
+}
+
+static struct cpu_hw_events *allocate_fake_cpuc(void)
+{
+        struct cpu_hw_events *cpuc;
+        int cpu = raw_smp_processor_id();
+
+        cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
+        if (!cpuc)
+                return ERR_PTR(-ENOMEM);
+
+        /* only needed, if we have extra_regs */
+        if (x86_pmu.extra_regs) {
+                cpuc->shared_regs = allocate_shared_regs(cpu);
+                if (!cpuc->shared_regs)
+                        goto error;
+        }
+        return cpuc;
+error:
+        free_fake_cpuc(cpuc);
+        return ERR_PTR(-ENOMEM);
+}
 
 /*
  * validate that we can schedule this event
@@ -1647,9 +1695,9 @@ static int validate_event(struct perf_event *event)
         struct event_constraint *c;
         int ret = 0;
 
-        fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
-        if (!fake_cpuc)
-                return -ENOMEM;
+        fake_cpuc = allocate_fake_cpuc();
+        if (IS_ERR(fake_cpuc))
+                return PTR_ERR(fake_cpuc);
 
         c = x86_pmu.get_event_constraints(fake_cpuc, event);
 
@@ -1659,7 +1707,7 @@ static int validate_event(struct perf_event *event)
         if (x86_pmu.put_event_constraints)
                 x86_pmu.put_event_constraints(fake_cpuc, event);
 
-        kfree(fake_cpuc);
+        free_fake_cpuc(fake_cpuc);
 
         return ret;
 }
@@ -1679,36 +1727,32 @@ static int validate_group(struct perf_event *event)
 {
         struct perf_event *leader = event->group_leader;
         struct cpu_hw_events *fake_cpuc;
-        int ret, n;
-
-        ret = -ENOMEM;
-        fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
-        if (!fake_cpuc)
-                goto out;
+        int ret = -ENOSPC, n;
 
+        fake_cpuc = allocate_fake_cpuc();
+        if (IS_ERR(fake_cpuc))
+                return PTR_ERR(fake_cpuc);
         /*
          * the event is not yet connected with its
          * siblings therefore we must first collect
          * existing siblings, then add the new event
          * before we can simulate the scheduling
          */
-        ret = -ENOSPC;
         n = collect_events(fake_cpuc, leader, true);
         if (n < 0)
-                goto out_free;
+                goto out;
 
         fake_cpuc->n_events = n;
         n = collect_events(fake_cpuc, event, false);
         if (n < 0)
-                goto out_free;
+                goto out;
 
         fake_cpuc->n_events = n;
 
         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
 
-out_free:
-        kfree(fake_cpuc);
 out:
+        free_fake_cpuc(fake_cpuc);
         return ret;
 }
 
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index fe29c1d2219e..941caa2e449b 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -89,6 +89,20 @@ static __initconst const u64 amd_hw_cache_event_ids
                 [ C(RESULT_MISS)   ] = -1,
         },
  },
+ [ C(NODE) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
+                [ C(RESULT_MISS)   ] = 0x98e9, /* CPU Request to Memory, r   */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
 };
 
 /*
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 41178c826c48..45fbb8f7f549 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1,25 +1,15 @@
 #ifdef CONFIG_CPU_SUP_INTEL
 
-#define MAX_EXTRA_REGS 2
-
-/*
- * Per register state.
- */
-struct er_account {
-        int                     ref;            /* reference count */
-        unsigned int            extra_reg;      /* extra MSR number */
-        u64                     extra_config;   /* extra MSR config */
-};
-
 /*
- * Per core state
- * This used to coordinate shared registers for HT threads.
+ * Per core/cpu state
+ *
+ * Used to coordinate shared registers between HT threads or
+ * among events on a single PMU.
  */
-struct intel_percore {
-        raw_spinlock_t          lock;           /* protect structure */
-        struct er_account       regs[MAX_EXTRA_REGS];
-        int                     refcnt;         /* number of threads */
-        unsigned                core_id;
+struct intel_shared_regs {
+        struct er_account       regs[EXTRA_REG_MAX];
+        int                     refcnt;         /* per-core: #HT threads */
+        unsigned                core_id;        /* per-core: core id */
 };
 
 /*
@@ -88,16 +78,10 @@ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
 
 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
 {
-        INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff),
+        INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
         EVENT_EXTRA_END
 };
 
-static struct event_constraint intel_nehalem_percore_constraints[] __read_mostly =
-{
-        INTEL_EVENT_CONSTRAINT(0xb7, 0),
-        EVENT_CONSTRAINT_END
-};
-
 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
 {
         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
@@ -116,8 +100,6 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
-        INTEL_EVENT_CONSTRAINT(0xb7, 0x1), /* OFF_CORE_RESPONSE_0 */
-        INTEL_EVENT_CONSTRAINT(0xbb, 0x8), /* OFF_CORE_RESPONSE_1 */
         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
         EVENT_CONSTRAINT_END
@@ -125,15 +107,13 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 
 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 {
-        INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff),
-        INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff),
+        INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
+        INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
         EVENT_EXTRA_END
 };
 
-static struct event_constraint intel_westmere_percore_constraints[] __read_mostly =
+static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 {
-        INTEL_EVENT_CONSTRAINT(0xb7, 0),
-        INTEL_EVENT_CONSTRAINT(0xbb, 0),
         EVENT_CONSTRAINT_END
 };
 
@@ -145,6 +125,12 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
         EVENT_CONSTRAINT_END
 };
 
+static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
+        INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
+        INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
+        EVENT_EXTRA_END
+};
+
 static u64 intel_pmu_event_map(int hw_event)
 {
         return intel_perfmon_event_map[hw_event];
@@ -245,6 +231,21 @@ static __initconst const u64 snb_hw_cache_event_ids
                 [ C(RESULT_MISS)   ] = -1,
         },
  },
+ [ C(NODE) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+
 };
 
 static __initconst const u64 westmere_hw_cache_event_ids
@@ -346,6 +347,20 @@ static __initconst const u64 westmere_hw_cache_event_ids
                 [ C(RESULT_MISS)   ] = -1,
         },
  },
+ [ C(NODE) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
+        },
+ },
 };
 
 /*
@@ -398,7 +413,21 @@ static __initconst const u64 nehalem_hw_cache_extra_regs
                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
         },
- }
+ },
+ [ C(NODE) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_ALL_DRAM,
+                [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE_DRAM,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_ALL_DRAM,
+                [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE_DRAM,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_ALL_DRAM,
+                [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE_DRAM,
+        },
+ },
 };
 
 static __initconst const u64 nehalem_hw_cache_event_ids
@@ -500,6 +529,20 @@ static __initconst const u64 nehalem_hw_cache_event_ids
                 [ C(RESULT_MISS)   ] = -1,
         },
  },
+ [ C(NODE) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
+        },
+ },
 };
 
 static __initconst const u64 core2_hw_cache_event_ids
@@ -1003,7 +1046,7 @@ again:
 
                 data.period = event->hw.last_period;
 
-                if (perf_event_overflow(event, 1, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         x86_pmu_stop(event, 0);
         }
 
@@ -1037,65 +1080,121 @@ intel_bts_constraints(struct perf_event *event)
         return NULL;
 }
 
+static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
+{
+        if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
+                return false;
+
+        if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
+                event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
+                event->hw.config |= 0x01bb;
+                event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
+                event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
+        } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
+                event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
+                event->hw.config |= 0x01b7;
+                event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
+                event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
+        }
+
+        if (event->hw.extra_reg.idx == orig_idx)
+                return false;
+
+        return true;
+}
+
+/*
+ * manage allocation of shared extra msr for certain events
+ *
+ * sharing can be:
+ * per-cpu: to be shared between the various events on a single PMU
+ * per-core: per-cpu + shared by HT threads
+ */
 static struct event_constraint *
-intel_percore_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
+                                   struct perf_event *event)
 {
-        struct hw_perf_event *hwc = &event->hw;
-        unsigned int e = hwc->config & ARCH_PERFMON_EVENTSEL_EVENT;
-        struct event_constraint *c;
-        struct intel_percore *pc;
+        struct event_constraint *c = &emptyconstraint;
+        struct hw_perf_event_extra *reg = &event->hw.extra_reg;
         struct er_account *era;
-        int i;
-        int free_slot;
-        int found;
+        unsigned long flags;
+        int orig_idx = reg->idx;
 
-        if (!x86_pmu.percore_constraints || hwc->extra_alloc)
-                return NULL;
+        /* already allocated shared msr */
+        if (reg->alloc)
+                return &unconstrained;
 
-        for (c = x86_pmu.percore_constraints; c->cmask; c++) {
-                if (e != c->code)
-                        continue;
+again:
+        era = &cpuc->shared_regs->regs[reg->idx];
+        /*
+         * we use spin_lock_irqsave() to avoid lockdep issues when
+         * passing a fake cpuc
+         */
+        raw_spin_lock_irqsave(&era->lock, flags);
+
+        if (!atomic_read(&era->ref) || era->config == reg->config) {
+
+                /* lock in msr value */
+                era->config = reg->config;
+                era->reg = reg->reg;
+
+                /* one more user */
+                atomic_inc(&era->ref);
+
+                /* no need to reallocate during incremental event scheduling */
+                reg->alloc = 1;
 
                 /*
-                 * Allocate resource per core.
+                 * All events using extra_reg are unconstrained.
+                 * Avoids calling x86_get_event_constraints()
+                 *
+                 * Must revisit if extra_reg controlling events
+                 * ever have constraints. Worst case we go through
+                 * the regular event constraint table.
                  */
-                pc = cpuc->per_core;
-                if (!pc)
-                        break;
-                c = &emptyconstraint;
-                raw_spin_lock(&pc->lock);
-                free_slot = -1;
-                found = 0;
-                for (i = 0; i < MAX_EXTRA_REGS; i++) {
-                        era = &pc->regs[i];
-                        if (era->ref > 0 && hwc->extra_reg == era->extra_reg) {
-                                /* Allow sharing same config */
-                                if (hwc->extra_config == era->extra_config) {
-                                        era->ref++;
-                                        cpuc->percore_used = 1;
-                                        hwc->extra_alloc = 1;
-                                        c = NULL;
-                                }
-                                /* else conflict */
-                                found = 1;
-                                break;
-                        } else if (era->ref == 0 && free_slot == -1)
-                                free_slot = i;
-                }
-                if (!found && free_slot != -1) {
-                        era = &pc->regs[free_slot];
-                        era->ref = 1;
-                        era->extra_reg = hwc->extra_reg;
-                        era->extra_config = hwc->extra_config;
-                        cpuc->percore_used = 1;
-                        hwc->extra_alloc = 1;
-                        c = NULL;
-                }
-                raw_spin_unlock(&pc->lock);
-                return c;
+                c = &unconstrained;
+        } else if (intel_try_alt_er(event, orig_idx)) {
+                raw_spin_unlock(&era->lock);
+                goto again;
         }
+        raw_spin_unlock_irqrestore(&era->lock, flags);
 
-        return NULL;
+        return c;
+}
+
+static void
+__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
+                                   struct hw_perf_event_extra *reg)
+{
+        struct er_account *era;
+
+        /*
+         * only put constraint if extra reg was actually
+         * allocated. Also takes care of event which do
+         * not use an extra shared reg
+         */
+        if (!reg->alloc)
+                return;
+
+        era = &cpuc->shared_regs->regs[reg->idx];
+
+        /* one fewer user */
+        atomic_dec(&era->ref);
+
+        /* allocate again next time */
+        reg->alloc = 0;
+}
+
+static struct event_constraint *
+intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
+                              struct perf_event *event)
+{
+        struct event_constraint *c = NULL;
+
+        if (event->hw.extra_reg.idx != EXTRA_REG_NONE)
+                c = __intel_shared_reg_get_constraints(cpuc, event);
+
+        return c;
 }
 
 static struct event_constraint *
@@ -1111,49 +1210,28 @@ intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event
         if (c)
                 return c;
 
-        c = intel_percore_constraints(cpuc, event);
+        c = intel_shared_regs_constraints(cpuc, event);
         if (c)
                 return c;
 
         return x86_get_event_constraints(cpuc, event);
 }
 
-static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
+static void
+intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
                                         struct perf_event *event)
 {
-        struct extra_reg *er;
-        struct intel_percore *pc;
-        struct er_account *era;
-        struct hw_perf_event *hwc = &event->hw;
-        int i, allref;
+        struct hw_perf_event_extra *reg;
 
-        if (!cpuc->percore_used)
-                return;
-
-        for (er = x86_pmu.extra_regs; er->msr; er++) {
-                if (er->event != (hwc->config & er->config_mask))
-                        continue;
+        reg = &event->hw.extra_reg;
+        if (reg->idx != EXTRA_REG_NONE)
+                __intel_shared_reg_put_constraints(cpuc, reg);
+}
 
-                pc = cpuc->per_core;
-                raw_spin_lock(&pc->lock);
-                for (i = 0; i < MAX_EXTRA_REGS; i++) {
-                        era = &pc->regs[i];
-                        if (era->ref > 0 &&
-                            era->extra_config == hwc->extra_config &&
-                            era->extra_reg == er->msr) {
-                                era->ref--;
-                                hwc->extra_alloc = 0;
-                                break;
-                        }
-                }
-                allref = 0;
-                for (i = 0; i < MAX_EXTRA_REGS; i++)
-                        allref += pc->regs[i].ref;
-                if (allref == 0)
-                        cpuc->percore_used = 0;
-                raw_spin_unlock(&pc->lock);
-                break;
-        }
+static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
+                                        struct perf_event *event)
+{
+        intel_put_shared_regs_event_constraints(cpuc, event);
 }
 
 static int intel_pmu_hw_config(struct perf_event *event)
@@ -1231,20 +1309,36 @@ static __initconst const struct x86_pmu core_pmu = {
         .event_constraints      = intel_core_event_constraints,
 };
 
+static struct intel_shared_regs *allocate_shared_regs(int cpu)
+{
+        struct intel_shared_regs *regs;
+        int i;
+
+        regs = kzalloc_node(sizeof(struct intel_shared_regs),
+                            GFP_KERNEL, cpu_to_node(cpu));
+        if (regs) {
+                /*
+                 * initialize the locks to keep lockdep happy
+                 */
+                for (i = 0; i < EXTRA_REG_MAX; i++)
+                        raw_spin_lock_init(&regs->regs[i].lock);
+
+                regs->core_id = -1;
+        }
+        return regs;
+}
+
 static int intel_pmu_cpu_prepare(int cpu)
 {
         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 
-        if (!cpu_has_ht_siblings())
+        if (!x86_pmu.extra_regs)
                 return NOTIFY_OK;
 
-        cpuc->per_core = kzalloc_node(sizeof(struct intel_percore),
-                                      GFP_KERNEL, cpu_to_node(cpu));
-        if (!cpuc->per_core)
+        cpuc->shared_regs = allocate_shared_regs(cpu);
+        if (!cpuc->shared_regs)
                 return NOTIFY_BAD;
 
-        raw_spin_lock_init(&cpuc->per_core->lock);
-        cpuc->per_core->core_id = -1;
         return NOTIFY_OK;
 }
 
@@ -1260,32 +1354,34 @@ static void intel_pmu_cpu_starting(int cpu)
          */
         intel_pmu_lbr_reset();
 
-        if (!cpu_has_ht_siblings())
+        if (!cpuc->shared_regs || (x86_pmu.er_flags & ERF_NO_HT_SHARING))
                 return;
 
         for_each_cpu(i, topology_thread_cpumask(cpu)) {
-                struct intel_percore *pc = per_cpu(cpu_hw_events, i).per_core;
+                struct intel_shared_regs *pc;
 
+                pc = per_cpu(cpu_hw_events, i).shared_regs;
                 if (pc && pc->core_id == core_id) {
-                        kfree(cpuc->per_core);
-                        cpuc->per_core = pc;
+                        kfree(cpuc->shared_regs);
+                        cpuc->shared_regs = pc;
                         break;
                 }
         }
 
-        cpuc->per_core->core_id = core_id;
-        cpuc->per_core->refcnt++;
+        cpuc->shared_regs->core_id = core_id;
+        cpuc->shared_regs->refcnt++;
 }
 
 static void intel_pmu_cpu_dying(int cpu)
 {
         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
-        struct intel_percore *pc = cpuc->per_core;
+        struct intel_shared_regs *pc;
 
+        pc = cpuc->shared_regs;
         if (pc) {
                 if (pc->core_id == -1 || --pc->refcnt == 0)
                         kfree(pc);
-                cpuc->per_core = NULL;
+                cpuc->shared_regs = NULL;
         }
 
         fini_debug_store_on_cpu(cpu);
@@ -1436,7 +1532,6 @@ static __init int intel_pmu_init(void)
 
                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
-                x86_pmu.percore_constraints = intel_nehalem_percore_constraints;
                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
 
@@ -1481,10 +1576,10 @@ static __init int intel_pmu_init(void)
                 intel_pmu_lbr_init_nhm();
 
                 x86_pmu.event_constraints = intel_westmere_event_constraints;
-                x86_pmu.percore_constraints = intel_westmere_percore_constraints;
                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
                 x86_pmu.extra_regs = intel_westmere_extra_regs;
+                x86_pmu.er_flags |= ERF_HAS_RSP_1;
 
                 /* UOPS_ISSUED.STALLED_CYCLES */
                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
@@ -1502,6 +1597,10 @@ static __init int intel_pmu_init(void)
 
                 x86_pmu.event_constraints = intel_snb_event_constraints;
                 x86_pmu.pebs_constraints = intel_snb_pebs_events;
+                x86_pmu.extra_regs = intel_snb_extra_regs;
+                /* all extra regs are per-cpu when HT is on */
+                x86_pmu.er_flags |= ERF_HAS_RSP_1;
+                x86_pmu.er_flags |= ERF_NO_HT_SHARING;
 
                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
@@ -1512,11 +1611,19 @@ static __init int intel_pmu_init(void)
                 break;
 
         default:
-                /*
-                 * default constraints for v2 and up
-                 */
-                x86_pmu.event_constraints = intel_gen_event_constraints;
-                pr_cont("generic architected perfmon, ");
+                switch (x86_pmu.version) {
+                case 1:
+                        x86_pmu.event_constraints = intel_v1_event_constraints;
+                        pr_cont("generic architected perfmon v1, ");
+                        break;
+                default:
+                        /*
+                         * default constraints for v2 and up
+                         */
+                        x86_pmu.event_constraints = intel_gen_event_constraints;
+                        pr_cont("generic architected perfmon, ");
+                        break;
+                }
         }
         return 0;
 }
@@ -1528,4 +1635,8 @@ static int intel_pmu_init(void)
         return 0;
 }
 
+static struct intel_shared_regs *allocate_shared_regs(int cpu)
+{
+        return NULL;
+}
 #endif /* CONFIG_CPU_SUP_INTEL */
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index bab491b8ee25..1b1ef3addcfd 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -340,7 +340,7 @@ static int intel_pmu_drain_bts_buffer(void)
          */
         perf_prepare_sample(&header, &data, event, &regs);
 
-        if (perf_output_begin(&handle, event, header.size * (top - at), 1, 1))
+        if (perf_output_begin(&handle, event, header.size * (top - at)))
                 return 1;
 
         for (; at < top; at++) {
@@ -616,7 +616,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
         else
                 regs.flags &= ~PERF_EFLAGS_EXACT;
 
-        if (perf_event_overflow(event, 1, &data, &regs))
+        if (perf_event_overflow(event, &data, &regs))
                 x86_pmu_stop(event, 0);
 }
 
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index ead584fb6a7d..7809d2bcb209 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -554,13 +554,102 @@ static __initconst const u64 p4_hw_cache_event_ids
                 [ C(RESULT_MISS)   ] = -1,
         },
  },
+ [ C(NODE) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
 };
 
+/*
+ * Because of Netburst being quite restricted in how many
+ * identical events may run simultaneously, we introduce event aliases,
+ * ie the different events which have the same functionality but
+ * utilize non-intersected resources (ESCR/CCCR/counter registers).
+ *
+ * This allow us to relax restrictions a bit and run two or more
+ * identical events together.
+ *
+ * Never set any custom internal bits such as P4_CONFIG_HT,
+ * P4_CONFIG_ALIASABLE or bits for P4_PEBS_METRIC, they are
+ * either up to date automatically or not applicable at all.
+ */
+struct p4_event_alias {
+        u64 original;
+        u64 alternative;
+} p4_event_aliases[] = {
+        {
+                /*
+                 * Non-halted cycles can be substituted with non-sleeping cycles (see
+                 * Intel SDM Vol3b for details). We need this alias to be able
+                 * to run nmi-watchdog and 'perf top' (or any other user space tool
+                 * which is interested in running PERF_COUNT_HW_CPU_CYCLES)
+                 * simultaneously.
+                 */
+        .original       =
+                p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS)         |
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)),
+        .alternative    =
+                p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_EXECUTION_EVENT)             |
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0)|
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1)|
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2)|
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3)|
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0) |
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1) |
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2) |
+                                    P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3))|
+                p4_config_pack_cccr(P4_CCCR_THRESHOLD(15) | P4_CCCR_COMPLEMENT          |
+                                    P4_CCCR_COMPARE),
+        },
+};
+
+static u64 p4_get_alias_event(u64 config)
+{
+        u64 config_match;
+        int i;
+
+        /*
+         * Only event with special mark is allowed,
+         * we're to be sure it didn't come as malformed
+         * RAW event.
+         */
+        if (!(config & P4_CONFIG_ALIASABLE))
+                return 0;
+
+        config_match = config & P4_CONFIG_EVENT_ALIAS_MASK;
+
+        for (i = 0; i < ARRAY_SIZE(p4_event_aliases); i++) {
+                if (config_match == p4_event_aliases[i].original) {
+                        config_match = p4_event_aliases[i].alternative;
+                        break;
+                } else if (config_match == p4_event_aliases[i].alternative) {
+                        config_match = p4_event_aliases[i].original;
+                        break;
+                }
+        }
+
+        if (i >= ARRAY_SIZE(p4_event_aliases))
+                return 0;
+
+        return config_match | (config & P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS);
+}
+
 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
   /* non-halted CPU clocks */
   [PERF_COUNT_HW_CPU_CYCLES] =
         p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS)         |
-                P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)),
+                P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING))       |
+                P4_CONFIG_ALIASABLE,
 
   /*
    * retired instructions
@@ -945,7 +1034,7 @@ static int p4_pmu_handle_irq(struct pt_regs *regs)
 
                 if (!x86_perf_event_set_period(event))
                         continue;
-                if (perf_event_overflow(event, 1, &data, regs))
+                if (perf_event_overflow(event, &data, regs))
                         x86_pmu_stop(event, 0);
         }
 
@@ -1120,6 +1209,8 @@ static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign
         struct p4_event_bind *bind;
         unsigned int i, thread, num;
         int cntr_idx, escr_idx;
+        u64 config_alias;
+        int pass;
 
         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
         bitmap_zero(escr_mask, P4_ESCR_MSR_TABLE_SIZE);
@@ -1128,6 +1219,17 @@ static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign
 
                 hwc = &cpuc->event_list[i]->hw;
                 thread = p4_ht_thread(cpu);
+                pass = 0;
+
+again:
+                /*
+                 * It's possible to hit a circular lock
+                 * between original and alternative events
+                 * if both are scheduled already.
+                 */
+                if (pass > 2)
+                        goto done;
+
                 bind = p4_config_get_bind(hwc->config);
                 escr_idx = p4_get_escr_idx(bind->escr_msr[thread]);
                 if (unlikely(escr_idx == -1))
@@ -1141,8 +1243,17 @@ static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign
                 }
 
                 cntr_idx = p4_next_cntr(thread, used_mask, bind);
-                if (cntr_idx == -1 || test_bit(escr_idx, escr_mask))
-                        goto done;
+                if (cntr_idx == -1 || test_bit(escr_idx, escr_mask)) {
+                        /*
+                         * Check whether an event alias is still available.
+                         */
+                        config_alias = p4_get_alias_event(hwc->config);
+                        if (!config_alias)
+                                goto done;
+                        hwc->config = config_alias;
+                        pass++;
+                        goto again;
+                }
 
                 p4_pmu_swap_config_ts(hwc, cpu);
                 if (assign)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 9aeb78a23de4..a621f3427685 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -134,6 +134,24 @@ static int __init add_bus_probe(void)
 module_init(add_bus_probe);
 
 #ifdef CONFIG_PCI
+struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
+{
+        struct device_node *np;
+
+        for_each_node_by_type(np, "pci") {
+                const void *prop;
+                unsigned int bus_min;
+
+                prop = of_get_property(np, "bus-range", NULL);
+                if (!prop)
+                        continue;
+                bus_min = be32_to_cpup(prop);
+                if (bus->number == bus_min)
+                        return np;
+        }
+        return NULL;
+}
+
 static int x86_of_pci_irq_enable(struct pci_dev *dev)
 {
         struct of_irq oirq;
@@ -165,50 +183,8 @@ static void x86_of_pci_irq_disable(struct pci_dev *dev)
 
 void __cpuinit x86_of_pci_init(void)
 {
-        struct device_node *np;
-
         pcibios_enable_irq = x86_of_pci_irq_enable;
         pcibios_disable_irq = x86_of_pci_irq_disable;
-
-        for_each_node_by_type(np, "pci") {
-                const void *prop;
-                struct pci_bus *bus;
-                unsigned int bus_min;
-                struct device_node *child;
-
-                prop = of_get_property(np, "bus-range", NULL);
-                if (!prop)
-                        continue;
-                bus_min = be32_to_cpup(prop);
-
-                bus = pci_find_bus(0, bus_min);
-                if (!bus) {
-                        printk(KERN_ERR "Can't find a node for bus %s.\n",
-                                        np->full_name);
-                        continue;
-                }
-
-                if (bus->self)
-                        bus->self->dev.of_node = np;
-                else
-                        bus->dev.of_node = np;
-
-                for_each_child_of_node(np, child) {
-                        struct pci_dev *dev;
-                        u32 devfn;
-
-                        prop = of_get_property(child, "reg", NULL);
-                        if (!prop)
-                                continue;
-
-                        devfn = (be32_to_cpup(prop) >> 8) & 0xff;
-                        dev = pci_get_slot(bus, devfn);
-                        if (!dev)
-                                continue;
-                        dev->dev.of_node = child;
-                        pci_dev_put(dev);
-                }
-        }
 }
 #endif
 
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index e71c98d3c0d2..19853ad8afc5 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -105,34 +105,6 @@ in_irq_stack(unsigned long *stack, unsigned long *irq_stack,
 }
 
 /*
- * We are returning from the irq stack and go to the previous one.
- * If the previous stack is also in the irq stack, then bp in the first
- * frame of the irq stack points to the previous, interrupted one.
- * Otherwise we have another level of indirection: We first save
- * the bp of the previous stack, then we switch the stack to the irq one
- * and save a new bp that links to the previous one.
- * (See save_args())
- */
-static inline unsigned long
-fixup_bp_irq_link(unsigned long bp, unsigned long *stack,
-                  unsigned long *irq_stack, unsigned long *irq_stack_end)
-{
-#ifdef CONFIG_FRAME_POINTER
-        struct stack_frame *frame = (struct stack_frame *)bp;
-        unsigned long next;
-
-        if (!in_irq_stack(stack, irq_stack, irq_stack_end)) {
-                if (!probe_kernel_address(&frame->next_frame, next))
-                        return next;
-                else
-                        WARN_ONCE(1, "Perf: bad frame pointer = %p in "
-                                  "callchain\n", &frame->next_frame);
-        }
-#endif
-        return bp;
-}
-
-/*
  * x86-64 can have up to three kernel stacks:
  * process stack
  * interrupt stack
@@ -155,9 +127,12 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                 task = current;
 
         if (!stack) {
-                stack = &dummy;
-                if (task && task != current)
+                if (regs)
+                        stack = (unsigned long *)regs->sp;
+                else if (task && task != current)
                         stack = (unsigned long *)task->thread.sp;
+                else
+                        stack = &dummy;
         }
 
         if (!bp)
@@ -205,8 +180,6 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                                  * pointer (index -1 to end) in the IRQ stack:
                                  */
                                 stack = (unsigned long *) (irq_stack_end[-1]);
-                                bp = fixup_bp_irq_link(bp, stack, irq_stack,
-                                                       irq_stack_end);
                                 irq_stack_end = NULL;
                                 ops->stack(data, "EOI");
                                 continue;
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 8a445a0c989e..e13329d800c8 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -9,6 +9,8 @@
 /*
  * entry.S contains the system-call and fault low-level handling routines.
  *
+ * Some of this is documented in Documentation/x86/entry_64.txt
+ *
  * NOTE: This code handles signal-recognition, which happens every time
  * after an interrupt and after each system call.
  *
@@ -297,27 +299,26 @@ ENDPROC(native_usergs_sysret64)
         .endm
 
 /* save partial stack frame */
-        .pushsection .kprobes.text, "ax"
-ENTRY(save_args)
-        XCPT_FRAME
+        .macro SAVE_ARGS_IRQ
         cld
-        /*
-         * start from rbp in pt_regs and jump over
-         * return address.
-         */
-        movq_cfi rdi, RDI+8-RBP
-        movq_cfi rsi, RSI+8-RBP
-        movq_cfi rdx, RDX+8-RBP
-        movq_cfi rcx, RCX+8-RBP
-        movq_cfi rax, RAX+8-RBP
-        movq_cfi  r8,  R8+8-RBP
-        movq_cfi  r9,  R9+8-RBP
-        movq_cfi r10, R10+8-RBP
-        movq_cfi r11, R11+8-RBP
-
-        leaq -RBP+8(%rsp),%rdi  /* arg1 for handler */
-        movq_cfi rbp, 8         /* push %rbp */
-        leaq 8(%rsp), %rbp              /* mov %rsp, %ebp */
+        /* start from rbp in pt_regs and jump over */
+        movq_cfi rdi, RDI-RBP
+        movq_cfi rsi, RSI-RBP
+        movq_cfi rdx, RDX-RBP
+        movq_cfi rcx, RCX-RBP
+        movq_cfi rax, RAX-RBP
+        movq_cfi  r8,  R8-RBP
+        movq_cfi  r9,  R9-RBP
+        movq_cfi r10, R10-RBP
+        movq_cfi r11, R11-RBP
+
+        /* Save rbp so that we can unwind from get_irq_regs() */
+        movq_cfi rbp, 0
+
+        /* Save previous stack value */
+        movq %rsp, %rsi
+
+        leaq -RBP(%rsp),%rdi    /* arg1 for handler */
         testl $3, CS(%rdi)
         je 1f
         SWAPGS
@@ -329,19 +330,14 @@ ENTRY(save_args)
          */
 1:      incl PER_CPU_VAR(irq_count)
         jne 2f
-        popq_cfi %rax                   /* move return address... */
         mov PER_CPU_VAR(irq_stack_ptr),%rsp
         EMPTY_FRAME 0
-        pushq_cfi %rbp                  /* backlink for unwinder */
-        pushq_cfi %rax                  /* ... to the new stack */
-        /*
-         * We entered an interrupt context - irqs are off:
-         */
-2:      TRACE_IRQS_OFF
-        ret
-        CFI_ENDPROC
-END(save_args)
-        .popsection
+
+2:      /* Store previous stack value */
+        pushq %rsi
+        /* We entered an interrupt context - irqs are off: */
+        TRACE_IRQS_OFF
+        .endm
 
 ENTRY(save_rest)
         PARTIAL_FRAME 1 REST_SKIP+8
@@ -473,7 +469,7 @@ ENTRY(system_call_after_swapgs)
          * and short:
          */
         ENABLE_INTERRUPTS(CLBR_NONE)
-        SAVE_ARGS 8,1
+        SAVE_ARGS 8,0
         movq  %rax,ORIG_RAX-ARGOFFSET(%rsp)
         movq  %rcx,RIP-ARGOFFSET(%rsp)
         CFI_REL_OFFSET rip,RIP-ARGOFFSET
@@ -508,7 +504,7 @@ sysret_check:
         TRACE_IRQS_ON
         movq RIP-ARGOFFSET(%rsp),%rcx
         CFI_REGISTER    rip,rcx
-        RESTORE_ARGS 0,-ARG_SKIP,1
+        RESTORE_ARGS 1,-ARG_SKIP,0
         /*CFI_REGISTER  rflags,r11*/
         movq    PER_CPU_VAR(old_rsp), %rsp
         USERGS_SYSRET64
@@ -791,7 +787,7 @@ END(interrupt)
         /* reserve pt_regs for scratch regs and rbp */
         subq $ORIG_RAX-RBP, %rsp
         CFI_ADJUST_CFA_OFFSET ORIG_RAX-RBP
-        call save_args
+        SAVE_ARGS_IRQ
         PARTIAL_FRAME 0
         call \func
         .endm
@@ -814,15 +810,14 @@ ret_from_intr:
         DISABLE_INTERRUPTS(CLBR_NONE)
         TRACE_IRQS_OFF
         decl PER_CPU_VAR(irq_count)
-        leaveq
 
-        CFI_RESTORE             rbp
+        /* Restore saved previous stack */
+        popq %rsi
+        leaq 16(%rsi), %rsp
+
         CFI_DEF_CFA_REGISTER    rsp
-        CFI_ADJUST_CFA_OFFSET   -8
+        CFI_ADJUST_CFA_OFFSET   -16
 
-        /* we did not save rbx, restore only from ARGOFFSET */
-        addq $8, %rsp
-        CFI_ADJUST_CFA_OFFSET   -8
 exit_intr:
         GET_THREAD_INFO(%rcx)
         testl $3,CS-ARGOFFSET(%rsp)
@@ -858,7 +853,7 @@ retint_restore_args:	/* return to kernel space */
          */
         TRACE_IRQS_IRETQ
 restore_args:
-        RESTORE_ARGS 0,8,0
+        RESTORE_ARGS 1,8,1
 
 irq_return:
         INTERRUPT_RETURN
@@ -991,11 +986,6 @@ apicinterrupt THRESHOLD_APIC_VECTOR \
 apicinterrupt THERMAL_APIC_VECTOR \
         thermal_interrupt smp_thermal_interrupt
 
-#ifdef CONFIG_X86_MCE
-apicinterrupt MCE_SELF_VECTOR \
-        mce_self_interrupt smp_mce_self_interrupt
-#endif
-
 #ifdef CONFIG_SMP
 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR \
         call_function_single_interrupt smp_call_function_single_interrupt
@@ -1121,6 +1111,8 @@ zeroentry spurious_interrupt_bug do_spurious_interrupt_bug
 zeroentry coprocessor_error do_coprocessor_error
 errorentry alignment_check do_alignment_check
 zeroentry simd_coprocessor_error do_simd_coprocessor_error
+zeroentry emulate_vsyscall do_emulate_vsyscall
+
 
         /* Reload gs selector with exception handling */
         /* edi:  new selector */
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 6781765b3a0d..4aecc54236a9 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -4,6 +4,7 @@
 #include <linux/sysdev.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/i8253.h>
 #include <linux/slab.h>
 #include <linux/hpet.h>
 #include <linux/init.h>
@@ -12,8 +13,8 @@
 #include <linux/io.h>
 
 #include <asm/fixmap.h>
-#include <asm/i8253.h>
 #include <asm/hpet.h>
+#include <asm/time.h>
 
 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
 
@@ -71,7 +72,7 @@ static inline void hpet_set_mapping(void)
 {
         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
 #ifdef CONFIG_X86_64
-        __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
+        __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
 #endif
 }
 
@@ -738,13 +739,6 @@ static cycle_t read_hpet(struct clocksource *cs)
         return (cycle_t)hpet_readl(HPET_COUNTER);
 }
 
-#ifdef CONFIG_X86_64
-static cycle_t __vsyscall_fn vread_hpet(void)
-{
-        return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
-}
-#endif
-
 static struct clocksource clocksource_hpet = {
         .name           = "hpet",
         .rating         = 250,
@@ -753,7 +747,7 @@ static struct clocksource clocksource_hpet = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
         .resume         = hpet_resume_counter,
 #ifdef CONFIG_X86_64
-        .vread          = vread_hpet,
+        .archdata       = { .vclock_mode = VCLOCK_HPET },
 #endif
 };
 
diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index fb66dc9e36cb..f2b96de3c7c1 100644
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -3,113 +3,24 @@
  *
  */
 #include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/jiffies.h>
 #include <linux/module.h>
 #include <linux/timex.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
+#include <linux/i8253.h>
 
-#include <asm/i8253.h>
 #include <asm/hpet.h>
+#include <asm/time.h>
 #include <asm/smp.h>
 
-DEFINE_RAW_SPINLOCK(i8253_lock);
-EXPORT_SYMBOL(i8253_lock);
-
 /*
  * HPET replaces the PIT, when enabled. So we need to know, which of
  * the two timers is used
  */
 struct clock_event_device *global_clock_event;
 
-/*
- * Initialize the PIT timer.
- *
- * This is also called after resume to bring the PIT into operation again.
- */
-static void init_pit_timer(enum clock_event_mode mode,
-                           struct clock_event_device *evt)
-{
-        raw_spin_lock(&i8253_lock);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                /* binary, mode 2, LSB/MSB, ch 0 */
-                outb_pit(0x34, PIT_MODE);
-                outb_pit(LATCH & 0xff , PIT_CH0);       /* LSB */
-                outb_pit(LATCH >> 8 , PIT_CH0);         /* MSB */
-                break;
-
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-                if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
-                    evt->mode == CLOCK_EVT_MODE_ONESHOT) {
-                        outb_pit(0x30, PIT_MODE);
-                        outb_pit(0, PIT_CH0);
-                        outb_pit(0, PIT_CH0);
-                }
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* One shot setup */
-                outb_pit(0x38, PIT_MODE);
-                break;
-
-        case CLOCK_EVT_MODE_RESUME:
-                /* Nothing to do here */
-                break;
-        }
-        raw_spin_unlock(&i8253_lock);
-}
-
-/*
- * Program the next event in oneshot mode
- *
- * Delta is given in PIT ticks
- */
-static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
-{
-        raw_spin_lock(&i8253_lock);
-        outb_pit(delta & 0xff , PIT_CH0);       /* LSB */
-        outb_pit(delta >> 8 , PIT_CH0);         /* MSB */
-        raw_spin_unlock(&i8253_lock);
-
-        return 0;
-}
-
-/*
- * On UP the PIT can serve all of the possible timer functions. On SMP systems
- * it can be solely used for the global tick.
- *
- * The profiling and update capabilities are switched off once the local apic is
- * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
- * !using_apic_timer decisions in do_timer_interrupt_hook()
- */
-static struct clock_event_device pit_ce = {
-        .name           = "pit",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = init_pit_timer,
-        .set_next_event = pit_next_event,
-        .irq            = 0,
-};
-
-/*
- * Initialize the conversion factor and the min/max deltas of the clock event
- * structure and register the clock event source with the framework.
- */
 void __init setup_pit_timer(void)
 {
-        /*
-         * Start pit with the boot cpu mask and make it global after the
-         * IO_APIC has been initialized.
-         */
-        pit_ce.cpumask = cpumask_of(smp_processor_id());
-
-        clockevents_config_and_register(&pit_ce, CLOCK_TICK_RATE, 0xF, 0x7FFF);
-        global_clock_event = &pit_ce;
+        clockevent_i8253_init(true);
+        global_clock_event = &i8253_clockevent;
 }
 
 #ifndef CONFIG_X86_64
@@ -123,7 +34,7 @@ static int __init init_pit_clocksource(void)
           * - when local APIC timer is active (PIT is switched off)
           */
         if (num_possible_cpus() > 1 || is_hpet_enabled() ||
-            pit_ce.mode != CLOCK_EVT_MODE_PERIODIC)
+            i8253_clockevent.mode != CLOCK_EVT_MODE_PERIODIC)
                 return 0;
 
         return clocksource_i8253_init();
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index f470e4ef993e..f09d4bbe2d2d 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -272,9 +272,6 @@ static void __init apic_intr_init(void)
 #ifdef CONFIG_X86_MCE_THRESHOLD
         alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 #endif
-#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
-        alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
-#endif
 
 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
         /* self generated IPI for local APIC timer */
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 5f9ecff328b5..00354d4919a9 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -608,7 +608,7 @@ int kgdb_arch_init(void)
         return register_die_notifier(&kgdb_notifier);
 }
 
-static void kgdb_hw_overflow_handler(struct perf_event *event, int nmi,
+static void kgdb_hw_overflow_handler(struct perf_event *event,
                 struct perf_sample_data *data, struct pt_regs *regs)
 {
         struct task_struct *tsk = current;
@@ -638,7 +638,7 @@ void kgdb_arch_late(void)
         for (i = 0; i < HBP_NUM; i++) {
                 if (breakinfo[i].pev)
                         continue;
-                breakinfo[i].pev = register_wide_hw_breakpoint(&attr, NULL);
+                breakinfo[i].pev = register_wide_hw_breakpoint(&attr, NULL, NULL);
                 if (IS_ERR((void * __force)breakinfo[i].pev)) {
                         printk(KERN_ERR "kgdb: Could not allocate hw"
                                "breakpoints\nDisabling the kernel debugger\n");
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index c5610384ab16..591be0ee1934 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -66,8 +66,8 @@ struct microcode_amd {
         unsigned int                    mpb[0];
 };
 
-#define UCODE_CONTAINER_SECTION_HDR     8
-#define UCODE_CONTAINER_HEADER_SIZE     12
+#define SECTION_HDR_SIZE        8
+#define CONTAINER_HDR_SZ        12
 
 static struct equiv_cpu_entry *equiv_cpu_table;
 
@@ -157,7 +157,7 @@ static int apply_microcode_amd(int cpu)
 static unsigned int verify_ucode_size(int cpu, const u8 *buf, unsigned int size)
 {
         struct cpuinfo_x86 *c = &cpu_data(cpu);
-        unsigned int max_size, actual_size;
+        u32 max_size, actual_size;
 
 #define F1XH_MPB_MAX_SIZE 2048
 #define F14H_MPB_MAX_SIZE 1824
@@ -175,9 +175,9 @@ static unsigned int verify_ucode_size(int cpu, const u8 *buf, unsigned int size)
                 break;
         }
 
-        actual_size = buf[4] + (buf[5] << 8);
+        actual_size = *(u32 *)(buf + 4);
 
-        if (actual_size > size || actual_size > max_size) {
+        if (actual_size + SECTION_HDR_SIZE > size || actual_size > max_size) {
                 pr_err("section size mismatch\n");
                 return 0;
         }
@@ -191,7 +191,7 @@ get_next_ucode(int cpu, const u8 *buf, unsigned int size, unsigned int *mc_size)
         struct microcode_header_amd *mc = NULL;
         unsigned int actual_size = 0;
 
-        if (buf[0] != UCODE_UCODE_TYPE) {
+        if (*(u32 *)buf != UCODE_UCODE_TYPE) {
                 pr_err("invalid type field in container file section header\n");
                 goto out;
         }
@@ -204,8 +204,8 @@ get_next_ucode(int cpu, const u8 *buf, unsigned int size, unsigned int *mc_size)
         if (!mc)
                 goto out;
 
-        get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, actual_size);
-        *mc_size = actual_size + UCODE_CONTAINER_SECTION_HDR;
+        get_ucode_data(mc, buf + SECTION_HDR_SIZE, actual_size);
+        *mc_size = actual_size + SECTION_HDR_SIZE;
 
 out:
         return mc;
@@ -229,9 +229,10 @@ static int install_equiv_cpu_table(const u8 *buf)
                 return -ENOMEM;
         }
 
-        get_ucode_data(equiv_cpu_table, buf + UCODE_CONTAINER_HEADER_SIZE, size);
+        get_ucode_data(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
 
-        return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
+        /* add header length */
+        return size + CONTAINER_HDR_SZ;
 }
 
 static void free_equiv_cpu_table(void)
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 807c2a2b80f1..82528799c5de 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -528,7 +528,7 @@ static int genregs_set(struct task_struct *target,
         return ret;
 }
 
-static void ptrace_triggered(struct perf_event *bp, int nmi,
+static void ptrace_triggered(struct perf_event *bp,
                              struct perf_sample_data *data,
                              struct pt_regs *regs)
 {
@@ -715,7 +715,8 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
                 attr.bp_type = HW_BREAKPOINT_W;
                 attr.disabled = 1;
 
-                bp = register_user_hw_breakpoint(&attr, ptrace_triggered, tsk);
+                bp = register_user_hw_breakpoint(&attr, ptrace_triggered,
+                                                 NULL, tsk);
 
                 /*
                  * CHECKME: the previous code returned -EIO if the addr wasn't
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 8bbe8c56916d..b78643d0f9a5 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -10,7 +10,7 @@
 
 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
 {
-        u8 config, rev;
+        u8 config;
         u16 word;
 
         /* BIOS may enable hardware IRQ balancing for
@@ -18,8 +18,7 @@ static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
          * based platforms.
          * Disable SW irqbalance/affinity on those platforms.
          */
-        pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
-        if (rev > 0x9)
+        if (dev->revision > 0x9)
                 return;
 
         /* enable access to config space*/
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 0c016f727695..9242436e9937 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -294,6 +294,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
                         DMI_MATCH(DMI_BOARD_NAME, "VersaLogic Menlow board"),
                 },
         },
+        { /* Handle reboot issue on Acer Aspire one */
+                .callback = set_bios_reboot,
+                .ident = "Acer Aspire One A110",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "AOA110"),
+                },
+        },
         { }
 };
 
@@ -411,6 +419,30 @@ static struct dmi_system_id __initdata pci_reboot_dmi_table[] = {
                         DMI_MATCH(DMI_PRODUCT_NAME, "iMac9,1"),
                 },
         },
+        {       /* Handle problems with rebooting on the Latitude E6320. */
+                .callback = set_pci_reboot,
+                .ident = "Dell Latitude E6320",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6320"),
+                },
+        },
+        {       /* Handle problems with rebooting on the Latitude E5420. */
+                .callback = set_pci_reboot,
+                .ident = "Dell Latitude E5420",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E5420"),
+                },
+        },
+        {       /* Handle problems with rebooting on the Latitude E6420. */
+                .callback = set_pci_reboot,
+                .ident = "Dell Latitude E6420",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6420"),
+                },
+        },
         { }
 };
 
diff --git a/arch/x86/kernel/relocate_kernel_32.S b/arch/x86/kernel/relocate_kernel_32.S
index 41235531b11c..36818f8ec2be 100644
--- a/arch/x86/kernel/relocate_kernel_32.S
+++ b/arch/x86/kernel/relocate_kernel_32.S
@@ -97,6 +97,8 @@ relocate_kernel:
         ret
 
 identity_mapped:
+        /* set return address to 0 if not preserving context */
+        pushl   $0
         /* store the start address on the stack */
         pushl   %edx
 
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S
index 4de8f5b3d476..7a6f3b3be3cf 100644
--- a/arch/x86/kernel/relocate_kernel_64.S
+++ b/arch/x86/kernel/relocate_kernel_64.S
@@ -100,6 +100,8 @@ relocate_kernel:
         ret
 
 identity_mapped:
+        /* set return address to 0 if not preserving context */
+        pushq   $0
         /* store the start address on the stack */
         pushq   %rdx
 
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 40a24932a8a1..54ddaeb221c1 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -485,17 +485,18 @@ static int __setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
 asmlinkage int
 sys_sigsuspend(int history0, int history1, old_sigset_t mask)
 {
-        mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
+        sigset_t blocked;
+
         current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+
+        mask &= _BLOCKABLE;
+        siginitset(&blocked, mask);
+        set_current_blocked(&blocked);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
-        set_restore_sigmask();
 
+        set_restore_sigmask();
         return -ERESTARTNOHAND;
 }
 
@@ -572,10 +573,7 @@ unsigned long sys_sigreturn(struct pt_regs *regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         if (restore_sigcontext(regs, &frame->sc, &ax))
                 goto badframe;
@@ -653,11 +651,15 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka,
 
 static int
 setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-               sigset_t *set, struct pt_regs *regs)
+                struct pt_regs *regs)
 {
         int usig = signr_convert(sig);
+        sigset_t *set = &current->blocked;
         int ret;
 
+        if (current_thread_info()->status & TS_RESTORE_SIGMASK)
+                set = &current->saved_sigmask;
+
         /* Set up the stack frame */
         if (is_ia32) {
                 if (ka->sa.sa_flags & SA_SIGINFO)
@@ -672,12 +674,13 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 return -EFAULT;
         }
 
+        current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
         return ret;
 }
 
 static int
 handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
-              sigset_t *oldset, struct pt_regs *regs)
+                struct pt_regs *regs)
 {
         sigset_t blocked;
         int ret;
@@ -712,20 +715,11 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
             likely(test_and_clear_thread_flag(TIF_FORCED_TF)))
                 regs->flags &= ~X86_EFLAGS_TF;
 
-        ret = setup_rt_frame(sig, ka, info, oldset, regs);
+        ret = setup_rt_frame(sig, ka, info, regs);
 
         if (ret)
                 return ret;
 
-#ifdef CONFIG_X86_64
-        /*
-         * This has nothing to do with segment registers,
-         * despite the name.  This magic affects uaccess.h
-         * macros' behavior.  Reset it to the normal setting.
-         */
-        set_fs(USER_DS);
-#endif
-
         /*
          * Clear the direction flag as per the ABI for function entry.
          */
@@ -767,7 +761,6 @@ static void do_signal(struct pt_regs *regs)
         struct k_sigaction ka;
         siginfo_t info;
         int signr;
-        sigset_t *oldset;
 
         /*
          * We want the common case to go fast, which is why we may in certain
@@ -779,23 +772,10 @@ static void do_signal(struct pt_regs *regs)
         if (!user_mode(regs))
                 return;
 
-        if (current_thread_info()->status & TS_RESTORE_SIGMASK)
-                oldset = &current->saved_sigmask;
-        else
-                oldset = &current->blocked;
-
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
         if (signr > 0) {
                 /* Whee! Actually deliver the signal.  */
-                if (handle_signal(signr, &info, &ka, oldset, regs) == 0) {
-                        /*
-                         * A signal was successfully delivered; the saved
-                         * sigmask will have been stored in the signal frame,
-                         * and will be restored by sigreturn, so we can simply
-                         * clear the TS_RESTORE_SIGMASK flag.
-                         */
-                        current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-                }
+                handle_signal(signr, &info, &ka, regs);
                 return;
         }
 
@@ -823,7 +803,7 @@ static void do_signal(struct pt_regs *regs)
          */
         if (current_thread_info()->status & TS_RESTORE_SIGMASK) {
                 current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+                set_current_blocked(&current->saved_sigmask);
         }
 }
 
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 9fd3137230d4..9f548cb4a958 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -438,7 +438,7 @@ static void impress_friends(void)
 void __inquire_remote_apic(int apicid)
 {
         unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
-        char *names[] = { "ID", "VERSION", "SPIV" };
+        const char * const names[] = { "ID", "VERSION", "SPIV" };
         int timeout;
         u32 status;
 
diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c
index 55d9bc03f696..fdd0c6430e5a 100644
--- a/arch/x86/kernel/stacktrace.c
+++ b/arch/x86/kernel/stacktrace.c
@@ -66,7 +66,7 @@ void save_stack_trace(struct stack_trace *trace)
 }
 EXPORT_SYMBOL_GPL(save_stack_trace);
 
-void save_stack_trace_regs(struct stack_trace *trace, struct pt_regs *regs)
+void save_stack_trace_regs(struct pt_regs *regs, struct stack_trace *trace)
 {
         dump_trace(current, regs, NULL, 0, &save_stack_ops, trace);
         if (trace->nr_entries < trace->max_entries)
diff --git a/arch/x86/kernel/tboot.c b/arch/x86/kernel/tboot.c
index 30ac65df7d4e..e07a2fc876b9 100644
--- a/arch/x86/kernel/tboot.c
+++ b/arch/x86/kernel/tboot.c
@@ -36,6 +36,7 @@
 #include <asm/bootparam.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
+#include <asm/swiotlb.h>
 #include <asm/fixmap.h>
 #include <asm/proto.h>
 #include <asm/setup.h>
diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c
index 00cbb272627f..5a64d057be57 100644
--- a/arch/x86/kernel/time.c
+++ b/arch/x86/kernel/time.c
@@ -11,13 +11,13 @@
 
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
+#include <linux/i8253.h>
 #include <linux/time.h>
 #include <linux/mca.h>
 
 #include <asm/vsyscall.h>
 #include <asm/x86_init.h>
 #include <asm/i8259.h>
-#include <asm/i8253.h>
 #include <asm/timer.h>
 #include <asm/hpet.h>
 #include <asm/time.h>
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index b9b67166f9de..fbc097a085ca 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -872,6 +872,12 @@ void __init trap_init(void)
         set_bit(SYSCALL_VECTOR, used_vectors);
 #endif
 
+#ifdef CONFIG_X86_64
+        BUG_ON(test_bit(VSYSCALL_EMU_VECTOR, used_vectors));
+        set_system_intr_gate(VSYSCALL_EMU_VECTOR, &emulate_vsyscall);
+        set_bit(VSYSCALL_EMU_VECTOR, used_vectors);
+#endif
+
         /*
          * Should be a barrier for any external CPU state:
          */
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 6cc6922262af..db483369f10b 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -5,7 +5,6 @@
 #include <linux/timer.h>
 #include <linux/acpi_pmtmr.h>
 #include <linux/cpufreq.h>
-#include <linux/dmi.h>
 #include <linux/delay.h>
 #include <linux/clocksource.h>
 #include <linux/percpu.h>
@@ -777,7 +776,7 @@ static struct clocksource clocksource_tsc = {
         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
                                   CLOCK_SOURCE_MUST_VERIFY,
 #ifdef CONFIG_X86_64
-        .vread                  = vread_tsc,
+        .archdata               = { .vclock_mode = VCLOCK_TSC },
 #endif
 };
 
@@ -800,27 +799,6 @@ void mark_tsc_unstable(char *reason)
 
 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
 
-static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
-{
-        printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
-                        d->ident);
-        tsc_unstable = 1;
-        return 0;
-}
-
-/* List of systems that have known TSC problems */
-static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
-        {
-                .callback = dmi_mark_tsc_unstable,
-                .ident = "IBM Thinkpad 380XD",
-                .matches = {
-                        DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
-                        DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
-                },
-        },
-        {}
-};
-
 static void __init check_system_tsc_reliable(void)
 {
 #ifdef CONFIG_MGEODE_LX
@@ -1010,8 +988,6 @@ void __init tsc_init(void)
         lpj_fine = lpj;
 
         use_tsc_delay();
-        /* Check and install the TSC clocksource */
-        dmi_check_system(bad_tsc_dmi_table);
 
         if (unsynchronized_tsc())
                 mark_tsc_unstable("TSCs unsynchronized");
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 89aed99aafce..4aa9c54a9b76 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -161,50 +161,47 @@ SECTIONS
 
 #define VVIRT_OFFSET (VSYSCALL_ADDR - __vsyscall_0)
 #define VVIRT(x) (ADDR(x) - VVIRT_OFFSET)
-#define EMIT_VVAR(x, offset) .vsyscall_var_ ## x        \
-        ADDR(.vsyscall_0) + offset                      \
-        : AT(VLOAD(.vsyscall_var_ ## x)) {              \
-                *(.vsyscall_var_ ## x)                  \
-        }                                               \
-        x = VVIRT(.vsyscall_var_ ## x);
 
         . = ALIGN(4096);
         __vsyscall_0 = .;
 
         . = VSYSCALL_ADDR;
-        .vsyscall_0 : AT(VLOAD(.vsyscall_0)) {
+        .vsyscall : AT(VLOAD(.vsyscall)) {
                 *(.vsyscall_0)
-        } :user
 
-        . = ALIGN(L1_CACHE_BYTES);
-        .vsyscall_fn : AT(VLOAD(.vsyscall_fn)) {
-                *(.vsyscall_fn)
-        }
-
-        .vsyscall_1 ADDR(.vsyscall_0) + 1024: AT(VLOAD(.vsyscall_1)) {
+                . = 1024;
                 *(.vsyscall_1)
-        }
-        .vsyscall_2 ADDR(.vsyscall_0) + 2048: AT(VLOAD(.vsyscall_2)) {
-                *(.vsyscall_2)
-        }
 
-        .vsyscall_3 ADDR(.vsyscall_0) + 3072: AT(VLOAD(.vsyscall_3)) {
-                *(.vsyscall_3)
-        }
-
-#define __VVAR_KERNEL_LDS
-#include <asm/vvar.h>
-#undef __VVAR_KERNEL_LDS
+                . = 2048;
+                *(.vsyscall_2)
 
-        . = __vsyscall_0 + PAGE_SIZE;
+                . = 4096;  /* Pad the whole page. */
+        } :user =0xcc
+        . = ALIGN(__vsyscall_0 + PAGE_SIZE, PAGE_SIZE);
 
 #undef VSYSCALL_ADDR
 #undef VLOAD_OFFSET
 #undef VLOAD
 #undef VVIRT_OFFSET
 #undef VVIRT
+
+        __vvar_page = .;
+
+        .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) {
+
+              /* Place all vvars at the offsets in asm/vvar.h. */
+#define EMIT_VVAR(name, offset)                 \
+                . = offset;             \
+                *(.vvar_ ## name)
+#define __VVAR_KERNEL_LDS
+#include <asm/vvar.h>
+#undef __VVAR_KERNEL_LDS
 #undef EMIT_VVAR
 
+        } :data
+
+       . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE);
+
 #endif /* CONFIG_X86_64 */
 
         /* Init code and data - will be freed after init */
diff --git a/arch/x86/kernel/vread_tsc_64.c b/arch/x86/kernel/vread_tsc_64.c
deleted file mode 100644
index a81aa9e9894c..000000000000
--- a/arch/x86/kernel/vread_tsc_64.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* This code runs in userspace. */
-
-#define DISABLE_BRANCH_PROFILING
-#include <asm/vgtod.h>
-
-notrace cycle_t __vsyscall_fn vread_tsc(void)
-{
-        cycle_t ret;
-        u64 last;
-
-        /*
-         * Empirically, a fence (of type that depends on the CPU)
-         * before rdtsc is enough to ensure that rdtsc is ordered
-         * with respect to loads.  The various CPU manuals are unclear
-         * as to whether rdtsc can be reordered with later loads,
-         * but no one has ever seen it happen.
-         */
-        rdtsc_barrier();
-        ret = (cycle_t)vget_cycles();
-
-        last = VVAR(vsyscall_gtod_data).clock.cycle_last;
-
-        if (likely(ret >= last))
-                return ret;
-
-        /*
-         * GCC likes to generate cmov here, but this branch is extremely
-         * predictable (it's just a funciton of time and the likely is
-         * very likely) and there's a data dependence, so force GCC
-         * to generate a branch instead.  I don't barrier() because
-         * we don't actually need a barrier, and if this function
-         * ever gets inlined it will generate worse code.
-         */
-        asm volatile ("");
-        return last;
-}
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index 3e682184d76c..dda7dff9cef7 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -2,6 +2,8 @@
  *  Copyright (C) 2001 Andrea Arcangeli <andrea@suse.de> SuSE
  *  Copyright 2003 Andi Kleen, SuSE Labs.
  *
+ *  [ NOTE: this mechanism is now deprecated in favor of the vDSO. ]
+ *
  *  Thanks to hpa@transmeta.com for some useful hint.
  *  Special thanks to Ingo Molnar for his early experience with
  *  a different vsyscall implementation for Linux/IA32 and for the name.
@@ -11,10 +13,9 @@
  *  vsyscalls. One vsyscall can reserve more than 1 slot to avoid
  *  jumping out of line if necessary. We cannot add more with this
  *  mechanism because older kernels won't return -ENOSYS.
- *  If we want more than four we need a vDSO.
  *
- *  Note: the concept clashes with user mode linux. If you use UML and
- *  want per guest time just set the kernel.vsyscall64 sysctl to 0.
+ *  Note: the concept clashes with user mode linux.  UML users should
+ *  use the vDSO.
  */
 
 /* Disable profiling for userspace code: */
@@ -32,9 +33,12 @@
 #include <linux/cpu.h>
 #include <linux/smp.h>
 #include <linux/notifier.h>
+#include <linux/syscalls.h>
+#include <linux/ratelimit.h>
 
 #include <asm/vsyscall.h>
 #include <asm/pgtable.h>
+#include <asm/compat.h>
 #include <asm/page.h>
 #include <asm/unistd.h>
 #include <asm/fixmap.h>
@@ -44,16 +48,12 @@
 #include <asm/desc.h>
 #include <asm/topology.h>
 #include <asm/vgtod.h>
-
-#define __vsyscall(nr) \
-                __attribute__ ((unused, __section__(".vsyscall_" #nr))) notrace
-#define __syscall_clobber "r11","cx","memory"
+#include <asm/traps.h>
 
 DEFINE_VVAR(int, vgetcpu_mode);
 DEFINE_VVAR(struct vsyscall_gtod_data, vsyscall_gtod_data) =
 {
         .lock = __SEQLOCK_UNLOCKED(__vsyscall_gtod_data.lock),
-        .sysctl_enabled = 1,
 };
 
 void update_vsyscall_tz(void)
@@ -72,179 +72,149 @@ void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
         unsigned long flags;
 
         write_seqlock_irqsave(&vsyscall_gtod_data.lock, flags);
+
         /* copy vsyscall data */
-        vsyscall_gtod_data.clock.vread = clock->vread;
-        vsyscall_gtod_data.clock.cycle_last = clock->cycle_last;
-        vsyscall_gtod_data.clock.mask = clock->mask;
-        vsyscall_gtod_data.clock.mult = mult;
-        vsyscall_gtod_data.clock.shift = clock->shift;
-        vsyscall_gtod_data.wall_time_sec = wall_time->tv_sec;
-        vsyscall_gtod_data.wall_time_nsec = wall_time->tv_nsec;
-        vsyscall_gtod_data.wall_to_monotonic = *wtm;
-        vsyscall_gtod_data.wall_time_coarse = __current_kernel_time();
+        vsyscall_gtod_data.clock.vclock_mode    = clock->archdata.vclock_mode;
+        vsyscall_gtod_data.clock.cycle_last     = clock->cycle_last;
+        vsyscall_gtod_data.clock.mask           = clock->mask;
+        vsyscall_gtod_data.clock.mult           = mult;
+        vsyscall_gtod_data.clock.shift          = clock->shift;
+        vsyscall_gtod_data.wall_time_sec        = wall_time->tv_sec;
+        vsyscall_gtod_data.wall_time_nsec       = wall_time->tv_nsec;
+        vsyscall_gtod_data.wall_to_monotonic    = *wtm;
+        vsyscall_gtod_data.wall_time_coarse     = __current_kernel_time();
+
         write_sequnlock_irqrestore(&vsyscall_gtod_data.lock, flags);
 }
 
-/* RED-PEN may want to readd seq locking, but then the variable should be
- * write-once.
- */
-static __always_inline void do_get_tz(struct timezone * tz)
+static void warn_bad_vsyscall(const char *level, struct pt_regs *regs,
+                              const char *message)
 {
-        *tz = VVAR(vsyscall_gtod_data).sys_tz;
-}
+        static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST);
+        struct task_struct *tsk;
 
-static __always_inline int gettimeofday(struct timeval *tv, struct timezone *tz)
-{
-        int ret;
-        asm volatile("syscall"
-                : "=a" (ret)
-                : "0" (__NR_gettimeofday),"D" (tv),"S" (tz)
-                : __syscall_clobber );
-        return ret;
-}
+        if (!show_unhandled_signals || !__ratelimit(&rs))
+                return;
 
-static __always_inline long time_syscall(long *t)
-{
-        long secs;
-        asm volatile("syscall"
-                : "=a" (secs)
-                : "0" (__NR_time),"D" (t) : __syscall_clobber);
-        return secs;
-}
+        tsk = current;
 
-static __always_inline void do_vgettimeofday(struct timeval * tv)
-{
-        cycle_t now, base, mask, cycle_delta;
-        unsigned seq;
-        unsigned long mult, shift, nsec;
-        cycle_t (*vread)(void);
-        do {
-                seq = read_seqbegin(&VVAR(vsyscall_gtod_data).lock);
-
-                vread = VVAR(vsyscall_gtod_data).clock.vread;
-                if (unlikely(!VVAR(vsyscall_gtod_data).sysctl_enabled ||
-                             !vread)) {
-                        gettimeofday(tv,NULL);
-                        return;
-                }
-
-                now = vread();
-                base = VVAR(vsyscall_gtod_data).clock.cycle_last;
-                mask = VVAR(vsyscall_gtod_data).clock.mask;
-                mult = VVAR(vsyscall_gtod_data).clock.mult;
-                shift = VVAR(vsyscall_gtod_data).clock.shift;
-
-                tv->tv_sec = VVAR(vsyscall_gtod_data).wall_time_sec;
-                nsec = VVAR(vsyscall_gtod_data).wall_time_nsec;
-        } while (read_seqretry(&VVAR(vsyscall_gtod_data).lock, seq));
-
-        /* calculate interval: */
-        cycle_delta = (now - base) & mask;
-        /* convert to nsecs: */
-        nsec += (cycle_delta * mult) >> shift;
-
-        while (nsec >= NSEC_PER_SEC) {
-                tv->tv_sec += 1;
-                nsec -= NSEC_PER_SEC;
-        }
-        tv->tv_usec = nsec / NSEC_PER_USEC;
+        printk("%s%s[%d] %s ip:%lx cs:%lx sp:%lx ax:%lx si:%lx di:%lx\n",
+               level, tsk->comm, task_pid_nr(tsk),
+               message, regs->ip - 2, regs->cs,
+               regs->sp, regs->ax, regs->si, regs->di);
 }
 
-int __vsyscall(0) vgettimeofday(struct timeval * tv, struct timezone * tz)
+static int addr_to_vsyscall_nr(unsigned long addr)
 {
-        if (tv)
-                do_vgettimeofday(tv);
-        if (tz)
-                do_get_tz(tz);
-        return 0;
-}
+        int nr;
 
-/* This will break when the xtime seconds get inaccurate, but that is
- * unlikely */
-time_t __vsyscall(1) vtime(time_t *t)
-{
-        unsigned seq;
-        time_t result;
-        if (unlikely(!VVAR(vsyscall_gtod_data).sysctl_enabled))
-                return time_syscall(t);
+        if ((addr & ~0xC00UL) != VSYSCALL_START)
+                return -EINVAL;
 
-        do {
-                seq = read_seqbegin(&VVAR(vsyscall_gtod_data).lock);
+        nr = (addr & 0xC00UL) >> 10;
+        if (nr >= 3)
+                return -EINVAL;
 
-                result = VVAR(vsyscall_gtod_data).wall_time_sec;
+        return nr;
+}
 
-        } while (read_seqretry(&VVAR(vsyscall_gtod_data).lock, seq));
+void dotraplinkage do_emulate_vsyscall(struct pt_regs *regs, long error_code)
+{
+        struct task_struct *tsk;
+        unsigned long caller;
+        int vsyscall_nr;
+        long ret;
+
+        local_irq_enable();
+
+        /*
+         * Real 64-bit user mode code has cs == __USER_CS.  Anything else
+         * is bogus.
+         */
+        if (regs->cs != __USER_CS) {
+                /*
+                 * If we trapped from kernel mode, we might as well OOPS now
+                 * instead of returning to some random address and OOPSing
+                 * then.
+                 */
+                BUG_ON(!user_mode(regs));
+
+                /* Compat mode and non-compat 32-bit CS should both segfault. */
+                warn_bad_vsyscall(KERN_WARNING, regs,
+                                  "illegal int 0xcc from 32-bit mode");
+                goto sigsegv;
+        }
 
-        if (t)
-                *t = result;
-        return result;
-}
+        /*
+         * x86-ism here: regs->ip points to the instruction after the int 0xcc,
+         * and int 0xcc is two bytes long.
+         */
+        vsyscall_nr = addr_to_vsyscall_nr(regs->ip - 2);
+        if (vsyscall_nr < 0) {
+                warn_bad_vsyscall(KERN_WARNING, regs,
+                                  "illegal int 0xcc (exploit attempt?)");
+                goto sigsegv;
+        }
 
-/* Fast way to get current CPU and node.
-   This helps to do per node and per CPU caches in user space.
-   The result is not guaranteed without CPU affinity, but usually
-   works out because the scheduler tries to keep a thread on the same
-   CPU.
+        if (get_user(caller, (unsigned long __user *)regs->sp) != 0) {
+                warn_bad_vsyscall(KERN_WARNING, regs, "int 0xcc with bad stack (exploit attempt?)");
+                goto sigsegv;
+        }
 
-   tcache must point to a two element sized long array.
-   All arguments can be NULL. */
-long __vsyscall(2)
-vgetcpu(unsigned *cpu, unsigned *node, struct getcpu_cache *tcache)
-{
-        unsigned int p;
-        unsigned long j = 0;
-
-        /* Fast cache - only recompute value once per jiffies and avoid
-           relatively costly rdtscp/cpuid otherwise.
-           This works because the scheduler usually keeps the process
-           on the same CPU and this syscall doesn't guarantee its
-           results anyways.
-           We do this here because otherwise user space would do it on
-           its own in a likely inferior way (no access to jiffies).
-           If you don't like it pass NULL. */
-        if (tcache && tcache->blob[0] == (j = VVAR(jiffies))) {
-                p = tcache->blob[1];
-        } else if (VVAR(vgetcpu_mode) == VGETCPU_RDTSCP) {
-                /* Load per CPU data from RDTSCP */
-                native_read_tscp(&p);
-        } else {
-                /* Load per CPU data from GDT */
-                asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG));
+        tsk = current;
+        if (seccomp_mode(&tsk->seccomp))
+                do_exit(SIGKILL);
+
+        switch (vsyscall_nr) {
+        case 0:
+                ret = sys_gettimeofday(
+                        (struct timeval __user *)regs->di,
+                        (struct timezone __user *)regs->si);
+                break;
+
+        case 1:
+                ret = sys_time((time_t __user *)regs->di);
+                break;
+
+        case 2:
+                ret = sys_getcpu((unsigned __user *)regs->di,
+                                 (unsigned __user *)regs->si,
+                                 0);
+                break;
         }
-        if (tcache) {
-                tcache->blob[0] = j;
-                tcache->blob[1] = p;
+
+        if (ret == -EFAULT) {
+                /*
+                 * Bad news -- userspace fed a bad pointer to a vsyscall.
+                 *
+                 * With a real vsyscall, that would have caused SIGSEGV.
+                 * To make writing reliable exploits using the emulated
+                 * vsyscalls harder, generate SIGSEGV here as well.
+                 */
+                warn_bad_vsyscall(KERN_INFO, regs,
+                                  "vsyscall fault (exploit attempt?)");
+                goto sigsegv;
         }
-        if (cpu)
-                *cpu = p & 0xfff;
-        if (node)
-                *node = p >> 12;
-        return 0;
-}
 
-static long __vsyscall(3) venosys_1(void)
-{
-        return -ENOSYS;
-}
+        regs->ax = ret;
 
-#ifdef CONFIG_SYSCTL
-static ctl_table kernel_table2[] = {
-        { .procname = "vsyscall64",
-          .data = &vsyscall_gtod_data.sysctl_enabled, .maxlen = sizeof(int),
-          .mode = 0644,
-          .proc_handler = proc_dointvec },
-        {}
-};
+        /* Emulate a ret instruction. */
+        regs->ip = caller;
+        regs->sp += 8;
 
-static ctl_table kernel_root_table2[] = {
-        { .procname = "kernel", .mode = 0555,
-          .child = kernel_table2 },
-        {}
-};
-#endif
+        local_irq_disable();
+        return;
+
+sigsegv:
+        regs->ip -= 2;  /* The faulting instruction should be the int 0xcc. */
+        force_sig(SIGSEGV, current);
+        local_irq_disable();
+}
 
-/* Assume __initcall executes before all user space. Hopefully kmod
-   doesn't violate that. We'll find out if it does. */
+/*
+ * Assume __initcall executes before all user space. Hopefully kmod
+ * doesn't violate that. We'll find out if it does.
+ */
 static void __cpuinit vsyscall_set_cpu(int cpu)
 {
         unsigned long d;
@@ -255,13 +225,15 @@ static void __cpuinit vsyscall_set_cpu(int cpu)
         if (cpu_has(&cpu_data(cpu), X86_FEATURE_RDTSCP))
                 write_rdtscp_aux((node << 12) | cpu);
 
-        /* Store cpu number in limit so that it can be loaded quickly
-           in user space in vgetcpu.
-           12 bits for the CPU and 8 bits for the node. */
+        /*
+         * Store cpu number in limit so that it can be loaded quickly
+         * in user space in vgetcpu. (12 bits for the CPU and 8 bits for the node)
+         */
         d = 0x0f40000000000ULL;
         d |= cpu;
         d |= (node & 0xf) << 12;
         d |= (node >> 4) << 48;
+
         write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_PER_CPU, &d, DESCTYPE_S);
 }
 
@@ -275,8 +247,10 @@ static int __cpuinit
 cpu_vsyscall_notifier(struct notifier_block *n, unsigned long action, void *arg)
 {
         long cpu = (long)arg;
+
         if (action == CPU_ONLINE || action == CPU_ONLINE_FROZEN)
                 smp_call_function_single(cpu, cpu_vsyscall_init, NULL, 1);
+
         return NOTIFY_DONE;
 }
 
@@ -284,25 +258,23 @@ void __init map_vsyscall(void)
 {
         extern char __vsyscall_0;
         unsigned long physaddr_page0 = __pa_symbol(&__vsyscall_0);
+        extern char __vvar_page;
+        unsigned long physaddr_vvar_page = __pa_symbol(&__vvar_page);
 
         /* Note that VSYSCALL_MAPPED_PAGES must agree with the code below. */
         __set_fixmap(VSYSCALL_FIRST_PAGE, physaddr_page0, PAGE_KERNEL_VSYSCALL);
+        __set_fixmap(VVAR_PAGE, physaddr_vvar_page, PAGE_KERNEL_VVAR);
+        BUILD_BUG_ON((unsigned long)__fix_to_virt(VVAR_PAGE) != (unsigned long)VVAR_ADDRESS);
 }
 
 static int __init vsyscall_init(void)
 {
-        BUG_ON(((unsigned long) &vgettimeofday !=
-                        VSYSCALL_ADDR(__NR_vgettimeofday)));
-        BUG_ON((unsigned long) &vtime != VSYSCALL_ADDR(__NR_vtime));
-        BUG_ON((VSYSCALL_ADDR(0) != __fix_to_virt(VSYSCALL_FIRST_PAGE)));
-        BUG_ON((unsigned long) &vgetcpu != VSYSCALL_ADDR(__NR_vgetcpu));
-#ifdef CONFIG_SYSCTL
-        register_sysctl_table(kernel_root_table2);
-#endif
+        BUG_ON(VSYSCALL_ADDR(0) != __fix_to_virt(VSYSCALL_FIRST_PAGE));
+
         on_each_cpu(cpu_vsyscall_init, NULL, 1);
         /* notifier priority > KVM */
         hotcpu_notifier(cpu_vsyscall_notifier, 30);
+
         return 0;
 }
-
 __initcall(vsyscall_init);
diff --git a/arch/x86/kernel/vsyscall_emu_64.S b/arch/x86/kernel/vsyscall_emu_64.S
new file mode 100644
index 000000000000..ffa845eae5ca
--- /dev/null
+++ b/arch/x86/kernel/vsyscall_emu_64.S
@@ -0,0 +1,27 @@
+/*
+ * vsyscall_emu_64.S: Vsyscall emulation page
+ *
+ * Copyright (c) 2011 Andy Lutomirski
+ *
+ * Subject to the GNU General Public License, version 2
+ */
+
+#include <linux/linkage.h>
+#include <asm/irq_vectors.h>
+
+/* The unused parts of the page are filled with 0xcc by the linker script. */
+
+.section .vsyscall_0, "a"
+ENTRY(vsyscall_0)
+        int $VSYSCALL_EMU_VECTOR
+END(vsyscall_0)
+
+.section .vsyscall_1, "a"
+ENTRY(vsyscall_1)
+        int $VSYSCALL_EMU_VECTOR
+END(vsyscall_1)
+
+.section .vsyscall_2, "a"
+ENTRY(vsyscall_2)
+        int $VSYSCALL_EMU_VECTOR
+END(vsyscall_2)
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 99c3f0589faa..988724b236b6 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -77,6 +77,5 @@ config KVM_MMU_AUDIT
 # the virtualization menu.
 source drivers/vhost/Kconfig
 source drivers/lguest/Kconfig
-source drivers/virtio/Kconfig
 
 endif # VIRTUALIZATION
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index db832fd65ecb..13ee258442ae 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -71,7 +71,8 @@
 #include <asm/stackprotector.h>
 #include <asm/reboot.h>         /* for struct machine_ops */
 
-/*G:010 Welcome to the Guest!
+/*G:010
+ * Welcome to the Guest!
  *
  * The Guest in our tale is a simple creature: identical to the Host but
  * behaving in simplified but equivalent ways.  In particular, the Guest is the
@@ -190,15 +191,23 @@ static void lazy_hcall4(unsigned long call,
 #endif
 
 /*G:036
- * When lazy mode is turned off reset the per-cpu lazy mode variable and then
- * issue the do-nothing hypercall to flush any stored calls.
-:*/
+ * When lazy mode is turned off, we issue the do-nothing hypercall to
+ * flush any stored calls, and call the generic helper to reset the
+ * per-cpu lazy mode variable.
+ */
 static void lguest_leave_lazy_mmu_mode(void)
 {
         hcall(LHCALL_FLUSH_ASYNC, 0, 0, 0, 0);
         paravirt_leave_lazy_mmu();
 }
 
+/*
+ * We also catch the end of context switch; we enter lazy mode for much of
+ * that too, so again we need to flush here.
+ *
+ * (Technically, this is lazy CPU mode, and normally we're in lazy MMU
+ * mode, but unlike Xen, lguest doesn't care about the difference).
+ */
 static void lguest_end_context_switch(struct task_struct *next)
 {
         hcall(LHCALL_FLUSH_ASYNC, 0, 0, 0, 0);
@@ -391,7 +400,7 @@ static void lguest_load_tr_desc(void)
  * giant ball of hair.  Its entry in the current Intel manual runs to 28 pages.
  *
  * This instruction even it has its own Wikipedia entry.  The Wikipedia entry
- * has been translated into 5 languages.  I am not making this up!
+ * has been translated into 6 languages.  I am not making this up!
  *
  * We could get funky here and identify ourselves as "GenuineLguest", but
  * instead we just use the real "cpuid" instruction.  Then I pretty much turned
@@ -458,7 +467,7 @@ static void lguest_cpuid(unsigned int *ax, unsigned int *bx,
         /*
          * PAE systems can mark pages as non-executable.  Linux calls this the
          * NX bit.  Intel calls it XD (eXecute Disable), AMD EVP (Enhanced
-         * Virus Protection).  We just switch turn if off here, since we don't
+         * Virus Protection).  We just switch it off here, since we don't
          * support it.
          */
         case 0x80000001:
@@ -520,17 +529,16 @@ static unsigned long lguest_read_cr2(void)
 
 /* See lguest_set_pte() below. */
 static bool cr3_changed = false;
+static unsigned long current_cr3;
 
 /*
  * cr3 is the current toplevel pagetable page: the principle is the same as
- * cr0.  Keep a local copy, and tell the Host when it changes.  The only
- * difference is that our local copy is in lguest_data because the Host needs
- * to set it upon our initial hypercall.
+ * cr0.  Keep a local copy, and tell the Host when it changes.
  */
 static void lguest_write_cr3(unsigned long cr3)
 {
-        lguest_data.pgdir = cr3;
         lazy_hcall1(LHCALL_NEW_PGTABLE, cr3);
+        current_cr3 = cr3;
 
         /* These two page tables are simple, linear, and used during boot */
         if (cr3 != __pa(swapper_pg_dir) && cr3 != __pa(initial_page_table))
@@ -539,7 +547,7 @@ static void lguest_write_cr3(unsigned long cr3)
 
 static unsigned long lguest_read_cr3(void)
 {
-        return lguest_data.pgdir;
+        return current_cr3;
 }
 
 /* cr4 is used to enable and disable PGE, but we don't care. */
@@ -641,7 +649,7 @@ static void lguest_write_cr4(unsigned long val)
 
 /*
  * The Guest calls this after it has set a second-level entry (pte), ie. to map
- * a page into a process' address space.  Wetell the Host the toplevel and
+ * a page into a process' address space.  We tell the Host the toplevel and
  * address this corresponds to.  The Guest uses one pagetable per process, so
  * we need to tell the Host which one we're changing (mm->pgd).
  */
@@ -758,7 +766,7 @@ static void lguest_pmd_clear(pmd_t *pmdp)
 static void lguest_flush_tlb_single(unsigned long addr)
 {
         /* Simply set it to zero: if it was not, it will fault back in. */
-        lazy_hcall3(LHCALL_SET_PTE, lguest_data.pgdir, addr, 0);
+        lazy_hcall3(LHCALL_SET_PTE, current_cr3, addr, 0);
 }
 
 /*
@@ -1140,7 +1148,7 @@ static struct notifier_block paniced = {
 static __init char *lguest_memory_setup(void)
 {
         /*
-         *The Linux bootloader header contains an "e820" memory map: the
+         * The Linux bootloader header contains an "e820" memory map: the
          * Launcher populated the first entry with our memory limit.
          */
         e820_add_region(boot_params.e820_map[0].addr,
diff --git a/arch/x86/lguest/i386_head.S b/arch/x86/lguest/i386_head.S
index 4f420c2f2d55..6ddfe4fc23c3 100644
--- a/arch/x86/lguest/i386_head.S
+++ b/arch/x86/lguest/i386_head.S
@@ -6,18 +6,22 @@
 #include <asm/processor-flags.h>
 
 /*G:020
- * Our story starts with the kernel booting into startup_32 in
- * arch/x86/kernel/head_32.S.  It expects a boot header, which is created by
- * the bootloader (the Launcher in our case).
+
+ * Our story starts with the bzImage: booting starts at startup_32 in
+ * arch/x86/boot/compressed/head_32.S.  This merely uncompresses the real
+ * kernel in place and then jumps into it: startup_32 in
+ * arch/x86/kernel/head_32.S.  Both routines expects a boot header in the %esi
+ * register, which is created by the bootloader (the Launcher in our case).
  *
  * The startup_32 function does very little: it clears the uninitialized global
  * C variables which we expect to be zero (ie. BSS) and then copies the boot
- * header and kernel command line somewhere safe.  Finally it checks the
- * 'hardware_subarch' field.  This was introduced in 2.6.24 for lguest and Xen:
- * if it's set to '1' (lguest's assigned number), then it calls us here.
+ * header and kernel command line somewhere safe, and populates some initial
+ * page tables.  Finally it checks the 'hardware_subarch' field.  This was
+ * introduced in 2.6.24 for lguest and Xen: if it's set to '1' (lguest's
+ * assigned number), then it calls us here.
  *
  * WARNING: be very careful here!  We're running at addresses equal to physical
- * addesses (around 0), not above PAGE_OFFSET as most code expectes
+ * addresses (around 0), not above PAGE_OFFSET as most code expects
  * (eg. 0xC0000000).  Jumps are relative, so they're OK, but we can't touch any
  * data without remembering to subtract __PAGE_OFFSET!
  *
@@ -27,13 +31,18 @@
 .section .init.text, "ax", @progbits
 ENTRY(lguest_entry)
         /*
-         * We make the "initialization" hypercall now to tell the Host about
-         * us, and also find out where it put our page tables.
+         * We make the "initialization" hypercall now to tell the Host where
+         * our lguest_data struct is.
          */
         movl $LHCALL_LGUEST_INIT, %eax
         movl $lguest_data - __PAGE_OFFSET, %ebx
         int $LGUEST_TRAP_ENTRY
 
+        /* Now turn our pagetables on; setup by arch/x86/kernel/head_32.S. */
+        movl $LHCALL_NEW_PGTABLE, %eax
+        movl $(initial_page_table - __PAGE_OFFSET), %ebx
+        int $LGUEST_TRAP_ENTRY
+
         /* Set up the initial stack so we can run C code. */
         movl $(init_thread_union+THREAD_SIZE),%esp
 
@@ -96,12 +105,8 @@ send_interrupts:
          */
         pushl %eax
         movl $LHCALL_SEND_INTERRUPTS, %eax
-        /*
-         * This is a vmcall instruction (same thing that KVM uses).  Older
-         * assembler versions might not know the "vmcall" instruction, so we
-         * create one manually here.
-         */
-        .byte 0x0f,0x01,0xc1 /* KVM_HYPERCALL */
+        /* This is the actual hypercall trap. */
+        int  $LGUEST_TRAP_ENTRY
         /* Put eax back the way we found it. */
         popl %eax
         ret
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f2479f19ddde..b00f6785da74 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -18,8 +18,10 @@ obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o
 
 lib-y := delay.o
 lib-y += thunk_$(BITS).o
-lib-y += usercopy_$(BITS).o getuser.o putuser.o
+lib-y += usercopy_$(BITS).o usercopy.o getuser.o putuser.o
 lib-y += memcpy_$(BITS).o
+lib-$(CONFIG_SMP) += rwlock.o
+lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
 lib-$(CONFIG_INSTRUCTION_DECODER) += insn.o inat.o
 
 obj-y += msr.o msr-reg.o msr-reg-export.o
@@ -29,7 +31,7 @@ ifeq ($(CONFIG_X86_32),y)
         lib-y += atomic64_cx8_32.o
         lib-y += checksum_32.o
         lib-y += strstr_32.o
-        lib-y += semaphore_32.o string_32.o
+        lib-y += string_32.o
         lib-y += cmpxchg.o
 ifneq ($(CONFIG_X86_CMPXCHG64),y)
         lib-y += cmpxchg8b_emu.o atomic64_386_32.o
@@ -40,7 +42,6 @@ else
         lib-y += csum-partial_64.o csum-copy_64.o csum-wrappers_64.o
         lib-y += thunk_64.o clear_page_64.o copy_page_64.o
         lib-y += memmove_64.o memset_64.o
-        lib-y += copy_user_64.o rwlock_64.o copy_user_nocache_64.o
-        lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem_64.o
+        lib-y += copy_user_64.o copy_user_nocache_64.o
         lib-y += cmpxchg16b_emu.o
 endif
diff --git a/arch/x86/lib/copy_page_64.S b/arch/x86/lib/copy_page_64.S
index 6fec2d1cebe1..01c805ba5359 100644
--- a/arch/x86/lib/copy_page_64.S
+++ b/arch/x86/lib/copy_page_64.S
@@ -2,6 +2,7 @@
 
 #include <linux/linkage.h>
 #include <asm/dwarf2.h>
+#include <asm/alternative-asm.h>
 
         ALIGN
 copy_page_c:
@@ -110,10 +111,6 @@ ENDPROC(copy_page)
 2:
         .previous
         .section .altinstructions,"a"
-        .align 8
-        .quad copy_page
-        .quad 1b
-        .word X86_FEATURE_REP_GOOD
-        .byte .Lcopy_page_end - copy_page
-        .byte 2b - 1b
+        altinstruction_entry copy_page, 1b, X86_FEATURE_REP_GOOD,       \
+                .Lcopy_page_end-copy_page, 2b-1b
         .previous
diff --git a/arch/x86/lib/memmove_64.S b/arch/x86/lib/memmove_64.S
index d0ec9c2936d7..ee164610ec46 100644
--- a/arch/x86/lib/memmove_64.S
+++ b/arch/x86/lib/memmove_64.S
@@ -9,6 +9,7 @@
 #include <linux/linkage.h>
 #include <asm/dwarf2.h>
 #include <asm/cpufeature.h>
+#include <asm/alternative-asm.h>
 
 #undef memmove
 
@@ -214,11 +215,9 @@ ENTRY(memmove)
         .previous
 
         .section .altinstructions,"a"
-        .align 8
-        .quad .Lmemmove_begin_forward
-        .quad .Lmemmove_begin_forward_efs
-        .word X86_FEATURE_ERMS
-        .byte .Lmemmove_end_forward-.Lmemmove_begin_forward
-        .byte .Lmemmove_end_forward_efs-.Lmemmove_begin_forward_efs
+        altinstruction_entry .Lmemmove_begin_forward,           \
+                .Lmemmove_begin_forward_efs,X86_FEATURE_ERMS,   \
+                .Lmemmove_end_forward-.Lmemmove_begin_forward,  \
+                .Lmemmove_end_forward_efs-.Lmemmove_begin_forward_efs
         .previous
 ENDPROC(memmove)
diff --git a/arch/x86/lib/rwlock.S b/arch/x86/lib/rwlock.S
new file mode 100644
index 000000000000..1cad22139c88
--- /dev/null
+++ b/arch/x86/lib/rwlock.S
@@ -0,0 +1,44 @@
+/* Slow paths of read/write spinlocks. */
+
+#include <linux/linkage.h>
+#include <asm/alternative-asm.h>
+#include <asm/frame.h>
+#include <asm/rwlock.h>
+
+#ifdef CONFIG_X86_32
+# define __lock_ptr eax
+#else
+# define __lock_ptr rdi
+#endif
+
+ENTRY(__write_lock_failed)
+        CFI_STARTPROC
+        FRAME
+0:      LOCK_PREFIX
+        WRITE_LOCK_ADD($RW_LOCK_BIAS) (%__lock_ptr)
+1:      rep; nop
+        cmpl    $WRITE_LOCK_CMP, (%__lock_ptr)
+        jne     1b
+        LOCK_PREFIX
+        WRITE_LOCK_SUB($RW_LOCK_BIAS) (%__lock_ptr)
+        jnz     0b
+        ENDFRAME
+        ret
+        CFI_ENDPROC
+END(__write_lock_failed)
+
+ENTRY(__read_lock_failed)
+        CFI_STARTPROC
+        FRAME
+0:      LOCK_PREFIX
+        READ_LOCK_SIZE(inc) (%__lock_ptr)
+1:      rep; nop
+        READ_LOCK_SIZE(cmp) $1, (%__lock_ptr)
+        js      1b
+        LOCK_PREFIX
+        READ_LOCK_SIZE(dec) (%__lock_ptr)
+        js      0b
+        ENDFRAME
+        ret
+        CFI_ENDPROC
+END(__read_lock_failed)
diff --git a/arch/x86/lib/rwlock_64.S b/arch/x86/lib/rwlock_64.S
deleted file mode 100644
index 05ea55f71405..000000000000
--- a/arch/x86/lib/rwlock_64.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Slow paths of read/write spinlocks. */
-
-#include <linux/linkage.h>
-#include <asm/rwlock.h>
-#include <asm/alternative-asm.h>
-#include <asm/dwarf2.h>
-
-/* rdi: pointer to rwlock_t */
-ENTRY(__write_lock_failed)
-        CFI_STARTPROC
-        LOCK_PREFIX
-        addl $RW_LOCK_BIAS,(%rdi)
-1:      rep
-        nop
-        cmpl $RW_LOCK_BIAS,(%rdi)
-        jne 1b
-        LOCK_PREFIX
-        subl $RW_LOCK_BIAS,(%rdi)
-        jnz  __write_lock_failed
-        ret
-        CFI_ENDPROC
-END(__write_lock_failed)
-
-/* rdi: pointer to rwlock_t */
-ENTRY(__read_lock_failed)
-        CFI_STARTPROC
-        LOCK_PREFIX
-        incl (%rdi)
-1:      rep
-        nop
-        cmpl $1,(%rdi)
-        js 1b
-        LOCK_PREFIX
-        decl (%rdi)
-        js __read_lock_failed
-        ret
-        CFI_ENDPROC
-END(__read_lock_failed)
diff --git a/arch/x86/lib/rwsem_64.S b/arch/x86/lib/rwsem.S
index 67743977398b..5dff5f042468 100644
--- a/arch/x86/lib/rwsem_64.S
+++ b/arch/x86/lib/rwsem.S
@@ -1,4 +1,51 @@
 /*
+ * x86 semaphore implementation.
+ *
+ * (C) Copyright 1999 Linus Torvalds
+ *
+ * Portions Copyright 1999 Red Hat, Inc.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ * rw semaphores implemented November 1999 by Benjamin LaHaise <bcrl@kvack.org>
+ */
+
+#include <linux/linkage.h>
+#include <asm/alternative-asm.h>
+#include <asm/dwarf2.h>
+
+#define __ASM_HALF_REG(reg)     __ASM_SEL(reg, e##reg)
+#define __ASM_HALF_SIZE(inst)   __ASM_SEL(inst##w, inst##l)
+
+#ifdef CONFIG_X86_32
+
+/*
+ * The semaphore operations have a special calling sequence that
+ * allow us to do a simpler in-line version of them. These routines
+ * need to convert that sequence back into the C sequence when
+ * there is contention on the semaphore.
+ *
+ * %eax contains the semaphore pointer on entry. Save the C-clobbered
+ * registers (%eax, %edx and %ecx) except %eax whish is either a return
+ * value or just clobbered..
+ */
+
+#define save_common_regs \
+        pushl_cfi %ecx; CFI_REL_OFFSET ecx, 0
+
+#define restore_common_regs \
+        popl_cfi %ecx; CFI_RESTORE ecx
+
+        /* Avoid uglifying the argument copying x86-64 needs to do. */
+        .macro movq src, dst
+        .endm
+
+#else
+
+/*
  * x86-64 rwsem wrappers
  *
  * This interfaces the inline asm code to the slow-path
@@ -16,12 +63,6 @@
  * but %rdi, %rsi, %rcx, %r8-r11 always need saving.
  */
 
-#include <linux/linkage.h>
-#include <asm/rwlock.h>
-#include <asm/alternative-asm.h>
-#include <asm/frame.h>
-#include <asm/dwarf2.h>
-
 #define save_common_regs \
         pushq_cfi %rdi; CFI_REL_OFFSET rdi, 0; \
         pushq_cfi %rsi; CFI_REL_OFFSET rsi, 0; \
@@ -40,16 +81,18 @@
         popq_cfi %rsi; CFI_RESTORE rsi; \
         popq_cfi %rdi; CFI_RESTORE rdi
 
+#endif
+
 /* Fix up special calling conventions */
 ENTRY(call_rwsem_down_read_failed)
         CFI_STARTPROC
         save_common_regs
-        pushq_cfi %rdx
-        CFI_REL_OFFSET rdx, 0
+        __ASM_SIZE(push,_cfi) %__ASM_REG(dx)
+        CFI_REL_OFFSET __ASM_REG(dx), 0
         movq %rax,%rdi
         call rwsem_down_read_failed
-        popq_cfi %rdx
-        CFI_RESTORE rdx
+        __ASM_SIZE(pop,_cfi) %__ASM_REG(dx)
+        CFI_RESTORE __ASM_REG(dx)
         restore_common_regs
         ret
         CFI_ENDPROC
@@ -67,7 +110,8 @@ ENDPROC(call_rwsem_down_write_failed)
 
 ENTRY(call_rwsem_wake)
         CFI_STARTPROC
-        decl %edx       /* do nothing if still outstanding active readers */
+        /* do nothing if still outstanding active readers */
+        __ASM_HALF_SIZE(dec) %__ASM_HALF_REG(dx)
         jnz 1f
         save_common_regs
         movq %rax,%rdi
@@ -77,16 +121,15 @@ ENTRY(call_rwsem_wake)
         CFI_ENDPROC
 ENDPROC(call_rwsem_wake)
 
-/* Fix up special calling conventions */
 ENTRY(call_rwsem_downgrade_wake)
         CFI_STARTPROC
         save_common_regs
-        pushq_cfi %rdx
-        CFI_REL_OFFSET rdx, 0
+        __ASM_SIZE(push,_cfi) %__ASM_REG(dx)
+        CFI_REL_OFFSET __ASM_REG(dx), 0
         movq %rax,%rdi
         call rwsem_downgrade_wake
-        popq_cfi %rdx
-        CFI_RESTORE rdx
+        __ASM_SIZE(pop,_cfi) %__ASM_REG(dx)
+        CFI_RESTORE __ASM_REG(dx)
         restore_common_regs
         ret
         CFI_ENDPROC
diff --git a/arch/x86/lib/semaphore_32.S b/arch/x86/lib/semaphore_32.S
deleted file mode 100644
index 06691daa4108..000000000000
--- a/arch/x86/lib/semaphore_32.S
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * i386 semaphore implementation.
- *
- * (C) Copyright 1999 Linus Torvalds
- *
- * Portions Copyright 1999 Red Hat, Inc.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- *
- * rw semaphores implemented November 1999 by Benjamin LaHaise <bcrl@kvack.org>
- */
-
-#include <linux/linkage.h>
-#include <asm/rwlock.h>
-#include <asm/alternative-asm.h>
-#include <asm/frame.h>
-#include <asm/dwarf2.h>
-
-/*
- * The semaphore operations have a special calling sequence that
- * allow us to do a simpler in-line version of them. These routines
- * need to convert that sequence back into the C sequence when
- * there is contention on the semaphore.
- *
- * %eax contains the semaphore pointer on entry. Save the C-clobbered
- * registers (%eax, %edx and %ecx) except %eax whish is either a return
- * value or just clobbered..
- */
-        .section .sched.text, "ax"
-
-/*
- * rw spinlock fallbacks
- */
-#ifdef CONFIG_SMP
-ENTRY(__write_lock_failed)
-        CFI_STARTPROC
-        FRAME
-2:      LOCK_PREFIX
-        addl    $ RW_LOCK_BIAS,(%eax)
-1:      rep; nop
-        cmpl    $ RW_LOCK_BIAS,(%eax)
-        jne     1b
-        LOCK_PREFIX
-        subl    $ RW_LOCK_BIAS,(%eax)
-        jnz     2b
-        ENDFRAME
-        ret
-        CFI_ENDPROC
-        ENDPROC(__write_lock_failed)
-
-ENTRY(__read_lock_failed)
-        CFI_STARTPROC
-        FRAME
-2:      LOCK_PREFIX
-        incl    (%eax)
-1:      rep; nop
-        cmpl    $1,(%eax)
-        js      1b
-        LOCK_PREFIX
-        decl    (%eax)
-        js      2b
-        ENDFRAME
-        ret
-        CFI_ENDPROC
-        ENDPROC(__read_lock_failed)
-
-#endif
-
-#ifdef CONFIG_RWSEM_XCHGADD_ALGORITHM
-
-/* Fix up special calling conventions */
-ENTRY(call_rwsem_down_read_failed)
-        CFI_STARTPROC
-        pushl_cfi %ecx
-        CFI_REL_OFFSET ecx,0
-        pushl_cfi %edx
-        CFI_REL_OFFSET edx,0
-        call rwsem_down_read_failed
-        popl_cfi %edx
-        popl_cfi %ecx
-        ret
-        CFI_ENDPROC
-        ENDPROC(call_rwsem_down_read_failed)
-
-ENTRY(call_rwsem_down_write_failed)
-        CFI_STARTPROC
-        pushl_cfi %ecx
-        CFI_REL_OFFSET ecx,0
-        calll rwsem_down_write_failed
-        popl_cfi %ecx
-        ret
-        CFI_ENDPROC
-        ENDPROC(call_rwsem_down_write_failed)
-
-ENTRY(call_rwsem_wake)
-        CFI_STARTPROC
-        decw %dx    /* do nothing if still outstanding active readers */
-        jnz 1f
-        pushl_cfi %ecx
-        CFI_REL_OFFSET ecx,0
-        call rwsem_wake
-        popl_cfi %ecx
-1:      ret
-        CFI_ENDPROC
-        ENDPROC(call_rwsem_wake)
-
-/* Fix up special calling conventions */
-ENTRY(call_rwsem_downgrade_wake)
-        CFI_STARTPROC
-        pushl_cfi %ecx
-        CFI_REL_OFFSET ecx,0
-        pushl_cfi %edx
-        CFI_REL_OFFSET edx,0
-        call rwsem_downgrade_wake
-        popl_cfi %edx
-        popl_cfi %ecx
-        ret
-        CFI_ENDPROC
-        ENDPROC(call_rwsem_downgrade_wake)
-
-#endif
diff --git a/arch/x86/lib/thunk_64.S b/arch/x86/lib/thunk_64.S
index 782b082c9ff7..a63efd6bb6a5 100644
--- a/arch/x86/lib/thunk_64.S
+++ b/arch/x86/lib/thunk_64.S
@@ -5,50 +5,41 @@
  * Added trace_hardirqs callers - Copyright 2007 Steven Rostedt, Red Hat, Inc.
  * Subject to the GNU public license, v.2. No warranty of any kind.
  */
+#include <linux/linkage.h>
+#include <asm/dwarf2.h>
+#include <asm/calling.h>
 
-        #include <linux/linkage.h>
-        #include <asm/dwarf2.h>
-        #include <asm/calling.h>                        
-        #include <asm/rwlock.h>
-                
-        /* rdi: arg1 ... normal C conventions. rax is saved/restored. */        
-        .macro thunk name,func
-        .globl \name
-\name:  
-        CFI_STARTPROC
-        SAVE_ARGS
-        call \func
-        jmp  restore
-        CFI_ENDPROC
-        .endm
-
-#ifdef CONFIG_TRACE_IRQFLAGS
-        /* put return address in rdi (arg1) */
-        .macro thunk_ra name,func
+        /* rdi: arg1 ... normal C conventions. rax is saved/restored. */
+        .macro THUNK name, func, put_ret_addr_in_rdi=0
         .globl \name
 \name:
         CFI_STARTPROC
+
+        /* this one pushes 9 elems, the next one would be %rIP */
         SAVE_ARGS
-        /* SAVE_ARGS pushs 9 elements */
-        /* the next element would be the rip */
-        movq 9*8(%rsp), %rdi
+
+        .if \put_ret_addr_in_rdi
+        movq_cfi_restore 9*8, rdi
+        .endif
+
         call \func
         jmp  restore
         CFI_ENDPROC
         .endm
 
-        thunk_ra trace_hardirqs_on_thunk,trace_hardirqs_on_caller
-        thunk_ra trace_hardirqs_off_thunk,trace_hardirqs_off_caller
+#ifdef CONFIG_TRACE_IRQFLAGS
+        THUNK trace_hardirqs_on_thunk,trace_hardirqs_on_caller,1
+        THUNK trace_hardirqs_off_thunk,trace_hardirqs_off_caller,1
 #endif
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
-        thunk lockdep_sys_exit_thunk,lockdep_sys_exit
+        THUNK lockdep_sys_exit_thunk,lockdep_sys_exit
 #endif
-        
+
         /* SAVE_ARGS below is used only for the .cfi directives it contains. */
         CFI_STARTPROC
         SAVE_ARGS
 restore:
         RESTORE_ARGS
-        ret     
+        ret
         CFI_ENDPROC
diff --git a/arch/x86/lib/usercopy.c b/arch/x86/lib/usercopy.c
new file mode 100644
index 000000000000..97be9cb54483
--- /dev/null
+++ b/arch/x86/lib/usercopy.c
@@ -0,0 +1,43 @@
+/*
+ * User address space access functions.
+ *
+ *  For licencing details see kernel-base/COPYING
+ */
+
+#include <linux/highmem.h>
+#include <linux/module.h>
+
+/*
+ * best effort, GUP based copy_from_user() that is NMI-safe
+ */
+unsigned long
+copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
+{
+        unsigned long offset, addr = (unsigned long)from;
+        unsigned long size, len = 0;
+        struct page *page;
+        void *map;
+        int ret;
+
+        do {
+                ret = __get_user_pages_fast(addr, 1, 0, &page);
+                if (!ret)
+                        break;
+
+                offset = addr & (PAGE_SIZE - 1);
+                size = min(PAGE_SIZE - offset, n - len);
+
+                map = kmap_atomic(page);
+                memcpy(to, map+offset, size);
+                kunmap_atomic(map);
+                put_page(page);
+
+                len  += size;
+                to   += size;
+                addr += size;
+
+        } while (len < n);
+
+        return len;
+}
+EXPORT_SYMBOL_GPL(copy_from_user_nmi);
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 2dbf6bf4c7e5..4d09df054e39 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -1059,7 +1059,7 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code)
         if (unlikely(error_code & PF_RSVD))
                 pgtable_bad(regs, error_code, address);
 
-        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
 
         /*
          * If we're in an interrupt, have no user context or are running
@@ -1161,11 +1161,11 @@ good_area:
         if (flags & FAULT_FLAG_ALLOW_RETRY) {
                 if (fault & VM_FAULT_MAJOR) {
                         tsk->maj_flt++;
-                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
                                       regs, address);
                 } else {
                         tsk->min_flt++;
-                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
                                       regs, address);
                 }
                 if (fault & VM_FAULT_RETRY) {
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index d865c4aeec55..bbaaa005bf0e 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -28,6 +28,7 @@
 #include <linux/poison.h>
 #include <linux/dma-mapping.h>
 #include <linux/module.h>
+#include <linux/memory.h>
 #include <linux/memory_hotplug.h>
 #include <linux/nmi.h>
 #include <linux/gfp.h>
@@ -895,8 +896,6 @@ const char *arch_vma_name(struct vm_area_struct *vma)
 }
 
 #ifdef CONFIG_X86_UV
-#define MIN_MEMORY_BLOCK_SIZE   (1 << SECTION_SIZE_BITS)
-
 unsigned long memory_block_size_bytes(void)
 {
         if (is_uv_system()) {
diff --git a/arch/x86/mm/kmemcheck/error.c b/arch/x86/mm/kmemcheck/error.c
index 704a37cedddb..dab41876cdd5 100644
--- a/arch/x86/mm/kmemcheck/error.c
+++ b/arch/x86/mm/kmemcheck/error.c
@@ -185,7 +185,7 @@ void kmemcheck_error_save(enum kmemcheck_shadow state,
         e->trace.entries = e->trace_entries;
         e->trace.max_entries = ARRAY_SIZE(e->trace_entries);
         e->trace.skip = 0;
-        save_stack_trace_regs(&e->trace, regs);
+        save_stack_trace_regs(regs, &e->trace);
 
         /* Round address down to nearest 16 bytes */
         shadow_copy = kmemcheck_shadow_lookup(address
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index f5510d889a22..fbeaaf416610 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -496,6 +496,7 @@ static bool __init numa_meminfo_cover_memory(const struct numa_meminfo *mi)
 
 static int __init numa_register_memblks(struct numa_meminfo *mi)
 {
+        unsigned long uninitialized_var(pfn_align);
         int i, nid;
 
         /* Account for nodes with cpus and no memory */
@@ -511,6 +512,20 @@ static int __init numa_register_memblks(struct numa_meminfo *mi)
 
         /* for out of order entries */
         sort_node_map();
+
+        /*
+         * If sections array is gonna be used for pfn -> nid mapping, check
+         * whether its granularity is fine enough.
+         */
+#ifdef NODE_NOT_IN_PAGE_FLAGS
+        pfn_align = node_map_pfn_alignment();
+        if (pfn_align && pfn_align < PAGES_PER_SECTION) {
+                printk(KERN_WARNING "Node alignment %LuMB < min %LuMB, rejecting NUMA config\n",
+                       PFN_PHYS(pfn_align) >> 20,
+                       PFN_PHYS(PAGES_PER_SECTION) >> 20);
+                return -EINVAL;
+        }
+#endif
         if (!numa_meminfo_cover_memory(mi))
                 return -EINVAL;
 
diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c
index 849a975d3fa0..3adebe7e536a 100644
--- a/arch/x86/mm/numa_32.c
+++ b/arch/x86/mm/numa_32.c
@@ -41,7 +41,7 @@
  *     physnode_map[16-31] = 1;
  *     physnode_map[32- ] = -1;
  */
-s8 physnode_map[MAX_ELEMENTS] __read_mostly = { [0 ... (MAX_ELEMENTS - 1)] = -1};
+s8 physnode_map[MAX_SECTIONS] __read_mostly = { [0 ... (MAX_SECTIONS - 1)] = -1};
 EXPORT_SYMBOL(physnode_map);
 
 void memory_present(int nid, unsigned long start, unsigned long end)
@@ -52,8 +52,8 @@ void memory_present(int nid, unsigned long start, unsigned long end)
                         nid, start, end);
         printk(KERN_DEBUG "  Setting physnode_map array to node %d for pfns:\n", nid);
         printk(KERN_DEBUG "  ");
-        for (pfn = start; pfn < end; pfn += PAGES_PER_ELEMENT) {
-                physnode_map[pfn / PAGES_PER_ELEMENT] = nid;
+        for (pfn = start; pfn < end; pfn += PAGES_PER_SECTION) {
+                physnode_map[pfn / PAGES_PER_SECTION] = nid;
                 printk(KERN_CONT "%lx ", pfn);
         }
         printk(KERN_CONT "\n");
diff --git a/arch/x86/mm/pageattr-test.c b/arch/x86/mm/pageattr-test.c
index e1d106909218..b0086567271c 100644
--- a/arch/x86/mm/pageattr-test.c
+++ b/arch/x86/mm/pageattr-test.c
@@ -123,12 +123,11 @@ static int pageattr_test(void)
         if (print)
                 printk(KERN_INFO "CPA self-test:\n");
 
-        bm = vmalloc((max_pfn_mapped + 7) / 8);
+        bm = vzalloc((max_pfn_mapped + 7) / 8);
         if (!bm) {
                 printk(KERN_ERR "CPA Cannot vmalloc bitmap\n");
                 return -ENOMEM;
         }
-        memset(bm, 0, (max_pfn_mapped + 7) / 8);
 
         failed += print_split(&sa);
         srandom32(100);
diff --git a/arch/x86/oprofile/backtrace.c b/arch/x86/oprofile/backtrace.c
index a5b64ab4cd6e..bff89dfe3619 100644
--- a/arch/x86/oprofile/backtrace.c
+++ b/arch/x86/oprofile/backtrace.c
@@ -11,10 +11,11 @@
 #include <linux/oprofile.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/compat.h>
+#include <linux/uaccess.h>
+
 #include <asm/ptrace.h>
-#include <asm/uaccess.h>
 #include <asm/stacktrace.h>
-#include <linux/compat.h>
 
 static int backtrace_stack(void *data, char *name)
 {
@@ -40,13 +41,13 @@ static struct stacktrace_ops backtrace_ops = {
 static struct stack_frame_ia32 *
 dump_user_backtrace_32(struct stack_frame_ia32 *head)
 {
+        /* Also check accessibility of one struct frame_head beyond: */
         struct stack_frame_ia32 bufhead[2];
         struct stack_frame_ia32 *fp;
+        unsigned long bytes;
 
-        /* Also check accessibility of one struct frame_head beyond */
-        if (!access_ok(VERIFY_READ, head, sizeof(bufhead)))
-                return NULL;
-        if (__copy_from_user_inatomic(bufhead, head, sizeof(bufhead)))
+        bytes = copy_from_user_nmi(bufhead, head, sizeof(bufhead));
+        if (bytes != sizeof(bufhead))
                 return NULL;
 
         fp = (struct stack_frame_ia32 *) compat_ptr(bufhead[0].next_frame);
@@ -87,12 +88,12 @@ x86_backtrace_32(struct pt_regs * const regs, unsigned int depth)
 
 static struct stack_frame *dump_user_backtrace(struct stack_frame *head)
 {
+        /* Also check accessibility of one struct frame_head beyond: */
         struct stack_frame bufhead[2];
+        unsigned long bytes;
 
-        /* Also check accessibility of one struct stack_frame beyond */
-        if (!access_ok(VERIFY_READ, head, sizeof(bufhead)))
-                return NULL;
-        if (__copy_from_user_inatomic(bufhead, head, sizeof(bufhead)))
+        bytes = copy_from_user_nmi(bufhead, head, sizeof(bufhead));
+        if (bytes != sizeof(bufhead))
                 return NULL;
 
         oprofile_add_trace(bufhead[0].return_address);
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index cf9750004a08..68894fdc034b 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -112,8 +112,10 @@ static void nmi_cpu_start(void *dummy)
 static int nmi_start(void)
 {
         get_online_cpus();
-        on_each_cpu(nmi_cpu_start, NULL, 1);
         ctr_running = 1;
+        /* make ctr_running visible to the nmi handler: */
+        smp_mb();
+        on_each_cpu(nmi_cpu_start, NULL, 1);
         put_online_cpus();
         return 0;
 }
@@ -504,15 +506,18 @@ static int nmi_setup(void)
 
         nmi_enabled = 0;
         ctr_running = 0;
-        barrier();
+        /* make variables visible to the nmi handler: */
+        smp_mb();
         err = register_die_notifier(&profile_exceptions_nb);
         if (err)
                 goto fail;
 
         get_online_cpus();
         register_cpu_notifier(&oprofile_cpu_nb);
-        on_each_cpu(nmi_cpu_setup, NULL, 1);
         nmi_enabled = 1;
+        /* make nmi_enabled visible to the nmi handler: */
+        smp_mb();
+        on_each_cpu(nmi_cpu_setup, NULL, 1);
         put_online_cpus();
 
         return 0;
@@ -531,7 +536,8 @@ static void nmi_shutdown(void)
         nmi_enabled = 0;
         ctr_running = 0;
         put_online_cpus();
-        barrier();
+        /* make variables visible to the nmi handler: */
+        smp_mb();
         unregister_die_notifier(&profile_exceptions_nb);
         msrs = &get_cpu_var(cpu_msrs);
         model->shutdown(msrs);
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 750c346ef50a..301e325992f6 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -519,7 +519,8 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
         if (cfg->address < 0xFFFFFFFF)
                 return 0;
 
-        if (!strcmp(mcfg->header.oem_id, "SGI"))
+        if (!strcmp(mcfg->header.oem_id, "SGI") ||
+                        !strcmp(mcfg->header.oem_id, "SGI2"))
                 return 0;
 
         if (mcfg->header.revision >= 1) {
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index fe008309ffec..1017c7bee388 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -1,8 +1,13 @@
 /*
- * Xen PCI Frontend Stub - puts some "dummy" functions in to the Linux
- *                         x86 PCI core to support the Xen PCI Frontend
+ * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
+ * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
+ * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
+ * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
+ * 0xcf8 PCI configuration read/write.
  *
  *   Author: Ryan Wilson <hap9@epoch.ncsc.mil>
+ *           Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+ *           Stefano Stabellini <stefano.stabellini@eu.citrix.com>
  */
 #include <linux/module.h>
 #include <linux/init.h>
@@ -19,22 +24,53 @@
 #include <xen/events.h>
 #include <asm/xen/pci.h>
 
+static int xen_pcifront_enable_irq(struct pci_dev *dev)
+{
+        int rc;
+        int share = 1;
+        int pirq;
+        u8 gsi;
+
+        rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
+        if (rc < 0) {
+                dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
+                         rc);
+                return rc;
+        }
+        /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
+        pirq = gsi;
+
+        if (gsi < NR_IRQS_LEGACY)
+                share = 0;
+
+        rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
+        if (rc < 0) {
+                dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
+                         gsi, pirq, rc);
+                return rc;
+        }
+
+        dev->irq = rc;
+        dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
+        return 0;
+}
+
 #ifdef CONFIG_ACPI
-static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
-                                 int trigger, int polarity)
+static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,
+                             bool set_pirq)
 {
-        int rc, irq;
+        int rc, pirq = -1, irq = -1;
         struct physdev_map_pirq map_irq;
         int shareable = 0;
         char *name;
 
-        if (!xen_hvm_domain())
-                return -1;
+        if (set_pirq)
+                pirq = gsi;
 
         map_irq.domid = DOMID_SELF;
         map_irq.type = MAP_PIRQ_TYPE_GSI;
         map_irq.index = gsi;
-        map_irq.pirq = -1;
+        map_irq.pirq = pirq;
 
         rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
         if (rc) {
@@ -42,7 +78,7 @@ static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
                 return -1;
         }
 
-        if (trigger == ACPI_EDGE_SENSITIVE) {
+        if (triggering == ACPI_EDGE_SENSITIVE) {
                 shareable = 0;
                 name = "ioapic-edge";
         } else {
@@ -50,12 +86,63 @@ static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
                 name = "ioapic-level";
         }
 
+        if (gsi_override >= 0)
+                gsi = gsi_override;
+
         irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
+        if (irq < 0)
+                goto out;
 
-        printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
+        printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
+out:
+        return irq;
+}
+
+static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
+                                     int trigger, int polarity)
+{
+        if (!xen_hvm_domain())
+                return -1;
+
+        return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,
+                                 false /* no mapping of GSI to PIRQ */);
+}
+
+#ifdef CONFIG_XEN_DOM0
+static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)
+{
+        int rc, irq;
+        struct physdev_setup_gsi setup_gsi;
+
+        if (!xen_pv_domain())
+                return -1;
+
+        printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
+                        gsi, triggering, polarity);
+
+        irq = xen_register_pirq(gsi, gsi_override, triggering, true);
+
+        setup_gsi.gsi = gsi;
+        setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
+        setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
+
+        rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
+        if (rc == -EEXIST)
+                printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
+        else if (rc) {
+                printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
+                                gsi, rc);
+        }
 
         return irq;
 }
+
+static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
+                                 int trigger, int polarity)
+{
+        return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);
+}
+#endif
 #endif
 
 #if defined(CONFIG_PCI_MSI)
@@ -65,6 +152,43 @@ static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
 struct xen_pci_frontend_ops *xen_pci_frontend;
 EXPORT_SYMBOL_GPL(xen_pci_frontend);
 
+static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        int irq, ret, i;
+        struct msi_desc *msidesc;
+        int *v;
+
+        v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
+        if (!v)
+                return -ENOMEM;
+
+        if (type == PCI_CAP_ID_MSIX)
+                ret = xen_pci_frontend_enable_msix(dev, v, nvec);
+        else
+                ret = xen_pci_frontend_enable_msi(dev, v);
+        if (ret)
+                goto error;
+        i = 0;
+        list_for_each_entry(msidesc, &dev->msi_list, list) {
+                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i], 0,
+                                               (type == PCI_CAP_ID_MSIX) ?
+                                               "pcifront-msi-x" :
+                                               "pcifront-msi",
+                                                DOMID_SELF);
+                if (irq < 0)
+                        goto free;
+                i++;
+        }
+        kfree(v);
+        return 0;
+
+error:
+        dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
+free:
+        kfree(v);
+        return ret;
+}
+
 #define XEN_PIRQ_MSI_DATA  (MSI_DATA_TRIGGER_EDGE | \
                 MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0))
 
@@ -123,67 +247,6 @@ error:
         return -ENODEV;
 }
 
-/*
- * For MSI interrupts we have to use drivers/xen/event.s functions to
- * allocate an irq_desc and setup the right */
-
-
-static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
-{
-        int irq, ret, i;
-        struct msi_desc *msidesc;
-        int *v;
-
-        v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
-        if (!v)
-                return -ENOMEM;
-
-        if (type == PCI_CAP_ID_MSIX)
-                ret = xen_pci_frontend_enable_msix(dev, v, nvec);
-        else
-                ret = xen_pci_frontend_enable_msi(dev, v);
-        if (ret)
-                goto error;
-        i = 0;
-        list_for_each_entry(msidesc, &dev->msi_list, list) {
-                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i], 0,
-                                               (type == PCI_CAP_ID_MSIX) ?
-                                               "pcifront-msi-x" :
-                                               "pcifront-msi",
-                                                DOMID_SELF);
-                if (irq < 0)
-                        goto free;
-                i++;
-        }
-        kfree(v);
-        return 0;
-
-error:
-        dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
-free:
-        kfree(v);
-        return ret;
-}
-
-static void xen_teardown_msi_irqs(struct pci_dev *dev)
-{
-        struct msi_desc *msidesc;
-
-        msidesc = list_entry(dev->msi_list.next, struct msi_desc, list);
-        if (msidesc->msi_attrib.is_msix)
-                xen_pci_frontend_disable_msix(dev);
-        else
-                xen_pci_frontend_disable_msi(dev);
-
-        /* Free the IRQ's and the msidesc using the generic code. */
-        default_teardown_msi_irqs(dev);
-}
-
-static void xen_teardown_msi_irq(unsigned int irq)
-{
-        xen_destroy_irq(irq);
-}
-
 #ifdef CONFIG_XEN_DOM0
 static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 {
@@ -242,45 +305,28 @@ out:
         return ret;
 }
 #endif
-#endif
 
-static int xen_pcifront_enable_irq(struct pci_dev *dev)
+static void xen_teardown_msi_irqs(struct pci_dev *dev)
 {
-        int rc;
-        int share = 1;
-        int pirq;
-        u8 gsi;
-
-        rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
-        if (rc < 0) {
-                dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
-                         rc);
-                return rc;
-        }
-
-        rc = xen_allocate_pirq_gsi(gsi);
-        if (rc < 0) {
-                dev_warn(&dev->dev, "Xen PCI: failed to allocate a PIRQ for GSI%d: %d\n",
-                         gsi, rc);
-                return rc;
-        }
-        pirq = rc;
+        struct msi_desc *msidesc;
 
-        if (gsi < NR_IRQS_LEGACY)
-                share = 0;
+        msidesc = list_entry(dev->msi_list.next, struct msi_desc, list);
+        if (msidesc->msi_attrib.is_msix)
+                xen_pci_frontend_disable_msix(dev);
+        else
+                xen_pci_frontend_disable_msi(dev);
 
-        rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
-        if (rc < 0) {
-                dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
-                         gsi, pirq, rc);
-                return rc;
-        }
+        /* Free the IRQ's and the msidesc using the generic code. */
+        default_teardown_msi_irqs(dev);
+}
 
-        dev->irq = rc;
-        dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
-        return 0;
+static void xen_teardown_msi_irq(unsigned int irq)
+{
+        xen_destroy_irq(irq);
 }
 
+#endif
+
 int __init pci_xen_init(void)
 {
         if (!xen_pv_domain() || xen_initial_domain())
@@ -327,104 +373,13 @@ int __init pci_xen_hvm_init(void)
 }
 
 #ifdef CONFIG_XEN_DOM0
-static int xen_register_pirq(u32 gsi, int triggering)
-{
-        int rc, pirq, irq = -1;
-        struct physdev_map_pirq map_irq;
-        int shareable = 0;
-        char *name;
-        bool gsi_override = false;
-
-        if (!xen_pv_domain())
-                return -1;
-
-        if (triggering == ACPI_EDGE_SENSITIVE) {
-                shareable = 0;
-                name = "ioapic-edge";
-        } else {
-                shareable = 1;
-                name = "ioapic-level";
-        }
-
-        pirq = xen_allocate_pirq_gsi(gsi);
-        if (pirq < 0)
-                goto out;
-
-        /* Before we bind the GSI to a Linux IRQ, check whether
-         * we need to override it with bus_irq (IRQ) value. Usually for
-         * IRQs below IRQ_LEGACY_IRQ this holds IRQ == GSI, as so:
-         *  ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
-         * but there are oddballs where the IRQ != GSI:
-         *  ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 20 low level)
-         * which ends up being: gsi_to_irq[9] == 20
-         * (which is what acpi_gsi_to_irq ends up calling when starting the
-         * the ACPI interpreter and keels over since IRQ 9 has not been
-         * setup as we had setup IRQ 20 for it).
-         */
-        if (gsi == acpi_sci_override_gsi) {
-                /* Check whether the GSI != IRQ */
-                acpi_gsi_to_irq(gsi, &irq);
-                if (irq != gsi)
-                        /* Bugger, we MUST have that IRQ. */
-                        gsi_override = true;
-        }
-        if (gsi_override)
-                irq = xen_bind_pirq_gsi_to_irq(irq, pirq, shareable, name);
-        else
-                irq = xen_bind_pirq_gsi_to_irq(gsi, pirq, shareable, name);
-        if (irq < 0)
-                goto out;
-
-        printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", pirq, irq, gsi);
-
-        map_irq.domid = DOMID_SELF;
-        map_irq.type = MAP_PIRQ_TYPE_GSI;
-        map_irq.index = gsi;
-        map_irq.pirq = pirq;
-
-        rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
-        if (rc) {
-                printk(KERN_WARNING "xen map irq failed %d\n", rc);
-                return -1;
-        }
-
-out:
-        return irq;
-}
-
-static int xen_register_gsi(u32 gsi, int triggering, int polarity)
-{
-        int rc, irq;
-        struct physdev_setup_gsi setup_gsi;
-
-        if (!xen_pv_domain())
-                return -1;
-
-        printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
-                        gsi, triggering, polarity);
-
-        irq = xen_register_pirq(gsi, triggering);
-
-        setup_gsi.gsi = gsi;
-        setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
-        setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
-
-        rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
-        if (rc == -EEXIST)
-                printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
-        else if (rc) {
-                printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
-                                gsi, rc);
-        }
-
-        return irq;
-}
-
 static __init void xen_setup_acpi_sci(void)
 {
         int rc;
         int trigger, polarity;
         int gsi = acpi_sci_override_gsi;
+        int irq = -1;
+        int gsi_override = -1;
 
         if (!gsi)
                 return;
@@ -437,51 +392,43 @@ static __init void xen_setup_acpi_sci(void)
         }
         trigger = trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
         polarity = polarity ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
-        
+
         printk(KERN_INFO "xen: sci override: global_irq=%d trigger=%d "
                         "polarity=%d\n", gsi, trigger, polarity);
 
-        gsi = xen_register_gsi(gsi, trigger, polarity);
+        /* Before we bind the GSI to a Linux IRQ, check whether
+         * we need to override it with bus_irq (IRQ) value. Usually for
+         * IRQs below IRQ_LEGACY_IRQ this holds IRQ == GSI, as so:
+         *  ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
+         * but there are oddballs where the IRQ != GSI:
+         *  ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 20 low level)
+         * which ends up being: gsi_to_irq[9] == 20
+         * (which is what acpi_gsi_to_irq ends up calling when starting the
+         * the ACPI interpreter and keels over since IRQ 9 has not been
+         * setup as we had setup IRQ 20 for it).
+         */
+        if (acpi_gsi_to_irq(gsi, &irq) == 0) {
+                /* Use the provided value if it's valid. */
+                if (irq >= 0)
+                        gsi_override = irq;
+        }
+
+        gsi = xen_register_gsi(gsi, gsi_override, trigger, polarity);
         printk(KERN_INFO "xen: acpi sci %d\n", gsi);
 
         return;
 }
 
-static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
-                                 int trigger, int polarity)
+int __init pci_xen_initial_domain(void)
 {
-        return xen_register_gsi(gsi, trigger, polarity);
-}
+        int irq;
 
-static int __init pci_xen_initial_domain(void)
-{
 #ifdef CONFIG_PCI_MSI
         x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
         x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
 #endif
         xen_setup_acpi_sci();
         __acpi_register_gsi = acpi_register_gsi_xen;
-
-        return 0;
-}
-
-void __init xen_setup_pirqs(void)
-{
-        int pirq, irq;
-
-        pci_xen_initial_domain();
-
-        if (0 == nr_ioapics) {
-                for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
-                        pirq = xen_allocate_pirq_gsi(irq);
-                        if (WARN(pirq < 0,
-                                 "Could not allocate PIRQ for legacy interrupt\n"))
-                                break;
-                        irq = xen_bind_pirq_gsi_to_irq(irq, pirq, 0, "xt-pic");
-                }
-                return;
-        }
-
         /* Pre-allocate legacy irqs */
         for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
                 int trigger, polarity;
@@ -489,13 +436,17 @@ void __init xen_setup_pirqs(void)
                 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
                         continue;
 
-                xen_register_pirq(irq,
-                        trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE);
+                xen_register_pirq(irq, -1 /* no GSI override */,
+                        trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
+                        true /* Map GSI to PIRQ */);
         }
+        if (0 == nr_ioapics) {
+                for (irq = 0; irq < NR_IRQS_LEGACY; irq++)
+                        xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
+        }
+        return 0;
 }
-#endif
 
-#ifdef CONFIG_XEN_DOM0
 struct xen_device_domain_owner {
         domid_t domain;
         struct pci_dev *dev;
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 474356b98ede..3ae4128013e6 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -51,7 +51,17 @@
 int efi_enabled;
 EXPORT_SYMBOL(efi_enabled);
 
-struct efi efi;
+struct efi __read_mostly efi = {
+        .mps        = EFI_INVALID_TABLE_ADDR,
+        .acpi       = EFI_INVALID_TABLE_ADDR,
+        .acpi20     = EFI_INVALID_TABLE_ADDR,
+        .smbios     = EFI_INVALID_TABLE_ADDR,
+        .sal_systab = EFI_INVALID_TABLE_ADDR,
+        .boot_info  = EFI_INVALID_TABLE_ADDR,
+        .hcdp       = EFI_INVALID_TABLE_ADDR,
+        .uga        = EFI_INVALID_TABLE_ADDR,
+        .uv_systab  = EFI_INVALID_TABLE_ADDR,
+};
 EXPORT_SYMBOL(efi);
 
 struct efi_memory_map memmap;
@@ -79,26 +89,50 @@ early_param("add_efi_memmap", setup_add_efi_memmap);
 
 static efi_status_t virt_efi_get_time(efi_time_t *tm, efi_time_cap_t *tc)
 {
-        return efi_call_virt2(get_time, tm, tc);
+        unsigned long flags;
+        efi_status_t status;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        status = efi_call_virt2(get_time, tm, tc);
+        spin_unlock_irqrestore(&rtc_lock, flags);
+        return status;
 }
 
 static efi_status_t virt_efi_set_time(efi_time_t *tm)
 {
-        return efi_call_virt1(set_time, tm);
+        unsigned long flags;
+        efi_status_t status;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        status = efi_call_virt1(set_time, tm);
+        spin_unlock_irqrestore(&rtc_lock, flags);
+        return status;
 }
 
 static efi_status_t virt_efi_get_wakeup_time(efi_bool_t *enabled,
                                              efi_bool_t *pending,
                                              efi_time_t *tm)
 {
-        return efi_call_virt3(get_wakeup_time,
-                              enabled, pending, tm);
+        unsigned long flags;
+        efi_status_t status;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        status = efi_call_virt3(get_wakeup_time,
+                                enabled, pending, tm);
+        spin_unlock_irqrestore(&rtc_lock, flags);
+        return status;
 }
 
 static efi_status_t virt_efi_set_wakeup_time(efi_bool_t enabled, efi_time_t *tm)
 {
-        return efi_call_virt2(set_wakeup_time,
-                              enabled, tm);
+        unsigned long flags;
+        efi_status_t status;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        status = efi_call_virt2(set_wakeup_time,
+                                enabled, tm);
+        spin_unlock_irqrestore(&rtc_lock, flags);
+        return status;
 }
 
 static efi_status_t virt_efi_get_variable(efi_char16_t *name,
@@ -122,7 +156,7 @@ static efi_status_t virt_efi_get_next_variable(unsigned long *name_size,
 
 static efi_status_t virt_efi_set_variable(efi_char16_t *name,
                                           efi_guid_t *vendor,
-                                          unsigned long attr,
+                                          u32 attr,
                                           unsigned long data_size,
                                           void *data)
 {
@@ -131,6 +165,18 @@ static efi_status_t virt_efi_set_variable(efi_char16_t *name,
                               data_size, data);
 }
 
+static efi_status_t virt_efi_query_variable_info(u32 attr,
+                                                 u64 *storage_space,
+                                                 u64 *remaining_space,
+                                                 u64 *max_variable_size)
+{
+        if (efi.runtime_version < EFI_2_00_SYSTEM_TABLE_REVISION)
+                return EFI_UNSUPPORTED;
+
+        return efi_call_virt4(query_variable_info, attr, storage_space,
+                              remaining_space, max_variable_size);
+}
+
 static efi_status_t virt_efi_get_next_high_mono_count(u32 *count)
 {
         return efi_call_virt1(get_next_high_mono_count, count);
@@ -145,6 +191,28 @@ static void virt_efi_reset_system(int reset_type,
                        data_size, data);
 }
 
+static efi_status_t virt_efi_update_capsule(efi_capsule_header_t **capsules,
+                                            unsigned long count,
+                                            unsigned long sg_list)
+{
+        if (efi.runtime_version < EFI_2_00_SYSTEM_TABLE_REVISION)
+                return EFI_UNSUPPORTED;
+
+        return efi_call_virt3(update_capsule, capsules, count, sg_list);
+}
+
+static efi_status_t virt_efi_query_capsule_caps(efi_capsule_header_t **capsules,
+                                                unsigned long count,
+                                                u64 *max_size,
+                                                int *reset_type)
+{
+        if (efi.runtime_version < EFI_2_00_SYSTEM_TABLE_REVISION)
+                return EFI_UNSUPPORTED;
+
+        return efi_call_virt4(query_capsule_caps, capsules, count, max_size,
+                              reset_type);
+}
+
 static efi_status_t __init phys_efi_set_virtual_address_map(
         unsigned long memory_map_size,
         unsigned long descriptor_size,
@@ -164,11 +232,14 @@ static efi_status_t __init phys_efi_set_virtual_address_map(
 static efi_status_t __init phys_efi_get_time(efi_time_t *tm,
                                              efi_time_cap_t *tc)
 {
+        unsigned long flags;
         efi_status_t status;
 
+        spin_lock_irqsave(&rtc_lock, flags);
         efi_call_phys_prelog();
         status = efi_call_phys2(efi_phys.get_time, tm, tc);
         efi_call_phys_epilog();
+        spin_unlock_irqrestore(&rtc_lock, flags);
         return status;
 }
 
@@ -504,9 +575,6 @@ void __init efi_init(void)
         x86_platform.set_wallclock = efi_set_rtc_mmss;
 #endif
 
-        /* Setup for EFI runtime service */
-        reboot_type = BOOT_EFI;
-
 #if EFI_DEBUG
         print_efi_memmap();
 #endif
@@ -672,6 +740,9 @@ void __init efi_enter_virtual_mode(void)
         efi.get_next_high_mono_count = virt_efi_get_next_high_mono_count;
         efi.reset_system = virt_efi_reset_system;
         efi.set_virtual_address_map = NULL;
+        efi.query_variable_info = virt_efi_query_variable_info;
+        efi.update_capsule = virt_efi_update_capsule;
+        efi.query_capsule_caps = virt_efi_query_capsule_caps;
         if (__supported_pte_mask & _PAGE_NX)
                 runtime_code_page_mkexec();
         early_iounmap(memmap.map, memmap.nr_map * memmap.desc_size);
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 68e467f69fec..db8b915f54bc 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -296,14 +296,18 @@ static void bau_process_message(struct msg_desc *mdp,
 }
 
 /*
- * Determine the first cpu on a uvhub.
+ * Determine the first cpu on a pnode.
  */
-static int uvhub_to_first_cpu(int uvhub)
+static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
 {
         int cpu;
-        for_each_present_cpu(cpu)
-                if (uvhub == uv_cpu_to_blade_id(cpu))
+        struct hub_and_pnode *hpp;
+
+        for_each_present_cpu(cpu) {
+                hpp = &smaster->thp[cpu];
+                if (pnode == hpp->pnode)
                         return cpu;
+        }
         return -1;
 }
 
@@ -366,28 +370,32 @@ static void do_reset(void *ptr)
  * Use IPI to get all target uvhubs to release resources held by
  * a given sending cpu number.
  */
-static void reset_with_ipi(struct bau_targ_hubmask *distribution, int sender)
+static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
 {
-        int uvhub;
+        int pnode;
+        int apnode;
         int maskbits;
-        cpumask_t mask;
+        int sender = bcp->cpu;
+        cpumask_t *mask = bcp->uvhub_master->cpumask;
+        struct bau_control *smaster = bcp->socket_master;
         struct reset_args reset_args;
 
         reset_args.sender = sender;
-        cpus_clear(mask);
+        cpus_clear(*mask);
         /* find a single cpu for each uvhub in this distribution mask */
-        maskbits = sizeof(struct bau_targ_hubmask) * BITSPERBYTE;
-        for (uvhub = 0; uvhub < maskbits; uvhub++) {
+        maskbits = sizeof(struct pnmask) * BITSPERBYTE;
+        /* each bit is a pnode relative to the partition base pnode */
+        for (pnode = 0; pnode < maskbits; pnode++) {
                 int cpu;
-                if (!bau_uvhub_isset(uvhub, distribution))
+                if (!bau_uvhub_isset(pnode, distribution))
                         continue;
-                /* find a cpu for this uvhub */
-                cpu = uvhub_to_first_cpu(uvhub);
-                cpu_set(cpu, mask);
+                apnode = pnode + bcp->partition_base_pnode;
+                cpu = pnode_to_first_cpu(apnode, smaster);
+                cpu_set(cpu, *mask);
         }
 
         /* IPI all cpus; preemption is already disabled */
-        smp_call_function_many(&mask, do_reset, (void *)&reset_args, 1);
+        smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
         return;
 }
 
@@ -604,7 +612,7 @@ static void destination_plugged(struct bau_desc *bau_desc,
                 quiesce_local_uvhub(hmaster);
 
                 spin_lock(&hmaster->queue_lock);
-                reset_with_ipi(&bau_desc->distribution, bcp->cpu);
+                reset_with_ipi(&bau_desc->distribution, bcp);
                 spin_unlock(&hmaster->queue_lock);
 
                 end_uvhub_quiesce(hmaster);
@@ -626,7 +634,7 @@ static void destination_timeout(struct bau_desc *bau_desc,
                 quiesce_local_uvhub(hmaster);
 
                 spin_lock(&hmaster->queue_lock);
-                reset_with_ipi(&bau_desc->distribution, bcp->cpu);
+                reset_with_ipi(&bau_desc->distribution, bcp);
                 spin_unlock(&hmaster->queue_lock);
 
                 end_uvhub_quiesce(hmaster);
@@ -1334,9 +1342,10 @@ static ssize_t tunables_write(struct file *file, const char __user *user,
 
         instr[count] = '\0';
 
-        bcp = &per_cpu(bau_control, smp_processor_id());
-
+        cpu = get_cpu();
+        bcp = &per_cpu(bau_control, cpu);
         ret = parse_tunables_write(bcp, instr, count);
+        put_cpu();
         if (ret)
                 return ret;
 
@@ -1687,6 +1696,16 @@ static void make_per_cpu_thp(struct bau_control *smaster)
 }
 
 /*
+ * Each uvhub is to get a local cpumask.
+ */
+static void make_per_hub_cpumask(struct bau_control *hmaster)
+{
+        int sz = sizeof(cpumask_t);
+
+        hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
+}
+
+/*
  * Initialize all the per_cpu information for the cpu's on a given socket,
  * given what has been gathered into the socket_desc struct.
  * And reports the chosen hub and socket masters back to the caller.
@@ -1751,11 +1770,12 @@ static int __init summarize_uvhub_sockets(int nuvhubs,
                                 sdp = &bdp->socket[socket];
                                 if (scan_sock(sdp, bdp, &smaster, &hmaster))
                                         return 1;
+                                make_per_cpu_thp(smaster);
                         }
                         socket++;
                         socket_mask = (socket_mask >> 1);
-                        make_per_cpu_thp(smaster);
                 }
+                make_per_hub_cpumask(hmaster);
         }
         return 0;
 }
@@ -1777,15 +1797,20 @@ static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
         uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
 
         if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
-                return 1;
+                goto fail;
 
         if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
-                return 1;
+                goto fail;
 
         kfree(uvhub_descs);
         kfree(uvhub_mask);
         init_per_cpu_tunables();
         return 0;
+
+fail:
+        kfree(uvhub_descs);
+        kfree(uvhub_mask);
+        return 1;
 }
 
 /*
diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile
index bef0bc962400..5d179502a52c 100644
--- a/arch/x86/vdso/Makefile
+++ b/arch/x86/vdso/Makefile
@@ -26,6 +26,7 @@ targets += vdso.so vdso.so.dbg vdso.lds $(vobjs-y)
 export CPPFLAGS_vdso.lds += -P -C
 
 VDSO_LDFLAGS_vdso.lds = -m64 -Wl,-soname=linux-vdso.so.1 \
+                        -Wl,--no-undefined \
                         -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096
 
 $(obj)/vdso.o: $(src)/vdso.S $(obj)/vdso.so
diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c
index a724905fdae7..6bc0e723b6e8 100644
--- a/arch/x86/vdso/vclock_gettime.c
+++ b/arch/x86/vdso/vclock_gettime.c
@@ -6,7 +6,6 @@
  *
  * The code should have no internal unresolved relocations.
  * Check with readelf after changing.
- * Also alternative() doesn't work.
  */
 
 /* Disable profiling for userspace code: */
@@ -17,6 +16,7 @@
 #include <linux/time.h>
 #include <linux/string.h>
 #include <asm/vsyscall.h>
+#include <asm/fixmap.h>
 #include <asm/vgtod.h>
 #include <asm/timex.h>
 #include <asm/hpet.h>
@@ -25,6 +25,43 @@
 
 #define gtod (&VVAR(vsyscall_gtod_data))
 
+notrace static cycle_t vread_tsc(void)
+{
+        cycle_t ret;
+        u64 last;
+
+        /*
+         * Empirically, a fence (of type that depends on the CPU)
+         * before rdtsc is enough to ensure that rdtsc is ordered
+         * with respect to loads.  The various CPU manuals are unclear
+         * as to whether rdtsc can be reordered with later loads,
+         * but no one has ever seen it happen.
+         */
+        rdtsc_barrier();
+        ret = (cycle_t)vget_cycles();
+
+        last = VVAR(vsyscall_gtod_data).clock.cycle_last;
+
+        if (likely(ret >= last))
+                return ret;
+
+        /*
+         * GCC likes to generate cmov here, but this branch is extremely
+         * predictable (it's just a funciton of time and the likely is
+         * very likely) and there's a data dependence, so force GCC
+         * to generate a branch instead.  I don't barrier() because
+         * we don't actually need a barrier, and if this function
+         * ever gets inlined it will generate worse code.
+         */
+        asm volatile ("");
+        return last;
+}
+
+static notrace cycle_t vread_hpet(void)
+{
+        return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
+}
+
 notrace static long vdso_fallback_gettime(long clock, struct timespec *ts)
 {
         long ret;
@@ -36,9 +73,12 @@ notrace static long vdso_fallback_gettime(long clock, struct timespec *ts)
 notrace static inline long vgetns(void)
 {
         long v;
-        cycles_t (*vread)(void);
-        vread = gtod->clock.vread;
-        v = (vread() - gtod->clock.cycle_last) & gtod->clock.mask;
+        cycles_t cycles;
+        if (gtod->clock.vclock_mode == VCLOCK_TSC)
+                cycles = vread_tsc();
+        else
+                cycles = vread_hpet();
+        v = (cycles - gtod->clock.cycle_last) & gtod->clock.mask;
         return (v * gtod->clock.mult) >> gtod->clock.shift;
 }
 
@@ -116,21 +156,21 @@ notrace static noinline int do_monotonic_coarse(struct timespec *ts)
 
 notrace int __vdso_clock_gettime(clockid_t clock, struct timespec *ts)
 {
-        if (likely(gtod->sysctl_enabled))
-                switch (clock) {
-                case CLOCK_REALTIME:
-                        if (likely(gtod->clock.vread))
-                                return do_realtime(ts);
-                        break;
-                case CLOCK_MONOTONIC:
-                        if (likely(gtod->clock.vread))
-                                return do_monotonic(ts);
-                        break;
-                case CLOCK_REALTIME_COARSE:
-                        return do_realtime_coarse(ts);
-                case CLOCK_MONOTONIC_COARSE:
-                        return do_monotonic_coarse(ts);
-                }
+        switch (clock) {
+        case CLOCK_REALTIME:
+                if (likely(gtod->clock.vclock_mode != VCLOCK_NONE))
+                        return do_realtime(ts);
+                break;
+        case CLOCK_MONOTONIC:
+                if (likely(gtod->clock.vclock_mode != VCLOCK_NONE))
+                        return do_monotonic(ts);
+                break;
+        case CLOCK_REALTIME_COARSE:
+                return do_realtime_coarse(ts);
+        case CLOCK_MONOTONIC_COARSE:
+                return do_monotonic_coarse(ts);
+        }
+
         return vdso_fallback_gettime(clock, ts);
 }
 int clock_gettime(clockid_t, struct timespec *)
@@ -139,7 +179,7 @@ int clock_gettime(clockid_t, struct timespec *)
 notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
 {
         long ret;
-        if (likely(gtod->sysctl_enabled && gtod->clock.vread)) {
+        if (likely(gtod->clock.vclock_mode != VCLOCK_NONE)) {
                 if (likely(tv != NULL)) {
                         BUILD_BUG_ON(offsetof(struct timeval, tv_usec) !=
                                      offsetof(struct timespec, tv_nsec) ||
@@ -161,27 +201,14 @@ notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
 int gettimeofday(struct timeval *, struct timezone *)
         __attribute__((weak, alias("__vdso_gettimeofday")));
 
-/* This will break when the xtime seconds get inaccurate, but that is
- * unlikely */
-
-static __always_inline long time_syscall(long *t)
-{
-        long secs;
-        asm volatile("syscall"
-                     : "=a" (secs)
-                     : "0" (__NR_time), "D" (t) : "cc", "r11", "cx", "memory");
-        return secs;
-}
-
+/*
+ * This will break when the xtime seconds get inaccurate, but that is
+ * unlikely
+ */
 notrace time_t __vdso_time(time_t *t)
 {
-        time_t result;
-
-        if (unlikely(!VVAR(vsyscall_gtod_data).sysctl_enabled))
-                return time_syscall(t);
-
         /* This is atomic on x86_64 so we don't need any locks. */
-        result = ACCESS_ONCE(VVAR(vsyscall_gtod_data).wall_time_sec);
+        time_t result = ACCESS_ONCE(VVAR(vsyscall_gtod_data).wall_time_sec);
 
         if (t)
                 *t = result;
diff --git a/arch/x86/vdso/vdso.S b/arch/x86/vdso/vdso.S
index 1d3aa6b87181..1b979c12ba85 100644
--- a/arch/x86/vdso/vdso.S
+++ b/arch/x86/vdso/vdso.S
@@ -1,10 +1,21 @@
+#include <asm/page_types.h>
+#include <linux/linkage.h>
 #include <linux/init.h>
 
-__INITDATA
+__PAGE_ALIGNED_DATA
 
         .globl vdso_start, vdso_end
+        .align PAGE_SIZE
 vdso_start:
         .incbin "arch/x86/vdso/vdso.so"
 vdso_end:
 
-__FINIT
+.previous
+
+        .globl vdso_pages
+        .bss
+        .align 8
+        .type vdso_pages, @object
+vdso_pages:
+        .zero (vdso_end - vdso_start + PAGE_SIZE - 1) / PAGE_SIZE * 8
+        .size vdso_pages, .-vdso_pages
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index 7abd2be0f9b9..316fbca3490e 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -14,41 +14,61 @@
 #include <asm/vgtod.h>
 #include <asm/proto.h>
 #include <asm/vdso.h>
+#include <asm/page.h>
 
 unsigned int __read_mostly vdso_enabled = 1;
 
 extern char vdso_start[], vdso_end[];
 extern unsigned short vdso_sync_cpuid;
 
-static struct page **vdso_pages;
+extern struct page *vdso_pages[];
 static unsigned vdso_size;
 
-static int __init init_vdso_vars(void)
+static void __init patch_vdso(void *vdso, size_t len)
+{
+        Elf64_Ehdr *hdr = vdso;
+        Elf64_Shdr *sechdrs, *alt_sec = 0;
+        char *secstrings;
+        void *alt_data;
+        int i;
+
+        BUG_ON(len < sizeof(Elf64_Ehdr));
+        BUG_ON(memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0);
+
+        sechdrs = (void *)hdr + hdr->e_shoff;
+        secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
+
+        for (i = 1; i < hdr->e_shnum; i++) {
+                Elf64_Shdr *shdr = &sechdrs[i];
+                if (!strcmp(secstrings + shdr->sh_name, ".altinstructions")) {
+                        alt_sec = shdr;
+                        goto found;
+                }
+        }
+
+        /* If we get here, it's probably a bug. */
+        pr_warning("patch_vdso: .altinstructions not found\n");
+        return;  /* nothing to patch */
+
+found:
+        alt_data = (void *)hdr + alt_sec->sh_offset;
+        apply_alternatives(alt_data, alt_data + alt_sec->sh_size);
+}
+
+static int __init init_vdso(void)
 {
         int npages = (vdso_end - vdso_start + PAGE_SIZE - 1) / PAGE_SIZE;
         int i;
 
+        patch_vdso(vdso_start, vdso_end - vdso_start);
+
         vdso_size = npages << PAGE_SHIFT;
-        vdso_pages = kmalloc(sizeof(struct page *) * npages, GFP_KERNEL);
-        if (!vdso_pages)
-                goto oom;
-        for (i = 0; i < npages; i++) {
-                struct page *p;
-                p = alloc_page(GFP_KERNEL);
-                if (!p)
-                        goto oom;
-                vdso_pages[i] = p;
-                copy_page(page_address(p), vdso_start + i*PAGE_SIZE);
-        }
+        for (i = 0; i < npages; i++)
+                vdso_pages[i] = virt_to_page(vdso_start + i*PAGE_SIZE);
 
         return 0;
-
- oom:
-        printk("Cannot allocate vdso\n");
-        vdso_enabled = 0;
-        return -ENOMEM;
 }
-subsys_initcall(init_vdso_vars);
+subsys_initcall(init_vdso);
 
 struct linux_binprm;
 
diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile
index 17c565de3d64..ccf73b2f3e69 100644
--- a/arch/x86/xen/Makefile
+++ b/arch/x86/xen/Makefile
@@ -13,10 +13,10 @@ CFLAGS_mmu.o			:= $(nostackp)
 obj-y           := enlighten.o setup.o multicalls.o mmu.o irq.o \
                         time.o xen-asm.o xen-asm_$(BITS).o \
                         grant-table.o suspend.o platform-pci-unplug.o \
-                        p2m.o
+                        p2m.o trace.o
 
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
 obj-$(CONFIG_XEN_DEBUG_FS)      += debugfs.o
-
+obj-$(CONFIG_XEN_DOM0)          += vga.o
 obj-$(CONFIG_SWIOTLB_XEN)       += pci-swiotlb-xen.o
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 5525163a0398..974a528458a0 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -341,6 +341,8 @@ static void xen_set_ldt(const void *addr, unsigned entries)
         struct mmuext_op *op;
         struct multicall_space mcs = xen_mc_entry(sizeof(*op));
 
+        trace_xen_cpu_set_ldt(addr, entries);
+
         op = mcs.args;
         op->cmd = MMUEXT_SET_LDT;
         op->arg1.linear_addr = (unsigned long)addr;
@@ -496,6 +498,8 @@ static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum,
         xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]);
         u64 entry = *(u64 *)ptr;
 
+        trace_xen_cpu_write_ldt_entry(dt, entrynum, entry);
+
         preempt_disable();
 
         xen_mc_flush();
@@ -565,6 +569,8 @@ static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g)
         unsigned long p = (unsigned long)&dt[entrynum];
         unsigned long start, end;
 
+        trace_xen_cpu_write_idt_entry(dt, entrynum, g);
+
         preempt_disable();
 
         start = __this_cpu_read(idt_desc.address);
@@ -619,6 +625,8 @@ static void xen_load_idt(const struct desc_ptr *desc)
         static DEFINE_SPINLOCK(lock);
         static struct trap_info traps[257];
 
+        trace_xen_cpu_load_idt(desc);
+
         spin_lock(&lock);
 
         __get_cpu_var(idt_desc) = *desc;
@@ -637,6 +645,8 @@ static void xen_load_idt(const struct desc_ptr *desc)
 static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
                                 const void *desc, int type)
 {
+        trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
+
         preempt_disable();
 
         switch (type) {
@@ -665,6 +675,8 @@ static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
                                             const void *desc, int type)
 {
+        trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
+
         switch (type) {
         case DESC_LDT:
         case DESC_TSS:
@@ -684,7 +696,9 @@ static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
 static void xen_load_sp0(struct tss_struct *tss,
                          struct thread_struct *thread)
 {
-        struct multicall_space mcs = xen_mc_entry(0);
+        struct multicall_space mcs;
+
+        mcs = xen_mc_entry(0);
         MULTI_stack_switch(mcs.mc, __KERNEL_DS, thread->sp0);
         xen_mc_issue(PARAVIRT_LAZY_CPU);
 }
@@ -1248,6 +1262,14 @@ asmlinkage void __init xen_start_kernel(void)
                 if (pci_xen)
                         x86_init.pci.arch_init = pci_xen_init;
         } else {
+                const struct dom0_vga_console_info *info =
+                        (void *)((char *)xen_start_info +
+                                 xen_start_info->console.dom0.info_off);
+
+                xen_init_vga(info, xen_start_info->console.dom0.info_size);
+                xen_start_info->console.domU.mfn = 0;
+                xen_start_info->console.domU.evtchn = 0;
+
                 /* Make sure ACS will be enabled */
                 pci_request_acs();
         }
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 0ccccb67a993..f987bde77c49 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -48,6 +48,8 @@
 #include <linux/memblock.h>
 #include <linux/seq_file.h>
 
+#include <trace/events/xen.h>
+
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/fixmap.h>
@@ -194,6 +196,8 @@ void xen_set_domain_pte(pte_t *ptep, pte_t pteval, unsigned domid)
         struct multicall_space mcs;
         struct mmu_update *u;
 
+        trace_xen_mmu_set_domain_pte(ptep, pteval, domid);
+
         mcs = xen_mc_entry(sizeof(*u));
         u = mcs.args;
 
@@ -225,6 +229,24 @@ static void xen_extend_mmu_update(const struct mmu_update *update)
         *u = *update;
 }
 
+static void xen_extend_mmuext_op(const struct mmuext_op *op)
+{
+        struct multicall_space mcs;
+        struct mmuext_op *u;
+
+        mcs = xen_mc_extend_args(__HYPERVISOR_mmuext_op, sizeof(*u));
+
+        if (mcs.mc != NULL) {
+                mcs.mc->args[1]++;
+        } else {
+                mcs = __xen_mc_entry(sizeof(*u));
+                MULTI_mmuext_op(mcs.mc, mcs.args, 1, NULL, DOMID_SELF);
+        }
+
+        u = mcs.args;
+        *u = *op;
+}
+
 static void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
 {
         struct mmu_update u;
@@ -245,6 +267,8 @@ static void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
 
 static void xen_set_pmd(pmd_t *ptr, pmd_t val)
 {
+        trace_xen_mmu_set_pmd(ptr, val);
+
         /* If page is not pinned, we can just update the entry
            directly */
         if (!xen_page_pinned(ptr)) {
@@ -282,22 +306,30 @@ static bool xen_batched_set_pte(pte_t *ptep, pte_t pteval)
         return true;
 }
 
-static void xen_set_pte(pte_t *ptep, pte_t pteval)
+static inline void __xen_set_pte(pte_t *ptep, pte_t pteval)
 {
         if (!xen_batched_set_pte(ptep, pteval))
                 native_set_pte(ptep, pteval);
 }
 
+static void xen_set_pte(pte_t *ptep, pte_t pteval)
+{
+        trace_xen_mmu_set_pte(ptep, pteval);
+        __xen_set_pte(ptep, pteval);
+}
+
 static void xen_set_pte_at(struct mm_struct *mm, unsigned long addr,
                     pte_t *ptep, pte_t pteval)
 {
-        xen_set_pte(ptep, pteval);
+        trace_xen_mmu_set_pte_at(mm, addr, ptep, pteval);
+        __xen_set_pte(ptep, pteval);
 }
 
 pte_t xen_ptep_modify_prot_start(struct mm_struct *mm,
                                  unsigned long addr, pte_t *ptep)
 {
         /* Just return the pte as-is.  We preserve the bits on commit */
+        trace_xen_mmu_ptep_modify_prot_start(mm, addr, ptep, *ptep);
         return *ptep;
 }
 
@@ -306,6 +338,7 @@ void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
 {
         struct mmu_update u;
 
+        trace_xen_mmu_ptep_modify_prot_commit(mm, addr, ptep, pte);
         xen_mc_batch();
 
         u.ptr = virt_to_machine(ptep).maddr | MMU_PT_UPDATE_PRESERVE_AD;
@@ -530,6 +563,8 @@ static void xen_set_pud_hyper(pud_t *ptr, pud_t val)
 
 static void xen_set_pud(pud_t *ptr, pud_t val)
 {
+        trace_xen_mmu_set_pud(ptr, val);
+
         /* If page is not pinned, we can just update the entry
            directly */
         if (!xen_page_pinned(ptr)) {
@@ -543,17 +578,20 @@ static void xen_set_pud(pud_t *ptr, pud_t val)
 #ifdef CONFIG_X86_PAE
 static void xen_set_pte_atomic(pte_t *ptep, pte_t pte)
 {
+        trace_xen_mmu_set_pte_atomic(ptep, pte);
         set_64bit((u64 *)ptep, native_pte_val(pte));
 }
 
 static void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
+        trace_xen_mmu_pte_clear(mm, addr, ptep);
         if (!xen_batched_set_pte(ptep, native_make_pte(0)))
                 native_pte_clear(mm, addr, ptep);
 }
 
 static void xen_pmd_clear(pmd_t *pmdp)
 {
+        trace_xen_mmu_pmd_clear(pmdp);
         set_pmd(pmdp, __pmd(0));
 }
 #endif  /* CONFIG_X86_PAE */
@@ -629,6 +667,8 @@ static void xen_set_pgd(pgd_t *ptr, pgd_t val)
 {
         pgd_t *user_ptr = xen_get_user_pgd(ptr);
 
+        trace_xen_mmu_set_pgd(ptr, user_ptr, val);
+
         /* If page is not pinned, we can just update the entry
            directly */
         if (!xen_page_pinned(ptr)) {
@@ -788,14 +828,12 @@ static void xen_pte_unlock(void *v)
 
 static void xen_do_pin(unsigned level, unsigned long pfn)
 {
-        struct mmuext_op *op;
-        struct multicall_space mcs;
+        struct mmuext_op op;
 
-        mcs = __xen_mc_entry(sizeof(*op));
-        op = mcs.args;
-        op->cmd = level;
-        op->arg1.mfn = pfn_to_mfn(pfn);
-        MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
+        op.cmd = level;
+        op.arg1.mfn = pfn_to_mfn(pfn);
+
+        xen_extend_mmuext_op(&op);
 }
 
 static int xen_pin_page(struct mm_struct *mm, struct page *page,
@@ -863,6 +901,8 @@ static int xen_pin_page(struct mm_struct *mm, struct page *page,
    read-only, and can be pinned. */
 static void __xen_pgd_pin(struct mm_struct *mm, pgd_t *pgd)
 {
+        trace_xen_mmu_pgd_pin(mm, pgd);
+
         xen_mc_batch();
 
         if (__xen_pgd_walk(mm, pgd, xen_pin_page, USER_LIMIT)) {
@@ -988,6 +1028,8 @@ static int xen_unpin_page(struct mm_struct *mm, struct page *page,
 /* Release a pagetables pages back as normal RW */
 static void __xen_pgd_unpin(struct mm_struct *mm, pgd_t *pgd)
 {
+        trace_xen_mmu_pgd_unpin(mm, pgd);
+
         xen_mc_batch();
 
         xen_do_pin(MMUEXT_UNPIN_TABLE, PFN_DOWN(__pa(pgd)));
@@ -1196,6 +1238,8 @@ static void xen_flush_tlb(void)
         struct mmuext_op *op;
         struct multicall_space mcs;
 
+        trace_xen_mmu_flush_tlb(0);
+
         preempt_disable();
 
         mcs = xen_mc_entry(sizeof(*op));
@@ -1214,6 +1258,8 @@ static void xen_flush_tlb_single(unsigned long addr)
         struct mmuext_op *op;
         struct multicall_space mcs;
 
+        trace_xen_mmu_flush_tlb_single(addr);
+
         preempt_disable();
 
         mcs = xen_mc_entry(sizeof(*op));
@@ -1240,6 +1286,8 @@ static void xen_flush_tlb_others(const struct cpumask *cpus,
         } *args;
         struct multicall_space mcs;
 
+        trace_xen_mmu_flush_tlb_others(cpus, mm, va);
+
         if (cpumask_empty(cpus))
                 return;         /* nothing to do */
 
@@ -1275,10 +1323,11 @@ static void set_current_cr3(void *v)
 
 static void __xen_write_cr3(bool kernel, unsigned long cr3)
 {
-        struct mmuext_op *op;
-        struct multicall_space mcs;
+        struct mmuext_op op;
         unsigned long mfn;
 
+        trace_xen_mmu_write_cr3(kernel, cr3);
+
         if (cr3)
                 mfn = pfn_to_mfn(PFN_DOWN(cr3));
         else
@@ -1286,13 +1335,10 @@ static void __xen_write_cr3(bool kernel, unsigned long cr3)
 
         WARN_ON(mfn == 0 && kernel);
 
-        mcs = __xen_mc_entry(sizeof(*op));
-
-        op = mcs.args;
-        op->cmd = kernel ? MMUEXT_NEW_BASEPTR : MMUEXT_NEW_USER_BASEPTR;
-        op->arg1.mfn = mfn;
+        op.cmd = kernel ? MMUEXT_NEW_BASEPTR : MMUEXT_NEW_USER_BASEPTR;
+        op.arg1.mfn = mfn;
 
-        MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
+        xen_extend_mmuext_op(&op);
 
         if (kernel) {
                 percpu_write(xen_cr3, cr3);
@@ -1451,19 +1497,52 @@ static void __init xen_release_pmd_init(unsigned long pfn)
         make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
 }
 
+static inline void __pin_pagetable_pfn(unsigned cmd, unsigned long pfn)
+{
+        struct multicall_space mcs;
+        struct mmuext_op *op;
+
+        mcs = __xen_mc_entry(sizeof(*op));
+        op = mcs.args;
+        op->cmd = cmd;
+        op->arg1.mfn = pfn_to_mfn(pfn);
+
+        MULTI_mmuext_op(mcs.mc, mcs.args, 1, NULL, DOMID_SELF);
+}
+
+static inline void __set_pfn_prot(unsigned long pfn, pgprot_t prot)
+{
+        struct multicall_space mcs;
+        unsigned long addr = (unsigned long)__va(pfn << PAGE_SHIFT);
+
+        mcs = __xen_mc_entry(0);
+        MULTI_update_va_mapping(mcs.mc, (unsigned long)addr,
+                                pfn_pte(pfn, prot), 0);
+}
+
 /* This needs to make sure the new pte page is pinned iff its being
    attached to a pinned pagetable. */
-static void xen_alloc_ptpage(struct mm_struct *mm, unsigned long pfn, unsigned level)
+static inline void xen_alloc_ptpage(struct mm_struct *mm, unsigned long pfn,
+                                    unsigned level)
 {
-        struct page *page = pfn_to_page(pfn);
+        bool pinned = PagePinned(virt_to_page(mm->pgd));
+
+        trace_xen_mmu_alloc_ptpage(mm, pfn, level, pinned);
+
+        if (pinned) {
+                struct page *page = pfn_to_page(pfn);
 
-        if (PagePinned(virt_to_page(mm->pgd))) {
                 SetPagePinned(page);
 
                 if (!PageHighMem(page)) {
-                        make_lowmem_page_readonly(__va(PFN_PHYS((unsigned long)pfn)));
+                        xen_mc_batch();
+
+                        __set_pfn_prot(pfn, PAGE_KERNEL_RO);
+
                         if (level == PT_PTE && USE_SPLIT_PTLOCKS)
-                                pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
+                                __pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
+
+                        xen_mc_issue(PARAVIRT_LAZY_MMU);
                 } else {
                         /* make sure there are no stray mappings of
                            this page */
@@ -1483,15 +1562,23 @@ static void xen_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
 }
 
 /* This should never happen until we're OK to use struct page */
-static void xen_release_ptpage(unsigned long pfn, unsigned level)
+static inline void xen_release_ptpage(unsigned long pfn, unsigned level)
 {
         struct page *page = pfn_to_page(pfn);
+        bool pinned = PagePinned(page);
 
-        if (PagePinned(page)) {
+        trace_xen_mmu_release_ptpage(pfn, level, pinned);
+
+        if (pinned) {
                 if (!PageHighMem(page)) {
+                        xen_mc_batch();
+
                         if (level == PT_PTE && USE_SPLIT_PTLOCKS)
-                                pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn);
-                        make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
+                                __pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn);
+
+                        __set_pfn_prot(pfn, PAGE_KERNEL);
+
+                        xen_mc_issue(PARAVIRT_LAZY_MMU);
                 }
                 ClearPagePinned(page);
         }
diff --git a/arch/x86/xen/multicalls.c b/arch/x86/xen/multicalls.c
index 1b2b73ff0a6e..0d82003e76ad 100644
--- a/arch/x86/xen/multicalls.c
+++ b/arch/x86/xen/multicalls.c
@@ -30,12 +30,13 @@
 
 #define MC_BATCH        32
 
-#define MC_DEBUG        1
+#define MC_DEBUG        0
 
 #define MC_ARGS         (MC_BATCH * 16)
 
 
 struct mc_buffer {
+        unsigned mcidx, argidx, cbidx;
         struct multicall_entry entries[MC_BATCH];
 #if MC_DEBUG
         struct multicall_entry debug[MC_BATCH];
@@ -46,85 +47,15 @@ struct mc_buffer {
                 void (*fn)(void *);
                 void *data;
         } callbacks[MC_BATCH];
-        unsigned mcidx, argidx, cbidx;
 };
 
 static DEFINE_PER_CPU(struct mc_buffer, mc_buffer);
 DEFINE_PER_CPU(unsigned long, xen_mc_irq_flags);
 
-/* flush reasons 0- slots, 1- args, 2- callbacks */
-enum flush_reasons
-{
-        FL_SLOTS,
-        FL_ARGS,
-        FL_CALLBACKS,
-
-        FL_N_REASONS
-};
-
-#ifdef CONFIG_XEN_DEBUG_FS
-#define NHYPERCALLS     40              /* not really */
-
-static struct {
-        unsigned histo[MC_BATCH+1];
-
-        unsigned issued;
-        unsigned arg_total;
-        unsigned hypercalls;
-        unsigned histo_hypercalls[NHYPERCALLS];
-
-        unsigned flush[FL_N_REASONS];
-} mc_stats;
-
-static u8 zero_stats;
-
-static inline void check_zero(void)
-{
-        if (unlikely(zero_stats)) {
-                memset(&mc_stats, 0, sizeof(mc_stats));
-                zero_stats = 0;
-        }
-}
-
-static void mc_add_stats(const struct mc_buffer *mc)
-{
-        int i;
-
-        check_zero();
-
-        mc_stats.issued++;
-        mc_stats.hypercalls += mc->mcidx;
-        mc_stats.arg_total += mc->argidx;
-
-        mc_stats.histo[mc->mcidx]++;
-        for(i = 0; i < mc->mcidx; i++) {
-                unsigned op = mc->entries[i].op;
-                if (op < NHYPERCALLS)
-                        mc_stats.histo_hypercalls[op]++;
-        }
-}
-
-static void mc_stats_flush(enum flush_reasons idx)
-{
-        check_zero();
-
-        mc_stats.flush[idx]++;
-}
-
-#else  /* !CONFIG_XEN_DEBUG_FS */
-
-static inline void mc_add_stats(const struct mc_buffer *mc)
-{
-}
-
-static inline void mc_stats_flush(enum flush_reasons idx)
-{
-}
-#endif  /* CONFIG_XEN_DEBUG_FS */
-
 void xen_mc_flush(void)
 {
         struct mc_buffer *b = &__get_cpu_var(mc_buffer);
+        struct multicall_entry *mc;
         int ret = 0;
         unsigned long flags;
         int i;
@@ -135,9 +66,26 @@ void xen_mc_flush(void)
            something in the middle */
         local_irq_save(flags);
 
-        mc_add_stats(b);
+        trace_xen_mc_flush(b->mcidx, b->argidx, b->cbidx);
+
+        switch (b->mcidx) {
+        case 0:
+                /* no-op */
+                BUG_ON(b->argidx != 0);
+                break;
+
+        case 1:
+                /* Singleton multicall - bypass multicall machinery
+                   and just do the call directly. */
+                mc = &b->entries[0];
+
+                mc->result = privcmd_call(mc->op,
+                                          mc->args[0], mc->args[1], mc->args[2], 
+                                          mc->args[3], mc->args[4]);
+                ret = mc->result < 0;
+                break;
 
-        if (b->mcidx) {
+        default:
 #if MC_DEBUG
                 memcpy(b->debug, b->entries,
                        b->mcidx * sizeof(struct multicall_entry));
@@ -164,11 +112,10 @@ void xen_mc_flush(void)
                         }
                 }
 #endif
+        }
 
-                b->mcidx = 0;
-                b->argidx = 0;
-        } else
-                BUG_ON(b->argidx != 0);
+        b->mcidx = 0;
+        b->argidx = 0;
 
         for (i = 0; i < b->cbidx; i++) {
                 struct callback *cb = &b->callbacks[i];
@@ -188,18 +135,21 @@ struct multicall_space __xen_mc_entry(size_t args)
         struct multicall_space ret;
         unsigned argidx = roundup(b->argidx, sizeof(u64));
 
+        trace_xen_mc_entry_alloc(args);
+
         BUG_ON(preemptible());
         BUG_ON(b->argidx >= MC_ARGS);
 
-        if (b->mcidx == MC_BATCH ||
-            (argidx + args) >= MC_ARGS) {
-                mc_stats_flush(b->mcidx == MC_BATCH ? FL_SLOTS : FL_ARGS);
+        if (unlikely(b->mcidx == MC_BATCH ||
+                     (argidx + args) >= MC_ARGS)) {
+                trace_xen_mc_flush_reason((b->mcidx == MC_BATCH) ?
+                                          XEN_MC_FL_BATCH : XEN_MC_FL_ARGS);
                 xen_mc_flush();
                 argidx = roundup(b->argidx, sizeof(u64));
         }
 
         ret.mc = &b->entries[b->mcidx];
-#ifdef MC_DEBUG
+#if MC_DEBUG
         b->caller[b->mcidx] = __builtin_return_address(0);
 #endif
         b->mcidx++;
@@ -218,20 +168,25 @@ struct multicall_space xen_mc_extend_args(unsigned long op, size_t size)
         BUG_ON(preemptible());
         BUG_ON(b->argidx >= MC_ARGS);
 
-        if (b->mcidx == 0)
-                return ret;
-
-        if (b->entries[b->mcidx - 1].op != op)
-                return ret;
+        if (unlikely(b->mcidx == 0 ||
+                     b->entries[b->mcidx - 1].op != op)) {
+                trace_xen_mc_extend_args(op, size, XEN_MC_XE_BAD_OP);
+                goto out;
+        }
 
-        if ((b->argidx + size) >= MC_ARGS)
-                return ret;
+        if (unlikely((b->argidx + size) >= MC_ARGS)) {
+                trace_xen_mc_extend_args(op, size, XEN_MC_XE_NO_SPACE);
+                goto out;
+        }
 
         ret.mc = &b->entries[b->mcidx - 1];
         ret.args = &b->args[b->argidx];
         b->argidx += size;
 
         BUG_ON(b->argidx >= MC_ARGS);
+
+        trace_xen_mc_extend_args(op, size, XEN_MC_XE_OK);
+out:
         return ret;
 }
 
@@ -241,43 +196,13 @@ void xen_mc_callback(void (*fn)(void *), void *data)
         struct callback *cb;
 
         if (b->cbidx == MC_BATCH) {
-                mc_stats_flush(FL_CALLBACKS);
+                trace_xen_mc_flush_reason(XEN_MC_FL_CALLBACK);
                 xen_mc_flush();
         }
 
+        trace_xen_mc_callback(fn, data);
+
         cb = &b->callbacks[b->cbidx++];
         cb->fn = fn;
         cb->data = data;
 }
-
-#ifdef CONFIG_XEN_DEBUG_FS
-
-static struct dentry *d_mc_debug;
-
-static int __init xen_mc_debugfs(void)
-{
-        struct dentry *d_xen = xen_init_debugfs();
-
-        if (d_xen == NULL)
-                return -ENOMEM;
-
-        d_mc_debug = debugfs_create_dir("multicalls", d_xen);
-
-        debugfs_create_u8("zero_stats", 0644, d_mc_debug, &zero_stats);
-
-        debugfs_create_u32("batches", 0444, d_mc_debug, &mc_stats.issued);
-        debugfs_create_u32("hypercalls", 0444, d_mc_debug, &mc_stats.hypercalls);
-        debugfs_create_u32("arg_total", 0444, d_mc_debug, &mc_stats.arg_total);
-
-        xen_debugfs_create_u32_array("batch_histo", 0444, d_mc_debug,
-                                     mc_stats.histo, MC_BATCH);
-        xen_debugfs_create_u32_array("hypercall_histo", 0444, d_mc_debug,
-                                     mc_stats.histo_hypercalls, NHYPERCALLS);
-        xen_debugfs_create_u32_array("flush_reasons", 0444, d_mc_debug,
-                                     mc_stats.flush, FL_N_REASONS);
-
-        return 0;
-}
-fs_initcall(xen_mc_debugfs);
-
-#endif  /* CONFIG_XEN_DEBUG_FS */
diff --git a/arch/x86/xen/multicalls.h b/arch/x86/xen/multicalls.h
index 4ec8035e3216..dee79b78a90f 100644
--- a/arch/x86/xen/multicalls.h
+++ b/arch/x86/xen/multicalls.h
@@ -1,6 +1,8 @@
 #ifndef _XEN_MULTICALLS_H
 #define _XEN_MULTICALLS_H
 
+#include <trace/events/xen.h>
+
 #include "xen-ops.h"
 
 /* Multicalls */
@@ -20,8 +22,10 @@ DECLARE_PER_CPU(unsigned long, xen_mc_irq_flags);
 static inline void xen_mc_batch(void)
 {
         unsigned long flags;
+
         /* need to disable interrupts until this entry is complete */
         local_irq_save(flags);
+        trace_xen_mc_batch(paravirt_get_lazy_mode());
         __this_cpu_write(xen_mc_irq_flags, flags);
 }
 
@@ -37,6 +41,8 @@ void xen_mc_flush(void);
 /* Issue a multicall if we're not in a lazy mode */
 static inline void xen_mc_issue(unsigned mode)
 {
+        trace_xen_mc_issue(mode);
+
         if ((paravirt_get_lazy_mode() & mode) == 0)
                 xen_mc_flush();
 
diff --git a/arch/x86/xen/platform-pci-unplug.c b/arch/x86/xen/platform-pci-unplug.c
index 25c52f94a27c..ffcf2615640b 100644
--- a/arch/x86/xen/platform-pci-unplug.c
+++ b/arch/x86/xen/platform-pci-unplug.c
@@ -35,7 +35,7 @@ EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
 #ifdef CONFIG_XEN_PVHVM
 static int xen_emul_unplug;
 
-static int __init check_platform_magic(void)
+static int check_platform_magic(void)
 {
         short magic;
         char protocol;
diff --git a/arch/x86/xen/trace.c b/arch/x86/xen/trace.c
new file mode 100644
index 000000000000..734beba2a08c
--- /dev/null
+++ b/arch/x86/xen/trace.c
@@ -0,0 +1,61 @@
+#include <linux/ftrace.h>
+
+#define N(x)    [__HYPERVISOR_##x] = "("#x")"
+static const char *xen_hypercall_names[] = {
+        N(set_trap_table),
+        N(mmu_update),
+        N(set_gdt),
+        N(stack_switch),
+        N(set_callbacks),
+        N(fpu_taskswitch),
+        N(sched_op_compat),
+        N(dom0_op),
+        N(set_debugreg),
+        N(get_debugreg),
+        N(update_descriptor),
+        N(memory_op),
+        N(multicall),
+        N(update_va_mapping),
+        N(set_timer_op),
+        N(event_channel_op_compat),
+        N(xen_version),
+        N(console_io),
+        N(physdev_op_compat),
+        N(grant_table_op),
+        N(vm_assist),
+        N(update_va_mapping_otherdomain),
+        N(iret),
+        N(vcpu_op),
+        N(set_segment_base),
+        N(mmuext_op),
+        N(acm_op),
+        N(nmi_op),
+        N(sched_op),
+        N(callback_op),
+        N(xenoprof_op),
+        N(event_channel_op),
+        N(physdev_op),
+        N(hvm_op),
+
+/* Architecture-specific hypercall definitions. */
+        N(arch_0),
+        N(arch_1),
+        N(arch_2),
+        N(arch_3),
+        N(arch_4),
+        N(arch_5),
+        N(arch_6),
+        N(arch_7),
+};
+#undef N
+
+static const char *xen_hypercall_name(unsigned op)
+{
+        if (op < ARRAY_SIZE(xen_hypercall_names) && xen_hypercall_names[op] != NULL)
+                return xen_hypercall_names[op];
+
+        return "";
+}
+
+#define CREATE_TRACE_POINTS
+#include <trace/events/xen.h>
diff --git a/arch/x86/xen/vga.c b/arch/x86/xen/vga.c
new file mode 100644
index 000000000000..1cd7f4d11e29
--- /dev/null
+++ b/arch/x86/xen/vga.c
@@ -0,0 +1,67 @@
+#include <linux/screen_info.h>
+#include <linux/init.h>
+
+#include <asm/bootparam.h>
+#include <asm/setup.h>
+
+#include <xen/interface/xen.h>
+
+#include "xen-ops.h"
+
+void __init xen_init_vga(const struct dom0_vga_console_info *info, size_t size)
+{
+        struct screen_info *screen_info = &boot_params.screen_info;
+
+        /* This is drawn from a dump from vgacon:startup in
+         * standard Linux. */
+        screen_info->orig_video_mode = 3;
+        screen_info->orig_video_isVGA = 1;
+        screen_info->orig_video_lines = 25;
+        screen_info->orig_video_cols = 80;
+        screen_info->orig_video_ega_bx = 3;
+        screen_info->orig_video_points = 16;
+        screen_info->orig_y = screen_info->orig_video_lines - 1;
+
+        switch (info->video_type) {
+        case XEN_VGATYPE_TEXT_MODE_3:
+                if (size < offsetof(struct dom0_vga_console_info, u.text_mode_3)
+                    + sizeof(info->u.text_mode_3))
+                        break;
+                screen_info->orig_video_lines = info->u.text_mode_3.rows;
+                screen_info->orig_video_cols = info->u.text_mode_3.columns;
+                screen_info->orig_x = info->u.text_mode_3.cursor_x;
+                screen_info->orig_y = info->u.text_mode_3.cursor_y;
+                screen_info->orig_video_points =
+                        info->u.text_mode_3.font_height;
+                break;
+
+        case XEN_VGATYPE_VESA_LFB:
+                if (size < offsetof(struct dom0_vga_console_info,
+                                    u.vesa_lfb.gbl_caps))
+                        break;
+                screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
+                screen_info->lfb_width = info->u.vesa_lfb.width;
+                screen_info->lfb_height = info->u.vesa_lfb.height;
+                screen_info->lfb_depth = info->u.vesa_lfb.bits_per_pixel;
+                screen_info->lfb_base = info->u.vesa_lfb.lfb_base;
+                screen_info->lfb_size = info->u.vesa_lfb.lfb_size;
+                screen_info->lfb_linelength = info->u.vesa_lfb.bytes_per_line;
+                screen_info->red_size = info->u.vesa_lfb.red_size;
+                screen_info->red_pos = info->u.vesa_lfb.red_pos;
+                screen_info->green_size = info->u.vesa_lfb.green_size;
+                screen_info->green_pos = info->u.vesa_lfb.green_pos;
+                screen_info->blue_size = info->u.vesa_lfb.blue_size;
+                screen_info->blue_pos = info->u.vesa_lfb.blue_pos;
+                screen_info->rsvd_size = info->u.vesa_lfb.rsvd_size;
+                screen_info->rsvd_pos = info->u.vesa_lfb.rsvd_pos;
+                if (size >= offsetof(struct dom0_vga_console_info,
+                                     u.vesa_lfb.gbl_caps)
+                    + sizeof(info->u.vesa_lfb.gbl_caps))
+                        screen_info->capabilities = info->u.vesa_lfb.gbl_caps;
+                if (size >= offsetof(struct dom0_vga_console_info,
+                                     u.vesa_lfb.mode_attrs)
+                    + sizeof(info->u.vesa_lfb.mode_attrs))
+                        screen_info->vesa_attributes = info->u.vesa_lfb.mode_attrs;
+                break;
+        }
+}
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 97dfdc8757b3..b095739ccd4c 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -88,6 +88,17 @@ static inline void xen_uninit_lock_cpu(int cpu)
 }
 #endif
 
+struct dom0_vga_console_info;
+
+#ifdef CONFIG_XEN_DOM0
+void __init xen_init_vga(const struct dom0_vga_console_info *, size_t size);
+#else
+static inline void __init xen_init_vga(const struct dom0_vga_console_info *info,
+                                       size_t size)
+{
+}
+#endif
+
 /* Declare an asm function, along with symbols needed to make it
    inlineable */
 #define DECL_ASM(ret, name, ...)                \
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 5d43c1f8ada8..c346ccdce0df 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -80,18 +80,7 @@ config XTENSA_UNALIGNED_USER
 
           Say Y here to enable unaligned memory access in user space.
 
-config PREEMPT
-        bool "Preemptible Kernel"
-        help
-          This option reduces the latency of the kernel when reacting to
-          real-time or interactive events by allowing a low priority process to
-          be preempted even if it is in kernel mode executing a system call.
-          Unfortunately the kernel code has some race conditions if both
-          CONFIG_SMP and CONFIG_PREEMPT are enabled, so this option is
-          currently disabled if you are building an SMP kernel.
-
-          Say Y here if you are building a kernel for a desktop, embedded
-          or real-time system.  Say N if you are unsure.
+source "kernel/Kconfig.preempt"
 
 config MATH_EMULATION
         bool "Math emulation"