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-rw-r--r--arch/mips/Kconfig19
-rw-r--r--arch/mips/Makefile34
-rw-r--r--arch/mips/ath79/clock.c258
-rw-r--r--arch/mips/ath79/common.h2
-rw-r--r--arch/mips/ath79/dev-common.c10
-rw-r--r--arch/mips/ath79/setup.c23
-rw-r--r--arch/mips/boot/.gitignore1
-rw-r--r--arch/mips/boot/Makefile15
-rw-r--r--arch/mips/boot/compressed/Makefile2
l---------arch/mips/boot/dts/include/dt-bindings1
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c2
-rw-r--r--arch/mips/cavium-octeon/setup.c28
-rw-r--r--arch/mips/cavium-octeon/smp.c4
-rw-r--r--arch/mips/configs/xway_defconfig159
-rw-r--r--arch/mips/dec/time.c5
-rw-r--r--arch/mips/include/asm/Kbuild13
-rw-r--r--arch/mips/include/asm/bmips.h55
-rw-r--r--arch/mips/include/asm/cpu.h6
-rw-r--r--arch/mips/include/asm/cputime.h6
-rw-r--r--arch/mips/include/asm/current.h1
-rw-r--r--arch/mips/include/asm/emergency-restart.h6
-rw-r--r--arch/mips/include/asm/local64.h1
-rw-r--r--arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/gpio.h21
-rw-r--r--arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h58
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620.h40
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h57
-rw-r--r--arch/mips/include/asm/mutex.h9
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h10
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h5
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h31
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h17
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h2
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/parport.h1
-rw-r--r--arch/mips/include/asm/percpu.h6
-rw-r--r--arch/mips/include/asm/scatterlist.h6
-rw-r--r--arch/mips/include/asm/sections.h6
-rw-r--r--arch/mips/include/asm/segment.h6
-rw-r--r--arch/mips/include/asm/serial.h1
-rw-r--r--arch/mips/include/asm/ucontext.h1
-rw-r--r--arch/mips/include/asm/xor.h1
-rw-r--r--arch/mips/include/uapi/asm/Kbuild5
-rw-r--r--arch/mips/include/uapi/asm/auxvec.h4
-rw-r--r--arch/mips/include/uapi/asm/ipcbuf.h1
-rw-r--r--arch/mips/kernel/cpu-probe.c12
-rw-r--r--arch/mips/kernel/csrc-ioasic.c6
-rw-r--r--arch/mips/kernel/idle.c1
-rw-r--r--arch/mips/kernel/mcount.S2
-rw-r--r--arch/mips/kernel/relocate_kernel.S6
-rw-r--r--arch/mips/kernel/setup.c99
-rw-r--r--arch/mips/kernel/time.c10
-rw-r--r--arch/mips/kernel/vmlinux.lds.S1
-rw-r--r--arch/mips/lantiq/falcon/sysctrl.c5
-rw-r--r--arch/mips/lantiq/xway/Makefile2
-rw-r--r--arch/mips/lantiq/xway/dcdc.c63
-rw-r--r--arch/mips/lasat/image/Makefile6
-rw-r--r--arch/mips/loongson/common/Makefile3
-rw-r--r--arch/mips/math-emu/cp1emu.c27
-rw-r--r--arch/mips/mm/c-octeon.c14
-rw-r--r--arch/mips/mm/dma-default.c18
-rw-r--r--arch/mips/mm/gup.c3
-rw-r--r--arch/mips/mm/init.c1
-rw-r--r--arch/mips/mm/tlb-funcs.S2
-rw-r--r--arch/mips/mm/tlbex.c2
-rw-r--r--arch/mips/netlogic/Kconfig9
-rw-r--r--arch/mips/netlogic/common/smp.c4
-rw-r--r--arch/mips/netlogic/common/time.c3
-rw-r--r--arch/mips/netlogic/dts/Makefile1
-rw-r--r--arch/mips/netlogic/dts/xlp_evp.dts9
-rw-r--r--arch/mips/netlogic/dts/xlp_fvp.dts118
-rw-r--r--arch/mips/netlogic/dts/xlp_svp.dts9
-rw-r--r--arch/mips/netlogic/xlp/Makefile1
-rw-r--r--arch/mips/netlogic/xlp/dt.c8
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c237
-rw-r--r--arch/mips/netlogic/xlp/setup.c50
-rw-r--r--arch/mips/netlogic/xlp/usb-init-xlp2.c218
-rw-r--r--arch/mips/netlogic/xlp/usb-init.c6
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c10
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/pci-octeon.c9
-rw-r--r--arch/mips/pci/pci-rt3883.c636
-rw-r--r--arch/mips/powertv/Kconfig9
-rw-r--r--arch/mips/powertv/asic/asic_devices.c12
-rw-r--r--arch/mips/powertv/init.c4
-rw-r--r--arch/mips/powertv/reset.c12
-rw-r--r--arch/mips/ralink/Kconfig10
-rw-r--r--arch/mips/ralink/Makefile4
-rw-r--r--arch/mips/ralink/Platform1
-rw-r--r--arch/mips/ralink/cevt-rt3352.c145
-rw-r--r--arch/mips/ralink/clk.c1
-rw-r--r--arch/mips/ralink/common.h2
-rw-r--r--arch/mips/ralink/mt7620.c205
-rw-r--r--arch/mips/ralink/of.c3
-rw-r--r--arch/mips/ralink/reset.c62
-rw-r--r--arch/mips/ralink/timer.c185
-rw-r--r--arch/mips/txx9/generic/setup.c2
98 files changed, 2732 insertions, 484 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 71f15e73bc89..a9668d4653c2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -95,6 +95,7 @@ config ATH79
95 select CSRC_R4K 95 select CSRC_R4K
96 select DMA_NONCOHERENT 96 select DMA_NONCOHERENT
97 select HAVE_CLK 97 select HAVE_CLK
98 select CLKDEV_LOOKUP
98 select IRQ_CPU 99 select IRQ_CPU
99 select MIPS_MACHINE 100 select MIPS_MACHINE
100 select SYS_HAS_CPU_MIPS32_R2 101 select SYS_HAS_CPU_MIPS32_R2
@@ -131,7 +132,6 @@ config BCM63XX
131 select IRQ_CPU 132 select IRQ_CPU
132 select SYS_HAS_CPU_MIPS32_R1 133 select SYS_HAS_CPU_MIPS32_R1
133 select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 134 select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
134 select NR_CPUS_DEFAULT_2
135 select SYS_SUPPORTS_32BIT_KERNEL 135 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_BIG_ENDIAN 136 select SYS_SUPPORTS_BIG_ENDIAN
137 select SYS_HAS_EARLY_PRINTK 137 select SYS_HAS_EARLY_PRINTK
@@ -445,6 +445,8 @@ config RALINK
445 select SYS_HAS_EARLY_PRINTK 445 select SYS_HAS_EARLY_PRINTK
446 select HAVE_MACH_CLKDEV 446 select HAVE_MACH_CLKDEV
447 select CLKDEV_LOOKUP 447 select CLKDEV_LOOKUP
448 select ARCH_HAS_RESET_CONTROLLER
449 select RESET_CONTROLLER
448 450
449config SGI_IP22 451config SGI_IP22
450 bool "SGI IP22 (Indy/Indigo2)" 452 bool "SGI IP22 (Indy/Indigo2)"
@@ -609,7 +611,6 @@ config SIBYTE_SWARM
609 select BOOT_ELF32 611 select BOOT_ELF32
610 select DMA_COHERENT 612 select DMA_COHERENT
611 select HAVE_PATA_PLATFORM 613 select HAVE_PATA_PLATFORM
612 select NR_CPUS_DEFAULT_2
613 select SIBYTE_SB1250 614 select SIBYTE_SB1250
614 select SWAP_IO_SPACE 615 select SWAP_IO_SPACE
615 select SYS_HAS_CPU_SB1 616 select SYS_HAS_CPU_SB1
@@ -623,7 +624,6 @@ config SIBYTE_LITTLESUR
623 select BOOT_ELF32 624 select BOOT_ELF32
624 select DMA_COHERENT 625 select DMA_COHERENT
625 select HAVE_PATA_PLATFORM 626 select HAVE_PATA_PLATFORM
626 select NR_CPUS_DEFAULT_2
627 select SIBYTE_SB1250 627 select SIBYTE_SB1250
628 select SWAP_IO_SPACE 628 select SWAP_IO_SPACE
629 select SYS_HAS_CPU_SB1 629 select SYS_HAS_CPU_SB1
@@ -635,7 +635,6 @@ config SIBYTE_SENTOSA
635 bool "Sibyte BCM91250E-Sentosa" 635 bool "Sibyte BCM91250E-Sentosa"
636 select BOOT_ELF32 636 select BOOT_ELF32
637 select DMA_COHERENT 637 select DMA_COHERENT
638 select NR_CPUS_DEFAULT_2
639 select SIBYTE_SB1250 638 select SIBYTE_SB1250
640 select SWAP_IO_SPACE 639 select SWAP_IO_SPACE
641 select SYS_HAS_CPU_SB1 640 select SYS_HAS_CPU_SB1
@@ -731,6 +730,7 @@ config CAVIUM_OCTEON_SOC
731 select USB_ARCH_HAS_OHCI 730 select USB_ARCH_HAS_OHCI
732 select USB_ARCH_HAS_EHCI 731 select USB_ARCH_HAS_EHCI
733 select HOLES_IN_ZONE 732 select HOLES_IN_ZONE
733 select ARCH_REQUIRE_GPIOLIB
734 help 734 help
735 This option supports all of the Octeon reference boards from Cavium 735 This option supports all of the Octeon reference boards from Cavium
736 Networks. It builds a kernel that dynamically determines the Octeon 736 Networks. It builds a kernel that dynamically determines the Octeon
@@ -1860,7 +1860,6 @@ config MIPS_MT_SMP
1860 select CPU_MIPSR2_IRQ_VI 1860 select CPU_MIPSR2_IRQ_VI
1861 select CPU_MIPSR2_IRQ_EI 1861 select CPU_MIPSR2_IRQ_EI
1862 select MIPS_MT 1862 select MIPS_MT
1863 select NR_CPUS_DEFAULT_2
1864 select SMP 1863 select SMP
1865 select SYS_SUPPORTS_SCHED_SMT if SMP 1864 select SYS_SUPPORTS_SCHED_SMT if SMP
1866 select SYS_SUPPORTS_SMP 1865 select SYS_SUPPORTS_SMP
@@ -2171,12 +2170,6 @@ config SYS_SUPPORTS_MIPS_CMP
2171config SYS_SUPPORTS_SMP 2170config SYS_SUPPORTS_SMP
2172 bool 2171 bool
2173 2172
2174config NR_CPUS_DEFAULT_1
2175 bool
2176
2177config NR_CPUS_DEFAULT_2
2178 bool
2179
2180config NR_CPUS_DEFAULT_4 2173config NR_CPUS_DEFAULT_4
2181 bool 2174 bool
2182 2175
@@ -2194,10 +2187,8 @@ config NR_CPUS_DEFAULT_64
2194 2187
2195config NR_CPUS 2188config NR_CPUS
2196 int "Maximum number of CPUs (2-64)" 2189 int "Maximum number of CPUs (2-64)"
2197 range 1 64 if NR_CPUS_DEFAULT_1 2190 range 2 64
2198 depends on SMP 2191 depends on SMP
2199 default "1" if NR_CPUS_DEFAULT_1
2200 default "2" if NR_CPUS_DEFAULT_2
2201 default "4" if NR_CPUS_DEFAULT_4 2192 default "4" if NR_CPUS_DEFAULT_4
2202 default "8" if NR_CPUS_DEFAULT_8 2193 default "8" if NR_CPUS_DEFAULT_8
2203 default "16" if NR_CPUS_DEFAULT_16 2194 default "16" if NR_CPUS_DEFAULT_16
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 37f9ef324f2f..75a36ad11ff5 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -194,6 +194,8 @@ include $(srctree)/arch/mips/Kbuild.platforms
194ifdef CONFIG_PHYSICAL_START 194ifdef CONFIG_PHYSICAL_START
195load-y = $(CONFIG_PHYSICAL_START) 195load-y = $(CONFIG_PHYSICAL_START)
196endif 196endif
197entry-y = 0x$(shell $(NM) vmlinux 2>/dev/null \
198 | grep "\bkernel_entry\b" | cut -f1 -d \ )
197 199
198cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 200cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
199drivers-$(CONFIG_PCI) += arch/mips/pci/ 201drivers-$(CONFIG_PCI) += arch/mips/pci/
@@ -225,6 +227,9 @@ KBUILD_CFLAGS += $(cflags-y)
225KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) 227KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
226KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) 228KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
227 229
230bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
231 VMLINUX_ENTRY_ADDRESS=$(entry-y)
232
228LDFLAGS += -m $(ld-emul) 233LDFLAGS += -m $(ld-emul)
229 234
230ifdef CONFIG_CC_STACKPROTECTOR 235ifdef CONFIG_CC_STACKPROTECTOR
@@ -254,9 +259,25 @@ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
254# suspend and hibernation support 259# suspend and hibernation support
255drivers-$(CONFIG_PM) += arch/mips/power/ 260drivers-$(CONFIG_PM) += arch/mips/power/
256 261
262# boot image targets (arch/mips/boot/)
263boot-y := vmlinux.bin
264boot-y += vmlinux.ecoff
265boot-y += vmlinux.srec
266ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)
267boot-y += uImage
268boot-y += uImage.gz
269endif
270
271# compressed boot image targets (arch/mips/boot/compressed/)
272bootz-y := vmlinuz
273bootz-y += vmlinuz.bin
274bootz-y += vmlinuz.ecoff
275bootz-y += vmlinuz.srec
276
257ifdef CONFIG_LASAT 277ifdef CONFIG_LASAT
258rom.bin rom.sw: vmlinux 278rom.bin rom.sw: vmlinux
259 $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ 279 $(Q)$(MAKE) $(build)=arch/mips/lasat/image \
280 $(bootvars-y) $@
260endif 281endif
261 282
262# 283#
@@ -280,13 +301,14 @@ vmlinux.64: vmlinux
280all: $(all-y) 301all: $(all-y)
281 302
282# boot 303# boot
283vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE 304$(boot-y): $(vmlinux-32) FORCE
284 $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@ 305 $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
306 $(bootvars-y) arch/mips/boot/$@
285 307
286# boot/compressed 308# boot/compressed
287vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE 309$(bootz-y): $(vmlinux-32) FORCE
288 $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ 310 $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
289 VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@ 311 $(bootvars-y) 32bit-bfd=$(32bit-bfd) $@
290 312
291 313
292CLEAN_FILES += vmlinux.32 vmlinux.64 314CLEAN_FILES += vmlinux.32 vmlinux.64
@@ -323,6 +345,8 @@ define archhelp
323 echo ' vmlinuz.ecoff - ECOFF zboot image' 345 echo ' vmlinuz.ecoff - ECOFF zboot image'
324 echo ' vmlinuz.bin - Raw binary zboot image' 346 echo ' vmlinuz.bin - Raw binary zboot image'
325 echo ' vmlinuz.srec - SREC zboot image' 347 echo ' vmlinuz.srec - SREC zboot image'
348 echo ' uImage - U-Boot image'
349 echo ' uImage.gz - U-Boot image (gzip)'
326 echo 350 echo
327 echo ' These will be default as appropriate for a configured platform.' 351 echo ' These will be default as appropriate for a configured platform.'
328endef 352endef
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 765ef30e3e1c..26479f437675 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -16,6 +16,7 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/clkdev.h>
19 20
20#include <asm/div64.h> 21#include <asm/div64.h>
21 22
@@ -31,92 +32,132 @@ struct clk {
31 unsigned long rate; 32 unsigned long rate;
32}; 33};
33 34
34static struct clk ath79_ref_clk; 35static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
35static struct clk ath79_cpu_clk; 36{
36static struct clk ath79_ddr_clk; 37 struct clk *clk;
37static struct clk ath79_ahb_clk; 38 int err;
38static struct clk ath79_wdt_clk; 39
39static struct clk ath79_uart_clk; 40 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
41 if (!clk)
42 panic("failed to allocate %s clock structure", id);
43
44 clk->rate = rate;
45
46 err = clk_register_clkdev(clk, id, NULL);
47 if (err)
48 panic("unable to register %s clock device", id);
49}
40 50
41static void __init ar71xx_clocks_init(void) 51static void __init ar71xx_clocks_init(void)
42{ 52{
53 unsigned long ref_rate;
54 unsigned long cpu_rate;
55 unsigned long ddr_rate;
56 unsigned long ahb_rate;
43 u32 pll; 57 u32 pll;
44 u32 freq; 58 u32 freq;
45 u32 div; 59 u32 div;
46 60
47 ath79_ref_clk.rate = AR71XX_BASE_FREQ; 61 ref_rate = AR71XX_BASE_FREQ;
48 62
49 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); 63 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
50 64
51 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; 65 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
52 freq = div * ath79_ref_clk.rate; 66 freq = div * ref_rate;
53 67
54 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 68 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
55 ath79_cpu_clk.rate = freq / div; 69 cpu_rate = freq / div;
56 70
57 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 71 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
58 ath79_ddr_clk.rate = freq / div; 72 ddr_rate = freq / div;
59 73
60 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 74 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
61 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; 75 ahb_rate = cpu_rate / div;
76
77 ath79_add_sys_clkdev("ref", ref_rate);
78 ath79_add_sys_clkdev("cpu", cpu_rate);
79 ath79_add_sys_clkdev("ddr", ddr_rate);
80 ath79_add_sys_clkdev("ahb", ahb_rate);
62 81
63 ath79_wdt_clk.rate = ath79_ahb_clk.rate; 82 clk_add_alias("wdt", NULL, "ahb", NULL);
64 ath79_uart_clk.rate = ath79_ahb_clk.rate; 83 clk_add_alias("uart", NULL, "ahb", NULL);
65} 84}
66 85
67static void __init ar724x_clocks_init(void) 86static void __init ar724x_clocks_init(void)
68{ 87{
88 unsigned long ref_rate;
89 unsigned long cpu_rate;
90 unsigned long ddr_rate;
91 unsigned long ahb_rate;
69 u32 pll; 92 u32 pll;
70 u32 freq; 93 u32 freq;
71 u32 div; 94 u32 div;
72 95
73 ath79_ref_clk.rate = AR724X_BASE_FREQ; 96 ref_rate = AR724X_BASE_FREQ;
74 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); 97 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
75 98
76 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); 99 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
77 freq = div * ath79_ref_clk.rate; 100 freq = div * ref_rate;
78 101
79 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); 102 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
80 freq *= div; 103 freq *= div;
81 104
82 ath79_cpu_clk.rate = freq; 105 cpu_rate = freq;
83 106
84 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; 107 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
85 ath79_ddr_clk.rate = freq / div; 108 ddr_rate = freq / div;
86 109
87 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; 110 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
88 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; 111 ahb_rate = cpu_rate / div;
112
113 ath79_add_sys_clkdev("ref", ref_rate);
114 ath79_add_sys_clkdev("cpu", cpu_rate);
115 ath79_add_sys_clkdev("ddr", ddr_rate);
116 ath79_add_sys_clkdev("ahb", ahb_rate);
89 117
90 ath79_wdt_clk.rate = ath79_ahb_clk.rate; 118 clk_add_alias("wdt", NULL, "ahb", NULL);
91 ath79_uart_clk.rate = ath79_ahb_clk.rate; 119 clk_add_alias("uart", NULL, "ahb", NULL);
92} 120}
93 121
94static void __init ar913x_clocks_init(void) 122static void __init ar913x_clocks_init(void)
95{ 123{
124 unsigned long ref_rate;
125 unsigned long cpu_rate;
126 unsigned long ddr_rate;
127 unsigned long ahb_rate;
96 u32 pll; 128 u32 pll;
97 u32 freq; 129 u32 freq;
98 u32 div; 130 u32 div;
99 131
100 ath79_ref_clk.rate = AR913X_BASE_FREQ; 132 ref_rate = AR913X_BASE_FREQ;
101 pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); 133 pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
102 134
103 div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); 135 div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
104 freq = div * ath79_ref_clk.rate; 136 freq = div * ref_rate;
105 137
106 ath79_cpu_clk.rate = freq; 138 cpu_rate = freq;
107 139
108 div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; 140 div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
109 ath79_ddr_clk.rate = freq / div; 141 ddr_rate = freq / div;
110 142
111 div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; 143 div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
112 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; 144 ahb_rate = cpu_rate / div;
113 145
114 ath79_wdt_clk.rate = ath79_ahb_clk.rate; 146 ath79_add_sys_clkdev("ref", ref_rate);
115 ath79_uart_clk.rate = ath79_ahb_clk.rate; 147 ath79_add_sys_clkdev("cpu", cpu_rate);
148 ath79_add_sys_clkdev("ddr", ddr_rate);
149 ath79_add_sys_clkdev("ahb", ahb_rate);
150
151 clk_add_alias("wdt", NULL, "ahb", NULL);
152 clk_add_alias("uart", NULL, "ahb", NULL);
116} 153}
117 154
118static void __init ar933x_clocks_init(void) 155static void __init ar933x_clocks_init(void)
119{ 156{
157 unsigned long ref_rate;
158 unsigned long cpu_rate;
159 unsigned long ddr_rate;
160 unsigned long ahb_rate;
120 u32 clock_ctrl; 161 u32 clock_ctrl;
121 u32 cpu_config; 162 u32 cpu_config;
122 u32 freq; 163 u32 freq;
@@ -124,21 +165,21 @@ static void __init ar933x_clocks_init(void)
124 165
125 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); 166 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
126 if (t & AR933X_BOOTSTRAP_REF_CLK_40) 167 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
127 ath79_ref_clk.rate = (40 * 1000 * 1000); 168 ref_rate = (40 * 1000 * 1000);
128 else 169 else
129 ath79_ref_clk.rate = (25 * 1000 * 1000); 170 ref_rate = (25 * 1000 * 1000);
130 171
131 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); 172 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
132 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { 173 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
133 ath79_cpu_clk.rate = ath79_ref_clk.rate; 174 cpu_rate = ref_rate;
134 ath79_ahb_clk.rate = ath79_ref_clk.rate; 175 ahb_rate = ref_rate;
135 ath79_ddr_clk.rate = ath79_ref_clk.rate; 176 ddr_rate = ref_rate;
136 } else { 177 } else {
137 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); 178 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
138 179
139 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 180 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
140 AR933X_PLL_CPU_CONFIG_REFDIV_MASK; 181 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
141 freq = ath79_ref_clk.rate / t; 182 freq = ref_rate / t;
142 183
143 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & 184 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
144 AR933X_PLL_CPU_CONFIG_NINT_MASK; 185 AR933X_PLL_CPU_CONFIG_NINT_MASK;
@@ -153,19 +194,24 @@ static void __init ar933x_clocks_init(void)
153 194
154 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & 195 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
155 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; 196 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
156 ath79_cpu_clk.rate = freq / t; 197 cpu_rate = freq / t;
157 198
158 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & 199 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
159 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; 200 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
160 ath79_ddr_clk.rate = freq / t; 201 ddr_rate = freq / t;
161 202
162 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & 203 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
163 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; 204 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
164 ath79_ahb_clk.rate = freq / t; 205 ahb_rate = freq / t;
165 } 206 }
166 207
167 ath79_wdt_clk.rate = ath79_ref_clk.rate; 208 ath79_add_sys_clkdev("ref", ref_rate);
168 ath79_uart_clk.rate = ath79_ref_clk.rate; 209 ath79_add_sys_clkdev("cpu", cpu_rate);
210 ath79_add_sys_clkdev("ddr", ddr_rate);
211 ath79_add_sys_clkdev("ahb", ahb_rate);
212
213 clk_add_alias("wdt", NULL, "ahb", NULL);
214 clk_add_alias("uart", NULL, "ref", NULL);
169} 215}
170 216
171static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, 217static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
@@ -174,12 +220,12 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
174 u64 t; 220 u64 t;
175 u32 ret; 221 u32 ret;
176 222
177 t = ath79_ref_clk.rate; 223 t = ref;
178 t *= nint; 224 t *= nint;
179 do_div(t, ref_div); 225 do_div(t, ref_div);
180 ret = t; 226 ret = t;
181 227
182 t = ath79_ref_clk.rate; 228 t = ref;
183 t *= nfrac; 229 t *= nfrac;
184 do_div(t, ref_div * frac); 230 do_div(t, ref_div * frac);
185 ret += t; 231 ret += t;
@@ -190,6 +236,10 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
190 236
191static void __init ar934x_clocks_init(void) 237static void __init ar934x_clocks_init(void)
192{ 238{
239 unsigned long ref_rate;
240 unsigned long cpu_rate;
241 unsigned long ddr_rate;
242 unsigned long ahb_rate;
193 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; 243 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
194 u32 cpu_pll, ddr_pll; 244 u32 cpu_pll, ddr_pll;
195 u32 bootstrap; 245 u32 bootstrap;
@@ -199,9 +249,9 @@ static void __init ar934x_clocks_init(void)
199 249
200 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 250 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
201 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) 251 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
202 ath79_ref_clk.rate = 40 * 1000 * 1000; 252 ref_rate = 40 * 1000 * 1000;
203 else 253 else
204 ath79_ref_clk.rate = 25 * 1000 * 1000; 254 ref_rate = 25 * 1000 * 1000;
205 255
206 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); 256 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
207 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 257 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
@@ -227,7 +277,7 @@ static void __init ar934x_clocks_init(void)
227 frac = 1 << 6; 277 frac = 1 << 6;
228 } 278 }
229 279
230 cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, 280 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
231 nfrac, frac, out_div); 281 nfrac, frac, out_div);
232 282
233 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); 283 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
@@ -254,7 +304,7 @@ static void __init ar934x_clocks_init(void)
254 frac = 1 << 10; 304 frac = 1 << 10;
255 } 305 }
256 306
257 ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, 307 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
258 nfrac, frac, out_div); 308 nfrac, frac, out_div);
259 309
260 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); 310 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
@@ -263,49 +313,58 @@ static void __init ar934x_clocks_init(void)
263 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; 313 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
264 314
265 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) 315 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
266 ath79_cpu_clk.rate = ath79_ref_clk.rate; 316 cpu_rate = ref_rate;
267 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) 317 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
268 ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); 318 cpu_rate = cpu_pll / (postdiv + 1);
269 else 319 else
270 ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); 320 cpu_rate = ddr_pll / (postdiv + 1);
271 321
272 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & 322 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
273 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; 323 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
274 324
275 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) 325 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
276 ath79_ddr_clk.rate = ath79_ref_clk.rate; 326 ddr_rate = ref_rate;
277 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) 327 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
278 ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); 328 ddr_rate = ddr_pll / (postdiv + 1);
279 else 329 else
280 ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); 330 ddr_rate = cpu_pll / (postdiv + 1);
281 331
282 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & 332 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
283 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; 333 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
284 334
285 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) 335 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
286 ath79_ahb_clk.rate = ath79_ref_clk.rate; 336 ahb_rate = ref_rate;
287 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) 337 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
288 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); 338 ahb_rate = ddr_pll / (postdiv + 1);
289 else 339 else
290 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); 340 ahb_rate = cpu_pll / (postdiv + 1);
341
342 ath79_add_sys_clkdev("ref", ref_rate);
343 ath79_add_sys_clkdev("cpu", cpu_rate);
344 ath79_add_sys_clkdev("ddr", ddr_rate);
345 ath79_add_sys_clkdev("ahb", ahb_rate);
291 346
292 ath79_wdt_clk.rate = ath79_ref_clk.rate; 347 clk_add_alias("wdt", NULL, "ref", NULL);
293 ath79_uart_clk.rate = ath79_ref_clk.rate; 348 clk_add_alias("uart", NULL, "ref", NULL);
294 349
295 iounmap(dpll_base); 350 iounmap(dpll_base);
296} 351}
297 352
298static void __init qca955x_clocks_init(void) 353static void __init qca955x_clocks_init(void)
299{ 354{
355 unsigned long ref_rate;
356 unsigned long cpu_rate;
357 unsigned long ddr_rate;
358 unsigned long ahb_rate;
300 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; 359 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
301 u32 cpu_pll, ddr_pll; 360 u32 cpu_pll, ddr_pll;
302 u32 bootstrap; 361 u32 bootstrap;
303 362
304 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); 363 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
305 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) 364 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
306 ath79_ref_clk.rate = 40 * 1000 * 1000; 365 ref_rate = 40 * 1000 * 1000;
307 else 366 else
308 ath79_ref_clk.rate = 25 * 1000 * 1000; 367 ref_rate = 25 * 1000 * 1000;
309 368
310 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); 369 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
311 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 370 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
@@ -317,8 +376,8 @@ static void __init qca955x_clocks_init(void)
317 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 376 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
318 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; 377 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
319 378
320 cpu_pll = nint * ath79_ref_clk.rate / ref_div; 379 cpu_pll = nint * ref_rate / ref_div;
321 cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); 380 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
322 cpu_pll /= (1 << out_div); 381 cpu_pll /= (1 << out_div);
323 382
324 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); 383 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
@@ -331,8 +390,8 @@ static void __init qca955x_clocks_init(void)
331 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 390 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
332 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; 391 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
333 392
334 ddr_pll = nint * ath79_ref_clk.rate / ref_div; 393 ddr_pll = nint * ref_rate / ref_div;
335 ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); 394 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
336 ddr_pll /= (1 << out_div); 395 ddr_pll /= (1 << out_div);
337 396
338 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); 397 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
@@ -341,34 +400,39 @@ static void __init qca955x_clocks_init(void)
341 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; 400 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
342 401
343 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) 402 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
344 ath79_cpu_clk.rate = ath79_ref_clk.rate; 403 cpu_rate = ref_rate;
345 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) 404 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
346 ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); 405 cpu_rate = ddr_pll / (postdiv + 1);
347 else 406 else
348 ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); 407 cpu_rate = cpu_pll / (postdiv + 1);
349 408
350 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & 409 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
351 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; 410 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
352 411
353 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) 412 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
354 ath79_ddr_clk.rate = ath79_ref_clk.rate; 413 ddr_rate = ref_rate;
355 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) 414 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
356 ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); 415 ddr_rate = cpu_pll / (postdiv + 1);
357 else 416 else
358 ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); 417 ddr_rate = ddr_pll / (postdiv + 1);
359 418
360 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & 419 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
361 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; 420 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
362 421
363 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) 422 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
364 ath79_ahb_clk.rate = ath79_ref_clk.rate; 423 ahb_rate = ref_rate;
365 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) 424 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
366 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); 425 ahb_rate = ddr_pll / (postdiv + 1);
367 else 426 else
368 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); 427 ahb_rate = cpu_pll / (postdiv + 1);
369 428
370 ath79_wdt_clk.rate = ath79_ref_clk.rate; 429 ath79_add_sys_clkdev("ref", ref_rate);
371 ath79_uart_clk.rate = ath79_ref_clk.rate; 430 ath79_add_sys_clkdev("cpu", cpu_rate);
431 ath79_add_sys_clkdev("ddr", ddr_rate);
432 ath79_add_sys_clkdev("ahb", ahb_rate);
433
434 clk_add_alias("wdt", NULL, "ref", NULL);
435 clk_add_alias("uart", NULL, "ref", NULL);
372} 436}
373 437
374void __init ath79_clocks_init(void) 438void __init ath79_clocks_init(void)
@@ -387,46 +451,27 @@ void __init ath79_clocks_init(void)
387 qca955x_clocks_init(); 451 qca955x_clocks_init();
388 else 452 else
389 BUG(); 453 BUG();
390
391 pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, "
392 "Ref:%lu.%03luMHz",
393 ath79_cpu_clk.rate / 1000000,
394 (ath79_cpu_clk.rate / 1000) % 1000,
395 ath79_ddr_clk.rate / 1000000,
396 (ath79_ddr_clk.rate / 1000) % 1000,
397 ath79_ahb_clk.rate / 1000000,
398 (ath79_ahb_clk.rate / 1000) % 1000,
399 ath79_ref_clk.rate / 1000000,
400 (ath79_ref_clk.rate / 1000) % 1000);
401} 454}
402 455
403/* 456unsigned long __init
404 * Linux clock API 457ath79_get_sys_clk_rate(const char *id)
405 */
406struct clk *clk_get(struct device *dev, const char *id)
407{ 458{
408 if (!strcmp(id, "ref")) 459 struct clk *clk;
409 return &ath79_ref_clk; 460 unsigned long rate;
410
411 if (!strcmp(id, "cpu"))
412 return &ath79_cpu_clk;
413
414 if (!strcmp(id, "ddr"))
415 return &ath79_ddr_clk;
416
417 if (!strcmp(id, "ahb"))
418 return &ath79_ahb_clk;
419 461
420 if (!strcmp(id, "wdt")) 462 clk = clk_get(NULL, id);
421 return &ath79_wdt_clk; 463 if (IS_ERR(clk))
464 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
422 465
423 if (!strcmp(id, "uart")) 466 rate = clk_get_rate(clk);
424 return &ath79_uart_clk; 467 clk_put(clk);
425 468
426 return ERR_PTR(-ENOENT); 469 return rate;
427} 470}
428EXPORT_SYMBOL(clk_get);
429 471
472/*
473 * Linux clock API
474 */
430int clk_enable(struct clk *clk) 475int clk_enable(struct clk *clk)
431{ 476{
432 return 0; 477 return 0;
@@ -443,8 +488,3 @@ unsigned long clk_get_rate(struct clk *clk)
443 return clk->rate; 488 return clk->rate;
444} 489}
445EXPORT_SYMBOL(clk_get_rate); 490EXPORT_SYMBOL(clk_get_rate);
446
447void clk_put(struct clk *clk)
448{
449}
450EXPORT_SYMBOL(clk_put);
diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h
index 561906c2345e..648d2dafbc56 100644
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -21,6 +21,8 @@
21#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) 21#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
22 22
23void ath79_clocks_init(void); 23void ath79_clocks_init(void);
24unsigned long ath79_get_sys_clk_rate(const char *id);
25
24void ath79_ddr_wb_flush(unsigned int reg); 26void ath79_ddr_wb_flush(unsigned int reg);
25 27
26void ath79_gpio_function_enable(u32 mask); 28void ath79_gpio_function_enable(u32 mask);
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index a3a2741d0688..c3b04c929f29 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -81,21 +81,19 @@ static struct platform_device ar933x_uart_device = {
81 81
82void __init ath79_register_uart(void) 82void __init ath79_register_uart(void)
83{ 83{
84 struct clk *clk; 84 unsigned long uart_clk_rate;
85 85
86 clk = clk_get(NULL, "uart"); 86 uart_clk_rate = ath79_get_sys_clk_rate("uart");
87 if (IS_ERR(clk))
88 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
89 87
90 if (soc_is_ar71xx() || 88 if (soc_is_ar71xx() ||
91 soc_is_ar724x() || 89 soc_is_ar724x() ||
92 soc_is_ar913x() || 90 soc_is_ar913x() ||
93 soc_is_ar934x() || 91 soc_is_ar934x() ||
94 soc_is_qca955x()) { 92 soc_is_qca955x()) {
95 ath79_uart_data[0].uartclk = clk_get_rate(clk); 93 ath79_uart_data[0].uartclk = uart_clk_rate;
96 platform_device_register(&ath79_uart_device); 94 platform_device_register(&ath79_uart_device);
97 } else if (soc_is_ar933x()) { 95 } else if (soc_is_ar933x()) {
98 ar933x_uart_data.uartclk = clk_get_rate(clk); 96 ar933x_uart_data.uartclk = uart_clk_rate;
99 platform_device_register(&ar933x_uart_device); 97 platform_device_register(&ar933x_uart_device);
100 } else { 98 } else {
101 BUG(); 99 BUG();
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 80f4ecd42b0d..64807a4809d0 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -200,7 +200,6 @@ void __init plat_mem_setup(void)
200 200
201 ath79_detect_sys_type(); 201 ath79_detect_sys_type();
202 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); 202 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
203 ath79_clocks_init();
204 203
205 _machine_restart = ath79_restart; 204 _machine_restart = ath79_restart;
206 _machine_halt = ath79_halt; 205 _machine_halt = ath79_halt;
@@ -209,13 +208,25 @@ void __init plat_mem_setup(void)
209 208
210void __init plat_time_init(void) 209void __init plat_time_init(void)
211{ 210{
212 struct clk *clk; 211 unsigned long cpu_clk_rate;
212 unsigned long ahb_clk_rate;
213 unsigned long ddr_clk_rate;
214 unsigned long ref_clk_rate;
215
216 ath79_clocks_init();
217
218 cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
219 ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
220 ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
221 ref_clk_rate = ath79_get_sys_clk_rate("ref");
213 222
214 clk = clk_get(NULL, "cpu"); 223 pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz",
215 if (IS_ERR(clk)) 224 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
216 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); 225 ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
226 ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
227 ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
217 228
218 mips_hpt_frequency = clk_get_rate(clk) / 2; 229 mips_hpt_frequency = cpu_clk_rate / 2;
219} 230}
220 231
221static int __init ath79_setup(void) 232static int __init ath79_setup(void)
diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore
index f210b09ececc..a73d6e2c4f64 100644
--- a/arch/mips/boot/.gitignore
+++ b/arch/mips/boot/.gitignore
@@ -4,3 +4,4 @@ vmlinux.*
4zImage 4zImage
5zImage.tmp 5zImage.tmp
6calc_vmlinuz_load_addr 6calc_vmlinuz_load_addr
7uImage
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 851261e9fdc0..1466c0026093 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -40,3 +40,18 @@ quiet_cmd_srec = OBJCOPY $@
40 cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@ 40 cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
41$(obj)/vmlinux.srec: $(VMLINUX) FORCE 41$(obj)/vmlinux.srec: $(VMLINUX) FORCE
42 $(call if_changed,srec) 42 $(call if_changed,srec)
43
44UIMAGE_LOADADDR = $(VMLINUX_LOAD_ADDRESS)
45UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS)
46
47$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
48 $(call if_changed,gzip)
49
50targets += uImage.gz
51$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
52 $(call if_changed,uimage,gzip)
53
54targets += uImage
55$(obj)/uImage: $(obj)/uImage.gz FORCE
56 @ln -sf $(notdir $<) $@
57 @echo ' Image $@ is ready'
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index bb1dbf4abb9d..0048c0897896 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -25,7 +25,7 @@ KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
25 25
26KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ 26KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
27 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \ 27 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
28 -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) 28 -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
29 29
30targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o 30targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
31 31
diff --git a/arch/mips/boot/dts/include/dt-bindings b/arch/mips/boot/dts/include/dt-bindings
new file mode 120000
index 000000000000..68ae3887b3e5
--- /dev/null
+++ b/arch/mips/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
../../../../../include/dt-bindings
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 9d36774bded1..25fbfae06c1f 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1776,7 +1776,7 @@ asmlinkage void plat_irq_dispatch(void)
1776 1776
1777#ifdef CONFIG_HOTPLUG_CPU 1777#ifdef CONFIG_HOTPLUG_CPU
1778 1778
1779void fixup_irqs(void) 1779void octeon_fixup_irqs(void)
1780{ 1780{
1781 irq_cpu_offline(); 1781 irq_cpu_offline();
1782} 1782}
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 48b08eb9d9e4..b212ae12e5ac 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -8,6 +8,7 @@
8 * written by Ralf Baechle <ralf@linux-mips.org> 8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */ 9 */
10#include <linux/compiler.h> 10#include <linux/compiler.h>
11#include <linux/vmalloc.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
13#include <linux/console.h> 14#include <linux/console.h>
@@ -1139,3 +1140,30 @@ static int __init edac_devinit(void)
1139 return err; 1140 return err;
1140} 1141}
1141device_initcall(edac_devinit); 1142device_initcall(edac_devinit);
1143
1144static void __initdata *octeon_dummy_iospace;
1145
1146static int __init octeon_no_pci_init(void)
1147{
1148 /*
1149 * Initially assume there is no PCI. The PCI/PCIe platform code will
1150 * later re-initialize these to correct values if they are present.
1151 */
1152 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1153 set_io_port_base((unsigned long)octeon_dummy_iospace);
1154 ioport_resource.start = MAX_RESOURCE;
1155 ioport_resource.end = 0;
1156 return 0;
1157}
1158core_initcall(octeon_no_pci_init);
1159
1160static int __init octeon_no_pci_release(void)
1161{
1162 /*
1163 * Release the allocated memory if a real IO space is there.
1164 */
1165 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1166 vfree(octeon_dummy_iospace);
1167 return 0;
1168}
1169late_initcall(octeon_no_pci_release);
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 138cc80c5928..24a2167db778 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -255,8 +255,6 @@ static void octeon_cpus_done(void)
255/* State of each CPU. */ 255/* State of each CPU. */
256DEFINE_PER_CPU(int, cpu_state); 256DEFINE_PER_CPU(int, cpu_state);
257 257
258extern void fixup_irqs(void);
259
260static int octeon_cpu_disable(void) 258static int octeon_cpu_disable(void)
261{ 259{
262 unsigned int cpu = smp_processor_id(); 260 unsigned int cpu = smp_processor_id();
@@ -267,7 +265,7 @@ static int octeon_cpu_disable(void)
267 set_cpu_online(cpu, false); 265 set_cpu_online(cpu, false);
268 cpu_clear(cpu, cpu_callin_map); 266 cpu_clear(cpu, cpu_callin_map);
269 local_irq_disable(); 267 local_irq_disable();
270 fixup_irqs(); 268 octeon_fixup_irqs();
271 local_irq_enable(); 269 local_irq_enable();
272 270
273 flush_cache_all(); 271 flush_cache_all();
diff --git a/arch/mips/configs/xway_defconfig b/arch/mips/configs/xway_defconfig
new file mode 100644
index 000000000000..8987846240f7
--- /dev/null
+++ b/arch/mips/configs/xway_defconfig
@@ -0,0 +1,159 @@
1CONFIG_LANTIQ=y
2CONFIG_XRX200_PHY_FW=y
3CONFIG_CPU_MIPS32_R2=y
4# CONFIG_COMPACTION is not set
5# CONFIG_CROSS_MEMORY_ATTACH is not set
6CONFIG_HZ_100=y
7# CONFIG_SECCOMP is not set
8# CONFIG_LOCALVERSION_AUTO is not set
9CONFIG_SYSVIPC=y
10CONFIG_HIGH_RES_TIMERS=y
11CONFIG_BLK_DEV_INITRD=y
12# CONFIG_RD_GZIP is not set
13CONFIG_CC_OPTIMIZE_FOR_SIZE=y
14CONFIG_KALLSYMS_ALL=y
15# CONFIG_AIO is not set
16CONFIG_EMBEDDED=y
17# CONFIG_VM_EVENT_COUNTERS is not set
18# CONFIG_SLUB_DEBUG is not set
19# CONFIG_COMPAT_BRK is not set
20CONFIG_MODULES=y
21CONFIG_MODULE_UNLOAD=y
22# CONFIG_BLK_DEV_BSG is not set
23CONFIG_PARTITION_ADVANCED=y
24# CONFIG_IOSCHED_CFQ is not set
25# CONFIG_COREDUMP is not set
26# CONFIG_SUSPEND is not set
27CONFIG_NET=y
28CONFIG_PACKET=y
29CONFIG_UNIX=y
30CONFIG_INET=y
31CONFIG_IP_MULTICAST=y
32CONFIG_IP_ADVANCED_ROUTER=y
33CONFIG_IP_MULTIPLE_TABLES=y
34CONFIG_IP_ROUTE_MULTIPATH=y
35CONFIG_IP_ROUTE_VERBOSE=y
36CONFIG_IP_MROUTE=y
37CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
38CONFIG_ARPD=y
39CONFIG_SYN_COOKIES=y
40# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
41# CONFIG_INET_XFRM_MODE_TUNNEL is not set
42# CONFIG_INET_XFRM_MODE_BEET is not set
43# CONFIG_INET_LRO is not set
44# CONFIG_INET_DIAG is not set
45CONFIG_TCP_CONG_ADVANCED=y
46# CONFIG_TCP_CONG_BIC is not set
47# CONFIG_TCP_CONG_WESTWOOD is not set
48# CONFIG_TCP_CONG_HTCP is not set
49# CONFIG_IPV6 is not set
50CONFIG_NETFILTER=y
51# CONFIG_BRIDGE_NETFILTER is not set
52CONFIG_NF_CONNTRACK=m
53CONFIG_NF_CONNTRACK_FTP=m
54CONFIG_NF_CONNTRACK_IRC=m
55CONFIG_NETFILTER_XT_TARGET_CT=m
56CONFIG_NETFILTER_XT_TARGET_LOG=m
57CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
58CONFIG_NETFILTER_XT_MATCH_COMMENT=m
59CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
60CONFIG_NETFILTER_XT_MATCH_LIMIT=m
61CONFIG_NETFILTER_XT_MATCH_MAC=m
62CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
63CONFIG_NETFILTER_XT_MATCH_STATE=m
64CONFIG_NF_CONNTRACK_IPV4=m
65# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
66CONFIG_IP_NF_IPTABLES=m
67CONFIG_IP_NF_FILTER=m
68CONFIG_IP_NF_TARGET_REJECT=m
69CONFIG_IP_NF_MANGLE=m
70CONFIG_IP_NF_RAW=m
71CONFIG_BRIDGE=y
72# CONFIG_BRIDGE_IGMP_SNOOPING is not set
73CONFIG_VLAN_8021Q=y
74CONFIG_NET_SCHED=y
75CONFIG_HAMRADIO=y
76CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
77# CONFIG_FIRMWARE_IN_KERNEL is not set
78CONFIG_MTD=y
79CONFIG_MTD_CMDLINE_PARTS=y
80CONFIG_MTD_BLOCK=y
81CONFIG_MTD_CFI=y
82CONFIG_MTD_CFI_AMDSTD=y
83CONFIG_MTD_COMPLEX_MAPPINGS=y
84CONFIG_MTD_PHYSMAP=y
85CONFIG_MTD_PHYSMAP_OF=y
86CONFIG_MTD_LANTIQ=y
87CONFIG_EEPROM_93CX6=m
88CONFIG_SCSI=y
89CONFIG_BLK_DEV_SD=y
90CONFIG_NETDEVICES=y
91CONFIG_LANTIQ_ETOP=y
92# CONFIG_NET_VENDOR_WIZNET is not set
93CONFIG_PHYLIB=y
94CONFIG_PPP=m
95CONFIG_PPP_FILTER=y
96CONFIG_PPP_MULTILINK=y
97CONFIG_PPPOE=m
98CONFIG_PPP_ASYNC=m
99CONFIG_ISDN=y
100CONFIG_INPUT=m
101CONFIG_INPUT_POLLDEV=m
102# CONFIG_INPUT_MOUSEDEV is not set
103# CONFIG_KEYBOARD_ATKBD is not set
104# CONFIG_INPUT_MOUSE is not set
105CONFIG_INPUT_MISC=y
106# CONFIG_SERIO is not set
107# CONFIG_VT is not set
108# CONFIG_LEGACY_PTYS is not set
109# CONFIG_DEVKMEM is not set
110CONFIG_SERIAL_8250=y
111CONFIG_SERIAL_8250_CONSOLE=y
112CONFIG_SERIAL_8250_RUNTIME_UARTS=2
113CONFIG_SERIAL_OF_PLATFORM=y
114CONFIG_SPI=y
115CONFIG_GPIO_MM_LANTIQ=y
116CONFIG_GPIO_STP_XWAY=y
117# CONFIG_HWMON is not set
118CONFIG_WATCHDOG=y
119# CONFIG_HID is not set
120# CONFIG_USB_HID is not set
121CONFIG_USB=y
122CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
123CONFIG_USB_STORAGE=y
124CONFIG_USB_STORAGE_DEBUG=y
125CONFIG_NEW_LEDS=y
126CONFIG_LEDS_CLASS=y
127CONFIG_LEDS_TRIGGERS=y
128CONFIG_LEDS_TRIGGER_TIMER=y
129CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
130CONFIG_STAGING=y
131# CONFIG_IOMMU_SUPPORT is not set
132# CONFIG_DNOTIFY is not set
133# CONFIG_PROC_PAGE_MONITOR is not set
134CONFIG_TMPFS=y
135CONFIG_TMPFS_XATTR=y
136CONFIG_JFFS2_FS=y
137CONFIG_JFFS2_SUMMARY=y
138CONFIG_JFFS2_FS_XATTR=y
139# CONFIG_JFFS2_FS_POSIX_ACL is not set
140# CONFIG_JFFS2_FS_SECURITY is not set
141CONFIG_JFFS2_COMPRESSION_OPTIONS=y
142# CONFIG_JFFS2_ZLIB is not set
143CONFIG_SQUASHFS=y
144# CONFIG_SQUASHFS_ZLIB is not set
145CONFIG_SQUASHFS_XZ=y
146CONFIG_PRINTK_TIME=y
147# CONFIG_ENABLE_MUST_CHECK is not set
148CONFIG_STRIP_ASM_SYMS=y
149CONFIG_DEBUG_FS=y
150CONFIG_MAGIC_SYSRQ=y
151# CONFIG_SCHED_DEBUG is not set
152# CONFIG_FTRACE is not set
153CONFIG_CMDLINE_BOOL=y
154CONFIG_CRYPTO_MANAGER=m
155CONFIG_CRYPTO_ARC4=m
156# CONFIG_CRYPTO_ANSI_CPRNG is not set
157CONFIG_CRC_ITU_T=m
158CONFIG_CRC32_SARWATE=y
159CONFIG_AVERAGE=y
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index ea57f39e6736..56ebc7f2bede 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -126,12 +126,13 @@ int rtc_mips_set_mmss(unsigned long nowtime)
126void __init plat_time_init(void) 126void __init plat_time_init(void)
127{ 127{
128 u32 start, end; 128 u32 start, end;
129 int i = HZ / 10; 129 int i = HZ / 8;
130 130
131 /* Set up the rate of periodic DS1287 interrupts. */ 131 /* Set up the rate of periodic DS1287 interrupts. */
132 ds1287_set_base_clock(HZ); 132 ds1287_set_base_clock(HZ);
133 133
134 if (cpu_has_counter) { 134 if (cpu_has_counter) {
135 ds1287_timer_state();
135 while (!ds1287_timer_state()) 136 while (!ds1287_timer_state())
136 ; 137 ;
137 138
@@ -143,7 +144,7 @@ void __init plat_time_init(void)
143 144
144 end = read_c0_count(); 145 end = read_c0_count();
145 146
146 mips_hpt_frequency = (end - start) * 10; 147 mips_hpt_frequency = (end - start) * 8;
147 printk(KERN_INFO "MIPS counter frequency %dHz\n", 148 printk(KERN_INFO "MIPS counter frequency %dHz\n",
148 mips_hpt_frequency); 149 mips_hpt_frequency);
149 } else if (IOASIC) 150 } else if (IOASIC)
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 9b54b7a403d4..454ddf9bb76f 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -1,2 +1,15 @@
1# MIPS headers 1# MIPS headers
2generic-y += cputime.h
3generic-y += current.h
4generic-y += emergency-restart.h
5generic-y += local64.h
6generic-y += mutex.h
7generic-y += parport.h
8generic-y += percpu.h
9generic-y += scatterlist.h
10generic-y += sections.h
11generic-y += segment.h
12generic-y += serial.h
2generic-y += trace_clock.h 13generic-y += trace_clock.h
14generic-y += ucontext.h
15generic-y += xor.h
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 552a65a0cf2b..27bd060d716e 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -65,44 +65,33 @@ static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
65{ 65{
66 unsigned long ret; 66 unsigned long ret;
67 67
68 __asm__ __volatile__( 68 barrier();
69 ".set push\n" 69 cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
70 ".set noreorder\n" 70 __sync();
71 "cache %1, 0(%2)\n" 71 _ssnop();
72 "sync\n" 72 _ssnop();
73 "_ssnop\n" 73 _ssnop();
74 "_ssnop\n" 74 _ssnop();
75 "_ssnop\n" 75 _ssnop();
76 "_ssnop\n" 76 _ssnop();
77 "_ssnop\n" 77 _ssnop();
78 "_ssnop\n" 78 ret = read_c0_ddatalo();
79 "_ssnop\n" 79 _ssnop();
80 "mfc0 %0, $28, 3\n" 80
81 "_ssnop\n"
82 ".set pop\n"
83 : "=&r" (ret)
84 : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
85 : "memory");
86 return ret; 81 return ret;
87} 82}
88 83
89static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data) 84static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
90{ 85{
91 __asm__ __volatile__( 86 write_c0_ddatalo(data);
92 ".set push\n" 87 _ssnop();
93 ".set noreorder\n" 88 _ssnop();
94 "mtc0 %0, $28, 3\n" 89 _ssnop();
95 "_ssnop\n" 90 cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
96 "_ssnop\n" 91 _ssnop();
97 "_ssnop\n" 92 _ssnop();
98 "cache %1, 0(%2)\n" 93 _ssnop();
99 "_ssnop\n" 94 barrier();
100 "_ssnop\n"
101 "_ssnop\n"
102 : /* no outputs */
103 : "r" (data),
104 "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
105 : "memory");
106} 95}
107 96
108#endif /* !defined(__ASSEMBLY__) */ 97#endif /* !defined(__ASSEMBLY__) */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 632bbe5a79ea..71b9f1998be7 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -141,6 +141,9 @@
141#define PRID_IMP_CAVIUM_CN68XX 0x9100 141#define PRID_IMP_CAVIUM_CN68XX 0x9100
142#define PRID_IMP_CAVIUM_CN66XX 0x9200 142#define PRID_IMP_CAVIUM_CN66XX 0x9200
143#define PRID_IMP_CAVIUM_CN61XX 0x9300 143#define PRID_IMP_CAVIUM_CN61XX 0x9300
144#define PRID_IMP_CAVIUM_CNF71XX 0x9400
145#define PRID_IMP_CAVIUM_CN78XX 0x9500
146#define PRID_IMP_CAVIUM_CN70XX 0x9600
144 147
145/* 148/*
146 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC 149 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -176,6 +179,7 @@
176 179
177#define PRID_IMP_NETLOGIC_XLP8XX 0x1000 180#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
178#define PRID_IMP_NETLOGIC_XLP3XX 0x1100 181#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
182#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
179 183
180/* 184/*
181 * Definitions for 7:0 on legacy processors 185 * Definitions for 7:0 on legacy processors
@@ -272,7 +276,7 @@ enum cpu_type_enum {
272 */ 276 */
273 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 277 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
274 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 278 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
275 CPU_XLR, CPU_XLP, 279 CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
276 280
277 CPU_LAST 281 CPU_LAST
278}; 282};
diff --git a/arch/mips/include/asm/cputime.h b/arch/mips/include/asm/cputime.h
deleted file mode 100644
index c00eacbdd979..000000000000
--- a/arch/mips/include/asm/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __MIPS_CPUTIME_H
2#define __MIPS_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __MIPS_CPUTIME_H */
diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h
deleted file mode 100644
index 4c51401b5537..000000000000
--- a/arch/mips/include/asm/current.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/current.h>
diff --git a/arch/mips/include/asm/emergency-restart.h b/arch/mips/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/arch/mips/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/mips/include/asm/local64.h b/arch/mips/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/mips/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local64.h>
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
index ddb947e9221f..0089a740e5ae 100644
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -42,8 +42,6 @@
42#define cpu_has_mips64r1 0 42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0 43#define cpu_has_mips64r2 0
44 44
45#define cpu_has_dsp 0
46#define cpu_has_dsp2 0
47#define cpu_has_mipsmt 0 45#define cpu_has_mipsmt 0
48 46
49#define cpu_has_64bits 0 47#define cpu_has_64bits 0
diff --git a/arch/mips/include/asm/mach-cavium-octeon/gpio.h b/arch/mips/include/asm/mach-cavium-octeon/gpio.h
new file mode 100644
index 000000000000..34e9f7aabab4
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/gpio.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H
2#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H
3
4#ifdef CONFIG_GPIOLIB
5#define gpio_get_value __gpio_get_value
6#define gpio_set_value __gpio_set_value
7#define gpio_cansleep __gpio_cansleep
8#else
9int gpio_request(unsigned gpio, const char *label);
10void gpio_free(unsigned gpio);
11int gpio_direction_input(unsigned gpio);
12int gpio_direction_output(unsigned gpio, int value);
13int gpio_get_value(unsigned gpio);
14void gpio_set_value(unsigned gpio, int value);
15#endif
16
17#include <asm-generic/gpio.h>
18
19#define gpio_to_irq __gpio_to_irq
20
21#endif /* __ASM_MACH_GENERIC_GPIO_H */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
new file mode 100644
index 000000000000..096a10072430
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
@@ -0,0 +1,58 @@
1/*
2 * Lantiq FALCON specific CPU feature overrides
3 *
4 * Copyright (C) 2013 Thomas Langer, Lantiq Deutschland
5 *
6 * This file was derived from: include/asm-mips/cpu-features.h
7 * Copyright (C) 2003, 2004 Ralf Baechle
8 * Copyright (C) 2004 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
16#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
17
18#define cpu_has_tlb 1
19#define cpu_has_4kex 1
20#define cpu_has_3k_cache 0
21#define cpu_has_4k_cache 1
22#define cpu_has_tx39_cache 0
23#define cpu_has_sb1_cache 0
24#define cpu_has_fpu 0
25#define cpu_has_32fpr 0
26#define cpu_has_counter 1
27#define cpu_has_watch 1
28#define cpu_has_divec 1
29
30#define cpu_has_prefetch 1
31#define cpu_has_ejtag 1
32#define cpu_has_llsc 1
33
34#define cpu_has_mips16 1
35#define cpu_has_mdmx 0
36#define cpu_has_mips3d 0
37#define cpu_has_smartmips 0
38
39#define cpu_has_mips32r1 1
40#define cpu_has_mips32r2 1
41#define cpu_has_mips64r1 0
42#define cpu_has_mips64r2 0
43
44#define cpu_has_dsp 1
45#define cpu_has_mipsmt 1
46
47#define cpu_has_vint 1
48#define cpu_has_veic 1
49
50#define cpu_has_64bits 0
51#define cpu_has_64bit_zero_reg 0
52#define cpu_has_64bit_gp_regs 0
53#define cpu_has_64bit_addresses 0
54
55#define cpu_dcache_line_size() 32
56#define cpu_icache_line_size() 32
57
58#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 9809972ea882..6f9b24f51157 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -20,6 +20,8 @@
20#define SYSC_REG_CHIP_REV 0x0c 20#define SYSC_REG_CHIP_REV 0x0c
21#define SYSC_REG_SYSTEM_CONFIG0 0x10 21#define SYSC_REG_SYSTEM_CONFIG0 0x10
22#define SYSC_REG_SYSTEM_CONFIG1 0x14 22#define SYSC_REG_SYSTEM_CONFIG1 0x14
23#define SYSC_REG_CLKCFG0 0x2c
24#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
23#define SYSC_REG_CPLL_CONFIG0 0x54 25#define SYSC_REG_CPLL_CONFIG0 0x54
24#define SYSC_REG_CPLL_CONFIG1 0x58 26#define SYSC_REG_CPLL_CONFIG1 0x58
25 27
@@ -29,20 +31,42 @@
29#define MT7620A_CHIP_NAME0 0x3637544d 31#define MT7620A_CHIP_NAME0 0x3637544d
30#define MT7620A_CHIP_NAME1 0x20203032 32#define MT7620A_CHIP_NAME1 0x20203032
31 33
34#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
35
32#define CHIP_REV_PKG_MASK 0x1 36#define CHIP_REV_PKG_MASK 0x1
33#define CHIP_REV_PKG_SHIFT 16 37#define CHIP_REV_PKG_SHIFT 16
34#define CHIP_REV_VER_MASK 0xf 38#define CHIP_REV_VER_MASK 0xf
35#define CHIP_REV_VER_SHIFT 8 39#define CHIP_REV_VER_SHIFT 8
36#define CHIP_REV_ECO_MASK 0xf 40#define CHIP_REV_ECO_MASK 0xf
37 41
38#define CPLL_SW_CONFIG_SHIFT 31 42#define CLKCFG0_PERI_CLK_SEL BIT(4)
39#define CPLL_SW_CONFIG_MASK 0x1 43
40#define CPLL_CPU_CLK_SHIFT 24 44#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
41#define CPLL_CPU_CLK_MASK 0x1 45#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
42#define CPLL_MULT_RATIO_SHIFT 16 46#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
43#define CPLL_MULT_RATIO 0x7 47#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
44#define CPLL_DIV_RATIO_SHIFT 10 48#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
45#define CPLL_DIV_RATIO 0x3 49#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
50#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
51#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
52#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
53#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
54#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
55#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
56#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
57#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
58#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
59
60#define CPLL_CFG0_SW_CFG BIT(31)
61#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
62#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
63#define CPLL_CFG0_LC_CURFCK BIT(15)
64#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
65#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
66#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
67
68#define CPLL_CFG1_CPU_AUX1 BIT(25)
69#define CPLL_CFG1_CPU_AUX0 BIT(24)
46 70
47#define SYSCFG0_DRAM_TYPE_MASK 0x3 71#define SYSCFG0_DRAM_TYPE_MASK 0x3
48#define SYSCFG0_DRAM_TYPE_SHIFT 4 72#define SYSCFG0_DRAM_TYPE_SHIFT 4
diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f7bb8cfc5eb1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
@@ -0,0 +1,57 @@
1/*
2 * Ralink MT7620 specific CPU feature overrides
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This file was derived from: include/asm-mips/cpu-features.h
8 * Copyright (C) 2003, 2004 Ralf Baechle
9 * Copyright (C) 2004 Maciej W. Rozycki
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 *
15 */
16#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H
17#define _MT7620_CPU_FEATURE_OVERRIDES_H
18
19#define cpu_has_tlb 1
20#define cpu_has_4kex 1
21#define cpu_has_3k_cache 0
22#define cpu_has_4k_cache 1
23#define cpu_has_tx39_cache 0
24#define cpu_has_sb1_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_32fpr 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30
31#define cpu_has_prefetch 1
32#define cpu_has_ejtag 1
33#define cpu_has_llsc 1
34
35#define cpu_has_mips16 1
36#define cpu_has_mdmx 0
37#define cpu_has_mips3d 0
38#define cpu_has_smartmips 0
39
40#define cpu_has_mips32r1 1
41#define cpu_has_mips32r2 1
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
45#define cpu_has_dsp 1
46#define cpu_has_dsp2 0
47#define cpu_has_mipsmt 0
48
49#define cpu_has_64bits 0
50#define cpu_has_64bit_zero_reg 0
51#define cpu_has_64bit_gp_regs 0
52#define cpu_has_64bit_addresses 0
53
54#define cpu_dcache_line_size() 32
55#define cpu_icache_line_size() 32
56
57#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mutex.h b/arch/mips/include/asm/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/arch/mips/include/asm/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index 790f0f1e55c6..4e8eacb9588a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -88,6 +88,7 @@
88#define BRIDGE_DRAM_LIMIT6 0x22 88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23 89#define BRIDGE_DRAM_LIMIT7 0x23
90 90
91#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
91#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 92#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 93#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 94#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
@@ -96,6 +97,8 @@
96#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 97#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 98#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 99#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
100
101#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
99#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 102#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 103#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 104#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
@@ -104,6 +107,7 @@
104#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 107#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 108#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 109#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
110
107#define BRIDGE_PCIEMEM_BASE0 0x34 111#define BRIDGE_PCIEMEM_BASE0 0x34
108#define BRIDGE_PCIEMEM_BASE1 0x35 112#define BRIDGE_PCIEMEM_BASE1 0x35
109#define BRIDGE_PCIEMEM_BASE2 0x36 113#define BRIDGE_PCIEMEM_BASE2 0x36
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 9fac46fb7913..55eee77adaca 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -72,6 +72,12 @@
72#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) 72#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
73#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) 73#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
74 74
75/* XLP2xx has an updated USB block */
76#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i)
77#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1)
78#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2)
79#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3)
80
75#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) 81#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
76#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) 82#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
77 83
@@ -88,6 +94,9 @@
88#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) 94#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
89#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) 95#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
90#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) 96#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
97/* on 2XX, all I2C busses are on the same block */
98#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7)
99
91/* system management */ 100/* system management */
92#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) 101#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
93#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) 102#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
@@ -145,6 +154,7 @@
145#define PCI_DEVICE_ID_NLM_NOR 0x1015 154#define PCI_DEVICE_ID_NLM_NOR 0x1015
146#define PCI_DEVICE_ID_NLM_NAND 0x1016 155#define PCI_DEVICE_ID_NLM_NAND 0x1016
147#define PCI_DEVICE_ID_NLM_MMC 0x1018 156#define PCI_DEVICE_ID_NLM_MMC 0x1018
157#define PCI_DEVICE_ID_NLM_XHCI 0x101d
148 158
149#ifndef __ASSEMBLY__ 159#ifndef __ASSEMBLY__
150 160
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 4b5108dfaa16..105389b79f09 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -208,13 +208,14 @@
208#define PIC_LOCAL_SCHEDULING 1 208#define PIC_LOCAL_SCHEDULING 1
209#define PIC_GLOBAL_SCHEDULING 0 209#define PIC_GLOBAL_SCHEDULING 0
210 210
211#define PIC_CLK_HZ 133333333
212
213#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 211#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
214#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 212#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
215#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 213#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
216#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 214#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
217 215
216/* We use PIC on node 0 as a timer */
217#define pic_timer_freq() nlm_get_pic_frequency(0)
218
218/* IRT and h/w interrupt routines */ 219/* IRT and h/w interrupt routines */
219static inline int 220static inline int
220nlm_pic_read_irt(uint64_t base, int irt_index) 221nlm_pic_read_irt(uint64_t base, int irt_index)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index 470e52bfc061..fcf2833c16ca 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -117,6 +117,36 @@
117#define SYS_SCRTCH2 0x4b 117#define SYS_SCRTCH2 0x4b
118#define SYS_SCRTCH3 0x4c 118#define SYS_SCRTCH3 0x4c
119 119
120/* PLL registers XLP2XX */
121#define SYS_PLL_CTRL0 0x240
122#define SYS_PLL_CTRL1 0x241
123#define SYS_PLL_CTRL2 0x242
124#define SYS_PLL_CTRL3 0x243
125#define SYS_DMC_PLL_CTRL0 0x244
126#define SYS_DMC_PLL_CTRL1 0x245
127#define SYS_DMC_PLL_CTRL2 0x246
128#define SYS_DMC_PLL_CTRL3 0x247
129
130#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4)
131#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4)
132#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4)
133#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4)
134
135#define SYS_CPU_PLL_CHG_CTRL 0x288
136#define SYS_PLL_CHG_CTRL 0x289
137#define SYS_CLK_DEV_DIS 0x28a
138#define SYS_CLK_DEV_SEL 0x28b
139#define SYS_CLK_DEV_DIV 0x28c
140#define SYS_CLK_DEV_CHG 0x28d
141#define SYS_CLK_DEV_SEL_REG 0x28e
142#define SYS_CLK_DEV_DIV_REG 0x28f
143#define SYS_CPU_PLL_LOCK 0x29f
144#define SYS_SYS_PLL_LOCK 0x2a0
145#define SYS_PLL_MEM_CMD 0x2a1
146#define SYS_CPU_PLL_MEM_REQ 0x2a2
147#define SYS_SYS_PLL_MEM_REQ 0x2a3
148#define SYS_PLL_MEM_STAT 0x2a4
149
120#ifndef __ASSEMBLY__ 150#ifndef __ASSEMBLY__
121 151
122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 152#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
@@ -124,5 +154,6 @@
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 154#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 155#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126 156
157unsigned int nlm_get_pic_frequency(int node);
127#endif 158#endif
128#endif 159#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index f4ea0f7f3965..17daffb280a3 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -41,15 +41,22 @@
41#define PIC_PCIE_LINK_1_IRQ 20 41#define PIC_PCIE_LINK_1_IRQ 20
42#define PIC_PCIE_LINK_2_IRQ 21 42#define PIC_PCIE_LINK_2_IRQ 21
43#define PIC_PCIE_LINK_3_IRQ 22 43#define PIC_PCIE_LINK_3_IRQ 22
44
44#define PIC_EHCI_0_IRQ 23 45#define PIC_EHCI_0_IRQ 23
45#define PIC_EHCI_1_IRQ 24 46#define PIC_EHCI_1_IRQ 24
46#define PIC_OHCI_0_IRQ 25 47#define PIC_OHCI_0_IRQ 25
47#define PIC_OHCI_1_IRQ 26 48#define PIC_OHCI_1_IRQ 26
48#define PIC_OHCI_2_IRQ 27 49#define PIC_OHCI_2_IRQ 27
49#define PIC_OHCI_3_IRQ 28 50#define PIC_OHCI_3_IRQ 28
51#define PIC_2XX_XHCI_0_IRQ 23
52#define PIC_2XX_XHCI_1_IRQ 24
53#define PIC_2XX_XHCI_2_IRQ 25
54
50#define PIC_MMC_IRQ 29 55#define PIC_MMC_IRQ 29
51#define PIC_I2C_0_IRQ 30 56#define PIC_I2C_0_IRQ 30
52#define PIC_I2C_1_IRQ 31 57#define PIC_I2C_1_IRQ 31
58#define PIC_I2C_2_IRQ 32
59#define PIC_I2C_3_IRQ 33
53 60
54#ifndef __ASSEMBLY__ 61#ifndef __ASSEMBLY__
55 62
@@ -59,7 +66,17 @@ void xlp_wakeup_secondary_cpus(void);
59 66
60void xlp_mmu_init(void); 67void xlp_mmu_init(void);
61void nlm_hal_init(void); 68void nlm_hal_init(void);
69int xlp_get_dram_map(int n, uint64_t *dram_map);
70
71/* Device tree related */
62void *xlp_dt_init(void *fdtp); 72void *xlp_dt_init(void *fdtp);
63 73
74static inline int cpu_is_xlpii(void)
75{
76 int chip = read_c0_prid() & 0xff00;
77
78 return chip == PRID_IMP_NETLOGIC_XLP2XX;
79}
80
64#endif /* !__ASSEMBLY__ */ 81#endif /* !__ASSEMBLY__ */
65#endif /* _ASM_NLM_XLP_H */ 82#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 63c99176dffe..3c80a75233bd 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -36,6 +36,8 @@
36#define _ASM_NLM_XLR_PIC_H 36#define _ASM_NLM_XLR_PIC_H
37 37
38#define PIC_CLK_HZ 66666666 38#define PIC_CLK_HZ 66666666
39#define pic_timer_freq() PIC_CLK_HZ
40
39/* PIC hardware interrupt numbers */ 41/* PIC hardware interrupt numbers */
40#define PIC_IRT_WD_INDEX 0 42#define PIC_IRT_WD_INDEX 0
41#define PIC_IRT_TIMER_0_INDEX 1 43#define PIC_IRT_TIMER_0_INDEX 1
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index a2eed23c49a9..f5d77b91537f 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -251,4 +251,6 @@ extern void (*octeon_irq_setup_secondary)(void);
251typedef void (*octeon_irq_ip4_handler_t)(void); 251typedef void (*octeon_irq_ip4_handler_t)(void);
252void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); 252void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
253 253
254extern void octeon_fixup_irqs(void);
255
254#endif /* __ASM_OCTEON_OCTEON_H */ 256#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h
deleted file mode 100644
index cf252af64590..000000000000
--- a/arch/mips/include/asm/parport.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/parport.h>
diff --git a/arch/mips/include/asm/percpu.h b/arch/mips/include/asm/percpu.h
deleted file mode 100644
index 844e763e9332..000000000000
--- a/arch/mips/include/asm/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_PERCPU_H
2#define __ASM_PERCPU_H
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ASM_PERCPU_H */
diff --git a/arch/mips/include/asm/scatterlist.h b/arch/mips/include/asm/scatterlist.h
deleted file mode 100644
index 7ee0e646d82c..000000000000
--- a/arch/mips/include/asm/scatterlist.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SCATTERLIST_H
2#define __ASM_SCATTERLIST_H
3
4#include <asm-generic/scatterlist.h>
5
6#endif /* __ASM_SCATTERLIST_H */
diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h
deleted file mode 100644
index b7e37262c246..000000000000
--- a/arch/mips/include/asm/sections.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_SECTIONS_H
2#define _ASM_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6#endif /* _ASM_SECTIONS_H */
diff --git a/arch/mips/include/asm/segment.h b/arch/mips/include/asm/segment.h
deleted file mode 100644
index 92ac001fc483..000000000000
--- a/arch/mips/include/asm/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_SEGMENT_H
2#define _ASM_SEGMENT_H
3
4/* Only here because we have some old header files that expect it.. */
5
6#endif /* _ASM_SEGMENT_H */
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
deleted file mode 100644
index a0cb0caff152..000000000000
--- a/arch/mips/include/asm/serial.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/serial.h>
diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h
deleted file mode 100644
index 9bc07b9f30fb..000000000000
--- a/arch/mips/include/asm/ucontext.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ucontext.h>
diff --git a/arch/mips/include/asm/xor.h b/arch/mips/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/mips/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/xor.h>
diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild
index 350ccccadcb9..be7196eacb88 100644
--- a/arch/mips/include/uapi/asm/Kbuild
+++ b/arch/mips/include/uapi/asm/Kbuild
@@ -1,7 +1,9 @@
1# UAPI Header export list 1# UAPI Header export list
2include include/uapi/asm-generic/Kbuild.asm 2include include/uapi/asm-generic/Kbuild.asm
3 3
4header-y += auxvec.h 4generic-y += auxvec.h
5generic-y += ipcbuf.h
6
5header-y += bitsperlong.h 7header-y += bitsperlong.h
6header-y += break.h 8header-y += break.h
7header-y += byteorder.h 9header-y += byteorder.h
@@ -11,7 +13,6 @@ header-y += fcntl.h
11header-y += inst.h 13header-y += inst.h
12header-y += ioctl.h 14header-y += ioctl.h
13header-y += ioctls.h 15header-y += ioctls.h
14header-y += ipcbuf.h
15header-y += kvm_para.h 16header-y += kvm_para.h
16header-y += mman.h 17header-y += mman.h
17header-y += msgbuf.h 18header-y += msgbuf.h
diff --git a/arch/mips/include/uapi/asm/auxvec.h b/arch/mips/include/uapi/asm/auxvec.h
deleted file mode 100644
index 7cf7f2d21943..000000000000
--- a/arch/mips/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef _ASM_AUXVEC_H
2#define _ASM_AUXVEC_H
3
4#endif /* _ASM_AUXVEC_H */
diff --git a/arch/mips/include/uapi/asm/ipcbuf.h b/arch/mips/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/mips/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ipcbuf.h>
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 4c6167a17875..37663c7862a5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -852,10 +852,17 @@ platform:
852 case PRID_IMP_CAVIUM_CN63XX: 852 case PRID_IMP_CAVIUM_CN63XX:
853 case PRID_IMP_CAVIUM_CN66XX: 853 case PRID_IMP_CAVIUM_CN66XX:
854 case PRID_IMP_CAVIUM_CN68XX: 854 case PRID_IMP_CAVIUM_CN68XX:
855 case PRID_IMP_CAVIUM_CNF71XX:
855 c->cputype = CPU_CAVIUM_OCTEON2; 856 c->cputype = CPU_CAVIUM_OCTEON2;
856 __cpu_name[cpu] = "Cavium Octeon II"; 857 __cpu_name[cpu] = "Cavium Octeon II";
857 set_elf_platform(cpu, "octeon2"); 858 set_elf_platform(cpu, "octeon2");
858 break; 859 break;
860 case PRID_IMP_CAVIUM_CN70XX:
861 case PRID_IMP_CAVIUM_CN78XX:
862 c->cputype = CPU_CAVIUM_OCTEON3;
863 __cpu_name[cpu] = "Cavium Octeon III";
864 set_elf_platform(cpu, "octeon3");
865 break;
859 default: 866 default:
860 printk(KERN_INFO "Unknown Octeon chip!\n"); 867 printk(KERN_INFO "Unknown Octeon chip!\n");
861 c->cputype = CPU_UNKNOWN; 868 c->cputype = CPU_UNKNOWN;
@@ -899,6 +906,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
899 MIPS_CPU_LLSC); 906 MIPS_CPU_LLSC);
900 907
901 switch (c->processor_id & 0xff00) { 908 switch (c->processor_id & 0xff00) {
909 case PRID_IMP_NETLOGIC_XLP2XX:
910 c->cputype = CPU_XLP;
911 __cpu_name[cpu] = "Broadcom XLPII";
912 break;
913
902 case PRID_IMP_NETLOGIC_XLP8XX: 914 case PRID_IMP_NETLOGIC_XLP8XX:
903 case PRID_IMP_NETLOGIC_XLP3XX: 915 case PRID_IMP_NETLOGIC_XLP3XX:
904 c->cputype = CPU_XLP; 916 c->cputype = CPU_XLP;
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 0654bff9b69c..87e88feb4a25 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -41,9 +41,9 @@ void __init dec_ioasic_clocksource_init(void)
41{ 41{
42 unsigned int freq; 42 unsigned int freq;
43 u32 start, end; 43 u32 start, end;
44 int i = HZ / 10; 44 int i = HZ / 8;
45
46 45
46 ds1287_timer_state();
47 while (!ds1287_timer_state()) 47 while (!ds1287_timer_state())
48 ; 48 ;
49 49
@@ -55,7 +55,7 @@ void __init dec_ioasic_clocksource_init(void)
55 55
56 end = dec_ioasic_hpt_read(&clocksource_dec); 56 end = dec_ioasic_hpt_read(&clocksource_dec);
57 57
58 freq = (end - start) * 10; 58 freq = (end - start) * 8;
59 printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq); 59 printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
60 60
61 clocksource_dec.rating = 200 + freq / 10000000; 61 clocksource_dec.rating = 200 + freq / 10000000;
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 0c655deeea4a..42f8875d2444 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -166,6 +166,7 @@ void __init check_wait(void)
166 case CPU_CAVIUM_OCTEON: 166 case CPU_CAVIUM_OCTEON:
167 case CPU_CAVIUM_OCTEON_PLUS: 167 case CPU_CAVIUM_OCTEON_PLUS:
168 case CPU_CAVIUM_OCTEON2: 168 case CPU_CAVIUM_OCTEON2:
169 case CPU_CAVIUM_OCTEON3:
169 case CPU_JZRISC: 170 case CPU_JZRISC:
170 case CPU_LOONGSON1: 171 case CPU_LOONGSON1:
171 case CPU_XLR: 172 case CPU_XLR:
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index a03e93c4a946..539b6294b613 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -83,7 +83,7 @@ _mcount:
83 PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) 83 PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp)
84#endif 84#endif
85 85
86 move a0, ra /* arg1: self return address */ 86 PTR_SUBU a0, ra, 8 /* arg1: self address */
87 .globl ftrace_call 87 .globl ftrace_call
88ftrace_call: 88ftrace_call:
89 nop /* a placeholder for the call to a real tracing function */ 89 nop /* a placeholder for the call to a real tracing function */
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index 43d2d78d3287..74bab9ddd0e1 100644
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -26,6 +26,12 @@ process_entry:
26 PTR_L s2, (s0) 26 PTR_L s2, (s0)
27 PTR_ADD s0, s0, SZREG 27 PTR_ADD s0, s0, SZREG
28 28
29 /*
30 * In case of a kdump/crash kernel, the indirection page is not
31 * populated as the kernel is directly copied to a reserved location
32 */
33 beqz s2, done
34
29 /* destination page */ 35 /* destination page */
30 and s3, s2, 0x1 36 and s3, s2, 0x1
31 beq s3, zero, 1f 37 beq s3, zero, 1f
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index c7f90519e58c..c538d6e01b7b 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -552,6 +552,52 @@ static void __init arch_mem_addpart(phys_t mem, phys_t end, int type)
552 add_memory_region(mem, size, type); 552 add_memory_region(mem, size, type);
553} 553}
554 554
555#ifdef CONFIG_KEXEC
556static inline unsigned long long get_total_mem(void)
557{
558 unsigned long long total;
559
560 total = max_pfn - min_low_pfn;
561 return total << PAGE_SHIFT;
562}
563
564static void __init mips_parse_crashkernel(void)
565{
566 unsigned long long total_mem;
567 unsigned long long crash_size, crash_base;
568 int ret;
569
570 total_mem = get_total_mem();
571 ret = parse_crashkernel(boot_command_line, total_mem,
572 &crash_size, &crash_base);
573 if (ret != 0 || crash_size <= 0)
574 return;
575
576 crashk_res.start = crash_base;
577 crashk_res.end = crash_base + crash_size - 1;
578}
579
580static void __init request_crashkernel(struct resource *res)
581{
582 int ret;
583
584 ret = request_resource(res, &crashk_res);
585 if (!ret)
586 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
587 (unsigned long)((crashk_res.end -
588 crashk_res.start + 1) >> 20),
589 (unsigned long)(crashk_res.start >> 20));
590}
591#else /* !defined(CONFIG_KEXEC) */
592static void __init mips_parse_crashkernel(void)
593{
594}
595
596static void __init request_crashkernel(struct resource *res)
597{
598}
599#endif /* !defined(CONFIG_KEXEC) */
600
555static void __init arch_mem_init(char **cmdline_p) 601static void __init arch_mem_init(char **cmdline_p)
556{ 602{
557 extern void plat_mem_setup(void); 603 extern void plat_mem_setup(void);
@@ -608,6 +654,8 @@ static void __init arch_mem_init(char **cmdline_p)
608 BOOTMEM_DEFAULT); 654 BOOTMEM_DEFAULT);
609 } 655 }
610#endif 656#endif
657
658 mips_parse_crashkernel();
611#ifdef CONFIG_KEXEC 659#ifdef CONFIG_KEXEC
612 if (crashk_res.start != crashk_res.end) 660 if (crashk_res.start != crashk_res.end)
613 reserve_bootmem(crashk_res.start, 661 reserve_bootmem(crashk_res.start,
@@ -620,52 +668,6 @@ static void __init arch_mem_init(char **cmdline_p)
620 paging_init(); 668 paging_init();
621} 669}
622 670
623#ifdef CONFIG_KEXEC
624static inline unsigned long long get_total_mem(void)
625{
626 unsigned long long total;
627
628 total = max_pfn - min_low_pfn;
629 return total << PAGE_SHIFT;
630}
631
632static void __init mips_parse_crashkernel(void)
633{
634 unsigned long long total_mem;
635 unsigned long long crash_size, crash_base;
636 int ret;
637
638 total_mem = get_total_mem();
639 ret = parse_crashkernel(boot_command_line, total_mem,
640 &crash_size, &crash_base);
641 if (ret != 0 || crash_size <= 0)
642 return;
643
644 crashk_res.start = crash_base;
645 crashk_res.end = crash_base + crash_size - 1;
646}
647
648static void __init request_crashkernel(struct resource *res)
649{
650 int ret;
651
652 ret = request_resource(res, &crashk_res);
653 if (!ret)
654 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
655 (unsigned long)((crashk_res.end -
656 crashk_res.start + 1) >> 20),
657 (unsigned long)(crashk_res.start >> 20));
658}
659#else /* !defined(CONFIG_KEXEC) */
660static void __init mips_parse_crashkernel(void)
661{
662}
663
664static void __init request_crashkernel(struct resource *res)
665{
666}
667#endif /* !defined(CONFIG_KEXEC) */
668
669static void __init resource_init(void) 671static void __init resource_init(void)
670{ 672{
671 int i; 673 int i;
@@ -678,11 +680,6 @@ static void __init resource_init(void)
678 data_resource.start = __pa_symbol(&_etext); 680 data_resource.start = __pa_symbol(&_etext);
679 data_resource.end = __pa_symbol(&_edata) - 1; 681 data_resource.end = __pa_symbol(&_edata) - 1;
680 682
681 /*
682 * Request address space for all standard RAM.
683 */
684 mips_parse_crashkernel();
685
686 for (i = 0; i < boot_mem_map.nr_map; i++) { 683 for (i = 0; i < boot_mem_map.nr_map; i++) {
687 struct resource *res; 684 struct resource *res;
688 unsigned long start, end; 685 unsigned long start, end;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 9d686bf97b0e..364d26ae4215 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -121,6 +121,14 @@ void __init time_init(void)
121{ 121{
122 plat_time_init(); 122 plat_time_init();
123 123
124 if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) 124 /*
125 * The use of the R4k timer as a clock event takes precedence;
126 * if reading the Count register might interfere with the timer
127 * interrupt, then we don't use the timer as a clock source.
128 * We may still use the timer as a clock source though if the
129 * timer interrupt isn't reliable; the interference doesn't
130 * matter then, because we don't use the interrupt.
131 */
132 if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug())
125 init_mips_clocksource(); 133 init_mips_clocksource();
126} 134}
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 05826d20a792..3b46f7ce9ca7 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -179,5 +179,6 @@ SECTIONS
179 *(.options) 179 *(.options)
180 *(.pdr) 180 *(.pdr)
181 *(.reginfo) 181 *(.reginfo)
182 *(.eh_frame)
182 } 183 }
183} 184}
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index ff4894a833ee..8f1866d8124d 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -48,6 +48,7 @@
48#define CPU0CC_CPUDIV 0x0001 48#define CPU0CC_CPUDIV 0x0001
49 49
50/* Activation Status Register */ 50/* Activation Status Register */
51#define ACTS_ASC0_ACT 0x00001000
51#define ACTS_ASC1_ACT 0x00000800 52#define ACTS_ASC1_ACT 0x00000800
52#define ACTS_I2C_ACT 0x00004000 53#define ACTS_I2C_ACT 0x00004000
53#define ACTS_P0 0x00010000 54#define ACTS_P0 0x00010000
@@ -108,6 +109,7 @@ static void sysctl_deactivate(struct clk *clk)
108static int sysctl_clken(struct clk *clk) 109static int sysctl_clken(struct clk *clk)
109{ 110{
110 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); 111 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
112 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
111 sysctl_wait(clk, clk->bits, SYSCTL_CLKS); 113 sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
112 return 0; 114 return 0;
113} 115}
@@ -256,6 +258,7 @@ void __init ltq_soc_init(void)
256 clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1); 258 clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
257 clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3); 259 clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
258 clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4); 260 clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
259 clkdev_add_sys("1e100C00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT); 261 clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
262 clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT);
260 clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT); 263 clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
261} 264}
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 7a13660d630d..087497d97357 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,3 @@
1obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o 1obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
2 2
3obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o 3obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c
new file mode 100644
index 000000000000..7688ac0f06d0
--- /dev/null
+++ b/arch/mips/lantiq/xway/dcdc.c
@@ -0,0 +1,63 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
7 * Copyright (C) 2010 Sameer Ahmad, Lantiq GmbH
8 */
9
10#include <linux/ioport.h>
11#include <linux/of_platform.h>
12
13#include <lantiq_soc.h>
14
15/* Bias and regulator Setup Register */
16#define DCDC_BIAS_VREG0 0xa
17/* Bias and regulator Setup Register */
18#define DCDC_BIAS_VREG1 0xb
19
20#define dcdc_w8(x, y) ltq_w8((x), dcdc_membase + (y))
21#define dcdc_r8(x) ltq_r8(dcdc_membase + (x))
22
23static void __iomem *dcdc_membase;
24
25static int dcdc_probe(struct platform_device *pdev)
26{
27 struct resource *res;
28
29 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
30 dcdc_membase = devm_ioremap_resource(&pdev->dev, res);
31 if (IS_ERR(dcdc_membase))
32 return PTR_ERR(dcdc_membase);
33
34 dev_info(&pdev->dev, "Core Voltage : %d mV\n",
35 dcdc_r8(DCDC_BIAS_VREG1) * 8);
36
37 return 0;
38}
39
40static const struct of_device_id dcdc_match[] = {
41 { .compatible = "lantiq,dcdc-xrx200" },
42 {},
43};
44
45static struct platform_driver dcdc_driver = {
46 .probe = dcdc_probe,
47 .driver = {
48 .name = "dcdc-xrx200",
49 .owner = THIS_MODULE,
50 .of_match_table = dcdc_match,
51 },
52};
53
54int __init dcdc_init(void)
55{
56 int ret = platform_driver_register(&dcdc_driver);
57
58 if (ret)
59 pr_info("dcdc: Error registering platform driver\n");
60 return ret;
61}
62
63arch_initcall(dcdc_init);
diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile
index dfb509d21d8e..fd32075679c6 100644
--- a/arch/mips/lasat/image/Makefile
+++ b/arch/mips/lasat/image/Makefile
@@ -13,13 +13,11 @@ endif
13MKLASATIMG = mklasatimg 13MKLASATIMG = mklasatimg
14MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200 14MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200
15KERNEL_IMAGE = vmlinux 15KERNEL_IMAGE = vmlinux
16KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ )
17KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ )
18 16
19LDSCRIPT= -L$(srctree)/$(src) -Tromscript.normal 17LDSCRIPT= -L$(srctree)/$(src) -Tromscript.normal
20 18
21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ 19HEAD_DEFINES := -D_kernel_start=$(VMLINUX_LOAD_ADDRESS) \
22 -D_kernel_entry=0x$(KERNEL_ENTRY) \ 20 -D_kernel_entry=$(VMLINUX_ENTRY_ADDRESS) \
23 -D VERSION="\"$(Version)\"" \ 21 -D VERSION="\"$(Version)\"" \
24 -D TIMESTAMP=$(shell date +%s) 22 -D TIMESTAMP=$(shell date +%s)
25 23
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index 4c57b3e5743f..9e4484ccbb03 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -3,8 +3,9 @@
3# 3#
4 4
5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ 5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
6 pci.o bonito-irq.o mem.o machtype.o platform.o 6 bonito-irq.o mem.o machtype.o platform.o
7obj-$(CONFIG_GPIOLIB) += gpio.o 7obj-$(CONFIG_GPIOLIB) += gpio.o
8obj-$(CONFIG_PCI) += pci.o
8 9
9# 10#
10# Serial port support 11# Serial port support
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 46048d24328c..efe008846ed0 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -436,7 +436,6 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
436 break; 436 break;
437 default: 437 default:
438 return SIGILL; 438 return SIGILL;
439 break;
440 } 439 }
441 break; 440 break;
442 case mm_32f_74_op: /* c.cond.fmt */ 441 case mm_32f_74_op: /* c.cond.fmt */
@@ -451,12 +450,10 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
451 break; 450 break;
452 default: 451 default:
453 return SIGILL; 452 return SIGILL;
454 break;
455 } 453 }
456 break; 454 break;
457 default: 455 default:
458 return SIGILL; 456 return SIGILL;
459 break;
460 } 457 }
461 458
462 *insn_ptr = mips32_insn; 459 *insn_ptr = mips32_insn;
@@ -491,7 +488,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
491 dec_insn.next_pc_inc; 488 dec_insn.next_pc_inc;
492 *contpc = regs->regs[insn.mm_i_format.rs]; 489 *contpc = regs->regs[insn.mm_i_format.rs];
493 return 1; 490 return 1;
494 break;
495 } 491 }
496 } 492 }
497 break; 493 break;
@@ -513,7 +509,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
513 dec_insn.pc_inc + 509 dec_insn.pc_inc +
514 dec_insn.next_pc_inc; 510 dec_insn.next_pc_inc;
515 return 1; 511 return 1;
516 break;
517 case mm_bgezals_op: 512 case mm_bgezals_op:
518 case mm_bgezal_op: 513 case mm_bgezal_op:
519 regs->regs[31] = regs->cp0_epc + 514 regs->regs[31] = regs->cp0_epc +
@@ -530,7 +525,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
530 dec_insn.pc_inc + 525 dec_insn.pc_inc +
531 dec_insn.next_pc_inc; 526 dec_insn.next_pc_inc;
532 return 1; 527 return 1;
533 break;
534 case mm_blez_op: 528 case mm_blez_op:
535 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 529 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
536 *contpc = regs->cp0_epc + 530 *contpc = regs->cp0_epc +
@@ -541,7 +535,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
541 dec_insn.pc_inc + 535 dec_insn.pc_inc +
542 dec_insn.next_pc_inc; 536 dec_insn.next_pc_inc;
543 return 1; 537 return 1;
544 break;
545 case mm_bgtz_op: 538 case mm_bgtz_op:
546 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 539 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
547 *contpc = regs->cp0_epc + 540 *contpc = regs->cp0_epc +
@@ -552,7 +545,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
552 dec_insn.pc_inc + 545 dec_insn.pc_inc +
553 dec_insn.next_pc_inc; 546 dec_insn.next_pc_inc;
554 return 1; 547 return 1;
555 break;
556 case mm_bc2f_op: 548 case mm_bc2f_op:
557 case mm_bc1f_op: 549 case mm_bc1f_op:
558 bc_false = 1; 550 bc_false = 1;
@@ -580,7 +572,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
580 *contpc = regs->cp0_epc + 572 *contpc = regs->cp0_epc +
581 dec_insn.pc_inc + dec_insn.next_pc_inc; 573 dec_insn.pc_inc + dec_insn.next_pc_inc;
582 return 1; 574 return 1;
583 break;
584 } 575 }
585 break; 576 break;
586 case mm_pool16c_op: 577 case mm_pool16c_op:
@@ -593,7 +584,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
593 case mm_jr16_op: 584 case mm_jr16_op:
594 *contpc = regs->regs[insn.mm_i_format.rs]; 585 *contpc = regs->regs[insn.mm_i_format.rs];
595 return 1; 586 return 1;
596 break;
597 } 587 }
598 break; 588 break;
599 case mm_beqz16_op: 589 case mm_beqz16_op:
@@ -605,7 +595,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
605 *contpc = regs->cp0_epc + 595 *contpc = regs->cp0_epc +
606 dec_insn.pc_inc + dec_insn.next_pc_inc; 596 dec_insn.pc_inc + dec_insn.next_pc_inc;
607 return 1; 597 return 1;
608 break;
609 case mm_bnez16_op: 598 case mm_bnez16_op:
610 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) 599 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
611 *contpc = regs->cp0_epc + 600 *contpc = regs->cp0_epc +
@@ -615,12 +604,10 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
615 *contpc = regs->cp0_epc + 604 *contpc = regs->cp0_epc +
616 dec_insn.pc_inc + dec_insn.next_pc_inc; 605 dec_insn.pc_inc + dec_insn.next_pc_inc;
617 return 1; 606 return 1;
618 break;
619 case mm_b16_op: 607 case mm_b16_op:
620 *contpc = regs->cp0_epc + dec_insn.pc_inc + 608 *contpc = regs->cp0_epc + dec_insn.pc_inc +
621 (insn.mm_b0_format.simmediate << 1); 609 (insn.mm_b0_format.simmediate << 1);
622 return 1; 610 return 1;
623 break;
624 case mm_beq32_op: 611 case mm_beq32_op:
625 if (regs->regs[insn.mm_i_format.rs] == 612 if (regs->regs[insn.mm_i_format.rs] ==
626 regs->regs[insn.mm_i_format.rt]) 613 regs->regs[insn.mm_i_format.rt])
@@ -632,7 +619,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
632 dec_insn.pc_inc + 619 dec_insn.pc_inc +
633 dec_insn.next_pc_inc; 620 dec_insn.next_pc_inc;
634 return 1; 621 return 1;
635 break;
636 case mm_bne32_op: 622 case mm_bne32_op:
637 if (regs->regs[insn.mm_i_format.rs] != 623 if (regs->regs[insn.mm_i_format.rs] !=
638 regs->regs[insn.mm_i_format.rt]) 624 regs->regs[insn.mm_i_format.rt])
@@ -643,7 +629,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
643 *contpc = regs->cp0_epc + 629 *contpc = regs->cp0_epc +
644 dec_insn.pc_inc + dec_insn.next_pc_inc; 630 dec_insn.pc_inc + dec_insn.next_pc_inc;
645 return 1; 631 return 1;
646 break;
647 case mm_jalx32_op: 632 case mm_jalx32_op:
648 regs->regs[31] = regs->cp0_epc + 633 regs->regs[31] = regs->cp0_epc +
649 dec_insn.pc_inc + dec_insn.next_pc_inc; 634 dec_insn.pc_inc + dec_insn.next_pc_inc;
@@ -652,7 +637,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
652 *contpc <<= 28; 637 *contpc <<= 28;
653 *contpc |= (insn.j_format.target << 2); 638 *contpc |= (insn.j_format.target << 2);
654 return 1; 639 return 1;
655 break;
656 case mm_jals32_op: 640 case mm_jals32_op:
657 case mm_jal32_op: 641 case mm_jal32_op:
658 regs->regs[31] = regs->cp0_epc + 642 regs->regs[31] = regs->cp0_epc +
@@ -665,7 +649,6 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
665 *contpc |= (insn.j_format.target << 1); 649 *contpc |= (insn.j_format.target << 1);
666 set_isa16_mode(*contpc); 650 set_isa16_mode(*contpc);
667 return 1; 651 return 1;
668 break;
669 } 652 }
670 return 0; 653 return 0;
671} 654}
@@ -694,7 +677,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
694 case jr_op: 677 case jr_op:
695 *contpc = regs->regs[insn.r_format.rs]; 678 *contpc = regs->regs[insn.r_format.rs];
696 return 1; 679 return 1;
697 break;
698 } 680 }
699 break; 681 break;
700 case bcond_op: 682 case bcond_op:
@@ -716,7 +698,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
716 dec_insn.pc_inc + 698 dec_insn.pc_inc +
717 dec_insn.next_pc_inc; 699 dec_insn.next_pc_inc;
718 return 1; 700 return 1;
719 break;
720 case bgezal_op: 701 case bgezal_op:
721 case bgezall_op: 702 case bgezall_op:
722 regs->regs[31] = regs->cp0_epc + 703 regs->regs[31] = regs->cp0_epc +
@@ -734,7 +715,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
734 dec_insn.pc_inc + 715 dec_insn.pc_inc +
735 dec_insn.next_pc_inc; 716 dec_insn.next_pc_inc;
736 return 1; 717 return 1;
737 break;
738 } 718 }
739 break; 719 break;
740 case jalx_op: 720 case jalx_op:
@@ -752,7 +732,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
752 /* Set microMIPS mode bit: XOR for jalx. */ 732 /* Set microMIPS mode bit: XOR for jalx. */
753 *contpc ^= bit; 733 *contpc ^= bit;
754 return 1; 734 return 1;
755 break;
756 case beq_op: 735 case beq_op:
757 case beql_op: 736 case beql_op:
758 if (regs->regs[insn.i_format.rs] == 737 if (regs->regs[insn.i_format.rs] ==
@@ -765,7 +744,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
765 dec_insn.pc_inc + 744 dec_insn.pc_inc +
766 dec_insn.next_pc_inc; 745 dec_insn.next_pc_inc;
767 return 1; 746 return 1;
768 break;
769 case bne_op: 747 case bne_op:
770 case bnel_op: 748 case bnel_op:
771 if (regs->regs[insn.i_format.rs] != 749 if (regs->regs[insn.i_format.rs] !=
@@ -778,7 +756,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
778 dec_insn.pc_inc + 756 dec_insn.pc_inc +
779 dec_insn.next_pc_inc; 757 dec_insn.next_pc_inc;
780 return 1; 758 return 1;
781 break;
782 case blez_op: 759 case blez_op:
783 case blezl_op: 760 case blezl_op:
784 if ((long)regs->regs[insn.i_format.rs] <= 0) 761 if ((long)regs->regs[insn.i_format.rs] <= 0)
@@ -790,7 +767,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
790 dec_insn.pc_inc + 767 dec_insn.pc_inc +
791 dec_insn.next_pc_inc; 768 dec_insn.next_pc_inc;
792 return 1; 769 return 1;
793 break;
794 case bgtz_op: 770 case bgtz_op:
795 case bgtzl_op: 771 case bgtzl_op:
796 if ((long)regs->regs[insn.i_format.rs] > 0) 772 if ((long)regs->regs[insn.i_format.rs] > 0)
@@ -802,7 +778,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
802 dec_insn.pc_inc + 778 dec_insn.pc_inc +
803 dec_insn.next_pc_inc; 779 dec_insn.next_pc_inc;
804 return 1; 780 return 1;
805 break;
806#ifdef CONFIG_CPU_CAVIUM_OCTEON 781#ifdef CONFIG_CPU_CAVIUM_OCTEON
807 case lwc2_op: /* This is bbit0 on Octeon */ 782 case lwc2_op: /* This is bbit0 on Octeon */
808 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 783 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
@@ -856,7 +831,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
856 dec_insn.pc_inc + 831 dec_insn.pc_inc +
857 dec_insn.next_pc_inc; 832 dec_insn.next_pc_inc;
858 return 1; 833 return 1;
859 break;
860 case 1: /* bc1t */ 834 case 1: /* bc1t */
861 case 3: /* bc1tl */ 835 case 3: /* bc1tl */
862 if (fcr31 & (1 << bit)) 836 if (fcr31 & (1 << bit))
@@ -868,7 +842,6 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
868 dec_insn.pc_inc + 842 dec_insn.pc_inc +
869 dec_insn.next_pc_inc; 843 dec_insn.next_pc_inc;
870 return 1; 844 return 1;
871 break;
872 } 845 }
873 } 846 }
874 break; 847 break;
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index a0bcdbb81d41..729e7702b1de 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -224,6 +224,20 @@ static void probe_octeon(void)
224 c->options |= MIPS_CPU_PREFETCH; 224 c->options |= MIPS_CPU_PREFETCH;
225 break; 225 break;
226 226
227 case CPU_CAVIUM_OCTEON3:
228 c->icache.linesz = 128;
229 c->icache.sets = 16;
230 c->icache.ways = 39;
231 c->icache.flags |= MIPS_CACHE_VTAG;
232 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
233
234 c->dcache.linesz = 128;
235 c->dcache.ways = 32;
236 c->dcache.sets = 8;
237 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
238 c->options |= MIPS_CPU_PREFETCH;
239 break;
240
227 default: 241 default:
228 panic("Unsupported Cavium Networks CPU type"); 242 panic("Unsupported Cavium Networks CPU type");
229 break; 243 break;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index aaccf1c10699..664e523653d0 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -50,16 +50,20 @@ static inline struct page *dma_addr_to_page(struct device *dev,
50} 50}
51 51
52/* 52/*
53 * The affected CPUs below in 'cpu_needs_post_dma_flush()' can
54 * speculatively fill random cachelines with stale data at any time,
55 * requiring an extra flush post-DMA.
56 *
53 * Warning on the terminology - Linux calls an uncached area coherent; 57 * Warning on the terminology - Linux calls an uncached area coherent;
54 * MIPS terminology calls memory areas with hardware maintained coherency 58 * MIPS terminology calls memory areas with hardware maintained coherency
55 * coherent. 59 * coherent.
56 */ 60 */
57 61static inline int cpu_needs_post_dma_flush(struct device *dev)
58static inline int cpu_is_noncoherent_r10000(struct device *dev)
59{ 62{
60 return !plat_device_is_coherent(dev) && 63 return !plat_device_is_coherent(dev) &&
61 (current_cpu_type() == CPU_R10000 || 64 (boot_cpu_type() == CPU_R10000 ||
62 current_cpu_type() == CPU_R12000); 65 boot_cpu_type() == CPU_R12000 ||
66 boot_cpu_type() == CPU_BMIPS5000);
63} 67}
64 68
65static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) 69static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
@@ -230,7 +234,7 @@ static inline void __dma_sync(struct page *page,
230static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, 234static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
231 size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) 235 size_t size, enum dma_data_direction direction, struct dma_attrs *attrs)
232{ 236{
233 if (cpu_is_noncoherent_r10000(dev)) 237 if (cpu_needs_post_dma_flush(dev))
234 __dma_sync(dma_addr_to_page(dev, dma_addr), 238 __dma_sync(dma_addr_to_page(dev, dma_addr),
235 dma_addr & ~PAGE_MASK, size, direction); 239 dma_addr & ~PAGE_MASK, size, direction);
236 240
@@ -284,7 +288,7 @@ static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
284static void mips_dma_sync_single_for_cpu(struct device *dev, 288static void mips_dma_sync_single_for_cpu(struct device *dev,
285 dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) 289 dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
286{ 290{
287 if (cpu_is_noncoherent_r10000(dev)) 291 if (cpu_needs_post_dma_flush(dev))
288 __dma_sync(dma_addr_to_page(dev, dma_handle), 292 __dma_sync(dma_addr_to_page(dev, dma_handle),
289 dma_handle & ~PAGE_MASK, size, direction); 293 dma_handle & ~PAGE_MASK, size, direction);
290} 294}
@@ -305,7 +309,7 @@ static void mips_dma_sync_sg_for_cpu(struct device *dev,
305 309
306 /* Make sure that gcc doesn't leave the empty loop body. */ 310 /* Make sure that gcc doesn't leave the empty loop body. */
307 for (i = 0; i < nelems; i++, sg++) { 311 for (i = 0; i < nelems; i++, sg++) {
308 if (cpu_is_noncoherent_r10000(dev)) 312 if (cpu_needs_post_dma_flush(dev))
309 __dma_sync(sg_page(sg), sg->offset, sg->length, 313 __dma_sync(sg_page(sg), sg->offset, sg->length,
310 direction); 314 direction);
311 } 315 }
diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
index d4ea5c9c4a93..06ce17c2a905 100644
--- a/arch/mips/mm/gup.c
+++ b/arch/mips/mm/gup.c
@@ -12,6 +12,7 @@
12#include <linux/swap.h> 12#include <linux/swap.h>
13#include <linux/hugetlb.h> 13#include <linux/hugetlb.h>
14 14
15#include <asm/cpu-features.h>
15#include <asm/pgtable.h> 16#include <asm/pgtable.h>
16 17
17static inline pte_t gup_get_pte(pte_t *ptep) 18static inline pte_t gup_get_pte(pte_t *ptep)
@@ -273,7 +274,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
273 len = (unsigned long) nr_pages << PAGE_SHIFT; 274 len = (unsigned long) nr_pages << PAGE_SHIFT;
274 275
275 end = start + len; 276 end = start + len;
276 if (end < start) 277 if (end < start || cpu_has_dc_aliases)
277 goto slow_irqon; 278 goto slow_irqon;
278 279
279 /* XXX: batch / limit 'nr' */ 280 /* XXX: batch / limit 'nr' */
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 4e73f10a7519..e205ef598e97 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -254,6 +254,7 @@ void copy_from_user_page(struct vm_area_struct *vma,
254 SetPageDcacheDirty(page); 254 SetPageDcacheDirty(page);
255 } 255 }
256} 256}
257EXPORT_SYMBOL_GPL(copy_from_user_page);
257 258
258void __init fixrange_init(unsigned long start, unsigned long end, 259void __init fixrange_init(unsigned long start, unsigned long end,
259 pgd_t *pgd_base) 260 pgd_t *pgd_base)
diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S
index 30a494db99c2..79bca3130bd1 100644
--- a/arch/mips/mm/tlb-funcs.S
+++ b/arch/mips/mm/tlb-funcs.S
@@ -16,10 +16,12 @@
16 16
17#define FASTPATH_SIZE 128 17#define FASTPATH_SIZE 128
18 18
19#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
19LEAF(tlbmiss_handler_setup_pgd) 20LEAF(tlbmiss_handler_setup_pgd)
20 .space 16 * 4 21 .space 16 * 4
21END(tlbmiss_handler_setup_pgd) 22END(tlbmiss_handler_setup_pgd)
22EXPORT(tlbmiss_handler_setup_pgd_end) 23EXPORT(tlbmiss_handler_setup_pgd_end)
24#endif
23 25
24LEAF(handle_tlbm) 26LEAF(handle_tlbm)
25 .space FASTPATH_SIZE * 4 27 .space FASTPATH_SIZE * 4
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 556cb4815770..821b45175dc1 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -85,6 +85,7 @@ static int use_bbit_insns(void)
85 case CPU_CAVIUM_OCTEON: 85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS: 86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2: 87 case CPU_CAVIUM_OCTEON2:
88 case CPU_CAVIUM_OCTEON3:
88 return 1; 89 return 1;
89 default: 90 default:
90 return 0; 91 return 0;
@@ -95,6 +96,7 @@ static int use_lwx_insns(void)
95{ 96{
96 switch (current_cpu_type()) { 97 switch (current_cpu_type()) {
97 case CPU_CAVIUM_OCTEON2: 98 case CPU_CAVIUM_OCTEON2:
99 case CPU_CAVIUM_OCTEON3:
98 return 1; 100 return 1;
99 default: 101 default:
100 return 0; 102 return 0;
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 2447bf97d35a..852a4ee09954 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -19,6 +19,15 @@ config DT_XLP_SVP
19 pointer to the kernel. The corresponding DTS file is at 19 pointer to the kernel. The corresponding DTS file is at
20 arch/mips/netlogic/dts/xlp_svp.dts 20 arch/mips/netlogic/dts/xlp_svp.dts
21 21
22config DT_XLP_FVP
23 bool "Built-in device tree for XLP FVP boards"
24 default y
25 help
26 Add an FDT blob for XLP FVP board into the kernel.
27 This DTB will be used if the firmware does not pass in a DTB
28 pointer to the kernel. The corresponding DTS file is at
29 arch/mips/netlogic/dts/xlp_fvp.dts
30
22config NLM_MULTINODE 31config NLM_MULTINODE
23 bool "Support for multi-chip boards" 32 bool "Support for multi-chip boards"
24 depends on NLM_XLP_BOARD 33 depends on NLM_XLP_BOARD
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 4e35d9c453e2..6f8feb9efcff 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -106,9 +106,7 @@ void nlm_early_init_secondary(int cpu)
106{ 106{
107 change_c0_config(CONF_CM_CMASK, 0x3); 107 change_c0_config(CONF_CM_CMASK, 0x3);
108#ifdef CONFIG_CPU_XLP 108#ifdef CONFIG_CPU_XLP
109 /* mmu init, once per core */ 109 xlp_mmu_init();
110 if (cpu % NLM_THREADS_PER_CORE == 0)
111 xlp_mmu_init();
112#endif 110#endif
113 write_c0_ebase(nlm_current_node()->ebase); 111 write_c0_ebase(nlm_current_node()->ebase);
114} 112}
diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c
index 045a396c57ce..13391b8a6031 100644
--- a/arch/mips/netlogic/common/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -45,6 +45,7 @@
45#if defined(CONFIG_CPU_XLP) 45#if defined(CONFIG_CPU_XLP)
46#include <asm/netlogic/xlp-hal/iomap.h> 46#include <asm/netlogic/xlp-hal/iomap.h>
47#include <asm/netlogic/xlp-hal/xlp.h> 47#include <asm/netlogic/xlp-hal/xlp.h>
48#include <asm/netlogic/xlp-hal/sys.h>
48#include <asm/netlogic/xlp-hal/pic.h> 49#include <asm/netlogic/xlp-hal/pic.h>
49#elif defined(CONFIG_CPU_XLR) 50#elif defined(CONFIG_CPU_XLR)
50#include <asm/netlogic/xlr/iomap.h> 51#include <asm/netlogic/xlr/iomap.h>
@@ -91,7 +92,7 @@ static void nlm_init_pic_timer(void)
91 csrc_pic.read = nlm_get_pic_timer; 92 csrc_pic.read = nlm_get_pic_timer;
92 } 93 }
93 csrc_pic.rating = 1000; 94 csrc_pic.rating = 1000;
94 clocksource_register_hz(&csrc_pic, PIC_CLK_HZ); 95 clocksource_register_hz(&csrc_pic, pic_timer_freq());
95} 96}
96 97
97void __init plat_time_init(void) 98void __init plat_time_init(void)
diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile
index aecb6fa9a9c3..0b9be5fd2e46 100644
--- a/arch/mips/netlogic/dts/Makefile
+++ b/arch/mips/netlogic/dts/Makefile
@@ -1,2 +1,3 @@
1obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o 1obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
2obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o 2obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
3obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o
diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts
index 06407033678e..89ad04808c02 100644
--- a/arch/mips/netlogic/dts/xlp_evp.dts
+++ b/arch/mips/netlogic/dts/xlp_evp.dts
@@ -9,19 +9,12 @@
9 #address-cells = <2>; 9 #address-cells = <2>;
10 #size-cells = <2>; 10 #size-cells = <2>;
11 11
12 memory {
13 device_type = "memory";
14 reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M
15 0 0x20000000 0 0xa0000000 // 2560M at 512M
16 0 0xe0000000 1 0x00000000>;
17 };
18
19 soc { 12 soc {
20 #address-cells = <2>; 13 #address-cells = <2>;
21 #size-cells = <1>; 14 #size-cells = <1>;
22 compatible = "simple-bus"; 15 compatible = "simple-bus";
23 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG 16 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
24 1 0 0 0x16000000 0x01000000>; // GBU chipselects 17 1 0 0 0x16000000 0x02000000>; // GBU chipselects
25 18
26 serial0: serial@30000 { 19 serial0: serial@30000 {
27 device_type = "serial"; 20 device_type = "serial";
diff --git a/arch/mips/netlogic/dts/xlp_fvp.dts b/arch/mips/netlogic/dts/xlp_fvp.dts
new file mode 100644
index 000000000000..63e62b7bd758
--- /dev/null
+++ b/arch/mips/netlogic/dts/xlp_fvp.dts
@@ -0,0 +1,118 @@
1/*
2 * XLP2XX Device Tree Source for FVP boards
3 */
4
5/dts-v1/;
6/ {
7 model = "netlogic,XLP-FVP";
8 compatible = "netlogic,xlp";
9 #address-cells = <2>;
10 #size-cells = <2>;
11
12 soc {
13 #address-cells = <2>;
14 #size-cells = <1>;
15 compatible = "simple-bus";
16 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
17 1 0 0 0x16000000 0x02000000>; // GBU chipselects
18
19 serial0: serial@30000 {
20 device_type = "serial";
21 compatible = "ns16550";
22 reg = <0 0x30100 0xa00>;
23 reg-shift = <2>;
24 reg-io-width = <4>;
25 clock-frequency = <133333333>;
26 interrupt-parent = <&pic>;
27 interrupts = <17>;
28 };
29 serial1: serial@31000 {
30 device_type = "serial";
31 compatible = "ns16550";
32 reg = <0 0x31100 0xa00>;
33 reg-shift = <2>;
34 reg-io-width = <4>;
35 clock-frequency = <133333333>;
36 interrupt-parent = <&pic>;
37 interrupts = <18>;
38 };
39 i2c0: ocores@37100 {
40 compatible = "opencores,i2c-ocores";
41 #address-cells = <1>;
42 #size-cells = <0>;
43 reg = <0 0x37100 0x20>;
44 reg-shift = <2>;
45 reg-io-width = <4>;
46 clock-frequency = <32000000>;
47 interrupt-parent = <&pic>;
48 interrupts = <30>;
49 };
50 i2c1: ocores@37120 {
51 compatible = "opencores,i2c-ocores";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 reg = <0 0x37120 0x20>;
55 reg-shift = <2>;
56 reg-io-width = <4>;
57 clock-frequency = <32000000>;
58 interrupt-parent = <&pic>;
59 interrupts = <31>;
60
61 rtc@68 {
62 compatible = "dallas,ds1374";
63 reg = <0x68>;
64 };
65
66 dtt@4c {
67 compatible = "national,lm90";
68 reg = <0x4c>;
69 };
70 };
71 pic: pic@4000 {
72 compatible = "netlogic,xlp-pic";
73 #address-cells = <0>;
74 #interrupt-cells = <1>;
75 reg = <0 0x4000 0x200>;
76 interrupt-controller;
77 };
78
79 nor_flash@1,0 {
80 compatible = "cfi-flash";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 bank-width = <2>;
84 reg = <1 0 0x1000000>;
85
86 partition@0 {
87 label = "x-loader";
88 reg = <0x0 0x100000>; /* 1M */
89 read-only;
90 };
91
92 partition@100000 {
93 label = "u-boot";
94 reg = <0x100000 0x100000>; /* 1M */
95 };
96
97 partition@200000 {
98 label = "kernel";
99 reg = <0x200000 0x500000>; /* 5M */
100 };
101
102 partition@700000 {
103 label = "rootfs";
104 reg = <0x700000 0x800000>; /* 8M */
105 };
106
107 partition@f00000 {
108 label = "env";
109 reg = <0xf00000 0x100000>; /* 1M */
110 read-only;
111 };
112 };
113 };
114
115 chosen {
116 bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
117 };
118};
diff --git a/arch/mips/netlogic/dts/xlp_svp.dts b/arch/mips/netlogic/dts/xlp_svp.dts
index 9c5db102df53..1ebd00edaacc 100644
--- a/arch/mips/netlogic/dts/xlp_svp.dts
+++ b/arch/mips/netlogic/dts/xlp_svp.dts
@@ -9,19 +9,12 @@
9 #address-cells = <2>; 9 #address-cells = <2>;
10 #size-cells = <2>; 10 #size-cells = <2>;
11 11
12 memory {
13 device_type = "memory";
14 reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M
15 0 0x20000000 0 0xa0000000 // 2560M at 512M
16 0 0xe0000000 0 0x40000000>;
17 };
18
19 soc { 12 soc {
20 #address-cells = <2>; 13 #address-cells = <2>;
21 #size-cells = <1>; 14 #size-cells = <1>;
22 compatible = "simple-bus"; 15 compatible = "simple-bus";
23 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG 16 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
24 1 0 0 0x16000000 0x01000000>; // GBU chipselects 17 1 0 0 0x16000000 0x02000000>; // GBU chipselects
25 18
26 serial0: serial@30000 { 19 serial0: serial@30000 {
27 device_type = "serial"; 20 device_type = "serial";
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
index 85ac4a892ced..ed9a93c04650 100644
--- a/arch/mips/netlogic/xlp/Makefile
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -1,3 +1,4 @@
1obj-y += setup.o nlm_hal.o cop2-ex.o dt.o 1obj-y += setup.o nlm_hal.o cop2-ex.o dt.o
2obj-$(CONFIG_SMP) += wakeup.o 2obj-$(CONFIG_SMP) += wakeup.o
3obj-$(CONFIG_USB) += usb-init.o 3obj-$(CONFIG_USB) += usb-init.o
4obj-$(CONFIG_USB) += usb-init-xlp2.o
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
index a15cdbb8d0bd..88df445dda76 100644
--- a/arch/mips/netlogic/xlp/dt.c
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -39,12 +39,18 @@
39#include <linux/of_platform.h> 39#include <linux/of_platform.h>
40#include <linux/of_device.h> 40#include <linux/of_device.h>
41 41
42extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[]; 42extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
43 __dtb_xlp_fvp_begin[], __dtb_start[];
43 44
44void __init *xlp_dt_init(void *fdtp) 45void __init *xlp_dt_init(void *fdtp)
45{ 46{
46 if (!fdtp) { 47 if (!fdtp) {
47 switch (current_cpu_data.processor_id & 0xff00) { 48 switch (current_cpu_data.processor_id & 0xff00) {
49#ifdef CONFIG_DT_XLP_FVP
50 case PRID_IMP_NETLOGIC_XLP2XX:
51 fdtp = __dtb_xlp_fvp_begin;
52 break;
53#endif
48#ifdef CONFIG_DT_XLP_SVP 54#ifdef CONFIG_DT_XLP_SVP
49 case PRID_IMP_NETLOGIC_XLP3XX: 55 case PRID_IMP_NETLOGIC_XLP3XX:
50 fdtp = __dtb_xlp_svp_begin; 56 fdtp = __dtb_xlp_svp_begin;
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 87560e4db35f..56c50ba43c9b 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -44,6 +44,7 @@
44#include <asm/netlogic/haldefs.h> 44#include <asm/netlogic/haldefs.h>
45#include <asm/netlogic/xlp-hal/iomap.h> 45#include <asm/netlogic/xlp-hal/iomap.h>
46#include <asm/netlogic/xlp-hal/xlp.h> 46#include <asm/netlogic/xlp-hal/xlp.h>
47#include <asm/netlogic/xlp-hal/bridge.h>
47#include <asm/netlogic/xlp-hal/pic.h> 48#include <asm/netlogic/xlp-hal/pic.h>
48#include <asm/netlogic/xlp-hal/sys.h> 49#include <asm/netlogic/xlp-hal/sys.h>
49 50
@@ -64,6 +65,7 @@ int nlm_irq_to_irt(int irq)
64 uint64_t pcibase; 65 uint64_t pcibase;
65 int devoff, irt; 66 int devoff, irt;
66 67
68 devoff = 0;
67 switch (irq) { 69 switch (irq) {
68 case PIC_UART_0_IRQ: 70 case PIC_UART_0_IRQ:
69 devoff = XLP_IO_UART0_OFFSET(0); 71 devoff = XLP_IO_UART0_OFFSET(0);
@@ -71,44 +73,68 @@ int nlm_irq_to_irt(int irq)
71 case PIC_UART_1_IRQ: 73 case PIC_UART_1_IRQ:
72 devoff = XLP_IO_UART1_OFFSET(0); 74 devoff = XLP_IO_UART1_OFFSET(0);
73 break; 75 break;
74 case PIC_EHCI_0_IRQ:
75 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
76 break;
77 case PIC_EHCI_1_IRQ:
78 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
79 break;
80 case PIC_OHCI_0_IRQ:
81 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
82 break;
83 case PIC_OHCI_1_IRQ:
84 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
85 break;
86 case PIC_OHCI_2_IRQ:
87 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
88 break;
89 case PIC_OHCI_3_IRQ:
90 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
91 break;
92 case PIC_MMC_IRQ: 76 case PIC_MMC_IRQ:
93 devoff = XLP_IO_SD_OFFSET(0); 77 devoff = XLP_IO_SD_OFFSET(0);
94 break; 78 break;
95 case PIC_I2C_0_IRQ: 79 case PIC_I2C_0_IRQ: /* I2C will be fixed up */
96 devoff = XLP_IO_I2C0_OFFSET(0);
97 break;
98 case PIC_I2C_1_IRQ: 80 case PIC_I2C_1_IRQ:
99 devoff = XLP_IO_I2C1_OFFSET(0); 81 case PIC_I2C_2_IRQ:
82 case PIC_I2C_3_IRQ:
83 if (cpu_is_xlpii())
84 devoff = XLP2XX_IO_I2C_OFFSET(0);
85 else
86 devoff = XLP_IO_I2C0_OFFSET(0);
100 break; 87 break;
101 default: 88 default:
102 devoff = 0; 89 if (cpu_is_xlpii()) {
103 break; 90 switch (irq) {
91 /* XLP2XX has three XHCI USB controller */
92 case PIC_2XX_XHCI_0_IRQ:
93 devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
94 break;
95 case PIC_2XX_XHCI_1_IRQ:
96 devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
97 break;
98 case PIC_2XX_XHCI_2_IRQ:
99 devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
100 break;
101 }
102 } else {
103 switch (irq) {
104 case PIC_EHCI_0_IRQ:
105 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
106 break;
107 case PIC_EHCI_1_IRQ:
108 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
109 break;
110 case PIC_OHCI_0_IRQ:
111 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
112 break;
113 case PIC_OHCI_1_IRQ:
114 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
115 break;
116 case PIC_OHCI_2_IRQ:
117 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
118 break;
119 case PIC_OHCI_3_IRQ:
120 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
121 break;
122 }
123 }
104 } 124 }
105 125
106 if (devoff != 0) { 126 if (devoff != 0) {
107 pcibase = nlm_pcicfg_base(devoff); 127 pcibase = nlm_pcicfg_base(devoff);
108 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff; 128 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
109 /* HW bug, I2C 1 irt entry is off by one */ 129 /* HW weirdness, I2C IRT entry has to be fixed up */
110 if (irq == PIC_I2C_1_IRQ) 130 switch (irq) {
111 irt = irt + 1; 131 case PIC_I2C_1_IRQ:
132 irt = irt + 1; break;
133 case PIC_I2C_2_IRQ:
134 irt = irt + 2; break;
135 case PIC_I2C_3_IRQ:
136 irt = irt + 3; break;
137 }
112 } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) { 138 } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
113 /* HW bug, PCI IRT entries are bad on early silicon, fix */ 139 /* HW bug, PCI IRT entries are bad on early silicon, fix */
114 irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ); 140 irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);
@@ -126,19 +152,160 @@ unsigned int nlm_get_core_frequency(int node, int core)
126 152
127 sysbase = nlm_get_node(node)->sysbase; 153 sysbase = nlm_get_node(node)->sysbase;
128 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); 154 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
129 dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE); 155 if (cpu_is_xlpii()) {
130 pll_divf = ((rstval >> 10) & 0x7f) + 1; 156 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
131 pll_divr = ((rstval >> 8) & 0x3) + 1; 157 denom = 3;
132 ext_div = ((rstval >> 30) & 0x3) + 1; 158 } else {
133 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1; 159 dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
134 160 pll_divf = ((rstval >> 10) & 0x7f) + 1;
135 num = 800000000ULL * pll_divf; 161 pll_divr = ((rstval >> 8) & 0x3) + 1;
136 denom = 3 * pll_divr * ext_div * dfs_div; 162 ext_div = ((rstval >> 30) & 0x3) + 1;
163 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
164
165 num = 800000000ULL * pll_divf;
166 denom = 3 * pll_divr * ext_div * dfs_div;
167 }
137 do_div(num, denom); 168 do_div(num, denom);
138 return (unsigned int)num; 169 return (unsigned int)num;
139} 170}
140 171
172/* Calculate Frequency to the PIC from PLL.
173 * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
174 * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
175 */
176static unsigned int nlm_2xx_get_pic_frequency(int node)
177{
178 u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
179 u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
180 u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
181
182 sysbase = nlm_get_node(node)->sysbase;
183
184 /* Find ref_clk_base */
185 ref_clk_select =
186 (nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
187 switch (ref_clk_select) {
188 case 0:
189 ref_clk = 200000000ULL;
190 ref_div = 3;
191 break;
192 case 1:
193 ref_clk = 100000000ULL;
194 ref_div = 1;
195 break;
196 case 2:
197 ref_clk = 125000000ULL;
198 ref_div = 1;
199 break;
200 case 3:
201 ref_clk = 400000000ULL;
202 ref_div = 3;
203 break;
204 }
205
206 /* Find the clock source PLL device for PIC */
207 reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
208 switch (reg_select) {
209 case 0:
210 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
211 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
212 break;
213 case 1:
214 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
215 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
216 break;
217 case 2:
218 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
219 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
220 break;
221 case 3:
222 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
223 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
224 break;
225 }
226
227 vco_post_div = (ctrl_val0 >> 5) & 0x7;
228 pll_post_div = (ctrl_val0 >> 24) & 0x7;
229 mdiv = ctrl_val2 & 0xff;
230 fdiv = (ctrl_val2 >> 8) & 0xfff;
231
232 /* Find PLL post divider value */
233 switch (pll_post_div) {
234 case 1:
235 pll_post_div = 2;
236 break;
237 case 3:
238 pll_post_div = 4;
239 break;
240 case 7:
241 pll_post_div = 8;
242 break;
243 case 6:
244 pll_post_div = 16;
245 break;
246 case 0:
247 default:
248 pll_post_div = 1;
249 break;
250 }
251
252 fdiv = fdiv/(1 << 13);
253 pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
254 pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
255
256 if (pll_out_freq_den > 0)
257 do_div(pll_out_freq_num, pll_out_freq_den);
258
259 /* PIC post divider, which happens after PLL */
260 pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
261 do_div(pll_out_freq_num, 1 << pic_div);
262
263 return pll_out_freq_num;
264}
265
266unsigned int nlm_get_pic_frequency(int node)
267{
268 if (cpu_is_xlpii())
269 return nlm_2xx_get_pic_frequency(node);
270 else
271 return 133333333;
272}
273
141unsigned int nlm_get_cpu_frequency(void) 274unsigned int nlm_get_cpu_frequency(void)
142{ 275{
143 return nlm_get_core_frequency(0, 0); 276 return nlm_get_core_frequency(0, 0);
144} 277}
278
279/*
280 * Fills upto 8 pairs of entries containing the DRAM map of a node
281 * if n < 0, get dram map for all nodes
282 */
283int xlp_get_dram_map(int n, uint64_t *dram_map)
284{
285 uint64_t bridgebase, base, lim;
286 uint32_t val;
287 int i, node, rv;
288
289 /* Look only at mapping on Node 0, we don't handle crazy configs */
290 bridgebase = nlm_get_bridge_regbase(0);
291 rv = 0;
292 for (i = 0; i < 8; i++) {
293 val = nlm_read_bridge_reg(bridgebase,
294 BRIDGE_DRAM_NODE_TRANSLN(i));
295 node = (val >> 1) & 0x3;
296 if (n >= 0 && n != node)
297 continue;
298 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
299 val = (val >> 12) & 0xfffff;
300 base = (uint64_t) val << 20;
301 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
302 val = (val >> 12) & 0xfffff;
303 if (val == 0) /* BAR not used */
304 continue;
305 lim = ((uint64_t)val + 1) << 20;
306 dram_map[rv] = base;
307 dram_map[rv + 1] = lim;
308 rv += 2;
309 }
310 return rv;
311}
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 7b638f7be491..76a7131e486e 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -73,6 +73,23 @@ static void nlm_fixup_mem(void)
73 } 73 }
74} 74}
75 75
76static void __init xlp_init_mem_from_bars(void)
77{
78 uint64_t map[16];
79 int i, n;
80
81 n = xlp_get_dram_map(-1, map); /* -1: info for all nodes */
82 for (i = 0; i < n; i += 2) {
83 /* exclude 0x1000_0000-0x2000_0000, u-boot device */
84 if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
85 map[i+1] = 0x10000000;
86 if (map[i] > 0x10000000 && map[i] < 0x20000000)
87 map[i] = 0x20000000;
88
89 add_memory_region(map[i], map[i+1] - map[i], BOOT_MEM_RAM);
90 }
91}
92
76void __init plat_mem_setup(void) 93void __init plat_mem_setup(void)
77{ 94{
78 panic_timeout = 5; 95 panic_timeout = 5;
@@ -82,12 +99,23 @@ void __init plat_mem_setup(void)
82 99
83 /* memory and bootargs from DT */ 100 /* memory and bootargs from DT */
84 early_init_devtree(initial_boot_params); 101 early_init_devtree(initial_boot_params);
102
103 if (boot_mem_map.nr_map == 0) {
104 pr_info("Using DRAM BARs for memory map.\n");
105 xlp_init_mem_from_bars();
106 }
107 /* Calculate and setup wired entries for mapped kernel */
85 nlm_fixup_mem(); 108 nlm_fixup_mem();
86} 109}
87 110
88const char *get_system_type(void) 111const char *get_system_type(void)
89{ 112{
90 return "Netlogic XLP Series"; 113 switch (read_c0_prid() & 0xff00) {
114 case PRID_IMP_NETLOGIC_XLP2XX:
115 return "Broadcom XLPII Series";
116 default:
117 return "Netlogic XLP Series";
118 }
91} 119}
92 120
93void __init prom_free_prom_memory(void) 121void __init prom_free_prom_memory(void)
@@ -97,12 +125,20 @@ void __init prom_free_prom_memory(void)
97 125
98void xlp_mmu_init(void) 126void xlp_mmu_init(void)
99{ 127{
100 /* enable extended TLB and Large Fixed TLB */ 128 u32 conf4;
101 write_c0_config6(read_c0_config6() | 0x24); 129
102 130 if (cpu_is_xlpii()) {
103 /* set page mask of Fixed TLB in config7 */ 131 /* XLPII series has extended pagesize in config 4 */
104 write_c0_config7(PM_DEFAULT_MASK >> 132 conf4 = read_c0_config4() & ~0x1f00u;
105 (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); 133 write_c0_config4(conf4 | ((PAGE_SHIFT - 10) / 2 << 8));
134 } else {
135 /* enable extended TLB and Large Fixed TLB */
136 write_c0_config6(read_c0_config6() | 0x24);
137
138 /* set page mask of extended Fixed TLB in config7 */
139 write_c0_config7(PM_DEFAULT_MASK >>
140 (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
141 }
106} 142}
107 143
108void nlm_percpu_init(int hwcpuid) 144void nlm_percpu_init(int hwcpuid)
diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c
new file mode 100644
index 000000000000..36e9c22afc46
--- /dev/null
+++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c
@@ -0,0 +1,218 @@
1/*
2 * Copyright (c) 2003-2013 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/dma-mapping.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/init.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41#include <linux/irq.h>
42
43#include <asm/netlogic/common.h>
44#include <asm/netlogic/haldefs.h>
45#include <asm/netlogic/xlp-hal/iomap.h>
46#include <asm/netlogic/xlp-hal/xlp.h>
47
48#define XLPII_USB3_CTL_0 0xc0
49#define XLPII_VAUXRST BIT(0)
50#define XLPII_VCCRST BIT(1)
51#define XLPII_NUM2PORT 9
52#define XLPII_NUM3PORT 13
53#define XLPII_RTUNEREQ BIT(20)
54#define XLPII_MS_CSYSREQ BIT(21)
55#define XLPII_XS_CSYSREQ BIT(22)
56#define XLPII_RETENABLEN BIT(23)
57#define XLPII_TX2RX BIT(24)
58#define XLPII_XHCIREV BIT(25)
59#define XLPII_ECCDIS BIT(26)
60
61#define XLPII_USB3_INT_REG 0xc2
62#define XLPII_USB3_INT_MASK 0xc3
63
64#define XLPII_USB_PHY_TEST 0xc6
65#define XLPII_PRESET BIT(0)
66#define XLPII_ATERESET BIT(1)
67#define XLPII_LOOPEN BIT(2)
68#define XLPII_TESTPDHSP BIT(3)
69#define XLPII_TESTPDSSP BIT(4)
70#define XLPII_TESTBURNIN BIT(5)
71
72#define XLPII_USB_PHY_LOS_LV 0xc9
73#define XLPII_LOSLEV 0
74#define XLPII_LOSBIAS 5
75#define XLPII_SQRXTX 8
76#define XLPII_TXBOOST 11
77#define XLPII_RSLKSEL 16
78#define XLPII_FSEL 20
79
80#define XLPII_USB_RFCLK_REG 0xcc
81#define XLPII_VVLD 30
82
83#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
84#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
85
86#define nlm_xlpii_get_usb_pcibase(node, inst) \
87 nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst))
88#define nlm_xlpii_get_usb_regbase(node, inst) \
89 (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
90
91static void xlpii_usb_ack(struct irq_data *data)
92{
93 u64 port_addr;
94
95 switch (data->irq) {
96 case PIC_2XX_XHCI_0_IRQ:
97 port_addr = nlm_xlpii_get_usb_regbase(0, 1);
98 break;
99 case PIC_2XX_XHCI_1_IRQ:
100 port_addr = nlm_xlpii_get_usb_regbase(0, 2);
101 break;
102 case PIC_2XX_XHCI_2_IRQ:
103 port_addr = nlm_xlpii_get_usb_regbase(0, 3);
104 break;
105 default:
106 pr_err("No matching USB irq!\n");
107 return;
108 }
109 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
110}
111
112static void nlm_xlpii_usb_hw_reset(int node, int port)
113{
114 u64 port_addr, xhci_base, pci_base;
115 void __iomem *corebase;
116 u32 val;
117
118 port_addr = nlm_xlpii_get_usb_regbase(node, port);
119
120 /* Set frequency */
121 val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV);
122 val &= ~(0x3f << XLPII_FSEL);
123 val |= (0x27 << XLPII_FSEL);
124 nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val);
125
126 val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG);
127 val |= (1 << XLPII_VVLD);
128 nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val);
129
130 /* PHY reset */
131 val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST);
132 val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP
133 | XLPII_TESTPDSSP | XLPII_TESTBURNIN);
134 nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val);
135
136 /* Setup control register */
137 val = XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT)
138 | (1 << XLPII_NUM3PORT) | XLPII_MS_CSYSREQ | XLPII_XS_CSYSREQ
139 | XLPII_RETENABLEN | XLPII_XHCIREV;
140 nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val);
141
142 /* Enable interrupts */
143 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001);
144
145 /* Clear all interrupts */
146 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
147
148 udelay(2000);
149
150 /* XHCI configuration at PCI mem */
151 pci_base = nlm_xlpii_get_usb_pcibase(node, port);
152 xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf;
153 corebase = ioremap(xhci_base, 0x10000);
154 if (!corebase)
155 return;
156
157 writel(0x240002, corebase + 0xc2c0);
158 /* GCTL 0xc110 */
159 val = readl(corebase + 0xc110);
160 val &= ~(0x3 << 12);
161 val |= (1 << 12);
162 writel(val, corebase + 0xc110);
163 udelay(100);
164
165 /* PHYCFG 0xc200 */
166 val = readl(corebase + 0xc200);
167 val &= ~(1 << 6);
168 writel(val, corebase + 0xc200);
169 udelay(100);
170
171 /* PIPECTL 0xc2c0 */
172 val = readl(corebase + 0xc2c0);
173 val &= ~(1 << 17);
174 writel(val, corebase + 0xc2c0);
175
176 iounmap(corebase);
177}
178
179static int __init nlm_platform_xlpii_usb_init(void)
180{
181 if (!cpu_is_xlpii())
182 return 0;
183
184 pr_info("Initializing 2XX USB Interface\n");
185 nlm_xlpii_usb_hw_reset(0, 1);
186 nlm_xlpii_usb_hw_reset(0, 2);
187 nlm_xlpii_usb_hw_reset(0, 3);
188 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack);
189 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack);
190 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack);
191
192 return 0;
193}
194
195arch_initcall(nlm_platform_xlpii_usb_init);
196
197static u64 xlp_usb_dmamask = ~(u32)0;
198
199/* Fixup IRQ for USB devices on XLP the SoC PCIe bus */
200static void nlm_usb_fixup_final(struct pci_dev *dev)
201{
202 dev->dev.dma_mask = &xlp_usb_dmamask;
203 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
204 switch (dev->devfn) {
205 case 0x21:
206 dev->irq = PIC_2XX_XHCI_0_IRQ;
207 break;
208 case 0x22:
209 dev->irq = PIC_2XX_XHCI_1_IRQ;
210 break;
211 case 0x23:
212 dev->irq = PIC_2XX_XHCI_2_IRQ;
213 break;
214 }
215}
216
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
218 nlm_usb_fixup_final);
diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c
index ef3897ef0dc7..f8117985f0f8 100644
--- a/arch/mips/netlogic/xlp/usb-init.c
+++ b/arch/mips/netlogic/xlp/usb-init.c
@@ -75,8 +75,7 @@ static void nlm_usb_intr_en(int node, int port)
75 port_addr = nlm_get_usb_regbase(node, port); 75 port_addr = nlm_get_usb_regbase(node, port);
76 val = nlm_read_usb_reg(port_addr, USB_INT_EN); 76 val = nlm_read_usb_reg(port_addr, USB_INT_EN);
77 val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | 77 val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
78 USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN | 78 USB_OHCI_INTERRUPT1_EN | USB_OHCI_INTERRUPT2_EN;
79 USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
80 nlm_write_usb_reg(port_addr, USB_INT_EN, val); 79 nlm_write_usb_reg(port_addr, USB_INT_EN, val);
81} 80}
82 81
@@ -100,6 +99,9 @@ static void nlm_usb_hw_reset(int node, int port)
100 99
101static int __init nlm_platform_usb_init(void) 100static int __init nlm_platform_usb_init(void)
102{ 101{
102 if (cpu_is_xlpii())
103 return 0;
104
103 pr_info("Initializing USB Interface\n"); 105 pr_info("Initializing USB Interface\n");
104 nlm_usb_hw_reset(0, 0); 106 nlm_usb_hw_reset(0, 0);
105 nlm_usb_hw_reset(0, 3); 107 nlm_usb_hw_reset(0, 3);
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index 0cce37cbffef..682d5638dc01 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -58,10 +58,12 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
58 58
59 coremask = (1 << core); 59 coremask = (1 << core);
60 60
61 /* Enable CPU clock */ 61 /* Enable CPU clock in case of 8xx/3xx */
62 value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL); 62 if (!cpu_is_xlpii()) {
63 value &= ~coremask; 63 value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
64 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); 64 value &= ~coremask;
65 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
66 }
65 67
66 /* Remove CPU Reset */ 68 /* Remove CPU Reset */
67 value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET); 69 value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c382042911dd..719e4557e22e 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
41obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o 41obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
42obj-$(CONFIG_LANTIQ) += fixup-lantiq.o 42obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
43obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o 43obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
44obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
44obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 45obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
45obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 46obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
46obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 47obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 95c2ea815cac..59cccd95688b 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void)
586 else 586 else
587 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; 587 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
588 588
589 /* PCI I/O and PCI MEM values */
590 set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
591 ioport_resource.start = 0;
592 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
593 if (!octeon_is_pci_host()) { 589 if (!octeon_is_pci_host()) {
594 pr_notice("Not in host mode, PCI Controller not initialized\n"); 590 pr_notice("Not in host mode, PCI Controller not initialized\n");
595 return 0; 591 return 0;
596 } 592 }
597 593
594 /* PCI I/O and PCI MEM values */
595 set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
596 ioport_resource.start = 0;
597 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
598
598 pr_notice("%s Octeon big bar support\n", 599 pr_notice("%s Octeon big bar support\n",
599 (octeon_dma_bar_type == 600 (octeon_dma_bar_type ==
600 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); 601 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
new file mode 100644
index 000000000000..95c9d41382e7
--- /dev/null
+++ b/arch/mips/pci/pci-rt3883.c
@@ -0,0 +1,636 @@
1/*
2 * Ralink RT3662/RT3883 SoC PCI support
3 *
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/types.h>
14#include <linux/pci.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
22#include <linux/of_pci.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach-ralink/rt3883.h>
26#include <asm/mach-ralink/ralink_regs.h>
27
28#define RT3883_MEMORY_BASE 0x00000000
29#define RT3883_MEMORY_SIZE 0x02000000
30
31#define RT3883_PCI_REG_PCICFG 0x00
32#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
33#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
34#define RT3883_PCICFG_PCIRST BIT(1)
35#define RT3883_PCI_REG_PCIRAW 0x04
36#define RT3883_PCI_REG_PCIINT 0x08
37#define RT3883_PCI_REG_PCIENA 0x0c
38
39#define RT3883_PCI_REG_CFGADDR 0x20
40#define RT3883_PCI_REG_CFGDATA 0x24
41#define RT3883_PCI_REG_MEMBASE 0x28
42#define RT3883_PCI_REG_IOBASE 0x2c
43#define RT3883_PCI_REG_ARBCTL 0x80
44
45#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
46#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
47#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
48#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
49#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
50#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
51#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
52
53#define RT3883_PCI_MODE_NONE 0
54#define RT3883_PCI_MODE_PCI BIT(0)
55#define RT3883_PCI_MODE_PCIE BIT(1)
56#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
57
58#define RT3883_PCI_IRQ_COUNT 32
59
60#define RT3883_P2P_BR_DEVNUM 1
61
62struct rt3883_pci_controller {
63 void __iomem *base;
64 spinlock_t lock;
65
66 struct device_node *intc_of_node;
67 struct irq_domain *irq_domain;
68
69 struct pci_controller pci_controller;
70 struct resource io_res;
71 struct resource mem_res;
72
73 bool pcie_ready;
74};
75
76static inline struct rt3883_pci_controller *
77pci_bus_to_rt3883_controller(struct pci_bus *bus)
78{
79 struct pci_controller *hose;
80
81 hose = (struct pci_controller *) bus->sysdata;
82 return container_of(hose, struct rt3883_pci_controller, pci_controller);
83}
84
85static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
86 unsigned reg)
87{
88 return ioread32(rpc->base + reg);
89}
90
91static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
92 u32 val, unsigned reg)
93{
94 iowrite32(val, rpc->base + reg);
95}
96
97static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
98 unsigned int func, unsigned int where)
99{
100 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
101 0x80000000;
102}
103
104static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
105 unsigned bus, unsigned slot,
106 unsigned func, unsigned reg)
107{
108 unsigned long flags;
109 u32 address;
110 u32 ret;
111
112 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
113
114 spin_lock_irqsave(&rpc->lock, flags);
115 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
116 ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
117 spin_unlock_irqrestore(&rpc->lock, flags);
118
119 return ret;
120}
121
122static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
123 unsigned bus, unsigned slot,
124 unsigned func, unsigned reg, u32 val)
125{
126 unsigned long flags;
127 u32 address;
128
129 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
130
131 spin_lock_irqsave(&rpc->lock, flags);
132 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
133 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
134 spin_unlock_irqrestore(&rpc->lock, flags);
135}
136
137static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
138{
139 struct rt3883_pci_controller *rpc;
140 u32 pending;
141
142 rpc = irq_get_handler_data(irq);
143
144 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
145 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
146
147 if (!pending) {
148 spurious_interrupt();
149 return;
150 }
151
152 while (pending) {
153 unsigned bit = __ffs(pending);
154
155 irq = irq_find_mapping(rpc->irq_domain, bit);
156 generic_handle_irq(irq);
157
158 pending &= ~BIT(bit);
159 }
160}
161
162static void rt3883_pci_irq_unmask(struct irq_data *d)
163{
164 struct rt3883_pci_controller *rpc;
165 u32 t;
166
167 rpc = irq_data_get_irq_chip_data(d);
168
169 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
170 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
171 /* flush write */
172 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
173}
174
175static void rt3883_pci_irq_mask(struct irq_data *d)
176{
177 struct rt3883_pci_controller *rpc;
178 u32 t;
179
180 rpc = irq_data_get_irq_chip_data(d);
181
182 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
183 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
184 /* flush write */
185 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
186}
187
188static struct irq_chip rt3883_pci_irq_chip = {
189 .name = "RT3883 PCI",
190 .irq_mask = rt3883_pci_irq_mask,
191 .irq_unmask = rt3883_pci_irq_unmask,
192 .irq_mask_ack = rt3883_pci_irq_mask,
193};
194
195static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
196 irq_hw_number_t hw)
197{
198 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
199 irq_set_chip_data(irq, d->host_data);
200
201 return 0;
202}
203
204static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
205 .map = rt3883_pci_irq_map,
206 .xlate = irq_domain_xlate_onecell,
207};
208
209static int rt3883_pci_irq_init(struct device *dev,
210 struct rt3883_pci_controller *rpc)
211{
212 int irq;
213
214 irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
215 if (irq == 0) {
216 dev_err(dev, "%s has no IRQ",
217 of_node_full_name(rpc->intc_of_node));
218 return -EINVAL;
219 }
220
221 /* disable all interrupts */
222 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
223
224 rpc->irq_domain =
225 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
226 &rt3883_pci_irq_domain_ops,
227 rpc);
228 if (!rpc->irq_domain) {
229 dev_err(dev, "unable to add IRQ domain\n");
230 return -ENODEV;
231 }
232
233 irq_set_handler_data(irq, rpc);
234 irq_set_chained_handler(irq, rt3883_pci_irq_handler);
235
236 return 0;
237}
238
239static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
240 int where, int size, u32 *val)
241{
242 struct rt3883_pci_controller *rpc;
243 unsigned long flags;
244 u32 address;
245 u32 data;
246
247 rpc = pci_bus_to_rt3883_controller(bus);
248
249 if (!rpc->pcie_ready && bus->number == 1)
250 return PCIBIOS_DEVICE_NOT_FOUND;
251
252 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
253 PCI_FUNC(devfn), where);
254
255 spin_lock_irqsave(&rpc->lock, flags);
256 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
257 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
258 spin_unlock_irqrestore(&rpc->lock, flags);
259
260 switch (size) {
261 case 1:
262 *val = (data >> ((where & 3) << 3)) & 0xff;
263 break;
264 case 2:
265 *val = (data >> ((where & 3) << 3)) & 0xffff;
266 break;
267 case 4:
268 *val = data;
269 break;
270 }
271
272 return PCIBIOS_SUCCESSFUL;
273}
274
275static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
276 int where, int size, u32 val)
277{
278 struct rt3883_pci_controller *rpc;
279 unsigned long flags;
280 u32 address;
281 u32 data;
282
283 rpc = pci_bus_to_rt3883_controller(bus);
284
285 if (!rpc->pcie_ready && bus->number == 1)
286 return PCIBIOS_DEVICE_NOT_FOUND;
287
288 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
289 PCI_FUNC(devfn), where);
290
291 spin_lock_irqsave(&rpc->lock, flags);
292 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
293 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
294
295 switch (size) {
296 case 1:
297 data = (data & ~(0xff << ((where & 3) << 3))) |
298 (val << ((where & 3) << 3));
299 break;
300 case 2:
301 data = (data & ~(0xffff << ((where & 3) << 3))) |
302 (val << ((where & 3) << 3));
303 break;
304 case 4:
305 data = val;
306 break;
307 }
308
309 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
310 spin_unlock_irqrestore(&rpc->lock, flags);
311
312 return PCIBIOS_SUCCESSFUL;
313}
314
315static struct pci_ops rt3883_pci_ops = {
316 .read = rt3883_pci_config_read,
317 .write = rt3883_pci_config_write,
318};
319
320static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
321{
322 u32 syscfg1;
323 u32 rstctrl;
324 u32 clkcfg1;
325 u32 t;
326
327 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
328 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
329 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
330
331 if (mode & RT3883_PCI_MODE_PCIE) {
332 rstctrl |= RT3883_RSTCTRL_PCIE;
333 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
334
335 /* setup PCI PAD drive mode */
336 syscfg1 &= ~(0x30);
337 syscfg1 |= (2 << 4);
338 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
339
340 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
341 t &= ~BIT(31);
342 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
343
344 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
345 t &= 0x80ffffff;
346 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
347
348 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
349 t |= 0xa << 24;
350 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
351
352 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
353 t |= BIT(31);
354 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
355
356 msleep(50);
357
358 rstctrl &= ~RT3883_RSTCTRL_PCIE;
359 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
360 }
361
362 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
363
364 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
365
366 if (mode & RT3883_PCI_MODE_PCI) {
367 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
368 rstctrl &= ~RT3883_RSTCTRL_PCI;
369 }
370
371 if (mode & RT3883_PCI_MODE_PCIE) {
372 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
373 rstctrl &= ~RT3883_RSTCTRL_PCIE;
374 }
375
376 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
377 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
378 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
379
380 msleep(500);
381
382 /*
383 * setup the device number of the P2P bridge
384 * and de-assert the reset line
385 */
386 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
387 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
388
389 /* flush write */
390 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
391 msleep(500);
392
393 if (mode & RT3883_PCI_MODE_PCIE) {
394 msleep(500);
395
396 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
397
398 rpc->pcie_ready = t & BIT(0);
399
400 if (!rpc->pcie_ready) {
401 /* reset the PCIe block */
402 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
403 t |= RT3883_RSTCTRL_PCIE;
404 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
405 t &= ~RT3883_RSTCTRL_PCIE;
406 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
407
408 /* turn off PCIe clock */
409 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
410 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
411 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
412
413 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
414 t &= ~0xf000c080;
415 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
416 }
417 }
418
419 /* enable PCI arbiter */
420 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
421}
422
423static int rt3883_pci_probe(struct platform_device *pdev)
424{
425 struct rt3883_pci_controller *rpc;
426 struct device *dev = &pdev->dev;
427 struct device_node *np = dev->of_node;
428 struct resource *res;
429 struct device_node *child;
430 u32 val;
431 int err;
432 int mode;
433
434 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
435 if (!rpc)
436 return -ENOMEM;
437
438 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
439 if (!res)
440 return -EINVAL;
441
442 rpc->base = devm_ioremap_resource(dev, res);
443 if (IS_ERR(rpc->base))
444 return PTR_ERR(rpc->base);
445
446 /* find the interrupt controller child node */
447 for_each_child_of_node(np, child) {
448 if (of_get_property(child, "interrupt-controller", NULL) &&
449 of_node_get(child)) {
450 rpc->intc_of_node = child;
451 break;
452 }
453 }
454
455 if (!rpc->intc_of_node) {
456 dev_err(dev, "%s has no %s child node",
457 of_node_full_name(rpc->intc_of_node),
458 "interrupt controller");
459 return -EINVAL;
460 }
461
462 /* find the PCI host bridge child node */
463 for_each_child_of_node(np, child) {
464 if (child->type &&
465 of_node_cmp(child->type, "pci") == 0 &&
466 of_node_get(child)) {
467 rpc->pci_controller.of_node = child;
468 break;
469 }
470 }
471
472 if (!rpc->pci_controller.of_node) {
473 dev_err(dev, "%s has no %s child node",
474 of_node_full_name(rpc->intc_of_node),
475 "PCI host bridge");
476 err = -EINVAL;
477 goto err_put_intc_node;
478 }
479
480 mode = RT3883_PCI_MODE_NONE;
481 for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
482 int devfn;
483
484 if (!child->type ||
485 of_node_cmp(child->type, "pci") != 0)
486 continue;
487
488 devfn = of_pci_get_devfn(child);
489 if (devfn < 0)
490 continue;
491
492 switch (PCI_SLOT(devfn)) {
493 case 1:
494 mode |= RT3883_PCI_MODE_PCIE;
495 break;
496
497 case 17:
498 case 18:
499 mode |= RT3883_PCI_MODE_PCI;
500 break;
501 }
502 }
503
504 if (mode == RT3883_PCI_MODE_NONE) {
505 dev_err(dev, "unable to determine PCI mode\n");
506 err = -EINVAL;
507 goto err_put_hb_node;
508 }
509
510 dev_info(dev, "mode:%s%s\n",
511 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
512 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
513
514 rt3883_pci_preinit(rpc, mode);
515
516 rpc->pci_controller.pci_ops = &rt3883_pci_ops;
517 rpc->pci_controller.io_resource = &rpc->io_res;
518 rpc->pci_controller.mem_resource = &rpc->mem_res;
519
520 /* Load PCI I/O and memory resources from DT */
521 pci_load_of_ranges(&rpc->pci_controller,
522 rpc->pci_controller.of_node);
523
524 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
525 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
526
527 ioport_resource.start = rpc->io_res.start;
528 ioport_resource.end = rpc->io_res.end;
529
530 /* PCI */
531 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
532 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
533 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
534 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
535 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
536
537 /* PCIe */
538 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
539 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
540 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
541 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
542 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
543
544 err = rt3883_pci_irq_init(dev, rpc);
545 if (err)
546 goto err_put_hb_node;
547
548 /* PCIe */
549 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
550 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
551 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
552
553 /* PCI */
554 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
555 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
556 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
557
558 if (mode == RT3883_PCI_MODE_PCIE) {
559 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
560 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
561
562 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
563 PCI_BASE_ADDRESS_0,
564 RT3883_MEMORY_BASE);
565 /* flush write */
566 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
567 PCI_BASE_ADDRESS_0);
568 } else {
569 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
570 PCI_IO_BASE, 0x00000101);
571 }
572
573 register_pci_controller(&rpc->pci_controller);
574
575 return 0;
576
577err_put_hb_node:
578 of_node_put(rpc->pci_controller.of_node);
579err_put_intc_node:
580 of_node_put(rpc->intc_of_node);
581 return err;
582}
583
584int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
585{
586 struct of_irq dev_irq;
587 int err;
588 int irq;
589
590 err = of_irq_map_pci(dev, &dev_irq);
591 if (err) {
592 pr_err("pci %s: unable to get irq map, err=%d\n",
593 pci_name((struct pci_dev *) dev), err);
594 return 0;
595 }
596
597 irq = irq_create_of_mapping(dev_irq.controller,
598 dev_irq.specifier,
599 dev_irq.size);
600
601 if (irq == 0)
602 pr_crit("pci %s: no irq found for pin %u\n",
603 pci_name((struct pci_dev *) dev), pin);
604 else
605 pr_info("pci %s: using irq %d for pin %u\n",
606 pci_name((struct pci_dev *) dev), irq, pin);
607
608 return irq;
609}
610
611int pcibios_plat_dev_init(struct pci_dev *dev)
612{
613 return 0;
614}
615
616static const struct of_device_id rt3883_pci_ids[] = {
617 { .compatible = "ralink,rt3883-pci" },
618 {},
619};
620MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
621
622static struct platform_driver rt3883_pci_driver = {
623 .probe = rt3883_pci_probe,
624 .driver = {
625 .name = "rt3883-pci",
626 .owner = THIS_MODULE,
627 .of_match_table = of_match_ptr(rt3883_pci_ids),
628 },
629};
630
631static int __init rt3883_pci_init(void)
632{
633 return platform_driver_register(&rt3883_pci_driver);
634}
635
636postcore_initcall(rt3883_pci_init);
diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig
index 1a1b03ea6398..dd91fbacbcba 100644
--- a/arch/mips/powertv/Kconfig
+++ b/arch/mips/powertv/Kconfig
@@ -1,14 +1,7 @@
1config BOOTLOADER_DRIVER
2 bool "PowerTV Bootloader Driver Support"
3 default n
4 depends on POWERTV
5 help
6 Use this option if you want to load bootloader driver.
7
8config BOOTLOADER_FAMILY 1config BOOTLOADER_FAMILY
9 string "POWERTV Bootloader Family string" 2 string "POWERTV Bootloader Family string"
10 default "85" 3 default "85"
11 depends on POWERTV && !BOOTLOADER_DRIVER 4 depends on POWERTV
12 help 5 help
13 This value should be specified when the bootloader driver is disabled 6 This value should be specified when the bootloader driver is disabled
14 and must be exactly two characters long. Families supported are: 7 and must be exactly two characters long. Families supported are:
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index 0238af1ba503..8380605d597d 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -147,20 +147,10 @@ static __init noinline void platform_set_family(void)
147 if (check_forcefamily(forced_family) == 0) 147 if (check_forcefamily(forced_family) == 0)
148 bootldr_family = BOOTLDRFAMILY(forced_family[0], 148 bootldr_family = BOOTLDRFAMILY(forced_family[0],
149 forced_family[1]); 149 forced_family[1]);
150 else { 150 else
151
152#ifdef CONFIG_BOOTLOADER_DRIVER
153 bootldr_family = (unsigned short) kbldr_GetSWFamily();
154#else
155#if defined(CONFIG_BOOTLOADER_FAMILY)
156 bootldr_family = (unsigned short) BOOTLDRFAMILY( 151 bootldr_family = (unsigned short) BOOTLDRFAMILY(
157 CONFIG_BOOTLOADER_FAMILY[0], 152 CONFIG_BOOTLOADER_FAMILY[0],
158 CONFIG_BOOTLOADER_FAMILY[1]); 153 CONFIG_BOOTLOADER_FAMILY[1]);
159#else
160#error "Unknown Bootloader Family"
161#endif
162#endif
163 }
164 154
165 pr_info("Bootloader Family = 0x%04X\n", bootldr_family); 155 pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
166 156
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
index a01baff52cae..498926377e51 100644
--- a/arch/mips/powertv/init.c
+++ b/arch/mips/powertv/init.c
@@ -87,8 +87,4 @@ void __init prom_init(void)
87 87
88 configure_platform(); 88 configure_platform();
89 prom_meminit(); 89 prom_meminit();
90
91#ifndef CONFIG_BOOTLOADER_DRIVER
92 pr_info("\nBootloader driver isn't loaded...\n");
93#endif
94} 90}
diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c
index 0007652cb774..11c32fbf2784 100644
--- a/arch/mips/powertv/reset.c
+++ b/arch/mips/powertv/reset.c
@@ -21,24 +21,12 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <asm/reboot.h> /* Not included by linux/reboot.h */ 22#include <asm/reboot.h> /* Not included by linux/reboot.h */
23 23
24#ifdef CONFIG_BOOTLOADER_DRIVER
25#include <asm/mach-powertv/kbldr.h>
26#endif
27
28#include <asm/mach-powertv/asic_regs.h> 24#include <asm/mach-powertv/asic_regs.h>
29#include "reset.h" 25#include "reset.h"
30 26
31static void mips_machine_restart(char *command) 27static void mips_machine_restart(char *command)
32{ 28{
33#ifdef CONFIG_BOOTLOADER_DRIVER
34 /*
35 * Call the bootloader's reset function to ensure
36 * that persistent data is flushed before hard reset
37 */
38 kbldr_SetCauseAndReset();
39#else
40 writel(0x1, asic_reg_addr(watchdog)); 29 writel(0x1, asic_reg_addr(watchdog));
41#endif
42} 30}
43 31
44void mips_reboot_setup(void) 32void mips_reboot_setup(void)
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 026e823d871d..424f03496d14 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -1,5 +1,12 @@
1if RALINK 1if RALINK
2 2
3config CLKEVT_RT3352
4 bool
5 depends on SOC_RT305X || SOC_MT7620
6 default y
7 select CLKSRC_OF
8 select CLKSRC_MMIO
9
3choice 10choice
4 prompt "Ralink SoC selection" 11 prompt "Ralink SoC selection"
5 default SOC_RT305X 12 default SOC_RT305X
@@ -19,9 +26,12 @@ choice
19 bool "RT3883" 26 bool "RT3883"
20 select USB_ARCH_HAS_OHCI 27 select USB_ARCH_HAS_OHCI
21 select USB_ARCH_HAS_EHCI 28 select USB_ARCH_HAS_EHCI
29 select HW_HAS_PCI
22 30
23 config SOC_MT7620 31 config SOC_MT7620
24 bool "MT7620" 32 bool "MT7620"
33 select USB_ARCH_HAS_OHCI
34 select USB_ARCH_HAS_EHCI
25 35
26endchoice 36endchoice
27 37
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 38cf1a880aaa..98ae349827be 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -6,7 +6,9 @@
6# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 6# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7# Copyright (C) 2013 John Crispin <blogic@openwrt.org> 7# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8 8
9obj-y := prom.o of.o reset.o clk.o irq.o 9obj-y := prom.o of.o reset.o clk.o irq.o timer.o
10
11obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
10 12
11obj-$(CONFIG_SOC_RT288X) += rt288x.o 13obj-$(CONFIG_SOC_RT288X) += rt288x.o
12obj-$(CONFIG_SOC_RT305X) += rt305x.o 14obj-$(CONFIG_SOC_RT305X) += rt305x.o
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
index cda4b6645c50..6d9c8c499f98 100644
--- a/arch/mips/ralink/Platform
+++ b/arch/mips/ralink/Platform
@@ -26,3 +26,4 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt
26# Ralink MT7620 26# Ralink MT7620
27# 27#
28load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000 28load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
29cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c
new file mode 100644
index 000000000000..cc17566d1934
--- /dev/null
+++ b/arch/mips/ralink/cevt-rt3352.c
@@ -0,0 +1,145 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 by John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/interrupt.h>
12#include <linux/reset.h>
13#include <linux/init.h>
14#include <linux/time.h>
15#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18
19#include <asm/mach-ralink/ralink_regs.h>
20
21#define SYSTICK_FREQ (50 * 1000)
22
23#define SYSTICK_CONFIG 0x00
24#define SYSTICK_COMPARE 0x04
25#define SYSTICK_COUNT 0x08
26
27/* route systick irq to mips irq 7 instead of the r4k-timer */
28#define CFG_EXT_STK_EN 0x2
29/* enable the counter */
30#define CFG_CNT_EN 0x1
31
32struct systick_device {
33 void __iomem *membase;
34 struct clock_event_device dev;
35 int irq_requested;
36 int freq_scale;
37};
38
39static void systick_set_clock_mode(enum clock_event_mode mode,
40 struct clock_event_device *evt);
41
42static int systick_next_event(unsigned long delta,
43 struct clock_event_device *evt)
44{
45 struct systick_device *sdev;
46 u32 count;
47
48 sdev = container_of(evt, struct systick_device, dev);
49 count = ioread32(sdev->membase + SYSTICK_COUNT);
50 count = (count + delta) % SYSTICK_FREQ;
51 iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
52
53 return 0;
54}
55
56static void systick_event_handler(struct clock_event_device *dev)
57{
58 /* noting to do here */
59}
60
61static irqreturn_t systick_interrupt(int irq, void *dev_id)
62{
63 struct clock_event_device *dev = (struct clock_event_device *) dev_id;
64
65 dev->event_handler(dev);
66
67 return IRQ_HANDLED;
68}
69
70static struct systick_device systick = {
71 .dev = {
72 /*
73 * cevt-r4k uses 300, make sure systick
74 * gets used if available
75 */
76 .rating = 310,
77 .features = CLOCK_EVT_FEAT_ONESHOT,
78 .set_next_event = systick_next_event,
79 .set_mode = systick_set_clock_mode,
80 .event_handler = systick_event_handler,
81 },
82};
83
84static struct irqaction systick_irqaction = {
85 .handler = systick_interrupt,
86 .flags = IRQF_PERCPU | IRQF_TIMER,
87 .dev_id = &systick.dev,
88};
89
90static void systick_set_clock_mode(enum clock_event_mode mode,
91 struct clock_event_device *evt)
92{
93 struct systick_device *sdev;
94
95 sdev = container_of(evt, struct systick_device, dev);
96
97 switch (mode) {
98 case CLOCK_EVT_MODE_ONESHOT:
99 if (!sdev->irq_requested)
100 setup_irq(systick.dev.irq, &systick_irqaction);
101 sdev->irq_requested = 1;
102 iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
103 systick.membase + SYSTICK_CONFIG);
104 break;
105
106 case CLOCK_EVT_MODE_SHUTDOWN:
107 if (sdev->irq_requested)
108 free_irq(systick.dev.irq, &systick_irqaction);
109 sdev->irq_requested = 0;
110 iowrite32(0, systick.membase + SYSTICK_CONFIG);
111 break;
112
113 default:
114 pr_err("%s: Unhandeled mips clock_mode\n", systick.dev.name);
115 break;
116 }
117}
118
119static void __init ralink_systick_init(struct device_node *np)
120{
121 systick.membase = of_iomap(np, 0);
122 if (!systick.membase)
123 return;
124
125 systick_irqaction.name = np->name;
126 systick.dev.name = np->name;
127 clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
128 systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
129 systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
130 systick.dev.irq = irq_of_parse_and_map(np, 0);
131 if (!systick.dev.irq) {
132 pr_err("%s: request_irq failed", np->name);
133 return;
134 }
135
136 clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
137 SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up);
138
139 clockevents_register_device(&systick.dev);
140
141 pr_info("%s: runing - mult: %d, shift: %d\n",
142 np->name, systick.dev.mult, systick.dev.shift);
143}
144
145CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index 8dfa22ff300b..bba0cdfd83bc 100644
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -69,4 +69,5 @@ void __init plat_time_init(void)
69 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); 69 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
70 mips_hpt_frequency = clk_get_rate(clk) / 2; 70 mips_hpt_frequency = clk_get_rate(clk) / 2;
71 clk_put(clk); 71 clk_put(clk);
72 clocksource_of_init();
72} 73}
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
index 83144c3fc5ac..42dfd6100a2d 100644
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -46,6 +46,8 @@ extern void ralink_of_remap(void);
46extern void ralink_clk_init(void); 46extern void ralink_clk_init(void);
47extern void ralink_clk_add(const char *dev, unsigned long rate); 47extern void ralink_clk_add(const char *dev, unsigned long rate);
48 48
49extern void ralink_rst_init(void);
50
49extern void prom_soc_init(struct ralink_soc_info *soc_info); 51extern void prom_soc_init(struct ralink_soc_info *soc_info);
50 52
51__iomem void *plat_of_remap_node(const char *node); 53__iomem void *plat_of_remap_node(const char *node);
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 0018b1a661f6..d217509e5300 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -23,9 +23,6 @@
23/* does the board have sdram or ddram */ 23/* does the board have sdram or ddram */
24static int dram_type; 24static int dram_type;
25 25
26/* the pll dividers */
27static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
28
29static struct ralink_pinmux_grp mode_mux[] = { 26static struct ralink_pinmux_grp mode_mux[] = {
30 { 27 {
31 .name = "i2c", 28 .name = "i2c",
@@ -140,34 +137,189 @@ struct ralink_pinmux rt_gpio_pinmux = {
140 .uart_mask = MT7620_GPIO_MODE_UART0_MASK, 137 .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
141}; 138};
142 139
143void __init ralink_clk_init(void) 140static __init u32
141mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
144{ 142{
145 unsigned long cpu_rate, sys_rate; 143 u64 t;
146 u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
147 u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
148 u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
149 u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
150
151 if (cpu_clk) {
152 cpu_rate = 480000000;
153 } else if (!swconfig) {
154 cpu_rate = 600000000;
155 } else {
156 u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
157 u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
158 144
159 cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000; 145 t = ref_rate;
160 } 146 t *= mul;
147 do_div(t, div);
148
149 return t;
150}
151
152#define MHZ(x) ((x) * 1000 * 1000)
153
154static __init unsigned long
155mt7620_get_xtal_rate(void)
156{
157 u32 reg;
158
159 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
160 if (reg & SYSCFG0_XTAL_FREQ_SEL)
161 return MHZ(40);
162
163 return MHZ(20);
164}
165
166static __init unsigned long
167mt7620_get_periph_rate(unsigned long xtal_rate)
168{
169 u32 reg;
170
171 reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
172 if (reg & CLKCFG0_PERI_CLK_SEL)
173 return xtal_rate;
174
175 return MHZ(40);
176}
177
178static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
179
180static __init unsigned long
181mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
182{
183 u32 reg;
184 u32 mul;
185 u32 div;
186
187 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
188 if (reg & CPLL_CFG0_BYPASS_REF_CLK)
189 return xtal_rate;
190
191 if ((reg & CPLL_CFG0_SW_CFG) == 0)
192 return MHZ(600);
193
194 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
195 CPLL_CFG0_PLL_MULT_RATIO_MASK;
196 mul += 24;
197 if (reg & CPLL_CFG0_LC_CURFCK)
198 mul *= 2;
199
200 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
201 CPLL_CFG0_PLL_DIV_RATIO_MASK;
202
203 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
204
205 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
206}
207
208static __init unsigned long
209mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
210{
211 u32 reg;
212
213 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
214 if (reg & CPLL_CFG1_CPU_AUX1)
215 return xtal_rate;
216
217 if (reg & CPLL_CFG1_CPU_AUX0)
218 return MHZ(480);
161 219
220 return cpu_pll_rate;
221}
222
223static __init unsigned long
224mt7620_get_cpu_rate(unsigned long pll_rate)
225{
226 u32 reg;
227 u32 mul;
228 u32 div;
229
230 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
231
232 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
233 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
234 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
235
236 return mt7620_calc_rate(pll_rate, mul, div);
237}
238
239static const u32 mt7620_ocp_dividers[16] __initconst = {
240 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
241 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
242 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
243 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
244 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
245};
246
247static __init unsigned long
248mt7620_get_dram_rate(unsigned long pll_rate)
249{
162 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) 250 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
163 sys_rate = cpu_rate / 4; 251 return pll_rate / 4;
164 else 252
165 sys_rate = cpu_rate / 3; 253 return pll_rate / 3;
254}
255
256static __init unsigned long
257mt7620_get_sys_rate(unsigned long cpu_rate)
258{
259 u32 reg;
260 u32 ocp_ratio;
261 u32 div;
262
263 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
264
265 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
266 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
267
268 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
269 return cpu_rate;
270
271 div = mt7620_ocp_dividers[ocp_ratio];
272 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
273 return cpu_rate;
274
275 return cpu_rate / div;
276}
277
278void __init ralink_clk_init(void)
279{
280 unsigned long xtal_rate;
281 unsigned long cpu_pll_rate;
282 unsigned long pll_rate;
283 unsigned long cpu_rate;
284 unsigned long sys_rate;
285 unsigned long dram_rate;
286 unsigned long periph_rate;
287
288 xtal_rate = mt7620_get_xtal_rate();
289
290 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
291 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
292
293 cpu_rate = mt7620_get_cpu_rate(pll_rate);
294 dram_rate = mt7620_get_dram_rate(pll_rate);
295 sys_rate = mt7620_get_sys_rate(cpu_rate);
296 periph_rate = mt7620_get_periph_rate(xtal_rate);
297
298#define RFMT(label) label ":%lu.%03luMHz "
299#define RINT(x) ((x) / 1000000)
300#define RFRAC(x) (((x) / 1000) % 1000)
301
302 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
303 RINT(xtal_rate), RFRAC(xtal_rate),
304 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
305 RINT(pll_rate), RFRAC(pll_rate));
306
307 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
308 RINT(cpu_rate), RFRAC(cpu_rate),
309 RINT(dram_rate), RFRAC(dram_rate),
310 RINT(sys_rate), RFRAC(sys_rate),
311 RINT(periph_rate), RFRAC(periph_rate));
312
313#undef RFRAC
314#undef RINT
315#undef RFMT
166 316
167 ralink_clk_add("cpu", cpu_rate); 317 ralink_clk_add("cpu", cpu_rate);
168 ralink_clk_add("10000100.timer", 40000000); 318 ralink_clk_add("10000100.timer", periph_rate);
169 ralink_clk_add("10000500.uart", 40000000); 319 ralink_clk_add("10000120.watchdog", periph_rate);
170 ralink_clk_add("10000c00.uartlite", 40000000); 320 ralink_clk_add("10000500.uart", periph_rate);
321 ralink_clk_add("10000b00.spi", sys_rate);
322 ralink_clk_add("10000c00.uartlite", periph_rate);
171} 323}
172 324
173void __init ralink_of_remap(void) 325void __init ralink_of_remap(void)
@@ -214,16 +366,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
214 366
215 switch (dram_type) { 367 switch (dram_type) {
216 case SYSCFG0_DRAM_TYPE_SDRAM: 368 case SYSCFG0_DRAM_TYPE_SDRAM:
369 pr_info("Board has SDRAM\n");
217 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 370 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
218 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 371 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
219 break; 372 break;
220 373
221 case SYSCFG0_DRAM_TYPE_DDR1: 374 case SYSCFG0_DRAM_TYPE_DDR1:
375 pr_info("Board has DDR1\n");
222 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 376 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
223 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 377 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
224 break; 378 break;
225 379
226 case SYSCFG0_DRAM_TYPE_DDR2: 380 case SYSCFG0_DRAM_TYPE_DDR2:
381 pr_info("Board has DDR2\n");
227 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 382 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
228 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 383 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
229 break; 384 break;
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index f25ea5b45051..ce38d11f9da5 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -110,6 +110,9 @@ static int __init plat_of_setup(void)
110 if (of_platform_populate(NULL, of_ids, NULL, NULL)) 110 if (of_platform_populate(NULL, of_ids, NULL, NULL))
111 panic("failed to populate DT\n"); 111 panic("failed to populate DT\n");
112 112
113 /* make sure ithat the reset controller is setup early */
114 ralink_rst_init();
115
113 return 0; 116 return 0;
114} 117}
115 118
diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
index 22120e512e7e..55c7ec59df3c 100644
--- a/arch/mips/ralink/reset.c
+++ b/arch/mips/ralink/reset.c
@@ -10,6 +10,8 @@
10 10
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/of.h>
14#include <linux/reset-controller.h>
13 15
14#include <asm/reboot.h> 16#include <asm/reboot.h>
15 17
@@ -19,6 +21,66 @@
19#define SYSC_REG_RESET_CTRL 0x034 21#define SYSC_REG_RESET_CTRL 0x034
20#define RSTCTL_RESET_SYSTEM BIT(0) 22#define RSTCTL_RESET_SYSTEM BIT(0)
21 23
24static int ralink_assert_device(struct reset_controller_dev *rcdev,
25 unsigned long id)
26{
27 u32 val;
28
29 if (id < 8)
30 return -1;
31
32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
33 val |= BIT(id);
34 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
35
36 return 0;
37}
38
39static int ralink_deassert_device(struct reset_controller_dev *rcdev,
40 unsigned long id)
41{
42 u32 val;
43
44 if (id < 8)
45 return -1;
46
47 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
48 val &= ~BIT(id);
49 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
50
51 return 0;
52}
53
54static int ralink_reset_device(struct reset_controller_dev *rcdev,
55 unsigned long id)
56{
57 ralink_assert_device(rcdev, id);
58 return ralink_deassert_device(rcdev, id);
59}
60
61static struct reset_control_ops reset_ops = {
62 .reset = ralink_reset_device,
63 .assert = ralink_assert_device,
64 .deassert = ralink_deassert_device,
65};
66
67static struct reset_controller_dev reset_dev = {
68 .ops = &reset_ops,
69 .owner = THIS_MODULE,
70 .nr_resets = 32,
71 .of_reset_n_cells = 1,
72};
73
74void ralink_rst_init(void)
75{
76 reset_dev.of_node = of_find_compatible_node(NULL, NULL,
77 "ralink,rt2880-reset");
78 if (!reset_dev.of_node)
79 pr_err("Failed to find reset controller node");
80 else
81 reset_controller_register(&reset_dev);
82}
83
22static void ralink_restart(char *command) 84static void ralink_restart(char *command)
23{ 85{
24 local_irq_disable(); 86 local_irq_disable();
diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
new file mode 100644
index 000000000000..e49241a2c39a
--- /dev/null
+++ b/arch/mips/ralink/timer.c
@@ -0,0 +1,185 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
7*/
8
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/interrupt.h>
12#include <linux/timer.h>
13#include <linux/of_gpio.h>
14#include <linux/clk.h>
15
16#include <asm/mach-ralink/ralink_regs.h>
17
18#define TIMER_REG_TMRSTAT 0x00
19#define TIMER_REG_TMR0LOAD 0x10
20#define TIMER_REG_TMR0CTL 0x18
21
22#define TMRSTAT_TMR0INT BIT(0)
23
24#define TMR0CTL_ENABLE BIT(7)
25#define TMR0CTL_MODE_PERIODIC BIT(4)
26#define TMR0CTL_PRESCALER 1
27#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
28#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
29
30struct rt_timer {
31 struct device *dev;
32 void __iomem *membase;
33 int irq;
34 unsigned long timer_freq;
35 unsigned long timer_div;
36};
37
38static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
39{
40 __raw_writel(val, rt->membase + reg);
41}
42
43static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
44{
45 return __raw_readl(rt->membase + reg);
46}
47
48static irqreturn_t rt_timer_irq(int irq, void *_rt)
49{
50 struct rt_timer *rt = (struct rt_timer *) _rt;
51
52 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
53 rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
54
55 return IRQ_HANDLED;
56}
57
58
59static int rt_timer_request(struct rt_timer *rt)
60{
61 int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
62 dev_name(rt->dev), rt);
63 if (err) {
64 dev_err(rt->dev, "failed to request irq\n");
65 } else {
66 u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
67 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
68 }
69 return err;
70}
71
72static void rt_timer_free(struct rt_timer *rt)
73{
74 free_irq(rt->irq, rt);
75}
76
77static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
78{
79 if (rt->timer_freq < divisor)
80 rt->timer_div = rt->timer_freq;
81 else
82 rt->timer_div = divisor;
83
84 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
85
86 return 0;
87}
88
89static int rt_timer_enable(struct rt_timer *rt)
90{
91 u32 t;
92
93 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
94
95 t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
96 t |= TMR0CTL_ENABLE;
97 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
98
99 return 0;
100}
101
102static void rt_timer_disable(struct rt_timer *rt)
103{
104 u32 t;
105
106 t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
107 t &= ~TMR0CTL_ENABLE;
108 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
109}
110
111static int rt_timer_probe(struct platform_device *pdev)
112{
113 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
114 struct rt_timer *rt;
115 struct clk *clk;
116
117 rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
118 if (!rt) {
119 dev_err(&pdev->dev, "failed to allocate memory\n");
120 return -ENOMEM;
121 }
122
123 rt->irq = platform_get_irq(pdev, 0);
124 if (!rt->irq) {
125 dev_err(&pdev->dev, "failed to load irq\n");
126 return -ENOENT;
127 }
128
129 rt->membase = devm_request_and_ioremap(&pdev->dev, res);
130 if (IS_ERR(rt->membase))
131 return PTR_ERR(rt->membase);
132
133 clk = devm_clk_get(&pdev->dev, NULL);
134 if (IS_ERR(clk)) {
135 dev_err(&pdev->dev, "failed get clock rate\n");
136 return PTR_ERR(clk);
137 }
138
139 rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
140 if (!rt->timer_freq)
141 return -EINVAL;
142
143 rt->dev = &pdev->dev;
144 platform_set_drvdata(pdev, rt);
145
146 rt_timer_request(rt);
147 rt_timer_config(rt, 2);
148 rt_timer_enable(rt);
149
150 dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
151
152 return 0;
153}
154
155static int rt_timer_remove(struct platform_device *pdev)
156{
157 struct rt_timer *rt = platform_get_drvdata(pdev);
158
159 rt_timer_disable(rt);
160 rt_timer_free(rt);
161
162 return 0;
163}
164
165static const struct of_device_id rt_timer_match[] = {
166 { .compatible = "ralink,rt2880-timer" },
167 {},
168};
169MODULE_DEVICE_TABLE(of, rt_timer_match);
170
171static struct platform_driver rt_timer_driver = {
172 .probe = rt_timer_probe,
173 .remove = rt_timer_remove,
174 .driver = {
175 .name = "rt-timer",
176 .owner = THIS_MODULE,
177 .of_match_table = rt_timer_match
178 },
179};
180
181module_platform_driver(rt_timer_driver);
182
183MODULE_DESCRIPTION("Ralink RT2880 timer");
184MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
185MODULE_LICENSE("GPL");
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 681e7f86c080..2b0b83c171e0 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -350,7 +350,7 @@ static void __init select_board(void)
350 } 350 }
351 351
352 /* select "default" board */ 352 /* select "default" board */
353#ifdef CONFIG_CPU_TX39XX 353#ifdef CONFIG_TOSHIBA_JMR3927
354 txx9_board_vec = &jmr3927_vec; 354 txx9_board_vec = &jmr3927_vec;
355#endif 355#endif
356#ifdef CONFIG_CPU_TX49XX 356#ifdef CONFIG_CPU_TX49XX
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 02:24:44 -0500