diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-shmobile/clock-r8a7790.c | 34 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/setup-r8a7790.c | 55 |
2 files changed, 88 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 6869798effa3..bad9bf2e34d6 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c | |||
@@ -27,19 +27,51 @@ | |||
27 | #define CPG_BASE 0xe6150000 | 27 | #define CPG_BASE 0xe6150000 |
28 | #define CPG_LEN 0x1000 | 28 | #define CPG_LEN 0x1000 |
29 | 29 | ||
30 | #define SMSTPCR2 0xe6150138 | ||
31 | #define SMSTPCR7 0xe615014c | ||
32 | |||
30 | static struct clk_mapping cpg_mapping = { | 33 | static struct clk_mapping cpg_mapping = { |
31 | .phys = CPG_BASE, | 34 | .phys = CPG_BASE, |
32 | .len = CPG_LEN, | 35 | .len = CPG_LEN, |
33 | }; | 36 | }; |
34 | 37 | ||
38 | static struct clk p_clk = { | ||
39 | .rate = 65000000, /* shortcut for now */ | ||
40 | .mapping = &cpg_mapping, | ||
41 | }; | ||
42 | |||
43 | static struct clk mp_clk = { | ||
44 | .rate = 52000000, /* shortcut for now */ | ||
45 | .mapping = &cpg_mapping, | ||
46 | }; | ||
47 | |||
35 | static struct clk *main_clks[] = { | 48 | static struct clk *main_clks[] = { |
49 | &p_clk, | ||
50 | &mp_clk, | ||
36 | }; | 51 | }; |
37 | 52 | ||
38 | enum { MSTP_NR }; | 53 | enum { MSTP721, MSTP720, |
54 | MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; | ||
39 | static struct clk mstp_clks[MSTP_NR] = { | 55 | static struct clk mstp_clks[MSTP_NR] = { |
56 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ | ||
57 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | ||
58 | [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ | ||
59 | [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ | ||
60 | [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ | ||
61 | [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ | ||
62 | [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ | ||
63 | [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ | ||
40 | }; | 64 | }; |
41 | 65 | ||
42 | static struct clk_lookup lookups[] = { | 66 | static struct clk_lookup lookups[] = { |
67 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), | ||
68 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), | ||
69 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), | ||
70 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), | ||
71 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), | ||
72 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), | ||
73 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), | ||
74 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), | ||
43 | }; | 75 | }; |
44 | 76 | ||
45 | void __init r8a7790_clock_init(void) | 77 | void __init r8a7790_clock_init(void) |
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index af432ba11020..3bb5bf16000c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c | |||
@@ -22,13 +22,68 @@ | |||
22 | #include <linux/irqchip.h> | 22 | #include <linux/irqchip.h> |
23 | #include <linux/kernel.h> | 23 | #include <linux/kernel.h> |
24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
25 | #include <linux/serial_sci.h> | ||
25 | #include <mach/common.h> | 26 | #include <mach/common.h> |
26 | #include <mach/irqs.h> | 27 | #include <mach/irqs.h> |
27 | #include <mach/r8a7790.h> | 28 | #include <mach/r8a7790.h> |
28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
29 | 30 | ||
31 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | ||
32 | .type = scif_type, \ | ||
33 | .mapbase = baseaddr, \ | ||
34 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | ||
35 | .irqs = SCIx_IRQ_MUXED(irq) | ||
36 | |||
37 | #define SCIFA_DATA(index, baseaddr, irq) \ | ||
38 | [index] = { \ | ||
39 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | ||
40 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
41 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | ||
42 | } | ||
43 | |||
44 | #define SCIFB_DATA(index, baseaddr, irq) \ | ||
45 | [index] = { \ | ||
46 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | ||
47 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
48 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
49 | } | ||
50 | |||
51 | #define SCIF_DATA(index, baseaddr, irq) \ | ||
52 | [index] = { \ | ||
53 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | ||
54 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
55 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ | ||
56 | } | ||
57 | |||
58 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 }; | ||
59 | |||
60 | static const struct plat_sci_port scif[] = { | ||
61 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | ||
62 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | ||
63 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | ||
64 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | ||
65 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | ||
66 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | ||
67 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | ||
68 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | ||
69 | }; | ||
70 | |||
71 | static inline void r8a7790_register_scif(int idx) | ||
72 | { | ||
73 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | ||
74 | sizeof(struct plat_sci_port)); | ||
75 | } | ||
76 | |||
30 | void __init r8a7790_add_standard_devices(void) | 77 | void __init r8a7790_add_standard_devices(void) |
31 | { | 78 | { |
79 | r8a7790_register_scif(SCIFA0); | ||
80 | r8a7790_register_scif(SCIFA1); | ||
81 | r8a7790_register_scif(SCIFB0); | ||
82 | r8a7790_register_scif(SCIFB1); | ||
83 | r8a7790_register_scif(SCIFB2); | ||
84 | r8a7790_register_scif(SCIFA2); | ||
85 | r8a7790_register_scif(SCIF0); | ||
86 | r8a7790_register_scif(SCIF1); | ||
32 | } | 87 | } |
33 | 88 | ||
34 | #ifdef CONFIG_USE_OF | 89 | #ifdef CONFIG_USE_OF |