128 files changed, 3008 insertions, 1617 deletions

diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index e2d636336b7c..e7f80928949c 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -55,12 +55,47 @@ __tmp_stack:
 __continue:
 #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
 
-        /* Set board ID necessary for boot */
-        ldr     r7, 1f                          @ Set machine type register
-        mov     r8, #0                          @ pass null pointer as atag
+        adr     r0, dtb_info
+        ldmia   r0, {r1, r3, r4, r5, r7}
+
+        sub     r0, r0, r1              @ calculate the delta offset
+        add     r5, r5, r0              @ _edata
+
+        ldr     lr, [r5, #0]            @ check if valid DTB is present
+        cmp     lr, r3
+        bne     0f
+
+        add     r9, r7, #31             @ rounded up to a multiple
+        bic     r9, r9, #31             @ ... of 32 bytes
+
+        add     r6, r9, r5              @ copy from _edata
+        add     r9, r9, r4              @ to MEMORY_START
+
+1:      ldmdb   r6!, {r0 - r3, r10 - r12, lr}
+        cmp     r6, r5
+        stmdb   r9!, {r0 - r3, r10 - r12, lr}
+        bhi     1b
+
+        /* Success: Zero board ID, pointer to start of memory for atag/dtb */
+        mov     r7, #0
+        mov     r8, r4
         b       2f
 
-1 :     .long MACH_TYPE
+        .align  2
+dtb_info:
+        .word   dtb_info
+#ifndef __ARMEB__
+        .word   0xedfe0dd0              @ sig is 0xd00dfeed big endian
+#else
+        .word   0xd00dfeed
+#endif
+        .word   MEMORY_START
+        .word   _edata
+        .word   0x4000                  @ maximum DTB size
+0:
+        /* Failure: Zero board ID, NULL atag/dtb */
+        mov     r7, #0
+        mov     r8, #0                  @ pass null pointer as atag
 2 :
 
 #endif /* CONFIG_ZBOOT_ROM */
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9a7028..1d94303d4416 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
         armada-370-mirabox.dtb \
         armada-370-rd.dtb \
+        armada-xp-axpwifiap.dtb \
         armada-xp-db.dtb \
         armada-xp-gp.dtb \
         armada-xp-openblocks-ax3-4.dtb
@@ -183,6 +184,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
         ccu9540.dtb
 dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
+        emev2-kzm9d-reference.dtb \
         r8a7740-armadillo800eva.dtb \
         r8a7778-bockw.dtb \
         r8a7740-armadillo800eva-reference.dtb \
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index beee1699d49e..90ce29dbe119 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
 
 / {
         model = "Marvell Armada 370 Evaluation Board";
@@ -30,6 +30,9 @@
         };
 
         soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 45b107763e3b..2471d9da767b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
 
 / {
         model = "Globalscale Mirabox";
@@ -25,6 +25,25 @@
         };
 
         soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Connected on the PCB to a USB 3.0 XHCI controller */
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <200000000>;
@@ -120,22 +139,6 @@
                                         reg = <0x25>;
                                 };
                         };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /* Internal mini-PCIe connector */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-
-                                /* Connected on the PCB to a USB 3.0 XHCI controller */
-                                pcie@2,0 {
-                                        /* Port 1, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index a3a2fedb8726..f81810a59629 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,7 +12,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
 
 / {
         model = "Marvell Armada 370 Reference Design";
@@ -28,6 +28,25 @@
         };
 
         soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Internal mini-PCIe connector */
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <200000000>;
@@ -85,22 +104,6 @@
                                         gpios = <&gpio0 6 1>;
                                 };
                         };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /* Internal mini-PCIe connector */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-
-                                /* Internal mini-PCIe connector */
-                                pcie@2,0 {
-                                        /* Port 1, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90b117624abb..e984ce6bb33f 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -18,6 +18,8 @@
 
 /include/ "skeleton64.dtsi"
 
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
 / {
         model = "Marvell Armada 370 and XP SoC";
         compatible = "marvell,armada-370-xp";
@@ -38,18 +40,73 @@
         };
 
         soc {
-                #address-cells = <1>;
+                #address-cells = <2>;
                 #size-cells = <1>;
-                compatible = "simple-bus";
+                controller = <&mbusc>;
                 interrupt-parent = <&mpic>;
-                ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
-                          0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+
+                devbus-bootcs {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs0 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs1 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs2 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs3 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
 
                 internal-regs {
                         compatible = "simple-bus";
                         #address-cells = <1>;
                         #size-cells = <1>;
-                        ranges;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
 
                         mpic: interrupt-controller@20000 {
                                 compatible = "marvell,mpic";
@@ -195,50 +252,6 @@
                                 status = "disabled";
                         };
 
-                        devbus-bootcs@10400 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10400 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs0@10408 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10408 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs1@10410 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10410 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs2@10418 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10418 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs3@10420 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10420 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index fa3dfc6b4c6a..648e5303446e 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -15,7 +15,7 @@
  * common to all Armada SoCs.
  */
 
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
 /include/ "skeleton.dtsi"
 
 / {
@@ -29,8 +29,66 @@
         };
 
         soc {
-                ranges = <0          0xd0000000 0x0100000 /* internal registers */
-                          0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
+                compatible = "marvell,armada370-mbus", "simple-bus";
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+                };
+
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         system-controller@18200 {
                                 compatible = "marvell,armada-370-xp-system-controller";
@@ -169,54 +227,6 @@
                                         0x18304 0x4>;
                                 status = "okay";
                         };
-
-                        pcie-controller {
-                                compatible = "marvell,armada-370-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 62>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 9>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
new file mode 100644
index 000000000000..c5fe57269f5a
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -0,0 +1,164 @@
+/*
+ * Device Tree file for Marvell RD-AXPWiFiAP.
+ *
+ * Note: this board is shipped with a new generation boot loader that
+ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
+ * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
+ * used.
+ *
+ * Copyright (C) 2013 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+        model = "Marvell RD-AXPWiFiAP";
+        compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* First mini-PCIe port */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Second mini-PCIe port */
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+
+                        /* Renesas uPD720202 USB 3.0 controller */
+                        pcie@3,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+                        pinctrl {
+                                pinctrl-0 = <&pmx_phy_int>;
+                                pinctrl-names = "default";
+
+                                pmx_ge0: pmx-ge0 {
+                                        marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                                       "mpp4", "mpp5", "mpp6", "mpp7",
+                                                       "mpp8", "mpp9", "mpp10", "mpp11";
+                                        marvell,function = "ge0";
+                                };
+
+                                pmx_ge1: pmx-ge1 {
+                                        marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
+                                                       "mpp16", "mpp17", "mpp18", "mpp19",
+                                                       "mpp20", "mpp21", "mpp22", "mpp23";
+                                        marvell,function = "ge1";
+                                };
+
+                                pmx_keys: pmx-keys {
+                                        marvell,pins = "mpp33";
+                                        marvell,function = "gpio";
+                                };
+
+                                pmx_spi: pmx-spi {
+                                        marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
+                                        marvell,function = "spi";
+                                };
+
+                                pmx_phy_int: pmx-phy-int {
+                                        marvell,pins = "mpp32";
+                                        marvell,function = "gpio";
+                                };
+                        };
+
+                        serial@12000 {
+                                clock-frequency = <250000000>;
+                                status = "okay";
+                        };
+
+                        serial@12100 {
+                                clock-frequency = <250000000>;
+                                status = "okay";
+                        };
+
+                        sata@a0000 {
+                                nr-ports = <1>;
+                                status = "okay";
+                        };
+
+                        mdio {
+                                phy0: ethernet-phy@0 {
+                                        reg = <0>;
+                                };
+
+                                phy1: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+                        };
+
+                        ethernet@70000 {
+                                pinctrl-0 = <&pmx_ge0>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@74000 {
+                                pinctrl-0 = <&pmx_ge1>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        spi0: spi@10600 {
+                                status = "okay";
+                                pinctrl-0 = <&pmx_spi>;
+                                pinctrl-names = "default";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "n25q128a13";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_keys>;
+                pinctrl-names = "default";
+
+                button@1 {
+                        label = "Factory Reset Button";
+                        linux,code = <141>; /* KEY_SETUP */
+                        gpios = <&gpio1 1 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e28e68ff864d..bcf6d79a57ec 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
 
 / {
         model = "Marvell Armada XP Evaluation Board";
@@ -30,9 +30,70 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
-                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
-                          0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+                devbus-bootcs {
+                        status = "okay";
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 16 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x1000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * All 6 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+                        pcie@3,0 {
+                                /* Port 0, Lane 2 */
+                                status = "okay";
+                        };
+                        pcie@4,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
 
                 internal-regs {
                         serial@12000 {
@@ -127,68 +188,6 @@
                                         spi-max-frequency = <20000000>;
                                 };
                         };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /*
-                                 * All 6 slots are physically present as
-                                 * standard PCIe slots on the board.
-                                 */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@2,0 {
-                                        /* Port 0, Lane 1 */
-                                        status = "okay";
-                                };
-                                pcie@3,0 {
-                                        /* Port 0, Lane 2 */
-                                        status = "okay";
-                                };
-                                pcie@4,0 {
-                                        /* Port 0, Lane 3 */
-                                        status = "okay";
-                                };
-                                pcie@9,0 {
-                                        /* Port 2, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@10,0 {
-                                        /* Port 3, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
-
-                        devbus-bootcs@10400 {
-                                status = "okay";
-                                ranges = <0 0xf0000000 0x1000000>;
-
-                                /* Device Bus parameters are required */
-
-                                /* Read parameters */
-                                devbus,bus-width    = <8>;
-                                devbus,turn-off-ps  = <60000>;
-                                devbus,badr-skew-ps = <0>;
-                                devbus,acc-first-ps = <124000>;
-                                devbus,acc-next-ps  = <248000>;
-                                devbus,rd-setup-ps  = <0>;
-                                devbus,rd-hold-ps   = <0>;
-
-                                /* Write parameters */
-                                devbus,sync-enable = <0>;
-                                devbus,wr-high-ps  = <60000>;
-                                devbus,wr-low-ps   = <60000>;
-                                devbus,ale-wr-ps   = <60000>;
-
-                                /* NOR 16 MiB */
-                                nor@0 {
-                                        compatible = "cfi-flash";
-                                        reg = <0 0x1000000>;
-                                        bank-width = <2>;
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index c87b2de29c30..2298e4a910e2 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
 
 / {
         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
@@ -39,9 +39,58 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
-                          0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
-                          0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+                devbus-bootcs {
+                        status = "okay";
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 16 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x1000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * The 3 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
 
                 internal-regs {
                         serial@12000 {
@@ -126,56 +175,6 @@
                                         spi-max-frequency = <108000000>;
                                 };
                         };
-
-                        devbus-bootcs@10400 {
-                                status = "okay";
-                                ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
-
-                                /* Device Bus parameters are required */
-
-                                /* Read parameters */
-                                devbus,bus-width    = <8>;
-                                devbus,turn-off-ps  = <60000>;
-                                devbus,badr-skew-ps = <0>;
-                                devbus,acc-first-ps = <124000>;
-                                devbus,acc-next-ps  = <248000>;
-                                devbus,rd-setup-ps  = <0>;
-                                devbus,rd-hold-ps   = <0>;
-
-                                /* Write parameters */
-                                devbus,sync-enable = <0>;
-                                devbus,wr-high-ps  = <60000>;
-                                devbus,wr-low-ps   = <60000>;
-                                devbus,ale-wr-ps   = <60000>;
-
-                                /* NOR 16 MiB */
-                                nor@0 {
-                                        compatible = "cfi-flash";
-                                        reg = <0 0x1000000>;
-                                        bank-width = <2>;
-                                };
-                        };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /*
-                                 * The 3 slots are physically present as
-                                 * standard PCIe slots on the board.
-                                 */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@9,0 {
-                                        /* Port 2, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@10,0 {
-                                        /* Port 3, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa383e07f..e45e363cc9b9 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -13,7 +13,7 @@
  * common to all Armada XP SoCs.
  */
 
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
 
 / {
         model = "Marvell Armada XP MV78230 SoC";
@@ -44,6 +44,124 @@
         };
 
         soc {
+                /*
+                 * MV78230 has 2 PCIe units Gen2.0: One unit can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                                0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                                0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                                0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                                0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                                0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+                                0x82000000 0x9 0       MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                                0x81000000 0x9 0       MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         pinctrl {
                                 compatible = "marvell,mv78230-pinctrl";
@@ -77,110 +195,6 @@
                                 #interrupts-cells = <2>;
                                 interrupts = <87>, <88>, <89>;
                         };
-
-                        /*
-                         * MV78230 has 2 PCIe units Gen2.0: One unit can be
-                         * configured as x4 or quad x1 lanes. One unit is
-                         * x4/x1.
-                         */
-                        pcie-controller {
-                                compatible = "marvell,armada-xp-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-#address-cells = <3>;
-#size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                        0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                        0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                        0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 59>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 6>;
-                                        status = "disabled";
-                                };
-
-                                pcie@3,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-                                        reg = <0x1800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 60>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 7>;
-                                        status = "disabled";
-                                };
-
-                                pcie@4,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-                                        reg = <0x2000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 61>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 8>;
-                                        status = "disabled";
-                                };
-
-                                pcie@9,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-                                        reg = <0x4800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 99>;
-                                        marvell,pcie-port = <2>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 26>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d9335da210c..6dc3921df9b3 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -13,7 +13,7 @@
  * common to all Armada XP SoCs.
  */
 
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
 
 / {
         model = "Marvell Armada XP MV78260 SoC";
@@ -45,6 +45,145 @@
         };
 
         soc {
+                /*
+                 * MV78260 has 3 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                                0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                                0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                                0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+                                0x82000000 0x9 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                                0x81000000 0x9 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                                0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                                0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         pinctrl {
                                 compatible = "marvell,mv78260-pinctrl";
@@ -97,128 +236,6 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                         };
-
-                        /*
-                         * MV78260 has 3 PCIe units Gen2.0: Two units can be
-                         * configured as x4 or quad x1 lanes. One unit is
-                         * x4/x1.
-                         */
-                        pcie-controller {
-                                compatible = "marvell,armada-xp-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                        0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                        0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                        0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                        0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 59>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 6>;
-                                        status = "disabled";
-                                };
-
-                                pcie@3,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-                                        reg = <0x1800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 60>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 7>;
-                                        status = "disabled";
-                                };
-
-                                pcie@4,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-                                        reg = <0x2000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 61>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 8>;
-                                        status = "disabled";
-                                };
-
-                                pcie@9,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-                                        reg = <0x4800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 99>;
-                                        marvell,pcie-port = <2>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 26>;
-                                        status = "disabled";
-                                };
-
-                                pcie@10,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
-                                        reg = <0x5000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 103>;
-                                        marvell,pcie-port = <3>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 27>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index c7b1f4d5c1c7..a6661e3aea23 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -13,7 +13,7 @@
  * common to all Armada XP SoCs.
  */
 
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
 
 / {
         model = "Marvell Armada XP MV78460 SoC";
@@ -61,6 +61,227 @@
         };
 
         soc {
+                /*
+                 * MV78460 has 4 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. Two units are
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                                0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                                0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
+                                0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
+                                0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                                0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                                0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+
+                                0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                                0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                                0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
+                                0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
+                                0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
+                                0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
+                                0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
+                                0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
+
+                                0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                                0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
+
+                                0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                                0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@5,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+                                reg = <0x2800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
+                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+
+                        pcie@6,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
+                                reg = <0x3000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
+                                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 63>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 10>;
+                                status = "disabled";
+                        };
+
+                        pcie@7,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
+                                reg = <0x3800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
+                                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 64>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 11>;
+                                status = "disabled";
+                        };
+
+                        pcie@8,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
+                                reg = <0x4000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
+                                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 65>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 12>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         pinctrl {
                                 compatible = "marvell,mv78460-pinctrl";
@@ -113,194 +334,6 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                         };
-
-                        /*
-                         * MV78460 has 4 PCIe units Gen2.0: Two units can be
-                         * configured as x4 or quad x1 lanes. Two units are
-                         * x4/x1.
-                         */
-                        pcie-controller {
-                                compatible = "marvell,armada-xp-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                        0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                        0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                        0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                        0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
-                                        0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
-                                        0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
-                                        0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 59>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 6>;
-                                        status = "disabled";
-                                };
-
-                                pcie@3,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
-                                        reg = <0x1800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 60>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 7>;
-                                        status = "disabled";
-                                };
-
-                                pcie@4,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
-                                        reg = <0x2000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 61>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 8>;
-                                        status = "disabled";
-                                };
-
-                                pcie@5,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-                                        reg = <0x2800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 62>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 9>;
-                                        status = "disabled";
-                                };
-
-                                pcie@6,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
-                                        reg = <0x3000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 63>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 10>;
-                                        status = "disabled";
-                                };
-
-                                pcie@7,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
-                                        reg = <0x3800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 64>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 11>;
-                                        status = "disabled";
-                                };
-
-                                pcie@8,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
-                                        reg = <0x4000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 65>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 12>;
-                                        status = "disabled";
-                                };
-                                pcie@9,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
-                                        reg = <0x4800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 99>;
-                                        marvell,pcie-port = <2>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 26>;
-                                        status = "disabled";
-                                };
-
-                                pcie@10,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
-                                        reg = <0x5000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 103>;
-                                        marvell,pcie-port = <3>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 27>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 8f510458ea86..5695afcc04bf 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78260.dtsi"
+#include "armada-xp-mv78260.dtsi"
 
 / {
         model = "PlatHome OpenBlocks AX3-4 board";
@@ -27,9 +27,46 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
-                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
-                          0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+                devbus-bootcs {
+                        status = "okay";
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 128 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x8000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
 
                 internal-regs {
                         serial@12000 {
@@ -148,49 +185,6 @@
                         usb@51000 {
                                 status = "okay";
                         };
-
-                        /* USB interface in the mini-PCIe connector */
-                        usb@52000 {
-                                status = "okay";
-                        };
-
-                        devbus-bootcs@10400 {
-                                status = "okay";
-                                ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
-
-                                /* Device Bus parameters are required */
-
-                                /* Read parameters */
-                                devbus,bus-width    = <8>;
-                                devbus,turn-off-ps  = <60000>;
-                                devbus,badr-skew-ps = <0>;
-                                devbus,acc-first-ps = <124000>;
-                                devbus,acc-next-ps  = <248000>;
-                                devbus,rd-setup-ps  = <0>;
-                                devbus,rd-hold-ps   = <0>;
-
-                                /* Write parameters */
-                                devbus,sync-enable = <0>;
-                                devbus,wr-high-ps  = <60000>;
-                                devbus,wr-low-ps   = <60000>;
-                                devbus,ale-wr-ps   = <60000>;
-
-                                /* NOR 128 MiB */
-                                nor@0 {
-                                        compatible = "cfi-flash";
-                                        reg = <0 0x8000000>;
-                                        bank-width = <2>;
-                                };
-                        };
-
-                        pcie-controller {
-                                status = "okay";
-                                /* Internal mini-PCIe connector */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 416eb9481844..7ba99ce107bb 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -16,7 +16,7 @@
  * common to all Armada SoCs.
  */
 
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
 
 / {
         model = "Marvell Armada XP family SoC";
@@ -27,6 +27,13 @@
         };
 
         soc {
+                compatible = "marvell,armadaxp-mbus", "simple-bus";
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+                };
+
                 internal-regs {
                         L2: l2-cache {
                                 compatible = "marvell,aurora-system-cache";
diff --git a/arch/arm/boot/dts/emev2-kzm9d-reference.dts b/arch/arm/boot/dts/emev2-kzm9d-reference.dts
new file mode 100644
index 000000000000..bed676b95c27
--- /dev/null
+++ b/arch/arm/boot/dts/emev2-kzm9d-reference.dts
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Source for the KZM9D board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/dts-v1/;
+
+/include/ "emev2.dtsi"
+
+/ {
+        model = "EMEV2 KZM9D Board";
+        compatible = "renesas,kzm9d-reference", "renesas,emev2";
+
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096";
+        };
+
+        reg_1p8v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        reg_3p3v: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        lan9220@20000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x20000000 0x10000>;
+                phy-mode = "mii";
+                interrupt-parent = <&gpio0>;
+                interrupts = <1 1>;     /* active high */
+                reg-io-width = <4>;
+                smsc,irq-active-high;
+                smsc,irq-push-pull;
+                vddvario-supply = <&reg_1p8v>;
+                vdd33a-supply = <&reg_3p3v>;
+        };
+};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index b9b3241f173b..dda13bc02f9f 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -21,6 +21,6 @@
         };
 
         chosen {
-                bootargs = "console=tty0 console=ttyS1,115200n81 earlyprintk=serial8250-em.1,115200n81 mem=128M@0x40000000 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096";
+                bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096";
         };
 };
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index c8a8c08b48dd..99ad2b2e8e14 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -14,6 +14,14 @@
         compatible = "renesas,emev2";
         interrupt-parent = <&gic>;
 
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+                gpio3 = &gpio3;
+                gpio4 = &gpio4;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -67,4 +75,55 @@
                 reg = <0xe1050000 0x38>;
                 interrupts = <0 11 0>;
         };
+
+        gpio0: gpio@e0050000 {
+                compatible = "renesas,em-gio";
+                reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
+                interrupts = <0 67 0>, <0 68 0>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpios = <32>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpio1: gpio@e0050080 {
+                compatible = "renesas,em-gio";
+                reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
+                interrupts = <0 69 0>, <0 70 0>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpios = <32>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpio2: gpio@e0050100 {
+                compatible = "renesas,em-gio";
+                reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
+                interrupts = <0 71 0>, <0 72 0>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpios = <32>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpio3: gpio@e0050180 {
+                compatible = "renesas,em-gio";
+                reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
+                interrupts = <0 73 0>, <0 74 0>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpios = <32>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpio4: gpio@e0050200 {
+                compatible = "renesas,em-gio";
+                reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
+                interrupts = <0 75 0>, <0 76 0>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpios = <31>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 1e5bef0bead7..650ef30e1856 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -1,4 +1,39 @@
 / {
+        mbus {
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         compatible = "marvell,88f6281-pinctrl";
@@ -41,37 +76,6 @@
                         };
                 };
 
-                pcie-controller {
-                        compatible = "marvell,kirkwood-pcie";
-                        status = "disabled";
-                        device_type = "pci";
-
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-
-                        bus-range = <0x00 0xff>;
-
-                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
-                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                        pcie@1,0 {
-                                device_type = "pci";
-                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-                                reg = <0x0800 0 0 0 0>;
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-                                #interrupt-cells = <1>;
-                                ranges;
-                                interrupt-map-mask = <0 0 0 0>;
-                                interrupt-map = <0 0 0 0 &intc 9>;
-                                marvell,pcie-port = <0>;
-                                marvell,pcie-lane = <0>;
-                                clocks = <&gate_clk 2>;
-                                status = "disabled";
-                        };
-                };
-
                 rtc@10300 {
                         compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                         reg = <0x10300 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index a63a11137262..3933a331ddc2 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -1,4 +1,59 @@
 / {
+        mbus {
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 10>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 18>;
+                                status = "disabled";
+                        };
+                };
+        };
         ocp@f1000000 {
 
                 pinctrl: pinctrl@10000 {
@@ -94,52 +149,5 @@
                         status = "disabled";
                 };
 
-                pcie-controller {
-                        compatible = "marvell,kirkwood-pcie";
-                        status = "disabled";
-                        device_type = "pci";
-
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-
-                        bus-range = <0x00 0xff>;
-
-                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
-                                  0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
-                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                        pcie@1,0 {
-                                device_type = "pci";
-                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-                                reg = <0x0800 0 0 0 0>;
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-                                #interrupt-cells = <1>;
-                                ranges;
-                                interrupt-map-mask = <0 0 0 0>;
-                                interrupt-map = <0 0 0 0 &intc 9>;
-                                marvell,pcie-port = <0>;
-                                marvell,pcie-lane = <0>;
-                                clocks = <&gate_clk 2>;
-                                status = "disabled";
-                        };
-
-                        pcie@2,0 {
-                                device_type = "pci";
-                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
-                                reg = <0x1000 0 0 0 0>;
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-                                #interrupt-cells = <1>;
-                                ranges;
-                                interrupt-map-mask = <0 0 0 0>;
-                                interrupt-map = <0 0 0 0 &intc 10>;
-                                marvell,pcie-port = <1>;
-                                marvell,pcie-lane = <0>;
-                                clocks = <&gate_clk 18>;
-                                status = "disabled";
-                        };
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 00c48d26de68..9bf139c5a34d 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "LaCie CloudBox";
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
index 9d777edd1f36..72c4b0a0366f 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -11,14 +11,15 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-db.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood-db.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Marvell DB-88F6281-BP Development Board";
         compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
-        ocp@f1000000 {
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
                 pcie-controller {
                         status = "okay";
 
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
index f4c852886d23..36c411d34926 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -11,14 +11,15 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-db.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood-db.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "Marvell DB-88F6282-BP Development Board";
         compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
 
-        ocp@f1000000 {
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
                 pcie-controller {
                         status = "okay";
 
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index c87cfb816120..45c1bf74ac00 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -12,7 +12,7 @@
  * and 6282 variants of the Marvell Kirkwood Development Board.
  */
 
-/include/ "kirkwood.dtsi"
+#include "kirkwood.dtsi"
 
 / {
         memory {
@@ -77,13 +77,5 @@
                         cd-gpios = <&gpio1 6 0>;
                         status = "okay";
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 14d4ceea3057..e112ca62d978 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-dnskw.dtsi"
+#include "kirkwood-dnskw.dtsi"
 
 / {
         model = "D-Link DNS-320 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 63872570e6ce..5119fb8a8eb6 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-dnskw.dtsi"
+#include "kirkwood-dnskw.dtsi"
 
 / {
         model = "D-Link DNS-325 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 0afe1d07c803..2e04284846a0 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -1,5 +1,5 @@
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "D-Link DNS NASes (kirkwood-based)";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 7714742bb8d8..4387ae8e93fe 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Seagate FreeAgent Dockstar";
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 36c7ba38d500..c62837837246 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Globalscale Technologies Dreamplug";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 31caa6405065..e57118039277 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Seagate GoFlex Net";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 1e642f39b154..2c5673adb4bd 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Globalscale Technologies Guruplug Server Plus";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 20c4b081f420..158161ff6826 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 441204e8abc6..8314118b6b8a 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Iomega Iconnect";
@@ -18,6 +18,17 @@
                 linux,initrd-end   = <0x4800000>;
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pmx_button_reset: pmx-button-reset {
@@ -101,14 +112,6 @@
                                 reg = <0x980000 0x1f400000>;
                         };
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 00a7bfe5e83b..fd7f053e9c96 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Iomega StorCenter ix2-200";
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index c3f036b86cca..bd88a236f729 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Internet Space v2";
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5d9f5ea78700..b071d37cc291 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-98dx4122.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
 
 / {
         model = "Keymile Kirkwood Reference Design";
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts
index 9f55d95f35f5..e2fa368aef25 100644
--- a/arch/arm/boot/dts/kirkwood-lschlv2.dts
+++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-lsxl.dtsi"
+#include "kirkwood-lsxl.dtsi"
 
 / {
         model = "Buffalo Linkstation LS-CHLv2";
diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts
index 5c84c118ed8d..8d89cdf8d6bf 100644
--- a/arch/arm/boot/dts/kirkwood-lsxhl.dts
+++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-lsxl.dtsi"
+#include "kirkwood-lsxl.dtsi"
 
 / {
         model = "Buffalo Linkstation LS-XHL";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 31b17f5b9d28..f7e247cc925a 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -1,5 +1,5 @@
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         chosen {
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 6179333fd71f..21f1954c9e54 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "MPL CEC4";
@@ -16,6 +16,17 @@
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pmx_led_health: pmx-led-health {
@@ -134,14 +145,6 @@
                         cd-gpios = <&gpio1 15 1>;
                         /* No WP GPIO */
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index ad6ade7d9191..84ff31cfbcdc 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "NETGEAR ReadyNAS Duo v2";
@@ -16,6 +16,17 @@
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pmx_button_power: pmx-button-power {
@@ -101,14 +112,6 @@
                         status = "okay";
                         nr-ports = <2>;
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 2afac0405816..d0fb34dc1667 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -1,5 +1,5 @@
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         chosen {
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index b50e93d7796c..0599f3cb844e 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Network Space v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index af8259fe8955..b0e17984aea0 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Network Space Lite v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index 85f24d227e17..d4f6a586d553 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Network Space Max v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index 329e530bffe7..f30e05af6473 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         /* This machine is embedded in the first LaCie CloudBox product. */
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 69003598f5fa..bd7f05f6aa96 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "ZyXEL NSA310";
@@ -16,6 +16,17 @@
                 bootargs = "console=ttyS0,115200";
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pinctrl-0 = <&pmx_unknown>;
@@ -162,14 +173,6 @@
                                 reg = <0x5040000 0x2fc0000>;
                         };
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 38dc8517d777..365b792b23a7 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "Plat'Home OpenBlocksA6";
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index f7143f128504..0cc5f26bbbb6 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -6,8 +6,8 @@
  * Licensed under GPLv2
  */
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         memory {
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
index f620ce48de97..eac6a21f3b1f 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -8,7 +8,7 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-sheevaplug-common.dtsi"
+#include "kirkwood-sheevaplug-common.dtsi"
 
 / {
         model = "Globalscale Technologies eSATA SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
index bf1dff251432..bb61918313db 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -8,7 +8,7 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-sheevaplug-common.dtsi"
+#include "kirkwood-sheevaplug-common.dtsi"
 
 / {
         model = "Globalscale Technologies SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index f2052d7bc10f..974f1e0f09b2 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "Univeral Scientific Industrial Co. Topkick-1281P2";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 6dd1038e4de4..3867ae3030be 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,8 +1,8 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
-/include/ "kirkwood-ts219.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-ts219.dtsi"
 
 / {
         ocp@f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 6fdc5ffcaae5..04f6fe106bb5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,10 +1,21 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
-/include/ "kirkwood-ts219.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-ts219.dtsi"
 
 / {
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
@@ -30,14 +41,6 @@
                                 marvell,function = "gpio";
                         };
                 };
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@2,0 {
-                                status = "okay";
-                        };
-                };
-
         };
 
         gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 0c9a94cd666c..7019cf675df2 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -11,6 +11,16 @@
                 bootargs = "console=ttyS0,115200n8";
         };
 
+        mbus {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 i2c@11000 {
                         status = "okay";
@@ -87,12 +97,5 @@
                         status = "okay";
                         nr-ports = <2>;
                 };
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 9809fc1f105c..70f414d9bd9a 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,5 +1,7 @@
 /include/ "skeleton.dtsi"
 
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
 / {
         compatible = "marvell,kirkwood";
         interrupt-parent = <&intc>;
@@ -28,15 +30,28 @@
                       <0xf1020214 0x04>;
         };
 
+        mbus {
+                compatible = "marvell,kirkwood-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
+                pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */
+        };
+
         ocp@f1000000 {
                 compatible = "simple-bus";
                 ranges = <0x00000000 0xf1000000 0x0100000
-                          0xe0000000 0xe0000000 0x8100000 /* PCIE */
                           0xf4000000 0xf4000000 0x0000400
                           0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
 
+                mbusc: mbus-controller@20000 {
+                        compatible = "marvell,mbus-controller";
+                        reg = <0x20000 0x80>, <0x1500 0x20>;
+                };
+
                 core_clk: core-clocks@10030 {
                         compatible = "marvell,kirkwood-core-clock";
                         reg = <0x10030 0x4>;
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index f603c6946c29..e657a9db1666 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -50,3 +50,25 @@
                 };
         };
 };
+
+&i2c5 {
+        vdd_dvfs: max8973@1b {
+                compatible = "maxim,max8973";
+                reg = <0x1b>;
+
+                regulator-min-microvolt = <935000>;
+                regulator-max-microvolt = <1200000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&cpu0 {
+        cpu0-supply = <&vdd_dvfs>;
+        operating-points = <
+                /* kHz  uV */
+                1950000 1115000
+                1462500  995000
+        >;
+        voltage-tolerance = <1>; /* 1% */
+};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 4ff2019c0e30..6ce699be6095 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -85,4 +85,130 @@
                 interrupt-parent = <&gic>;
                 interrupts = <0 69 4>;
         };
+
+        i2c0: i2c@e6500000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6500000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 174 0x4>;
+        };
+
+        i2c1: i2c@e6510000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6510000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 175 0x4>;
+        };
+
+        i2c2: i2c@e6520000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6520000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 176 0x4>;
+        };
+
+        i2c3: i2c@e6530000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6530000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 177 0x4>;
+        };
+
+        i2c4: i2c@e6540000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6540000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 178 0x4>;
+        };
+
+        i2c5: i2c@e60b0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe60b0000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 179 0x4>;
+        };
+
+        i2c6: i2c@e6550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6550000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 184 0x4>;
+        };
+
+        i2c7: i2c@e6560000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6560000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 185 0x4>;
+        };
+
+        i2c8: i2c@e6570000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0 0xe6570000 0 0x428>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 173 0x4>;
+        };
+
+        mmcif0: mmcif@ee200000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0 0xee200000 0 0x80>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 169 0x4>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
+        mmcif1: mmcif@ee220000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0 0xee220000 0 0x80>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 170 0x4>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
+        sdhi0: sdhi@ee100000 {
+                compatible = "renesas,r8a73a4-sdhi";
+                reg = <0 0xee100000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 165 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sdhi1: sdhi@ee120000 {
+                compatible = "renesas,r8a73a4-sdhi";
+                reg = <0 0xee120000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 166 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sdhi2: sdhi@ee140000 {
+                compatible = "renesas,r8a73a4-sdhi";
+                reg = <0 0xee140000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 167 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 339d9b11721c..9cd882028095 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -54,4 +54,58 @@
                 interrupt-parent = <&gic>;
                 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
         };
+
+        mmcif0: mmcif@ee200000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0 0xee200000 0 0x80>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 169 0x4>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
+        mmcif1: mmcif@ee220000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0 0xee220000 0 0x80>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 170 0x4>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
+        sdhi0: sdhi@ee100000 {
+                compatible = "renesas,r8a7790-sdhi";
+                reg = <0 0xee100000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 165 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sdhi1: sdhi@ee120000 {
+                compatible = "renesas,r8a7790-sdhi";
+                reg = <0 0xee120000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 166 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sdhi2: sdhi@ee140000 {
+                compatible = "renesas,r8a7790-sdhi";
+                reg = <0 0xee140000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 167 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sdhi3: sdhi@ee160000 {
+                compatible = "renesas,r8a7790-sdhi";
+                reg = <0 0xee160000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 168 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index d2803be4e1a8..759b0cd20013 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -125,6 +125,12 @@
                 clock-names = "apb_pclk";
         };
 
+        scc@7fff0000 {
+                compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
+                reg = <0 0x7fff0000 0 0x1000>;
+                interrupts = <0 95 4>;
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
                 interrupts = <1 13 0xf08>,
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 00247c771313..bc22056200ae 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -27,6 +27,22 @@
 #include <plat/time.h>
 #include "common.h"
 
+/* These can go away once Dove uses the mvebu-mbus DT binding */
+#define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
+#define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
+#define DOVE_MBUS_PCIE0_IO_TARGET     0x4
+#define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
+#define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
+#define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
+#define DOVE_MBUS_PCIE1_IO_TARGET     0x8
+#define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
+#define DOVE_MBUS_CESA_TARGET         0x3
+#define DOVE_MBUS_CESA_ATTR           0x1
+#define DOVE_MBUS_BOOTROM_TARGET      0x1
+#define DOVE_MBUS_BOOTROM_ATTR        0xfd
+#define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
+#define DOVE_MBUS_SCRATCHPAD_ATTR     0x0
+
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void)
 {
         /*
          * The PCIe windows will no longer be statically allocated
-         * here once Dove is migrated to the pci-mvebu driver.
+         * here once Dove is migrated to the pci-mvebu driver. The
+         * non-PCIe windows will no longer be created here once Dove
+         * fully moves to DT.
          */
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
+        mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
+                                          DOVE_MBUS_PCIE0_IO_ATTR,
                                           DOVE_PCIE0_IO_PHYS_BASE,
                                           DOVE_PCIE0_IO_SIZE,
-                                          DOVE_PCIE0_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          DOVE_PCIE0_IO_BUS_BASE);
+        mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
+                                          DOVE_MBUS_PCIE1_IO_ATTR,
                                           DOVE_PCIE1_IO_PHYS_BASE,
                                           DOVE_PCIE1_IO_SIZE,
-                                          DOVE_PCIE1_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          DOVE_PCIE0_MEM_PHYS_BASE,
-                                          DOVE_PCIE0_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          DOVE_PCIE1_MEM_PHYS_BASE,
-                                          DOVE_PCIE1_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
-                              DOVE_CESA_SIZE);
-        mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
-                              DOVE_BOOTROM_SIZE);
-        mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
-                              DOVE_SCRATCHPAD_SIZE);
+                                          DOVE_PCIE1_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
+                                    DOVE_MBUS_PCIE0_MEM_ATTR,
+                                    DOVE_PCIE0_MEM_PHYS_BASE,
+                                    DOVE_PCIE0_MEM_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
+                                    DOVE_MBUS_PCIE1_MEM_ATTR,
+                                    DOVE_PCIE1_MEM_PHYS_BASE,
+                                    DOVE_PCIE1_MEM_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
+                                    DOVE_MBUS_CESA_ATTR,
+                                    DOVE_CESA_PHYS_BASE,
+                                    DOVE_CESA_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
+                                    DOVE_MBUS_BOOTROM_ATTR,
+                                    DOVE_BOOTROM_PHYS_BASE,
+                                    DOVE_BOOTROM_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
+                                    DOVE_MBUS_SCRATCHPAD_ATTR,
+                                    DOVE_SCRATCHPAD_PHYS_BASE,
+                                    DOVE_SCRATCHPAD_SIZE);
 }
 
 void __init dove_init(void)
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 6e122ed3282f..682b7ac8deb8 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,7 @@ static void __init kirkwood_dt_init(void)
          */
         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 
+        BUG_ON(mvebu_mbus_dt_init());
         kirkwood_setup_wins();
 
         kirkwood_l2_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index e9238b5567ee..15b7e72e890b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -37,6 +37,12 @@
 #include <linux/platform_data/dma-mv_xor.h>
 #include "common.h"
 
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_NAND_TARGET 0x01
+#define KIRKWOOD_MBUS_NAND_ATTR   0x2f
+#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
+#define KIRKWOOD_MBUS_SRAM_ATTR   0x01
+
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -528,10 +534,6 @@ void __init kirkwood_cpuidle_init(void)
 void __init kirkwood_init_early(void)
 {
         orion_time_set_base(TIMER_VIRT_BASE);
-
-        mvebu_mbus_init("marvell,kirkwood-mbus",
-                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
-                        DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
 }
 
 int kirkwood_tclk;
@@ -672,10 +674,14 @@ char * __init kirkwood_id(void)
 
 void __init kirkwood_setup_wins(void)
 {
-        mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
-                              KIRKWOOD_NAND_MEM_SIZE);
-        mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
-                              KIRKWOOD_SRAM_SIZE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
+                                    KIRKWOOD_MBUS_NAND_ATTR,
+                                    KIRKWOOD_NAND_MEM_PHYS_BASE,
+                                    KIRKWOOD_NAND_MEM_SIZE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
+                                    KIRKWOOD_MBUS_SRAM_ATTR,
+                                    KIRKWOOD_SRAM_PHYS_BASE,
+                                    KIRKWOOD_SRAM_SIZE);
 }
 
 void __init kirkwood_l2_init(void)
@@ -703,6 +709,10 @@ void __init kirkwood_init(void)
          */
         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 
+        BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus",
+                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
+                        DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ));
+
         kirkwood_setup_wins();
 
         kirkwood_l2_init();
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index ddcb09f5bdd3..12d86f39f380 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -20,6 +20,16 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET    0x4
+#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR      0xe8
+#define KIRKWOOD_MBUS_PCIE0_IO_TARGET     0x4
+#define KIRKWOOD_MBUS_PCIE0_IO_ATTR       0xe0
+#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET    0x4
+#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR      0xd8
+#define KIRKWOOD_MBUS_PCIE1_IO_TARGET     0x4
+#define KIRKWOOD_MBUS_PCIE1_IO_ATTR       0xd0
+
 static void kirkwood_enable_pcie_clk(const char *port)
 {
         struct clk *clk;
@@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base)
 
 void __init kirkwood_pcie_init(unsigned int portmask)
 {
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
+        mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
+                                          KIRKWOOD_MBUS_PCIE0_IO_ATTR,
                                           KIRKWOOD_PCIE_IO_PHYS_BASE,
                                           KIRKWOOD_PCIE_IO_SIZE,
-                                          KIRKWOOD_PCIE_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
+                                    KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
+                                    KIRKWOOD_PCIE_MEM_PHYS_BASE,
+                                    KIRKWOOD_PCIE_MEM_SIZE);
+        mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
+                                          KIRKWOOD_MBUS_PCIE1_IO_ATTR,
                                           KIRKWOOD_PCIE1_IO_PHYS_BASE,
                                           KIRKWOOD_PCIE1_IO_SIZE,
-                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
+                                          KIRKWOOD_PCIE1_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
+                                    KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
+                                    KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+                                    KIRKWOOD_PCIE1_MEM_SIZE);
 
         vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index dc26a654c496..445e553f4a28 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -18,6 +18,11 @@
 #include <mach/mv78xx0.h>
 #include "common.h"
 
+#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane)   (0xf8 & ~(0x10 << (lane)))
+#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane)  ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane)    (0xf0 & ~(0x10 << (lane)))
+
 struct pcie_port {
         u8                      maj;
         u8                      min;
@@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void)
         start = MV78XX0_PCIE_MEM_PHYS_BASE;
         for (i = 0; i < num_pcie_ports; i++) {
                 struct pcie_port *pp = pcie_port + i;
-                char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
 
                 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                         "PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void)
                 if (request_resource(&iomem_resource, &pp->res))
                         panic("can't allocate PCIe MEM sub-space");
 
-                snprintf(winname, sizeof(winname), "pcie%d.%d",
-                         pp->maj, pp->min);
-
-                mvebu_mbus_add_window_remap_flags(winname,
-                                                  pp->res.start,
-                                                  resource_size(&pp->res),
-                                                  MVEBU_MBUS_NO_REMAP,
-                                                  MVEBU_MBUS_PCI_MEM);
-                mvebu_mbus_add_window_remap_flags(winname,
-                                                  i * SZ_64K, SZ_64K,
-                                                  0, MVEBU_MBUS_PCI_IO);
+                mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
+                                            MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
+                                            pp->res.start, resource_size(&pp->res));
+                mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
+                                                  MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
+                                                  i * SZ_64K, SZ_64K, 0);
         }
 }
 
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 97cbb8021919..829b57306328 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void)
         debug_ll_io_init();
 }
 
-/*
- * This initialization will be replaced by a DT-based
- * initialization once the mvebu-mbus driver gains DT support.
- */
-
-#define ARMADA_370_XP_MBUS_WINS_OFFS   0x20000
-#define ARMADA_370_XP_MBUS_WINS_SIZE   0x100
-#define ARMADA_370_XP_SDRAM_WINS_OFFS  0x20180
-#define ARMADA_370_XP_SDRAM_WINS_SIZE  0x20
-
-static void __init armada_370_xp_mbus_init(void)
-{
-        char *mbus_soc_name;
-        struct device_node *dn;
-        const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
-        const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
-
-        if (of_machine_is_compatible("marvell,armada370"))
-                mbus_soc_name = "marvell,armada370-mbus";
-        else
-                mbus_soc_name = "marvell,armadaxp-mbus";
-
-        dn = of_find_node_by_name(NULL, "internal-regs");
-        BUG_ON(!dn);
-
-        mvebu_mbus_init(mbus_soc_name,
-                        of_translate_address(dn, &mbus_wins_offs),
-                        ARMADA_370_XP_MBUS_WINS_SIZE,
-                        of_translate_address(dn, &sdram_wins_offs),
-                        ARMADA_370_XP_SDRAM_WINS_SIZE);
-}
-
 static void __init armada_370_xp_timer_and_clk_init(void)
 {
         of_clk_init(NULL);
         armada_370_xp_timer_init();
         coherency_init();
-        armada_370_xp_mbus_init();
+        BUG_ON(mvebu_mbus_dt_init());
 #ifdef CONFIG_CACHE_L2X0
         l2x0_of_init(0, ~0UL);
 #endif
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index ce81d3031405..c6b00fce6d8d 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
 #include <linux/smp.h>
 #include <linux/clk.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/mbus.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -29,6 +30,9 @@
 #include "pmsu.h"
 #include "coherency.h"
 
+#define AXP_BOOTROM_BASE 0xfff00000
+#define AXP_BOOTROM_SIZE 0x100000
+
 void __init set_secondary_cpus_clock(void)
 {
         int thiscpu;
@@ -114,10 +118,29 @@ static void __init armada_xp_smp_init_cpus(void)
 
 void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
 {
+        struct device_node *node;
+        struct resource res;
+        int err;
+
         set_secondary_cpus_clock();
         flush_cache_all();
         set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-        mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
+
+        /*
+         * In order to boot the secondary CPUs we need to ensure
+         * the bootROM is mapped at the correct address.
+         */
+        node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
+        if (!node)
+                panic("Cannot find 'marvell,bootrom' compatible node");
+
+        err = of_address_to_resource(node, 0, &res);
+        if (err < 0)
+                panic("Cannot get 'bootrom' node address");
+
+        if (res.start != AXP_BOOTROM_BASE ||
+            resource_size(&res) != AXP_BOOTROM_SIZE)
+                panic("The address for the BootROM is incorrect");
 }
 
 struct smp_operations armada_xp_smp_ops __initdata = {
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b41599f98a8e..91a5852b44f3 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -174,8 +174,10 @@ void __init orion5x_xor_init(void)
  ****************************************************************************/
 static void __init orion5x_crypto_init(void)
 {
-        mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
-                              ORION5X_SRAM_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
+                                    ORION_MBUS_SRAM_ATTR,
+                                    ORION5X_SRAM_PHYS_BASE,
+                                    ORION5X_SRAM_SIZE);
         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
                           SZ_8K, IRQ_ORION5X_CESA);
 }
@@ -222,22 +224,24 @@ void orion5x_setup_wins(void)
          * The PCIe windows will no longer be statically allocated
          * here once Orion5x is migrated to the pci-mvebu driver.
          */
-        mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
+        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
+                                          ORION_MBUS_PCIE_IO_ATTR,
+                                          ORION5X_PCIE_IO_PHYS_BASE,
                                           ORION5X_PCIE_IO_SIZE,
-                                          ORION5X_PCIE_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
-                                          ORION5X_PCIE_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
+                                          ORION5X_PCIE_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
+                                    ORION_MBUS_PCIE_MEM_ATTR,
+                                    ORION5X_PCIE_MEM_PHYS_BASE,
+                                    ORION5X_PCIE_MEM_SIZE);
+        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
+                                          ORION_MBUS_PCI_IO_ATTR,
+                                          ORION5X_PCI_IO_PHYS_BASE,
                                           ORION5X_PCI_IO_SIZE,
-                                          ORION5X_PCI_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
-                                          ORION5X_PCI_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
+                                          ORION5X_PCI_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
+                                    ORION_MBUS_PCI_MEM_ATTR,
+                                    ORION5X_PCI_MEM_PHYS_BASE,
+                                    ORION5X_PCI_MEM_SIZE);
 }
 
 int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index a909afb384fb..f565f9944af2 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -7,6 +7,23 @@ struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
+#define ORION_MBUS_PCIE_MEM_TARGET    0x04
+#define ORION_MBUS_PCIE_MEM_ATTR      0x59
+#define ORION_MBUS_PCIE_IO_TARGET     0x04
+#define ORION_MBUS_PCIE_IO_ATTR       0x51
+#define ORION_MBUS_PCIE_WA_TARGET     0x04
+#define ORION_MBUS_PCIE_WA_ATTR       0x79
+#define ORION_MBUS_PCI_MEM_TARGET     0x03
+#define ORION_MBUS_PCI_MEM_ATTR       0x59
+#define ORION_MBUS_PCI_IO_TARGET      0x03
+#define ORION_MBUS_PCI_IO_ATTR        0x51
+#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
+#define ORION_MBUS_DEVBUS_BOOT_ATTR   0x0f
+#define ORION_MBUS_DEVBUS_TARGET(cs)  0x01
+#define ORION_MBUS_DEVBUS_ATTR(cs)    (~(1 << cs))
+#define ORION_MBUS_SRAM_TARGET        0x00
+#define ORION_MBUS_SRAM_ATTR          0x00
+
 /*
  * Basic Orion init functions used early by machine-setup.
  */
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 16c88bbabc98..8f68b745c1d5 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -317,8 +317,10 @@ static void __init d2net_init(void)
         d2net_sata_power_init();
         orion5x_sata_init(&d2net_sata_data);
 
-        mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
-                              D2NET_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    D2NET_NOR_BOOT_BASE,
+                                    D2NET_NOR_BOOT_SIZE);
         platform_device_register(&d2net_nor_flash);
 
         platform_device_register(&d2net_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4e1263da38bb..4b2aefd1d961 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -340,19 +340,27 @@ static void __init db88f5281_init(void)
         orion5x_uart0_init();
         orion5x_uart1_init();
 
-        mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
-                              DB88F5281_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    DB88F5281_NOR_BOOT_BASE,
+                                    DB88F5281_NOR_BOOT_SIZE);
         platform_device_register(&db88f5281_boot_flash);
 
-        mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
-                              DB88F5281_7SEG_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+                                    ORION_MBUS_DEVBUS_ATTR(0),
+                                    DB88F5281_7SEG_BASE,
+                                    DB88F5281_7SEG_SIZE);
 
-        mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
-                              DB88F5281_NOR_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+                                    ORION_MBUS_DEVBUS_ATTR(1),
+                                    DB88F5281_NOR_BASE,
+                                    DB88F5281_NOR_SIZE);
         platform_device_register(&db88f5281_nor_flash);
 
-        mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
-                              DB88F5281_NAND_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
+                                    ORION_MBUS_DEVBUS_ATTR(2),
+                                    DB88F5281_NAND_BASE,
+                                    DB88F5281_NAND_SIZE);
         platform_device_register(&db88f5281_nand_flash);
 
         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 9e6baf581ed3..70974732cbf0 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -611,8 +611,10 @@ static void __init dns323_init(void)
         /* setup flash mapping
          * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
          */
-        mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
-                              DNS323_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    DNS323_NOR_BOOT_BASE,
+                                    DNS323_NOR_BOOT_SIZE);
         platform_device_register(&dns323_nor_flash);
 
         /* Sort out LEDs, Buttons and i2c devices */
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 147615510dd0..0fc33c56cbb7 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -154,8 +154,10 @@ void __init edmini_v2_init(void)
         orion5x_ehci0_init();
         orion5x_eth_init(&edmini_v2_eth_data);
 
-        mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
-                              EDMINI_V2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    EDMINI_V2_NOR_BOOT_BASE,
+                                    EDMINI_V2_NOR_BOOT_SIZE);
         platform_device_register(&edmini_v2_nor_flash);
 
         pr_notice("edmini_v2: USB device port, flash write and power-off "
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index aae10e4a917c..fe6a48a325e8 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void)
         orion5x_uart1_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
-                              KUROBOX_PRO_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    KUROBOX_PRO_NOR_BOOT_BASE,
+                                    KUROBOX_PRO_NOR_BOOT_SIZE);
         platform_device_register(&kurobox_pro_nor_flash);
 
         if (machine_is_kurobox_pro()) {
-                mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
-                                      KUROBOX_PRO_NAND_SIZE);
+                mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+                                            ORION_MBUS_DEVBUS_ATTR(0),
+                                            KUROBOX_PRO_NAND_BASE,
+                                            KUROBOX_PRO_NAND_SIZE);
                 platform_device_register(&kurobox_pro_nand_flash);
         }
 
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6234977b5aea..028ea038d404 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -294,8 +294,10 @@ static void __init lschl_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
-                              LSCHL_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    LSCHL_NOR_BOOT_BASE,
+                                    LSCHL_NOR_BOOT_SIZE);
         platform_device_register(&lschl_nor_flash);
 
         platform_device_register(&lschl_leds);
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fe04c4b64569..32b7129b767d 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -243,8 +243,10 @@ static void __init ls_hgl_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
-                              LS_HGL_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    LS_HGL_NOR_BOOT_BASE,
+                                    LS_HGL_NOR_BOOT_SIZE);
         platform_device_register(&ls_hgl_nor_flash);
 
         platform_device_register(&ls_hgl_button_device);
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ca4dbe973daf..a6493e76f96d 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -244,8 +244,10 @@ static void __init lsmini_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
-                              LSMINI_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    LSMINI_NOR_BOOT_BASE,
+                                    LSMINI_NOR_BOOT_SIZE);
         platform_device_register(&lsmini_nor_flash);
 
         platform_device_register(&lsmini_button_device);
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 827acbafc9dc..e105130ba51c 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -241,8 +241,10 @@ static void __init mss2_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
-                              MSS2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    MSS2_NOR_BOOT_BASE,
+                                    MSS2_NOR_BOOT_SIZE);
         platform_device_register(&mss2_nor_flash);
 
         platform_device_register(&mss2_button_device);
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 92600ae2b4b6..e032f01da49e 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -204,8 +204,10 @@ static void __init mv2120_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
-                              MV2120_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    MV2120_NOR_BOOT_BASE,
+                                    MV2120_NOR_BOOT_SIZE);
         platform_device_register(&mv2120_nor_flash);
 
         platform_device_register(&mv2120_button_device);
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index dd0641a0d074..ba73dc7ffb9e 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -397,8 +397,10 @@ static void __init net2big_init(void)
         net2big_sata_power_init();
         orion5x_sata_init(&net2big_sata_data);
 
-        mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
-                              NET2BIG_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    NET2BIG_NOR_BOOT_BASE,
+                                    NET2BIG_NOR_BOOT_SIZE);
         platform_device_register(&net2big_nor_flash);
 
         platform_device_register(&net2big_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 503368023bb1..7fab67053030 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
                 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
                                    "read transaction workaround\n");
-                mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                                  ORION5X_PCIE_WA_PHYS_BASE,
-                                                  ORION5X_PCIE_WA_SIZE,
-                                                  MVEBU_MBUS_NO_REMAP,
-                                                  MVEBU_MBUS_PCI_WA);
+                mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
+                                            ORION_MBUS_PCIE_WA_ATTR,
+                                            ORION5X_PCIE_WA_PHYS_BASE,
+                                            ORION5X_PCIE_WA_SIZE);
                 pcie_ops.read = pcie_rd_conf_wa;
         }
 
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 1c4498bf650a..213b3e143c57 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void)
         orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
-                              RD88F5181L_FXO_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    RD88F5181L_FXO_NOR_BOOT_BASE,
+                                    RD88F5181L_FXO_NOR_BOOT_SIZE);
         platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
 }
 
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index adabe34c4fc6..594800e1d691 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void)
         orion5x_i2c_init();
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
-                              RD88F5181L_GE_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    RD88F5181L_GE_NOR_BOOT_BASE,
+                                    RD88F5181L_GE_NOR_BOOT_SIZE);
         platform_device_register(&rd88f5181l_ge_nor_boot_flash);
 
         i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 66e77ec91532..b1cf68493ffc 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -264,11 +264,14 @@ static void __init rd88f5182_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
-                              RD88F5182_NOR_BOOT_SIZE);
-
-        mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
-                              RD88F5182_NOR_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    RD88F5182_NOR_BOOT_BASE,
+                                    RD88F5182_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+                                    ORION_MBUS_DEVBUS_ATTR(1),
+                                    RD88F5182_NOR_BASE,
+                                    RD88F5182_NOR_SIZE);
         platform_device_register(&rd88f5182_nor_flash);
         platform_device_register(&rd88f5182_gpio_leds);
 
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index a0bfa53e7556..7e9064844698 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -329,8 +329,10 @@ static void __init tsp2_init(void)
         /*
          * Configure peripherals.
          */
-        mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
-                              TSP2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    TSP2_NOR_BOOT_BASE,
+                                    TSP2_NOR_BOOT_SIZE);
         platform_device_register(&tsp2_nor_flash);
 
         orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 80174f0f168e..e90c0618fdad 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void)
         /*
          * Configure peripherals.
          */
-        mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
-                              QNAP_TS209_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    QNAP_TS209_NOR_BOOT_BASE,
+                                    QNAP_TS209_NOR_BOOT_SIZE);
         platform_device_register(&qnap_ts209_nor_flash);
 
         orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 92592790d6da..5c079d312015 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void)
         /*
          * Configure peripherals.
          */
-        mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
-                              QNAP_TS409_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    QNAP_TS409_NOR_BOOT_BASE,
+                                    QNAP_TS409_NOR_BOOT_SIZE);
         platform_device_register(&qnap_ts409_nor_flash);
 
         orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 6b84863c018d..80a56ee245b3 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -127,8 +127,10 @@ static void __init wnr854t_init(void)
         orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
-                              WNR854T_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    WNR854T_NOR_BOOT_BASE,
+                                    WNR854T_NOR_BOOT_SIZE);
         platform_device_register(&wnr854t_nor_flash);
 }
 
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fae684bc54f2..670e30dc0d1b 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void)
         orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
-                              WRT350N_V2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    WRT350N_V2_NOR_BOOT_BASE,
+                                    WRT350N_V2_NOR_BOOT_SIZE);
         platform_device_register(&wrt350n_v2_nor_flash);
         platform_device_register(&wrt350n_v2_leds);
         platform_device_register(&wrt350n_v2_button_device);
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 02cc34388b05..c4525a88e5da 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -34,7 +34,10 @@ static void sirfsoc_set_wakeup_source(void)
         pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
                 SIRFSOC_PWRC_TRIGGER_EN);
 #define X_ON_KEY_B (1 << 0)
-        sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B,
+#define RTC_ALARM0_B (1 << 2)
+#define RTC_ALARM1_B (1 << 3)
+        sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B |
+                RTC_ALARM0_B | RTC_ALARM1_B,
                 sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
 }
 
@@ -85,12 +88,6 @@ static const struct platform_suspend_ops sirfsoc_pm_ops = {
         .valid = suspend_valid_only_mem,
 };
 
-int __init sirfsoc_pm_init(void)
-{
-        suspend_set_ops(&sirfsoc_pm_ops);
-        return 0;
-}
-
 static const struct of_device_id pwrc_ids[] = {
         { .compatible = "sirf,prima2-pwrc" },
         {}
@@ -118,7 +115,6 @@ static int __init sirfsoc_of_pwrc_init(void)
 
         return 0;
 }
-postcore_initcall(sirfsoc_of_pwrc_init);
 
 static const struct of_device_id memc_ids[] = {
         { .compatible = "sirf,prima2-memc" },
@@ -149,4 +145,11 @@ static int __init sirfsoc_memc_init(void)
 {
         return platform_driver_register(&sirfsoc_memc_driver);
 }
-postcore_initcall(sirfsoc_memc_init);
+
+int __init sirfsoc_pm_init(void)
+{
+        sirfsoc_of_pwrc_init();
+        sirfsoc_memc_init();
+        suspend_set_ops(&sirfsoc_pm_ops);
+        return 0;
+}
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3912ce91fee4..dd80f215feeb 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,9 +23,10 @@ config ARCH_R8A73A4
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
@@ -59,7 +60,6 @@ config ARCH_R8A7790
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
 
@@ -156,6 +156,18 @@ config MACH_KZM9D
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select USE_OF
 
+config MACH_KZM9D_REFERENCE
+        bool "KZM9D board - Reference Device Tree Implementation"
+        depends on ARCH_EMEV2
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select USE_OF
+        ---help---
+           Use reference implementation of KZM9D board support
+           which makes a greater use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
+
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 6165a517f580..e8d0a2c904a0 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_LAGER)	+= board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
 obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
+obj-$(CONFIG_MACH_KZM9D_REFERENCE)      += board-kzm9d-reference.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
 
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 84c6868580f0..7785c52b5cfd 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,6 +7,7 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
 loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000
 loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
+loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
 loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 5eb0caa6a7d0..af6dd39d3758 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -20,7 +20,6 @@
 
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
@@ -102,7 +101,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-        .init_irq       = irqchip_init,
+        .init_early     = r8a73a4_init_delay,
         .init_time      = shmobile_timer_init,
         .init_machine   = ape6evm_add_standard_devices,
         .dt_compat      = ape6evm_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index c5be60d85e4b..f6952c266fe9 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -679,15 +679,6 @@ static struct platform_device vcc_sdhi1 = {
 };
 
 /* SDHI0 */
-/*
- * FIXME
- *
- * It use polling mode here, since
- * CD (= Card Detect) pin is not connected to SDHI0_CD.
- * We can use IRQ31 as card detect irq,
- * but it needs chattering removal operation
- */
-#define IRQ31   irq_pin(31)
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c
new file mode 100644
index 000000000000..a7b28b24ab38
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c
@@ -0,0 +1,46 @@
+/*
+ * kzm9d board support - Reference DT implementation
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <mach/emev2.h>
+#include <mach/common.h>
+#include <asm/mach/arch.h>
+
+static void __init kzm9d_add_standard_devices(void)
+{
+        emev2_clock_init();
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *kzm9d_boards_compat_dt[] __initdata = {
+        "renesas,kzm9d-reference",
+        NULL,
+};
+
+DT_MACHINE_START(KZM9D_DT, "kzm9d")
+        .smp            = smp_ops(emev2_smp_ops),
+        .map_io         = emev2_map_io,
+        .init_early     = emev2_init_delay,
+        .init_machine   = kzm9d_add_standard_devices,
+        .init_late      = shmobile_init_late,
+        .dt_compat      = kzm9d_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 4368000e1127..30c2cc695b12 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -85,9 +85,7 @@ static const char *kzm9d_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(KZM9D_DT, "kzm9d")
         .smp            = smp_ops(emev2_smp_ops),
         .map_io         = emev2_map_io,
-        .init_early     = emev2_add_early_devices,
-        .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = emev2_init_irq,
+        .init_early     = emev2_init_delay,
         .init_machine   = kzm9d_add_standard_devices,
         .init_late      = shmobile_init_late,
         .dt_compat      = kzm9d_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 44055fe8a45c..41092bb01ee5 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -24,7 +24,6 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/input.h>
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
@@ -99,7 +98,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
         .init_machine   = kzm_init,
         .init_time      = shmobile_timer_init,
         .dt_compat      = kzm9g_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 8d6bd5c5efb9..f89f16650731 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -22,7 +22,6 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
 #include <linux/pinctrl/machine.h>
@@ -103,7 +102,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
-        .init_irq       = irqchip_init,
+        .init_early     = r8a7790_init_delay,
         .init_time      = r8a7790_timer_init,
         .init_machine   = lager_add_standard_devices,
         .dt_compat      = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
index 4710f1847bb7..5ac13ba71d54 100644
--- a/arch/arm/mach-shmobile/clock-emev2.c
+++ b/arch/arm/mach-shmobile/clock-emev2.c
@@ -40,7 +40,6 @@
 #define USIB2SCLKDIV 0x65c
 #define USIB3SCLKDIV 0x660
 #define STI_CLKSEL 0x688
-#define SMU_GENERAL_REG0 0x7c0
 
 /* not pretty, but hey */
 static void __iomem *smu_base;
@@ -51,11 +50,6 @@ static void emev2_smu_write(unsigned long value, int offs)
         iowrite32(value, smu_base + offs);
 }
 
-void emev2_set_boot_vector(unsigned long value)
-{
-        emev2_smu_write(value, SMU_GENERAL_REG0);
-}
-
 static struct clk_mapping smu_mapping = {
         .phys   = EMEV2_SMU_BASE,
         .len    = PAGE_SIZE,
@@ -205,23 +199,11 @@ static struct clk_lookup lookups[] = {
 void __init emev2_clock_init(void)
 {
         int k, ret = 0;
-        static int is_setup;
-
-        /* yuck, this is ugly as hell, but the non-smp case of clocks
-         * code is now designed to rely on ioremap() instead of static
-         * entity maps. in the case of smp we need access to the SMU
-         * register earlier than ioremap() is actually working without
-         * any static maps. to enable SMP in ugly but with dynamic
-         * mappings we have to call emev2_clock_init() from different
-         * places depending on UP and SMP...
-         */
-        if (is_setup++)
-                return;
 
         smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
         BUG_ON(!smu_base);
 
-        /* setup STI timer to run on 37.768 kHz and deassert reset */
+        /* setup STI timer to run on 32.768 kHz and deassert reset */
         emev2_smu_write(0, STI_CLKSEL);
         emev2_smu_write(1, STI_RSTCTRL);
 
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 5f7fe628b8a1..8ea5ef6c79cc 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -30,10 +30,12 @@
 
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR4 0xe6150140
 #define SMSTPCR5 0xe6150144
 
 #define FRQCRA          0xE6150000
 #define FRQCRB          0xE6150004
+#define FRQCRC          0xE61500E0
 #define VCLKCR1         0xE6150008
 #define VCLKCR2         0xE615000C
 #define VCLKCR3         0xE615001C
@@ -52,6 +54,7 @@
 #define HSICKCR         0xE615026C
 #define M4CKCR          0xE6150098
 #define PLLECR          0xE61500D0
+#define PLL0CR          0xE61500D8
 #define PLL1CR          0xE6150028
 #define PLL2CR          0xE615002C
 #define PLL2SCR         0xE61501F4
@@ -177,6 +180,7 @@ static struct sh_clk_ops pll_clk_ops = {
                 .mapping        = &cpg_mapping,         \
         }
 
+PLL_CLOCK(pll0_clk,  &main_clk,      pll_parent_main,      1, 20, PLL0CR,  0);
 PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
 PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
 PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
@@ -184,6 +188,157 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
 
 SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
 
+static atomic_t frqcr_lock;
+
+/* Several clocks need to access FRQCRB, have to lock */
+static bool frqcr_kick_check(struct clk *clk)
+{
+        return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
+}
+
+static int frqcr_kick_do(struct clk *clk)
+{
+        int i;
+
+        /* set KICK bit in FRQCRB to update hardware setting, check success */
+        iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
+        for (i = 1000; i; i--)
+                if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
+                        cpu_relax();
+                else
+                        return 0;
+
+        return -ETIMEDOUT;
+}
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        void __iomem *frqcrc;
+        int ret;
+        unsigned long step, p_rate;
+        u32 val;
+
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+
+        if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
+                ret = -EBUSY;
+                goto done;
+        }
+
+        /*
+         * Users are supposed to first call clk_set_rate() only with
+         * clk_round_rate() results. So, we don't fix wrong rates here, but
+         * guard against them anyway
+         */
+
+        p_rate = clk_get_rate(clk->parent);
+        if (rate == p_rate) {
+                val = 0;
+        } else {
+                step = DIV_ROUND_CLOSEST(p_rate, 32);
+
+                if (rate > p_rate || rate < step) {
+                        ret = -EINVAL;
+                        goto done;
+                }
+
+                val = 32 - rate / step;
+        }
+
+        frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
+        iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
+                  (val << clk->enable_bit), frqcrc);
+
+        ret = frqcr_kick_do(clk);
+
+done:
+        atomic_dec(&frqcr_lock);
+        __clk_put(clk->parent);
+        return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        /*
+         * theoretical rate = parent rate * multiplier / 32,
+         * where 1 <= multiplier <= 32. Therefore we should do
+         * multiplier = rate * 32 / parent rate
+         * rounded rate = parent rate * multiplier / 32.
+         * However, multiplication before division won't fit in 32 bits, so
+         * we sacrifice some precision by first dividing and then multiplying.
+         * To find the nearest divisor we calculate both and pick up the best
+         * one. This avoids 64-bit arithmetics.
+         */
+        unsigned long step, mul_min, mul_max, rate_min, rate_max;
+
+        rate_max = clk_get_rate(clk->parent);
+
+        /* output freq <= parent */
+        if (rate >= rate_max)
+                return rate_max;
+
+        step = DIV_ROUND_CLOSEST(rate_max, 32);
+        /* output freq >= parent / 32 */
+        if (step >= rate)
+                return step;
+
+        mul_min = rate / step;
+        mul_max = DIV_ROUND_UP(rate, step);
+        rate_min = step * mul_min;
+        if (mul_max == mul_min)
+                return rate_min;
+
+        rate_max = step * mul_max;
+
+        if (rate_max - rate <  rate - rate_min)
+                return rate_max;
+
+        return rate_min;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
+        unsigned int max = clk->div_mask + 1;
+        unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
+                             clk->div_mask);
+
+        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
+                (max - val);
+}
+
+static struct sh_clk_ops zclk_ops = {
+        .recalc = zclk_recalc,
+        .set_rate = zclk_set_rate,
+        .round_rate = zclk_round_rate,
+};
+
+static struct clk z_clk = {
+        .parent = &pll0_clk,
+        .div_mask = 0x1f,
+        .enable_bit = 8,
+        /* We'll need to access FRQCRB and FRQCRC */
+        .enable_reg = (void __iomem *)FRQCRB,
+        .ops = &zclk_ops,
+};
+
+/*
+ * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
+ * switching is only available in auto-DVFS mode
+ */
+SH_FIXED_RATIO_CLK(pll0_div2_clk,       pll0_clk,               div2);
+
+static struct clk z2_clk = {
+        .parent = &pll0_div2_clk,
+        .div_mask = 0x1f,
+        .enable_bit = 0,
+        /* We'll need to access FRQCRB and FRQCRC */
+        .enable_reg = (void __iomem *)FRQCRB,
+        .ops = &zclk_ops,
+};
+
 static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
@@ -195,22 +350,23 @@ static struct clk *main_clks[] = {
         &main_div2_clk,
         &fsiack_clk,
         &fsibck_clk,
+        &pll0_clk,
         &pll1_clk,
         &pll1_div2_clk,
         &pll2_clk,
         &pll2s_clk,
         &pll2h_clk,
+        &z_clk,
+        &pll0_div2_clk,
+        &z2_clk,
 };
 
 /* DIV4 */
 static void div4_kick(struct clk *clk)
 {
-        unsigned long value;
-
-        /* set KICK bit in FRQCRB to update hardware setting */
-        value = ioread32(CPG_MAP(FRQCRB));
-        value |= (1 << 31);
-        iowrite32(value, CPG_MAP(FRQCRB));
+        if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
+                frqcr_kick_do(clk);
+        atomic_dec(&frqcr_lock);
 }
 
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
@@ -349,8 +505,10 @@ static struct clk div6_clks[DIV6_NR] = {
 /* MSTP */
 enum {
         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
-        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
-        MSTP522,
+        MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
+        MSTP411, MSTP410, MSTP409,
+        MSTP522, MSTP515,
         MSTP_NR
 };
 
@@ -361,12 +519,22 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 0, 0), /* IIC2 */
         [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
         [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
         [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
+        [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 16, 0), /* IIC6 */
+        [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 17, 0), /* IIC7 */
+        [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 18, 0), /* IIC0 */
+        [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP409] = SH_CLK_MSTP32(&main_div2_clk,       SMSTPCR4, 9, 0), /* IIC5 */
+        [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 10, 0), /* IIC4 */
+        [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 11, 0), /* IIC3 */
         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
+        [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR5, 15, 0), /* IIC8 */
 };
 
 static struct clk_lookup lookups[] = {
@@ -386,6 +554,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
         CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
 
+        /* CPU clock */
+        CLKDEV_DEV_ID("cpufreq-cpu0",           &z_clk),
+
         /* DIV6 */
         CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
         CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
@@ -408,6 +579,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
@@ -418,6 +590,15 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
+        CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
+        CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
+        CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
+        CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
+        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
+        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
+        CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
 
         /* for DT */
         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -429,6 +610,8 @@ void __init r8a73a4_clock_init(void)
         int k, ret = 0;
         u32 ckscr;
 
+        atomic_set(&frqcr_lock, -1);
+
         reg = ioremap_nocache(CKSCR, PAGE_SIZE);
         BUG_ON(!reg);
         ckscr = ioread32(reg);
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index de10fd78bf2b..c826bca4024e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -596,7 +596,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("r8a7740-gether",         &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
-        CLKDEV_DEV_ID("renesas_tpu_pwm",        &mstp_clks[MSTP304]),
+        CLKDEV_DEV_ID("renesas-tpu-pwm",        &mstp_clks[MSTP304]),
+        CLKDEV_DEV_ID("e6600000.pwm",           &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
         CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 5d71313df52d..fc36d3db0b4d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -24,6 +24,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7790.h>
 
 /*
  *   MD         EXTAL           PLL0    PLL1    PLL3
@@ -42,16 +43,16 @@
  *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
  */
 
-#define MD(nr)  (1 << nr)
-
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
+#define SMSTPCR1 0xe6150134
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR5 0xe6150144
 #define SMSTPCR7 0xe615014c
+#define SMSTPCR8 0xe6150990
 
-#define MODEMR          0xE6160060
 #define SDCKCR          0xE6150074
 #define SD2CKCR         0xE6150078
 #define SD3CKCR         0xE615007C
@@ -180,16 +181,23 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+        MSTP813,
         MSTP721, MSTP720,
         MSTP717, MSTP716,
+        MSTP522,
         MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
         MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP124,
         MSTP_NR
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
+        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
         [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
@@ -203,8 +211,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
         [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
         [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
-        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
-        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
 };
 
 static struct clk_lookup lookups[] = {
@@ -254,6 +261,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+        CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
@@ -266,6 +275,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
         CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
 };
 
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
@@ -280,14 +290,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7790_clock_init(void)
 {
-        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-        u32 mode;
+        u32 mode = r8a7790_read_mode_pins();
         int k, ret = 0;
 
-        BUG_ON(!modemr);
-        mode = ioread32(modemr);
-        iounmap(modemr);
-
         switch (mode & (MD(14) | MD(13))) {
         case 0:
                 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bfd920083a3b..f45dde701d7b 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -37,13 +37,15 @@ ENTRY(shmobile_boot_scu)
         lsl     r1, r1, #3              @ we will shift by cpu_id * 8 bits
         ldr     r2, [r0, #8]            @ SCU Power Status Register
         mov     r3, #3
-        bic     r2, r2, r3, lsl r1      @ Clear bits of our CPU (Run Mode)
+        lsl     r3, r3, r1
+        bic     r2, r2, r3              @ Clear bits of our CPU (Run Mode)
         str     r2, [r0, #8]            @ write back
 
         b       shmobile_invalidate_start
 ENDPROC(shmobile_boot_scu)
 
         .text
+        .align  2
         .globl  shmobile_scu_base
 shmobile_scu_base:
         .space  4
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index a9d212498987..2667db806c39 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -24,12 +24,16 @@ ENDPROC(shmobile_invalidate_start)
  * This will be mapped at address 0 by SBAR register.
  * We need _long_ jump to the physical address.
  */
+        .arm
         .align  12
 ENTRY(shmobile_boot_vector)
         ldr     r0, 2f
-        ldr     pc, 1f
+        ldr     r1, 1f
+        bx      r1
+
 ENDPROC(shmobile_boot_vector)
 
+        .align  2
         .globl  shmobile_boot_fn
 shmobile_boot_fn:
 1:      .space  4
diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-shmobile/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index ac3751705cab..c2eb7568d9be 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -2,11 +2,9 @@
 #define __ASM_EMEV2_H__
 
 extern void emev2_map_io(void);
-extern void emev2_init_irq(void);
-extern void emev2_add_early_devices(void);
+extern void emev2_init_delay(void);
 extern void emev2_add_standard_devices(void);
 extern void emev2_clock_init(void);
-extern void emev2_set_boot_vector(unsigned long value);
 
 #define EMEV2_GPIO_BASE 200
 #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f043103e32c9..144a85e29245 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -4,5 +4,6 @@
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
+void r8a73a4_init_delay(void);
 
 #endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index b34d19b5ca5c..56f375005fcd 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -42,6 +42,8 @@ enum {
         SHDMA_SLAVE_FSIB_TX,
         SHDMA_SLAVE_USBHS_TX,
         SHDMA_SLAVE_USBHS_RX,
+        SHDMA_SLAVE_MMCIF_TX,
+        SHDMA_SLAVE_MMCIF_RX,
 };
 
 extern void r8a7740_meram_workaround(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 851d027a2f06..9b561bf4229f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -33,7 +33,6 @@ extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info);
 
 extern void r8a7778_init_late(void);
 extern void r8a7778_init_delay(void);
-extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 2e919e61fa0d..7aaef409a059 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -4,6 +4,10 @@
 void r8a7790_add_standard_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
+void r8a7790_init_delay(void);
 void r8a7790_timer_init(void);
 
+#define MD(nr) BIT(nr)
+u32 r8a7790_read_mode_pins(void);
+
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index f2d8744c1f14..c3c4669a2d72 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -1,7 +1,6 @@
 #ifndef ZBOOT_H
 #define ZBOOT_H
 
-#include <asm/mach-types.h>
 #include <mach/zboot_macros.h>
 
 /**************************************************
@@ -11,7 +10,6 @@
  **************************************************/
 
 #ifdef CONFIG_MACH_MACKEREL
-#define MACH_TYPE       MACH_TYPE_MACKEREL
 #define MEMORY_START    0x40000000
 #include "mach/head-mackerel.txt"
 #else
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 1ccddd228112..19980be7d6a9 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -20,7 +20,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/gpio-em.h>
 #include <linux/of_platform.h>
@@ -39,13 +38,6 @@
 
 static struct map_desc emev2_io_desc[] __initdata = {
 #ifdef CONFIG_SMP
-        /* 128K entity map for 0xe0100000 (SMU) */
-        {
-                .virtual        = 0xe0100000,
-                .pfn            = __phys_to_pfn(0xe0100000),
-                .length         = SZ_128K,
-                .type           = MT_DEVICE
-        },
         /* 2M mapping for SCU + L2 controller */
         {
                 .virtual        = 0xf0000000,
@@ -63,102 +55,40 @@ void __init emev2_map_io(void)
 
 /* UART */
 static struct resource uart0_resources[] = {
-        [0]     = {
-                .start  = 0xe1020000,
-                .end    = 0xe1020037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 40,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device uart0_device = {
-        .name           = "serial8250-em",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-        .resource       = uart0_resources,
+        DEFINE_RES_MEM(0xe1020000, 0x38),
+        DEFINE_RES_IRQ(40),
 };
 
 static struct resource uart1_resources[] = {
-        [0]     = {
-                .start  = 0xe1030000,
-                .end    = 0xe1030037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 41,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device uart1_device = {
-        .name           = "serial8250-em",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-        .resource       = uart1_resources,
+        DEFINE_RES_MEM(0xe1030000, 0x38),
+        DEFINE_RES_IRQ(41),
 };
 
 static struct resource uart2_resources[] = {
-        [0]     = {
-                .start  = 0xe1040000,
-                .end    = 0xe1040037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 42,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device uart2_device = {
-        .name           = "serial8250-em",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-        .resource       = uart2_resources,
+        DEFINE_RES_MEM(0xe1040000, 0x38),
+        DEFINE_RES_IRQ(42),
 };
 
 static struct resource uart3_resources[] = {
-        [0]     = {
-                .start  = 0xe1050000,
-                .end    = 0xe1050037,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = 43,
-                .flags  = IORESOURCE_IRQ,
-        }
+        DEFINE_RES_MEM(0xe1050000, 0x38),
+        DEFINE_RES_IRQ(43),
 };
 
-static struct platform_device uart3_device = {
-        .name           = "serial8250-em",
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(uart3_resources),
-        .resource       = uart3_resources,
-};
+#define emev2_register_uart(idx)                                        \
+        platform_device_register_simple("serial8250-em", idx,           \
+                                        uart##idx##_resources,          \
+                                        ARRAY_SIZE(uart##idx##_resources))
 
 /* STI */
 static struct resource sti_resources[] = {
-        [0] = {
-                .name   = "STI",
-                .start  = 0xe0180000,
-                .end    = 0xe0180053,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 157,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device sti_device = {
-        .name           = "em_sti",
-        .id             = 0,
-        .resource       = sti_resources,
-        .num_resources  = ARRAY_SIZE(sti_resources),
+        DEFINE_RES_MEM(0xe0180000, 0x54),
+        DEFINE_RES_IRQ(157),
 };
 
+#define emev2_register_sti()                                    \
+        platform_device_register_simple("em_sti", 0,            \
+                                        sti_resources,          \
+                                        ARRAY_SIZE(sti_resources))
 
 /* GIO */
 static struct gpio_em_config gio0_config = {
@@ -168,36 +98,10 @@ static struct gpio_em_config gio0_config = {
 };
 
 static struct resource gio0_resources[] = {
-        [0] = {
-                .name   = "GIO_000",
-                .start  = 0xe0050000,
-                .end    = 0xe005002b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_000",
-                .start  = 0xe0050040,
-                .end    = 0xe005005f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 99,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 100,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio0_device = {
-        .name           = "em_gio",
-        .id             = 0,
-        .resource       = gio0_resources,
-        .num_resources  = ARRAY_SIZE(gio0_resources),
-        .dev            = {
-                .platform_data  = &gio0_config,
-        },
+        DEFINE_RES_MEM(0xe0050000, 0x2c),
+        DEFINE_RES_MEM(0xe0050040, 0x20),
+        DEFINE_RES_IRQ(99),
+        DEFINE_RES_IRQ(100),
 };
 
 static struct gpio_em_config gio1_config = {
@@ -207,36 +111,10 @@ static struct gpio_em_config gio1_config = {
 };
 
 static struct resource gio1_resources[] = {
-        [0] = {
-                .name   = "GIO_032",
-                .start  = 0xe0050080,
-                .end    = 0xe00500ab,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_032",
-                .start  = 0xe00500c0,
-                .end    = 0xe00500df,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 101,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 102,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio1_device = {
-        .name           = "em_gio",
-        .id             = 1,
-        .resource       = gio1_resources,
-        .num_resources  = ARRAY_SIZE(gio1_resources),
-        .dev            = {
-                .platform_data  = &gio1_config,
-        },
+        DEFINE_RES_MEM(0xe0050080, 0x2c),
+        DEFINE_RES_MEM(0xe00500c0, 0x20),
+        DEFINE_RES_IRQ(101),
+        DEFINE_RES_IRQ(102),
 };
 
 static struct gpio_em_config gio2_config = {
@@ -246,36 +124,10 @@ static struct gpio_em_config gio2_config = {
 };
 
 static struct resource gio2_resources[] = {
-        [0] = {
-                .name   = "GIO_064",
-                .start  = 0xe0050100,
-                .end    = 0xe005012b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_064",
-                .start  = 0xe0050140,
-                .end    = 0xe005015f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 103,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 104,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio2_device = {
-        .name           = "em_gio",
-        .id             = 2,
-        .resource       = gio2_resources,
-        .num_resources  = ARRAY_SIZE(gio2_resources),
-        .dev            = {
-                .platform_data  = &gio2_config,
-        },
+        DEFINE_RES_MEM(0xe0050100, 0x2c),
+        DEFINE_RES_MEM(0xe0050140, 0x20),
+        DEFINE_RES_IRQ(103),
+        DEFINE_RES_IRQ(104),
 };
 
 static struct gpio_em_config gio3_config = {
@@ -285,36 +137,10 @@ static struct gpio_em_config gio3_config = {
 };
 
 static struct resource gio3_resources[] = {
-        [0] = {
-                .name   = "GIO_096",
-                .start  = 0xe0050180,
-                .end    = 0xe00501ab,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_096",
-                .start  = 0xe00501c0,
-                .end    = 0xe00501df,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 105,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 106,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device gio3_device = {
-        .name           = "em_gio",
-        .id             = 3,
-        .resource       = gio3_resources,
-        .num_resources  = ARRAY_SIZE(gio3_resources),
-        .dev            = {
-                .platform_data  = &gio3_config,
-        },
+        DEFINE_RES_MEM(0xe0050180, 0x2c),
+        DEFINE_RES_MEM(0xe00501c0, 0x20),
+        DEFINE_RES_IRQ(105),
+        DEFINE_RES_IRQ(106),
 };
 
 static struct gpio_em_config gio4_config = {
@@ -324,126 +150,52 @@ static struct gpio_em_config gio4_config = {
 };
 
 static struct resource gio4_resources[] = {
-        [0] = {
-                .name   = "GIO_128",
-                .start  = 0xe0050200,
-                .end    = 0xe005022b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "GIO_128",
-                .start  = 0xe0050240,
-                .end    = 0xe005025f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = 107,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = 108,
-                .flags  = IORESOURCE_IRQ,
-        },
+        DEFINE_RES_MEM(0xe0050200, 0x2c),
+        DEFINE_RES_MEM(0xe0050240, 0x20),
+        DEFINE_RES_IRQ(107),
+        DEFINE_RES_IRQ(108),
 };
 
-static struct platform_device gio4_device = {
-        .name           = "em_gio",
-        .id             = 4,
-        .resource       = gio4_resources,
-        .num_resources  = ARRAY_SIZE(gio4_resources),
-        .dev            = {
-                .platform_data  = &gio4_config,
-        },
-};
+#define emev2_register_gio(idx)                                         \
+        platform_device_register_resndata(&platform_bus, "em_gio",      \
+                                          idx, gio##idx##_resources,    \
+                                          ARRAY_SIZE(gio##idx##_resources), \
+                                          &gio##idx##_config,           \
+                                          sizeof(struct gpio_em_config))
 
 static struct resource pmu_resources[] = {
-        [0] = {
-                .start  = 152,
-                .end    = 152,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = 153,
-                .end    = 153,
-                .flags  = IORESOURCE_IRQ,
-        },
+        DEFINE_RES_IRQ(152),
+        DEFINE_RES_IRQ(153),
 };
 
-static struct platform_device pmu_device = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(pmu_resources),
-        .resource       = pmu_resources,
-};
-
-static struct platform_device *emev2_early_devices[] __initdata = {
-        &uart0_device,
-        &uart1_device,
-        &uart2_device,
-        &uart3_device,
-};
-
-static struct platform_device *emev2_late_devices[] __initdata = {
-        &sti_device,
-        &gio0_device,
-        &gio1_device,
-        &gio2_device,
-        &gio3_device,
-        &gio4_device,
-        &pmu_device,
-};
+#define emev2_register_pmu()                                    \
+        platform_device_register_simple("arm-pmu", -1,          \
+                                        pmu_resources,          \
+                                        ARRAY_SIZE(pmu_resources))
 
 void __init emev2_add_standard_devices(void)
 {
         emev2_clock_init();
 
-        platform_add_devices(emev2_early_devices,
-                             ARRAY_SIZE(emev2_early_devices));
-
-        platform_add_devices(emev2_late_devices,
-                             ARRAY_SIZE(emev2_late_devices));
+        emev2_register_uart(0);
+        emev2_register_uart(1);
+        emev2_register_uart(2);
+        emev2_register_uart(3);
+        emev2_register_sti();
+        emev2_register_gio(0);
+        emev2_register_gio(1);
+        emev2_register_gio(2);
+        emev2_register_gio(3);
+        emev2_register_gio(4);
+        emev2_register_pmu();
 }
 
-static void __init emev2_init_delay(void)
+void __init emev2_init_delay(void)
 {
         shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
 
-void __init emev2_add_early_devices(void)
-{
-        emev2_init_delay();
-
-        early_platform_add_devices(emev2_early_devices,
-                                   ARRAY_SIZE(emev2_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-
-void __init emev2_init_irq(void)
-{
-        void __iomem *gic_dist_base;
-        void __iomem *gic_cpu_base;
-
-        /* Static mappings, never released */
-        gic_dist_base = ioremap(0xe0028000, PAGE_SIZE);
-        gic_cpu_base = ioremap(0xe0020000, PAGE_SIZE);
-        BUG_ON(!gic_dist_base || !gic_cpu_base);
-
-        /* Use GIC to handle interrupts */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
-}
-
 #ifdef CONFIG_USE_OF
-static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
-        { }
-};
-
-static void __init emev2_add_standard_devices_dt(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             emev2_auxdata_lookup, NULL);
-}
 
 static const char *emev2_boards_compat_dt[] __initdata = {
         "renesas,emev2",
@@ -452,10 +204,8 @@ static const char *emev2_boards_compat_dt[] __initdata = {
 
 DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
         .smp            = smp_ops(emev2_smp_ops),
+        .map_io         = emev2_map_io,
         .init_early     = emev2_init_delay,
-        .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
-        .init_machine   = emev2_add_standard_devices_dt,
         .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 7f45c2edbca9..d533bd23865c 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -18,11 +18,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a73a4.h>
@@ -169,6 +169,25 @@ static const struct resource thermal0_resources[] = {
                                         thermal0_resources,             \
                                         ARRAY_SIZE(thermal0_resources))
 
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .timer_bit = 0,
+        .clockevent_rating = 80,
+};
+
+static struct resource cmt10_resources[] = {
+        DEFINE_RES_MEM(0xe6130010, 0x0c),
+        DEFINE_RES_MEM(0xe6130000, 0x04),
+        DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
+};
+
+#define r8a7790_register_cmt(idx)                                       \
+        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+                                          idx, cmt##idx##_resources,    \
+                                          ARRAY_SIZE(cmt##idx##_resources), \
+                                          &cmt##idx##_platform_data,    \
+                                          sizeof(struct sh_timer_config))
+
 void __init r8a73a4_add_standard_devices(void)
 {
         r8a73a4_register_scif(SCIFA0);
@@ -180,11 +199,20 @@ void __init r8a73a4_add_standard_devices(void)
         r8a73a4_register_irqc(0);
         r8a73a4_register_irqc(1);
         r8a73a4_register_thermal();
+        r8a7790_register_cmt(10);
+}
+
+void __init r8a73a4_init_delay(void)
+{
+#ifndef CONFIG_ARM_ARCH_TIMER
+        shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
+#endif
 }
 
 #ifdef CONFIG_USE_OF
 void __init r8a73a4_add_standard_devices_dt(void)
 {
+        platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -194,7 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
-        .init_irq       = irqchip_init,
+        .init_early     = r8a73a4_init_delay,
         .init_machine   = r8a73a4_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a73a4_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 00c5a707238b..84c5bb6d9725 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -588,6 +588,16 @@ static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
                 .addr           = 0xfe1f0064,
                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
                 .mid_rid        = 0xb5,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd2,
         },
 };
 
@@ -986,16 +996,22 @@ void __init r8a7740_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
-        { }
-};
+void __init r8a7740_add_early_devices_dt(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+
+        early_platform_add_devices(r8a7740_early_devices,
+                                   ARRAY_SIZE(r8a7740_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
 
 void __init r8a7740_add_standard_devices_dt(void)
 {
         platform_add_devices(r8a7740_devices_dt,
                             ARRAY_SIZE(r8a7740_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             r8a7740_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 void __init r8a7740_init_delay(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 80c20392ad7c..a3a2e37b03f3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -53,7 +53,7 @@
         .irqs           = SCIx_IRQ_MUXED(irq),                  \
 }
 
-static struct plat_sci_port scif_platform_data[] = {
+static struct plat_sci_port scif_platform_data[] __initdata = {
         SCIF_INFO(0xffe40000, gic_iid(0x66)),
         SCIF_INFO(0xffe41000, gic_iid(0x67)),
         SCIF_INFO(0xffe42000, gic_iid(0x68)),
@@ -63,24 +63,24 @@ static struct plat_sci_port scif_platform_data[] = {
 };
 
 /* TMU */
-static struct resource sh_tmu0_resources[] = {
+static struct resource sh_tmu0_resources[] __initdata = {
         DEFINE_RES_MEM(0xffd80008, 12),
         DEFINE_RES_IRQ(gic_iid(0x40)),
 };
 
-static struct sh_timer_config sh_tmu0_platform_data = {
+static struct sh_timer_config sh_tmu0_platform_data __initdata = {
         .name                   = "TMU00",
         .channel_offset         = 0x4,
         .timer_bit              = 0,
         .clockevent_rating      = 200,
 };
 
-static struct resource sh_tmu1_resources[] = {
+static struct resource sh_tmu1_resources[] __initdata = {
         DEFINE_RES_MEM(0xffd80014, 12),
         DEFINE_RES_IRQ(gic_iid(0x41)),
 };
 
-static struct sh_timer_config sh_tmu1_platform_data = {
+static struct sh_timer_config sh_tmu1_platform_data __initdata = {
         .name                   = "TMU01",
         .channel_offset         = 0x10,
         .timer_bit              = 1,
@@ -189,7 +189,7 @@ USB_PLATFORM_INFO(ehci);
 USB_PLATFORM_INFO(ohci);
 
 /* Ether */
-static struct resource ether_resources[] = {
+static struct resource ether_resources[] __initdata = {
         DEFINE_RES_MEM(0xfde00000, 0x400),
         DEFINE_RES_IRQ(gic_iid(0x89)),
 };
@@ -203,17 +203,17 @@ void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
 }
 
 /* PFC/GPIO */
-static struct resource pfc_resources[] = {
+static struct resource pfc_resources[] __initdata = {
         DEFINE_RES_MEM(0xfffc0000, 0x118),
 };
 
 #define R8A7778_GPIO(idx)                                               \
-static struct resource r8a7778_gpio##idx##_resources[] = {              \
+static struct resource r8a7778_gpio##idx##_resources[] __initdata = {   \
         DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
         DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
 };                                                                      \
                                                                         \
-static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
         .gpio_base      = 32 * (idx),                                   \
         .irq_base       = GPIO_IRQ_BASE(idx),                           \
         .number_of_pins = 32,                                           \
@@ -249,7 +249,7 @@ void __init r8a7778_pinmux_init(void)
 };
 
 /* SDHI */
-static struct resource sdhi_resources[] = {
+static struct resource sdhi_resources[] __initdata = {
         /* SDHI0 */
         DEFINE_RES_MEM(0xFFE4C000, 0x100),
         DEFINE_RES_IRQ(gic_iid(0x77)),
@@ -365,12 +365,12 @@ void __init r8a7778_init_late(void)
         platform_device_register_full(&ohci_info);
 }
 
-static struct renesas_intc_irqpin_config irqpin_platform_data = {
+static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
         .sense_bitfield_width = 2,
 };
 
-static struct resource irqpin_resources[] = {
+static struct resource irqpin_resources[] __initdata = {
         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
@@ -408,17 +408,25 @@ void __init r8a7778_init_irq_extpin(int irlm)
                         &irqpin_platform_data, sizeof(irqpin_platform_data));
 }
 
+void __init r8a7778_init_delay(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+}
+
+#ifdef CONFIG_USE_OF
 #define INT2SMSKCR0     0x82288 /* 0xfe782288 */
 #define INT2SMSKCR1     0x8228c /* 0xfe78228c */
 
 #define INT2NTSR0       0x00018 /* 0xfe700018 */
 #define INT2NTSR1       0x0002c /* 0xfe70002c */
-static void __init r8a7778_init_irq_common(void)
+void __init r8a7778_init_irq_dt(void)
 {
         void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
 
         BUG_ON(!base);
 
+        irqchip_init();
+
         /* route all interrupts to ARM */
         __raw_writel(0x73ffffff, base + INT2NTSR0);
         __raw_writel(0xffffffff, base + INT2NTSR1);
@@ -430,43 +438,6 @@ static void __init r8a7778_init_irq_common(void)
         iounmap(base);
 }
 
-void __init r8a7778_init_irq(void)
-{
-        void __iomem *gic_dist_base;
-        void __iomem *gic_cpu_base;
-
-        gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
-        gic_cpu_base  = ioremap_nocache(0xfe430000, PAGE_SIZE);
-        BUG_ON(!gic_dist_base || !gic_cpu_base);
-
-        /* use GIC to handle interrupts */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
-
-        r8a7778_init_irq_common();
-}
-
-void __init r8a7778_init_delay(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-}
-
-#ifdef CONFIG_USE_OF
-void __init r8a7778_init_irq_dt(void)
-{
-        irqchip_init();
-        r8a7778_init_irq_common();
-}
-
-static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
-        {},
-};
-
-void __init r8a7778_add_standard_devices_dt(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             r8a7778_auxdata_lookup, NULL);
-}
-
 static const char *r8a7778_compat_dt[] __initdata = {
         "renesas,r8a7778",
         NULL,
@@ -475,7 +446,6 @@ static const char *r8a7778_compat_dt[] __initdata = {
 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
         .init_early     = r8a7778_init_delay,
         .init_irq       = r8a7778_init_irq_dt,
-        .init_machine   = r8a7778_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7778_compat_dt,
         .init_late      = r8a7778_init_late,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 398687761f50..66d38261ecaa 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -665,10 +665,6 @@ void __init r8a7779_init_delay(void)
         shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
 }
 
-static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
-        {},
-};
-
 void __init r8a7779_add_standard_devices_dt(void)
 {
         /* clocks are setup late during boot in the case of DT */
@@ -676,8 +672,7 @@ void __init r8a7779_add_standard_devices_dt(void)
 
         platform_add_devices(r8a7779_devices_dt,
                              ARRAY_SIZE(r8a7779_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             r8a7779_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char *r8a7779_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 28f94752b8ff..4c96dad21195 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -19,12 +19,12 @@
  */
 
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
-#include <linux/serial_sci.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
@@ -149,6 +149,36 @@ static struct resource irqc0_resources[] __initdata = {
                                           &irqc##idx##_data,            \
                                           sizeof(struct renesas_irqc_config))
 
+static struct resource thermal_resources[] __initdata = {
+        DEFINE_RES_MEM(0xe61f0000, 0x14),
+        DEFINE_RES_MEM(0xe61f0100, 0x38),
+        DEFINE_RES_IRQ(gic_spi(69)),
+};
+
+#define r8a7790_register_thermal()                                      \
+        platform_device_register_simple("rcar_thermal", -1,             \
+                                        thermal_resources,              \
+                                        ARRAY_SIZE(thermal_resources))
+
+static struct sh_timer_config cmt00_platform_data = {
+        .name = "CMT00",
+        .timer_bit = 0,
+        .clockevent_rating = 80,
+};
+
+static struct resource cmt00_resources[] = {
+        DEFINE_RES_MEM(0xffca0510, 0x0c),
+        DEFINE_RES_MEM(0xffca0500, 0x04),
+        DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
+};
+
+#define r8a7790_register_cmt(idx)                                       \
+        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+                                          idx, cmt##idx##_resources,    \
+                                          ARRAY_SIZE(cmt##idx##_resources), \
+                                          &cmt##idx##_platform_data,    \
+                                          sizeof(struct sh_timer_config))
+
 void __init r8a7790_add_standard_devices(void)
 {
         r8a7790_register_scif(SCIFA0);
@@ -162,34 +192,91 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_scif(HSCIF0);
         r8a7790_register_scif(HSCIF1);
         r8a7790_register_irqc(0);
+        r8a7790_register_thermal();
+        r8a7790_register_cmt(00);
 }
 
+#define MODEMR 0xe6160060
+
+u32 __init r8a7790_read_mode_pins(void)
+{
+        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+        u32 mode;
+
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        return mode;
+}
+
+#define CNTCR 0
+#define CNTFID0 0x20
+
 void __init r8a7790_timer_init(void)
 {
-        void __iomem *cntcr;
+#ifdef CONFIG_ARM_ARCH_TIMER
+        u32 mode = r8a7790_read_mode_pins();
+        void __iomem *base;
+        int extal_mhz = 0;
+        u32 freq;
+
+        /* At Linux boot time the r8a7790 arch timer comes up
+         * with the counter disabled. Moreover, it may also report
+         * a potentially incorrect fixed 13 MHz frequency. To be
+         * correct these registers need to be updated to use the
+         * frequency EXTAL / 2 which can be determined by the MD pins.
+         */
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                extal_mhz = 15;
+                break;
+        case MD(13):
+                extal_mhz = 20;
+                break;
+        case MD(14):
+                extal_mhz = 26;
+                break;
+        case MD(13) | MD(14):
+                extal_mhz = 30;
+                break;
+        }
 
-        /* make sure arch timer is started by setting bit 0 of CNTCT */
-        cntcr = ioremap(0xe6080000, PAGE_SIZE);
-        iowrite32(1, cntcr);
-        iounmap(cntcr);
+        /* The arch timer frequency equals EXTAL / 2 */
+        freq = extal_mhz * (1000000 / 2);
+
+        /* Remap "armgcnt address map" space */
+        base = ioremap(0xe6080000, PAGE_SIZE);
+
+        /* Update registers with correct frequency */
+        iowrite32(freq, base + CNTFID0);
+        asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+        /* make sure arch timer is started by setting bit 0 of CNTCR */
+        iowrite32(1, base + CNTCR);
+        iounmap(base);
+#endif /* CONFIG_ARM_ARCH_TIMER */
 
         shmobile_timer_init();
 }
 
-#ifdef CONFIG_USE_OF
-void __init r8a7790_add_standard_devices_dt(void)
+void __init r8a7790_init_delay(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+#ifndef CONFIG_ARM_ARCH_TIMER
+        shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
+#endif
 }
 
+#ifdef CONFIG_USE_OF
+
 static const char *r8a7790_boards_compat_dt[] __initdata = {
         "renesas,r8a7790",
         NULL,
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
-        .init_irq       = irqchip_init,
-        .init_machine   = r8a7790_add_standard_devices_dt,
+        .init_early     = r8a7790_init_delay,
         .init_time      = r8a7790_timer_init,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5502d624aca6..13e6fdbde0a5 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1147,10 +1147,6 @@ void __init sh7372_add_early_devices_dt(void)
         shmobile_setup_console();
 }
 
-static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
-        { }
-};
-
 void __init sh7372_add_standard_devices_dt(void)
 {
         /* clocks are setup late during boot in the case of DT */
@@ -1159,8 +1155,7 @@ void __init sh7372_add_standard_devices_dt(void)
         platform_add_devices(sh7372_early_devices,
                             ARRAY_SIZE(sh7372_early_devices));
 
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             sh7372_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char *sh7372_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 96e7ca1e4e11..516c2391b47a 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,7 +22,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -61,29 +60,16 @@ void __init sh73a0_map_io(void)
         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
 }
 
-static struct resource sh73a0_pfc_resources[] = {
-        [0] = {
-                .start  = 0xe6050000,
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605801c,
-                .end    = 0xe6058027,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device sh73a0_pfc_device = {
-        .name           = "pfc-sh73a0",
-        .id             = -1,
-        .resource       = sh73a0_pfc_resources,
-        .num_resources  = ARRAY_SIZE(sh73a0_pfc_resources),
+/* PFC */
+static struct resource pfc_resources[] __initdata = {
+        DEFINE_RES_MEM(0xe6050000, 0x8000),
+        DEFINE_RES_MEM(0xe605801c, 0x000c),
 };
 
 void __init sh73a0_pinmux_init(void)
 {
-        platform_device_register(&sh73a0_pfc_device);
+        platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
+                                        ARRAY_SIZE(pfc_resources));
 }
 
 static struct plat_sci_port scif0_platform_data = {
@@ -958,10 +944,6 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
-        {},
-};
-
 void __init sh73a0_add_standard_devices_dt(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
@@ -971,8 +953,7 @@ void __init sh73a0_add_standard_devices_dt(void)
 
         platform_add_devices(sh73a0_devices_dt,
                              ARRAY_SIZE(sh73a0_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             sh73a0_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         /* Instantiate cpufreq-cpu0 */
         platform_device_register_full(&devinfo);
@@ -988,7 +969,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
         .map_io         = sh73a0_map_io,
         .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
         .init_machine   = sh73a0_add_standard_devices_dt,
         .dt_compat      = sh73a0_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 53f4840e4949..9782862899e8 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -41,6 +41,7 @@
 sh7372_resume_core_standby_sysc:
         ldr     pc, 1f
 
+        .align  2
         .globl  sh7372_cpu_resume
 sh7372_cpu_resume:
 1:      .space  4
@@ -96,6 +97,7 @@ sh7372_do_idle_sysc:
 1:
         b      1b
 
+        .align  2
 kernel_flush:
         .word v7_flush_dcache_all
 #endif
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 22a05a869d25..78e84c582453 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -29,6 +29,8 @@
 #include <asm/smp_scu.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
+#define EMEV2_SMU_BASE 0xe0110000
+#define SMU_GENERAL_REG0 0x7c0
 
 static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
@@ -38,10 +40,18 @@ static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
+        void __iomem *smu;
+
+        /* setup EMEV2 specific SCU base, enable */
+        shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
         scu_enable(shmobile_scu_base);
 
         /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
-        emev2_set_boot_vector(__pa(shmobile_boot_vector));
+        smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
+        if (smu) {
+                iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0);
+                iounmap(smu);
+        }
         shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
         shmobile_boot_arg = (unsigned long)shmobile_scu_base;
 
@@ -49,21 +59,7 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
         scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
-static void __init emev2_smp_init_cpus(void)
-{
-        unsigned int ncores;
-
-        /* setup EMEV2 specific SCU base */
-        shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
-        emev2_clock_init(); /* need ioremapped SMU */
-
-        ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
-
-        shmobile_smp_init_cpus(ncores);
-}
-
 struct smp_operations emev2_smp_ops __initdata = {
-        .smp_init_cpus          = emev2_smp_init_cpus,
         .smp_prepare_cpus       = emev2_smp_prepare_cpus,
         .smp_boot_secondary     = emev2_boot_secondary,
 };
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index b8bbabec6310..c700e623f9d8 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB
           This is needed to provide CPU and cluster power management
           on RTSM implementing big.LITTLE.
 
+config ARCH_VEXPRESS_TC2_PM
+        bool "Versatile Express TC2 power management"
+        depends on MCPM
+        select ARM_CCI
+        help
+          Support for CPU and cluster power management on Versatile Express
+          with a TC2 (A15x2 A7x3) big.LITTLE core tile.
+
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 48ba89a8149f..36ea8247123a 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
+obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM)      += tc2_pm.o spc.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 16d57a8a9d5a..3a6384c6c435 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -136,14 +136,35 @@ static void dcscb_power_down(void)
                 /*
                  * Flush all cache levels for this cluster.
                  *
-                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
-                 * a preliminary flush here for those CPUs.  At least, that's
-                 * the theory -- without the extra flush, Linux explodes on
-                 * RTSM (to be investigated).
+                 * To do so we do:
+                 * - Clear the SCTLR.C bit to prevent further cache allocations
+                 * - Flush the whole cache
+                 * - Clear the ACTLR "SMP" bit to disable local coherency
+                 *
+                 * Let's do it in the safest possible way i.e. with
+                 * no memory access within the following sequence
+                 * including to the stack.
+                 *
+                 * Note: fp is preserved to the stack explicitly prior doing
+                 * this since adding it to the clobber list is incompatible
+                 * with having CONFIG_FRAME_POINTER=y.
                  */
-                flush_cache_all();
-                set_cr(get_cr() & ~CR_C);
-                flush_cache_all();
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_all \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
 
                 /*
                  * This is a harmless no-op.  On platforms with a real
@@ -152,9 +173,6 @@ static void dcscb_power_down(void)
                  */
                 outer_flush_all();
 
-                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
-                set_auxcr(get_auxcr() & ~(1 << 6));
-
                 /*
                  * Disable cluster-level coherency by masking
                  * incoming snoops and DVM messages:
@@ -167,18 +185,24 @@ static void dcscb_power_down(void)
 
                 /*
                  * Flush the local CPU cache.
-                 *
-                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
-                 * a preliminary flush here for those CPUs.  At least, that's
-                 * the theory -- without the extra flush, Linux explodes on
-                 * RTSM (to be investigated).
+                 * Let's do it in the safest possible way as above.
                  */
-                flush_cache_louis();
-                set_cr(get_cr() & ~CR_C);
-                flush_cache_louis();
-
-                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
-                set_auxcr(get_auxcr() & ~(1 << 6));
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_louis \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
         }
 
         __mcpm_cpu_down(cpu, cluster);
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
new file mode 100644
index 000000000000..eefb029197ca
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.c
@@ -0,0 +1,180 @@
+/*
+ * Versatile Express Serial Power Controller (SPC) support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
+ *          Achin Gupta           <achin.gupta@arm.com>
+ *          Lorenzo Pieralisi     <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+
+#define SPCLOG "vexpress-spc: "
+
+/* SPC wake-up IRQs status and mask */
+#define WAKE_INT_MASK           0x24
+#define WAKE_INT_RAW            0x28
+#define WAKE_INT_STAT           0x2c
+/* SPC power down registers */
+#define A15_PWRDN_EN            0x30
+#define A7_PWRDN_EN             0x34
+/* SPC per-CPU mailboxes */
+#define A15_BX_ADDR0            0x68
+#define A7_BX_ADDR0             0x78
+
+/* wake-up interrupt masks */
+#define GBL_WAKEUP_INT_MSK      (0x3 << 10)
+
+/* TC2 static dual-cluster configuration */
+#define MAX_CLUSTERS            2
+
+struct ve_spc_drvdata {
+        void __iomem *baseaddr;
+        /*
+         * A15s cluster identifier
+         * It corresponds to A15 processors MPIDR[15:8] bitfield
+         */
+        u32 a15_clusid;
+};
+
+static struct ve_spc_drvdata *info;
+
+static inline bool cluster_is_a15(u32 cluster)
+{
+        return cluster == info->a15_clusid;
+}
+
+/**
+ * ve_spc_global_wakeup_irq()
+ *
+ * Function to set/clear global wakeup IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @set: if true, global wake-up IRQs are set, if false they are cleared
+ */
+void ve_spc_global_wakeup_irq(bool set)
+{
+        u32 reg;
+
+        reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+
+        if (set)
+                reg |= GBL_WAKEUP_INT_MSK;
+        else
+                reg &= ~GBL_WAKEUP_INT_MSK;
+
+        writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
+}
+
+/**
+ * ve_spc_cpu_wakeup_irq()
+ *
+ * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @set: if true, wake-up IRQs are set, if false they are cleared
+ */
+void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
+{
+        u32 mask, reg;
+
+        if (cluster >= MAX_CLUSTERS)
+                return;
+
+        mask = 1 << cpu;
+
+        if (!cluster_is_a15(cluster))
+                mask <<= 4;
+
+        reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+
+        if (set)
+                reg |= mask;
+        else
+                reg &= ~mask;
+
+        writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
+}
+
+/**
+ * ve_spc_set_resume_addr() - set the jump address used for warm boot
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @addr: physical resume address
+ */
+void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
+{
+        void __iomem *baseaddr;
+
+        if (cluster >= MAX_CLUSTERS)
+                return;
+
+        if (cluster_is_a15(cluster))
+                baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
+        else
+                baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
+
+        writel_relaxed(addr, baseaddr);
+}
+
+/**
+ * ve_spc_powerdown()
+ *
+ * Function to enable/disable cluster powerdown. Not protected by locking
+ * since it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @enable: if true enables powerdown, if false disables it
+ */
+void ve_spc_powerdown(u32 cluster, bool enable)
+{
+        u32 pwdrn_reg;
+
+        if (cluster >= MAX_CLUSTERS)
+                return;
+
+        pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
+        writel_relaxed(enable, info->baseaddr + pwdrn_reg);
+}
+
+int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid)
+{
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
+        if (!info) {
+                pr_err(SPCLOG "unable to allocate mem\n");
+                return -ENOMEM;
+        }
+
+        info->baseaddr = baseaddr;
+        info->a15_clusid = a15_clusid;
+
+        /*
+         * Multi-cluster systems may need this data when non-coherent, during
+         * cluster power-up/power-down. Make sure driver info reaches main
+         * memory.
+         */
+        sync_cache_w(info);
+        sync_cache_w(&info);
+
+        return 0;
+}
diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h
new file mode 100644
index 000000000000..5f7e4a446a17
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.h
@@ -0,0 +1,24 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+
+
+#ifndef __SPC_H_
+#define __SPC_H_
+
+int __init ve_spc_init(void __iomem *base, u32 a15_clusid);
+void ve_spc_global_wakeup_irq(bool set);
+void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set);
+void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr);
+void ve_spc_powerdown(u32 cluster, bool enable);
+
+#endif
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
new file mode 100644
index 000000000000..2b7c93a724ed
--- /dev/null
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -0,0 +1,352 @@
+/*
+ * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
+ *
+ * Created by:  Nicolas Pitre, October 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * Some portions of this file were originally written by Achin Gupta
+ * Copyright:   (C) 2012  ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+#include <linux/arm-cci.h>
+
+#include "spc.h"
+
+/* SCC conf registers */
+#define A15_CONF                0x400
+#define A7_CONF                 0x500
+#define SYS_INFO                0x700
+#define SPC_BASE                0xb00
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+#define TC2_CLUSTERS                    2
+#define TC2_MAX_CPUS_PER_CLUSTER        3
+
+static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
+
+/* Keep per-cpu usage count to cope with unordered up/down requests */
+static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
+
+#define tc2_cluster_unused(cluster) \
+        (!tc2_pm_use_count[0][cluster] && \
+         !tc2_pm_use_count[1][cluster] && \
+         !tc2_pm_use_count[2][cluster])
+
+static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
+{
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
+                return -EINVAL;
+
+        /*
+         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+         * variant exists, we need to disable IRQs manually here.
+         */
+        local_irq_disable();
+        arch_spin_lock(&tc2_pm_lock);
+
+        if (tc2_cluster_unused(cluster))
+                ve_spc_powerdown(cluster, false);
+
+        tc2_pm_use_count[cpu][cluster]++;
+        if (tc2_pm_use_count[cpu][cluster] == 1) {
+                ve_spc_set_resume_addr(cluster, cpu,
+                                       virt_to_phys(mcpm_entry_point));
+                ve_spc_cpu_wakeup_irq(cluster, cpu, true);
+        } else if (tc2_pm_use_count[cpu][cluster] != 2) {
+                /*
+                 * The only possible values are:
+                 * 0 = CPU down
+                 * 1 = CPU (still) up
+                 * 2 = CPU requested to be up before it had a chance
+                 *     to actually make itself down.
+                 * Any other value is a bug.
+                 */
+                BUG();
+        }
+
+        arch_spin_unlock(&tc2_pm_lock);
+        local_irq_enable();
+
+        return 0;
+}
+
+static void tc2_pm_down(u64 residency)
+{
+        unsigned int mpidr, cpu, cluster;
+        bool last_man = false, skip_wfi = false;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
+
+        __mcpm_cpu_going_down(cpu, cluster);
+
+        arch_spin_lock(&tc2_pm_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        tc2_pm_use_count[cpu][cluster]--;
+        if (tc2_pm_use_count[cpu][cluster] == 0) {
+                ve_spc_cpu_wakeup_irq(cluster, cpu, true);
+                if (tc2_cluster_unused(cluster)) {
+                        ve_spc_powerdown(cluster, true);
+                        ve_spc_global_wakeup_irq(true);
+                        last_man = true;
+                }
+        } else if (tc2_pm_use_count[cpu][cluster] == 1) {
+                /*
+                 * A power_up request went ahead of us.
+                 * Even if we do not want to shut this CPU down,
+                 * the caller expects a certain state as if the WFI
+                 * was aborted.  So let's continue with cache cleaning.
+                 */
+                skip_wfi = true;
+        } else
+                BUG();
+
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                arch_spin_unlock(&tc2_pm_lock);
+
+                if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+                        /*
+                         * On the Cortex-A15 we need to disable
+                         * L2 prefetching before flushing the cache.
+                         */
+                        asm volatile(
+                        "mcr    p15, 1, %0, c15, c0, 3 \n\t"
+                        "isb    \n\t"
+                        "dsb    "
+                        : : "r" (0x400) );
+                }
+
+                /*
+                 * We need to disable and flush the whole (L1 and L2) cache.
+                 * Let's do it in the safest possible way i.e. with
+                 * no memory access within the following sequence
+                 * including the stack.
+                 *
+                 * Note: fp is preserved to the stack explicitly prior doing
+                 * this since adding it to the clobber list is incompatible
+                 * with having CONFIG_FRAME_POINTER=y.
+                 */
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_all \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
+
+                cci_disable_port_by_cpu(mpidr);
+
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                /*
+                 * If last man then undo any setup done previously.
+                 */
+                if (last_man) {
+                        ve_spc_powerdown(cluster, false);
+                        ve_spc_global_wakeup_irq(false);
+                }
+
+                arch_spin_unlock(&tc2_pm_lock);
+
+                /*
+                 * We need to disable and flush only the L1 cache.
+                 * Let's do it in the safest possible way as above.
+                 */
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_louis \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
+        }
+
+        __mcpm_cpu_down(cpu, cluster);
+
+        /* Now we are prepared for power-down, do it: */
+        if (!skip_wfi)
+                wfi();
+
+        /* Not dead at this point?  Let our caller cope. */
+}
+
+static void tc2_pm_power_down(void)
+{
+        tc2_pm_down(0);
+}
+
+static void tc2_pm_suspend(u64 residency)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
+        tc2_pm_down(residency);
+}
+
+static void tc2_pm_powered_up(void)
+{
+        unsigned int mpidr, cpu, cluster;
+        unsigned long flags;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
+
+        local_irq_save(flags);
+        arch_spin_lock(&tc2_pm_lock);
+
+        if (tc2_cluster_unused(cluster)) {
+                ve_spc_powerdown(cluster, false);
+                ve_spc_global_wakeup_irq(false);
+        }
+
+        if (!tc2_pm_use_count[cpu][cluster])
+                tc2_pm_use_count[cpu][cluster] = 1;
+
+        ve_spc_cpu_wakeup_irq(cluster, cpu, false);
+        ve_spc_set_resume_addr(cluster, cpu, 0);
+
+        arch_spin_unlock(&tc2_pm_lock);
+        local_irq_restore(flags);
+}
+
+static const struct mcpm_platform_ops tc2_pm_power_ops = {
+        .power_up       = tc2_pm_power_up,
+        .power_down     = tc2_pm_power_down,
+        .suspend        = tc2_pm_suspend,
+        .powered_up     = tc2_pm_powered_up,
+};
+
+static bool __init tc2_pm_usage_count_init(void)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
+                pr_err("%s: boot CPU is out of bound!\n", __func__);
+                return false;
+        }
+        tc2_pm_use_count[cpu][cluster] = 1;
+        return true;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
+{
+        asm volatile (" \n"
+"       cmp     r0, #1 \n"
+"       bxne    lr \n"
+"       b       cci_enable_port_for_self ");
+}
+
+static int __init tc2_pm_init(void)
+{
+        int ret;
+        void __iomem *scc;
+        u32 a15_cluster_id, a7_cluster_id, sys_info;
+        struct device_node *np;
+
+        /*
+         * The power management-related features are hidden behind
+         * SCC registers. We need to extract runtime information like
+         * cluster ids and number of CPUs really available in clusters.
+         */
+        np = of_find_compatible_node(NULL, NULL,
+                        "arm,vexpress-scc,v2p-ca15_a7");
+        scc = of_iomap(np, 0);
+        if (!scc)
+                return -ENODEV;
+
+        a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
+        a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
+        if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
+                return -EINVAL;
+
+        sys_info = readl_relaxed(scc + SYS_INFO);
+        tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
+        tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
+
+        /*
+         * A subset of the SCC registers is also used to communicate
+         * with the SPC (power controller). We need to be able to
+         * drive it very early in the boot process to power up
+         * processors, so we initialize the SPC driver here.
+         */
+        ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id);
+        if (ret)
+                return ret;
+
+        if (!cci_probed())
+                return -ENODEV;
+
+        if (!tc2_pm_usage_count_init())
+                return -EINVAL;
+
+        ret = mcpm_platform_register(&tc2_pm_power_ops);
+        if (!ret) {
+                mcpm_sync_init(tc2_pm_power_up_setup);
+                pr_info("TC2 power management initialized\n");
+        }
+        return ret;
+}
+
+early_initcall(tc2_pm_init);