213 files changed, 5554 insertions, 3865 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b8dcec..fb1ee1c07021 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -299,9 +299,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-wandboard.dtb \
         imx6q-wandboard-revb1.dtb
 dtb-$(CONFIG_SOC_IMX6SL) += \
-        imx6sl-evk.dtb
+        imx6sl-evk.dtb \
+        imx6sl-warp.dtb
 dtb-$(CONFIG_SOC_IMX6SX) += \
         imx6sx-sabreauto.dtb \
+        imx6sx-sdb-reva.dtb \
         imx6sx-sdb.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
         ls1021a-qds.dtb \
@@ -386,6 +388,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
         omap3-overo-storm-tobi.dtb \
         omap3-overo-summit.dtb \
         omap3-overo-tobi.dtb \
+        omap3-pandora-600mhz.dtb \
+        omap3-pandora-1ghz.dtb \
         omap3-sbc-t3517.dtb \
         omap3-sbc-t3530.dtb \
         omap3-sbc-t3730.dtb \
@@ -401,7 +405,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \
         am335x-evmsk.dtb \
         am335x-nano.dtb \
         am335x-pepper.dtb \
-        am335x-lxm.dtb
+        am335x-lxm.dtb \
+        am335x-chiliboard.dtb
 dtb-$(CONFIG_ARCH_OMAP4) += \
         omap4-duovero-parlor.dtb \
         omap4-panda.dtb \
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 6cc25ed912ee..2c6248d9a9ef 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -195,6 +195,7 @@
 
 &usb0 {
         status = "okay";
+        dr_mode = "peripheral";
 };
 
 &usb1 {
diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
new file mode 100644
index 000000000000..310da20a8aa7
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy <lisovy@jablotron.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "am335x-chilisom.dtsi"
+
+/ {
+        model = "AM335x Chiliboard";
+        compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
+                     "ti,am33xx";
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_gpio_pins>;
+
+                led0 {
+                        label = "led0";
+                        gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led1 {
+                        label = "led1";
+                        gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                };
+        };
+};
+
+&am33xx_pinmux {
+        usb1_drvvbus: usb1_drvvbus {
+                pinctrl-single,pins = <
+                        0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
+                >;
+        };
+
+        sd_pins: pinmux_sd_card {
+                pinctrl-single,pins = <
+                        0xf0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+                        0xf4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+                        0xf8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+                        0xfc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+                        0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+                        0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+                        0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                >;
+        };
+
+        led_gpio_pins: led_gpio_pins {
+                pinctrl-single,pins = <
+                        0x1e4 (PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
+                        0x1e8 (PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
+                >;
+        };
+};
+
+&ldo4_reg {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+};
+
+/* Ethernet */
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "rmii";
+};
+
+&phy_sel {
+        rmii-clock-ext;
+};
+
+/* USB */
+&usb {
+        status = "okay";
+};
+
+&usb_ctrl_mod {
+        status = "okay";
+};
+
+&usb1_phy {
+        status = "okay";
+};
+
+&usb1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_drvvbus>;
+
+        status = "okay";
+        dr_mode = "host";
+};
+
+&cppi41dma  {
+        status = "okay";
+};
+
+/* microSD */
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd_pins>;
+        vmmc-supply = <&ldo4_reg>;
+        bus-width = <0x4>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi
new file mode 100644
index 000000000000..7e9a34dffe21
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chilisom.dtsi
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy <lisovy@jablotron.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "am33xx.dtsi"
+
+/ {
+        model = "Grinn AM335x ChiliSOM";
+        compatible = "grinn,am335x-chilisom", "ti,am33xx";
+
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&dcdc2_reg>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+};
+
+&am33xx_pinmux {
+        pinctrl-names = "default";
+
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                        0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                >;
+        };
+
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                        0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                >;
+        };
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
+                        0x110 (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxerr.rmii1_rxerr */
+                        0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
+                        0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+                        0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+                        0x13c (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd1.rmii1_rxd1 */
+                        0x140 (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd0.rmii1_rxd0 */
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_ref_clk.rmii_ref_clk */
+                >;
+        };
+
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* mdio_data.mdio_data */
+                        0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+                        /* mdio_clk.mdio_clk */
+                        0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                >;
+        };
+
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        nandflash_pins: nandflash_pins {
+                pinctrl-single,pins = <
+                        0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
+                        0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
+                        0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
+                        0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
+                        0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
+                        0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
+                        0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
+                        0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
+
+                        0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                        0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_csn0.gpmc_csn0 */
+                        0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_advn_ale.gpmc_advn_ale */
+                        0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_oen_ren.gpmc_oen_ren */
+                        0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_wen.gpmc_wen */
+                        0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_be0n_cle.gpmc_be0n_cle */
+                >;
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+
+        status = "okay";
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tps: tps@24 {
+                reg = <0x24>;
+        };
+
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+        regulators {
+                dcdc1_reg: regulator@0 {
+                        regulator-name = "vdds_dpr";
+                        regulator-always-on;
+                };
+
+                dcdc2_reg: regulator@1 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1325000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc3_reg: regulator@2 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo1_reg: regulator@3 {
+                        regulator-name = "vio,vrtc,vdds";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo2_reg: regulator@4 {
+                        regulator-name = "vdd_3v3aux";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo3_reg: regulator@5 {
+                        regulator-name = "vdd_1v8";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo4_reg: regulator@6 {
+                        regulator-name = "vdd_3v3d";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+        };
+};
+
+/* Ethernet MAC */
+&mac {
+        slaves = <1>;
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        status = "okay";
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+};
+
+/* NAND Flash */
+&elm {
+        status = "okay";
+};
+
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nandflash_pins>;
+        ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
+        nand@0,0 {
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <8>;
+                gpmc,device-width = <1>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wait-on-read = "true";
+                gpmc,wait-on-write = "true";
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
index a3466455b171..5ed4ca6eaf55 100644
--- a/arch/arm/boot/dts/am335x-nano.dts
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -213,7 +213,9 @@
         pinctrl-0 = <&i2c0_pins>;
 
         gpio@20 {
-                compatible = "mcp,mcp23017";
+                compatible = "microchip,mcp23017";
+                gpio-controller;
+                #gpio-cells = <2>;
                 reg = <0x20>;
         };
 
@@ -222,7 +224,7 @@
         };
 
         eeprom@53 {
-                compatible = "mcp,24c02";
+                compatible = "microchip,24c02";
                 reg = <0x53>;
                 pagesize = <8>;
         };
@@ -297,8 +299,8 @@
                 |            |-->0x004FFFFF-> Kernel end
                 |            |-->0x00500000-> File system start
                 |            |
-                |            |-->0x014FFFFF-> File system end
-                |            |-->0x01500000-> User data start
+                |            |-->0x01FFFFFF-> File system end
+                |            |-->0x02000000-> User data start
                 |            |
                 |            |-->0x03FFFFFF-> User data end
                 |            |-->0x04000000-> Data storage start
@@ -327,12 +329,12 @@
 
                 partition@4 {
                         label = "rootfs";
-                        reg = <0x00500000 0x01000000>; /* 16MB */
+                        reg = <0x00500000 0x01b00000>; /* 27MB */
                 };
 
                 partition@5 {
                         label = "user";
-                        reg = <0x01500000 0x02b00000>; /* 43MB */
+                        reg = <0x02000000 0x02000000>; /* 32MB */
                 };
 
                 partition@6 {
@@ -343,7 +345,7 @@
 };
 
 &mac {
-        dual_emac = <1>;
+        dual_emac;
         status = "okay";
 };
 
@@ -353,11 +355,13 @@
 
 &cpsw_emac0 {
         phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "mii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
         phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "mii";
         dual_emac_res_vlan = <2>;
 };
 
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce7d6fb..236c78a3c6ca 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-&scrm_clocks {
+&scm_clocks {
         sys_clkin_ck: sys_clkin_ck {
                 #clock-cells = <0>;
                 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd37057bca9..21fcc440fc1a 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
                 };
         };
 
-        am33xx_control_module: control_module@4a002000 {
-                compatible = "syscon";
-                reg = <0x44e10000 0x7fc>;
-        };
-
-        am33xx_pinmux: pinmux@44e10800 {
-                compatible = "pinctrl-single";
-                reg = <0x44e10800 0x0238>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-single,register-width = <32>;
-                pinctrl-single,function-mask = <0x7f>;
-        };
-
         /*
          * XXX: Use a flat representation of the AM33XX interconnect.
          * The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
-                prcm: prcm@44e00000 {
-                        compatible = "ti,am3-prcm";
-                        reg = <0x44e00000 0x4000>;
-
-                        prcm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
+                l4_wkup: l4_wkup@44c00000 {
+                        compatible = "ti,am3-l4-wkup", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x44c00000 0x280000>;
 
-                        prcm_clockdomains: clockdomains {
-                        };
-                };
+                        prcm: prcm@200000 {
+                                compatible = "ti,am3-prcm";
+                                reg = <0x200000 0x4000>;
 
-                scrm: scrm@44e10000 {
-                        compatible = "ti,am3-scrm";
-                        reg = <0x44e10000 0x2000>;
+                                prcm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                        scrm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                prcm_clockdomains: clockdomains {
+                                };
                         };
 
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@210000 {
+                                compatible = "ti,am3-scm", "simple-bus";
+                                reg = <0x210000 0x2000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x210000 0x2000>;
+
+                                am33xx_pinmux: pinmux@800 {
+                                        compatible = "pinctrl-single";
+                                        reg = <0x800 0x238>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0x7f>;
+                                };
+
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+
+                                scm_clockdomains: clockdomains {
+                                };
                         };
                 };
 
-                cm: syscon@44e10000 {
-                        compatible = "ti,am33xx-controlmodule", "syscon";
-                        reg = <0x44e10000 0x800>;
-                };
-
                 intc: interrupt-controller@48200000 {
                         compatible = "ti,am33xx-intc";
                         interrupt-controller;
@@ -350,7 +357,7 @@
                         reg = <0x481cc000 0x2000>;
                         clocks = <&dcan0_fck>;
                         clock-names = "fck";
-                        syscon-raminit = <&am33xx_control_module 0x644 0>;
+                        syscon-raminit = <&scm_conf 0x644 0>;
                         interrupts = <52>;
                         status = "disabled";
                 };
@@ -361,7 +368,7 @@
                         reg = <0x481d0000 0x2000>;
                         clocks = <&dcan1_fck>;
                         clock-names = "fck";
-                        syscon-raminit = <&am33xx_control_module 0x644 1>;
+                        syscon-raminit = <&scm_conf 0x644 1>;
                         interrupts = <55>;
                         status = "disabled";
                 };
@@ -720,7 +727,7 @@
                          */
                         interrupts = <40 41 42 43>;
                         ranges;
-                        syscon = <&cm>;
+                        syscon = <&scm_conf>;
                         status = "disabled";
 
                         davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724bded10..f164dce08755 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -31,7 +31,7 @@
                         status = "disabled";
                         reg = <0x5c000000 0x30000>;
                         interrupts = <67 68 69 70>;
-                        syscon = <&omap3_scm_general>;
+                        syscon = <&scm_conf>;
                         ti,davinci-ctrl-reg-offset = <0x10000>;
                         ti,davinci-ctrl-mod-reg-offset = <0>;
                         ti,davinci-ctrl-ram-offset = <0x20000>;
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index df489d310b50..518b8fde88b0 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -7,7 +7,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-&scrm_clocks {
+&scm_clocks {
         emac_ick: emac_ick {
                 #clock-cells = <0>;
                 compatible = "ti,am35xx-gate-clock";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc333e7c..48c9bea8df10 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -57,22 +57,6 @@
                 cache-level = <2>;
         };
 
-        am43xx_control_module: control_module@4a002000 {
-                compatible = "syscon";
-                reg = <0x44e10000 0x7f4>;
-        };
-
-        am43xx_pinmux: pinmux@44e10800 {
-                compatible = "ti,am437-padconf", "pinctrl-single";
-                reg = <0x44e10800 0x31c>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                #interrupt-cells = <1>;
-                interrupt-controller;
-                pinctrl-single,register-width = <32>;
-                pinctrl-single,function-mask = <0xffffffff>;
-        };
-
         ocp {
                 compatible = "ti,am4372-l3-noc", "simple-bus";
                 #address-cells = <1>;
@@ -84,29 +68,58 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
-                prcm: prcm@44df0000 {
-                        compatible = "ti,am4-prcm";
-                        reg = <0x44df0000 0x11000>;
-
-                        prcm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
+                l4_wkup: l4_wkup@44c00000 {
+                        compatible = "ti,am4-l4-wkup", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x44c00000 0x287000>;
 
-                        prcm_clockdomains: clockdomains {
-                        };
-                };
+                        prcm: prcm@1f0000 {
+                                compatible = "ti,am4-prcm";
+                                reg = <0x1f0000 0x11000>;
 
-                scrm: scrm@44e10000 {
-                        compatible = "ti,am4-scrm";
-                        reg = <0x44e10000 0x2000>;
+                                prcm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                        scrm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                prcm_clockdomains: clockdomains {
+                                };
                         };
 
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@210000 {
+                                compatible = "ti,am4-scm", "simple-bus";
+                                reg = <0x210000 0x4000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x210000 0x4000>;
+
+                                am43xx_pinmux: pinmux@800 {
+                                        compatible = "ti,am437-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x800 0x31c>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0xffffffff>;
+                                };
+
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+
+                                scm_clockdomains: clockdomains {
+                                };
                         };
                 };
 
@@ -787,7 +800,7 @@
                 };
 
                 ocp2scp0: ocp2scp@483a8000 {
-                        compatible = "ti,omap-ocp2scp";
+                        compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
                         #address-cells = <1>;
                         #size-cells = <1>;
                         ranges;
@@ -806,7 +819,7 @@
                 };
 
                 ocp2scp1: ocp2scp@483e8000 {
-                        compatible = "ti,omap-ocp2scp";
+                        compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
                         #address-cells = <1>;
                         #size-cells = <1>;
                         ranges;
@@ -884,7 +897,7 @@
                 };
 
                 hdq: hdq@48347000 {
-                        compatible = "ti,am43xx-hdq";
+                        compatible = "ti,am4372-hdq";
                         reg = <0x48347000 0x1000>;
                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&func_12m_clk>;
@@ -933,7 +946,7 @@
                         clocks = <&dcan0_fck>;
                         clock-names = "fck";
                         reg = <0x481cc000 0x2000>;
-                        syscon-raminit = <&am43xx_control_module 0x644 0>;
+                        syscon-raminit = <&scm_conf 0x644 0>;
                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -944,7 +957,7 @@
                         clocks = <&dcan1_fck>;
                         clock-names = "fck";
                         reg = <0x481d0000 0x2000>;
-                        syscon-raminit = <&am43xx_control_module 0x644 1>;
+                        syscon-raminit = <&scm_conf 0x644 1>;
                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index f9a17e2ca8cb..378344271746 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -133,17 +133,17 @@
                 >;
         };
 
-        i2c1_pins_default: i2c1_pins_default {
+        i2c2_pins_default: i2c2_pins_default {
                 pinctrl-single,pins = <
-                        0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
-                        0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
+                        0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
+                        0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
                 >;
         };
 
-        i2c1_pins_sleep: i2c1_pins_sleep {
+        i2c2_pins_sleep: i2c2_pins_sleep {
                 pinctrl-single,pins = <
-                        0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
-                        0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
+                        0x1e8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1ec (PIN_INPUT_PULLDOWN | MUX_MODE7)
                 >;
         };
 
@@ -254,7 +254,7 @@
         status = "okay";
         pinctrl-names = "default", "sleep";
         pinctrl-0 = <&i2c0_pins_default>;
-        pinctrl-1 = <&i2c0_pins_default>;
+        pinctrl-1 = <&i2c0_pins_sleep>;
         clock-frequency = <400000>;
 
         at24@50 {
@@ -262,17 +262,10 @@
                 pagesize = <64>;
                 reg = <0x50>;
         };
-};
-
-&i2c1 {
-        status = "okay";
-        pinctrl-names = "default", "sleep";
-        pinctrl-0 = <&i2c1_pins_default>;
-        pinctrl-1 = <&i2c1_pins_default>;
-        clock-frequency = <400000>;
 
         tps: tps62362@60 {
                 compatible = "ti,tps62362";
+                reg = <0x60>;
                 regulator-name = "VDD_MPU";
                 regulator-min-microvolt = <950000>;
                 regulator-max-microvolt = <1330000>;
@@ -284,6 +277,14 @@
         };
 };
 
+&i2c2 {
+        status = "okay";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&i2c2_pins_default>;
+        pinctrl-1 = <&i2c2_pins_sleep>;
+        clock-frequency = <100000>;
+};
+
 &epwmss0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 257c099c347e..72f01bb5d61c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -69,7 +69,48 @@
                 };
         };
 
-        am43xx_pinmux: pinmux@44e10800 {
+        matrix_keypad: matrix_keypad@0 {
+                compatible = "gpio-matrix-keypad";
+                debounce-delay-ms = <5>;
+                col-scan-delay-us = <2>;
+
+                row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
+                             &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
+                             &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
+                             &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
+
+                col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
+                             &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
+                             &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
+                             &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
+
+                linux,keymap = <0x00000201      /* P1 */
+                        0x01000204      /* P4 */
+                        0x02000207      /* P7 */
+                        0x0300020a      /* NUMERIC_STAR */
+                        0x00010202      /* P2 */
+                        0x01010205      /* P5 */
+                        0x02010208      /* P8 */
+                        0x03010200      /* P0 */
+                        0x00020203      /* P3 */
+                        0x01020206      /* P6 */
+                        0x02020209      /* P9 */
+                        0x0302020b      /* NUMERIC_POUND */
+                        0x00030067      /* UP */
+                        0x0103006a      /* RIGHT */
+                        0x0203006c      /* DOWN */
+                        0x03030069>;    /* LEFT */
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
+};
+
+&am43xx_pinmux {
                 cpsw_default: cpsw_default {
                         pinctrl-single,pins = <
                                 /* Slave 1 */
@@ -279,47 +320,6 @@
                                 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
                         >;
                 };
-        };
-
-        matrix_keypad: matrix_keypad@0 {
-                        compatible = "gpio-matrix-keypad";
-                        debounce-delay-ms = <5>;
-                        col-scan-delay-us = <2>;
-
-                        row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
-                                     &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
-                                     &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
-                                     &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
-
-                        col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
-                                     &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
-                                     &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
-                                     &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
-
-                        linux,keymap = <0x00000201      /* P1 */
-                                0x01000204      /* P4 */
-                                0x02000207      /* P7 */
-                                0x0300020a      /* NUMERIC_STAR */
-                                0x00010202      /* P2 */
-                                0x01010205      /* P5 */
-                                0x02010208      /* P8 */
-                                0x03010200      /* P0 */
-                                0x00020203      /* P3 */
-                                0x01020206      /* P6 */
-                                0x02020209      /* P9 */
-                                0x0302020b      /* NUMERIC_POUND */
-                                0x00030067      /* UP */
-                                0x0103006a      /* RIGHT */
-                                0x0203006c      /* DOWN */
-                                0x03030069>;    /* LEFT */
-                };
-
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
-                brightness-levels = <0 51 53 56 62 75 101 152 255>;
-                default-brightness-level = <8>;
-        };
 };
 
 &mmc1 {
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index c7dc9dab93a4..44869aa72642 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -7,7 +7,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-&scrm_clocks {
+&scm_clocks {
         sys_clkin_ck: sys_clkin_ck {
                 #clock-cells = <0>;
                 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 03750af3b49a..6a3621c23017 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -8,7 +8,6 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
-#include <dt-bindings/clk/ti-dra7-atl.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -87,6 +86,7 @@
                 gpios =  <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
                 gpio-fan,speed-map = <0     0>,
                                      <13000 1>;
+                #cooling-cells = <2>;
         };
 
         extcon_usb1: extcon_usb1 {
@@ -442,6 +442,7 @@
                 pinctrl-0 = <&tmp102_pins_default>;
                 interrupt-parent = <&gpio7>;
                 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+                #thermal-sensor-cells = <1>;
         };
 };
 
@@ -560,3 +561,50 @@
 &usb2 {
         dr_mode = "peripheral";
 };
+
+&cpu_trips {
+        cpu_alert1: cpu_alert1 {
+                temperature = <50000>; /* millicelsius */
+                hysteresis = <2000>; /* millicelsius */
+                type = "active";
+        };
+};
+
+&cpu_cooling_maps {
+        map1 {
+                trip = <&cpu_alert1>;
+                cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+        };
+};
+
+&thermal_zones {
+        board_thermal: board_thermal {
+                polling-delay-passive = <1250>; /* milliseconds */
+                polling-delay = <1500>; /* milliseconds */
+
+                                /* sensor       ID */
+                thermal-sensors = <&tmp102     0>;
+
+                board_trips: trips {
+                        board_alert0: board_alert {
+                                temperature = <40000>; /* millicelsius */
+                                hysteresis = <2000>; /* millicelsius */
+                                type = "active";
+                        };
+
+                        board_crit: board_crit {
+                                temperature = <105000>; /* millicelsius */
+                                hysteresis = <0>; /* millicelsius */
+                                type = "critical";
+                        };
+                };
+
+                board_cooling_maps: cooling-maps {
+                        map0 {
+                                trip = <&board_alert0>;
+                                cooling-device =
+                                  <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                        };
+                };
+       };
+};
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 857d0289ad4d..dee39c3f830f 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -29,10 +29,22 @@
 &dm816x_pinmux {
         mcspi1_pins: pinmux_mcspi1_pins {
                 pinctrl-single,pins = <
-                        DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0)     /* SPI_SCLK */
-                        DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0)    /* SPI_SCS0 */
-                        DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0)     /* SPI_D0 */
-                        DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0)     /* SPI_D1 */
+                        DM816X_IOPAD(0x0a94, MUX_MODE0)                 /* SPI_SCLK */
+                        DM816X_IOPAD(0x0a98, MUX_MODE0)                 /* SPI_SCS0 */
+                        DM816X_IOPAD(0x0aa8, MUX_MODE0)                 /* SPI_D0 */
+                        DM816X_IOPAD(0x0aac, MUX_MODE0)                 /* SPI_D1 */
+                >;
+        };
+
+        usb0_pins: pinmux_usb0_pins {
+                pinctrl-single,pins = <
+                        DM816X_IOPAD(0x0d04, MUX_MODE0)                 /* USB0_DRVVBUS */
+                >;
+        };
+
+        usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+                        DM816X_IOPAD(0x0d08, MUX_MODE0)                 /* USB1_DRVVBUS */
                 >;
         };
 };
@@ -127,3 +139,16 @@
 &mmc1 {
         vmmc-supply = <&vmmcsd_fixed>;
 };
+
+/* At least dm8168-evm rev c won't support multipoint, later may */
+&usb0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb0_pins>;
+        mentor,multipoint = <0>;
+};
+
+&usb1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+        mentor,multipoint = <0>;
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index d98d0f7de380..90c820715521 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -97,10 +97,31 @@
 
                         /* Device Configuration Registers */
                         scm_conf: syscon@600 {
-                                compatible = "syscon";
+                                compatible = "syscon", "simple-bus";
                                 reg = <0x600 0x110>;
                                 #address-cells = <1>;
                                 #size-cells = <1>;
+                                ranges = <0 0x600 0x110>;
+
+                                usb_phy0: usb-phy@20 {
+                                        compatible = "ti,dm8168-usb-phy";
+                                        reg = <0x20 0x8>;
+                                        reg-names = "phy";
+                                        clocks = <&main_fapll 6>;
+                                        clock-names = "refclk";
+                                        #phy-cells = <0>;
+                                        syscon = <&scm_conf>;
+                                };
+
+                                usb_phy1: usb-phy@28 {
+                                        compatible = "ti,dm8168-usb-phy";
+                                        reg = <0x28 0x8>;
+                                        reg-names = "phy";
+                                        clocks = <&main_fapll 6>;
+                                        clock-names = "refclk";
+                                        #phy-cells = <0>;
+                                        syscon = <&scm_conf>;
+                                };
                         };
 
                         scrm_clocks: clocks {
@@ -357,26 +378,91 @@
                                 reg-names = "mc", "control";
                                 interrupts = <18>;
                                 interrupt-names = "mc";
-                                dr_mode = "otg";
+                                dr_mode = "host";
+                                interface-type = <0>;
+                                phys = <&usb_phy0>;
+                                phy-names = "usb2-phy";
                                 mentor,multipoint = <1>;
                                 mentor,num-eps = <16>;
                                 mentor,ram-bits = <12>;
                                 mentor,power = <500>;
+
+                                dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+                                        &cppi41dma  2 0 &cppi41dma  3 0
+                                        &cppi41dma  4 0 &cppi41dma  5 0
+                                        &cppi41dma  6 0 &cppi41dma  7 0
+                                        &cppi41dma  8 0 &cppi41dma  9 0
+                                        &cppi41dma 10 0 &cppi41dma 11 0
+                                        &cppi41dma 12 0 &cppi41dma 13 0
+                                        &cppi41dma 14 0 &cppi41dma  0 1
+                                        &cppi41dma  1 1 &cppi41dma  2 1
+                                        &cppi41dma  3 1 &cppi41dma  4 1
+                                        &cppi41dma  5 1 &cppi41dma  6 1
+                                        &cppi41dma  7 1 &cppi41dma  8 1
+                                        &cppi41dma  9 1 &cppi41dma 10 1
+                                        &cppi41dma 11 1 &cppi41dma 12 1
+                                        &cppi41dma 13 1 &cppi41dma 14 1>;
+                                dma-names =
+                                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                        "rx14", "rx15",
+                                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                        "tx14", "tx15";
                         };
 
                         usb1: usb@47401800 {
                                 compatible = "ti,musb-am33xx";
-                                status = "disabled";
                                 reg = <0x47401c00 0x400
                                        0x47401800 0x200>;
                                 reg-names = "mc", "control";
                                 interrupts = <19>;
                                 interrupt-names = "mc";
-                                dr_mode = "otg";
+                                dr_mode = "host";
+                                interface-type = <0>;
+                                phys = <&usb_phy1>;
+                                phy-names = "usb2-phy";
                                 mentor,multipoint = <1>;
                                 mentor,num-eps = <16>;
                                 mentor,ram-bits = <12>;
                                 mentor,power = <500>;
+
+                                dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+                                        &cppi41dma 17 0 &cppi41dma 18 0
+                                        &cppi41dma 19 0 &cppi41dma 20 0
+                                        &cppi41dma 21 0 &cppi41dma 22 0
+                                        &cppi41dma 23 0 &cppi41dma 24 0
+                                        &cppi41dma 25 0 &cppi41dma 26 0
+                                        &cppi41dma 27 0 &cppi41dma 28 0
+                                        &cppi41dma 29 0 &cppi41dma 15 1
+                                        &cppi41dma 16 1 &cppi41dma 17 1
+                                        &cppi41dma 18 1 &cppi41dma 19 1
+                                        &cppi41dma 20 1 &cppi41dma 21 1
+                                        &cppi41dma 22 1 &cppi41dma 23 1
+                                        &cppi41dma 24 1 &cppi41dma 25 1
+                                        &cppi41dma 26 1 &cppi41dma 27 1
+                                        &cppi41dma 28 1 &cppi41dma 29 1>;
+                                dma-names =
+                                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                        "rx14", "rx15",
+                                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                        "tx14", "tx15";
+                        };
+
+                        cppi41dma: dma-controller@47402000 {
+                                compatible = "ti,am3359-cppi41";
+                                reg =  <0x47400000 0x1000
+                                        0x47402000 0x1000
+                                        0x47403000 0x1000
+                                        0x47404000 0x4000>;
+                                reg-names = "glue", "controller", "scheduler", "queuemgr";
+                                interrupts = <17>;
+                                interrupt-names = "glue";
+                                #dma-cells = <2>;
+                                #dma-channels = <30>;
+                                #dma-requests = <256>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fedafd43..a3c32e8ee90f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -94,17 +94,101 @@
                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
 
-                prm: prm@4ae06000 {
-                        compatible = "ti,dra7-prm";
-                        reg = <0x4ae06000 0x3000>;
-                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                l4_cfg: l4@4a000000 {
+                        compatible = "ti,dra7-l4-cfg", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4a000000 0x22c000>;
 
-                        prm_clocks: clocks {
+                        scm: scm@2000 {
+                                compatible = "ti,dra7-scm-core", "simple-bus";
+                                reg = <0x2000 0x2000>;
                                 #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x2000>;
+
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x1400>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0xe00 0x4>;
+                                                syscon = <&scm_conf>;
+                                                pbias_mmc_reg: pbias_mmc_omap5 {
+                                                        regulator-name = "pbias_mmc_omap5";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
+
+                                dra7_pmx_core: pinmux@1400 {
+                                        compatible = "ti,dra7-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x1400 0x0464>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0x3fffffff>;
+                                };
+                        };
+
+                        cm_core_aon: cm_core_aon@5000 {
+                                compatible = "ti,dra7-cm-core-aon";
+                                reg = <0x5000 0x2000>;
+
+                                cm_core_aon_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+
+                                cm_core_aon_clockdomains: clockdomains {
+                                };
+                        };
+
+                        cm_core: cm_core@8000 {
+                                compatible = "ti,dra7-cm-core";
+                                reg = <0x8000 0x3000>;
+
+                                cm_core_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+
+                                cm_core_clockdomains: clockdomains {
+                                };
                         };
+                };
 
-                        prm_clockdomains: clockdomains {
+                l4_wkup: l4@4ae00000 {
+                        compatible = "ti,dra7-l4-wkup", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4ae00000 0x3f000>;
+
+                        counter32k: counter@4000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x4000 0x40>;
+                                ti,hwmods = "counter_32k";
+                        };
+
+                        prm: prm@6000 {
+                                compatible = "ti,dra7-prm";
+                                reg = <0x6000 0x3000>;
+                                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+                                prm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+
+                                prm_clockdomains: clockdomains {
+                                };
                         };
                 };
 
@@ -177,36 +261,16 @@
                         };
                 };
 
-                cm_core_aon: cm_core_aon@4a005000 {
-                        compatible = "ti,dra7-cm-core-aon";
-                        reg = <0x4a005000 0x2000>;
-
-                        cm_core_aon_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-
-                        cm_core_aon_clockdomains: clockdomains {
-                        };
-                };
-
-                cm_core: cm_core@4a008000 {
-                        compatible = "ti,dra7-cm-core";
-                        reg = <0x4a008000 0x3000>;
-
-                        cm_core_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-
-                        cm_core_clockdomains: clockdomains {
-                        };
-                };
-
-                counter32k: counter@4ae04000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x4ae04000 0x40>;
-                        ti,hwmods = "counter_32k";
+                bandgap: bandgap@4a0021e0 {
+                        reg = <0x4a0021e0 0xc
+                                0x4a00232c 0xc
+                                0x4a002380 0x2c
+                                0x4a0023C0 0x3c
+                                0x4a002564 0x8
+                                0x4a002574 0x50>;
+                                compatible = "ti,dra752-bandgap";
+                                interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+                                #thermal-sensor-cells = <1>;
                 };
 
                 dra7_ctrl_core: ctrl_core@4a002000 {
@@ -219,28 +283,6 @@
                         reg = <0x4a002e00 0x7c>;
                 };
 
-                pbias_regulator: pbias_regulator {
-                        compatible = "ti,pbias-omap";
-                        reg = <0 0x4>;
-                        syscon = <&dra7_ctrl_general>;
-                        pbias_mmc_reg: pbias_mmc_omap5 {
-                                regulator-name = "pbias_mmc_omap5";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
-                        };
-                };
-
-                dra7_pmx_core: pinmux@4a003400 {
-                        compatible = "ti,dra7-padconf", "pinctrl-single";
-                        reg = <0x4a003400 0x0464>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <32>;
-                        pinctrl-single,function-mask = <0x3fffffff>;
-                };
-
                 sdma: dma-controller@4a056000 {
                         compatible = "ti,omap4430-sdma";
                         reg = <0x4a056000 0x1000>;
@@ -249,8 +291,8 @@
                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
-                        #dma-channels = <32>;
-                        #dma-requests = <127>;
+                        dma-channels = <32>;
+                        dma-requests = <127>;
                 };
 
                 gpio1: gpio@4ae10000 {
@@ -658,7 +700,6 @@
                         reg = <0x48820000 0x80>;
                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer5";
-                        ti,timer-dsp;
                 };
 
                 timer6: timer@48822000 {
@@ -666,8 +707,6 @@
                         reg = <0x48822000 0x80>;
                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer6";
-                        ti,timer-dsp;
-                        ti,timer-pwm;
                 };
 
                 timer7: timer@48824000 {
@@ -675,7 +714,6 @@
                         reg = <0x48824000 0x80>;
                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer7";
-                        ti,timer-dsp;
                 };
 
                 timer8: timer@48826000 {
@@ -683,8 +721,6 @@
                         reg = <0x48826000 0x80>;
                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer8";
-                        ti,timer-dsp;
-                        ti,timer-pwm;
                 };
 
                 timer9: timer@4803e000 {
@@ -706,7 +742,6 @@
                         reg = <0x48088000 0x80>;
                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer11";
-                        ti,timer-pwm;
                 };
 
                 timer13: timer@48828000 {
@@ -1090,8 +1125,8 @@
                                       <0x4A096800 0x40>; /* pll_ctrl */
                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
                                 ctrl-module = <&omap_control_sata>;
-                                clocks = <&sys_clkin1>;
-                                clock-names = "sysclk";
+                                clocks = <&sys_clkin1>, <&sata_ref_clk>;
+                                clock-names = "sysclk", "refclk";
                                 #phy-cells = <0>;
                         };
 
@@ -1410,7 +1445,7 @@
                         compatible = "ti,dra7-d_can";
                         ti,hwmods = "dcan1";
                         reg = <0x4ae3c000 0x2000>;
-                        syscon-raminit = <&dra7_ctrl_core 0x558 0>;
+                        syscon-raminit = <&scm_conf 0x558 0>;
                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&dcan1_sys_clk_mux>;
                         status = "disabled";
@@ -1420,12 +1455,23 @@
                         compatible = "ti,dra7-d_can";
                         ti,hwmods = "dcan2";
                         reg = <0x48480000 0x2000>;
-                        syscon-raminit = <&dra7_ctrl_core 0x558 1>;
+                        syscon-raminit = <&scm_conf 0x558 1>;
                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&sys_clkin1>;
                         status = "disabled";
                 };
         };
+
+        thermal_zones: thermal-zones {
+                #include "omap4-cpu-thermal.dtsi"
+                #include "omap5-gpu-thermal.dtsi"
+                #include "omap5-core-thermal.dtsi"
+        };
+
+};
+
+&cpu_thermal {
+        polling-delay = <500>; /* milliseconds */
 };
 
 /include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df1..6ac8e3601499 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -20,6 +20,11 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0>;
+
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <2>;
+                        #cooling-cells = <2>; /* min followed by max */
                 };
         };
 
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15..eef981f4bcd5 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -31,6 +31,11 @@
                         clock-names = "cpu";
 
                         clock-latency = <300000>; /* From omap-cpufreq driver */
+
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <2>;
+                        #cooling-cells = <2>; /* min followed by max */
                 };
                 cpu@1 {
                         device_type = "cpu";
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 4bdcbd61ce47..2a9994f73974 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1421,6 +1421,14 @@
                 ti,dividers = <1>, <8>;
         };
 
+        clkout2_clk: clkout2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkoutmux2_clk_mux>;
+                ti,bit-shift = <8>;
+                reg = <0x06b0>;
+        };
+
         l3init_960m_gfclk: l3init_960m_gfclk {
                 #clock-cells = <0>;
                 compatible = "ti,gate-clock";
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 9c21b1583762..dd45e6971bc3 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -75,6 +75,27 @@
                 mux-int-port = <1>;
                 mux-ext-port = <4>;
         };
+
+        wvga: display {
+                model = "CLAA057VC01CW";
+                bits-per-pixel = <16>;
+                fsl,pcr = <0xfa208b80>;
+                bus-width = <18>;
+                native-mode = <&wvga_timings>;
+                display-timings {
+                        wvga_timings: 640x480 {
+                                hactive = <640>;
+                                vactive = <480>;
+                                hback-porch = <45>;
+                                hfront-porch = <114>;
+                                hsync-len = <1>;
+                                vback-porch = <33>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock-frequency = <25200000>;
+                        };
+                };
+        };
 };
 
 &audmux {
@@ -190,6 +211,33 @@
                         >;
                 };
 
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX25_PAD_LD0__LD0               0xe0
+                                MX25_PAD_LD1__LD1               0xe0
+                                MX25_PAD_LD2__LD2               0xe0
+                                MX25_PAD_LD3__LD3               0xe0
+                                MX25_PAD_LD4__LD4               0xe0
+                                MX25_PAD_LD5__LD5               0xe0
+                                MX25_PAD_LD6__LD6               0xe0
+                                MX25_PAD_LD7__LD7               0xe0
+                                MX25_PAD_LD8__LD8               0xe0
+                                MX25_PAD_LD9__LD9               0xe0
+                                MX25_PAD_LD10__LD10             0xe0
+                                MX25_PAD_LD11__LD11             0xe0
+                                MX25_PAD_LD12__LD12             0xe0
+                                MX25_PAD_LD13__LD13             0xe0
+                                MX25_PAD_LD14__LD14             0xe0
+                                MX25_PAD_LD15__LD15             0xe0
+                                MX25_PAD_GPIO_E__LD16           0xe0
+                                MX25_PAD_GPIO_F__LD17           0xe0
+                                MX25_PAD_HSYNC__HSYNC           0xe0
+                                MX25_PAD_VSYNC__VSYNC           0xe0
+                                MX25_PAD_LSCLK__LSCLK           0xe0
+                                MX25_PAD_OE_ACD__OE_ACD         0xe0
+                                MX25_PAD_CONTRAST__CONTRAST     0xe0
+                        >;
+                };
 
                 pinctrl_uart1: uart1grp {
                         fsl,pins = <
@@ -202,6 +250,16 @@
         };
 };
 
+&lcdc {
+        display = <&wvga>;
+        fsl,lpccr = <0x00a903ff>;
+        fsl,lscr1 = <0x00120300>;
+        fsl,dmacr = <0x00020010>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        status = "okay";
+};
+
 &nfc {
         nand-on-flash-bbt;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 88eebb15da6a..7c4b9f2f9aad 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -17,48 +17,69 @@
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
 
+#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
+
 #define MX25_PAD_A10__A10                       0x008 0x000 0x000 0x00 0x000
 #define MX25_PAD_A10__GPIO_4_0                  0x008 0x000 0x000 0x05 0x000
 
 #define MX25_PAD_A13__A13                       0x00c 0x22C 0x000 0x00 0x000
 #define MX25_PAD_A13__GPIO_4_1                  0x00c 0x22C 0x000 0x05 0x000
+#define MX25_PAD_A13__LCDC_CLS                  0x00c 0x22C 0x000 0x07 0x000
 
 #define MX25_PAD_A14__A14                       0x010 0x230 0x000 0x10 0x000
 #define MX25_PAD_A14__GPIO_2_0                  0x010 0x230 0x000 0x15 0x000
+#define MX25_PAD_A14__SIM1_CLK1                 0x010 0x230 0x000 0x16 0x000
+#define MX25_PAD_A14__LCDC_SPL                  0x010 0x230 0x000 0x17 0x000
 
 #define MX25_PAD_A15__A15                       0x014 0x234 0x000 0x10 0x000
 #define MX25_PAD_A15__GPIO_2_1                  0x014 0x234 0x000 0x15 0x000
+#define MX25_PAD_A15__SIM1_RST1                 0x014 0x234 0x000 0x16 0x000
+#define MX25_PAD_A15__LCDC_PS                   0x014 0x234 0x000 0x17 0x000
 
 #define MX25_PAD_A16__A16                       0x018 0x000 0x000 0x10 0x000
 #define MX25_PAD_A16__GPIO_2_2                  0x018 0x000 0x000 0x15 0x000
+#define MX25_PAD_A16__SIM1_VEN1                 0x018 0x000 0x000 0x16 0x000
+#define MX25_PAD_A16__LCDC_REV                  0x018 0x000 0x000 0x17 0x000
 
 #define MX25_PAD_A17__A17                       0x01c 0x238 0x000 0x10 0x000
 #define MX25_PAD_A17__GPIO_2_3                  0x01c 0x238 0x000 0x15 0x000
+#define MX25_PAD_A17__SIM1_TX                   0x01c 0x238 0x554 0x16 0x000
+#define MX25_PAD_A17__FEC_TX_ERR                0x01c 0x238 0x000 0x17 0x000
 
 #define MX25_PAD_A18__A18                       0x020 0x23c 0x000 0x10 0x000
 #define MX25_PAD_A18__GPIO_2_4                  0x020 0x23c 0x000 0x15 0x000
+#define MX25_PAD_A18__SIM1_PD1                  0x020 0x23c 0x550 0x16 0x000
 #define MX25_PAD_A18__FEC_COL                   0x020 0x23c 0x504 0x17 0x000
 
 #define MX25_PAD_A19__A19                       0x024 0x240 0x000 0x10 0x000
-#define MX25_PAD_A19__FEC_RX_ER                 0x024 0x240 0x518 0x17 0x000
 #define MX25_PAD_A19__GPIO_2_5                  0x024 0x240 0x000 0x15 0x000
+#define MX25_PAD_A19__SIM1_RX1                  0x024 0x240 0x54c 0x16 0x000
+#define MX25_PAD_A19__FEC_RX_ERR                0x024 0x240 0x518 0x17 0x000
 
 #define MX25_PAD_A20__A20                       0x028 0x244 0x000 0x10 0x000
 #define MX25_PAD_A20__GPIO_2_6                  0x028 0x244 0x000 0x15 0x000
+#define MX25_PAD_A20__SIM2_CLK1                 0x028 0x244 0x000 0x16 0x000
 #define MX25_PAD_A20__FEC_RDATA2                0x028 0x244 0x50c 0x17 0x000
 
 #define MX25_PAD_A21__A21                       0x02c 0x248 0x000 0x10 0x000
 #define MX25_PAD_A21__GPIO_2_7                  0x02c 0x248 0x000 0x15 0x000
+#define MX25_PAD_A21__SIM2_RST1                 0x02c 0x248 0x000 0x16 0x000
 #define MX25_PAD_A21__FEC_RDATA3                0x02c 0x248 0x510 0x17 0x000
 
 #define MX25_PAD_A22__A22                       0x030 0x000 0x000 0x10 0x000
 #define MX25_PAD_A22__GPIO_2_8                  0x030 0x000 0x000 0x15 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
+#define MX25_PAD_A22__SIM2_VEN1                 0x030 0x000 0x000 0x16 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
 
 #define MX25_PAD_A23__A23                       0x034 0x24c 0x000 0x10 0x000
 #define MX25_PAD_A23__GPIO_2_9                  0x034 0x24c 0x000 0x15 0x000
+#define MX25_PAD_A23__SIM2_TX1                  0x034 0x24c 0x560 0x16 0x000
+#define MX25_PAD_A23__FEC_TDATA3                0x034 0x24c 0x000 0x17 0x000
 
 #define MX25_PAD_A24__A24                       0x038 0x250 0x000 0x10 0x000
 #define MX25_PAD_A24__GPIO_2_10                 0x038 0x250 0x000 0x15 0x000
+#define MX25_PAD_A24__SIM2_PD1                  0x038 0x250 0x55c 0x16 0x000
 #define MX25_PAD_A24__FEC_RX_CLK                0x038 0x250 0x514 0x17 0x000
 
 #define MX25_PAD_A25__A25                       0x03c 0x254 0x000 0x10 0x000
@@ -133,20 +154,25 @@
 #define MX25_PAD_D15__D15                       0x088 0x280 0x000 0x00 0x000
 #define MX25_PAD_D15__LD16                      0x088 0x280 0x000 0x01 0x000
 #define MX25_PAD_D15__GPIO_4_5                  0x088 0x280 0x000 0x05 0x000
+#define MX25_PAD_D15__SDHC1_DAT7                0x088 0x280 0x4d8 0x06 0x000
 
 #define MX25_PAD_D14__D14                       0x08c 0x284 0x000 0x00 0x000
 #define MX25_PAD_D14__LD17                      0x08c 0x284 0x000 0x01 0x000
 #define MX25_PAD_D14__GPIO_4_6                  0x08c 0x284 0x000 0x05 0x000
+#define MX25_PAD_D14__SDHC1_DAT6                0x08c 0x284 0x4d4 0x06 0x000
 
 #define MX25_PAD_D13__D13                       0x090 0x288 0x000 0x00 0x000
 #define MX25_PAD_D13__LD18                      0x090 0x288 0x000 0x01 0x000
 #define MX25_PAD_D13__GPIO_4_7                  0x090 0x288 0x000 0x05 0x000
+#define MX25_PAD_D13__SDHC1_DAT5                0x090 0x288 0x4d0 0x06 0x000
 
 #define MX25_PAD_D12__D12                       0x094 0x28c 0x000 0x00 0x000
 #define MX25_PAD_D12__GPIO_4_8                  0x094 0x28c 0x000 0x05 0x000
+#define MX25_PAD_D12__SDHC1_DAT4                0x094 0x28c 0x4cc 0x06 0x000
 
 #define MX25_PAD_D11__D11                       0x098 0x290 0x000 0x00 0x000
 #define MX25_PAD_D11__GPIO_4_9                  0x098 0x290 0x000 0x05 0x000
+#define MX25_PAD_D11__USBOTG_PWR                0x098 0x290 0x000 0x06 0x000
 
 #define MX25_PAD_D10__D10                       0x09c 0x294 0x000 0x00 0x000
 #define MX25_PAD_D10__GPIO_4_10                 0x09c 0x294 0x000 0x05 0x000
@@ -212,26 +238,33 @@
 
 #define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x10 0x000
 #define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x15 0x000
+#define MX25_PAD_LD8__SDHC2_CMD                 0x0e8 0x2e0 0x4e0 0x06 0x000
 
 #define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x10 0x000
 #define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x15 0x001
+#define MX25_PAD_LD9__SDHC2_CLK                 0x0ec 0x2e4 0x4dc 0x06 0x000
 
 #define MX25_PAD_LD10__LD10                     0x0f0 0x2e8 0x000 0x10 0x000
-#define MX25_PAD_LD10__FEC_RX_ER                0x0f0 0x2e8 0x518 0x15 0x001
+#define MX25_PAD_LD10__FEC_RX_ERR               0x0f0 0x2e8 0x518 0x15 0x001
 
 #define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x10 0x000
 #define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x15 0x001
+#define MX25_PAD_LD11__SDHC2_DAT1               0x0f4 0x2ec 0x4e8 0x06 0x000
 
 #define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x10 0x000
+#define MX25_PAD_LD12__CSPI2_MOSI               0x0f8 0x2f0 0x4a0 0x02 0x000
 #define MX25_PAD_LD12__FEC_RDATA3               0x0f8 0x2f0 0x510 0x15 0x001
 
 #define MX25_PAD_LD13__LD13                     0x0fc 0x2f4 0x000 0x10 0x000
+#define MX25_PAD_LD13__CSPI2_MISO               0x0fc 0x2f4 0x49c 0x02 0x000
 #define MX25_PAD_LD13__FEC_TDATA2               0x0fc 0x2f4 0x000 0x15 0x000
 
 #define MX25_PAD_LD14__LD14                     0x100 0x2f8 0x000 0x10 0x000
+#define MX25_PAD_LD14__CSPI2_SCLK               0x100 0x2f8 0x494 0x02 0x000
 #define MX25_PAD_LD14__FEC_TDATA3               0x100 0x2f8 0x000 0x15 0x000
 
 #define MX25_PAD_LD15__LD15                     0x104 0x2fc 0x000 0x10 0x000
+#define MX25_PAD_LD15__CSPI2_RDY                0x104 0x2fc 0x498 0x02 0x000
 #define MX25_PAD_LD15__FEC_RX_CLK               0x104 0x2fc 0x514 0x15 0x001
 
 #define MX25_PAD_HSYNC__HSYNC                   0x108 0x300 0x000 0x10 0x000
@@ -244,6 +277,7 @@
 #define MX25_PAD_LSCLK__GPIO_1_24               0x110 0x308 0x000 0x15 0x000
 
 #define MX25_PAD_OE_ACD__OE_ACD                 0x114 0x30c 0x000 0x10 0x000
+#define MX25_PAD_OE_ACD__CSPI2_SS0              0x114 0x30c 0x4a4 0x02 0x000
 #define MX25_PAD_OE_ACD__GPIO_1_25              0x114 0x30c 0x000 0x15 0x000
 
 #define MX25_PAD_CONTRAST__CONTRAST             0x118 0x310 0x000 0x10 0x000
@@ -257,26 +291,31 @@
 
 #define MX25_PAD_CSI_D2__CSI_D2                 0x120 0x318 0x000 0x10 0x000
 #define MX25_PAD_CSI_D2__UART5_RXD_MUX          0x120 0x318 0x578 0x11 0x001
+#define MX25_PAD_CSI_D2__SIM1_CLK0              0x120 0x318 0x000 0x04 0x000
 #define MX25_PAD_CSI_D2__GPIO_1_27              0x120 0x318 0x000 0x15 0x000
 #define MX25_PAD_CSI_D2__CSPI3_MOSI             0x120 0x318 0x000 0x17 0x000
 
 #define MX25_PAD_CSI_D3__CSI_D3                 0x124 0x31c 0x000 0x10 0x000
 #define MX25_PAD_CSI_D3__UART5_TXD_MUX          0x124 0x31c 0x000 0x11 0x000
+#define MX25_PAD_CSI_D3__SIM1_RST0              0x124 0x31c 0x000 0x04 0x000
 #define MX25_PAD_CSI_D3__GPIO_1_28              0x124 0x31c 0x000 0x15 0x000
 #define MX25_PAD_CSI_D3__CSPI3_MISO             0x124 0x31c 0x4b4 0x17 0x001
 
 #define MX25_PAD_CSI_D4__CSI_D4                 0x128 0x320 0x000 0x10 0x000
 #define MX25_PAD_CSI_D4__UART5_RTS              0x128 0x320 0x574 0x11 0x001
+#define MX25_PAD_CSI_D4__SIM1_VEN0              0x128 0x320 0x000 0x04 0x000
 #define MX25_PAD_CSI_D4__GPIO_1_29              0x128 0x320 0x000 0x15 0x000
 #define MX25_PAD_CSI_D4__CSPI3_SCLK             0x128 0x320 0x000 0x17 0x000
 
 #define MX25_PAD_CSI_D5__CSI_D5                 0x12c 0x324 0x000 0x10 0x000
-#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x001
+#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x000
+#define MX25_PAD_CSI_D5__SIM1_TX0               0x12c 0x324 0x000 0x04 0x000
 #define MX25_PAD_CSI_D5__GPIO_1_30              0x12c 0x324 0x000 0x15 0x000
 #define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x17 0x000
 
 #define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x10 0x000
 #define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x12 0x001
+#define MX25_PAD_CSI_D6__SIM1_PD0               0x130 0x328 0x000 0x04 0x000
 #define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x10 0x000
@@ -284,32 +323,32 @@
 #define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x10 0x000
-#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x001
+#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x000
 #define MX25_PAD_CSI_D8__GPIO_1_7               0x138 0x330 0x000 0x15 0x000
 #define MX25_PAD_CSI_D8__CSPI3_SS2              0x138 0x330 0x4c4 0x17 0x000
 
 #define MX25_PAD_CSI_D9__CSI_D9                 0x13c 0x334 0x000 0x10 0x000
-#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x001
+#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x000
 #define MX25_PAD_CSI_D9__GPIO_4_21              0x13c 0x334 0x000 0x15 0x000
 #define MX25_PAD_CSI_D9__CSPI3_SS3              0x13c 0x334 0x4c8 0x17 0x000
 
 #define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x10 0x000
-#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x001
+#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x000
 #define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x12 0x001
 #define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x10 0x000
-#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x001
+#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x000
 #define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x12 0x001
 #define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x10 0x000
-#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x001
+#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x000
 #define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x12 0x001
 #define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x15 0x000
 
 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x10 0x000
-#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x001
+#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x000
 #define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x12 0x001
 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x15 0x000
 
@@ -369,8 +408,8 @@
 #define MX25_PAD_UART2_RTS__CC1                 0x188 0x380 0x000 0x13 0x000
 #define MX25_PAD_UART2_RTS__GPIO_4_28           0x188 0x380 0x000 0x15 0x000
 
-#define MX25_PAD_UART2_CTS__FEC_RX_ER           0x18c 0x384 0x518 0x12 0x002
 #define MX25_PAD_UART2_CTS__UART2_CTS           0x18c 0x384 0x000 0x10 0x000
+#define MX25_PAD_UART2_CTS__FEC_RX_ERR          0x18c 0x384 0x518 0x12 0x002
 #define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x15 0x000
 
 #define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
@@ -392,11 +431,11 @@
 #define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x15 0x000
 
 #define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x15 0x002
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x12 0x002
 #define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x15 0x000
 
 #define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x10 0x002
+#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x12 0x002
 #define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x15 0x000
 
 #define MX25_PAD_KPP_ROW0__KPP_ROW0             0x1a8 0x3a0 0x000 0x10 0x000
@@ -410,7 +449,7 @@
 #define MX25_PAD_KPP_ROW2__GPIO_2_31            0x1b0 0x3a8 0x000 0x15 0x000
 
 #define MX25_PAD_KPP_ROW3__KPP_ROW3             0x1b4 0x3ac 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW3__CSI_LD1              0x1b4 0x3ac 0x48c 0x13 0x002
+#define MX25_PAD_KPP_ROW3__CSI_D1               0x1b4 0x3ac 0x48c 0x13 0x002
 #define MX25_PAD_KPP_ROW3__GPIO_3_0             0x1b4 0x3ac 0x000 0x15 0x000
 
 #define MX25_PAD_KPP_COL0__KPP_COL0             0x1b8 0x3b0 0x000 0x10 0x000
@@ -455,9 +494,18 @@
 #define MX25_PAD_FEC_RDATA0__GPIO_3_10          0x1dc 0x3d4 0x000 0x15 0x000
 
 #define MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x1e0 0x3d8 0x000 0x10 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_TX but that's wrong.
+ */
+#define MX25_PAD_FEC_RDATA1__CAN2_TX            0x1e0 0x3d8 0x000 0x14 0x000
 #define MX25_PAD_FEC_RDATA1__GPIO_3_11          0x1e0 0x3d8 0x000 0x15 0x000
 
 #define MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x1e4 0x3dc 0x000 0x10 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_RX but that's wrong.
+ */
 #define MX25_PAD_FEC_RX_DV__CAN2_RX             0x1e4 0x3dc 0x484 0x14 0x000
 #define MX25_PAD_FEC_RX_DV__GPIO_3_12           0x1e4 0x3dc 0x000 0x15 0x000
 
@@ -471,30 +519,34 @@
 #define MX25_PAD_DE_B__DE_B                     0x1f0 0x3ec 0x000 0x10 0x000
 #define MX25_PAD_DE_B__GPIO_2_20                0x1f0 0x3ec 0x000 0x15 0x000
 
-#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
-
 #define MX25_PAD_GPIO_A__GPIO_A                 0x1f4 0x3f0 0x000 0x10 0x000
 #define MX25_PAD_GPIO_A__CAN1_TX                0x1f4 0x3f0 0x000 0x16 0x000
 #define MX25_PAD_GPIO_A__USBOTG_PWR             0x1f4 0x3f0 0x000 0x12 0x000
 
 #define MX25_PAD_GPIO_B__GPIO_B                 0x1f8 0x3f4 0x000 0x10 0x000
-#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
 #define MX25_PAD_GPIO_B__USBOTG_OC              0x1f8 0x3f4 0x57c 0x12 0x001
+#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
 
 #define MX25_PAD_GPIO_C__GPIO_C                 0x1fc 0x3f8 0x000 0x10 0x000
+#define MX25_PAD_GPIO_C__PWM4_PWMO              0x1fc 0x3f8 0x000 0x11 0x000
+#define MX25_PAD_GPIO_C__I2C2_SCL               0x1fc 0x3f8 0x51c 0x12 0x001
+#define MX25_PAD_GPIO_C__KPP_COL4               0x1fc 0x3f8 0x52c 0x13 0x001
 #define MX25_PAD_GPIO_C__CAN2_TX                0x1fc 0x3f8 0x000 0x16 0x000
 
 #define MX25_PAD_GPIO_D__GPIO_D                 0x200 0x3fc 0x000 0x10 0x000
+#define MX25_PAD_GPIO_D__I2C2_SDA               0x200 0x3fc 0x520 0x12 0x001
 #define MX25_PAD_GPIO_D__CAN2_RX                0x200 0x3fc 0x484 0x16 0x001
 
 #define MX25_PAD_GPIO_E__GPIO_E                 0x204 0x400 0x000 0x10 0x000
 #define MX25_PAD_GPIO_E__I2C3_CLK               0x204 0x400 0x524 0x11 0x002
 #define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x12 0x000
 #define MX25_PAD_GPIO_E__AUD7_TXD               0x204 0x400 0x000 0x14 0x000
+#define MX25_PAD_GPIO_E__UART4_RXD              0x204 0x400 0x570 0x16 0x002
 
 #define MX25_PAD_GPIO_F__GPIO_F                 0x208 0x404 0x000 0x10 0x000
 #define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x12 0x000
 #define MX25_PAD_GPIO_F__AUD7_TXC               0x208 0x404 0x000 0x14 0x000
+#define MX25_PAD_GPIO_F__UART4_TXD              0x208 0x404 0x000 0x16 0x000
 
 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK         0x20c 0x000 0x000 0x10 0x000
 #define MX25_PAD_EXT_ARMCLK__GPIO_3_15          0x20c 0x000 0x000 0x15 0x000
@@ -505,6 +557,7 @@
 #define MX25_PAD_VSTBY_REQ__VSTBY_REQ           0x214 0x408 0x000 0x10 0x000
 #define MX25_PAD_VSTBY_REQ__AUD7_TXFS           0x214 0x408 0x000 0x14 0x000
 #define MX25_PAD_VSTBY_REQ__GPIO_3_17           0x214 0x408 0x000 0x15 0x000
+
 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK           0x218 0x40c 0x000 0x10 0x000
 #define MX25_PAD_VSTBY_ACK__GPIO_3_18           0x218 0x40c 0x000 0x15 0x000
 
@@ -517,6 +570,7 @@
 
 #define MX25_PAD_BOOT_MODE0__BOOT_MODE0         0x224 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE0__GPIO_4_30          0x224 0x000 0x000 0x05 0x000
+
 #define MX25_PAD_BOOT_MODE1__BOOT_MODE1         0x228 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE1__GPIO_4_31          0x228 0x000 0x000 0x05 0x000
 
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 4b063b68db44..6951b66d1ab7 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -488,6 +488,7 @@
                                 interrupts = <54>;
                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
                                 fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -497,6 +498,7 @@
                                 interrupts = <55>;
                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
                                 fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 7198fe3798c6..070e59cbdd8b 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -78,7 +78,7 @@
                         phy-mode = "rmii";
                         pinctrl-names = "default";
                         pinctrl-0 = <&mac0_pins_a>;
-                        phy-reset-gpios = <&gpio4 13 0>;
+                        phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 1f38a052ad4b..7ac4f1af16ac 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -110,6 +110,13 @@
                                         };
                                 };
                         };
+
+                        can0: can@80032000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can0_pins_a>;
+                                xceiver-supply = <&reg_can0_vcc>;
+                                status = "okay";
+                        };
                 };
 
                 apbx@80040000 {
@@ -130,6 +137,13 @@
                                 status = "okay";
                         };
 
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
                         usbphy0: usbphy@8007c000 {
                                 status = "okay";
                         };
@@ -143,7 +157,8 @@
         ahb@80080000 {
                 usb0: usb@80080000 {
                         pinctrl-names = "default";
-                        pinctrl-0 = <&usb0_otg_apf28dev>;
+                        pinctrl-0 = <&usb0_otg_apf28dev
+                                        &usb0_id_pins_b>;
                         vbus-supply = <&reg_usb0_vbus>;
                         status = "okay";
                 };
@@ -156,7 +171,7 @@
                         phy-mode = "rmii";
                         pinctrl-names = "default";
                         pinctrl-0 = <&mac1_pins_a>;
-                        phy-reset-gpios = <&gpio0 23 0>;
+                        phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
                         status = "okay";
                 };
         };
@@ -175,6 +190,14 @@
                         gpio = <&gpio1 23 1>;
                         enable-active-high;
                 };
+
+                reg_can0_vcc: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "can0_vcc";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
         };
 
         leds {
@@ -200,8 +223,9 @@
 
                 user-button {
                         label = "User button";
-                        gpios = <&gpio0 17 0>;
+                        gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
                         linux,code = <0x100>;
+                        gpio-key,wakeup;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 47f68ac868d4..25e25f82fbae 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -829,6 +829,19 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
+                                spi3_pins_b: spi3@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SSP3_SCK__SSP3_SCK
+                                                MX28_PAD_SSP3_MOSI__SSP3_CMD
+                                                MX28_PAD_SSP3_MISO__SSP3_D0
+                                                MX28_PAD_SSP3_SS0__SSP3_D3
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
+
                                 usb0_pins_a: usb0@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -1197,6 +1210,7 @@
                         interrupts = <92>;
                         clocks = <&clks 61>;
                         fsl,usbphy = <&usbphy1>;
+                        dr_mode = "host";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 6932928f3b45..b6478e97d6a7 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -318,6 +318,7 @@
                                 clocks = <&clks 73>;
                                 fsl,usbmisc = <&usbmisc 1>;
                                 fsl,usbphy = <&usbphy1>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 620b0f030591..e2457138311f 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -197,6 +197,7 @@
                                 reg = <0x53f80200 0x0200>;
                                 interrupts = <14>;
                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -205,6 +206,7 @@
                                 reg = <0x53f80400 0x0200>;
                                 interrupts = <16>;
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -213,6 +215,7 @@
                                 reg = <0x53f80600 0x0200>;
                                 interrupts = <17>;
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index c0116cffc513..f46fe9bf0bcb 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -265,6 +265,7 @@
                                 interrupts = <14>;
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                 fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -274,6 +275,7 @@
                                 interrupts = <16>;
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                 fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -283,6 +285,7 @@
                                 interrupts = <17>;
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                 fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index ff4fa7ecacd8..c3e3ca9362fb 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -309,6 +309,7 @@
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                 fsl,usbmisc = <&usbmisc 1>;
                                 fsl,usbphy = <&usbphy1>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -318,6 +319,7 @@
                                 interrupts = <16>;
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                 fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -327,6 +329,7 @@
                                 interrupts = <17>;
                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                 fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 9cd06e5e59f0..d4c4a22db488 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -83,3 +83,7 @@
 &ipu1_di0_disp0 {
         remote-endpoint = <&display0_in>;
 };
+
+&pwm1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index b413e24288dc..15203f0e9725 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -72,3 +72,7 @@
 &ipu1_di0_disp0 {
         remote-endpoint = <&display0_in>;
 };
+
+&pwm3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts
index 58aa8f2b0f26..e0b7fe8e18f8 100644
--- a/arch/arm/boot/dts/imx6dl-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts
@@ -1,5 +1,43 @@
 /*
  * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 44a0e6736bb1..7369d2d7da3e 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,6 +1,44 @@
 /*
  * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
  * Based on dt work by Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
index 9efd8b0c8011..670bd8c4c847 100644
--- a/arch/arm/boot/dts/imx6q-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
@@ -1,5 +1,43 @@
 /*
  * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
index c2bf8476ce45..0f6044553a24 100644
--- a/arch/arm/boot/dts/imx6q-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -1,6 +1,44 @@
 /*
  * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
  * Based on dt work by Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 93ec79bb6b35..399103b8e2c9 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -294,19 +294,21 @@
 };
 
 &mipi_dsi {
-        port@2 {
-                reg = <2>;
+        ports {
+                port@2 {
+                        reg = <2>;
 
-                mipi_mux_2: endpoint {
-                        remote-endpoint = <&ipu2_di0_mipi>;
+                        mipi_mux_2: endpoint {
+                                remote-endpoint = <&ipu2_di0_mipi>;
+                        };
                 };
-        };
 
-        port@3 {
-                reg = <3>;
+                port@3 {
+                        reg = <3>;
 
-                mipi_mux_3: endpoint {
-                        remote-endpoint = <&ipu2_di1_mipi>;
+                        mipi_mux_3: endpoint {
+                                remote-endpoint = <&ipu2_di1_mipi>;
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 6a524ca011e7..d033bb182060 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -1,8 +1,48 @@
 /*
  * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include "imx6qdl-microsom.dtsi"
 #include "imx6qdl-microsom-ar8035.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         ir_recv: ir-receiver {
@@ -66,6 +106,18 @@
                 spdif-controller = <&spdif>;
                 spdif-out;
         };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pinctrl_gpio_key>;
+                pinctrl-names = "default";
+
+                button_0 {
+                        label = "Button 0";
+                        gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+                        linux,code = <BTN_0>;
+                };
+        };
 };
 
 &hdmi {
@@ -170,9 +222,19 @@
                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
                         >;
                 };
+
+                pinctrl_gpio_key: gpio-key {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_DA8__GPIO3_IO08  0x17059
+                        >;
+                };
         };
 };
 
+&pwm1 {
+        status = "okay";
+};
+
 &spdif {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_cubox_i_spdif>;
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 62841e85a91e..151a3db2aea9 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -1,5 +1,43 @@
 /*
  * Copyright (C) 2013,2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include "imx6qdl-microsom.dtsi"
 #include "imx6qdl-microsom-ar8035.dtsi"
@@ -50,6 +88,19 @@
                 };
         };
 
+        sound-sgtl5000 {
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                compatible = "fsl,imx-audio-sgtl5000";
+                model = "On-board Codec";
+                mux-ext-port = <5>;
+                mux-int-port = <1>;
+                ssi-controller = <&ssi1>;
+        };
+
         sound-spdif {
                 compatible = "fsl,imx-audio-spdif";
                 model = "On-board SPDIF";
@@ -59,6 +110,10 @@
         };
 };
 
+&audmux {
+        status = "okay";
+};
+
 &can1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
@@ -75,16 +130,24 @@
 &i2c1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
-
-        /*
-         * Not fitted on Carrier-1 board... yet
         status = "okay";
 
+        /* Pro baseboard model */
         rtc: pcf8523@68 {
                 compatible = "nxp,pcf8523";
                 reg = <0x68>;
         };
-         */
+
+        /* Pro baseboard model */
+        sgtl5000: sgtl5000@0a {
+                clocks = <&clks IMX6QDL_CLK_CKO>;
+                compatible = "fsl,sgtl5000";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p3v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
 };
 
 &i2c2 {
@@ -129,6 +192,20 @@
                         >;
                 };
 
+                pinctrl_hummingboard_pwm1: pwm1grp {
+                        fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
+                };
+
+                pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+                                MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+                                MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
+                                MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+                                MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
+                        >;
+                };
+
                 pinctrl_hummingboard_spdif: hummingboard-spdif {
                         fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                 };
@@ -168,12 +245,28 @@
         };
 };
 
+&pwm1 {
+         pinctrl-names = "default";
+         pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
+         status = "okay";
+};
+
+&pwm2 {
+         pinctrl-names = "default";
+         status = "okay";
+};
+
 &spdif {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hummingboard_spdif>;
         status = "okay";
 };
 
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
 &usbh1 {
         disable-over-current;
         vbus-supply = <&reg_usbh1_vbus>;
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index db9f45b2c573..4a1820309cdb 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -3,6 +3,44 @@
  *
  * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
  * MicroSOM.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 &fec {
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 79eac6849d4c..349f82be816e 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -1,5 +1,43 @@
 /*
  * Copyright (C) 2013,2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 &iomuxc {
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd69385d..46b2fed7c319 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -182,6 +182,34 @@
         };
 };
 
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+
+        max7310_a: gpio@30 {
+                compatible = "maxim,max7310";
+                reg = <0x30>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        max7310_b: gpio@32 {
+                compatible = "maxim,max7310";
+                reg = <0x32>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        max7310_c: gpio@34 {
+                compatible = "maxim,max7310";
+                reg = <0x34>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+
 &iomuxc {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +293,13 @@
                         >;
                 };
 
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
+                                MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+                        >;
+                };
+
                 pinctrl_pwm3: pwm1grp {
                         fsl,pins = <
                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d6c69ec44314..f74a8ded515f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
                 interrupt-controller;
                 reg = <0x00a01000 0x1000>,
                       <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
         };
 
         clocks {
@@ -82,7 +83,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                 ranges;
 
                 dma_apbh: dma-apbh@00110000 {
@@ -122,6 +123,7 @@
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0x00a00600 0x20>;
                         interrupts = <1 13 0xf01>;
+                        interrupt-parent = <&intc>;
                         clocks = <&clks IMX6QDL_CLK_TWD>;
                 };
 
@@ -357,6 +359,7 @@
                                 clocks = <&clks IMX6QDL_CLK_IPG>,
                                          <&clks IMX6QDL_CLK_PWM1>;
                                 clock-names = "ipg", "per";
+                                status = "disabled";
                         };
 
                         pwm2: pwm@02084000 {
@@ -367,6 +370,7 @@
                                 clocks = <&clks IMX6QDL_CLK_IPG>,
                                          <&clks IMX6QDL_CLK_PWM2>;
                                 clock-names = "ipg", "per";
+                                status = "disabled";
                         };
 
                         pwm3: pwm@02088000 {
@@ -377,6 +381,7 @@
                                 clocks = <&clks IMX6QDL_CLK_IPG>,
                                          <&clks IMX6QDL_CLK_PWM3>;
                                 clock-names = "ipg", "per";
+                                status = "disabled";
                         };
 
                         pwm4: pwm@0208c000 {
@@ -387,6 +392,7 @@
                                 clocks = <&clks IMX6QDL_CLK_IPG>,
                                          <&clks IMX6QDL_CLK_PWM4>;
                                 clock-names = "ipg", "per";
+                                status = "disabled";
                         };
 
                         can1: flexcan@02090000 {
@@ -598,7 +604,7 @@
                                         regulator-name = "vddpu";
                                         regulator-min-microvolt = <725000>;
                                         regulator-max-microvolt = <1450000>;
-                                        regulator-always-on;
+                                        regulator-enable-ramp-delay = <150>;
                                         anatop-reg-offset = <0x140>;
                                         anatop-vol-bit-shift = <9>;
                                         anatop-vol-bit-width = <5>;
@@ -658,7 +664,7 @@
                                 #size-cells = <1>;
                                 ranges = <0 0x020cc000 0x4000>;
 
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                         reg = <0x34 0x58>;
                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -693,8 +699,19 @@
                         gpc: gpc@020dc000 {
                                 compatible = "fsl,imx6q-gpc";
                                 reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
+                                pu-supply = <&reg_pu>;
+                                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+                                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                                         <&clks IMX6QDL_CLK_VPU_AXI>;
+                                #power-domain-cells = <1>;
                         };
 
                         gpr: iomuxc-gpr@020e0000 {
@@ -845,6 +862,7 @@
                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                 fsl,usbphy = <&usbphy2>;
                                 fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -854,6 +872,7 @@
                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                 fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -863,6 +882,7 @@
                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                 fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
@@ -1022,19 +1042,24 @@
                                 reg = <0x021e0000 0x4000>;
                                 status = "disabled";
 
-                                port@0 {
-                                        reg = <0>;
+                                ports {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        port@0 {
+                                                reg = <0>;
 
-                                        mipi_mux_0: endpoint {
-                                                remote-endpoint = <&ipu1_di0_mipi>;
+                                                mipi_mux_0: endpoint {
+                                                        remote-endpoint = <&ipu1_di0_mipi>;
+                                                };
                                         };
-                                };
 
-                                port@1 {
-                                        reg = <1>;
+                                        port@1 {
+                                                reg = <1>;
 
-                                        mipi_mux_1: endpoint {
-                                                remote-endpoint = <&ipu1_di1_mipi>;
+                                                mipi_mux_1: endpoint {
+                                                        remote-endpoint = <&ipu1_di1_mipi>;
+                                                };
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
new file mode 100644
index 000000000000..64f7decf1fdc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2014, 2015 O.S. Systems Software LTDA.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+
+/ {
+        model = "WaRP Board";
+        compatible = "warp,imx6sl-warp", "fsl,imx6sl";
+
+        memory {
+                reg = <0x80000000 0x20000000>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                reg_usb_otg1_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb_otg1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 0 0>;
+                        enable-active-high;
+                };
+
+                reg_usb_otg2_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_otg2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 2 0>;
+                        enable-active-high;
+                };
+
+                reg_1p8v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "1P8V";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+        };
+
+        usdhc3_pwrseq: usdhc3_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>,       /* WL_REG_ON */
+                              <&gpio3 25 GPIO_ACTIVE_LOW>,      /* BT_REG_ON */
+                              <&gpio4 4 GPIO_ACTIVE_LOW>,       /* BT_WAKE */
+                              <&gpio4 6 GPIO_ACTIVE_LOW>;       /* BT_RST_N */
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+
+&usbotg1 {
+        vbus-supply = <&reg_usb_otg1_vbus>;
+        dr_mode = "host";
+        disable-over-current;
+        status = "okay";
+};
+
+&usbotg2 {
+        vbus-supply = <&reg_usb_otg2_vbus>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        bus-width = <4>;
+        non-removable;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        mmc-pwrseq = <&usdhc3_pwrseq>;
+        status = "okay";
+};
+
+&iomuxc {
+        imx6sl-warp {
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x41b0b1
+                                MX6SL_PAD_UART1_TXD__UART1_TX_DATA      0x41b0b1
+                        >;
+                };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_EPDC_D12__UART2_RX_DATA       0x41b0b1
+                                MX6SL_PAD_EPDC_D13__UART2_TX_DATA       0x41b0b1
+                                MX6SL_PAD_EPDC_D14__UART2_RTS_B         0x4130B1
+                                MX6SL_PAD_EPDC_D15__UART2_CTS_B         0x4130B1
+                        >;
+                };
+
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_AUD_RXC__UART3_RX_DATA        0x41b0b1
+                                MX6SL_PAD_AUD_RXC__UART3_TX_DATA        0x41b0b1
+                        >;
+                };
+
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x417059
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x410059
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x417059
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x417059
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x417059
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x417059
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x417059
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x417059
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x417059
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x417059
+                        >;
+                };
+
+                pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170b9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100b9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170b9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170b9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170b9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170b9
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170b9
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170b9
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170b9
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170b9
+                        >;
+                };
+
+                pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170f9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100f9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170f9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170f9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170f9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170f9
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170f9
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170f9
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170f9
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170f9
+                        >;
+                };
+
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x417059
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x410059
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x417059
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x417059
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x417059
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x417059
+                        >;
+                };
+
+                pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170b9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100b9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170b9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170b9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170b9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170b9
+                        >;
+                };
+
+                pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170f9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100f9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170f9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170f9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170f9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170f9
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e054cee..a78e715e3982 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
                 interrupt-controller;
                 reg = <0x00a01000 0x1000>,
                       <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
         };
 
         clocks {
@@ -95,7 +96,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                 ranges;
 
                 ocram: sram@00900000 {
@@ -568,7 +569,7 @@
                                 #size-cells = <1>;
                                 ranges = <0 0x020cc000 0x4000>;
 
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                         reg = <0x34 0x58>;
                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -603,7 +604,14 @@
                         gpc: gpc@020dc000 {
                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
                                 reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
+                                pu-supply = <&reg_pu>;
+                                clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
+                                         <&clks IMX6SL_CLK_GPU2D_PODF>;
+                                #power-domain-cells = <1>;
                         };
 
                         gpr: iomuxc-gpr@020e0000 {
@@ -699,6 +707,7 @@
                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
                                 fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
new file mode 100644
index 000000000000..c76b87cba275
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-sdb.dtsi"
+
+/ {
+        model = "Freescale i.MX6 SoloX SDB RevA Board";
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                                regulator-always-on;
+                        };
+
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&qspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_qspi2>;
+        status = "okay";
+
+        flash0: s25fl128s@0 {
+                reg = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl128s";
+                spi-max-frequency = <66000000>;
+        };
+
+        flash1: s25fl128s@1 {
+                reg = <1>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl128s";
+                spi-max-frequency = <66000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 32f07d6b4042..0bfc4e7865b2 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -1,197 +1,40 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "imx6sx.dtsi"
+#include "imx6sx-sdb.dtsi"
 
 / {
-        model = "Freescale i.MX6 SoloX SDB Board";
-        compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
-
-        chosen {
-                stdout-path = &uart1;
-        };
-
-        memory {
-                reg = <0x80000000 0x40000000>;
-        };
-
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&pwm3 0 5000000>;
-                brightness-levels = <0 4 8 16 32 64 128 255>;
-                default-brightness-level = <6>;
-        };
-
-        gpio-keys {
-                compatible = "gpio-keys";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_gpio_keys>;
-
-                volume-up {
-                        label = "Volume Up";
-                        gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_VOLUMEUP>;
-                };
-
-                volume-down {
-                        label = "Volume Down";
-                        gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_VOLUMEDOWN>;
-                };
-        };
-
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                vcc_sd3: regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_vcc_sd3>;
-                        regulator-name = "VCC_SD3";
-                        regulator-min-microvolt = <3000000>;
-                        regulator-max-microvolt = <3000000>;
-                        gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                reg_usb_otg1_vbus: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_usb_otg1>;
-                        regulator-name = "usb_otg1_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                reg_usb_otg2_vbus: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_usb_otg2>;
-                        regulator-name = "usb_otg2_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                reg_psu_5v: regulator@3 {
-                        compatible = "regulator-fixed";
-                        reg = <3>;
-                        regulator-name = "PSU-5V0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                };
-
-                reg_lcd_3v3: regulator@4 {
-                        compatible = "regulator-fixed";
-                        reg = <4>;
-                        regulator-name = "lcd-3v3";
-                        gpio = <&gpio3 27 0>;
-                        enable-active-high;
-                };
-
-                reg_peri_3v3: regulator@5 {
-                        compatible = "regulator-fixed";
-                        reg = <5>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_peri_3v3>;
-                        regulator-name = "peri_3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        regulator-always-on;
-                };
-
-                reg_enet_3v3: regulator@6 {
-                        compatible = "regulator-fixed";
-                        reg = <6>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_enet_3v3>;
-                        regulator-name = "enet_3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
-                };
-        };
-
-        sound {
-                compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
-                model = "wm8962-audio";
-                ssi-controller = <&ssi2>;
-                audio-codec = <&codec>;
-                audio-routing =
-                        "Headphone Jack", "HPOUTL",
-                        "Headphone Jack", "HPOUTR",
-                        "Ext Spk", "SPKOUTL",
-                        "Ext Spk", "SPKOUTR",
-                        "AMIC", "MICBIAS",
-                        "IN3R", "AMIC";
-                mux-int-port = <2>;
-                mux-ext-port = <6>;
-        };
-};
-
-&audmux {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux>;
-        status = "okay";
+        model = "Freescale i.MX6 SoloX SDB RevB Board";
 };
 
-&fec1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet1>;
-        phy-supply = <&reg_enet_3v3>;
-        phy-mode = "rgmii";
-        phy-handle = <&ethphy1>;
-        status = "okay";
-
-        mdio {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                ethphy1: ethernet-phy@1 {
-                        reg = <1>;
-                };
-
-                ethphy2: ethernet-phy@2 {
-                        reg = <2>;
-                };
-        };
+&cpu0 {
+        operating-points = <
+                /* kHz    uV */
+                996000  1250000
+                792000  1175000
+                396000  1175000
+                >;
+        fsl,soc-operating-points = <
+                /* ARM kHz      SOC uV */
+                996000  1250000
+                792000  1175000
+                396000  1175000
+        >;
 };
 
-&fec2 {
+&i2c1 {
+        clock-frequency = <100000>;
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet2>;
-        phy-mode = "rgmii";
-        phy-handle = <&ethphy2>;
+        pinctrl-0 = <&pinctrl_i2c1>;
         status = "okay";
-};
-
-&i2c1 {
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1>;
-        status = "okay";
 
         pmic: pfuze100@08 {
-                compatible = "fsl,pfuze100";
+                compatible = "fsl,pfuze200";
                 reg = <0x08>;
 
                 regulators {
@@ -203,14 +46,6 @@
                                 regulator-ramp-delay = <6250>;
                         };
 
-                        sw1c_reg: sw1c {
-                                regulator-min-microvolt = <300000>;
-                                regulator-max-microvolt = <1875000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                                regulator-ramp-delay = <6250>;
-                        };
-
                         sw2_reg: sw2 {
                                 regulator-min-microvolt = <800000>;
                                 regulator-max-microvolt = <3300000>;
@@ -232,11 +67,6 @@
                                 regulator-always-on;
                         };
 
-                        sw4_reg: sw4 {
-                                regulator-min-microvolt = <800000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
                         swbst_reg: swbst {
                                 regulator-min-microvolt = <5000000>;
                                 regulator-max-microvolt = <5150000>;
@@ -292,401 +122,24 @@
         };
 };
 
-&i2c4 {
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c4>;
-        status = "okay";
-
-        codec: wm8962@1a {
-                compatible = "wlf,wm8962";
-                reg = <0x1a>;
-                clocks = <&clks IMX6SX_CLK_AUDIO>;
-                DCVDD-supply = <&vgen4_reg>;
-                DBVDD-supply = <&vgen4_reg>;
-                AVDD-supply = <&vgen4_reg>;
-                CPVDD-supply = <&vgen4_reg>;
-                MICVDD-supply = <&vgen3_reg>;
-                PLLVDD-supply = <&vgen4_reg>;
-                SPKVDD1-supply = <&reg_psu_5v>;
-                SPKVDD2-supply = <&reg_psu_5v>;
-        };
-};
-
-&lcdif1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_lcd>;
-        lcd-supply = <&reg_lcd_3v3>;
-        display = <&display0>;
-        status = "okay";
-
-        display0: display0 {
-                bits-per-pixel = <16>;
-                bus-width = <24>;
-
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: timing0 {
-                                clock-frequency = <33500000>;
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <89>;
-                                hfront-porch = <164>;
-                                vback-porch = <23>;
-                                vfront-porch = <10>;
-                                hsync-len = <10>;
-                                vsync-len = <10>;
-                                hsync-active = <0>;
-                                vsync-active = <0>;
-                                de-active = <1>;
-                                pixelclk-active = <0>;
-                        };
-                };
-        };
-};
-
-&pwm3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm3>;
-        status = "okay";
-};
-
-&snvs_poweroff {
-        status = "okay";
-};
-
 &qspi2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_qspi2>;
         status = "okay";
 
-        flash0: s25fl128s@0 {
-                reg = <0>;
+        flash0: n25q256a@0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
-                compatible = "spansion,s25fl128s";
-                spi-max-frequency = <66000000>;
+                compatible = "micron,n25q256a";
+                spi-max-frequency = <29000000>;
+                reg = <0>;
         };
 
-        flash1: s25fl128s@1 {
-                reg = <1>;
+        flash1: n25q256a@1 {
                 #address-cells = <1>;
                 #size-cells = <1>;
-                compatible = "spansion,s25fl128s";
-                spi-max-frequency = <66000000>;
-        };
-};
-
-&ssi2 {
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart5 { /* for bluetooth */
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        fsl,uart-has-rtscts;
-        status = "okay";
-};
-
-&usbotg1 {
-        vbus-supply = <&reg_usb_otg1_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usb_otg1_id>;
-        status = "okay";
-};
-
-&usbotg2 {
-        vbus-supply = <&reg_usb_otg2_vbus>;
-        dr_mode = "host";
-        status = "okay";
-};
-
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2>;
-        non-removable;
-        no-1-8-v;
-        keep-power-in-suspend;
-        enable-sdio-wakeup;
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc3>;
-        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-        bus-width = <8>;
-        cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-        keep-power-in-suspend;
-        enable-sdio-wakeup;
-        vmmc-supply = <&vcc_sd3>;
-        status = "okay";
-};
-
-&usdhc4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc4>;
-        cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
-        status = "okay";
-};
-
-&iomuxc {
-        imx6x-sdb {
-                pinctrl_audmux: audmuxgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
-                                MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
-                                MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
-                                MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
-                                MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
-                        >;
-                };
-
-                pinctrl_enet1: enet1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
-                                MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
-                                MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
-                                MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
-                                MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
-                                MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
-                                MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
-                                MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
-                                MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
-                                MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
-                                MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
-                                MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
-                                MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
-                                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
-                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
-                        >;
-                };
-
-                pinctrl_enet_3v3: enet3v3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
-                        >;
-                };
-
-                pinctrl_enet2: enet2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
-                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
-                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
-                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
-                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
-                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
-                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
-                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
-                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
-                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
-                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
-                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
-                        >;
-                };
-
-                pinctrl_gpio_keys: gpio_keysgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
-                                MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
-                        >;
-                };
-
-                pinctrl_i2c1: i2c1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
-                                MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
-                        >;
-                };
-
-                pinctrl_i2c4: i2c4grp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
-                                MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
-                        >;
-                };
-
-                pinctrl_lcd: lcdgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
-                                MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
-                                MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
-                                MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
-                                MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
-                                MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
-                        >;
-                };
-
-                pinctrl_peri_3v3: peri3v3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
-                        >;
-                };
-
-                pinctrl_pwm3: pwm3grp-1 {
-                        fsl,pins = <
-                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
-                        >;
-                };
-
-                pinctrl_qspi2: qspi2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
-                                MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
-                                MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
-                                MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
-                                MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
-                                MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
-                                MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
-                                MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
-                                MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
-                                MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
-                                MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
-                                MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
-                        >;
-                };
-
-                pinctrl_vcc_sd3: vccsd3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
-                        >;
-                };
-
-                pinctrl_uart1: uart1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
-                                MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
-                        >;
-                };
-
-                pinctrl_uart5: uart5grp {
-                        fsl,pins = <
-                                MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
-                                MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
-                                MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
-                                MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
-                        >;
-                };
-
-                pinctrl_usb_otg1: usbotg1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
-                        >;
-                };
-
-                pinctrl_usb_otg1_id: usbotg1idgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
-                        >;
-                };
-
-                pinctrl_usb_otg2: usbot2ggrp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
-                        >;
-                };
-
-                pinctrl_usdhc2: usdhc2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
-                                MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
-                                MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
-                                MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
-                                MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
-                                MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
-                        >;
-                };
-
-                pinctrl_usdhc3: usdhc3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
-                                MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
-                                MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
-                        >;
-                };
-
-                pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
-                        >;
-                };
-
-                pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
-                        >;
-                };
-
-                pinctrl_usdhc4: usdhc4grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
-                                MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
-                                MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
-                                MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
-                                MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
-                                MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
-                                MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
-                                MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
-                        >;
-                };
+                compatible = "micron,n25q256a";
+                spi-max-frequency = <29000000>;
+                reg = <1>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
new file mode 100644
index 000000000000..cef04cef3a80
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -0,0 +1,562 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sx.dtsi"
+
+/ {
+        model = "Freescale i.MX6 SoloX SDB Board";
+        compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm3 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEUP>;
+                };
+
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEDOWN>;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vcc_sd3: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_vcc_sd3>;
+                        regulator-name = "VCC_SD3";
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3000000>;
+                        gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+
+                reg_usb_otg1_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb_otg1>;
+                        regulator-name = "usb_otg1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+
+                reg_usb_otg2_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb_otg2>;
+                        regulator-name = "usb_otg2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+
+                reg_psu_5v: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "PSU-5V0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+
+                reg_lcd_3v3: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "lcd-3v3";
+                        gpio = <&gpio3 27 0>;
+                        enable-active-high;
+                };
+
+                reg_peri_3v3: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_peri_3v3>;
+                        regulator-name = "peri_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-always-on;
+                };
+
+                reg_enet_3v3: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_enet_3v3>;
+                        regulator-name = "enet_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        sound {
+                compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "AMIC", "MICBIAS",
+                        "IN3R", "AMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <6>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        phy-supply = <&reg_enet_3v3>;
+        phy-mode = "rgmii";
+        phy-handle = <&ethphy1>;
+        status = "okay";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy1: ethernet-phy@1 {
+                        reg = <1>;
+                };
+
+                ethphy2: ethernet-phy@2 {
+                        reg = <2>;
+                };
+        };
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rgmii";
+        phy-handle = <&ethphy2>;
+        status = "okay";
+};
+
+&i2c4 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c4>;
+        status = "okay";
+
+        codec: wm8962@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks IMX6SX_CLK_AUDIO>;
+                DCVDD-supply = <&vgen4_reg>;
+                DBVDD-supply = <&vgen4_reg>;
+                AVDD-supply = <&vgen4_reg>;
+                CPVDD-supply = <&vgen4_reg>;
+                MICVDD-supply = <&vgen3_reg>;
+                PLLVDD-supply = <&vgen4_reg>;
+                SPKVDD1-supply = <&reg_psu_5v>;
+                SPKVDD2-supply = <&reg_psu_5v>;
+        };
+};
+
+&lcdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        lcd-supply = <&reg_lcd_3v3>;
+        display = <&display0>;
+        status = "okay";
+
+        display0: display0 {
+                bits-per-pixel = <16>;
+                bus-width = <24>;
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <33500000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <89>;
+                                hfront-porch = <164>;
+                                vback-porch = <23>;
+                                vfront-porch = <10>;
+                                hsync-len = <10>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&ssi2 {
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart5 { /* for bluetooth */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&usbotg1 {
+        vbus-supply = <&reg_usb_otg1_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usb_otg1_id>;
+        status = "okay";
+};
+
+&usbotg2 {
+        vbus-supply = <&reg_usb_otg2_vbus>;
+        dr_mode = "host";
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        non-removable;
+        no-1-8-v;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        bus-width = <8>;
+        cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        vmmc-supply = <&vcc_sd3>;
+        status = "okay";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&iomuxc {
+        imx6x-sdb {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
+                                MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
+                                MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
+                                MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
+                                MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
+                        >;
+                };
+
+                pinctrl_enet1: enet1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
+                                MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
+                                MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
+                                MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
+                        >;
+                };
+
+                pinctrl_enet_3v3: enet3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
+                        >;
+                };
+
+                pinctrl_enet2: enet2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
+                        >;
+                };
+
+                pinctrl_gpio_keys: gpio_keysgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
+                                MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
+                        >;
+                };
+
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
+                                MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
+                        >;
+                };
+
+                pinctrl_i2c4: i2c4grp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
+                                MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
+                        >;
+                };
+
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+                                MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
+                                MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+                                MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
+                        >;
+                };
+
+                pinctrl_peri_3v3: peri3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
+                        >;
+                };
+
+                pinctrl_pwm3: pwm3grp-1 {
+                        fsl,pins = <
+                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+                        >;
+                };
+
+                pinctrl_qspi2: qspi2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
+                                MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
+                                MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
+                                MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
+                                MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
+                                MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
+                                MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
+                                MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
+                                MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
+                                MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
+                                MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
+                                MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
+                        >;
+                };
+
+                pinctrl_vcc_sd3: vccsd3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
+                        >;
+                };
+
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
+                                MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
+                        >;
+                };
+
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
+                                MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
+                                MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
+                                MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
+                        >;
+                };
+
+                pinctrl_usb_otg1: usbotg1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
+                        >;
+                };
+
+                pinctrl_usb_otg1_id: usbotg1idgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
+                        >;
+                };
+
+                pinctrl_usb_otg2: usbot2ggrp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
+                        >;
+                };
+
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
+                                MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
+                                MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
+                                MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
+                                MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
+                                MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
+                        >;
+                };
+
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
+                                MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
+                                MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
+                        >;
+                };
+
+                pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
+                        >;
+                };
+
+                pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
+                        >;
+                };
+
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
+                                MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
+                                MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
+                                MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
+                                MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
+                                MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
+                                MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
+                                MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee1e7ae..708175d59b9c 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
                 interrupt-controller;
                 reg = <0x00a01000 0x1000>,
                       <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
         };
 
         clocks {
@@ -131,7 +132,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                 ranges;
 
                 pmu {
@@ -666,7 +667,7 @@
                                 #size-cells = <1>;
                                 ranges = <0 0x020cc000 0x4000>;
 
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                         reg = <0x34 0x58>;
                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -700,7 +701,10 @@
                         gpc: gpc@020dc000 {
                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
                                 reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
                         };
 
                         iomuxc: iomuxc@020e0000 {
@@ -763,6 +767,7 @@
                                 fsl,usbmisc = <&usbmisc 2>;
                                 phy_type = "hsic";
                                 fsl,anatop = <&anatop>;
+                                dr_mode = "host";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 59d1c297bb30..578fa2a54dce 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -87,8 +87,8 @@
                                      <14>,
                                      <15>;
                         #dma-cells = <1>;
-                        #dma-channels = <32>;
-                        #dma-requests = <64>;
+                        dma-channels = <32>;
+                        dma-requests = <64>;
                 };
 
                 i2c1: i2c@48070000 {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e2b2e93d7b61..5b9a376cc31e 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,47 +14,65 @@
         compatible = "ti,omap2420", "ti,omap2";
 
         ocp {
-                prcm: prcm@48008000 {
-                        compatible = "ti,omap2-prcm";
-                        reg = <0x48008000 0x1000>;
+                l4: l4@48000000 {
+                        compatible = "ti,omap2-l4", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x48000000 0x100000>;
 
-                        prcm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
+                        prcm: prcm@8000 {
+                                compatible = "ti,omap2-prcm";
+                                reg = <0x8000 0x1000>;
 
-                        prcm_clockdomains: clockdomains {
-                        };
-                };
+                                prcm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                scrm: scrm@48000000 {
-                        compatible = "ti,omap2-scrm";
-                        reg = <0x48000000 0x1000>;
+                                prcm_clockdomains: clockdomains {
+                                };
+                        };
 
-                        scrm_clocks: clocks {
+                        scm: scm@0 {
+                                compatible = "ti,omap2-scm", "simple-bus";
+                                reg = <0x0 0x1000>;
                                 #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x0 0x1000>;
+
+                                omap2420_pmx: pinmux@30 {
+                                        compatible = "ti,omap2420-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x0113>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <8>;
+                                        pinctrl-single,function-mask = <0x3f>;
+                                };
+
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x100>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+
+                                scm_clockdomains: clockdomains {
+                                };
                         };
 
-                        scrm_clockdomains: clockdomains {
+                        counter32k: counter@4000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x4000 0x20>;
+                                ti,hwmods = "counter_32k";
                         };
                 };
 
-                counter32k: counter@48004000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x48004000 0x20>;
-                        ti,hwmods = "counter_32k";
-                };
-
-                omap2420_pmx: pinmux@48000030 {
-                        compatible = "ti,omap2420-padconf", "pinctrl-single";
-                        reg = <0x48000030 0x0113>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        pinctrl-single,register-width = <8>;
-                        pinctrl-single,function-mask = <0x3f>;
-                };
-
                 gpio1: gpio@48018000 {
                         compatible = "ti,omap2-gpio";
                         reg = <0x48018000 0x200>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
index 805f75df1cf2..93fed68839b9 100644
--- a/arch/arm/boot/dts/omap2430-clocks.dtsi
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -8,12 +8,12 @@
  * published by the Free Software Foundation.
  */
 
-&scrm_clocks {
+&scm_clocks {
         mcbsp3_mux_fck: mcbsp3_mux_fck {
                 #clock-cells = <0>;
                 compatible = "ti,composite-mux-clock";
                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
-                reg = <0x02e8>;
+                reg = <0x78>;
         };
 
         mcbsp3_fck: mcbsp3_fck {
@@ -27,7 +27,7 @@
                 compatible = "ti,composite-mux-clock";
                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
                 ti,bit-shift = <2>;
-                reg = <0x02e8>;
+                reg = <0x78>;
         };
 
         mcbsp4_fck: mcbsp4_fck {
@@ -41,7 +41,7 @@
                 compatible = "ti,composite-mux-clock";
                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
                 ti,bit-shift = <4>;
-                reg = <0x02e8>;
+                reg = <0x78>;
         };
 
         mcbsp5_fck: mcbsp5_fck {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 0dc8de2782b1..11a7963be003 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,60 +14,73 @@
         compatible = "ti,omap2430", "ti,omap2";
 
         ocp {
-                prcm: prcm@49006000 {
-                        compatible = "ti,omap2-prcm";
-                        reg = <0x49006000 0x1000>;
+                l4_wkup: l4_wkup@49000000 {
+                        compatible = "ti,omap2-l4-wkup", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x49000000 0x31000>;
 
-                        prcm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
+                        prcm: prcm@6000 {
+                                compatible = "ti,omap2-prcm";
+                                reg = <0x6000 0x1000>;
 
-                        prcm_clockdomains: clockdomains {
-                        };
-                };
-
-                scrm: scrm@49002000 {
-                        compatible = "ti,omap2-scrm";
-                        reg = <0x49002000 0x1000>;
+                                prcm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                        scrm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                prcm_clockdomains: clockdomains {
+                                };
                         };
 
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@2000 {
+                                compatible = "ti,omap2-scm", "simple-bus";
+                                reg = <0x2000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x1000>;
+
+                                omap2430_pmx: pinmux@30 {
+                                        compatible = "ti,omap2430-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x0154>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <8>;
+                                        pinctrl-single,function-mask = <0x3f>;
+                                };
+
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x240>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x230 0x4>;
+                                                syscon = <&scm_conf>;
+                                                pbias_mmc_reg: pbias_mmc_omap2430 {
+                                                        regulator-name = "pbias_mmc_omap2430";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
+
+                                scm_clockdomains: clockdomains {
+                                };
                         };
-                };
-
-                counter32k: counter@49020000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x49020000 0x20>;
-                        ti,hwmods = "counter_32k";
-                };
-
-                omap2430_pmx: pinmux@49002030 {
-                        compatible = "ti,omap2430-padconf", "pinctrl-single";
-                        reg = <0x49002030 0x0154>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        pinctrl-single,register-width = <8>;
-                        pinctrl-single,function-mask = <0x3f>;
-                };
-
-                omap2_scm_general: tisyscon@49002270 {
-                        compatible = "syscon";
-                        reg = <0x49002270 0x240>;
-                };
 
-                pbias_regulator: pbias_regulator {
-                        compatible = "ti,pbias-omap";
-                        reg = <0x230 0x4>;
-                        syscon = <&omap2_scm_general>;
-                        pbias_mmc_reg: pbias_mmc_omap2430 {
-                                regulator-name = "pbias_mmc_omap2430";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
+                        counter32k: counter@20000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x20000 0x20>;
+                                ti,hwmods = "counter_32k";
                         };
                 };
 
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
index a1365ca926eb..63965b876973 100644
--- a/arch/arm/boot/dts/omap24xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -7,13 +7,13 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-&scrm_clocks {
+&scm_clocks {
         mcbsp1_mux_fck: mcbsp1_mux_fck {
                 #clock-cells = <0>;
                 compatible = "ti,composite-mux-clock";
                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
                 ti,bit-shift = <2>;
-                reg = <0x0274>;
+                reg = <0x4>;
         };
 
         mcbsp1_fck: mcbsp1_fck {
@@ -27,7 +27,7 @@
                 compatible = "ti,composite-mux-clock";
                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
                 ti,bit-shift = <6>;
-                reg = <0x0274>;
+                reg = <0x4>;
         };
 
         mcbsp2_fck: mcbsp2_fck {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 25f7b0a22114..da1464bfbc60 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -60,7 +60,6 @@
                 ti,model = "omap3beagle";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         gpio_keys {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index c792391ef090..28f99a14c0a1 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -71,7 +71,6 @@
                 ti,model = "omap3beagle";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         gpio_keys {
@@ -379,3 +378,55 @@
                 };
         };
 };
+
+&gpmc {
+        status = "ok";
+        ranges = <0 0 0x30000000 0x1000000>;    /* CS0 space, 16MB */
+
+        /* Chip select 0 */
+        nand@0,0 {
+                reg = <0 0 4>;          /* NAND I/O window, 4 bytes */
+                interrupts = <20>;
+                ti,nand-ecc-opt = "ham1";
+                nand-bus-width = <16>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                gpmc,device-width = <2>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <36>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <24>;
+                gpmc,adv-wr-off-ns = <36>;
+                gpmc,oe-on-ns = <6>;
+                gpmc,oe-off-ns = <48>;
+                gpmc,we-on-ns = <6>;
+                gpmc,we-off-ns = <30>;
+                gpmc,rd-cycle-ns = <72>;
+                gpmc,wr-cycle-ns = <72>;
+                gpmc,access-ns = <54>;
+                gpmc,wr-access-ns = <30>;
+
+                partition@0 {
+                        label = "X-Loader";
+                        reg = <0 0x80000>;
+                };
+                partition@80000 {
+                        label = "U-Boot";
+                        reg = <0x80000 0x1e0000>;
+                };
+                partition@1c0000 {
+                        label = "U-Boot Env";
+                        reg = <0x260000 0x20000>;
+                };
+                partition@280000 {
+                        label = "Kernel";
+                        reg = <0x280000 0x400000>;
+                };
+                partition@780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0xf980000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index d9e92b654f85..046cd7733c4f 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -16,7 +16,6 @@
                 ti,model = "cm-t35";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 };
 
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 169037e5ff53..134d3f27a8ec 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -48,7 +48,6 @@
                 ti,model = "devkit8000";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
                 ti,audio-routing =
                         "Ext Spk", "PREDRIVEL",
                         "Ext Spk", "PREDRIVER",
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fb3a69604ed5..b9f68817bd6e 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -46,7 +46,6 @@
                 ti,model = "gta04";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         spi_lcd {
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 8a63ad2286aa..d5e5cd449b16 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -22,7 +22,6 @@
                 compatible = "ti,omap-twl4030";
                 ti,model = "igep2";
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         vdd33: regulator-vdd33 {
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index e81fb651d5d0..e63133304a34 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -38,7 +38,6 @@
                 ti,model = "lilly-a83x";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         reg_vcc3: vcc3 {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index 9938b5dc1909..f2e213931e09 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -16,3 +16,40 @@
         model = "Nokia N9";
         compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
 };
+
+&i2c2 {
+        smia_1: camera@10 {
+                compatible = "nokia,smia";
+                reg = <0x10>;
+                /* No reset gpio */
+                vana-supply = <&vaux3>;
+                clocks = <&isp 0>;
+                clock-frequency = <9600000>;
+                nokia,nvm-size = <(16 * 64)>;
+                port {
+                        smia_1_1: endpoint {
+                                link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&csi2a_ep>;
+                        };
+                };
+        };
+};
+
+&isp {
+        vdd-csiphy1-supply = <&vaux2>;
+        vdd-csiphy2-supply = <&vaux2>;
+        ports {
+                port@2 {
+                        reg = <2>;
+                        csi2a_ep: endpoint {
+                                remote-endpoint = <&smia_1_1>;
+                                clock-lanes = <2>;
+                                data-lanes = <1 3>;
+                                crc = <1>;
+                                lane-polarities = <1 1 1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 60403273f83e..bbea3076e1d4 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -9,13 +9,34 @@
 
 /dts-v1/;
 
-#include "omap34xx-hs.dtsi"
+#include "omap34xx.dtsi"
 #include <dt-bindings/input/input.h>
 
+/*
+ * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
+ * for omap AES HW crypto support. When linux kernel try to access memory of AES
+ * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
+ * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
+ * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
+ * There is "unofficial" version of bootloader which enables AES in L3 firewall
+ * but it is not widely used and to prevent kernel crash rather AES is disabled.
+ * There is also no runtime detection code if AES is disabled in L3 firewall...
+ */
+&aes {
+        status = "disabled";
+};
+
 / {
         model = "Nokia N900";
         compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
 
+        aliases {
+                i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+        };
+
         cpus {
                 cpu@0 {
                         cpu0-supply = <&vcc>;
@@ -704,7 +725,7 @@
                 compatible = "smsc,lan91c94";
                 interrupt-parent = <&gpio2>;
                 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;  /* gpio54 */
-                reg = <1 0x300 0xf>;            /* 16 byte IO range at offset 0x300 */
+                reg = <1 0 0xf>;                /* 16 byte IO range */
                 bank-width = <2>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&ethernet_pins>;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index c41db94ee9c2..800b379d368d 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 
-#include "omap36xx-hs.dtsi"
+#include "omap36xx.dtsi"
 
 / {
         cpus {
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index 261c5589bfa3..0885b34d5d7d 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -16,3 +16,40 @@
         model = "Nokia N950";
         compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
 };
+
+&i2c2 {
+        smia_1: camera@10 {
+                compatible = "nokia,smia";
+                reg = <0x10>;
+                /* No reset gpio */
+                vana-supply = <&vaux3>;
+                clocks = <&isp 0>;
+                clock-frequency = <9600000>;
+                nokia,nvm-size = <(16 * 64)>;
+                port {
+                        smia_1_1: endpoint {
+                                link-frequencies = /bits/ 64 <210000000 333600000 398400000>;
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&csi2a_ep>;
+                        };
+                };
+        };
+};
+
+&isp {
+        vdd-csiphy1-supply = <&vaux2>;
+        vdd-csiphy2-supply = <&vaux2>;
+        ports {
+                port@2 {
+                        reg = <2>;
+                        csi2a_ep: endpoint {
+                                remote-endpoint = <&smia_1_1>;
+                                clock-lanes = <2>;
+                                data-lanes = <3 1>;
+                                crc = <1>;
+                                lane-polarities = <1 1 1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
index d36bf0250a05..18e1649681c1 100644
--- a/arch/arm/boot/dts/omap3-overo-base.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
@@ -27,7 +27,6 @@
                 ti,model = "overo";
 
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         /* HS USB Port 2 Power */
diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
new file mode 100644
index 000000000000..9619a28dfd7d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * device tree for OpenPandora 1GHz with DM3730
+ */
+
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "omap3-pandora-common.dtsi"
+
+/ {
+        model = "Pandora Handheld Console 1GHz";
+
+        compatible = "ti,omap36xx", "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusb2_2_pins
+                &control_pins
+        >;
+
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+
+        mmc3_pins: pinmux_mmc3_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
+                        OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_ctl.sdmmc3_cmd */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d5.sdmmc3_dat1 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
+                >;
+        };
+
+        control_pins: pinmux_control_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4)    /* etk_d0.gpio_14 =  HP_SHUTDOWN */
+                        OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4)            /* etk_d1.gpio_15 =  BT_SHUTDOWN */
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 =  RESET_USB_HOST */
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4)             /* etk_d7.gpio_21 =  WIFI IRQ */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)            /* etk_d8.gpio_22 =  MSECURE */
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4)            /* etk_d9.gpio_23 =  WIFI_POWER */
+                        OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4)                 /* reserved.gpio_127 = MMC2_WP */
+                        OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4)                 /* reserved.gpio_126 = MMC1_WP */
+                        OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4)                /* reserved.gpio_128 = LED_MMC1 */
+                        OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4)                /* reserved.gpio_129 = LED_MMC2 */
+
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts
new file mode 100644
index 000000000000..fb803a70a2bb
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-600mhz.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * device tree for OpenPandora with OMAP3530
+ */
+
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+#include "omap3-pandora-common.dtsi"
+
+/ {
+        model = "Pandora Handheld Console";
+
+        compatible = "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusb2_2_pins
+                &control_pins
+        >;
+
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+
+        mmc3_pins: pinmux_mmc3_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
+                        OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_ctl.sdmmc3_cmd */
+                        OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
+                        OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
+                        OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d5.sdmmc3_dat1 */
+                        OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
+                >;
+        };
+
+        control_pins: pinmux_control_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4)    /* etk_d0.gpio_14 =  HP_SHUTDOWN */
+                        OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4)            /* etk_d1.gpio_15 =  BT_SHUTDOWN */
+                        OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 =  RESET_USB_HOST */
+                        OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4)             /* etk_d7.gpio_21 =  WIFI IRQ */
+                        OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)            /* etk_d8.gpio_22 =  MSECURE */
+                        OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4)            /* etk_d9.gpio_23 =  WIFI_POWER */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi
new file mode 100644
index 000000000000..782ab1ff1d08
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi
@@ -0,0 +1,640 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * Common device tree include for OpenPandora devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vcc>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+
+        aliases {
+                display0 = &lcd;
+        };
+
+        tv: connector@1 {
+                compatible = "connector-analog-tv";
+                label = "tv";
+
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
+
+        gpio-leds {
+
+                compatible = "gpio-leds";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+
+                led@1 {
+                        label = "pandora::sd1";
+                        gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;    /* GPIO_128 */
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+
+                led@2 {
+                        label = "pandora::sd2";
+                        gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;    /* GPIO_129 */
+                        linux,default-trigger = "mmc1";
+                        default-state = "off";
+                };
+
+                led@3 {
+                        label = "pandora::bluetooth";
+                        gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;   /* GPIO_158 */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+
+                led@4 {
+                        label = "pandora::wifi";
+                        gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;   /* GPIO_159 */
+                        linux,default-trigger = "mmc2";
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&button_pins>;
+
+                up-button {
+                        label = "up";
+                        linux,code = <KEY_UP>;
+                        gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;    /* GPIO_110 */
+                        gpio-key,wakeup;
+                };
+
+                down-button {
+                        label = "down";
+                        linux,code = <KEY_DOWN>;
+                        gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;     /* GPIO_103 */
+                        gpio-key,wakeup;
+                };
+
+                left-button {
+                        label = "left";
+                        linux,code = <KEY_LEFT>;
+                        gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;     /* GPIO_96 */
+                        gpio-key,wakeup;
+                };
+
+                right-button {
+                        label = "right";
+                        linux,code = <KEY_RIGHT>;
+                        gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;     /* GPIO_98 */
+                        gpio-key,wakeup;
+                };
+
+                pageup-button {
+                        label = "game 1";
+                        linux,code = <KEY_PAGEUP>;
+                        gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;    /* GPIO_109 */
+                        gpio-key,wakeup;
+                };
+
+                pagedown-button {
+                        label = "game 3";
+                        linux,code = <KEY_PAGEDOWN>;
+                        gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;    /* GPIO_106 */
+                        gpio-key,wakeup;
+                };
+
+                home-button {
+                        label = "game 4";
+                        linux,code = <KEY_HOME>;
+                        gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;     /* GPIO_101 */
+                        gpio-key,wakeup;
+                };
+
+                end-button {
+                        label = "game 2";
+                        linux,code = <KEY_END>;
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;    /* GPIO_111 */
+                        gpio-key,wakeup;
+                };
+
+                right-shift {
+                        label = "l";
+                        linux,code = <KEY_RIGHTSHIFT>;
+                        gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;     /* GPIO_102 */
+                        gpio-key,wakeup;
+                };
+
+                kp-plus {
+                        label = "l2";
+                        linux,code = <KEY_KPPLUS>;
+                        gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;     /* GPIO_97 */
+                        gpio-key,wakeup;
+                };
+
+                right-ctrl {
+                        label = "r";
+                        linux,code = <KEY_RIGHTCTRL>;
+                        gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;     /* GPIO_105 */
+                        gpio-key,wakeup;
+                };
+
+                kp-minus {
+                        label = "r2";
+                        linux,code = <KEY_KPMINUS>;
+                        gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;    /* GPIO_107 */
+                        gpio-key,wakeup;
+                };
+
+                left-ctrl {
+                        label = "ctrl";
+                        linux,code = <KEY_LEFTCTRL>;
+                        gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;     /* GPIO_104 */
+                        gpio-key,wakeup;
+                };
+
+                menu {
+                        label = "menu";
+                        linux,code = <KEY_MENU>;
+                        gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;     /* GPIO_99 */
+                        gpio-key,wakeup;
+                };
+
+                hold {
+                        label = "hold";
+                        linux,code = <KEY_COFFEE>;
+                        gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;    /* GPIO_176 */
+                        gpio-key,wakeup;
+                };
+
+                left-alt {
+                        label = "alt";
+                        linux,code = <KEY_LEFTALT>;
+                        gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;    /* GPIO_100 */
+                        gpio-key,wakeup;
+                };
+
+                lid {
+                        label = "lid";
+                        linux,code = <0x00>;    /* SW_LID lid shut */
+                        linux,input-type = <0x05>;    /* EV_SW */
+                        gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;   /* GPIO_108 */
+                };
+        };
+};
+
+&omap3_pmx_core {
+
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat3.sdmmc2_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat4.sdmmc2_dirdat0 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat5.sdmmc2_dirdat1 */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat6.sdmmc2_dircmd */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1)         /* sdmmc2_dat7.sdmmc2_clkin */
+                >;
+        };
+
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)       /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)       /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)       /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)       /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)       /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)       /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)       /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)       /* dss_data23.dss_data23 */
+                        OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4)       /* GPIO_157 = lcd reset */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+
+        led_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4)       /* GPIO_128 */
+                        OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4)       /* GPIO_129 */
+                        OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4)       /* GPIO_158 */
+                        OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4)       /* GPIO_159 */
+                >;
+        };
+
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4)        /* GPIO_96 */
+                        OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4)        /* GPIO_97 */
+                        OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4)        /* GPIO_98 */
+                        OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4)        /* GPIO_99 */
+                        OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4)        /* GPIO_100 */
+                        OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4)        /* GPIO_101 */
+                        OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4)        /* GPIO_102 */
+                        OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4)        /* GPIO_103 */
+                        OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4)        /* GPIO_104 */
+                        OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4)        /* GPIO_105 */
+                        OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4)        /* GPIO_106 */
+                        OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4)        /* GPIO_107 */
+                        OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4)        /* GPIO_108 */
+                        OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4)        /* GPIO_109 */
+                        OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4)        /* GPIO_110 */
+                        OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4)        /* GPIO_111 */
+                        OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4)        /* GPIO_176 */
+                >;
+        };
+
+        penirq_pins: pinmux_penirq_pins {
+                pinctrl-single,pins = <
+                        /* here we could enable to wakeup the cpu from suspend by a pen touch */
+                        OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4)        /* GPIO_94 */
+                >;
+        };
+
+};
+
+&omap3_pmx_core2 {
+        /* define in CPU specific file that includes this one
+         * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD()
+         */
+};
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+
+                twl_power: power {
+                        compatible = "ti,twl4030-power-reset";
+                        ti,use_poweroff;
+                };
+
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+
+                        codec {
+                                ti,ramp_delay_value = <3>;
+                        };
+                };
+        };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&twl_keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <6>;
+        linux,keymap = <
+                MATRIX_KEY(0, 0, KEY_9)
+                MATRIX_KEY(0, 1, KEY_8)
+                MATRIX_KEY(0, 2, KEY_I)
+                MATRIX_KEY(0, 3, KEY_J)
+                MATRIX_KEY(0, 4, KEY_N)
+                MATRIX_KEY(0, 5, KEY_M)
+                MATRIX_KEY(1, 0, KEY_0)
+                MATRIX_KEY(1, 1, KEY_7)
+                MATRIX_KEY(1, 2, KEY_U)
+                MATRIX_KEY(1, 3, KEY_H)
+                MATRIX_KEY(1, 4, KEY_B)
+                MATRIX_KEY(1, 5, KEY_SPACE)
+                MATRIX_KEY(2, 0, KEY_BACKSPACE)
+                MATRIX_KEY(2, 1, KEY_6)
+                MATRIX_KEY(2, 2, KEY_Y)
+                MATRIX_KEY(2, 3, KEY_G)
+                MATRIX_KEY(2, 4, KEY_V)
+                MATRIX_KEY(2, 5, KEY_FN)
+                MATRIX_KEY(3, 0, KEY_O)
+                MATRIX_KEY(3, 1, KEY_5)
+                MATRIX_KEY(3, 2, KEY_T)
+                MATRIX_KEY(3, 3, KEY_F)
+                MATRIX_KEY(3, 4, KEY_C)
+                MATRIX_KEY(4, 0, KEY_P)
+                MATRIX_KEY(4, 1, KEY_4)
+                MATRIX_KEY(4, 2, KEY_R)
+                MATRIX_KEY(4, 3, KEY_D)
+                MATRIX_KEY(4, 4, KEY_X)
+                MATRIX_KEY(5, 0, KEY_K)
+                MATRIX_KEY(5, 1, KEY_3)
+                MATRIX_KEY(5, 2, KEY_E)
+                MATRIX_KEY(5, 3, KEY_S)
+                MATRIX_KEY(5, 4, KEY_Z)
+                MATRIX_KEY(6, 0, KEY_L)
+                MATRIX_KEY(6, 1, KEY_2)
+                MATRIX_KEY(6, 2, KEY_W)
+                MATRIX_KEY(6, 3, KEY_A)
+                MATRIX_KEY(6, 4, KEY_RIGHTBRACE)
+                MATRIX_KEY(7, 0, KEY_ENTER)
+                MATRIX_KEY(7, 1, KEY_1)
+                MATRIX_KEY(7, 2, KEY_Q)
+                MATRIX_KEY(7, 3, KEY_LEFTSHIFT)
+                MATRIX_KEY(7, 4, KEY_LEFTBRACE )
+         >;
+};
+
+/* backup battery charger */
+&charger {
+        ti,bb-uvolt = <3200000>;
+        ti,bb-uamp = <150>;
+};
+
+/* MMC2 */
+&vmmc2 {
+        regulator-min-microvolt = <1850000>;
+        regulator-max-microvolt = <3150000>;
+};
+
+/* LCD */
+&vaux1 {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+};
+
+/* USB Host PHY */
+&vaux2 {
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+};
+
+/* available on expansion connector */
+&vaux3 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
+/* ADS7846 and nubs */
+&vaux4 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
+/* power audio DAC and LID sensor */
+&vsim {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+        regulator-always-on;
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        /* no clients so we should disable clock */
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        bq27500@55 {
+                compatible = "ti,bq27500";
+                reg = <0x55>;
+        };
+
+};
+
+&usb_otg_hs {
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        phys = <&usb2_phy>;
+        phy-names = "usb2-phy";
+        mode = <3>;
+        power = <50>;
+};
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+        cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; /* GPIO_126 */
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&vmmc2>;
+        bus-width = <4>;
+        cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* GPIO_127 */
+};
+
+/* bluetooth*/
+&uart1 {
+};
+
+/* spare (expansion connector) */
+&uart2 {
+};
+
+/* console (expansion connector) */
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+};
+
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&gpmc {
+        ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
+
+        nand@0,0 {
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "sw";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,device-width = <2>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */
+
+                x-loader@0 {
+                        label = "xloader";
+                        reg = <0 0x80000>;
+                };
+
+                bootloaders@80000 {
+                        label = "uboot";
+                        reg = <0x80000 0x1e0000>;
+                };
+
+                bootloaders_env@260000 {
+                        label = "uboot-env";
+                        reg = <0x260000 0x20000>;
+                };
+
+                kernel@280000 {
+                        label = "boot";
+                        reg = <0x280000 0xa00000>;
+                };
+
+                filesystem@680000 {
+                        label = "rootfs";
+                        reg = <0xc80000 0>;     /* 0 = MTDPART_SIZ_FULL */
+                };
+        };
+};
+
+&mcspi1 {
+        tsc2046@0 {
+                reg = <0>;      /* CS0 */
+                compatible = "ti,tsc2046";
+                spi-max-frequency = <1000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&penirq_pins>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <30 0>;    /* GPIO_94 */
+                pendown-gpio = <&gpio3 30 0>;
+                vcc-supply = <&vaux4>;
+
+                ti,x-min = /bits/ 16 <0>;
+                ti,x-max = /bits/ 16 <8000>;
+                ti,y-min = /bits/ 16 <0>;
+                ti,y-max = /bits/ 16 <4800>;
+                ti,x-plate-ohms = /bits/ 16 <40>;
+                ti,pressure-max = /bits/ 16 <255>;
+
+                linux,wakeup;
+        };
+
+        lcd: lcd@1 {
+                reg = <1>;      /* CS1 */
+                compatible =    "omapdss,tpo,td043mtea1";
+                spi-max-frequency = <100000>;
+                spi-cpol;
+                spi-cpha;
+
+                label = "lcd";
+                reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;      /* GPIO_157 */
+                vcc-supply = <&vaux1>;
+
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+        };
+
+
+};
+
+/* n/a - used as GPIOs */
+&mcbsp1 {
+};
+
+/* audio DAC */
+&mcbsp2 {
+};
+
+/* bluetooth */
+&mcbsp3 {
+};
+
+/* to twl4030*/
+&mcbsp4 {
+};
+
+&venc {
+        status = "ok";
+
+        vdda-supply = <&vdac>;
+
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <2>;
+                };
+        };
+};
+
+&dss {
+        pinctrl-names = "default";
+        pinctrl-0 = < &dss_dpi_pins >;
+
+        status = "ok";
+        vdds_dsi-supply = <&vpll2>;
+
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index e89820a6776e..7bd8d9a4f67f 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -8,7 +8,16 @@
  */
 /dts-v1/;
 
-#include "omap34xx-hs.dtsi"
+#include "omap34xx.dtsi"
+
+/* Secure omaps have some devices inaccessible depending on the firmware */
+&aes {
+        status = "disabled";
+};
+
+&sham {
+        status = "disabled";
+};
 
 / {
         cpus {
@@ -45,7 +54,6 @@
 
                 /* McBSP2 is used for onboard sound, same as on beagle */
                 ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
         };
 
         /* Regulator to enable/switch the vcc of the Wifi module */
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 01b71111bd55..02cd996d0b06 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -87,6 +87,60 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
+                l4_core: l4@48000000 {
+                        compatible = "ti,omap3-l4-core", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x48000000 0x1000000>;
+
+                        scm: scm@2000 {
+                                compatible = "ti,omap3-scm", "simple-bus";
+                                reg = <0x2000 0x2000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x2000>;
+
+                                omap3_pmx_core: pinmux@30 {
+                                        compatible = "ti,omap3-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x238>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0xff1f>;
+                                };
+
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x330>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+
+                                scm_clockdomains: clockdomains {
+                                };
+
+                                omap3_pmx_wkup: pinmux@a00 {
+                                        compatible = "ti,omap3-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0xa00 0x5c>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0xff1f>;
+                                };
+                        };
+                };
+
                 aes: aes@480c5000 {
                         compatible = "ti,omap3-aes";
                         ti,hwmods = "aes";
@@ -121,19 +175,6 @@
                         };
                 };
 
-                scrm: scrm@48002000 {
-                        compatible = "ti,omap3-scrm";
-                        reg = <0x48002000 0x2000>;
-
-                        scrm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-
-                        scrm_clockdomains: clockdomains {
-                        };
-                };
-
                 counter32k: counter@48320000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x48320000 0x20>;
@@ -155,41 +196,14 @@
                                      <14>,
                                      <15>;
                         #dma-cells = <1>;
-                        #dma-channels = <32>;
-                        #dma-requests = <96>;
-                };
-
-                omap3_pmx_core: pinmux@48002030 {
-                        compatible = "ti,omap3-padconf", "pinctrl-single";
-                        reg = <0x48002030 0x0238>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0xff1f>;
-                };
-
-                omap3_pmx_wkup: pinmux@48002a00 {
-                        compatible = "ti,omap3-padconf", "pinctrl-single";
-                        reg = <0x48002a00 0x5c>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0xff1f>;
-                };
-
-                omap3_scm_general: tisyscon@48002270 {
-                        compatible = "syscon";
-                        reg = <0x48002270 0x2f0>;
+                        dma-channels = <32>;
+                        dma-requests = <96>;
                 };
 
                 pbias_regulator: pbias_regulator {
                         compatible = "ti,pbias-omap";
                         reg = <0x2b0 0x4>;
-                        syscon = <&omap3_scm_general>;
+                        syscon = <&scm_conf>;
                         pbias_mmc_reg: pbias_mmc_omap2430 {
                                 regulator-name = "pbias_mmc_omap2430";
                                 regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/omap34xx-hs.dtsi b/arch/arm/boot/dts/omap34xx-hs.dtsi
deleted file mode 100644
index 1ff626489546..000000000000
--- a/arch/arm/boot/dts/omap34xx-hs.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Disabled modules for secure omaps */
-
-#include "omap34xx.dtsi"
-
-/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
-        status = "disabled";
-};
-
-&sham {
-        status = "disabled";
-};
-
-&timer12 {
-        status = "disabled";
-};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 3819c1e91591..4f6b2d5b1902 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/media/omap3-isp.h>
+
 #include "omap3.dtsi"
 
 / {
@@ -37,6 +39,21 @@
                         pinctrl-single,register-width = <16>;
                         pinctrl-single,function-mask = <0xff1f>;
                 };
+
+                isp: isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x017c>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&scm_conf 0xdc>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/omap36xx-hs.dtsi b/arch/arm/boot/dts/omap36xx-hs.dtsi
deleted file mode 100644
index 2c7febb0e016..000000000000
--- a/arch/arm/boot/dts/omap36xx-hs.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Disabled modules for secure omaps */
-
-#include "omap36xx.dtsi"
-
-/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
-        status = "disabled";
-};
-
-&sham {
-        status = "disabled";
-};
-
-&timer12 {
-        status = "disabled";
-};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 541704a59a5a..86253de5a97a 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/media/omap3-isp.h>
+
 #include "omap3.dtsi"
 
 / {
@@ -69,6 +71,21 @@
                         pinctrl-single,register-width = <16>;
                         pinctrl-single,function-mask = <0xff1f>;
                 };
+
+                isp: isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x0600>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&scm_conf 0x2f0>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 5c375003bad1..bbba5bdc4bc9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -79,13 +79,14 @@
                 clock-div = <1>;
         };
 };
-&scrm_clocks {
+
+&scm_clocks {
         mcbsp5_mux_fck: mcbsp5_mux_fck {
                 #clock-cells = <0>;
                 compatible = "ti,composite-mux-clock";
                 clocks = <&core_96m_fck>, <&mcbsp_clks>;
                 ti,bit-shift = <4>;
-                reg = <0x02d8>;
+                reg = <0x68>;
         };
 
         mcbsp5_fck: mcbsp5_fck {
@@ -99,7 +100,7 @@
                 compatible = "ti,composite-mux-clock";
                 clocks = <&core_96m_fck>, <&mcbsp_clks>;
                 ti,bit-shift = <2>;
-                reg = <0x0274>;
+                reg = <0x04>;
         };
 
         mcbsp1_fck: mcbsp1_fck {
@@ -113,7 +114,7 @@
                 compatible = "ti,composite-mux-clock";
                 clocks = <&per_96m_fck>, <&mcbsp_clks>;
                 ti,bit-shift = <6>;
-                reg = <0x0274>;
+                reg = <0x04>;
         };
 
         mcbsp2_fck: mcbsp2_fck {
@@ -126,7 +127,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,composite-mux-clock";
                 clocks = <&per_96m_fck>, <&mcbsp_clks>;
-                reg = <0x02d8>;
+                reg = <0x68>;
         };
 
         mcbsp3_fck: mcbsp3_fck {
@@ -140,7 +141,7 @@
                 compatible = "ti,composite-mux-clock";
                 clocks = <&per_96m_fck>, <&mcbsp_clks>;
                 ti,bit-shift = <2>;
-                reg = <0x02d8>;
+                reg = <0x68>;
         };
 
         mcbsp4_fck: mcbsp4_fck {
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
index cb9458feb2e3..ab7f87ae96f0 100644
--- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -18,7 +18,7 @@ cpu_thermal: cpu_thermal {
                         /* sensor       ID */
         thermal-sensors = <&bandgap     0>;
 
-        trips {
+        cpu_trips: trips {
                 cpu_alert0: cpu_alert {
                         temperature = <100000>; /* millicelsius */
                         hysteresis = <2000>; /* millicelsius */
@@ -31,7 +31,7 @@ cpu_thermal: cpu_thermal {
                 };
         };
 
-        cooling-maps {
+        cpu_cooling_maps: cooling-maps {
                 map0 {
                         trip = <&cpu_alert0>;
                         cooling-device =
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 074147cebae4..cf2681b2d173 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -114,99 +114,141 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
-                cm1: cm1@4a004000 {
-                        compatible = "ti,omap4-cm1";
-                        reg = <0x4a004000 0x2000>;
-
-                        cm1_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
+                l4_cfg: l4@4a000000 {
+                        compatible = "ti,omap4-l4-cfg", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4a000000 0x1000000>;
 
-                        cm1_clockdomains: clockdomains {
-                        };
-                };
+                        cm1: cm1@4000 {
+                                compatible = "ti,omap4-cm1";
+                                reg = <0x4000 0x2000>;
 
-                prm: prm@4a306000 {
-                        compatible = "ti,omap4-prm";
-                        reg = <0x4a306000 0x3000>;
-                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                cm1_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                        prm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                cm1_clockdomains: clockdomains {
+                                };
                         };
 
-                        prm_clockdomains: clockdomains {
-                        };
-                };
+                        cm2: cm2@8000 {
+                                compatible = "ti,omap4-cm2";
+                                reg = <0x8000 0x3000>;
 
-                cm2: cm2@4a008000 {
-                        compatible = "ti,omap4-cm2";
-                        reg = <0x4a008000 0x3000>;
+                                cm2_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                        cm2_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                cm2_clockdomains: clockdomains {
+                                };
                         };
 
-                        cm2_clockdomains: clockdomains {
+                        omap4_scm_core: scm@2000 {
+                                compatible = "ti,omap4-scm-core", "simple-bus";
+                                reg = <0x2000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x1000>;
+
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                };
                         };
-                };
-
-                scrm: scrm@4a30a000 {
-                        compatible = "ti,omap4-scrm";
-                        reg = <0x4a30a000 0x2000>;
 
-                        scrm_clocks: clocks {
+                        omap4_padconf_core: scm@100000 {
+                                compatible = "ti,omap4-scm-padconf-core",
+                                             "simple-bus";
                                 #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x100000 0x1000>;
+
+                                omap4_pmx_core: pinmux@40 {
+                                        compatible = "ti,omap4-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x40 0x0196>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
+
+                                omap4_padconf_global: omap4_padconf_global@5a0 {
+                                        compatible = "syscon";
+                                        reg = <0x5a0 0x170>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x60 0x4>;
+                                                syscon = <&omap4_padconf_global>;
+                                                pbias_mmc_reg: pbias_mmc_omap4 {
+                                                        regulator-name = "pbias_mmc_omap4";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
                         };
 
-                        scrm_clockdomains: clockdomains {
-                        };
-                };
-
-                counter32k: counter@4a304000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x4a304000 0x20>;
-                        ti,hwmods = "counter_32k";
-                };
-
-                omap4_pmx_core: pinmux@4a100040 {
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
-                        reg = <0x4a100040 0x0196>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
-                omap4_pmx_wkup: pinmux@4a31e040 {
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
-                        reg = <0x4a31e040 0x0038>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
-
-                omap4_padconf_global: tisyscon@4a1005a0 {
-                        compatible = "syscon";
-                        reg = <0x4a1005a0 0x170>;
-                };
-
-                pbias_regulator: pbias_regulator {
-                        compatible = "ti,pbias-omap";
-                        reg = <0x60 0x4>;
-                        syscon = <&omap4_padconf_global>;
-                        pbias_mmc_reg: pbias_mmc_omap4 {
-                                regulator-name = "pbias_mmc_omap4";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
+                        l4_wkup: l4@300000 {
+                                compatible = "ti,omap4-l4-wkup", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x300000 0x40000>;
+
+                                counter32k: counter@4000 {
+                                        compatible = "ti,omap-counter32k";
+                                        reg = <0x4000 0x20>;
+                                        ti,hwmods = "counter_32k";
+                                };
+
+                                prm: prm@6000 {
+                                        compatible = "ti,omap4-prm";
+                                        reg = <0x6000 0x3000>;
+                                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+                                        prm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+
+                                        prm_clockdomains: clockdomains {
+                                        };
+                                };
+
+                                scrm: scrm@a000 {
+                                        compatible = "ti,omap4-scrm";
+                                        reg = <0xa000 0x2000>;
+
+                                        scrm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+
+                                        scrm_clockdomains: clockdomains {
+                                        };
+                                };
+
+                                omap4_pmx_wkup: pinmux@1e040 {
+                                        compatible = "ti,omap4-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x1e040 0x0038>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
                         };
                 };
 
@@ -223,8 +265,8 @@
                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
-                        #dma-channels = <32>;
-                        #dma-requests = <127>;
+                        dma-channels = <32>;
+                        dma-requests = <127>;
                 };
 
                 gpio1: gpio@4a310000 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf42c9f..3cdb5c22148d 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -129,99 +129,141 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
-                prm: prm@4ae06000 {
-                        compatible = "ti,omap5-prm";
-                        reg = <0x4ae06000 0x3000>;
-                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                l4_cfg: l4@4a000000 {
+                        compatible = "ti,omap5-l4-cfg", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4a000000 0x22a000>;
 
-                        prm_clocks: clocks {
+                        scm_core: scm@2000 {
+                                compatible = "ti,omap5-scm-core", "simple-bus";
+                                reg = <0x2000 0x1000>;
                                 #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x800>;
+
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                };
                         };
 
-                        prm_clockdomains: clockdomains {
+                        scm_padconf_core: scm@2800 {
+                                compatible = "ti,omap5-scm-padconf-core",
+                                             "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2800 0x800>;
+
+                                omap5_pmx_core: pinmux@40 {
+                                        compatible = "ti,omap5-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x40 0x01b6>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
+
+                                omap5_padconf_global: omap5_padconf_global@5a0 {
+                                        compatible = "syscon";
+                                        reg = <0x5a0 0xec>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x60 0x4>;
+                                                syscon = <&omap5_padconf_global>;
+                                                pbias_mmc_reg: pbias_mmc_omap5 {
+                                                        regulator-name = "pbias_mmc_omap5";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
                         };
-                };
 
-                cm_core_aon: cm_core_aon@4a004000 {
-                        compatible = "ti,omap5-cm-core-aon";
-                        reg = <0x4a004000 0x2000>;
+                        cm_core_aon: cm_core_aon@4000 {
+                                compatible = "ti,omap5-cm-core-aon";
+                                reg = <0x4000 0x2000>;
 
-                        cm_core_aon_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
+                                cm_core_aon_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                        cm_core_aon_clockdomains: clockdomains {
+                                cm_core_aon_clockdomains: clockdomains {
+                                };
                         };
-                };
 
-                scrm: scrm@4ae0a000 {
-                        compatible = "ti,omap5-scrm";
-                        reg = <0x4ae0a000 0x2000>;
+                        cm_core: cm_core@8000 {
+                                compatible = "ti,omap5-cm-core";
+                                reg = <0x8000 0x3000>;
 
-                        scrm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
+                                cm_core_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                        scrm_clockdomains: clockdomains {
+                                cm_core_clockdomains: clockdomains {
+                                };
                         };
                 };
 
-                cm_core: cm_core@4a008000 {
-                        compatible = "ti,omap5-cm-core";
-                        reg = <0x4a008000 0x3000>;
+                l4_wkup: l4@4ae00000 {
+                        compatible = "ti,omap5-l4-wkup", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4ae00000 0x2b000>;
 
-                        cm_core_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+                        counter32k: counter@4000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x4000 0x40>;
+                                ti,hwmods = "counter_32k";
                         };
 
-                        cm_core_clockdomains: clockdomains {
+                        prm: prm@6000 {
+                                compatible = "ti,omap5-prm";
+                                reg = <0x6000 0x3000>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+                                prm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+
+                                prm_clockdomains: clockdomains {
+                                };
                         };
-                };
 
-                counter32k: counter@4ae04000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x4ae04000 0x40>;
-                        ti,hwmods = "counter_32k";
-                };
+                        scrm: scrm@a000 {
+                                compatible = "ti,omap5-scrm";
+                                reg = <0xa000 0x2000>;
 
-                omap5_pmx_core: pinmux@4a002840 {
-                        compatible = "ti,omap5-padconf", "pinctrl-single";
-                        reg = <0x4a002840 0x01b6>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
-                omap5_pmx_wkup: pinmux@4ae0c840 {
-                        compatible = "ti,omap5-padconf", "pinctrl-single";
-                        reg = <0x4ae0c840 0x0038>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
+                                scrm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
 
-                omap5_padconf_global: tisyscon@4a002da0 {
-                        compatible = "syscon";
-                        reg = <0x4A002da0 0xec>;
-                };
+                                scrm_clockdomains: clockdomains {
+                                };
+                        };
 
-                pbias_regulator: pbias_regulator {
-                        compatible = "ti,pbias-omap";
-                        reg = <0x60 0x4>;
-                        syscon = <&omap5_padconf_global>;
-                        pbias_mmc_reg: pbias_mmc_omap5 {
-                                regulator-name = "pbias_mmc_omap5";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
+                        omap5_pmx_wkup: pinmux@c840 {
+                                compatible = "ti,omap5-padconf",
+                                             "pinctrl-single";
+                                reg = <0xc840 0x0038>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #interrupt-cells = <1>;
+                                interrupt-controller;
+                                pinctrl-single,register-width = <16>;
+                                pinctrl-single,function-mask = <0x7fff>;
                         };
                 };
 
@@ -238,8 +280,8 @@
                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
-                        #dma-channels = <32>;
-                        #dma-requests = <127>;
+                        dma-channels = <32>;
+                        dma-requests = <127>;
                 };
 
                 gpio1: gpio@4ae10000 {
@@ -929,8 +971,8 @@
                                       <0x4A096800 0x40>; /* pll_ctrl */
                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
                                 ctrl-module = <&omap_control_sata>;
-                                clocks = <&sys_clkin>;
-                                clock-names = "sysclk";
+                                clocks = <&sys_clkin>, <&sata_ref_clk>;
+                                clock-names = "sysclk", "refclk";
                                 #phy-cells = <0>;
                         };
                 };
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 36cafbfa1bfa..606753eb72c8 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -12,6 +12,12 @@
                 bootargs = "console=ttyLP0,115200";
         };
 
+        clk16m: clk16m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -47,6 +53,21 @@
         status  = "okay";
 };
 
+&dspi1 {
+        status = "okay";
+
+        mcp2515can: can@0 {
+                compatible = "microchip,mcp2515";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_can_int>;
+                reg = <0>;
+                clocks = <&clk16m>;
+                spi-max-frequency = <10000000>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <11 GPIO_ACTIVE_LOW>;
+        };
+};
+
 &esdhc1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc1>;
@@ -94,3 +115,13 @@
 &usbh1 {
         vbus-supply = <&usbh_vbus_reg>;
 };
+
+&iomuxc {
+        vf610-colibri {
+                pinctrl_can_int: can_int {
+                        fsl,pins = <
+                                VF610_PAD_PTB21__GPIO_43        0x22ed
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 5c2b7320856d..fbef0828e930 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -23,6 +23,12 @@
         status = "okay";
 };
 
+&dspi1 {
+        bus-num = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_dspi1>;
+};
+
 &edma0 {
         status = "okay";
 };
@@ -107,6 +113,15 @@
                         >;
                 };
 
+                pinctrl_dspi1: dspi1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTD5__DSPI1_CS0               0x33e2
+                                VF610_PAD_PTD6__DSPI1_SIN               0x33e1
+                                VF610_PAD_PTD7__DSPI1_SOUT              0x33e2
+                                VF610_PAD_PTD8__DSPI1_SCK               0x33e2
+                        >;
+                };
+
                 pinctrl_esdhc1: esdhc1grp {
                         fsl,pins = <
                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2d1ddf..e976d2fa1527 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
         };
 
         soc {
-                interrupt-parent = <&intc>;
-
                 aips-bus@40000000 {
 
                         intc: interrupt-controller@40002000 {
                                 compatible = "arm,cortex-a9-gic";
                                 #interrupt-cells = <3>;
                                 interrupt-controller;
+                                interrupt-parent = <&intc>;
                                 reg = <0x40003000 0x1000>,
                                       <0x40002100 0x100>;
                         };
@@ -40,145 +39,17 @@
                                 compatible = "arm,cortex-a9-global-timer";
                                 reg = <0x40002200 0x20>;
                                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
                                 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
                         };
                 };
         };
 };
 
-&adc0 {
-        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&adc1 {
-        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can0 {
-        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&can1 {
-        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&dspi0 {
-        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&edma0 {
-        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "edma-tx", "edma-err";
-};
-
-&edma1 {
-        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "edma-tx", "edma-err";
-};
-
-&esdhc1 {
-        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec0 {
-        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&fec1 {
-        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&ftm {
-        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio0 {
-        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio1 {
-        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio2 {
-        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio3 {
-        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpio4 {
-        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&i2c0 {
-        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&pit {
-        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&qspi0 {
-        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&sai2 {
-        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&snvsrtc {
-        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&src {
-        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart0 {
-        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart1 {
-        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart2 {
-        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart3 {
-        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart4 {
-        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&uart5 {
-        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbdev0 {
-        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbh1 {
-        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy0 {
-        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&usbphy1 {
-        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+&mscm_ir {
+        interrupt-parent = <&intc>;
 };
 
 &wdoga5 {
-        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce15eaf..4aa335166be7 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "simple-bus";
+                interrupt-parent = <&mscm_ir>;
                 ranges;
 
                 aips0: aips-bus@40000000 {
@@ -62,6 +63,19 @@
                         #size-cells = <1>;
                         ranges;
 
+                        mscm_cpucfg: cpucfg@40001000 {
+                                compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+                                reg = <0x40001000 0x800>;
+                        };
+
+                        mscm_ir: interrupt-controller@40001800 {
+                                compatible = "fsl,vf610-mscm-ir";
+                                reg = <0x40001800 0x400>;
+                                fsl,cpucfg = <&mscm_cpucfg>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
                         edma0: dma-controller@40018000 {
                                 #dma-cells = <2>;
                                 compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
                                         <0x40024000 0x1000>,
                                         <0x40025000 0x1000>;
                                 dma-channels = <32>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+                                                <9 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
                                 clock-names = "dmamux0", "dmamux1";
                                 clocks = <&clks VF610_CLK_DMAMUX0>,
                                         <&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
                         can0: flexcan@40020000 {
                                 compatible = "fsl,vf610-flexcan";
                                 reg = <0x40020000 0x4000>;
+                                interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_FLEXCAN0>,
                                          <&clks VF610_CLK_FLEXCAN0>;
                                 clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
                         uart0: serial@40027000 {
                                 compatible = "fsl,vf610-lpuart";
                                 reg = <0x40027000 0x1000>;
+                                interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_UART0>;
                                 clock-names = "ipg";
                                 dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
                         uart1: serial@40028000 {
                                 compatible = "fsl,vf610-lpuart";
                                 reg = <0x40028000 0x1000>;
+                                interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_UART1>;
                                 clock-names = "ipg";
                                 dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
                         uart2: serial@40029000 {
                                 compatible = "fsl,vf610-lpuart";
                                 reg = <0x40029000 0x1000>;
+                                interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_UART2>;
                                 clock-names = "ipg";
                                 dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
                         uart3: serial@4002a000 {
                                 compatible = "fsl,vf610-lpuart";
                                 reg = <0x4002a000 0x1000>;
+                                interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_UART3>;
                                 clock-names = "ipg";
                                 dmas = <&edma0 0 8>,
@@ -133,15 +155,29 @@
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-dspi";
                                 reg = <0x4002c000 0x1000>;
+                                interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_DSPI0>;
                                 clock-names = "dspi";
                                 spi-num-chipselects = <5>;
                                 status = "disabled";
                         };
 
+                        dspi1: dspi1@4002d000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-dspi";
+                                reg = <0x4002d000 0x1000>;
+                                interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_DSPI1>;
+                                clock-names = "dspi";
+                                spi-num-chipselects = <5>;
+                                status = "disabled";
+                        };
+
                         sai2: sai@40031000 {
                                 compatible = "fsl,vf610-sai";
                                 reg = <0x40031000 0x1000>;
+                                interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_SAI2>;
                                 clock-names = "sai";
                                 dma-names = "tx", "rx";
@@ -153,6 +189,7 @@
                         pit: pit@40037000 {
                                 compatible = "fsl,vf610-pit";
                                 reg = <0x40037000 0x1000>;
+                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_PIT>;
                                 clock-names = "pit";
                         };
@@ -186,6 +223,7 @@
                         adc0: adc@4003b000 {
                                 compatible = "fsl,vf610-adc";
                                 reg = <0x4003b000 0x1000>;
+                                interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_ADC0>;
                                 clock-names = "adc";
                                 status = "disabled";
@@ -194,6 +232,7 @@
                         wdoga5: wdog@4003e000 {
                                 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
                                 reg = <0x4003e000 0x1000>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_WDT>;
                                 clock-names = "wdog";
                                 status = "disabled";
@@ -204,6 +243,7 @@
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-qspi";
                                 reg = <0x40044000 0x1000>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_QSPI0_EN>,
                                         <&clks VF610_CLK_QSPI0>;
                                 clock-names = "qspi_en", "qspi";
@@ -213,7 +253,6 @@
                         iomuxc: iomuxc@40048000 {
                                 compatible = "fsl,vf610-iomuxc";
                                 reg = <0x40048000 0x1000>;
-                                #gpio-range-cells = <3>;
                         };
 
                         gpio0: gpio@40049000 {
@@ -221,6 +260,7 @@
                                 reg = <0x40049000 0x1000 0x400ff000 0x40>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
+                                interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
                                 gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +271,7 @@
                                 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
+                                interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
                                 gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +282,7 @@
                                 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
+                                interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
                                 gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +293,7 @@
                                 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
+                                interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
                                 gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +304,7 @@
                                 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
+                                interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
                                 gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +318,7 @@
                         usbphy0: usbphy@40050800 {
                                 compatible = "fsl,vf610-usbphy";
                                 reg = <0x40050800 0x400>;
+                                interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_USBPHY0>;
                                 fsl,anatop = <&anatop>;
                                 status = "disabled";
@@ -282,6 +327,7 @@
                         usbphy1: usbphy@40050c00 {
                                 compatible = "fsl,vf610-usbphy";
                                 reg = <0x40050c00 0x400>;
+                                interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_USBPHY1>;
                                 fsl,anatop = <&anatop>;
                                 status = "disabled";
@@ -292,6 +338,7 @@
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-i2c";
                                 reg = <0x40066000 0x1000>;
+                                interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_I2C0>;
                                 clock-names = "ipg";
                                 dmas = <&edma0 0 50>,
@@ -311,6 +358,7 @@
                         usbdev0: usb@40034000 {
                                 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
                                 reg = <0x40034000 0x800>;
+                                interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_USBC0>;
                                 fsl,usbphy = <&usbphy0>;
                                 fsl,usbmisc = <&usbmisc0 0>;
@@ -329,6 +377,7 @@
                         src: src@4006e000 {
                                 compatible = "fsl,vf610-src", "syscon";
                                 reg = <0x4006e000 0x1000>;
+                                interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
                         };
                 };
 
@@ -345,6 +394,9 @@
                                         <0x400a1000 0x1000>,
                                         <0x400a2000 0x1000>;
                                 dma-channels = <32>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+                                                <11 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
                                 clock-names = "dmamux0", "dmamux1";
                                 clocks = <&clks VF610_CLK_DMAMUX2>,
                                         <&clks VF610_CLK_DMAMUX3>;
@@ -360,6 +412,7 @@
                                 snvsrtc: snvs-rtc-lp@34 {
                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                         reg = <0x34 0x58>;
+                                        interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
                                         clocks = <&clks VF610_CLK_SNVS>;
                                         clock-names = "snvs-rtc";
                                 };
@@ -368,6 +421,7 @@
                         uart4: serial@400a9000 {
                                 compatible = "fsl,vf610-lpuart";
                                 reg = <0x400a9000 0x1000>;
+                                interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_UART4>;
                                 clock-names = "ipg";
                                 status = "disabled";
@@ -376,6 +430,7 @@
                         uart5: serial@400aa000 {
                                 compatible = "fsl,vf610-lpuart";
                                 reg = <0x400aa000 0x1000>;
+                                interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_UART5>;
                                 clock-names = "ipg";
                                 status = "disabled";
@@ -384,6 +439,7 @@
                         adc1: adc@400bb000 {
                                 compatible = "fsl,vf610-adc";
                                 reg = <0x400bb000 0x1000>;
+                                interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_ADC1>;
                                 clock-names = "adc";
                                 status = "disabled";
@@ -392,6 +448,7 @@
                         esdhc1: esdhc@400b2000 {
                                 compatible = "fsl,imx53-esdhc";
                                 reg = <0x400b2000 0x1000>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_IPG_BUS>,
                                         <&clks VF610_CLK_PLATFORM_BUS>,
                                         <&clks VF610_CLK_ESDHC1>;
@@ -402,6 +459,7 @@
                         usbh1: usb@400b4000 {
                                 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
                                 reg = <0x400b4000 0x800>;
+                                interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_USBC1>;
                                 fsl,usbphy = <&usbphy1>;
                                 fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +478,7 @@
                         ftm: ftm@400b8000 {
                                 compatible = "fsl,ftm-timer";
                                 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+                                interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
                                 clock-names = "ftm-evt", "ftm-src",
                                         "ftm-evt-counter-en", "ftm-src-counter-en";
                                 clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +491,7 @@
                         fec0: ethernet@400d0000 {
                                 compatible = "fsl,mvf600-fec";
                                 reg = <0x400d0000 0x1000>;
+                                interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_ENET0>,
                                         <&clks VF610_CLK_ENET0>,
                                         <&clks VF610_CLK_ENET>;
@@ -442,6 +502,7 @@
                         fec1: ethernet@400d1000 {
                                 compatible = "fsl,mvf600-fec";
                                 reg = <0x400d1000 0x1000>;
+                                interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_ENET1>,
                                         <&clks VF610_CLK_ENET1>,
                                         <&clks VF610_CLK_ENET>;
@@ -452,6 +513,7 @@
                         can1: flexcan@400d4000 {
                                 compatible = "fsl,vf610-flexcan";
                                 reg = <0x400d4000 0x4000>;
+                                interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks VF610_CLK_FLEXCAN1>,
                                          <&clks VF610_CLK_FLEXCAN1>;
                                 clock-names = "ipg", "per";
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e6b0007355f8..af07e058ba11 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -24,9 +24,8 @@ CONFIG_ARCH_MXC=y
 CONFIG_MACH_SCB9328=y
 CONFIG_MACH_APF9328=y
 CONFIG_MACH_MX21ADS=y
-CONFIG_MACH_MX25_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX25SD=y
-CONFIG_MACH_IMX25_DT=y
+CONFIG_SOC_IMX25=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_MX27_3DS=y
 CONFIG_MACH_IMX27_VISSTRIM_M10=y
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 9d56781a8f80..f69a459f4f92 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -13,7 +13,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_KIRKWOOD=y
 CONFIG_MACH_NETXBIG=y
 CONFIG_ARCH_MXC=y
-CONFIG_MACH_IMX25_DT=y
+CONFIG_SOC_IMX25=y
 CONFIG_MACH_IMX27_DT=y
 CONFIG_ARCH_U300=y
 CONFIG_PCI_MVEBU=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e8a4c955241b..b7e6b6fba5e0 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -62,6 +62,17 @@ CONFIG_MACH_SPEAR1340=y
 CONFIG_ARCH_STI=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_EXYNOS5420_MCPM=y
+CONFIG_ARCH_SHMOBILE_MULTI=y
+CONFIG_ARCH_EMEV2=y
+CONFIG_ARCH_R7S72100=y
+CONFIG_ARCH_R8A73A4=y
+CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7779=y
+CONFIG_ARCH_R8A7790=y
+CONFIG_ARCH_R8A7791=y
+CONFIG_ARCH_R8A7794=y
+CONFIG_ARCH_SH73A0=y
+CONFIG_MACH_MARZEN=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_SIRF=y
 CONFIG_ARCH_TEGRA=y
@@ -84,6 +95,8 @@ CONFIG_PCI_KEYSTONE=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PCI_TEGRA=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PCI_RCAR_GEN2_PCIE=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=8
@@ -130,6 +143,7 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_OMAP_OCP2SCP=y
+CONFIG_SIMPLE_PM_BUS=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
@@ -157,6 +171,7 @@ CONFIG_AHCI_SUNXI=y
 CONFIG_AHCI_TEGRA=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
+CONFIG_SATA_RCAR=y
 CONFIG_NETDEVICES=y
 CONFIG_HIX5HD2_GMAC=y
 CONFIG_SUN4I_EMAC=y
@@ -167,14 +182,17 @@ CONFIG_MV643XX_ETH=y
 CONFIG_MVNETA=y
 CONFIG_KS8851=y
 CONFIG_R8169=y
+CONFIG_SH_ETH=y
 CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=y
 CONFIG_TI_CPSW=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_AT803X_PHY=y
 CONFIG_MARVELL_PHY=y
+CONFIG_SMSC_PHY=y
 CONFIG_BROADCOM_PHY=y
 CONFIG_ICPLUS_PHY=y
+CONFIG_MICREL_PHY=y
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
@@ -192,15 +210,18 @@ CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_ST1232=m
 CONFIG_TOUCHSCREEN_STMPE=y
 CONFIG_TOUCHSCREEN_SUN4I=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 CONFIG_INPUT_AXP20X_PEK=y
+CONFIG_INPUT_ADXL34X=m
 CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_EM=y
 CONFIG_SERIAL_8250_MT6577=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -213,6 +234,9 @@ CONFIG_SERIAL_SIRFSOC_CONSOLE=y
 CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=20
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_VT8500=y
@@ -233,19 +257,26 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_CADENCE=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_GPIO=m
 CONFIG_I2C_EXYNOS5=y
 CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_RIIC=y
 CONFIG_I2C_S3C2410=y
+CONFIG_I2C_SH_MOBILE=y
 CONFIG_I2C_SIRF=y
-CONFIG_I2C_TEGRA=y
 CONFIG_I2C_ST=y
-CONFIG_SPI=y
+CONFIG_I2C_TEGRA=y
 CONFIG_I2C_XILINX=y
-CONFIG_SPI_DAVINCI=y
+CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
 CONFIG_SPI_CADENCE=y
+CONFIG_SPI_DAVINCI=y
 CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_ORION=y
 CONFIG_SPI_PL022=y
+CONFIG_SPI_RSPI=y
+CONFIG_SPI_SH_MSIOF=m
+CONFIG_SPI_SH_HSPI=y
 CONFIG_SPI_SIRF=y
 CONFIG_SPI_SUN4I=y
 CONFIG_SPI_SUN6I=y
@@ -259,12 +290,15 @@ CONFIG_PINCTRL_PALMAS=y
 CONFIG_PINCTRL_APQ8084=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_DAVINCI=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_EM=y
+CONFIG_GPIO_RCAR=y
 CONFIG_GPIO_XILINX=y
 CONFIG_GPIO_ZYNQ=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCF857X=y
 CONFIG_GPIO_TWL4030=y
 CONFIG_GPIO_PALMAS=y
 CONFIG_GPIO_SYSCON=y
@@ -276,10 +310,12 @@ CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_POWER_RESET_KEYSTONE=y
 CONFIG_POWER_RESET_SUN6I=y
+CONFIG_POWER_RESET_RMOBILE=y
 CONFIG_SENSORS_LM90=y
 CONFIG_SENSORS_LM95245=y
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
+CONFIG_RCAR_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
 CONFIG_DAVINCI_WATCHDOG
 CONFIG_ST_THERMAL_SYSCFG=y
@@ -290,6 +326,7 @@ CONFIG_ARM_SP805_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
 CONFIG_MESON_WATCHDOG=y
+CONFIG_MFD_AS3711=y
 CONFIG_MFD_AS3722=y
 CONFIG_MFD_BCM590XX=y
 CONFIG_MFD_AXP20X=y
@@ -304,13 +341,16 @@ CONFIG_MFD_TPS65090=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR_AB8500=y
+CONFIG_REGULATOR_AS3711=y
 CONFIG_REGULATOR_AS3722=y
 CONFIG_REGULATOR_AXP20X=y
 CONFIG_REGULATOR_BCM590XX=y
+CONFIG_REGULATOR_DA9210=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_MFD_SYSCON=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_MAX8973=y
 CONFIG_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_PALMAS=y
 CONFIG_REGULATOR_S2MPS11=y
@@ -324,18 +364,32 @@ CONFIG_REGULATOR_TWL4030=y
 CONFIG_REGULATOR_VEXPRESS=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=y
 CONFIG_USB_GSPCA=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=m
+CONFIG_SOC_CAMERA_PLATFORM=m
+CONFIG_VIDEO_RCAR_VIN=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_RENESAS_VSP1=m
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_VIDEO_ADV7180=m
 CONFIG_DRM=y
+CONFIG_DRM_RCAR_DU=m
 CONFIG_DRM_TEGRA=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FB_WM8505=y
+CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FB_SIMPLE=y
+CONFIG_FB_SH_MOBILE_MERAM=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_AS3711=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_SOUND=y
@@ -343,6 +397,8 @@ CONFIG_SND=y
 CONFIG_SND_DYNAMIC_MINORS=y
 CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_SOC=y
+CONFIG_SND_SOC_SH4_FSI=m
+CONFIG_SND_SOC_RCAR=m
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_RT5640=y
 CONFIG_SND_SOC_TEGRA_WM8753=y
@@ -350,6 +406,8 @@ CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
 CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_SND_SOC_TEGRA_MAX98090=y
+CONFIG_SND_SOC_AK4642=m
+CONFIG_SND_SOC_WM8978=m
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_MVEBU=y
@@ -362,6 +420,8 @@ CONFIG_USB_ISP1760_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_STI=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_RENESAS_USBHS=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_CHIPIDEA=y
@@ -374,6 +434,10 @@ CONFIG_SAMSUNG_USB3PHY=y
 CONFIG_USB_GPIO_VBUS=y
 CONFIG_USB_ISP1301=y
 CONFIG_USB_MXS_PHY=y
+CONFIG_USB_RCAR_PHY=m
+CONFIG_USB_RCAR_GEN2_PHY=m
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=m
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_ARMMMCI=y
@@ -392,12 +456,14 @@ CONFIG_MMC_SDHCI_ST=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_MVSDIO=y
-CONFIG_MMC_SUNXI=y
+CONFIG_MMC_SDHI=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_MMC_SUNXI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -421,10 +487,12 @@ CONFIG_RTC_DRV_AS3722=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_RS5C372=m
 CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_DRV_TPS6586X=y
 CONFIG_RTC_DRV_TPS65910=y
+CONFIG_RTC_DRV_S35390A=m
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RTC_DRV_VT8500=y
@@ -436,6 +504,9 @@ CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
 CONFIG_MV_XOR=y
 CONFIG_TEGRA20_APB_DMA=y
+CONFIG_SH_DMAE=y
+CONFIG_RCAR_AUDMAC_PP=m
+CONFIG_RCAR_DMAC=y
 CONFIG_STE_DMA40=y
 CONFIG_SIRF_DMA=y
 CONFIG_TI_EDMA=y
@@ -468,6 +539,7 @@ CONFIG_IIO=y
 CONFIG_XILINX_XADC=y
 CONFIG_AK8975=y
 CONFIG_PWM=y
+CONFIG_PWM_RENESAS_TPU=y
 CONFIG_PWM_TEGRA=y
 CONFIG_PWM_VT8500=y
 CONFIG_PHY_HIX5HD2_SATA=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index b7386524c356..a097cffa1231 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -114,6 +114,7 @@ CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC_BCH=y
 CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_OMAP_BCH=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_OMAP2=y
@@ -248,6 +249,7 @@ CONFIG_TWL6040_CORE=y
 CONFIG_REGULATOR_PALMAS=y
 CONFIG_REGULATOR_PBIAS=y
 CONFIG_REGULATOR_TI_ABB=y
+CONFIG_REGULATOR_TPS62360=m
 CONFIG_REGULATOR_TPS65023=y
 CONFIG_REGULATOR_TPS6507X=y
 CONFIG_REGULATOR_TPS65217=y
@@ -374,7 +376,7 @@ CONFIG_PWM_TIEHRPWM=m
 CONFIG_PWM_TWL=m
 CONFIG_PWM_TWL_LED=m
 CONFIG_OMAP_USB2=m
-CONFIG_TI_PIPE3=m
+CONFIG_TI_PIPE3=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/mach-asm9260/Kconfig b/arch/arm/mach-asm9260/Kconfig
index 8423be76080e..52241207a82a 100644
--- a/arch/arm/mach-asm9260/Kconfig
+++ b/arch/arm/mach-asm9260/Kconfig
@@ -2,5 +2,7 @@ config MACH_ASM9260
         bool "Alphascale ASM9260"
         depends on ARCH_MULTI_V5
         select CPU_ARM926T
+        select ASM9260_TIMER
+        select GENERIC_CLOCKEVENTS
         help
           Support for Alphascale ASM9260 based platform.
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8627e04e1e6..3a3d3e9d7bfd 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -21,6 +21,7 @@ config MXC_AVIC
 
 config MXC_DEBUG_BOARD
         bool "Enable MXC debug board(for 3-stack)"
+        depends on MACH_MX27_3DS || MACH_MX31_3DS || MACH_MX35_3DS
         help
           The debug board is an integral part of the MXC 3-stack(PDK)
           platforms, it can be attached or removed from the peripheral
@@ -50,6 +51,7 @@ config HAVE_IMX_ANATOP
 
 config HAVE_IMX_GPC
         bool
+        select PM_GENERIC_DOMAINS if PM
 
 config HAVE_IMX_MMDC
         bool
@@ -77,13 +79,6 @@ config SOC_IMX21
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
 
-config SOC_IMX25
-        bool
-        select ARCH_MXC_IOMUX_V3
-        select CPU_ARM926T
-        select MXC_AVIC
-        select PINCTRL_IMX25
-
 config SOC_IMX27
         bool
         select CPU_ARM926T
@@ -149,62 +144,6 @@ config MACH_MX21ADS
           Include support for MX21ADS platform. This includes specific
           configurations for the board and its peripherals.
 
-comment "MX25 platforms:"
-
-config MACH_MX25_3DS
-        bool "Support MX25PDK (3DS) Platform"
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMXDI_RTC
-        select IMX_HAVE_PLATFORM_IMX_FB
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select SOC_IMX25
-
-config MACH_EUKREA_CPUIMX25SD
-        bool "Support Eukrea CPUIMX25 Platform"
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMXDI_RTC
-        select IMX_HAVE_PLATFORM_IMX_FB
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select USB_ULPI_VIEWPORT if USB_ULPI
-        select SOC_IMX25
-
-choice
-        prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX25SD
-        default MACH_EUKREA_MBIMXSD25_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD25_BASEBOARD
-        bool "Eukrea MBIMXSD development board"
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMXSD evaluation board.
-
-endchoice
-
-config MACH_IMX25_DT
-        bool "Support i.MX25 platforms from device tree"
-        select SOC_IMX25
-        help
-          Include support for Freescale i.MX25 based platforms
-          using the device tree for discovery
-
 comment "MX27 platforms:"
 
 config MACH_MX27ADS
@@ -557,6 +496,20 @@ config MACH_VPR200
 
 endif
 
+if ARCH_MULTI_V5
+
+comment "Device tree only"
+
+config SOC_IMX25
+        bool "i.MX25 support"
+        select ARCH_MXC_IOMUX_V3
+        select CPU_ARM926T
+        select MXC_AVIC
+        select PINCTRL_IMX25
+        help
+          This enables support for Freescale i.MX25 processor
+endif
+
 if ARCH_MULTI_V7
 
 comment "Device tree only"
@@ -631,12 +584,14 @@ config SOC_IMX6SX
 
 config SOC_VF610
         bool "Vybrid Family VF610 support"
+        select IRQ_DOMAIN_HIERARCHY
         select ARM_GIC
         select PINCTRL_VF610
         select PL310_ERRATA_769419 if CACHE_L2X0
+        select SMP_ON_UP if SMP
 
         help
-          This enable support for Freescale Vybrid VF610 processor.
+          This enables support for Freescale Vybrid VF610 processor.
 
 choice
         prompt "Clocksource for scheduler clock"
@@ -666,7 +621,7 @@ config SOC_LS1021A
         select ZONE_DMA if ARM_LPAE
 
         help
-          This enable support for Freescale LS1021A processor.
+          This enables support for Freescale LS1021A processor.
 
 endif
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8d1b10180908..3244cf1d2773 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -3,7 +3,7 @@ obj-y := time.o cpu.o system.o irq-common.o
 obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
 
-obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
+obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o
 
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
@@ -48,12 +48,6 @@ obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
 # i.MX21 based machines
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
 
-# i.MX25 based machines
-obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
-obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
-
 # i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 59c0c8558c6b..9c2633a9de9f 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -30,7 +30,6 @@
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
-#include "mx25.h"
 
 #define CCM_MPCTL       0x00
 #define CCM_UPCTL       0x04
@@ -239,80 +238,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
         return 0;
 }
 
-int __init mx25_clocks_init(void)
-{
-        void __iomem *ccm;
-
-        ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
-
-        __mx25_clocks_init(24000000, ccm);
-
-        clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        /* i.mx25 has the i.mx21 type uart */
-        clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
-        clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
-        /* i.mx25 has the i.mx35 type cspi */
-        clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
-        clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
-        clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
-        clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
-        clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
-        clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
-        clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
-        clk_register_clkdev(clk[dummy], "audmux", NULL);
-        clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
-        clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
-        /* i.mx25 has the i.mx35 type sdma */
-        clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
-        clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
-        clk_register_clkdev(clk[iim_ipg], "iim", NULL);
-
-        mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
-
-        return 0;
-}
-
 static void __init mx25_clocks_init_dt(struct device_node *np)
 {
         struct device_node *refnp;
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index d04a430607b8..469a150bf98f 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_asrc;
 static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
+static unsigned int share_count_mipi_core_cfg;
 
 static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
@@ -246,6 +247,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
         clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
         clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
+        clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
         if (cpu_is_imx6dl()) {
                 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
                 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
@@ -400,7 +402,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
         clk[IMX6QDL_CLK_GPU3D_CORE]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
         clk[IMX6QDL_CLK_HDMI_IAHB]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
-        clk[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
+        clk[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_gate2("hdmi_isfr",     "video_27m",         base + 0x70, 4);
         clk[IMX6QDL_CLK_I2C1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
         clk[IMX6QDL_CLK_I2C2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
         clk[IMX6QDL_CLK_I2C3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
@@ -415,7 +417,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
         clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
         clk[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
-        clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
+        clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf",       base + 0x74, 16, &share_count_mipi_core_cfg);
+        clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
+        clk[IMX6QDL_CLK_MIPI_IPG]     = imx_clk_gate2_shared("mipi_ipg", "ipg",             base + 0x74, 16, &share_count_mipi_core_cfg);
         if (cpu_is_imx6dl())
                 /*
                  * The multiplexer and divider of the imx6q clock gpu2d get
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1028b6c505c4..0f04e30b726d 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -23,13 +23,11 @@ struct of_device_id;
 
 void mx1_map_io(void);
 void mx21_map_io(void);
-void mx25_map_io(void);
 void mx27_map_io(void);
 void mx31_map_io(void);
 void mx35_map_io(void);
 void imx1_init_early(void);
 void imx21_init_early(void);
-void imx25_init_early(void);
 void imx27_init_early(void);
 void imx31_init_early(void);
 void imx35_init_early(void);
@@ -37,13 +35,11 @@ void mxc_init_irq(void __iomem *);
 void tzic_init_irq(void);
 void mx1_init_irq(void);
 void mx21_init_irq(void);
-void mx25_init_irq(void);
 void mx27_init_irq(void);
 void mx31_init_irq(void);
 void mx35_init_irq(void);
 void imx1_soc_init(void);
 void imx21_soc_init(void);
-void imx25_soc_init(void);
 void imx27_soc_init(void);
 void imx31_soc_init(void);
 void imx35_soc_init(void);
@@ -51,7 +47,6 @@ void epit_timer_init(void __iomem *base, int irq);
 void mxc_timer_init(void __iomem *, int);
 int mx1_clocks_init(unsigned long fref);
 int mx21_clocks_init(unsigned long lref, unsigned long fref);
-int mx25_clocks_init(void);
 int mx27_clocks_init(unsigned long fref);
 int mx31_clocks_init(unsigned long fref);
 int mx35_clocks_init(void);
@@ -71,6 +66,7 @@ unsigned int imx_get_soc_revision(void);
 void imx_init_revision_from_anatop(void);
 struct device *imx_soc_device_init(void);
 void imx6_enable_rbc(bool enable);
+void imx_gpc_check_dt(void);
 void imx_gpc_set_arm_power_in_lpm(bool power_off);
 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
@@ -106,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 #endif
 void imx_src_init(void);
-void imx_gpc_init(void);
 void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
index 96ec64b5ff7d..d0ad67e802d3 100644
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -11,6 +11,8 @@
  */
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "iim.h"
 #include "hardware.h"
@@ -20,8 +22,15 @@ static int mx25_cpu_rev = -1;
 static int mx25_read_cpu_rev(void)
 {
         u32 rev;
+        void __iomem *iim_base;
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
+        iim_base = of_iomap(np, 0);
+        BUG_ON(!iim_base);
+        rev = readl(iim_base + MXC_IIMSREV);
+        iounmap(iim_base);
 
-        rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
         switch (rev) {
         case 0x00:
                 return IMX_CHIP_REVISION_1_0;
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
deleted file mode 100644
index 61a114cddc39..000000000000
--- a/arch/arm/mach-imx/devices-imx25.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_fec_data imx25_fec_data;
-#define imx25_add_fec(pdata)    \
-        imx_add_fec(&imx25_fec_data, pdata)
-
-extern const struct imx_flexcan_data imx25_flexcan_data[];
-#define imx25_add_flexcan(id)   \
-        imx_add_flexcan(&imx25_flexcan_data[id])
-#define imx25_add_flexcan0()            imx25_add_flexcan(0)
-#define imx25_add_flexcan1()            imx25_add_flexcan(1)
-
-extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
-#define imx25_add_fsl_usb2_udc(pdata)   \
-        imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
-
-extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
-#define imx25_add_imxdi_rtc()   \
-        imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
-
-extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
-#define imx25_add_imx2_wdt()    \
-        imx_add_imx2_wdt(&imx25_imx2_wdt_data)
-
-extern const struct imx_imx_fb_data imx25_imx_fb_data;
-#define imx25_add_imx_fb(pdata) \
-        imx_add_imx_fb(&imx25_imx_fb_data, pdata)
-
-extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
-#define imx25_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
-#define imx25_add_imx_i2c0(pdata)       imx25_add_imx_i2c(0, pdata)
-#define imx25_add_imx_i2c1(pdata)       imx25_add_imx_i2c(1, pdata)
-#define imx25_add_imx_i2c2(pdata)       imx25_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
-#define imx25_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
-#define imx25_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
-#define imx25_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
-#define imx25_add_imx_uart0(pdata)      imx25_add_imx_uart(0, pdata)
-#define imx25_add_imx_uart1(pdata)      imx25_add_imx_uart(1, pdata)
-#define imx25_add_imx_uart2(pdata)      imx25_add_imx_uart(2, pdata)
-#define imx25_add_imx_uart3(pdata)      imx25_add_imx_uart(3, pdata)
-#define imx25_add_imx_uart4(pdata)      imx25_add_imx_uart(4, pdata)
-
-extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
-#define imx25_add_mx2_camera(pdata)     \
-        imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
-
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
-#define imx25_add_mxc_ehci_otg(pdata)   \
-        imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
-#define imx25_add_mxc_ehci_hs(pdata)    \
-        imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
-
-extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
-#define imx25_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
-#define imx25_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx25_cspi_data[];
-#define imx25_add_spi_imx(id, pdata)    \
-        imx_add_spi_imx(&imx25_cspi_data[id], pdata)
-#define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
-#define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
-#define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 1d2cc1805f3e..3a552989248e 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -21,9 +21,6 @@ config IMX_HAVE_PLATFORM_IMX27_CODA
 config IMX_HAVE_PLATFORM_IMX2_WDT
         bool
 
-config IMX_HAVE_PLATFORM_IMXDI_RTC
-        bool
-
 config IMX_HAVE_PLATFORM_IMX_FB
         bool
 
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 8fdb12b4ca7e..e5cf587bc1a0 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -8,7 +8,6 @@ obj-y += platform-gpio-mxc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
 obj-y += platform-imx-dma.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index d86f9250b4ee..b403a4fe2892 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -19,11 +19,6 @@
                 .irq = soc ## _INT_FEC,                                 \
         }
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_fec_data imx25_fec_data __initconst =
-        imx_fec_data_entry_single(MX25, "imx25-fec");
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_fec_data imx27_fec_data __initconst =
         imx_fec_data_entry_single(MX27, "imx27-fec");
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 23b0061347cb..25e1de6f3a47 100644
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -18,11 +18,6 @@
                 .irq = soc ## _INT_USB_OTG,                             \
         }
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
         imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index 25a47c616b2d..7df6328306f9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -29,11 +29,6 @@ const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
         imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
         imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 644ac2689882..ae9791522fc8 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -31,16 +31,6 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
         imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
-#define imx25_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K)
-        imx25_imx_i2c_data_entry(0, 1),
-        imx25_imx_i2c_data_entry(1, 2),
-        imx25_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
 #define imx27_imx_i2c_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index f42200b7aca9..479e4d70dbf9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -21,11 +21,6 @@ const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
         imx_imx_keypad_data_entry_single(MX21, SZ_16);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX25, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
         imx_imx_keypad_data_entry_single(MX27, SZ_16);
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index 1c7c721ebff1..6f0e94eb29ee 100644
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -30,15 +30,6 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
-#define imx25_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
-        imx25_imx_ssi_data_entry(0, 1),
-        imx25_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
 #define imx27_imx_ssi_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index 8c01836bc1d4..6962cff4a950 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -47,18 +47,6 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
 };
 #endif
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
-#define imx25_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_imx_uart_data_entry(0, 1),
-        imx25_imx_uart_data_entry(1, 2),
-        imx25_imx_uart_data_entry(2, 3),
-        imx25_imx_uart_data_entry(3, 4),
-        imx25_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
 #define imx27_imx_uart_data_entry(_id, _hwid)                           \
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index 54f63bc25ca4..8c134c8d7500 100644
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -25,11 +25,6 @@ const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
         imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
-        imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
         imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
deleted file mode 100644
index 5bb490d556ea..000000000000
--- a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imxdi_rtc_data_entry_single(soc)                            \
-        {                                                               \
-                .iobase = soc ## _DRYICE_BASE_ADDR,                     \
-                .irq = soc ## _INT_DRYICE,                              \
-        }
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
-        imx_imxdi_rtc_data_entry_single(MX25);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-struct platform_device *__init imx_add_imxdi_rtc(
-                const struct imx_imxdi_rtc_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("imxdi_rtc", 0,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
index b53e1f348f51..4c377c33242c 100644
--- a/arch/arm/mach-imx/devices/platform-mx2-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-camera.c
@@ -27,11 +27,6 @@
                 .irqemmaprp = soc ## _INT_EMMAPRP,                      \
         }
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
-        imx_mx2_camera_data_entry_single(MX25, "imx25-camera");
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
         imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
index 296353662ff0..4537abd2a8f2 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
@@ -18,13 +18,6 @@
                 .irq = soc ## _INT_USB_ ## hs,                          \
         }
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
-const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX25, 1, HS);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
         imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index fa618a34f462..676df4920c7b 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -34,11 +34,6 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index aca825d74c48..5e9707b47f92 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -39,17 +39,6 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
 };
 #endif
 
-#ifdef CONFIG_SOC_IMX25
-/* i.mx25 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
-#define imx25_cspi_data_entry(_id, _hwid)                               \
-        imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K)
-        imx25_cspi_data_entry(0, 1),
-        imx25_cspi_data_entry(1, 2),
-        imx25_cspi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
 #define imx27_cspi_data_entry(_id, _hwid)                               \
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
deleted file mode 100644
index 42a5a3d14c5f..000000000000
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-
-#include "ehci.h"
-#include "hardware.h"
-
-#define USBCTRL_OTGBASE_OFFSET  0x600
-
-#define MX25_OTG_SIC_SHIFT      29
-#define MX25_OTG_SIC_MASK       (0x3 << MX25_OTG_SIC_SHIFT)
-#define MX25_OTG_PM_BIT         (1 << 24)
-#define MX25_OTG_PP_BIT         (1 << 11)
-#define MX25_OTG_OCPOL_BIT      (1 << 3)
-
-#define MX25_H1_SIC_SHIFT       21
-#define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
-#define MX25_H1_PP_BIT          (1 << 18)
-#define MX25_H1_PM_BIT          (1 << 16)
-#define MX25_H1_IPPUE_UP_BIT    (1 << 7)
-#define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
-#define MX25_H1_TLL_BIT         (1 << 5)
-#define MX25_H1_USBTE_BIT       (1 << 4)
-#define MX25_H1_OCPOL_BIT       (1 << 2)
-
-int mx25_initialize_usb_hw(int port, unsigned int flags)
-{
-        unsigned int v;
-
-        v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
-        switch (port) {
-        case 0: /* OTG port */
-                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
-                        MX25_OTG_OCPOL_BIT);
-                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
-
-                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                        v |= MX25_OTG_PM_BIT;
-
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX25_OTG_PP_BIT;
-
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX25_OTG_OCPOL_BIT;
-
-                break;
-        case 1: /* H1 port */
-                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
-                        MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
-                        MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
-                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
-
-                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                        v |= MX25_H1_PM_BIT;
-
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX25_H1_PP_BIT;
-
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX25_H1_OCPOL_BIT;
-
-                if (!(flags & MXC_EHCI_TTL_ENABLED))
-                        v |= MX25_H1_TLL_BIT;
-
-                if (flags & MXC_EHCI_INTERNAL_PHY)
-                        v |= MX25_H1_USBTE_BIT;
-
-                if (flags & MXC_EHCI_IPPUE_DOWN)
-                        v |= MX25_H1_IPPUE_DOWN_BIT;
-
-                if (flags & MXC_EHCI_IPPUE_UP)
-                        v |= MX25_H1_IPPUE_UP_BIT;
-
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
-        return 0;
-}
-
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
deleted file mode 100644
index e77cc3af6db2..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/spi/spi.h>
-#include <video/platform_lcd.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "devices-imx25.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
-
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
-        /* LCD */
-        MX25_PAD_LD0__LD0,
-        MX25_PAD_LD1__LD1,
-        MX25_PAD_LD2__LD2,
-        MX25_PAD_LD3__LD3,
-        MX25_PAD_LD4__LD4,
-        MX25_PAD_LD5__LD5,
-        MX25_PAD_LD6__LD6,
-        MX25_PAD_LD7__LD7,
-        MX25_PAD_LD8__LD8,
-        MX25_PAD_LD9__LD9,
-        MX25_PAD_LD10__LD10,
-        MX25_PAD_LD11__LD11,
-        MX25_PAD_LD12__LD12,
-        MX25_PAD_LD13__LD13,
-        MX25_PAD_LD14__LD14,
-        MX25_PAD_LD15__LD15,
-        MX25_PAD_GPIO_E__LD16,
-        MX25_PAD_GPIO_F__LD17,
-        MX25_PAD_HSYNC__HSYNC,
-        MX25_PAD_VSYNC__VSYNC,
-        MX25_PAD_LSCLK__LSCLK,
-        MX25_PAD_OE_ACD__OE_ACD,
-        MX25_PAD_CONTRAST__CONTRAST,
-        /* LCD_PWR */
-        MX25_PAD_PWM__GPIO_1_26,
-        /* LED */
-        MX25_PAD_POWER_FAIL__GPIO_3_19,
-        /* SWITCH */
-        MX25_PAD_VSTBY_ACK__GPIO_3_18,
-        /* UART2 */
-        MX25_PAD_UART2_RTS__UART2_RTS,
-        MX25_PAD_UART2_CTS__UART2_CTS,
-        MX25_PAD_UART2_TXD__UART2_TXD,
-        MX25_PAD_UART2_RXD__UART2_RXD,
-        /* SD1 */
-        MX25_PAD_SD1_CMD__SD1_CMD,
-        MX25_PAD_SD1_CLK__SD1_CLK,
-        MX25_PAD_SD1_DATA0__SD1_DATA0,
-        MX25_PAD_SD1_DATA1__SD1_DATA1,
-        MX25_PAD_SD1_DATA2__SD1_DATA2,
-        MX25_PAD_SD1_DATA3__SD1_DATA3,
-        /* SD1 CD */
-        MX25_PAD_DE_B__GPIO_2_20,
-        /* I2S */
-        MX25_PAD_KPP_COL3__AUD5_TXFS,
-        MX25_PAD_KPP_COL2__AUD5_TXC,
-        MX25_PAD_KPP_COL1__AUD5_RXD,
-        MX25_PAD_KPP_COL0__AUD5_TXD,
-        /* CAN */
-        MX25_PAD_GPIO_D__CAN2_RX,
-        MX25_PAD_GPIO_C__CAN2_TX,
-        /* SPI1 */
-        MX25_PAD_CSPI1_MOSI__CSPI1_MOSI,
-        MX25_PAD_CSPI1_MISO__CSPI1_MISO,
-        MX25_PAD_CSPI1_SS0__GPIO_1_16,
-        MX25_PAD_CSPI1_SS1__GPIO_1_17,
-        MX25_PAD_CSPI1_SCLK__CSPI1_SCLK,
-        MX25_PAD_CSPI1_RDY__GPIO_2_22,
-};
-
-#define GPIO_LED1               IMX_GPIO_NR(3, 19)
-#define GPIO_SWITCH1    IMX_GPIO_NR(3, 18)
-#define GPIO_SD1CD              IMX_GPIO_NR(2, 20)
-#define GPIO_LCDPWR             IMX_GPIO_NR(1, 26)
-#define GPIO_SPI1_SS0   IMX_GPIO_NR(1, 16)
-#define GPIO_SPI1_SS1   IMX_GPIO_NR(1, 17)
-#define GPIO_SPI1_IRQ   IMX_GPIO_NR(2, 22)
-
-static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
-        {
-                .mode   = {
-                        .name           = "CMO-QVGA",
-                        .refresh        = 60,
-                        .xres           = 320,
-                        .yres           = 240,
-                        .pixclock       = KHZ2PICOS(6500),
-                        .left_margin    = 30,
-                        .right_margin   = 38,
-                        .upper_margin   = 20,
-                        .lower_margin   = 3,
-                        .hsync_len      = 15,
-                        .vsync_len      = 4,
-                },
-                .bpp    = 16,
-                .pcr    = 0xCAD08B80,
-        }, {
-                .mode = {
-                        .name           = "DVI-VGA",
-                        .refresh        = 60,
-                        .xres           = 640,
-                        .yres           = 480,
-                        .pixclock       = 32000,
-                        .hsync_len      = 7,
-                        .left_margin    = 100,
-                        .right_margin   = 100,
-                        .vsync_len      = 7,
-                        .upper_margin   = 7,
-                        .lower_margin   = 100,
-                },
-                .pcr            = 0xFA208B80,
-                .bpp            = 16,
-        }, {
-                .mode = {
-                        .name           = "DVI-SVGA",
-                        .refresh        = 60,
-                        .xres           = 800,
-                        .yres           = 600,
-                        .pixclock       = 25000,
-                        .hsync_len      = 7,
-                        .left_margin    = 75,
-                        .right_margin   = 75,
-                        .vsync_len      = 7,
-                        .upper_margin   = 7,
-                        .lower_margin   = 75,
-                },
-                .pcr            = 0xFA208B80,
-                .bpp            = 16,
-        },
-};
-
-static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
-        .mode           = eukrea_mximxsd_modes,
-        .num_modes      = ARRAY_SIZE(eukrea_mximxsd_modes),
-        .pwmr           = 0x00A903FF,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00040060,
-};
-
-static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power)
-                gpio_direction_output(GPIO_LCDPWR, 1);
-        else
-                gpio_direction_output(GPIO_LCDPWR, 0);
-}
-
-static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
-        .set_power              = eukrea_mbimxsd_lcd_power_set,
-};
-
-static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
-        .name                   = "platform-lcd",
-        .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
-};
-
-static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
-        {
-                .name                   = "led1",
-                .default_trigger        = "heartbeat",
-                .active_low             = 1,
-                .gpio                   = GPIO_LED1,
-        },
-};
-
-static const struct gpio_led_platform_data
-                eukrea_mbimxsd_led_info __initconst = {
-        .leds           = eukrea_mbimxsd_leds,
-        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
-};
-
-static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
-        {
-                .gpio           = GPIO_SWITCH1,
-                .code           = BTN_0,
-                .desc           = "BP1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-};
-
-static const struct gpio_keys_platform_data
-                eukrea_mbimxsd_button_data __initconst = {
-        .buttons        = eukrea_mbimxsd_gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
-};
-
-static struct platform_device *platform_devices[] __initdata = {
-        &eukrea_mbimxsd_lcd_powerdev,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-};
-
-static const
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
-        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
-};
-
-static struct esdhc_platform_data sd1_pdata = {
-        .cd_gpio = GPIO_SD1CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_NONE,
-};
-
-static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .mode = SPI_MODE_0,
-        },
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-        },
-};
-
-static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
-
-static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
-        .chipselect     = eukrea_mbimxsd25_spi_cs,
-        .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
-};
-
-/*
- * system init for baseboard usage. Will be called by cpuimx25 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimxsd25_baseboard_init(void)
-{
-        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
-                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
-                printk(KERN_ERR "error setting mbimxsd pads !\n");
-
-        imx25_add_imx_uart1(&uart_pdata);
-        imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
-        imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
-
-        imx25_add_flexcan1();
-        imx25_add_sdhci_esdhc_imx(0, &sd1_pdata);
-
-        gpio_request(GPIO_LED1, "LED1");
-        gpio_direction_output(GPIO_LED1, 1);
-        gpio_free(GPIO_LED1);
-
-        gpio_request(GPIO_SWITCH1, "SWITCH1");
-        gpio_direction_input(GPIO_SWITCH1);
-        gpio_free(GPIO_SWITCH1);
-
-        gpio_request(GPIO_LCDPWR, "LCDPWR");
-        gpio_direction_output(GPIO_LCDPWR, 1);
-
-        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
-                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
-
-        gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
-        gpio_direction_input(GPIO_SPI1_IRQ);
-        gpio_free(GPIO_SPI1_IRQ);
-        imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data);
-        spi_register_board_info(eukrea_mbimxsd25_spi_board_info,
-                ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info));
-
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
-        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
-}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 14d6c8249b76..6edc940e0865 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -100,7 +100,7 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .num_modes      = ARRAY_SIZE(fb_modedb),
 };
 
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
+static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
         /* LCD */
         MX35_PAD_LD0__IPU_DISPB_DAT_0,
         MX35_PAD_LD1__IPU_DISPB_DAT_1,
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 745caa18ab2c..4d60005e9277 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -10,15 +10,25 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regulator/consumer.h>
 #include <linux/irqchip/arm-gic.h>
 #include "common.h"
+#include "hardware.h"
 
+#define GPC_CNTR                0x000
 #define GPC_IMR1                0x008
+#define GPC_PGC_GPU_PDN         0x260
+#define GPC_PGC_GPU_PUPSCR      0x264
+#define GPC_PGC_GPU_PDNSCR      0x268
 #define GPC_PGC_CPU_PDN         0x2a0
 #define GPC_PGC_CPU_PUPSCR      0x2a4
 #define GPC_PGC_CPU_PDNSCR      0x2a8
@@ -26,6 +36,19 @@
 #define GPC_PGC_SW_SHIFT        0x0
 
 #define IMR_NUM                 4
+#define GPC_MAX_IRQS            (IMR_NUM * 32)
+
+#define GPU_VPU_PUP_REQ         BIT(1)
+#define GPU_VPU_PDN_REQ         BIT(0)
+
+#define GPC_CLK_MAX             6
+
+struct pu_domain {
+        struct generic_pm_domain base;
+        struct regulator *reg;
+        struct clk *clk[GPC_CLK_MAX];
+        int num_clks;
+};
 
 static void __iomem *gpc_base;
 static u32 gpc_wake_irqs[IMR_NUM];
@@ -77,17 +100,17 @@ void imx_gpc_post_resume(void)
 
 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        unsigned int idx = d->hwirq / 32 - 1;
+        unsigned int idx = d->hwirq / 32;
         u32 mask;
 
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return -EINVAL;
-
         mask = 1 << d->hwirq % 32;
         gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
                                   gpc_wake_irqs[idx] & ~mask;
 
+        /*
+         * Do *not* call into the parent, as the GIC doesn't have any
+         * wake-up facility...
+         */
         return 0;
 }
 
@@ -117,7 +140,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
         void __iomem *reg;
         u32 val;
 
-        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
         val = readl_relaxed(reg);
         val &= ~(1 << hwirq % 32);
         writel_relaxed(val, reg);
@@ -128,7 +151,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
         void __iomem *reg;
         u32 val;
 
-        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
         val = readl_relaxed(reg);
         val |= 1 << (hwirq % 32);
         writel_relaxed(val, reg);
@@ -136,37 +159,319 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
 
 static void imx_gpc_irq_unmask(struct irq_data *d)
 {
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return;
-
         imx_gpc_hwirq_unmask(d->hwirq);
+        irq_chip_unmask_parent(d);
 }
 
 static void imx_gpc_irq_mask(struct irq_data *d)
 {
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return;
-
         imx_gpc_hwirq_mask(d->hwirq);
+        irq_chip_mask_parent(d);
 }
 
-void __init imx_gpc_init(void)
+static struct irq_chip imx_gpc_chip = {
+        .name                   = "GPC",
+        .irq_eoi                = irq_chip_eoi_parent,
+        .irq_mask               = imx_gpc_irq_mask,
+        .irq_unmask             = imx_gpc_irq_unmask,
+        .irq_retrigger          = irq_chip_retrigger_hierarchy,
+        .irq_set_wake           = imx_gpc_irq_set_wake,
+#ifdef CONFIG_SMP
+        .irq_set_affinity       = irq_chip_set_affinity_parent,
+#endif
+};
+
+static int imx_gpc_domain_xlate(struct irq_domain *domain,
+                                struct device_node *controller,
+                                const u32 *intspec,
+                                unsigned int intsize,
+                                unsigned long *out_hwirq,
+                                unsigned int *out_type)
 {
-        struct device_node *np;
+        if (domain->of_node != controller)
+                return -EINVAL; /* Shouldn't happen, really... */
+        if (intsize != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (intspec[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+
+        *out_hwirq = intspec[1];
+        *out_type = intspec[2];
+        return 0;
+}
+
+static int imx_gpc_domain_alloc(struct irq_domain *domain,
+                                  unsigned int irq,
+                                  unsigned int nr_irqs, void *data)
+{
+        struct of_phandle_args *args = data;
+        struct of_phandle_args parent_args;
+        irq_hw_number_t hwirq;
         int i;
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
-        gpc_base = of_iomap(np, 0);
-        WARN_ON(!gpc_base);
+        if (args->args_count != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (args->args[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+
+        hwirq = args->args[1];
+        if (hwirq >= GPC_MAX_IRQS)
+                return -EINVAL; /* Can't deal with this */
+
+        for (i = 0; i < nr_irqs; i++)
+                irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
+                                              &imx_gpc_chip, NULL);
+
+        parent_args = *args;
+        parent_args.np = domain->parent->of_node;
+        return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
+}
+
+static struct irq_domain_ops imx_gpc_domain_ops = {
+        .xlate  = imx_gpc_domain_xlate,
+        .alloc  = imx_gpc_domain_alloc,
+        .free   = irq_domain_free_irqs_common,
+};
+
+static int __init imx_gpc_init(struct device_node *node,
+                               struct device_node *parent)
+{
+        struct irq_domain *parent_domain, *domain;
+        int i;
+
+        if (!parent) {
+                pr_err("%s: no parent, giving up\n", node->full_name);
+                return -ENODEV;
+        }
+
+        parent_domain = irq_find_host(parent);
+        if (!parent_domain) {
+                pr_err("%s: unable to obtain parent domain\n", node->full_name);
+                return -ENXIO;
+        }
+
+        gpc_base = of_iomap(node, 0);
+        if (WARN_ON(!gpc_base))
+                return -ENOMEM;
+
+        domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
+                                          node, &imx_gpc_domain_ops,
+                                          NULL);
+        if (!domain) {
+                iounmap(gpc_base);
+                return -ENOMEM;
+        }
 
         /* Initially mask all interrupts */
         for (i = 0; i < IMR_NUM; i++)
                 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
 
-        /* Register GPC as the secondary interrupt controller behind GIC */
-        gic_arch_extn.irq_mask = imx_gpc_irq_mask;
-        gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
-        gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
+        return 0;
+}
+
+/*
+ * We cannot use the IRQCHIP_DECLARE macro that lives in
+ * drivers/irqchip, so we're forced to roll our own. Not very nice.
+ */
+OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
+
+void __init imx_gpc_check_dt(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+        if (WARN_ON(!np ||
+                    !of_find_property(np, "interrupt-controller", NULL)))
+                pr_warn("Outdated DT detected, system is about to crash!!!\n");
+}
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS
+
+static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+        int iso, iso2sw;
+        u32 val;
+
+        /* Read ISO and ISO2SW power down delays */
+        val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
+        iso = val & 0x3f;
+        iso2sw = (val >> 8) & 0x3f;
+
+        /* Gate off PU domain when GPU/VPU when powered down */
+        writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+        /* Request GPC to power down GPU/VPU */
+        val = readl_relaxed(gpc_base + GPC_CNTR);
+        val |= GPU_VPU_PDN_REQ;
+        writel_relaxed(val, gpc_base + GPC_CNTR);
+
+        /* Wait ISO + ISO2SW IPG clock cycles */
+        ndelay((iso + iso2sw) * 1000 / 66);
+}
+
+static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+        struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
+
+        _imx6q_pm_pu_power_off(genpd);
+
+        if (pu->reg)
+                regulator_disable(pu->reg);
+
+        return 0;
+}
+
+static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
+{
+        struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
+        int i, ret, sw, sw2iso;
+        u32 val;
+
+        if (pu->reg)
+                ret = regulator_enable(pu->reg);
+        if (pu->reg && ret) {
+                pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
+                return ret;
+        }
+
+        /* Enable reset clocks for all devices in the PU domain */
+        for (i = 0; i < pu->num_clks; i++)
+                clk_prepare_enable(pu->clk[i]);
+
+        /* Gate off PU domain when GPU/VPU when powered down */
+        writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+        /* Read ISO and ISO2SW power down delays */
+        val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
+        sw = val & 0x3f;
+        sw2iso = (val >> 8) & 0x3f;
+
+        /* Request GPC to power up GPU/VPU */
+        val = readl_relaxed(gpc_base + GPC_CNTR);
+        val |= GPU_VPU_PUP_REQ;
+        writel_relaxed(val, gpc_base + GPC_CNTR);
+
+        /* Wait ISO + ISO2SW IPG clock cycles */
+        ndelay((sw + sw2iso) * 1000 / 66);
+
+        /* Disable reset clocks for all devices in the PU domain */
+        for (i = 0; i < pu->num_clks; i++)
+                clk_disable_unprepare(pu->clk[i]);
+
+        return 0;
+}
+
+static struct generic_pm_domain imx6q_arm_domain = {
+        .name = "ARM",
+};
+
+static struct pu_domain imx6q_pu_domain = {
+        .base = {
+                .name = "PU",
+                .power_off = imx6q_pm_pu_power_off,
+                .power_on = imx6q_pm_pu_power_on,
+                .power_off_latency_ns = 25000,
+                .power_on_latency_ns = 2000000,
+        },
+};
+
+static struct generic_pm_domain imx6sl_display_domain = {
+        .name = "DISPLAY",
+};
+
+static struct generic_pm_domain *imx_gpc_domains[] = {
+        &imx6q_arm_domain,
+        &imx6q_pu_domain.base,
+        &imx6sl_display_domain,
+};
+
+static struct genpd_onecell_data imx_gpc_onecell_data = {
+        .domains = imx_gpc_domains,
+        .num_domains = ARRAY_SIZE(imx_gpc_domains),
+};
+
+static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
+{
+        struct clk *clk;
+        bool is_off;
+        int i;
+
+        imx6q_pu_domain.reg = pu_reg;
+
+        for (i = 0; ; i++) {
+                clk = of_clk_get(dev->of_node, i);
+                if (IS_ERR(clk))
+                        break;
+                if (i >= GPC_CLK_MAX) {
+                        dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
+                        goto clk_err;
+                }
+                imx6q_pu_domain.clk[i] = clk;
+        }
+        imx6q_pu_domain.num_clks = i;
+
+        is_off = IS_ENABLED(CONFIG_PM);
+        if (is_off) {
+                _imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
+        } else {
+                /*
+                 * Enable power if compiled without CONFIG_PM in case the
+                 * bootloader disabled it.
+                 */
+                imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
+        }
+
+        pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
+        return of_genpd_add_provider_onecell(dev->of_node,
+                                             &imx_gpc_onecell_data);
+
+clk_err:
+        while (i--)
+                clk_put(imx6q_pu_domain.clk[i]);
+        return -EINVAL;
+}
+
+#else
+static inline int imx_gpc_genpd_init(struct device *dev, struct regulator *reg)
+{
+        return 0;
+}
+#endif /* CONFIG_PM_GENERIC_DOMAINS */
+
+static int imx_gpc_probe(struct platform_device *pdev)
+{
+        struct regulator *pu_reg;
+        int ret;
+
+        pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
+        if (PTR_ERR(pu_reg) == -ENODEV)
+                pu_reg = NULL;
+        if (IS_ERR(pu_reg)) {
+                ret = PTR_ERR(pu_reg);
+                dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
+                return ret;
+        }
+
+        return imx_gpc_genpd_init(&pdev->dev, pu_reg);
+}
+
+static const struct of_device_id imx_gpc_dt_ids[] = {
+        { .compatible = "fsl,imx6q-gpc" },
+        { .compatible = "fsl,imx6sl-gpc" },
+        { }
+};
+
+static struct platform_driver imx_gpc_driver = {
+        .driver = {
+                .name = "imx-gpc",
+                .owner = THIS_MODULE,
+                .of_match_table = imx_gpc_dt_ids,
+        },
+        .probe = imx_gpc_probe,
+};
+
+static int __init imx_pgc_init(void)
+{
+        return platform_driver_register(&imx_gpc_driver);
 }
+subsys_initcall(imx_pgc_init);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 66b2b564c463..76af2c03c241 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -112,7 +112,6 @@
 #include "mx21.h"
 #include "mx27.h"
 #include "mx1.h"
-#include "mx25.h"
 
 #define imx_map_entry(soc, name, _type) {                               \
         .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
diff --git a/arch/arm/mach-imx/iomux-mx25.h b/arch/arm/mach-imx/iomux-mx25.h
deleted file mode 100644
index be51e838375c..000000000000
--- a/arch/arm/mach-imx/iomux-mx25.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * arch/arm/plat-mxc/include/mach/iomux-mx25.h
- *
- * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
- *
- * based on arch/arm/mach-mx25/mx25_pins.h
- *    Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * and
- * arch/arm/plat-mxc/include/mach/iomux-mx35.h
- *    Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_IOMUX_MX25_H__
-#define __MACH_IOMUX_MX25_H__
-
-#include "iomux-v3.h"
-
-/*
- * IOMUX/PAD Bit field definitions
- */
-
-#define MX25_PAD_A10__A10               IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A10__GPIO_4_0          IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A13__A13               IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A13__GPIO_4_1          IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A14__A14               IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A14__GPIO_2_0          IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A15__A15               IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A15__GPIO_2_1          IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A16__A16               IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A16__GPIO_2_2          IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A17__A17               IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A17__GPIO_2_3          IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A18__A18               IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__GPIO_2_4          IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A19__A19               IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__GPIO_2_5          IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A20__A20               IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__GPIO_2_6          IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A21__A21               IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__GPIO_2_7          IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A22__A22               IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A22__GPIO_2_8          IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A23__A23               IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A23__GPIO_2_9          IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A24__A24               IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__GPIO_2_10         IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_A25__A25               IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__GPIO_2_11         IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EB0__EB0               IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__AUD4_TXD          IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__GPIO_2_12         IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EB1__EB1               IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__AUD4_RXD          IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__GPIO_2_13         IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_OE__OE                 IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__AUD4_TXC           IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__GPIO_2_14          IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS0__CS0               IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS0__GPIO_4_2          IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS1__CS1               IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__NF_CE3            IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__GPIO_4_3          IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS4__CS4               IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__NF_CE1            IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__UART5_CTS         IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__GPIO_3_20         IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CS5__CS5               IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__NF_CE2            IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NF_CE0__GPIO_3_22      IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_ECB__ECB               IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__UART5_TXD_MUX     IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__GPIO_3_23         IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LBA__LBA               IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__UART5_RXD_MUX     IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__GPIO_3_24         IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_BCLK__BCLK             IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BCLK__GPIO_4_4         IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_RW__RW                 IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__AUD4_TXFS          IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__GPIO_3_25          IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFWE_B__NFWE_B         IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWE_B__GPIO_3_26      IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFRE_B__NFRE_B         IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFRE_B__GPIO_3_27      IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFALE__NFALE           IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFALE__GPIO_3_28       IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFCLE__NFCLE           IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFCLE__GPIO_3_29       IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFWP_B__NFWP_B         IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWP_B__GPIO_3_30      IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_NFRB__NFRB             IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D12__GPIO_4_8          IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D11__D11               IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D11__GPIO_4_9          IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D10__D10               IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__GPIO_4_10         IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__USBOTG_OC         IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_D9__D9                 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__GPIO_4_11          IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__USBH2_PWR          IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
-
-#define MX25_PAD_D8__D8                 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__GPIO_4_12          IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__USBH2_OC           IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_D7__D7                 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D7__GPIO_4_13          IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D6__D6                 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D6__GPIO_4_14          IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D5__D5                 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D5__GPIO_4_15          IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D4__D4                 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D4__GPIO_4_16          IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D3__D3                 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D3__GPIO_4_17          IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D2__D2                 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D2__GPIO_4_18          IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D1__D1                 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D1__GPIO_4_19          IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_HSYNC__GPIO_1_22       IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_VSYNC__VSYNC           IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSYNC__GPIO_1_23       IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_LSCLK__LSCLK           IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LSCLK__GPIO_1_24       IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_OE_ACD__OE_ACD         IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__PWM4_PWMO    IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__GPIO_1_26         IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__USBH2_OC          IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__CSPI3_MOSI     IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__CSPI3_MISO     IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__CSPI3_SCLK     IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__CSPI3_RDY      IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D7__CSI_D7         IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D7__GPIO_1_6       IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D8__CSI_D8         IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D8__GPIO_1_7       IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_D9__CSI_D9         IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D9__GPIO_4_21      IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_MCLK__CSI_MCLK     IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_MCLK__GPIO_1_8     IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_VSYNC__CSI_VSYNC   IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_VSYNC__GPIO_1_9    IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_HSYNC__CSI_HSYNC   IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_HSYNC__GPIO_1_10   IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_PIXCLK__GPIO_1_11  IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_I2C1_CLK__I2C1_CLK     IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_CLK__GPIO_1_12    IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_I2C1_DAT__I2C1_DAT     IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_DAT__GPIO_1_13    IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MOSI__GPIO_1_14  IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MISO__GPIO_1_15  IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SS0__CSPI1_SS0   IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS0__GPIO_1_16   IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SS1__CSPI1_SS1   IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS1__GPIO_1_17   IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SCLK__GPIO_1_18  IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CSPI1_RDY__CSPI1_RDY   IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_CSPI1_RDY__GPIO_2_22   IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_UART1_RXD__GPIO_4_22   IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_TXD__GPIO_4_23   IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_RTS__CSI_D0      IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_RTS__GPIO_4_24   IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_CTS__CSI_D1      IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_CTS__GPIO_4_25   IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RXD__GPIO_4_26   IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_TXD__GPIO_4_27   IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__GPIO_4_28   IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__GPIO_4_29   IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__GPIO_2_23     IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__GPIO_2_24     IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA0__GPIO_2_25   IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA1__AUD7_RXD    IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__GPIO_2_26   IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__GPIO_2_27   IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define KPP_CTL_ROW     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define KPP_CTL_COL     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL0__AUD5_TXD     IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL1__AUD5_RXD     IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL2__UART4_RTS    IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL2__AUD5_TXC     IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL3__UART4_CTS    IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL3__AUD5_TXFS    IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__AUD4_TXD      IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__GPIO_3_5      IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_MDIO__FEC_MDIO     IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_FEC_MDIO__AUD4_RXD     IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDIO__GPIO_3_6     IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA0__GPIO_3_7   IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__AUD4_TXFS  IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__GPIO_3_8   IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TX_EN__GPIO_3_9    IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA0__GPIO_3_10  IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA1__GPIO_3_11  IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RX_DV__CAN2_RX     IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_FEC_RX_DV__GPIO_3_12   IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_FEC_TX_CLK__GPIO_3_13  IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_RTCK__RTCK             IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__OWIRE            IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__GPIO_3_14        IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_DE_B__DE_B             IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_DE_B__GPIO_2_20        IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_TDO__TDO               IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_GPIO_A__GPIO_A         IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_A__CAN1_TX        IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_A__USBOTG_PWR     IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
-
-#define MX25_PAD_GPIO_B__GPIO_B         IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_B__CAN1_RX        IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_B__USBOTG_OC      IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
-
-#define MX25_PAD_GPIO_C__GPIO_C         IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-
-#define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16           IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
-
-#define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17           IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__AUD7_TXC       IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EXT_ARMCLK__GPIO_3_15  IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_VSTBY_REQ__VSTBY_REQ   IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__AUD7_TXFS   IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__GPIO_3_17   IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__VSTBY_ACK   IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__GPIO_3_18   IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__AUD7_RXD   IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__GPIO_3_19  IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CLKO__CLKO             IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CLKO__GPIO_2_21        IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE0__GPIO_4_30  IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__GPIO_4_31  IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
-
-#define MX25_PAD_CTL_GRP_DVS_MISC       IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_FEC        IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_JTAG       IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_NFC        IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSI        IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_WEIM       IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_DDR        IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CRM        IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_KPP        IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_SDHC1      IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_LCD        IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_UART       IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_NFC        IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CSI        IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSPI1      IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DDRTYPE        IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_SDHC1      IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_LCD        IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX25_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 0a5adba61e0b..2e4a0ddca76c 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -114,7 +114,7 @@ enum iomux_gp_func {
  */
 int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
 /*
- * setups mutliple pins
+ * setups multiple pins
  * convenient way to call the above function with tables
  */
 int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index d61f9606fc56..a53b2e64f98d 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -56,9 +56,10 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
         return 0;
 }
 
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
+                unsigned count)
 {
-        iomux_v3_cfg_t *p = pad_list;
+        const iomux_v3_cfg_t *p = pad_list;
         int i;
         int ret;
 
diff --git a/arch/arm/mach-imx/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h
index 2fa3b5430102..f79e165a3b3c 100644
--- a/arch/arm/mach-imx/iomux-v3.h
+++ b/arch/arm/mach-imx/iomux-v3.h
@@ -128,10 +128,11 @@ typedef u64 iomux_v3_cfg_t;
 int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 
 /*
- * setups mutliple pads
+ * setups multiple pads
  * convenient way to call the above function with tables
  */
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
+                unsigned count);
 
 /*
  * Initialise the iomux controller
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 62a6e02f4763..922ffd6ca039 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -75,7 +75,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
         },
 };
 
-static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
+static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
         /* UART1 */
         MX35_PAD_CTS1__UART1_CTS,
         MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
deleted file mode 100644
index b2ee6e009fe4..000000000000
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
- * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx25.h"
-#include "ehci.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
-        /* FEC - RMII */
-        MX25_PAD_FEC_MDC__FEC_MDC,
-        MX25_PAD_FEC_MDIO__FEC_MDIO,
-        MX25_PAD_FEC_TDATA0__FEC_TDATA0,
-        MX25_PAD_FEC_TDATA1__FEC_TDATA1,
-        MX25_PAD_FEC_TX_EN__FEC_TX_EN,
-        MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-        MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-        MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-        /* I2C1 */
-        MX25_PAD_I2C1_CLK__I2C1_CLK,
-        MX25_PAD_I2C1_DAT__I2C1_DAT,
-};
-
-static const struct fec_platform_data mx25_fec_pdata __initconst = {
-        .phy    = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct mxc_nand_platform_data
-eukrea_cpuimx25_nand_board_info __initconst = {
-        .width          = 1,
-        .hw_ecc         = 1,
-        .flash_bbt      = 1,
-};
-
-static const struct imxi2c_platform_data
-eukrea_cpuimx25_i2c0_data __initconst = {
-        .bitrate = 100000,
-};
-
-static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        },
-};
-
-static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
-{
-        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static const struct mxc_usbh_platform_data otg_pdata __initconst = {
-        .init   = eukrea_cpuimx25_otg_init,
-        .portsc = MXC_EHCI_MODE_UTMI,
-};
-
-static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
-{
-        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
-                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
-}
-
-static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
-        .init   = eukrea_cpuimx25_usbh2_init,
-        .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI,
-        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init eukrea_cpuimx25_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = true;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = false;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 1;
-}
-__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
-
-static void __init eukrea_cpuimx25_init(void)
-{
-        imx25_soc_init();
-
-        if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
-                        ARRAY_SIZE(eukrea_cpuimx25_pads)))
-                printk(KERN_ERR "error setting cpuimx25 pads !\n");
-
-        imx25_add_imx_uart0(&uart_pdata);
-        imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
-        imx25_add_imxdi_rtc();
-        imx25_add_fec(&mx25_fec_pdata);
-        imx25_add_imx2_wdt();
-
-        i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
-                                ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
-        imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
-
-        if (otg_mode_host)
-                imx25_add_mxc_ehci_otg(&otg_pdata);
-        else
-                imx25_add_fsl_usb2_udc(&otg_device_pdata);
-
-        imx25_add_mxc_ehci_hs(&usbh2_pdata);
-
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
-        eukrea_mbimxsd25_baseboard_init();
-#endif
-}
-
-static void __init eukrea_cpuimx25_timer_init(void)
-{
-        mx25_clocks_init();
-}
-
-MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
-        /* Maintainer: Eukrea Electromatique */
-        .atag_offset = 0x100,
-        .map_io = mx25_map_io,
-        .init_early = imx25_init_early,
-        .init_irq = mx25_init_irq,
-        .init_time = eukrea_cpuimx25_timer_init,
-        .init_machine = eukrea_cpuimx25_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/mach-imx25.c
index 25defbdb06c4..9379fd0a7b4d 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/mach-imx25.c
@@ -10,12 +10,29 @@
  */
 
 #include <linux/irq.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "common.h"
-#include "mx25.h"
+#include "hardware.h"
+
+static void __init imx25_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX25);
+}
+
+static void __init mx25_init_irq(void)
+{
+        struct device_node *np;
+        void __iomem *avic_base;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,avic");
+        avic_base = of_iomap(np, 0);
+        BUG_ON(!avic_base);
+        mxc_init_irq(avic_base);
+}
 
 static const char * const imx25_dt_board_compat[] __initconst = {
         "fsl,imx25",
@@ -23,7 +40,6 @@ static const char * const imx25_dt_board_compat[] __initconst = {
 };
 
 DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
-        .map_io         = mx25_map_io,
         .init_early     = imx25_init_early,
         .init_irq       = mx25_init_irq,
         .dt_compat      = imx25_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 4ad6e473cf83..e21a693fc984 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -387,10 +387,10 @@ static void __init imx6q_map_io(void)
 
 static void __init imx6q_init_irq(void)
 {
+        imx_gpc_check_dt();
         imx_init_revision_from_anatop();
         imx_init_l2cache();
         imx_src_init();
-        imx_gpc_init();
         irqchip_init();
 }
 
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 24bfaaf944c8..12a1b098fc6a 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -61,10 +61,10 @@ static void __init imx6sl_init_machine(void)
 
 static void __init imx6sl_init_irq(void)
 {
+        imx_gpc_check_dt();
         imx_init_revision_from_anatop();
         imx_init_l2cache();
         imx_src_init();
-        imx_gpc_init();
         irqchip_init();
 }
 
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 66988eb6a3a4..f17b7004c24b 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -81,10 +81,10 @@ static void __init imx6sx_init_machine(void)
 
 static void __init imx6sx_init_irq(void)
 {
+        imx_gpc_check_dt();
         imx_init_revision_from_anatop();
         imx_init_l2cache();
         imx_src_init();
-        imx_gpc_init();
         irqchip_init();
 }
 
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
deleted file mode 100644
index 0d01e367b062..000000000000
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-/*
- * This machine is known as:
- *  - i.MX25 3-Stack Development System
- *  - i.MX25 Platform Development Kit (i.MX25 PDK)
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/usb/otg.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx25.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
-
-#define MX25PDK_CAN_PWDN        IMX_GPIO_NR(4, 6)
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static iomux_v3_cfg_t mx25pdk_pads[] = {
-        MX25_PAD_FEC_MDC__FEC_MDC,
-        MX25_PAD_FEC_MDIO__FEC_MDIO,
-        MX25_PAD_FEC_TDATA0__FEC_TDATA0,
-        MX25_PAD_FEC_TDATA1__FEC_TDATA1,
-        MX25_PAD_FEC_TX_EN__FEC_TX_EN,
-        MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-        MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-        MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-        MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
-        MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
-
-        /* LCD */
-        MX25_PAD_LD0__LD0,
-        MX25_PAD_LD1__LD1,
-        MX25_PAD_LD2__LD2,
-        MX25_PAD_LD3__LD3,
-        MX25_PAD_LD4__LD4,
-        MX25_PAD_LD5__LD5,
-        MX25_PAD_LD6__LD6,
-        MX25_PAD_LD7__LD7,
-        MX25_PAD_LD8__LD8,
-        MX25_PAD_LD9__LD9,
-        MX25_PAD_LD10__LD10,
-        MX25_PAD_LD11__LD11,
-        MX25_PAD_LD12__LD12,
-        MX25_PAD_LD13__LD13,
-        MX25_PAD_LD14__LD14,
-        MX25_PAD_LD15__LD15,
-        MX25_PAD_GPIO_E__LD16,
-        MX25_PAD_GPIO_F__LD17,
-        MX25_PAD_HSYNC__HSYNC,
-        MX25_PAD_VSYNC__VSYNC,
-        MX25_PAD_LSCLK__LSCLK,
-        MX25_PAD_OE_ACD__OE_ACD,
-        MX25_PAD_CONTRAST__CONTRAST,
-
-        /* Keypad */
-        MX25_PAD_KPP_ROW0__KPP_ROW0,
-        MX25_PAD_KPP_ROW1__KPP_ROW1,
-        MX25_PAD_KPP_ROW2__KPP_ROW2,
-        MX25_PAD_KPP_ROW3__KPP_ROW3,
-        MX25_PAD_KPP_COL0__KPP_COL0,
-        MX25_PAD_KPP_COL1__KPP_COL1,
-        MX25_PAD_KPP_COL2__KPP_COL2,
-        MX25_PAD_KPP_COL3__KPP_COL3,
-
-        /* SD1 */
-        MX25_PAD_SD1_CMD__SD1_CMD,
-        MX25_PAD_SD1_CLK__SD1_CLK,
-        MX25_PAD_SD1_DATA0__SD1_DATA0,
-        MX25_PAD_SD1_DATA1__SD1_DATA1,
-        MX25_PAD_SD1_DATA2__SD1_DATA2,
-        MX25_PAD_SD1_DATA3__SD1_DATA3,
-        MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
-        MX25_PAD_A15__GPIO_2_1, /* CardDetect */
-
-        /* I2C1 */
-        MX25_PAD_I2C1_CLK__I2C1_CLK,
-        MX25_PAD_I2C1_DAT__I2C1_DAT,
-
-        /* CAN1 */
-        MX25_PAD_GPIO_A__CAN1_TX,
-        MX25_PAD_GPIO_B__CAN1_RX,
-        MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */
-};
-
-static const struct fec_platform_data mx25_fec_pdata __initconst = {
-        .phy    = PHY_INTERFACE_MODE_RMII,
-};
-
-#define FEC_ENABLE_GPIO         IMX_GPIO_NR(2, 3)
-#define FEC_RESET_B_GPIO        IMX_GPIO_NR(4, 8)
-
-static void __init mx25pdk_fec_reset(void)
-{
-        gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
-        gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
-
-        gpio_direction_output(FEC_ENABLE_GPIO, 0);  /* drop PHY power */
-        gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
-        udelay(2);
-
-        /* turn on PHY power and lift reset */
-        gpio_set_value(FEC_ENABLE_GPIO, 1);
-        gpio_set_value(FEC_RESET_B_GPIO, 1);
-}
-
-static const struct mxc_nand_platform_data
-mx25pdk_nand_board_info __initconst = {
-        .width          = 1,
-        .hw_ecc         = 1,
-        .flash_bbt      = 1,
-};
-
-static struct imx_fb_videomode mx25pdk_modes[] = {
-        {
-                .mode   = {
-                        .name           = "CRT-VGA",
-                        .refresh        = 60,
-                        .xres           = 640,
-                        .yres           = 480,
-                        .pixclock       = 39683,
-                        .left_margin    = 45,
-                        .right_margin   = 114,
-                        .upper_margin   = 33,
-                        .lower_margin   = 11,
-                        .hsync_len      = 1,
-                        .vsync_len      = 1,
-                },
-                .bpp    = 16,
-                .pcr    = 0xFA208B80,
-        },
-};
-
-static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
-        .mode           = mx25pdk_modes,
-        .num_modes      = ARRAY_SIZE(mx25pdk_modes),
-        .pwmr           = 0x00A903FF,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00020010,
-};
-
-static const uint32_t mx25pdk_keymap[] = {
-        KEY(0, 0, KEY_UP),
-        KEY(0, 1, KEY_DOWN),
-        KEY(0, 2, KEY_VOLUMEDOWN),
-        KEY(0, 3, KEY_HOME),
-        KEY(1, 0, KEY_RIGHT),
-        KEY(1, 1, KEY_LEFT),
-        KEY(1, 2, KEY_ENTER),
-        KEY(1, 3, KEY_VOLUMEUP),
-        KEY(2, 0, KEY_F6),
-        KEY(2, 1, KEY_F8),
-        KEY(2, 2, KEY_F9),
-        KEY(2, 3, KEY_F10),
-        KEY(3, 0, KEY_F1),
-        KEY(3, 1, KEY_F2),
-        KEY(3, 2, KEY_F3),
-        KEY(3, 3, KEY_POWER),
-};
-
-static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
-        .keymap         = mx25pdk_keymap,
-        .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
-};
-
-static int mx25pdk_usbh2_init(struct platform_device *pdev)
-{
-        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-
-static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
-        .init   = mx25pdk_usbh2_init,
-        .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI,
-};
-
-static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
-        .bitrate = 100000,
-};
-
-#define SD1_GPIO_WP     IMX_GPIO_NR(2, 0)
-#define SD1_GPIO_CD     IMX_GPIO_NR(2, 1)
-
-static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
-        .wp_gpio = SD1_GPIO_WP,
-        .cd_gpio = SD1_GPIO_CD,
-        .wp_type = ESDHC_WP_GPIO,
-        .cd_type = ESDHC_CD_GPIO,
-};
-
-static void __init mx25pdk_init(void)
-{
-        imx25_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
-                        ARRAY_SIZE(mx25pdk_pads));
-
-        imx25_add_imx_uart0(&uart_pdata);
-        imx25_add_fsl_usb2_udc(&otg_device_pdata);
-        imx25_add_mxc_ehci_hs(&usbh2_pdata);
-        imx25_add_mxc_nand(&mx25pdk_nand_board_info);
-        imx25_add_imxdi_rtc();
-        imx25_add_imx_fb(&mx25pdk_fb_pdata);
-        imx25_add_imx2_wdt();
-
-        mx25pdk_fec_reset();
-        imx25_add_fec(&mx25_fec_pdata);
-        imx25_add_imx_keypad(&mx25pdk_keymap_data);
-
-        imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
-        imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
-
-        gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
-        imx25_add_flexcan0();
-}
-
-static void __init mx25pdk_timer_init(void)
-{
-        mx25_clocks_init();
-}
-
-MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
-        .map_io = mx25_map_io,
-        .init_early = imx25_init_early,
-        .init_irq = mx25_init_irq,
-        .init_time      = mx25pdk_timer_init,
-        .init_machine = mx25pdk_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 72cd77d21f63..7e315f00648d 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -166,7 +166,7 @@ static struct platform_device *devices[] __initdata = {
         &mx35pdk_flash,
 };
 
-static iomux_v3_cfg_t mx35pdk_pads[] = {
+static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = {
         /* UART1 */
         MX35_PAD_CTS1__UART1_CTS,
         MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index b623bcaca76c..e447e59c0604 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -129,7 +129,7 @@ static struct platform_device *devices[] __initdata = {
         &pcm043_flash,
 };
 
-static iomux_v3_cfg_t pcm043_pads[] = {
+static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
         /* UART1 */
         MX35_PAD_CTS1__UART1_CTS,
         MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 97836e94451c..27a8f7e3ec08 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -161,7 +161,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
         }
 };
 
-static iomux_v3_cfg_t vpr200_pads[] = {
+static const iomux_v3_cfg_t vpr200_pads[] __initconst = {
         /* UART1 */
         MX35_PAD_TXD1__UART1_TXD_MUX,
         MX35_PAD_RXD1__UART1_RXD_MUX,
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
deleted file mode 100644
index 5211f62c624e..000000000000
--- a/arch/arm/mach-imx/mm-imx25.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/pinctrl/machine.h>
-
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v3.h"
-#include "mx25.h"
-
-/*
- * This table defines static virtual address mappings for I/O regions.
- * These are the mappings common across all MX25 boards.
- */
-static struct map_desc mx25_io_desc[] __initdata = {
-        imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx25_map_io(void)
-{
-        iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
-}
-
-void __init imx25_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX25);
-        mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
-}
-
-void __init mx25_init_irq(void)
-{
-        mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
-}
-
-static struct sdma_platform_data imx25_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx25.bin",
-};
-
-static const struct resource imx25_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-void __init imx25_soc_init(void)
-{
-        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
-        mxc_device_init();
-
-        /* i.mx25 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
-        mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
-        mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
-        mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
-
-        pinctrl_provide_dummies();
-        /* i.mx25 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
-        /* i.mx25 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
-                                        ARRAY_SIZE(imx25_audmux_res));
-}
diff --git a/arch/arm/mach-imx/mx25.h b/arch/arm/mach-imx/mx25.h
deleted file mode 100644
index ec466400a200..000000000000
--- a/arch/arm/mach-imx/mx25.h
+++ /dev/null
@@ -1,117 +0,0 @@
-#ifndef __MACH_MX25_H__
-#define __MACH_MX25_H__
-
-#define MX25_AIPS1_BASE_ADDR            0x43f00000
-#define MX25_AIPS1_SIZE                 SZ_1M
-#define MX25_AIPS2_BASE_ADDR            0x53f00000
-#define MX25_AIPS2_SIZE                 SZ_1M
-#define MX25_AVIC_BASE_ADDR             0x68000000
-#define MX25_AVIC_SIZE                  SZ_1M
-
-#define MX25_I2C1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x80000)
-#define MX25_I2C3_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x84000)
-#define MX25_CAN1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x88000)
-#define MX25_CAN2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x8c000)
-#define MX25_I2C2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x98000)
-#define MX25_CSPI1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0xa4000)
-#define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
-
-#define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
-#define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
-#define MX25_GPIO4_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0x9c000)
-#define MX25_PWM2_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa0000)
-#define MX25_GPIO3_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xa4000)
-#define MX25_PWM3_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa8000)
-#define MX25_PWM4_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xc8000)
-#define MX25_GPIO1_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xcc000)
-#define MX25_GPIO2_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xd0000)
-#define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
-#define MX25_PWM1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xe0000)
-
-#define MX25_UART1_BASE_ADDR            0x43f90000
-#define MX25_UART2_BASE_ADDR            0x43f94000
-#define MX25_AUDMUX_BASE_ADDR           0x43fb0000
-#define MX25_UART3_BASE_ADDR            0x5000c000
-#define MX25_UART4_BASE_ADDR            0x50008000
-#define MX25_UART5_BASE_ADDR            0x5002c000
-
-#define MX25_CSPI3_BASE_ADDR            0x50004000
-#define MX25_CSPI2_BASE_ADDR            0x50010000
-#define MX25_FEC_BASE_ADDR              0x50038000
-#define MX25_SSI2_BASE_ADDR             0x50014000
-#define MX25_SSI1_BASE_ADDR             0x50034000
-#define MX25_NFC_BASE_ADDR              0xbb000000
-#define MX25_IIM_BASE_ADDR              0x53ff0000
-#define MX25_DRYICE_BASE_ADDR           0x53ffc000
-#define MX25_ESDHC1_BASE_ADDR           0x53fb4000
-#define MX25_ESDHC2_BASE_ADDR           0x53fb8000
-#define MX25_LCDC_BASE_ADDR             0x53fbc000
-#define MX25_KPP_BASE_ADDR              0x43fa8000
-#define MX25_SDMA_BASE_ADDR             0x53fd4000
-#define MX25_USB_BASE_ADDR              0x53ff4000
-#define MX25_USB_OTG_BASE_ADDR                  (MX25_USB_BASE_ADDR + 0x0000)
-/*
- * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
- * for the host controller.  Early documentation drafts specified 0x400 and
- * Freescale internal sources confirm only the latter value to work.
- */
-#define MX25_USB_HS_BASE_ADDR                   (MX25_USB_BASE_ADDR + 0x0400)
-#define MX25_CSI_BASE_ADDR              0x53ff8000
-
-#define MX25_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX25_IO_ADDRESS(x)              IOMEM(MX25_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX25_INT_CSPI3          (NR_IRQS_LEGACY + 0)
-#define MX25_INT_I2C1           (NR_IRQS_LEGACY + 3)
-#define MX25_INT_I2C2           (NR_IRQS_LEGACY + 4)
-#define MX25_INT_UART4          (NR_IRQS_LEGACY + 5)
-#define MX25_INT_ESDHC2         (NR_IRQS_LEGACY + 8)
-#define MX25_INT_ESDHC1         (NR_IRQS_LEGACY + 9)
-#define MX25_INT_I2C3           (NR_IRQS_LEGACY + 10)
-#define MX25_INT_SSI2           (NR_IRQS_LEGACY + 11)
-#define MX25_INT_SSI1           (NR_IRQS_LEGACY + 12)
-#define MX25_INT_CSPI2          (NR_IRQS_LEGACY + 13)
-#define MX25_INT_CSPI1          (NR_IRQS_LEGACY + 14)
-#define MX25_INT_GPIO3          (NR_IRQS_LEGACY + 16)
-#define MX25_INT_CSI            (NR_IRQS_LEGACY + 17)
-#define MX25_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX25_INT_GPIO4          (NR_IRQS_LEGACY + 23)
-#define MX25_INT_KPP            (NR_IRQS_LEGACY + 24)
-#define MX25_INT_DRYICE         (NR_IRQS_LEGACY + 25)
-#define MX25_INT_PWM1           (NR_IRQS_LEGACY + 26)
-#define MX25_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX25_INT_NFC            (NR_IRQS_LEGACY + 33)
-#define MX25_INT_SDMA           (NR_IRQS_LEGACY + 34)
-#define MX25_INT_USB_HS         (NR_IRQS_LEGACY + 35)
-#define MX25_INT_PWM2           (NR_IRQS_LEGACY + 36)
-#define MX25_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
-#define MX25_INT_LCDC           (NR_IRQS_LEGACY + 39)
-#define MX25_INT_UART5          (NR_IRQS_LEGACY + 40)
-#define MX25_INT_PWM3           (NR_IRQS_LEGACY + 41)
-#define MX25_INT_PWM4           (NR_IRQS_LEGACY + 42)
-#define MX25_INT_CAN1           (NR_IRQS_LEGACY + 43)
-#define MX25_INT_CAN2           (NR_IRQS_LEGACY + 44)
-#define MX25_INT_UART1          (NR_IRQS_LEGACY + 45)
-#define MX25_INT_GPIO2          (NR_IRQS_LEGACY + 51)
-#define MX25_INT_GPIO1          (NR_IRQS_LEGACY + 52)
-#define MX25_INT_GPT1           (NR_IRQS_LEGACY + 54)
-#define MX25_INT_FEC            (NR_IRQS_LEGACY + 57)
-
-#define MX25_DMA_REQ_SSI2_RX1   22
-#define MX25_DMA_REQ_SSI2_TX1   23
-#define MX25_DMA_REQ_SSI2_RX0   24
-#define MX25_DMA_REQ_SSI2_TX0   25
-#define MX25_DMA_REQ_SSI1_RX1   26
-#define MX25_DMA_REQ_SSI1_TX1   27
-#define MX25_DMA_REQ_SSI1_RX0   28
-#define MX25_DMA_REQ_SSI1_TX0   29
-
-#ifndef __ASSEMBLY__
-extern int mx25_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 46fd695203c7..6a7c6fc780cc 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -310,10 +310,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
          *    Low-Power mode.
          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
          *    is set (set bits 0-1 of CCM_CLPCR).
+         *
+         * Note that IRQ #32 is GIC SPI #0.
          */
-        imx_gpc_hwirq_unmask(32);
+        imx_gpc_hwirq_unmask(0);
         writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_hwirq_mask(32);
+        imx_gpc_hwirq_mask(0);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 34b4c0044961..dd94567c3628 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -71,13 +71,7 @@ static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
 
-#ifndef CONFIG_OMAP_32K_TIMER
-
-static unsigned short enable_dyn_sleep = 0;
-
-#else
-
-static unsigned short enable_dyn_sleep = 1;
+static unsigned short enable_dyn_sleep;
 
 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
                          char *buf)
@@ -90,8 +84,9 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 {
         unsigned short value;
         if (sscanf(buf, "%hu", &value) != 1 ||
-            (value != 0 && value != 1)) {
-                printk(KERN_ERR "idle_sleep_store: Invalid value\n");
+            (value != 0 && value != 1) ||
+            (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
+                pr_err("idle_sleep_store: Invalid value\n");
                 return -EINVAL;
         }
         enable_dyn_sleep = value;
@@ -101,7 +96,6 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 static struct kobj_attribute sleep_while_idle_attr =
         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
 
-#endif
 
 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 
@@ -115,16 +109,11 @@ void omap1_pm_idle(void)
 {
         extern __u32 arm_idlect1_mask;
         __u32 use_idlect1 = arm_idlect1_mask;
-        int do_sleep = 0;
 
         local_fiq_disable();
 
 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
-#warning Enable 32kHz OS timer in order to allow sleep states in idle
         use_idlect1 = use_idlect1 & ~(1 << 9);
-#else
-        if (enable_dyn_sleep)
-                do_sleep = 1;
 #endif
 
 #ifdef CONFIG_OMAP_DM_TIMER
@@ -134,10 +123,12 @@ void omap1_pm_idle(void)
         if (omap_dma_running())
                 use_idlect1 &= ~(1 << 6);
 
-        /* We should be able to remove the do_sleep variable and multiple
+        /*
+         * We should be able to remove the do_sleep variable and multiple
          * tests above as soon as drivers, timer and DMA code have been fixed.
-         * Even the sleep block count should become obsolete. */
-        if ((use_idlect1 != ~0) || !do_sleep) {
+         * Even the sleep block count should become obsolete.
+         */
+        if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
 
                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
                 if (cpu_is_omap15xx())
@@ -635,15 +626,25 @@ static const struct platform_suspend_ops omap_pm_ops = {
 
 static int __init omap_pm_init(void)
 {
-
-#ifdef CONFIG_OMAP_32K_TIMER
-        int error;
-#endif
+        int error = 0;
 
         if (!cpu_class_is_omap1())
                 return -ENODEV;
 
-        printk("Power Management for TI OMAP.\n");
+        pr_info("Power Management for TI OMAP.\n");
+
+        if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
+                pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
+
+        if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
+                pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
+
+        if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
+            IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
+                /* OMAP16xx only */
+                pr_info("OMAP1 PM: sleep states in idle enabled\n");
+                enable_dyn_sleep = 1;
+        }
 
         /*
          * We copy the assembler sleep/wakeup routines to SRAM.
@@ -693,17 +694,15 @@ static int __init omap_pm_init(void)
         omap_pm_init_debugfs();
 #endif
 
-#ifdef CONFIG_OMAP_32K_TIMER
         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
         if (error)
                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
-#endif
 
         if (cpu_is_omap16xx()) {
                 /* configure LOW_PWR pin */
                 omap_cfg_reg(T20_1610_LOW_PWR);
         }
 
-        return 0;
+        return error;
 }
 __initcall(omap_pm_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 02f5f3faac1f..f92f389890bd 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -69,6 +69,7 @@ config SOC_DRA7XX
         select ARM_GIC
         select HAVE_ARM_ARCH_TIMER
         select IRQ_CROSSBAR
+        select ARM_ERRATA_798181 if SMP
 
 config ARCH_OMAP2PLUS
         bool
@@ -279,27 +280,6 @@ config OMAP3_SDRC_AC_TIMING
           wish to say no.  Selecting yes without understanding what is
           going on could result in system crashes;
 
-config OMAP4_ERRATA_I688
-        bool "OMAP4 errata: Async Bridge Corruption"
-        depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
-        select ARCH_HAS_BARRIERS
-        help
-          If a data is stalled inside asynchronous bridge because of back
-          pressure, it may be accepted multiple times, creating pointer
-          misalignment that will corrupt next transfers on that data path
-          until next reset of the system (No recovery procedure once the
-          issue is hit, the path remains consistently broken). Async bridge
-          can be found on path between MPU to EMIF and MPU to L3 interconnect.
-          This situation can happen only when the idle is initiated by a
-          Master Request Disconnection (which is trigged by software when
-          executing WFI on CPU).
-          The work-around for this errata needs all the initiators connected
-          through async bridge must ensure that data path is properly drained
-          before issuing WFI. This condition will be met if one Strongly ordered
-          access is performed to the target right before executing the WFI.
-          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
-          IO barrier ensure that there is no synchronisation loss on initiators
-          operating on both interconnect port simultaneously.
 endmenu
 
 endif
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6124db5c37ae..a699d7169307 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,6 +23,9 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/bootmem.h>
 #include <asm/cpu.h>
 
 #include <trace/events/power.h>
@@ -72,30 +75,110 @@ struct ti_clk_features ti_clk_features;
 static bool clkdm_control = true;
 
 static LIST_HEAD(clk_hw_omap_clocks);
-void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+struct clk_iomap {
+        struct regmap *regmap;
+        void __iomem *mem;
+};
+
+static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
+
+static void clk_memmap_writel(u32 val, void __iomem *reg)
+{
+        struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        struct clk_iomap *io = clk_memmaps[r->index];
+
+        if (io->regmap)
+                regmap_write(io->regmap, r->offset, val);
+        else
+                writel_relaxed(val, io->mem + r->offset);
+}
+
+static u32 clk_memmap_readl(void __iomem *reg)
+{
+        u32 val;
+        struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        struct clk_iomap *io = clk_memmaps[r->index];
+
+        if (io->regmap)
+                regmap_read(io->regmap, r->offset, &val);
+        else
+                val = readl_relaxed(io->mem + r->offset);
+
+        return val;
+}
 
 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
 {
-        if (clk->flags & MEMMAP_ADDRESSING) {
-                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
-                writel_relaxed(val, clk_memmaps[r->index] + r->offset);
-        } else {
+        if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
                 writel_relaxed(val, reg);
-        }
+        else
+                clk_memmap_writel(val, reg);
 }
 
 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
 {
-        u32 val;
+        if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
+                return readl_relaxed(reg);
+        else
+                return clk_memmap_readl(reg);
+}
 
-        if (clk->flags & MEMMAP_ADDRESSING) {
-                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
-                val = readl_relaxed(clk_memmaps[r->index] + r->offset);
-        } else {
-                val = readl_relaxed(reg);
-        }
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
+        .clk_readl = clk_memmap_readl,
+        .clk_writel = clk_memmap_writel,
+};
 
-        return val;
+/**
+ * omap2_clk_provider_init - initialize a clock provider
+ * @match_table: DT device table to match for devices to init
+ * @np: device node pointer for the this clock provider
+ * @index: index for the clock provider
+ + @syscon: syscon regmap pointer
+ * @mem: iomem pointer for the clock provider memory area, only used if
+ *       syscon is not provided
+ *
+ * Initializes a clock provider module (CM/PRM etc.), registering
+ * the memory mapping at specified index and initializing the
+ * low level driver infrastructure. Returns 0 in success.
+ */
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+                                   struct regmap *syscon, void __iomem *mem)
+{
+        struct clk_iomap *io;
+
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+
+        io = kzalloc(sizeof(*io), GFP_KERNEL);
+
+        io->regmap = syscon;
+        io->mem = mem;
+
+        clk_memmaps[index] = io;
+
+        ti_dt_clk_init_provider(np, index);
+
+        return 0;
+}
+
+/**
+ * omap2_clk_legacy_provider_init - initialize a legacy clock provider
+ * @index: index for the clock provider
+ * @mem: iomem pointer for the clock provider memory area
+ *
+ * Initializes a legacy clock provider memory mapping.
+ */
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
+{
+        struct clk_iomap *io;
+
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+
+        io = memblock_virt_alloc(sizeof(*io), 0);
+
+        io->mem = mem;
+
+        clk_memmaps[index] = io;
 }
 
 /*
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a56742f96000..652ed0ab86ec 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
 
-extern void __iomem *clk_memmaps[];
-
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
+struct regmap;
+
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+                                   struct regmap *syscon, void __iomem *mem);
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
+
 void __init ti_clk_init_features(void);
 #endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 6222e87a79b6..1fe3e6b833d2 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
 extern int cm_register(struct cm_ll_data *cld);
 extern int cm_unregister(struct cm_ll_data *cld);
+int omap_cm_init(void);
+int omap2_cm_base_init(void);
 
 # endif
 
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ef62ac9dcd05..3e5fd3587eb1 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
         .wait_module_ready      = &omap2xxx_cm_wait_module_ready,
 };
 
-int __init omap2xxx_cm_init(void)
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
 {
         return cm_register(&omap2xxx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 83b6c597b0e1..7b8c79c0ce27 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
 extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
                                          u32 mdm);
 
-extern int __init omap2xxx_cm_init(void);
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
 
 #endif
 
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index cc5aac784278..7b181f929525 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
         .module_disable         = &am33xx_cm_module_disable,
 };
 
-int __init am33xx_cm_init(void)
+int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
 {
         return cm_register(&am33xx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 046b4b2bc9d9..a91f7d282455 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -19,6 +19,7 @@
 
 #include "cm.h"
 #include "cm-regbits-33xx.h"
+#include "prcm-common.h"
 
 /* CM base address */
 #define AM33XX_CM_BASE          0x44e00000
@@ -374,6 +375,6 @@
 
 
 #ifndef __ASSEMBLER__
-int am33xx_cm_init(void);
+int am33xx_cm_init(const struct omap_prcm_init_data *data);
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index ebead8f035f9..187fa4386718 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
         .wait_module_ready      = &omap3xxx_cm_wait_module_ready,
 };
 
-int __init omap3xxx_cm_init(void)
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
 {
+        omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
         return cm_register(&omap3xxx_cm_ll_data);
 }
 
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 734a8581c0c4..bc444e2080a1 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
 extern void omap3_cm_restore_context(void);
 extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
 
-extern int __init omap3xxx_cm_init(void);
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
 
 #endif
 
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 728d06a4af19..309a4c913448 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,7 +23,6 @@
 #define OMAP4_CM_CLKSTCTRL                              0x0000
 #define OMAP4_CM_STATICDEP                              0x0004
 
-void omap_cm_base_init(void);
-int omap4_cm_init(void);
+int omap4_cm_init(const struct omap_prcm_init_data *data);
 
 #endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8fe02fcedc48..23e8bcec34e3 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,10 +15,14 @@
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/bug.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "cm2xxx.h"
 #include "cm3xxx.h"
+#include "cm33xx.h"
 #include "cm44xx.h"
+#include "clock.h"
 
 /*
  * cm_ll_data: function pointers to SoC-specific implementations of
@@ -33,6 +37,9 @@ void __iomem *cm_base;
 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
 void __iomem *cm2_base;
 
+#define CM_NO_CLOCKS            0x1
+#define CM_SINGLE_INSTANCE      0x2
+
 /**
  * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
  * @cm: CM base virtual address
@@ -212,3 +219,152 @@ int cm_unregister(struct cm_ll_data *cld)
 
         return 0;
 }
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+        defined(CONFIG_SOC_DRA7XX)
+static struct omap_prcm_init_data cm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap4_cm_init,
+};
+
+static struct omap_prcm_init_data cm2_data __initdata = {
+        .index = TI_CLKM_CM2,
+        .init = omap4_cm_init,
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2
+static struct omap_prcm_init_data omap2_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap2xxx_cm_init,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap_prcm_init_data omap3_cm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap3xxx_cm_init,
+        .flags = CM_SINGLE_INSTANCE,
+
+        /*
+         * IVA2 offset is a negative value, must offset the cm_base address
+         * by this to get it to positive side on the iomap
+         */
+        .offset = -OMAP3430_IVA2_MOD,
+};
+#endif
+
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
+static struct omap_prcm_init_data am3_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+        .init = am33xx_cm_init,
+};
+#endif
+
+#ifdef CONFIG_SOC_AM43XX
+static struct omap_prcm_init_data am4_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+        .init = omap4_cm_init,
+};
+#endif
+
+static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
+#ifdef CONFIG_ARCH_OMAP2
+        { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        { .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+        { .compatible = "ti,omap4-cm1", .data = &cm_data },
+        { .compatible = "ti,omap4-cm2", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_OMAP5
+        { .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
+        { .compatible = "ti,omap5-cm-core", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+        { .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
+        { .compatible = "ti,dra7-cm-core", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_AM33XX
+        { .compatible = "ti,am3-prcm", .data = &am3_prcm_data },
+#endif
+#ifdef CONFIG_SOC_AM43XX
+        { .compatible = "ti,am4-prcm", .data = &am4_prcm_data },
+#endif
+#ifdef CONFIG_SOC_TI81XX
+        { .compatible = "ti,dm814-prcm", .data = &am3_prcm_data },
+        { .compatible = "ti,dm816-prcm", .data = &am3_prcm_data },
+#endif
+        { }
+};
+
+/**
+ * omap2_cm_base_init - initialize iomappings for the CM drivers
+ *
+ * Detects and initializes the iomappings for the CM driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_cm_base_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        struct omap_prcm_init_data *data;
+        void __iomem *mem;
+
+        for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
+                data = (struct omap_prcm_init_data *)match->data;
+
+                mem = of_iomap(np, 0);
+                if (!mem)
+                        return -ENOMEM;
+
+                if (data->index == TI_CLKM_CM)
+                        cm_base = mem + data->offset;
+
+                if (data->index == TI_CLKM_CM2)
+                        cm2_base = mem + data->offset;
+
+                data->mem = mem;
+
+                data->np = np;
+
+                if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
+                                   (cm_base && cm2_base)))
+                        data->init(data);
+        }
+
+        return 0;
+}
+
+/**
+ * omap_cm_init - low level init for the CM drivers
+ *
+ * Initializes the low level clock infrastructure for CM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_cm_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+
+        for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
+                data = match->data;
+
+                if (data->flags & CM_NO_CLOCKS)
+                        continue;
+
+                ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 95a8cff66aff..2c0e07ed6b99 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
  * Populates the base addresses of the _cm_bases
  * array used for read/write of cm module registers.
  */
-void omap_cm_base_init(void)
+static void omap_cm_base_init(void)
 {
         _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
         _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
@@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
         .module_disable         = &omap4_cminst_module_disable,
 };
 
-int __init omap4_cm_init(void)
+int __init omap4_cm_init(const struct omap_prcm_init_data *data)
 {
+        omap_cm_base_init();
+
         return cm_register(&omap4xxx_cm_ll_data);
 }
 
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 484cdadfb187..eae6a0e87c90 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -30,5 +30,4 @@ int __weak omap_secure_ram_reserve_memblock(void)
 void __init omap_reserve(void)
 {
         omap_secure_ram_reserve_memblock();
-        omap_barrier_reserve_memblock();
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 46e24581d624..cf3cf22ecd42 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -200,9 +200,6 @@ void __init omap4_map_io(void);
 void __init omap5_map_io(void);
 void __init ti81xx_map_io(void);
 
-/* omap_barriers_init() is OMAP4 only */
-void omap_barriers_init(void);
-
 /**
  * omap_test_timeout - busy-loop, testing a condition
  * @cond: condition to test until it evaluates to true
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index da041b4ab29c..af95a624fe71 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -14,6 +14,9 @@
 
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 
 #include "soc.h"
 #include "iomap.h"
@@ -25,13 +28,15 @@
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
+#include "clock.h"
 
 /* Used by omap3_ctrl_save_padconf() */
 #define START_PADCONF_SAVE              0x2
 #define PADCONF_SAVE_DONE               0x1
 
 static void __iomem *omap2_ctrl_base;
-static void __iomem *omap4_ctrl_pad_base;
+static s16 omap2_ctrl_offset;
+static struct regmap *omap2_ctrl_syscon;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 struct omap3_scratchpad {
@@ -133,66 +138,79 @@ struct omap3_control_regs {
 static struct omap3_control_regs control_context;
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 
-#define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
-#define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
-
-void __init omap2_set_globals_control(void __iomem *ctrl,
-                                      void __iomem *ctrl_pad)
+void __init omap2_set_globals_control(void __iomem *ctrl)
 {
         omap2_ctrl_base = ctrl;
-        omap4_ctrl_pad_base = ctrl_pad;
-}
-
-void __iomem *omap_ctrl_base_get(void)
-{
-        return omap2_ctrl_base;
 }
 
 u8 omap_ctrl_readb(u16 offset)
 {
-        return readb_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        u8 byte_offset = offset & 0x3;
+
+        val = omap_ctrl_readl(offset);
+
+        return (val >> (byte_offset * 8)) & 0xff;
 }
 
 u16 omap_ctrl_readw(u16 offset)
 {
-        return readw_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        u16 byte_offset = offset & 0x2;
+
+        val = omap_ctrl_readl(offset);
+
+        return (val >> (byte_offset * 8)) & 0xffff;
 }
 
 u32 omap_ctrl_readl(u16 offset)
 {
-        return readl_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+
+        offset &= 0xfffc;
+        if (!omap2_ctrl_syscon)
+                val = readl_relaxed(omap2_ctrl_base + offset);
+        else
+                regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+                            &val);
+
+        return val;
 }
 
 void omap_ctrl_writeb(u8 val, u16 offset)
 {
-        writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
+        u32 tmp;
+        u8 byte_offset = offset & 0x3;
+
+        tmp = omap_ctrl_readl(offset);
+
+        tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
+        tmp |= val << (byte_offset * 8);
+
+        omap_ctrl_writel(tmp, offset);
 }
 
 void omap_ctrl_writew(u16 val, u16 offset)
 {
-        writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
-}
+        u32 tmp;
+        u8 byte_offset = offset & 0x2;
 
-void omap_ctrl_writel(u32 val, u16 offset)
-{
-        writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
-}
+        tmp = omap_ctrl_readl(offset);
 
-/*
- * On OMAP4 control pad are not addressable from control
- * core base. So the common omap_ctrl_read/write APIs breaks
- * Hence export separate APIs to manage the omap4 pad control
- * registers. This APIs will work only for OMAP4
- */
+        tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
+        tmp |= val << (byte_offset * 8);
 
-u32 omap4_ctrl_pad_readl(u16 offset)
-{
-        return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
+        omap_ctrl_writel(tmp, offset);
 }
 
-void omap4_ctrl_pad_writel(u32 val, u16 offset)
+void omap_ctrl_writel(u32 val, u16 offset)
 {
-        writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
+        offset &= 0xfffc;
+        if (!omap2_ctrl_syscon)
+                writel_relaxed(val, omap2_ctrl_base + offset);
+        else
+                regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+                             val);
 }
 
 #ifdef CONFIG_ARCH_OMAP3
@@ -611,3 +629,120 @@ void __init omap3_ctrl_init(void)
         omap3_ctrl_setup_d2d_padconf();
 }
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+
+struct control_init_data {
+        int index;
+        s16 offset;
+};
+
+static struct control_init_data ctrl_data = {
+        .index = TI_CLKM_CTRL,
+};
+
+static const struct control_init_data omap2_ctrl_data = {
+        .index = TI_CLKM_CTRL,
+        .offset = -OMAP2_CONTROL_GENERAL,
+};
+
+static const struct of_device_id omap_scrm_dt_match_table[] = {
+        { .compatible = "ti,am3-scm", .data = &ctrl_data },
+        { .compatible = "ti,am4-scm", .data = &ctrl_data },
+        { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
+        { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
+        { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
+        { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
+        { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
+        { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
+        { }
+};
+
+/**
+ * omap2_control_base_init - initialize iomappings for the control driver
+ *
+ * Detects and initializes the iomappings for the control driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_control_base_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        struct control_init_data *data;
+
+        for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
+                data = (struct control_init_data *)match->data;
+
+                omap2_ctrl_base = of_iomap(np, 0);
+                if (!omap2_ctrl_base)
+                        return -ENOMEM;
+
+                omap2_ctrl_offset = data->offset;
+        }
+
+        return 0;
+}
+
+/**
+ * omap_control_init - low level init for the control driver
+ *
+ * Initializes the low level clock infrastructure for control driver.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_control_init(void)
+{
+        struct device_node *np, *scm_conf;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+        struct regmap *syscon;
+
+        for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
+                data = match->data;
+
+                /*
+                 * Check if we have scm_conf node, if yes, use this to
+                 * access clock registers.
+                 */
+                scm_conf = of_get_child_by_name(np, "scm_conf");
+
+                if (scm_conf) {
+                        syscon = syscon_node_to_regmap(scm_conf);
+
+                        if (IS_ERR(syscon))
+                                return PTR_ERR(syscon);
+
+                        omap2_ctrl_syscon = syscon;
+
+                        if (of_get_child_by_name(scm_conf, "clocks")) {
+                                ret = omap2_clk_provider_init(scm_conf,
+                                                              data->index,
+                                                              syscon, NULL);
+                                if (ret)
+                                        return ret;
+                        }
+
+                        iounmap(omap2_ctrl_base);
+                        omap2_ctrl_base = NULL;
+                } else {
+                        /* No scm_conf found, direct access */
+                        ret = omap2_clk_provider_init(np, data->index, NULL,
+                                                      omap2_ctrl_base);
+                        if (ret)
+                                return ret;
+                }
+        }
+
+        return 0;
+}
+
+/**
+ * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
+ *
+ * Legacy iomap init for clock provider. Needed only by legacy boot mode,
+ * where the base addresses are not parsed from DT, but still required
+ * by the clock driver to be setup properly.
+ */
+void __init omap3_control_legacy_iomap_init(void)
+{
+        omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
+}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8a487181210..80d2b7d8e36e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -440,15 +440,12 @@
 
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_ARCH_OMAP2PLUS
-extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
-extern u32 omap4_ctrl_pad_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
-extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
 
 extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
@@ -464,10 +461,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 void omap3_ctrl_init(void);
-extern void omap2_set_globals_control(void __iomem *ctrl,
-                                      void __iomem *ctrl_pad);
+int omap2_control_base_init(void);
+int omap_control_init(void);
+void omap2_set_globals_control(void __iomem *ctrl);
+void __init omap3_control_legacy_iomap_init(void);
 #else
-#define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
 #define omap_ctrl_readw(x)              0
 #define omap_ctrl_readl(x)              0
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 7a050f9c37ff..f492ae147c6a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -26,6 +26,8 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #include <video/omapdss.h>
 #include "omap_hwmod.h"
@@ -104,6 +106,10 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
         { "dss_hdmi", "omapdss_hdmi", -1 },
 };
 
+#define OMAP4_DSIPHY_SYSCON_OFFSET              0x78
+
+static struct regmap *omap4_dsi_mux_syscon;
+
 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
         u32 enable_mask, enable_shift;
@@ -124,7 +130,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
                 return -ENODEV;
         }
 
-        reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+        regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
 
         reg &= ~enable_mask;
         reg &= ~pipd_mask;
@@ -132,7 +138,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
         reg |= (lanes << enable_shift) & enable_mask;
         reg |= (lanes << pipd_shift) & pipd_mask;
 
-        omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+        regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
 
         return 0;
 }
@@ -665,5 +671,10 @@ int __init omapdss_init_of(void)
                 return r;
         }
 
+        /* add DSI info for omap4 */
+        node = of_find_node_by_name(NULL, "omap4_padconf_global");
+        if (node)
+                omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
+
         return 0;
 }
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2a2f4d56e4c8..f8121dbc9d48 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
 
 int omap_type(void)
 {
-        u32 val = 0;
+        static u32 val = OMAP2_DEVICETYPE_MASK;
+
+        if (val < OMAP2_DEVICETYPE_MASK)
+                return val;
 
         if (cpu_is_omap24xx()) {
                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c4871c55bd8b..820dde8b5b04 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -306,7 +306,6 @@ void __init am33xx_map_io(void)
 void __init omap4_map_io(void)
 {
         iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
-        omap_barriers_init();
 }
 #endif
 
@@ -314,7 +313,6 @@ void __init omap4_map_io(void)
 void __init omap5_map_io(void)
 {
         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
-        omap_barriers_init();
 }
 #endif
 /*
@@ -384,13 +382,9 @@ void __init omap2420_init_early(void)
         omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
                                OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
+        omap2_control_base_init();
         omap2xxx_check_revision();
-        omap2xxx_prm_init();
-        omap2xxx_cm_init();
+        omap2_prcm_base_init();
         omap2xxx_voltagedomains_init();
         omap242x_powerdomains_init();
         omap242x_clockdomains_init();
@@ -414,13 +408,9 @@ void __init omap2430_init_early(void)
         omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
                                OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
+        omap2_control_base_init();
         omap2xxx_check_revision();
-        omap2xxx_prm_init();
-        omap2xxx_cm_init();
+        omap2_prcm_base_init();
         omap2xxx_voltagedomains_init();
         omap243x_powerdomains_init();
         omap243x_clockdomains_init();
@@ -448,21 +438,30 @@ void __init omap3_init_early(void)
         omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
                                OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
+        /* XXX: remove these once OMAP3 is DT only */
+        if (!of_have_populated_dt()) {
+                omap2_set_globals_control(
+                        OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
+                omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
+                omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
+                                     NULL);
+        }
+        omap2_control_base_init();
         omap3xxx_check_revision();
         omap3xxx_check_features();
-        omap3xxx_prm_init();
-        omap3xxx_cm_init();
+        omap2_prcm_base_init();
+        /* XXX: remove these once OMAP3 is DT only */
+        if (!of_have_populated_dt()) {
+                omap3xxx_prm_init(NULL);
+                omap3xxx_cm_init(NULL);
+        }
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
         if (!of_have_populated_dt()) {
-                omap3_prcm_legacy_iomaps_init();
+                omap3_control_legacy_iomap_init();
                 if (soc_is_am35xx())
                         omap_clk_soc_init = am35xx_clk_legacy_init;
                 else if (cpu_is_omap3630())
@@ -549,14 +548,10 @@ void __init ti814x_init_early(void)
 {
         omap2_set_globals_tap(TI814X_CLASS,
                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
+        omap2_control_base_init();
         omap3xxx_check_revision();
         ti81xx_check_features();
-        am33xx_prm_init();
-        am33xx_cm_init();
+        omap2_prcm_base_init();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
         ti81xx_clockdomains_init();
@@ -570,14 +565,10 @@ void __init ti816x_init_early(void)
 {
         omap2_set_globals_tap(TI816X_CLASS,
                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
+        omap2_control_base_init();
         omap3xxx_check_revision();
         ti81xx_check_features();
-        am33xx_prm_init();
-        am33xx_cm_init();
+        omap2_prcm_base_init();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
         ti81xx_clockdomains_init();
@@ -593,14 +584,10 @@ void __init am33xx_init_early(void)
 {
         omap2_set_globals_tap(AM335X_CLASS,
                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
-                                  NULL);
-        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
-        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
+        omap2_control_base_init();
         omap3xxx_check_revision();
         am33xx_check_features();
-        am33xx_prm_init();
-        am33xx_cm_init();
+        omap2_prcm_base_init();
         am33xx_powerdomains_init();
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
@@ -619,16 +606,10 @@ void __init am43xx_init_early(void)
 {
         omap2_set_globals_tap(AM335X_CLASS,
                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
-                                  NULL);
-        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
-        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
-        omap_prm_base_init();
-        omap_cm_base_init();
+        omap2_control_base_init();
         omap3xxx_check_revision();
         am33xx_check_features();
-        omap44xx_prm_init();
-        omap4_cm_init();
+        omap2_prcm_base_init();
         am43xx_powerdomains_init();
         am43xx_clockdomains_init();
         am43xx_hwmod_init();
@@ -648,19 +629,12 @@ void __init omap4430_init_early(void)
 {
         omap2_set_globals_tap(OMAP443X_CLASS,
                               OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
-        omap_prm_base_init();
-        omap_cm_base_init();
+        omap2_control_base_init();
         omap4xxx_check_revision();
         omap4xxx_check_features();
-        omap4_cm_init();
+        omap2_prcm_base_init();
         omap4_pm_init_early();
-        omap44xx_prm_init();
         omap44xx_voltagedomains_init();
         omap44xx_powerdomains_init();
         omap44xx_clockdomains_init();
@@ -683,18 +657,11 @@ void __init omap5_init_early(void)
 {
         omap2_set_globals_tap(OMAP54XX_CLASS,
                               OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap2_control_base_init();
         omap4_pm_init_early();
-        omap_prm_base_init();
-        omap_cm_base_init();
-        omap44xx_prm_init();
+        omap2_prcm_base_init();
         omap5xxx_check_revision();
-        omap4_cm_init();
         omap54xx_voltagedomains_init();
         omap54xx_powerdomains_init();
         omap54xx_clockdomains_init();
@@ -715,18 +682,11 @@ void __init omap5_init_late(void)
 void __init dra7xx_init_early(void)
 {
         omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap2_control_base_init();
         omap4_pm_init_early();
-        omap_prm_base_init();
-        omap_cm_base_init();
-        omap44xx_prm_init();
+        omap2_prcm_base_init();
         dra7xxx_check_revision();
-        omap4_cm_init();
         dra7xx_powerdomains_init();
         dra7xx_clockdomains_init();
         dra7xx_hwmod_init();
@@ -764,7 +724,11 @@ int __init omap_clk_init(void)
         ti_clk_init_features();
 
         if (of_have_populated_dt()) {
-                ret = of_prcm_init();
+                ret = omap_control_init();
+                if (ret)
+                        return ret;
+
+                ret = omap_prcm_init();
                 if (ret)
                         return ret;
 
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 78064b0d4db5..176eef6ef338 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1053,7 +1053,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition,
                 struct omap_mux *entry;
 
 #ifdef CONFIG_OMAP_MUX
-                if (!superset->muxnames || !superset->muxnames[0]) {
+                if (!superset->muxnames[0]) {
                         superset++;
                         continue;
                 }
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index dec2b05d184b..af2851fbcdf0 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -70,13 +70,6 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
 extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
 
-#ifdef CONFIG_OMAP4_ERRATA_I688
-extern int omap_barrier_reserve_memblock(void);
-#else
-static inline void omap_barrier_reserve_memblock(void)
-{ }
-#endif
-
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 void set_cntfreq(void);
 #else
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index cee0fe1ee6ff..afaac9e25764 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -52,75 +52,6 @@ static void __iomem *twd_base;
 
 #define IRQ_LOCALTIMER          29
 
-#ifdef CONFIG_OMAP4_ERRATA_I688
-/* Used to implement memory barrier on DRAM path */
-#define OMAP4_DRAM_BARRIER_VA                   0xfe600000
-
-void __iomem *dram_sync, *sram_sync;
-
-static phys_addr_t paddr;
-static u32 size;
-
-void omap_bus_sync(void)
-{
-        if (dram_sync && sram_sync) {
-                writel_relaxed(readl_relaxed(dram_sync), dram_sync);
-                writel_relaxed(readl_relaxed(sram_sync), sram_sync);
-                isb();
-        }
-}
-EXPORT_SYMBOL(omap_bus_sync);
-
-static int __init omap4_sram_init(void)
-{
-        struct device_node *np;
-        struct gen_pool *sram_pool;
-
-        np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
-        if (!np)
-                pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
-                        __func__);
-        sram_pool = of_get_named_gen_pool(np, "sram", 0);
-        if (!sram_pool)
-                pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
-                        __func__);
-        else
-                sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
-
-        return 0;
-}
-omap_arch_initcall(omap4_sram_init);
-
-/* Steal one page physical memory for barrier implementation */
-int __init omap_barrier_reserve_memblock(void)
-{
-
-        size = ALIGN(PAGE_SIZE, SZ_1M);
-        paddr = arm_memblock_steal(size, SZ_1M);
-
-        return 0;
-}
-
-void __init omap_barriers_init(void)
-{
-        struct map_desc dram_io_desc[1];
-
-        dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
-        dram_io_desc[0].pfn = __phys_to_pfn(paddr);
-        dram_io_desc[0].length = size;
-        dram_io_desc[0].type = MT_MEMORY_RW_SO;
-        iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
-        dram_sync = (void __iomem *) dram_io_desc[0].virtual;
-
-        pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
-                (long long) paddr, dram_io_desc[0].virtual);
-
-}
-#else
-void __init omap_barriers_init(void)
-{}
-#endif
-
 void gic_dist_disable(void)
 {
         if (gic_dist_base_addr)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index fe01c5a03aa2..b1aad7e1426c 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
 
         /* Clear old wake-up events */
         /* REVISIT: These write to reserved bits? */
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
-        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+        omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
 
         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,18 +104,16 @@ no_sleep:
         clk_enable(osc_ck);
 
         /* clear CORE wake-up events */
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
 
         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
-        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
+        omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
 
         /* MPU domain wake events */
-        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
-                                    0x1);
+        omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
 
-        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
-                                    0x20);
+        omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
 
         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -143,9 +141,9 @@ static void omap2_enter_mpu_retention(void)
          * it is in retention mode. */
         if (omap2_allow_mpu_retention()) {
                 /* REVISIT: These write to reserved bits? */
-                omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-                omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
-                omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+                omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+                omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+                omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
 
                 /* Try to enter MPU retention */
                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 88721df6001d..87b98bf92366 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -137,9 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
         int c;
 
-        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
-                                        ~(OMAP3430_ST_IO_MASK |
-                                          OMAP3430_ST_IO_CHAIN_MASK));
+        c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
+                                    OMAP3430_ST_IO_CHAIN_MASK);
 
         return c ? IRQ_HANDLED : IRQ_NONE;
 }
@@ -153,14 +152,13 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
          * these are handled in a separate handler to avoid acking
          * IO events before parsing in mux code
          */
-        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
-                                        OMAP3430_ST_IO_MASK |
-                                        OMAP3430_ST_IO_CHAIN_MASK);
-        c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
-        c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
+        c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
+                                                   OMAP3430_ST_IO_CHAIN_MASK));
+        c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
+        c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
-                c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+                c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
+                c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
         }
 
         return c ? IRQ_HANDLED : IRQ_NONE;
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6163d66102a3..6ae0b3a1781e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -518,6 +518,26 @@ struct omap_prcm_irq_setup {
         .priority = _priority                           \
         }
 
+/**
+ * struct omap_prcm_init_data - PRCM driver init data
+ * @index: clock memory mapping index to be used
+ * @mem: IO mem pointer for this module
+ * @offset: module base address offset from the IO base
+ * @flags: PRCM module init flags
+ * @device_inst_offset: device instance offset within the module address space
+ * @init: low level PRCM init function for this module
+ * @np: device node for this PRCM module
+ */
+struct omap_prcm_init_data {
+        int index;
+        void __iomem *mem;
+        s16 offset;
+        u16 flags;
+        s32 device_inst_offset;
+        int (*init)(const struct omap_prcm_init_data *data);
+        struct device_node *np;
+};
+
 extern void omap_prcm_irq_cleanup(void);
 extern int omap_prcm_register_chain_handler(
         struct omap_prcm_irq_setup *irq_setup);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index b9061a6a2db8..233bc84fbc0e 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -19,8 +19,9 @@
 extern void __iomem *prm_base;
 extern u16 prm_features;
 extern void omap2_set_globals_prm(void __iomem *prm);
-int of_prcm_init(void);
-void omap3_prcm_legacy_iomaps_init(void);
+int omap_prcm_init(void);
+int omap2_prm_base_init(void);
+int omap2_prcm_base_init(void);
 # endif
 
 /*
@@ -28,9 +29,11 @@ void omap3_prcm_legacy_iomaps_init(void);
  *
  * PRM_HAS_IO_WAKEUP: has IO wakeup capability
  * PRM_HAS_VOLTAGE: has voltage domains
+ * PRM_IRQ_DEFAULT: use default irq number for PRM irq
  */
-#define PRM_HAS_IO_WAKEUP       (1 << 0)
-#define PRM_HAS_VOLTAGE         (1 << 1)
+#define PRM_HAS_IO_WAKEUP       BIT(0)
+#define PRM_HAS_VOLTAGE         BIT(1)
+#define PRM_IRQ_DEFAULT         BIT(2)
 
 /*
  * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -146,6 +149,9 @@ struct prm_ll_data {
         int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
                                      u16 offset);
         void (*reset_system)(void);
+        int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
+        u32 (*vp_check_txdone)(u8 vp_id);
+        void (*vp_clear_txdone)(u8 vp_id);
 };
 
 extern int prm_register(struct prm_ll_data *pld);
@@ -161,6 +167,19 @@ extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
 void omap_prm_reset_system(void);
 
 void omap_prm_reconfigure_io_chain(void);
+int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
+
+/*
+ * Voltage Processor (VP) identifiers
+ */
+#define OMAP3_VP_VDD_MPU_ID     0
+#define OMAP3_VP_VDD_CORE_ID    1
+#define OMAP4_VP_VDD_CORE_ID    0
+#define OMAP4_VP_VDD_IVA_ID     1
+#define OMAP4_VP_VDD_MPU_ID     2
+
+u32 omap_prm_vp_check_txdone(u8 vp_id);
+void omap_prm_vp_clear_txdone(u8 vp_id);
 
 #endif
 
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index af0f15278fc2..752018ce129c 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -123,13 +123,14 @@ static void omap2xxx_prm_dpll_reset(void)
  * Clears wakeup status bits for a given module, so that the device can
  * re-enter idle.
  */
-void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
+static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
 {
         u32 wkst;
 
         wkst = omap2_prm_read_mod_reg(module, regs);
         wkst &= wkst_mask;
         omap2_prm_write_mod_reg(wkst, module, regs);
+        return 0;
 }
 
 int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
@@ -216,9 +217,10 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
         .deassert_hardreset = &omap2_prm_deassert_hardreset,
         .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
         .reset_system = &omap2xxx_prm_dpll_reset,
+        .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
 };
 
-int __init omap2xxx_prm_init(void)
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
 {
         return prm_register(&omap2xxx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 1d51643062f7..9008a9e55a1a 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -124,9 +124,7 @@
 extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
 extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
 
-void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
-
-extern int __init omap2xxx_prm_init(void);
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
 
 #endif
 
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 02f628601b09..dcb5001d77da 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -378,7 +378,7 @@ static struct prm_ll_data am33xx_prm_ll_data = {
         .reset_system                   = am33xx_prm_global_warm_sw_reset,
 };
 
-int __init am33xx_prm_init(void)
+int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
 {
         return prm_register(&am33xx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 98ac41f271da..2bc4ec52ba78 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -118,7 +118,7 @@
 #define AM33XX_PM_CEFUSE_PWRSTST                AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
 
 #ifndef __ASSEMBLER__
-int am33xx_prm_init(void);
+int am33xx_prm_init(const struct omap_prcm_init_data *data);
 
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 5713bbdf83bc..62680aad2126 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -29,6 +29,7 @@
 #include "prm-regbits-34xx.h"
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "clock.h"
 
 static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
 static void omap3xxx_prm_ocp_barrier(void);
@@ -96,7 +97,7 @@ static struct omap3_vp omap3_vp[] = {
 
 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
 
-u32 omap3_prm_vp_check_txdone(u8 vp_id)
+static u32 omap3_prm_vp_check_txdone(u8 vp_id)
 {
         struct omap3_vp *vp = &omap3_vp[vp_id];
         u32 irqstatus;
@@ -106,7 +107,7 @@ u32 omap3_prm_vp_check_txdone(u8 vp_id)
         return irqstatus & vp->tranxdone_status;
 }
 
-void omap3_prm_vp_clear_txdone(u8 vp_id)
+static void omap3_prm_vp_clear_txdone(u8 vp_id)
 {
         struct omap3_vp *vp = &omap3_vp[vp_id];
 
@@ -217,7 +218,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
  * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
  * @module: PRM module to clear wakeups from
  * @regs: register set to clear, 1 or 3
- * @ignore_bits: wakeup status bits to ignore
+ * @wkst_mask: wkst bits to clear
  *
  * The purpose of this function is to clear any wake-up events latched
  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
@@ -226,7 +227,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
  * that any peripheral wake-up events occurring while attempting to
  * clear the PM_WKST_x are detected and cleared.
  */
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
+static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
 {
         u32 wkst, fclk, iclk, clken;
         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -238,7 +239,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 
         wkst = omap2_prm_read_mod_reg(module, wkst_off);
         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
-        wkst &= ~ignore_bits;
+        wkst &= wkst_mask;
         if (wkst) {
                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -254,7 +255,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
-                        wkst &= ~ignore_bits;
+                        wkst &= wkst_mask;
                         c++;
                 }
                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -664,10 +665,15 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
         .deassert_hardreset = &omap2_prm_deassert_hardreset,
         .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
         .reset_system = &omap3xxx_prm_dpll3_reset,
+        .clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs,
+        .vp_check_txdone = &omap3_prm_vp_check_txdone,
+        .vp_clear_txdone = &omap3_prm_vp_clear_txdone,
 };
 
-int __init omap3xxx_prm_init(void)
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
 {
+        omap2_clk_legacy_provider_init(TI_CLKM_PRM,
+                                       prm_base + OMAP3430_IVA2_MOD);
         if (omap3_has_io_wakeup())
                 prm_features |= PRM_HAS_IO_WAKEUP;
 
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ed8a3d8b739a..5f095eec339c 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -132,10 +132,6 @@
 
 #ifndef __ASSEMBLER__
 
-/* OMAP3-specific VP functions */
-u32 omap3_prm_vp_check_txdone(u8 vp_id);
-void omap3_prm_vp_clear_txdone(u8 vp_id);
-
 /*
  * OMAP3 access functions for voltage controller (VC) and
  * voltage proccessor (VP) in the PRM.
@@ -144,8 +140,7 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
-extern int __init omap3xxx_prm_init(void);
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
 void omap3xxx_prm_iva_idle(void);
 void omap3_prm_reset_modem(void);
 int omap3xxx_prm_clear_global_cold_reset(void);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a08a617a6c11..c35ad0bedf81 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -138,7 +138,7 @@ static struct omap4_vp omap4_vp[] = {
         },
 };
 
-u32 omap4_prm_vp_check_txdone(u8 vp_id)
+static u32 omap4_prm_vp_check_txdone(u8 vp_id)
 {
         struct omap4_vp *vp = &omap4_vp[vp_id];
         u32 irqstatus;
@@ -149,7 +149,7 @@ u32 omap4_prm_vp_check_txdone(u8 vp_id)
         return irqstatus & vp->tranxdone_status;
 }
 
-void omap4_prm_vp_clear_txdone(u8 vp_id)
+static void omap4_prm_vp_clear_txdone(u8 vp_id)
 {
         struct omap4_vp *vp = &omap4_vp[vp_id];
 
@@ -699,29 +699,31 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
         .deassert_hardreset     = omap4_prminst_deassert_hardreset,
         .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
         .reset_system           = omap4_prminst_global_warm_sw_reset,
+        .vp_check_txdone        = omap4_prm_vp_check_txdone,
+        .vp_clear_txdone        = omap4_prm_vp_clear_txdone,
 };
 
-int __init omap44xx_prm_init(void)
+static const struct omap_prcm_init_data *prm_init_data;
+
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
 {
-        if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
+        omap_prm_base_init();
+
+        prm_init_data = data;
+
+        if (data->flags & PRM_HAS_IO_WAKEUP)
                 prm_features |= PRM_HAS_IO_WAKEUP;
 
-        if (!soc_is_dra7xx())
+        if (data->flags & PRM_HAS_VOLTAGE)
                 prm_features |= PRM_HAS_VOLTAGE;
 
+        omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
+
         return prm_register(&omap44xx_prm_ll_data);
 }
 
-static const struct of_device_id omap_prm_dt_match_table[] = {
-        { .compatible = "ti,omap4-prm" },
-        { .compatible = "ti,omap5-prm" },
-        { .compatible = "ti,dra7-prm" },
-        { }
-};
-
 static int omap44xx_prm_late_init(void)
 {
-        struct device_node *np;
         int irq_num;
 
         if (!(prm_features & PRM_HAS_IO_WAKEUP))
@@ -731,31 +733,23 @@ static int omap44xx_prm_late_init(void)
         if (!of_have_populated_dt())
                 return 0;
 
-        np = of_find_matching_node(NULL, omap_prm_dt_match_table);
-
-        if (!np) {
-                /* Default loaded up with OMAP4 values */
-                if (!cpu_is_omap44xx())
-                        return 0;
-        } else {
-                irq_num = of_irq_get(np, 0);
-                /*
-                 * Already have OMAP4 IRQ num. For all other platforms, we need
-                 * IRQ numbers from DT
-                 */
-                if (irq_num < 0 && !cpu_is_omap44xx()) {
-                        if (irq_num == -EPROBE_DEFER)
-                                return irq_num;
-
-                        /* Have nothing to do */
-                        return 0;
-                }
-
-                /* Once OMAP4 DT is filled as well */
-                if (irq_num >= 0) {
-                        omap4_prcm_irq_setup.irq = irq_num;
-                        omap4_prcm_irq_setup.xlate_irq = NULL;
-                }
+        irq_num = of_irq_get(prm_init_data->np, 0);
+        /*
+         * Already have OMAP4 IRQ num. For all other platforms, we need
+         * IRQ numbers from DT
+         */
+        if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
+                if (irq_num == -EPROBE_DEFER)
+                        return irq_num;
+
+                /* Have nothing to do */
+                return 0;
+        }
+
+        /* Once OMAP4 DT is filled as well */
+        if (irq_num >= 0) {
+                omap4_prcm_irq_setup.irq = irq_num;
+                omap4_prcm_irq_setup.xlate_irq = NULL;
         }
 
         omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7db2422faa16..efd6035d0871 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -26,7 +26,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
 #include "prm44xx_54xx.h"
-#include "prcm-common.h"
 #include "prm.h"
 
 #define OMAP4430_PRM_BASE               0x4a306000
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 714329565b90..3f139ebc8398 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -23,13 +23,11 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
 
+#include "prcm-common.h"
+
 /* Function prototypes */
 #ifndef __ASSEMBLER__
 
-/* OMAP4/OMAP5-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-
 /*
  * OMAP4/OMAP5 access functions for voltage controller (VC) and
  * voltage proccessor (VP) in the PRM.
@@ -38,7 +36,7 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
-extern int __init omap44xx_prm_init(void);
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data);
 
 #endif
 
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index e4411010309c..1eb22ff087dc 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -22,7 +22,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
 
 #include "prm44xx_54xx.h"
-#include "prcm-common.h"
 #include "prm.h"
 
 #define OMAP54XX_PRM_BASE               0x4ae06000
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index 4bb50fbf29be..cc1e6a2b97f6 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -22,8 +22,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
 
-#include "prm44xx_54xx.h"
 #include "prcm-common.h"
+#include "prm44xx_54xx.h"
 #include "prm.h"
 
 #define DRA7XX_PRM_BASE         0x4ae06000
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index bfaa7ba595cc..7add7994dbfc 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -32,7 +32,11 @@
 #include "prm2xxx_3xxx.h"
 #include "prm2xxx.h"
 #include "prm3xxx.h"
+#include "prm33xx.h"
 #include "prm44xx.h"
+#include "prm54xx.h"
+#include "prm7xx.h"
+#include "prcm43xx.h"
 #include "common.h"
 #include "clock.h"
 #include "cm.h"
@@ -534,6 +538,61 @@ void omap_prm_reset_system(void)
 }
 
 /**
+ * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
+ * @module: PRM module to clear wakeups from
+ * @regs: register to clear
+ * @wkst_mask: wkst bits to clear
+ *
+ * Clears any wakeup events for the module and register set defined.
+ * Uses SoC specific implementation to do the actual wakeup status
+ * clearing.
+ */
+int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
+{
+        if (!prm_ll_data->clear_mod_irqs) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+
+        return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
+}
+
+/**
+ * omap_prm_vp_check_txdone - check voltage processor TX done status
+ *
+ * Checks if voltage processor transmission has been completed.
+ * Returns non-zero if a transmission has completed, 0 otherwise.
+ */
+u32 omap_prm_vp_check_txdone(u8 vp_id)
+{
+        if (!prm_ll_data->vp_check_txdone) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return 0;
+        }
+
+        return prm_ll_data->vp_check_txdone(vp_id);
+}
+
+/**
+ * omap_prm_vp_clear_txdone - clears voltage processor TX done status
+ *
+ * Clears the status bit for completed voltage processor transmission
+ * returned by prm_vp_check_txdone.
+ */
+void omap_prm_vp_clear_txdone(u8 vp_id)
+{
+        if (!prm_ll_data->vp_clear_txdone) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return;
+        }
+
+        prm_ll_data->vp_clear_txdone(vp_id);
+}
+
+/**
  * prm_register - register per-SoC low-level data with the PRM
  * @pld: low-level per-SoC OMAP PRM data & function pointers to register
  *
@@ -578,78 +637,175 @@ int prm_unregister(struct prm_ll_data *pld)
         return 0;
 }
 
-static const struct of_device_id omap_prcm_dt_match_table[] = {
-        { .compatible = "ti,am3-prcm" },
-        { .compatible = "ti,am3-scrm" },
-        { .compatible = "ti,am4-prcm" },
-        { .compatible = "ti,am4-scrm" },
-        { .compatible = "ti,dm814-prcm" },
-        { .compatible = "ti,dm814-scrm" },
-        { .compatible = "ti,dm816-prcm" },
-        { .compatible = "ti,dm816-scrm" },
-        { .compatible = "ti,omap2-prcm" },
-        { .compatible = "ti,omap2-scrm" },
-        { .compatible = "ti,omap3-prm" },
-        { .compatible = "ti,omap3-cm" },
-        { .compatible = "ti,omap3-scrm" },
-        { .compatible = "ti,omap4-cm1" },
-        { .compatible = "ti,omap4-prm" },
-        { .compatible = "ti,omap4-cm2" },
-        { .compatible = "ti,omap4-scrm" },
-        { .compatible = "ti,omap5-prm" },
-        { .compatible = "ti,omap5-cm-core-aon" },
-        { .compatible = "ti,omap5-scrm" },
-        { .compatible = "ti,omap5-cm-core" },
-        { .compatible = "ti,dra7-prm" },
-        { .compatible = "ti,dra7-cm-core-aon" },
-        { .compatible = "ti,dra7-cm-core" },
-        { }
+#ifdef CONFIG_ARCH_OMAP2
+static struct omap_prcm_init_data omap2_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap2xxx_prm_init,
 };
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap_prcm_init_data omap3_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap3xxx_prm_init,
 
-static struct clk_hw_omap memmap_dummy_ck = {
-        .flags = MEMMAP_ADDRESSING,
+        /*
+         * IVA2 offset is a negative value, must offset the prm_base
+         * address by this to get it to positive
+         */
+        .offset = -OMAP3430_IVA2_MOD,
 };
+#endif
 
-static u32 prm_clk_readl(void __iomem *reg)
-{
-        return omap2_clk_readl(&memmap_dummy_ck, reg);
-}
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
+static struct omap_prcm_init_data am3_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = am33xx_prm_init,
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+static struct omap_prcm_init_data omap4_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAP5
+static struct omap_prcm_init_data omap5_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
+};
+#endif
+
+#ifdef CONFIG_SOC_DRA7XX
+static struct omap_prcm_init_data dra7_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP,
+};
+#endif
 
-static void prm_clk_writel(u32 val, void __iomem *reg)
-{
-        omap2_clk_writel(val, &memmap_dummy_ck, reg);
-}
+#ifdef CONFIG_SOC_AM43XX
+static struct omap_prcm_init_data am4_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = AM43XX_PRM_DEVICE_INST,
+};
+#endif
 
-static struct ti_clk_ll_ops omap_clk_ll_ops = {
-        .clk_readl = prm_clk_readl,
-        .clk_writel = prm_clk_writel,
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+static struct omap_prcm_init_data scrm_data __initdata = {
+        .index = TI_CLKM_SCRM,
+};
+#endif
+
+static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
+#ifdef CONFIG_SOC_AM33XX
+        { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_SOC_AM43XX
+        { .compatible = "ti,am4-prcm", .data = &am4_prm_data },
+#endif
+#ifdef CONFIG_SOC_TI81XX
+        { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
+        { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+        { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+        { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
+        { .compatible = "ti,omap4-scrm", .data = &scrm_data },
+#endif
+#ifdef CONFIG_SOC_OMAP5
+        { .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
+        { .compatible = "ti,omap5-scrm", .data = &scrm_data },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+        { .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
+#endif
+        { }
 };
 
-int __init of_prcm_init(void)
+/**
+ * omap2_prm_base_init - initialize iomappings for the PRM driver
+ *
+ * Detects and initializes the iomappings for the PRM driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_prm_base_init(void)
 {
         struct device_node *np;
+        const struct of_device_id *match;
+        struct omap_prcm_init_data *data;
         void __iomem *mem;
-        int memmap_index = 0;
 
-        ti_clk_ll_ops = &omap_clk_ll_ops;
+        for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
+                data = (struct omap_prcm_init_data *)match->data;
 
-        for_each_matching_node(np, omap_prcm_dt_match_table) {
                 mem = of_iomap(np, 0);
-                clk_memmaps[memmap_index] = mem;
-                ti_dt_clk_init_provider(np, memmap_index);
-                memmap_index++;
+                if (!mem)
+                        return -ENOMEM;
+
+                if (data->index == TI_CLKM_PRM)
+                        prm_base = mem + data->offset;
+
+                data->mem = mem;
+
+                data->np = np;
+
+                if (data->init)
+                        data->init(data);
         }
 
         return 0;
 }
 
-void __init omap3_prcm_legacy_iomaps_init(void)
+int __init omap2_prcm_base_init(void)
 {
-        ti_clk_ll_ops = &omap_clk_ll_ops;
+        int ret;
 
-        clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
-        clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
-        clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
+        ret = omap2_prm_base_init();
+        if (ret)
+                return ret;
+
+        return omap2_cm_base_init();
+}
+
+/**
+ * omap_prcm_init - low level init for the PRCM drivers
+ *
+ * Initializes the low level clock infrastructure for PRCM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_prcm_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+
+        for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
+                data = match->data;
+
+                ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
+                if (ret)
+                        return ret;
+        }
+
+        omap_cm_init();
+
+        return 0;
 }
 
 static int __init prm_late_init(void)
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 8adf7b1a1dce..c4859c4d3646 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -47,22 +47,14 @@ void omap_prm_base_init(void)
 
 s32 omap4_prmst_get_prm_dev_inst(void)
 {
-        if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
-                return prm_dev_inst;
-
-        /* This cannot be done way early at boot.. as things are not setup */
-        if (cpu_is_omap44xx())
-                prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
-        else if (soc_is_omap54xx())
-                prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
-        else if (soc_is_dra7xx())
-                prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
-        else if (soc_is_am43xx())
-                prm_dev_inst = AM43XX_PRM_DEVICE_INST;
-
         return prm_dev_inst;
 }
 
+void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
+{
+        prm_dev_inst = dev_inst;
+}
+
 /* Read a register in a PRM instance */
 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
 {
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index fb1c9d7a2f9d..0c03d0731d7f 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -14,6 +14,7 @@
 
 #define PRM_INSTANCE_UNKNOWN    -1
 extern s32 omap4_prmst_get_prm_dev_inst(void);
+void omap4_prminst_set_prm_dev_inst(s32 dev_inst);
 
 /*
  * In an ideal world, we would not export these low-level functions,
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index b84a0122d823..ad1bb9431e94 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -333,11 +333,9 @@ ENDPROC(omap4_cpu_resume)
 
 #endif  /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
 
-#ifndef CONFIG_OMAP4_ERRATA_I688
 ENTRY(omap_bus_sync)
         ret     lr
 ENDPROC(omap_bus_sync)
-#endif
 
 ENTRY(omap_do_wfi)
         stmfd   sp!, {lr}
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 0fdf7080e4a6..7e0829682bd0 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -21,15 +21,6 @@
 
 struct voltagedomain;
 
-/*
- * Voltage Processor (VP) identifiers
- */
-#define OMAP3_VP_VDD_MPU_ID 0
-#define OMAP3_VP_VDD_CORE_ID 1
-#define OMAP4_VP_VDD_CORE_ID 0
-#define OMAP4_VP_VDD_IVA_ID 1
-#define OMAP4_VP_VDD_MPU_ID 2
-
 /* XXX document */
 #define VP_IDLE_TIMEOUT         200
 #define VP_TRANXDONE_TIMEOUT    300
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 1914e026245e..b0590fe6ab01 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -28,8 +28,8 @@
 #include "prm2xxx_3xxx.h"
 
 static const struct omap_vp_ops omap3_vp_ops = {
-        .check_txdone = omap3_prm_vp_check_txdone,
-        .clear_txdone = omap3_prm_vp_clear_txdone,
+        .check_txdone = omap_prm_vp_check_txdone,
+        .clear_txdone = omap_prm_vp_clear_txdone,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index e62f6b018beb..2448bb9a8716 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -28,8 +28,8 @@
 #include "vp.h"
 
 static const struct omap_vp_ops omap4_vp_ops = {
-        .check_txdone = omap4_prm_vp_check_txdone,
-        .clear_txdone = omap4_prm_vp_clear_txdone,
+        .check_txdone = omap_prm_vp_check_txdone,
+        .clear_txdone = omap_prm_vp_clear_txdone,
 };
 
 /*
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 27f32962e55c..4eac8dcea423 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -34,6 +34,7 @@
                         reg = <0x0 0x0>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@1 {
                         device_type = "cpu";
@@ -41,6 +42,7 @@
                         reg = <0x0 0x1>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@2 {
                         device_type = "cpu";
@@ -48,6 +50,7 @@
                         reg = <0x0 0x2>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@3 {
                         device_type = "cpu";
@@ -55,6 +58,11 @@
                         reg = <0x0 0x3>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
+                };
+
+                L2_0: l2-cache0 {
+                        compatible = "cache";
                 };
         };
 
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index d429129ecb3d..133ee59de2d7 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -39,6 +39,7 @@
                         reg = <0x0 0x0>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A57_L2>;
                 };
 
                 A57_1: cpu@1 {
@@ -46,6 +47,7 @@
                         reg = <0x0 0x1>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A57_L2>;
                 };
 
                 A53_0: cpu@100 {
@@ -53,6 +55,7 @@
                         reg = <0x0 0x100>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
                 };
 
                 A53_1: cpu@101 {
@@ -60,6 +63,7 @@
                         reg = <0x0 0x101>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
                 };
 
                 A53_2: cpu@102 {
@@ -67,6 +71,7 @@
                         reg = <0x0 0x102>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
                 };
 
                 A53_3: cpu@103 {
@@ -74,6 +79,15 @@
                         reg = <0x0 0x103>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
+                };
+
+                A57_L2: l2-cache0 {
+                        compatible = "cache";
+                };
+
+                A53_L2: l2-cache1 {
+                        compatible = "cache";
                 };
         };
 
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index efc59b3baf63..20addabbd127 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -37,6 +37,7 @@
                         reg = <0x0 0x0>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@1 {
                         device_type = "cpu";
@@ -44,6 +45,7 @@
                         reg = <0x0 0x1>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@2 {
                         device_type = "cpu";
@@ -51,6 +53,7 @@
                         reg = <0x0 0x2>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@3 {
                         device_type = "cpu";
@@ -58,6 +61,11 @@
                         reg = <0x0 0x3>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
+                };
+
+                L2_0: l2-cache0 {
+                        compatible = "cache";
                 };
         };
 
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index 5720608c50b1..abb79b3cfcfe 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -29,7 +29,7 @@ aes-ce-blk-y := aes-glue-ce.o aes-ce.o
 obj-$(CONFIG_CRYPTO_AES_ARM64_NEON_BLK) += aes-neon-blk.o
 aes-neon-blk-y := aes-glue-neon.o aes-neon.o
 
-AFLAGS_aes-ce.o         := -DINTERLEAVE=2 -DINTERLEAVE_INLINE
+AFLAGS_aes-ce.o         := -DINTERLEAVE=4
 AFLAGS_aes-neon.o       := -DINTERLEAVE=4
 
 CFLAGS_aes-glue-ce.o    := -DUSE_V8_CRYPTO_EXTENSIONS
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 5901480bfdca..750bac4e637e 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -20,6 +20,9 @@
 #error "Only include this from assembly code"
 #endif
 
+#ifndef __ASM_ASSEMBLER_H
+#define __ASM_ASSEMBLER_H
+
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 
@@ -155,3 +158,5 @@ lr	.req	x30		// link register
 #endif
         orr     \rd, \lbits, \hbits, lsl #32
         .endm
+
+#endif  /* __ASM_ASSEMBLER_H */
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
index 0710654631e7..c60643f14cda 100644
--- a/arch/arm64/include/asm/cpuidle.h
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_CPUIDLE_H
 #define __ASM_CPUIDLE_H
 
+#include <asm/proc-fns.h>
+
 #ifdef CONFIG_CPU_IDLE
 extern int cpu_init_idle(unsigned int cpu);
 extern int cpu_suspend(unsigned long arg);
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index e2ff32a93b5c..d2f49423c5dc 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -264,8 +264,10 @@ __AARCH64_INSN_FUNCS(ands,	0x7F200000, 0x6A000000)
 __AARCH64_INSN_FUNCS(bics,      0x7F200000, 0x6A200000)
 __AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
 __AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
-__AARCH64_INSN_FUNCS(cbz,       0xFE000000, 0x34000000)
-__AARCH64_INSN_FUNCS(cbnz,      0xFE000000, 0x35000000)
+__AARCH64_INSN_FUNCS(cbz,       0x7F000000, 0x34000000)
+__AARCH64_INSN_FUNCS(cbnz,      0x7F000000, 0x35000000)
+__AARCH64_INSN_FUNCS(tbz,       0x7F000000, 0x36000000)
+__AARCH64_INSN_FUNCS(tbnz,      0x7F000000, 0x37000000)
 __AARCH64_INSN_FUNCS(bcond,     0xFF000010, 0x54000000)
 __AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
 __AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 16449c535e50..800ec0e87ed9 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -460,7 +460,7 @@ static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
         const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
-                              PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
+                              PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
         return pte;
 }
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index f9be30ea1cbd..20e9591a60cf 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -45,7 +45,8 @@
 #define STACK_TOP               STACK_TOP_MAX
 #endif /* CONFIG_COMPAT */
 
-#define ARCH_LOW_ADDRESS_LIMIT  PHYS_MASK
+extern phys_addr_t arm64_dma_phys_limit;
+#define ARCH_LOW_ADDRESS_LIMIT  (arm64_dma_phys_limit - 1)
 #endif /* __KERNEL__ */
 
 struct debug_info {
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 73f0ce570fb3..4abe9b945f77 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -24,11 +24,6 @@
 #include <linux/sched.h>
 #include <asm/cputype.h>
 
-extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
-extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
-
-extern struct cpu_tlb_fns cpu_tlb;
-
 /*
  *      TLB Management
  *      ==============
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index bef04afd6031..5ee07eee80c2 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -15,8 +15,9 @@ CFLAGS_REMOVE_return_address.o = -pg
 arm64-obj-y             := cputable.o debug-monitors.o entry.o irq.o fpsimd.o   \
                            entry-fpsimd.o process.o ptrace.o setup.o signal.o   \
                            sys.o stacktrace.o time.o traps.o io.o vdso.o        \
-                           hyp-stub.o psci.o cpu_ops.o insn.o return_address.o  \
-                           cpuinfo.o cpu_errata.o alternative.o cacheinfo.o
+                           hyp-stub.o psci.o psci-call.o cpu_ops.o insn.o       \
+                           return_address.o cpuinfo.o cpu_errata.o              \
+                           alternative.o cacheinfo.o
 
 arm64-obj-$(CONFIG_COMPAT)              += sys32.o kuser32.o signal32.o         \
                                            sys_compat.o entry32.o               \
diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index cf8556ae09d0..c851be795080 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -156,7 +156,7 @@ static int ftrace_modify_graph_caller(bool enable)
 
         branch = aarch64_insn_gen_branch_imm(pc,
                                              (unsigned long)ftrace_graph_caller,
-                                             AARCH64_INSN_BRANCH_LINK);
+                                             AARCH64_INSN_BRANCH_NOLINK);
         nop = aarch64_insn_gen_nop();
 
         if (enable)
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 27d4864577e5..c8eca88f12e6 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -87,8 +87,10 @@ static void __kprobes *patch_map(void *addr, int fixmap)
 
         if (module && IS_ENABLED(CONFIG_DEBUG_SET_MODULE_RONX))
                 page = vmalloc_to_page(addr);
-        else
+        else if (!module && IS_ENABLED(CONFIG_DEBUG_RODATA))
                 page = virt_to_page(addr);
+        else
+                return addr;
 
         BUG_ON(!page);
         set_fixmap(fixmap, page_to_phys(page));
diff --git a/arch/arm64/kernel/psci-call.S b/arch/arm64/kernel/psci-call.S
new file mode 100644
index 000000000000..cf83e61cd3b5
--- /dev/null
+++ b/arch/arm64/kernel/psci-call.S
@@ -0,0 +1,28 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2015 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#include <linux/linkage.h>
+
+/* int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1, u64 arg2) */
+ENTRY(__invoke_psci_fn_hvc)
+        hvc     #0
+        ret
+ENDPROC(__invoke_psci_fn_hvc)
+
+/* int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1, u64 arg2) */
+ENTRY(__invoke_psci_fn_smc)
+        smc     #0
+        ret
+ENDPROC(__invoke_psci_fn_smc)
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index 3425f311c49e..9b8a70ae64a1 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -57,6 +57,9 @@ static struct psci_operations psci_ops;
 static int (*invoke_psci_fn)(u64, u64, u64, u64);
 typedef int (*psci_initcall_t)(const struct device_node *);
 
+asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
+asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
+
 enum psci_function {
         PSCI_FN_CPU_SUSPEND,
         PSCI_FN_CPU_ON,
@@ -109,40 +112,6 @@ static void psci_power_state_unpack(u32 power_state,
                         PSCI_0_2_POWER_STATE_AFFL_SHIFT;
 }
 
-/*
- * The following two functions are invoked via the invoke_psci_fn pointer
- * and will not be inlined, allowing us to piggyback on the AAPCS.
- */
-static noinline int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1,
-                                         u64 arg2)
-{
-        asm volatile(
-                        __asmeq("%0", "x0")
-                        __asmeq("%1", "x1")
-                        __asmeq("%2", "x2")
-                        __asmeq("%3", "x3")
-                        "hvc    #0\n"
-                : "+r" (function_id)
-                : "r" (arg0), "r" (arg1), "r" (arg2));
-
-        return function_id;
-}
-
-static noinline int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
-                                         u64 arg2)
-{
-        asm volatile(
-                        __asmeq("%0", "x0")
-                        __asmeq("%1", "x1")
-                        __asmeq("%2", "x2")
-                        __asmeq("%3", "x3")
-                        "smc    #0\n"
-                : "+r" (function_id)
-                : "r" (arg0), "r" (arg1), "r" (arg2));
-
-        return function_id;
-}
-
 static int psci_get_version(void)
 {
         int err;
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
index c20a300e2213..d26fcd4cd6e6 100644
--- a/arch/arm64/kernel/signal32.c
+++ b/arch/arm64/kernel/signal32.c
@@ -154,8 +154,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
         case __SI_TIMER:
                  err |= __put_user(from->si_tid, &to->si_tid);
                  err |= __put_user(from->si_overrun, &to->si_overrun);
-                 err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr,
-                                   &to->si_ptr);
+                 err |= __put_user(from->si_int, &to->si_int);
                 break;
         case __SI_POLL:
                 err |= __put_user(from->si_band, &to->si_band);
@@ -184,7 +183,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
         case __SI_MESGQ: /* But this is */
                 err |= __put_user(from->si_pid, &to->si_pid);
                 err |= __put_user(from->si_uid, &to->si_uid);
-                err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr, &to->si_ptr);
+                err |= __put_user(from->si_int, &to->si_int);
                 break;
         case __SI_SYS:
                 err |= __put_user((compat_uptr_t)(unsigned long)
diff --git a/arch/arm64/kernel/vdso/gettimeofday.S b/arch/arm64/kernel/vdso/gettimeofday.S
index fe652ffd34c2..efa79e8d4196 100644
--- a/arch/arm64/kernel/vdso/gettimeofday.S
+++ b/arch/arm64/kernel/vdso/gettimeofday.S
@@ -174,8 +174,6 @@ ENDPROC(__kernel_clock_gettime)
 /* int __kernel_clock_getres(clockid_t clock_id, struct timespec *res); */
 ENTRY(__kernel_clock_getres)
         .cfi_startproc
-        cbz     w1, 3f
-
         cmp     w0, #CLOCK_REALTIME
         ccmp    w0, #CLOCK_MONOTONIC, #0x4, ne
         b.ne    1f
@@ -188,6 +186,7 @@ ENTRY(__kernel_clock_getres)
         b.ne    4f
         ldr     x2, 6f
 2:
+        cbz     w1, 3f
         stp     xzr, x2, [x1]
 
 3:      /* res == NULL. */
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 0a24b9b8c698..58e0c2bdde04 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -348,8 +348,6 @@ static struct dma_map_ops swiotlb_dma_ops = {
         .mapping_error = swiotlb_dma_mapping_error,
 };
 
-extern int swiotlb_late_init_with_default_size(size_t default_size);
-
 static int __init atomic_pool_init(void)
 {
         pgprot_t prot = __pgprot(PROT_NORMAL_NC);
@@ -411,21 +409,13 @@ out:
         return -ENOMEM;
 }
 
-static int __init swiotlb_late_init(void)
+static int __init arm64_dma_init(void)
 {
-        size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT);
+        int ret;
 
         dma_ops = &swiotlb_dma_ops;
 
-        return swiotlb_late_init_with_default_size(swiotlb_size);
-}
-
-static int __init arm64_dma_init(void)
-{
-        int ret = 0;
-
-        ret |= swiotlb_late_init();
-        ret |= atomic_pool_init();
+        ret = atomic_pool_init();
 
         return ret;
 }
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 71145f952070..ae85da6307bb 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -33,6 +33,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dma-contiguous.h>
 #include <linux/efi.h>
+#include <linux/swiotlb.h>
 
 #include <asm/fixmap.h>
 #include <asm/memory.h>
@@ -45,6 +46,7 @@
 #include "mm.h"
 
 phys_addr_t memstart_addr __read_mostly = 0;
+phys_addr_t arm64_dma_phys_limit __read_mostly;
 
 #ifdef CONFIG_BLK_DEV_INITRD
 static int __init early_initrd(char *p)
@@ -85,7 +87,7 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
 
         /* 4GB maximum for 32-bit only capable devices */
         if (IS_ENABLED(CONFIG_ZONE_DMA)) {
-                max_dma = PFN_DOWN(max_zone_dma_phys());
+                max_dma = PFN_DOWN(arm64_dma_phys_limit);
                 zone_size[ZONE_DMA] = max_dma - min;
         }
         zone_size[ZONE_NORMAL] = max - max_dma;
@@ -156,8 +158,6 @@ early_param("mem", early_mem);
 
 void __init arm64_memblock_init(void)
 {
-        phys_addr_t dma_phys_limit = 0;
-
         memblock_enforce_memory_limit(memory_limit);
 
         /*
@@ -174,8 +174,10 @@ void __init arm64_memblock_init(void)
 
         /* 4GB maximum for 32-bit only capable devices */
         if (IS_ENABLED(CONFIG_ZONE_DMA))
-                dma_phys_limit = max_zone_dma_phys();
-        dma_contiguous_reserve(dma_phys_limit);
+                arm64_dma_phys_limit = max_zone_dma_phys();
+        else
+                arm64_dma_phys_limit = PHYS_MASK + 1;
+        dma_contiguous_reserve(arm64_dma_phys_limit);
 
         memblock_allow_resize();
         memblock_dump_all();
@@ -276,6 +278,8 @@ static void __init free_unused_memmap(void)
  */
 void __init mem_init(void)
 {
+        swiotlb_init(1);
+
         set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
 
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h
index 93bcf2abd1a1..07d7a7ef8bd5 100644
--- a/arch/frv/include/asm/pgtable.h
+++ b/arch/frv/include/asm/pgtable.h
@@ -123,12 +123,14 @@ extern unsigned long empty_zero_page;
 #define PGDIR_MASK              (~(PGDIR_SIZE - 1))
 #define PTRS_PER_PGD            64
 
+#define __PAGETABLE_PUD_FOLDED
 #define PUD_SHIFT               26
 #define PTRS_PER_PUD            1
 #define PUD_SIZE                (1UL << PUD_SHIFT)
 #define PUD_MASK                (~(PUD_SIZE - 1))
 #define PUE_SIZE                256
 
+#define __PAGETABLE_PMD_FOLDED
 #define PMD_SHIFT               26
 #define PMD_SIZE                (1UL << PMD_SHIFT)
 #define PMD_MASK                (~(PMD_SIZE - 1))
diff --git a/arch/m32r/include/asm/pgtable-2level.h b/arch/m32r/include/asm/pgtable-2level.h
index 8fd8ee70266a..421e6ba3a173 100644
--- a/arch/m32r/include/asm/pgtable-2level.h
+++ b/arch/m32r/include/asm/pgtable-2level.h
@@ -13,6 +13,7 @@
  * the M32R is two-level, so we don't really have any
  * PMD directory physically.
  */
+#define __PAGETABLE_PMD_FOLDED
 #define PMD_SHIFT       22
 #define PTRS_PER_PMD    1
 
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
index 28a145bfbb71..35ed4a9981ae 100644
--- a/arch/m68k/include/asm/pgtable_mm.h
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -54,10 +54,12 @@
  */
 #ifdef CONFIG_SUN3
 #define PTRS_PER_PTE   16
+#define __PAGETABLE_PMD_FOLDED
 #define PTRS_PER_PMD   1
 #define PTRS_PER_PGD   2048
 #elif defined(CONFIG_COLDFIRE)
 #define PTRS_PER_PTE    512
+#define __PAGETABLE_PMD_FOLDED
 #define PTRS_PER_PMD    1
 #define PTRS_PER_PGD    1024
 #else
diff --git a/arch/metag/include/asm/processor.h b/arch/metag/include/asm/processor.h
index 881071c07942..13272fd5a5ba 100644
--- a/arch/metag/include/asm/processor.h
+++ b/arch/metag/include/asm/processor.h
@@ -149,8 +149,8 @@ extern void exit_thread(void);
 
 unsigned long get_wchan(struct task_struct *p);
 
-#define KSTK_EIP(tsk)   ((tsk)->thread.kernel_context->CurrPC)
-#define KSTK_ESP(tsk)   ((tsk)->thread.kernel_context->AX[0].U0)
+#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->ctx.CurrPC)
+#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->ctx.AX[0].U0)
 
 #define user_stack_pointer(regs)        ((regs)->ctx.AX[0].U0)
 
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
index afab728ab65e..96d3f9deb59c 100644
--- a/arch/mn10300/include/asm/pgtable.h
+++ b/arch/mn10300/include/asm/pgtable.h
@@ -56,7 +56,9 @@ extern void paging_init(void);
 #define PGDIR_SHIFT     22
 #define PTRS_PER_PGD    1024
 #define PTRS_PER_PUD    1       /* we don't really have any PUD physically */
+#define __PAGETABLE_PUD_FOLDED
 #define PTRS_PER_PMD    1       /* we don't really have any PMD physically */
+#define __PAGETABLE_PMD_FOLDED
 #define PTRS_PER_PTE    1024
 
 #define PGD_SIZE        PAGE_SIZE
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index 8c966b2270aa..15207b9362bf 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -96,6 +96,7 @@ extern void purge_tlb_entries(struct mm_struct *, unsigned long);
 #if PT_NLEVELS == 3
 #define BITS_PER_PMD    (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
 #else
+#define __PAGETABLE_PMD_FOLDED
 #define BITS_PER_PMD    0
 #endif
 #define PTRS_PER_PMD    (1UL << BITS_PER_PMD)
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index fbb5ee3ae57c..e08ec38f8c6e 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -91,7 +91,9 @@ extern unsigned long zero_page_mask;
  */
 #define PTRS_PER_PTE    256
 #ifndef CONFIG_64BIT
+#define __PAGETABLE_PUD_FOLDED
 #define PTRS_PER_PMD    1
+#define __PAGETABLE_PMD_FOLDED
 #define PTRS_PER_PUD    1
 #else /* CONFIG_64BIT */
 #define PTRS_PER_PMD    2048
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index b5c8ff5e9dfc..2346c95c6ab1 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1396,6 +1396,12 @@ void cpu_init(void)
 
         wait_for_master_cpu(cpu);
 
+        /*
+         * Initialize the CR4 shadow before doing anything that could
+         * try to read it.
+         */
+        cr4_init_shadow();
+
         show_ucode_info_early();
 
         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 94d7dcb12145..50163fa9034f 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -565,8 +565,8 @@ static const struct _tlb_table intel_tlb_table[] = {
         { 0xb2, TLB_INST_4K,            64,     " TLB_INST 4KByte pages, 4-way set associative" },
         { 0xb3, TLB_DATA_4K,            128,    " TLB_DATA 4 KByte pages, 4-way set associative" },
         { 0xb4, TLB_DATA_4K,            256,    " TLB_DATA 4 KByte pages, 4-way associative" },
-        { 0xb5, TLB_INST_4K,            64,     " TLB_INST 4 KByte pages, 8-way set ssociative" },
-        { 0xb6, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 8-way set ssociative" },
+        { 0xb5, TLB_INST_4K,            64,     " TLB_INST 4 KByte pages, 8-way set associative" },
+        { 0xb6, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 8-way set associative" },
         { 0xba, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way associative" },
         { 0xc0, TLB_DATA_4K_4M,         8,      " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
         { 0xc1, STLB_4K_2M,             1024,   " STLB 4 KByte and 2 MByte pages, 8-way associative" },
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index 000d4199b03e..31e2d5bf3e38 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -982,6 +982,9 @@ ENTRY(xen_hypervisor_callback)
 ENTRY(xen_do_upcall)
 1:      mov %esp, %eax
         call xen_evtchn_do_upcall
+#ifndef CONFIG_PREEMPT
+        call xen_maybe_preempt_hcall
+#endif
         jmp  ret_from_intr
         CFI_ENDPROC
 ENDPROC(xen_hypervisor_callback)
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index db13655c3a2a..10074ad9ebf8 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1208,6 +1208,9 @@ ENTRY(xen_do_hypervisor_callback)   # do_hypervisor_callback(struct *pt_regs)
         popq %rsp
         CFI_DEF_CFA_REGISTER rsp
         decl PER_CPU_VAR(irq_count)
+#ifndef CONFIG_PREEMPT
+        call xen_maybe_preempt_hcall
+#endif
         jmp  error_exit
         CFI_ENDPROC
 END(xen_do_hypervisor_callback)
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index 6a1146ea4d4d..4e3d5a9621fe 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -223,27 +223,48 @@ static unsigned long
 __recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr)
 {
         struct kprobe *kp;
+        unsigned long faddr;
 
         kp = get_kprobe((void *)addr);
-        /* There is no probe, return original address */
-        if (!kp)
+        faddr = ftrace_location(addr);
+        /*
+         * Addresses inside the ftrace location are refused by
+         * arch_check_ftrace_location(). Something went terribly wrong
+         * if such an address is checked here.
+         */
+        if (WARN_ON(faddr && faddr != addr))
+                return 0UL;
+        /*
+         * Use the current code if it is not modified by Kprobe
+         * and it cannot be modified by ftrace.
+         */
+        if (!kp && !faddr)
                 return addr;
 
         /*
-         *  Basically, kp->ainsn.insn has an original instruction.
-         *  However, RIP-relative instruction can not do single-stepping
-         *  at different place, __copy_instruction() tweaks the displacement of
-         *  that instruction. In that case, we can't recover the instruction
-         *  from the kp->ainsn.insn.
+         * Basically, kp->ainsn.insn has an original instruction.
+         * However, RIP-relative instruction can not do single-stepping
+         * at different place, __copy_instruction() tweaks the displacement of
+         * that instruction. In that case, we can't recover the instruction
+         * from the kp->ainsn.insn.
          *
-         *  On the other hand, kp->opcode has a copy of the first byte of
-         *  the probed instruction, which is overwritten by int3. And
-         *  the instruction at kp->addr is not modified by kprobes except
-         *  for the first byte, we can recover the original instruction
-         *  from it and kp->opcode.
+         * On the other hand, in case on normal Kprobe, kp->opcode has a copy
+         * of the first byte of the probed instruction, which is overwritten
+         * by int3. And the instruction at kp->addr is not modified by kprobes
+         * except for the first byte, we can recover the original instruction
+         * from it and kp->opcode.
+         *
+         * In case of Kprobes using ftrace, we do not have a copy of
+         * the original instruction. In fact, the ftrace location might
+         * be modified at anytime and even could be in an inconsistent state.
+         * Fortunately, we know that the original code is the ideal 5-byte
+         * long NOP.
          */
-        memcpy(buf, kp->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
-        buf[0] = kp->opcode;
+        memcpy(buf, (void *)addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
+        if (faddr)
+                memcpy(buf, ideal_nops[NOP_ATOMIC5], 5);
+        else
+                buf[0] = kp->opcode;
         return (unsigned long)buf;
 }
 
@@ -251,6 +272,7 @@ __recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr)
  * Recover the probed instruction at addr for further analysis.
  * Caller must lock kprobes by kprobe_mutex, or disable preemption
  * for preventing to release referencing kprobes.
+ * Returns zero if the instruction can not get recovered.
  */
 unsigned long recover_probed_instruction(kprobe_opcode_t *buf, unsigned long addr)
 {
@@ -285,6 +307,8 @@ static int can_probe(unsigned long paddr)
                  * normally used, we just go through if there is no kprobe.
                  */
                 __addr = recover_probed_instruction(buf, addr);
+                if (!__addr)
+                        return 0;
                 kernel_insn_init(&insn, (void *)__addr, MAX_INSN_SIZE);
                 insn_get_length(&insn);
 
@@ -333,6 +357,8 @@ int __copy_instruction(u8 *dest, u8 *src)
         unsigned long recovered_insn =
                 recover_probed_instruction(buf, (unsigned long)src);
 
+        if (!recovered_insn)
+                return 0;
         kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
         insn_get_length(&insn);
         /* Another subsystem puts a breakpoint, failed to recover */
diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c
index 0dd8d089c315..7b3b9d15c47a 100644
--- a/arch/x86/kernel/kprobes/opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -259,6 +259,8 @@ static int can_optimize(unsigned long paddr)
                          */
                         return 0;
                 recovered_insn = recover_probed_instruction(buf, addr);
+                if (!recovered_insn)
+                        return 0;
                 kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
                 insn_get_length(&insn);
                 /* Another subsystem puts a breakpoint */
diff --git a/arch/x86/lguest/Kconfig b/arch/x86/lguest/Kconfig
index 4a0890f815c4..08f41caada45 100644
--- a/arch/x86/lguest/Kconfig
+++ b/arch/x86/lguest/Kconfig
@@ -1,6 +1,6 @@
 config LGUEST_GUEST
         bool "Lguest guest support"
-        depends on X86_32 && PARAVIRT
+        depends on X86_32 && PARAVIRT && PCI
         select TTY
         select VIRTUALIZATION
         select VIRTIO
@@ -8,7 +8,7 @@ config LGUEST_GUEST
         help
           Lguest is a tiny in-kernel hypervisor.  Selecting this will
           allow your kernel to boot under lguest.  This option will increase
-          your kernel size by about 6k.  If in doubt, say N.
+          your kernel size by about 10k.  If in doubt, say N.
 
           If you say Y here, make sure you say Y (or M) to the virtio block
           and net drivers which lguest needs.
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 1bbedc4b0f88..3005f0c89f2e 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -130,7 +130,7 @@ static void intel_mid_arch_setup(void)
                 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
         else {
                 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
-                pr_info("ARCH: Uknown SoC, assuming PENWELL!\n");
+                pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
         }
 
 out:
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index bd8b8459c3d0..5240f563076d 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1070,6 +1070,23 @@ static inline void xen_write_cr8(unsigned long val)
         BUG_ON(val);
 }
 #endif
+
+static u64 xen_read_msr_safe(unsigned int msr, int *err)
+{
+        u64 val;
+
+        val = native_read_msr_safe(msr, err);
+        switch (msr) {
+        case MSR_IA32_APICBASE:
+#ifdef CONFIG_X86_X2APIC
+                if (!(cpuid_ecx(1) & (1 << (X86_FEATURE_X2APIC & 31))))
+#endif
+                        val &= ~X2APIC_ENABLE;
+                break;
+        }
+        return val;
+}
+
 static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
 {
         int ret;
@@ -1240,7 +1257,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
 
         .wbinvd = native_wbinvd,
 
-        .read_msr = native_read_msr_safe,
+        .read_msr = xen_read_msr_safe,
         .write_msr = xen_write_msr_safe,
 
         .read_tsc = native_read_tsc,
@@ -1741,6 +1758,7 @@ asmlinkage __visible void __init xen_start_kernel(void)
 #ifdef CONFIG_X86_32
         i386_start_kernel();
 #else
+        cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */
         x86_64_start_reservations((char *)__pa_symbol(&boot_params));
 #endif
 }